CN105487315A - Tft阵列基板 - Google Patents

Tft阵列基板 Download PDF

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CN105487315A
CN105487315A CN201610035497.XA CN201610035497A CN105487315A CN 105487315 A CN105487315 A CN 105487315A CN 201610035497 A CN201610035497 A CN 201610035497A CN 105487315 A CN105487315 A CN 105487315A
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electrode
drain electrode
array substrate
memory capacitance
public electrode
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刘元甫
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/137,003 priority patent/US9716116B1/en
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Abstract

本发明提供一种TFT阵列基板，通过增大位于遮光区的TFT(900)的漏极(420)的面积，使得所述漏极(420)与部分公共电极(600)的水平投影重叠，漏极(420)与公共电极(600)构成第一存储电容(Cst1)，像素电极(800)与公共电极(600)构成第二存储电容(Cst2)，由于像素电极(800)与漏极(420)相接触形成电性连接，二者等电位，第一存储电容(Cst1)与第二存储电容(Cst2)并联构成存储电容，该存储电容的容量等于第一存储电容(Cst1)和第二存储电容(Cst2)的容量之和，能够在不降低开口率的前提下增加存储电容的容量，改善交叉串扰、影像残留等问题，提升产品的显示质量。

Description

TFT阵列基板
技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板。
背景技术
液晶显示器(LiquidCrystalDisplay，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlightmodule)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(ThinFilmTransistorArraySubstrate，TFTArraySubstrate)与彩色滤光片基板(ColorFilter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
TFT阵列基板包括多条栅极线和数据线，相互垂直的多条栅极线和多条数据线形成了多个像素单元，且每个像素单元内均设置有TFT、像素电极及存储电容等。TFT包括一栅极连接至栅极线，源极连接至数据线，漏极连接至像素电极。当栅极线被驱动时，TFT处于导通状态，对应的数据线送入灰阶电压信号并将其加载至像素电极，从而使得像素电极与公共电极之间产生相应的电场，液晶层中的液晶分子则在电场的作用下发生取向变化，以实现不同的图像显示。
存储电容在TFT阵列基板中起到保持电位等重要作用，现有的TFT阵列基板通常通过公共电极与像素电极的重叠部分来构成存储电容。请参阅图1至图3，现有的TFT阵列基板通常包括：衬底基板10、设于所述衬底基板10上的缓冲层20、设于所述缓冲层20上的数个呈阵列式排布的TFT90、覆盖所述TFT90的平坦层50、设于所述平坦层50上的公共电极60、覆盖所述公共电极60的保护层70、及设于所述保护层70上的图案化的像素电极80。所述像素电极80与部分公共电极60重叠构成存储电容Cst。所述像素电极80接触TFT90的漏极901，TFT90的漏极901又接触TFT90的多晶硅半导体层902。针对该现有的TFT阵列基板，TFT90的漏极901的面积很小，仅用于电性连接像素电极80、及多晶硅半导体层902，所述漏极901与公共电极60无重叠。
随着显示技术的不断发展，高品质显示面板的解析度和分辨率越来越高，显示面板的开口率随之变小，同时存储电容也在逐渐变小，每个像素的充电时间逐渐减少，存储电容的电量将不能维持像素的正常工作电压，引起诸如交叉串扰(Crosstalk)，影像残留(ImageSticking)等缺陷。因此，如何提升高品质显示面板的存储电容的容量成为了亟待解决的问题。如图1和图2所示的现有的TFT阵列基板受限于工艺能力、光学品味及穿透率的需求，图案化的像素电极80的面积很难做出改变，也就不能通过增大像素电极80的面积这种方式来增大存储电容的容量。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够在不降低开口率的前提下，增加存储电容的容量，改善交叉串扰、影像残留等问题，提升产品的显示质量。
为实现上述目的，本发明提供了一种TFT阵列基板，包括：衬底基板、设于所述衬底基板上的缓冲层、设于所述缓冲层上的数个呈阵列式排布的TFT、设于所述TFT上的平坦层、设于所述平坦层上的公共电极、设于所述公共电极上的保护层、及设于所述保护层上的图案化的像素电极；
所述TFT包括：设于所述缓冲层上的多晶硅半导体层、覆盖所述多晶硅半导体层的栅极绝缘层、于所述多晶硅半导体层上方设于所述栅极绝缘层上的栅极、覆盖所述栅极与栅极绝缘层的层间绝缘层、及设于所述层间绝缘层上的源极与漏极；
所述像素电极与所述漏极电性连接；
所述漏极与部分公共电极的水平投影重叠；
所述漏极与所述公共电极构成第一存储电容，所述像素电极与公共电极构成第二存储电容，所述第一存储电容与第二存储电容并联构成存储电容。
位于所述漏极与部分公共电极的水平投影重叠的区域内的平坦层的厚度小于位于所述漏极与部分公共电极的水平投影重叠的区域外的平坦层的厚度。
位于所述漏极与部分公共电极的水平投影重叠的区域内的平坦层的厚度为0.5μm～1μm，位于所述漏极与部分公共电极的水平投影重叠的区域外的平坦层的厚度为1.5μm～3μm。
所述像素电极通过贯穿所述保护层、公共电极、及平坦层的过孔与所述漏极相接触形成电性连接。
所述TFT阵列基板还包括：多条沿第一方向平行间隔设置的栅极扫描线、及多条沿与第一方向垂直的第二方向平行间隔设置的数据线；
所述数据线、和源极、及所述漏极位于同一层，且数据线与源极电性连接；所述栅极扫描线与栅极位于同一层且电性连接。
所述源极和漏极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与多晶硅半导体层的两端相接触形成电性连接。
所述像素电极与公共电极的材料均为ITO。
所述缓冲层、栅极绝缘层、层间绝缘层、平坦层、及保护层的材料均为氮化硅、氧化硅中的一种或两种的复合。
所述栅极扫描线、数据线、栅极、源极、及漏极的材料均为钼、钛、铜、铝中的一种或多种的堆栈组合。
本发明的有益效果：本发明提供的一种TFT阵列基板通过增大位于遮光区的TFT的漏极的面积，使得所述漏极与部分公共电极的水平投影重叠，漏极与公共电极构成第一存储电容，像素电极与公共电极构成第二存储电容，由于像素电极与漏极相接触形成电性连接，二者等电位，第一存储电容与第二存储电容并联构成存储电容，该存储电容的容量等于第一存储电容和第二存储电容的容量之和，相比于现有技术，能够在不降低开口率的前提下增加存储电容的容量，改善交叉串扰、影像残留等问题，提升产品的显示质量。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的TFT阵列基板的俯视图；
图2为图1所示TFT阵列基板在A-A处的剖面展开示意图；
图3为图1所示TFT阵列基板中存储电容的等效电路示意图；
图4为本发明的TFT阵列基板的俯视图；
图5为图4所示的TFT阵列基板在B-B处的第一实施例的剖面展开示意图；
图6为图4所示的TFT阵列基板在B-B处的第二实施例的剖面展开示意图；
图7为本发明的TFT阵列基板中存储电容的等效电路示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4并结合图5或图6，本发明提供一种TFT阵列基板，包括：衬底基板100、设于所述衬底基板100上的缓冲层110、设于所述缓冲层110上的数个呈阵列式排布的TFT900、设于所述TFT900上的平坦层500、设于所述平坦层500上的公共电极600、设于所述公共电极600上的保护层700、及设于所述保护层700上的图案化的像素电极800。
所述TFT900包括：设于所述缓冲层110上的多晶硅半导体层200、覆盖所述多晶硅半导体层200的栅极绝缘层310、于所述多晶硅半导体层200上方设于所述栅极绝缘层310上的栅极410、覆盖所述栅极410与栅极绝缘层310的层间绝缘层320、及设于所述层间绝缘层320上的源极(未图示)与漏极420。
所述像素电极800与所述漏极420电性连接。所述漏极420与现有技术中的漏极相比，在遮光区范围内增大面积，使其与部分公共电极600的水平投影重叠。
如图5与图7、或图6与图7所示，所述漏极420与所述公共电极600构成第一存储电容Cst1，所述像素电极800与公共电极600构成第二电容Cst2，由于像素电极800与漏极420电性连接，二者等电位，所述第一存储电容Cst1与第二存储电容Cst2并联构成存储电容Cst。
具体地，请参阅图4与图5，在本发明的TFT阵列基板的第一实施例中，所述平坦层500各处的厚度均匀，优选的，所述平坦层500的厚度为1.5μm～3μm。
该TFT阵列基板的第一实施例通过增大TFT900的漏极420的面积，使得所述漏极420与部分公共电极600的水平投影重叠，漏极420与公共电极600构成第一存储电容Cst1，像素电极800与公共电极600构成第二存储电容Cst2，第一存储电容Cst1与第二存储电容Cst2并联构成存储电容Cst，该存储电容Cst的容量等于第一存储电容Cst1和第二存储电容Cst2的容量之和，相比于现有技术，增加了漏极420与公共电极600构成的第一存储电容Cst1，且TFT900上方设有用于遮光的黑色矩阵，即所述漏极420位于遮光区以内，增大漏极420的面积不会导致开口率降低，因此能够在不降低开口率的前提下增加存储电容的容量，改善交叉串扰、影像残留等问题，提升产品的显示质量。
请参阅图4与图6，为进一步增大存储电容，在本发明的TFT阵列基板的第二实施例中，位于所述漏极420与部分公共电极600的水平投影重叠的区域内的平坦层500的厚度小于位于所述漏极420与部分公共电极600的水平投影重叠的区域外的平坦层500的厚度，具体可通过使用半色调掩膜板进行曝光的方法来制作具有不同厚度的平坦层500。相比于第一实施例，该第二实施例减小了第一电容Cst1的一电极板(公共电极600)与另一电极板(漏极420)之间的距离，从而进一步增大了第一电容Cst1的容量。优选的，位于所述漏极420与部分公共电极600的水平投影重叠的区域内的平坦层500的厚度为0.5μm～1μm，位于所述漏极420与部分公共电极600的水平投影重叠的区域外的平坦层500的厚度为1.5μm～3μm。
具体地，所述像素电极800通过贯穿所述保护层700、公共电极600、及平坦层500的过孔810与所述漏极420相接触形成电性连接。
所述阵列基板还包括：多条沿第一方向平行间隔设置的栅极扫描线450、及多条沿与第一方向垂直的第二方向平行间隔设置的数据线440。进一步地，所述数据线440、和源极、及所述漏极420位于同一层，且数据线440与源极电性连接，可通过对第二金属层进行图案化处理得到。所述栅极扫描线450与栅极410位于同一层且电性连接，可通过对第一金属层进行图案化处理得到。
所述源极和漏极420分别通过贯穿层间绝缘层320和栅极绝缘层310的过孔与多晶硅半导体层200的两端相接触形成电性连接。
优选的，所述像素电极80与公共电极60的材料均为氧化铟锡(IndiumTinOxide，ITO)；所述缓冲层110、栅极绝缘层310、层间绝缘层320、平坦层500、及保护层700的材料均为氮化硅(SiNx)、氧化硅(SiOx)中的一种或两种的复合；所述栅极扫描线450、数据线440、栅极410、源极、及漏极420的材料均为钼(Mo)、钛(Ti)、铜(Cu)、铝(Al)中的一种或多种的堆栈组合。
综上所述，本发明的TFT阵列基板通过增大位于遮光区的TFT的漏极的面积，使得所述漏极与部分公共电极的水平投影重叠，漏极与公共电极构成第一存储电容，像素电极与公共电极构成第二存储电容，由于像素电极与漏极相接触形成电性连接，二者等电位，第一存储电容与第二存储电容并联构成存储电容，该存储电容的容量等于第一存储电容和第二存储电容的容量之和，相比于现有技术，能够在不降低开口率的前提下增加存储电容的容量，改善交叉串扰、影像残留等问题，提升产品的显示质量。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (9)

1.一种TFT阵列基板，其特征在于，包括：衬底基板(100)、设于所述衬底基板(100)上的缓冲层(110)、设于所述缓冲层(110)上的数个呈阵列式排布的TFT(900)、设于所述TFT(900)上的平坦层(500)、设于所述平坦层(500)上的公共电极(600)、设于所述公共电极(600)上的保护层(700)、及设于所述保护层(700)上的图案化的像素电极(800)；
所述TFT(900)包括：设于所述缓冲层(110)上的多晶硅半导体层(200)、覆盖所述半多晶硅导体层(200)的栅极绝缘层(310)、于所述多晶硅半导体层(200)上方设于所述栅极绝缘层(310)上的栅极(410)、覆盖所述栅极(410)与栅极绝缘层(310)的层间绝缘层(320)、及设于所述层间绝缘层(320)上的源极与漏极(420)；
所述像素电极(800)与所述漏极(420)电性连接；
所述漏极(420)与部分公共电极(600)的水平投影重叠；
所述漏极(420)与所述公共电极(600)构成第一存储电容(Cst1)，所述像素电极(800)与公共电极(600)构成第二存储电容(Cst2)，所述第一存储电容(Cst1)与第二存储电容(Cst2)并联构成存储电容(Cst)。
2.如权利要求1所述的TTF阵列基板，其特征在于，位于所述漏极(420)与部分公共电极(600)的水平投影重叠的区域内的平坦层(500)的厚度小于位于所述漏极(420)与部分公共电极(600)的水平投影重叠的区域外的平坦层(500)的厚度。
3.如权利要求2所述的TFT阵列基板，其特征在于，位于所述漏极(420)与部分公共电极(600)的水平投影重叠的区域内的平坦层(500)的厚度为0.5μm～1μm，位于所述漏极(420)与部分公共电极(600)的水平投影重叠的区域外的平坦层(500)的厚度为1.5μm～3μm。
4.如权利要求1所述的TFT阵列基板，其特征在于，所述像素电极(800)通过贯穿所述保护层(700)、公共电极(600)、及平坦层(500)的过孔(810)与所述漏极(420)相接触形成电性连接。
5.如权利要求1所述的TFT阵列基板，其特征在于，还包括：多条沿第一方向平行间隔设置的栅极扫描线(450)、及多条沿与第一方向垂直的第二方向平行间隔设置的数据线(440)；
所述数据线(440)、和源极、及所述漏极(420)位于同一层，且数据线(440)与源极电性连接；所述栅极扫描线(450)与栅极(410)位于同一层且电性连接。
6.如权利要求1所述的TFT阵列基板，其特征在于，所述源极和漏极(420)分别通过贯穿层间绝缘层(320)和栅极绝缘层(310)的过孔与多晶硅半导体层(200)的两端相接触形成电性连接。
7.如权利要求1所述的TFT阵列基板，其特征在于，所述像素电极(80)与公共电极(60)的材料均为ITO。
8.如权利要求1所述的TFT阵列基板，其特征在于，所述缓冲层(110)、栅极绝缘层(310)、层间绝缘层(320)、平坦层(500)、及保护层(700)的材料均为氮化硅、氧化硅中的一种或两种的复合。
9.如权利要求5所述的TFT阵列基板，其特征在于，所述栅极扫描线(450)、数据线(440)、栅极(410)、源极、及漏极(420)的材料均为钼、钛、铜、铝中的一种或多种的堆栈组合。
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US11696471B2 (en) 2020-07-24 2023-07-04 Boe Technology Group Co., Ltd. Array substrate including a second electrode of the second capacitor disposed on the same layer with the power supply voltage line, OLED display panel, and display device having the same
CN114497409A (zh) * 2020-10-27 2022-05-13 京东方科技集团股份有限公司 显示模组和具有其的显示装置
CN114497409B (zh) * 2020-10-27 2024-04-05 京东方科技集团股份有限公司 显示模组和具有其的显示装置
WO2022127396A1 (zh) * 2020-12-18 2022-06-23 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114236924A (zh) * 2021-12-14 2022-03-25 Tcl华星光电技术有限公司 显示面板及移动终端
WO2023178794A1 (zh) * 2022-03-25 2023-09-28 惠州华星光电显示有限公司 阵列基板、阵列基板的制作方法及显示面板

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