WO2023178794A1 - 阵列基板、阵列基板的制作方法及显示面板 - Google Patents

阵列基板、阵列基板的制作方法及显示面板 Download PDF

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Publication number
WO2023178794A1
WO2023178794A1 PCT/CN2022/090107 CN2022090107W WO2023178794A1 WO 2023178794 A1 WO2023178794 A1 WO 2023178794A1 CN 2022090107 W CN2022090107 W CN 2022090107W WO 2023178794 A1 WO2023178794 A1 WO 2023178794A1
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Prior art keywords
layer
groove
pixel electrode
array substrate
data
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PCT/CN2022/090107
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English (en)
French (fr)
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黄磊
唐淑敏
杨柳
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惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Publication of WO2023178794A1 publication Critical patent/WO2023178794A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a manufacturing method of the array substrate, and a display panel.
  • the industry usually adopts the COA (Color on Array) process, that is, RGB (red, green , blue, three primary colors) color resist layer is made on the array substrate.
  • COA Color on Array
  • RGB red, green , blue, three primary colors
  • This process can reduce the color resistance shift caused by the alignment shift of the upper and lower substrates and simplify the preparation process of the CF (Color Film) substrate.
  • this process technology prepares the color resistor layer between the pixel electrode and the common electrode, which increases the distance between the pixel electrode and the common electrode and leads to a decrease in storage capacitance.
  • the decrease in storage capacitance can lead to poor display problems such as flicker and crosstalk.
  • This application provides an array substrate to solve the existing technology of preparing a color resistor layer between a pixel electrode and a common electrode.
  • the increase in the distance between the pixel electrode and the common electrode leads to a decrease in storage capacitance, which in turn leads to poor display problems such as flicker and crosstalk.
  • an array substrate which includes:
  • a color resistance layer is formed on the common electrode layer, and a first groove and a second groove are provided on the surface of the side of the color resistance layer facing away from the substrate layer;
  • the data shielding line layer includes data shielding lines, the data shielding lines are formed on the color resist layer, and part of the data shielding lines are located in the first groove;
  • the pixel electrode layer includes a pixel electrode.
  • the pixel electrode is formed on the color resistor layer and is insulated from the data shielding line. Part of the pixel electrode is located in the second groove to connect with the first The data shielding line in the groove forms a first capacitor.
  • the first capacitance is smaller than the second capacitance formed by the pixel electrode and the common electrode layer.
  • the width of the first groove is equal to the width of the second groove.
  • a depth of the first groove is equal to a depth of the second groove.
  • the thickness of the color resist layer is 2 to 3 microns.
  • the depth of the first groove and the second groove is 0.5 to 2 microns.
  • the data shielding line and the pixel electrode are arranged in the same layer.
  • the data shielding line is made of the same material as the pixel electrode.
  • the data shielding line and the pixel electrode are made of any one of ITO, IGZO, and ITO/Ag/ITO stacked materials.
  • a data line is also provided between the common electrode layer and the color resistor layer, and the projection of the data line on the substrate layer is located on the data line shielding line on the substrate layer. within the projection range.
  • embodiments of the present application also provide a method for manufacturing an array substrate, including the following steps:
  • a data shielding line layer and a pixel electrode layer are formed on the color resist layer, wherein part of the data shielding line layer is formed in the first groove, and part of the pixel electrode layer is formed in the second groove. and forms a first capacitor with part of the data shielding line layer.
  • the method further includes:
  • a passivation layer is formed on the source and drain electrode layers.
  • the pixel electrode layer includes a pixel electrode, and part of the pixel electrode and the common electrode layer form a second capacitor.
  • forming the data shielding line layer and the pixel electrode layer on the color resist layer includes: using the same material and forming the data shielding line layer and the pixel electrode layer on the same layer.
  • embodiments of the present application further provide a display panel, including the array substrate described in the above embodiments.
  • this application provides a first groove and a second groove on the color resist layer, forming part of the data shielding line in the first groove, and forming part of the pixel electrode position in the second groove. , so that the data shielding line located in the first groove and the pixel electrode located in the second groove form a first capacitor, thereby increasing the capacitance of the storage capacitor in the display panel, which is used to solve the problem of using the color resist layer in the existing technology.
  • FIG. 1 is a top view of an array substrate provided by the present application and a schematic cross-sectional view of an array substrate provided by the present application.
  • FIG. 2 is a schematic cross-sectional view of the first groove and the second groove of the array substrate provided by the present application.
  • FIG. 3 is a schematic cross-sectional view of the data shielding lines and pixel electrodes of the array substrate provided by the present application.
  • the present application provides an array substrate, a manufacturing method of the array substrate, and a display panel.
  • the present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.
  • one embodiment of the present application provides a method for manufacturing an array substrate, which includes the following steps:
  • a data shielding line layer and a pixel electrode layer are formed on the color resistor layer 4. It can be known that the data shielding line layer includes the data shielding line 12, and the pixel electrode layer includes the pixel electrode 11, wherein part of The data shielding line 12 is formed in the first groove 13 , and part of the pixel electrode 11 is formed in the second groove 14 .
  • the common electrode layer includes the common electrode 2, the data shielding line 12 in the first groove 13 and the pixel electrode 11 in the second groove 14 form a first capacitor, and the pixel electrode 11 and the common electrode 2 form a second capacitor, and the first capacitor and the second capacitor together form a storage capacitor in the display panel.
  • This embodiment provides a method for manufacturing an array substrate.
  • the data shielding lines 12 are formed on the color resist layer 4 and part of the data shielding lines 12 are located on the color resist layer 4.
  • the pixel electrode 11 is formed on the color resist layer 4 and part of the pixel electrode 11 is located in the second groove 14.
  • the data shielding line 12 located in the first groove 13 and the data shielding line 12 located in the second groove 14 The pixel electrode 11 forms a first capacitor, which is used to solve the problem of the existing technology.
  • the color resistor layer 4 is prepared between the pixel electrode 11 and the common electrode 2, so that the distance between the pixel electrode 11 and the common electrode 2 increases, resulting in a capacitance of the second capacitor. decrease, which will lead to poor display problems such as flicker and crosstalk, ensuring the stability of the display screen.
  • the gate electrode 5 and the gate line are also formed at the same time. It can be known that there is a gap between the gate electrode 5 and the gate line. Electrical connection.
  • the above steps can be produced by etching methods commonly used in this field, such as depositing a first metal layer on the substrate layer 1, etching the first metal layer after photoresist treatment, to obtain the above-mentioned common electrode 2, gate electrode 5 and gate electrode 2.
  • the material of the first metal layer usually includes one or more of Cu (copper) and Al (aluminum).
  • the substrate layer 1 may include a single layer of insulating material such as glass, quartz and polymer resin, or a multi-layer insulating material such as a double layer of polymer resin.
  • the substrate layer 1 may be rigid or flexible and carries a film layer disposed thereon.
  • the insulating layer 3 covers the etched structure of the first metal layer.
  • the insulating layer 3 can be a commonly used method in the art. Made by chemical vapor deposition method, such as depositing a layer of insulating material on the substrate layer 1 to cover the common electrode 2, gate 5 and gate lines.
  • the insulating material usually includes SiNx (silicon nitride) and SiOx (oxide Silicon) one or more.
  • a semiconductor material layer is deposited on the insulating layer 3 using a chemical vapor deposition method, the semiconductor material layer is etched to form an active layer 7 , and a layer of semiconductor material is deposited on the active layer 7
  • the second metal layer is etched to form the source electrode 8, the drain electrode 9 and the data line 6.
  • the data line 6 is electrically connected to the source electrode 8. It can be known that the The data line 6 may be connected to the drain electrode 9 or the source electrode 8.
  • the gate electrode 5, the active layer 7, the drain electrode 9 and the source electrode 8 constitute a TFT (Thin Film Transistor, thin film transistor).
  • a passivation layer needs to be covered.
  • the passivation layer can also be formed by the chemical vapor phase. The deposition method is produced and will not be described in detail here.
  • forming the color resistance layer 4 on the common electrode 2 involves depositing a color resistance material on the passivation layer and etching the color resistance material to form the color resistance layer 4, and A first groove 13 and a second groove 14 are formed on a surface of the color resist layer 4 facing away from the substrate layer 1 .
  • a transparent conductive material layer can be deposited on the color resistor layer 4.
  • the transparent conductive material layer can be After etching, the data shielding line 12 and the pixel electrode 11 are obtained. It can be known that the projection of the data line 6 on the substrate layer 1 is located at the position of the data shielding line 12 on the substrate layer 1 Within the projection outline, since there are the first groove 13 and the second groove 14 on the color resist layer 4, during deposition, the transparent conductive material will also be deposited on the first groove 13 and the second groove 14.
  • the data shielding line 12 also includes a portion deposited in the first groove 13, and the pixel electrode 11 also includes a portion deposited in the second groove 14. part. It can be known that the pixel electrode 11 needs to be connected to the drain electrode 9 to receive the data signal of the data line 6. Therefore, in the above steps, a via hole 10 will also be formed to connect the pixel electrode 11 with the drain electrode. 9 Electrical connection.
  • This embodiment provides an array substrate, including:
  • Substrate layer 1 a common electrode layer is formed on the substrate layer 1, and the common electrode layer includes a common electrode 2;
  • Color resistor layer 4 the color resistor layer 4 is formed on the common electrode layer, and a first groove 13 and a second groove 14 are provided on the surface of the side of the color resistor away from the substrate layer 1;
  • Data shielding line layer includes data shielding lines 12, the data shielding lines 12 are formed on the color resistor, and part of the data shielding lines 12 is located in the first groove 13;
  • the pixel electrode layer includes a pixel electrode 11.
  • the pixel electrode 11 is formed on the color resistor layer 4 and is insulated from the data shielding line 12. Part of the pixel electrode 11 is located on the second in the groove 14 to form a first capacitor with the data shielding line 12 in the first groove 13 .
  • This embodiment provides an array substrate.
  • the color resistor layer 4 of the array substrate is provided with a first groove 13 and a second groove 14.
  • the data shielding line 12 is formed on the color resistor layer 4 and partially The data shielding line 12 is located in the first groove 13.
  • the pixel electrode 11 is formed on the color resist layer 4 and part of the pixel electrode 11 is located in the second groove 14.
  • the data shielding line 12 located in the first groove 13 and The pixel electrode 11 located in the second groove 14 forms a first capacitor to solve the problem that in the prior art, the color resistance layer 4 is prepared between the pixel electrode 11 and the common electrode 2, so that the distance between the pixel electrode 11 and the common electrode 2 is increased. , leading to a decrease in the capacitance of the second capacitor formed by the pixel electrode 11 and the common electrode 2, which in turn leads to display problems such as flicker and crosstalk, ensuring the stability of the display screen.
  • setting the first capacitance to be smaller than the second capacitance formed by the pixel electrode 11 and the common electrode 2 can prevent the first capacitance from being too large, causing the first capacitance to be
  • the charging rate of the second capacitor becomes low, that is, the first capacitor and the second capacitor cannot be charged to the required amount of electricity within the original charging time, that is, the required voltage cannot be reached.
  • the width of the first groove 13 is equal to the width of the second groove 14, and the depth of the first groove 13 is equal to the depth of the second groove 14.
  • the width refers to the length of one side of the side where the first groove 13 and the second groove 14 are close to each other, and the length of the other side of the side is the depth of the corresponding groove. It can be known that, from the capacitance Capacity calculation formula:
  • c ⁇ s/4 ⁇ kd
  • ⁇ is the dielectric constant of the intermediate medium
  • s is the effective facing area of the two electrode plates
  • ⁇ and k are constants
  • d is the distance between the two electrode plates.
  • the capacitance value of the capacitor is usually related to the effective facing area and spacing between the two plates and the dielectric constant of the medium between the two plates. Therefore, when other parameters are fixed, the data shielding line 12 and the pixel are added.
  • the effective facing area of the electrode 11 can increase the capacitance of the first capacitor formed by the data shielding line 12 and the pixel electrode 11, thus making the first groove 13 and the second groove 14 The areas close to each other are equal. Even if the effective facing area is the largest, the capacitance value of the capacitor can be maximized.
  • the thickness of the color resist layer 4 is 2 to 3 microns, and the depths of the first groove 13 and the second groove 14 are 0.5 to 2 microns. It can be understood that in order to prevent short circuit, the depth of the first groove 13 and the second groove 14 cannot exceed the thickness of the color resist. Specifically, the depth of the first groove 13 and the second groove 14 cannot exceed the thickness of the color resistor.
  • the depth of the two grooves 14 is 0.7 microns, that is, the depth at which the pixel electrode 11 and the data shielding line 12 are inserted into the color resist layer 4 is 0.7 microns, and the thickness of the color resist layer 4 is 2.3 microns.
  • the data shielding line 12 and the pixel electrode 11 are arranged in the same layer and made of the same material.
  • the materials of the data shielding line 12 and the pixel electrode 11 include ITO (Indium-Tin- Any one of Oxide (indium tin oxide), IGZO (indium gallium zinc oxide, indium gallium zinc oxide) and ITO/Ag/ITO stacked materials, it can be known that the data shielding line 12 and the pixel
  • the material of the electrode 11 includes transparent conductive materials commonly used in this field.
  • a data line 6 is also provided between the common electrode 2 and the color resistance layer 4. It can be understood that the data shielding line 12 is used to form an electric field with the common electrode 2 to make the display panel The liquid crystal in the area corresponding to the data shielding line 12 remains undeflected, thus achieving the purpose of shielding light. Then the projection of the data line 6 on the substrate layer 1 is located at the shielding line of the data line 6. Within the projection range on the substrate layer 1, the data line 6 is usually 5 to 10 microns, specifically, the data line 6 is 8 microns, and the data shielding line 12 usually exceeds the data on one side. Line 6 is two microns, specifically, when the data line 6 is 8 microns, the data shielding line 12 is 12 microns.
  • This embodiment provides a display panel, which includes the array substrate shown in the above embodiment.
  • the display panel includes a display area and a non-display area, and the display area may be a sub-section for setting a display image.
  • the non-display area of a pixel may be a driving unit, such as a gate driving circuit, that is configured to provide a driving signal to a pixel driving circuit of a sub-pixel, and an area of some lines, such as power lines, connected to the driving unit. There may be no sub-pixels provided in the non-display area.
  • the non-display area may be provided on at least one side of the display area.
  • the non-display area may at least partially surround the display area.
  • the non-display area may be provided on at least one side of the display area.
  • the non-display area may at least partially surround the display area.
  • the display area includes an opening area and a non-opening area.
  • the gate electrode 5, gate line, drain electrode 9, and source electrode 8 are all located in the non-opening area.
  • the pixel electrode 11 and the common electrode 2 are located in the opening area, and the color resist layer 4 covers both the opening area and the non-opening area.
  • the location of the film layer is well known to those skilled in the art, and is only illustrative and will not be described in detail.

Abstract

公开一种阵列基板、阵列基板的制作方法及显示面板，该阵列基板包括衬底、公共电极层以及色阻层，色阻层背离衬底层的一侧表面开设有第一凹槽和第二凹槽，在色阻层上形成数据遮蔽线层和像素电极层，且部分数据遮蔽线层位于第一凹槽内，部分像素电极层位于第二凹槽内，以与第一凹槽内的数据遮蔽线层形成第一电容。

Description

阵列基板、阵列基板的制作方法及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、阵列基板的制作方法及显示面板。
背景技术
目前的LCD(Liquid Cystal Display，液晶显示面板)中，基于高解析度产品的开口率和穿透率，以及曲面应用场景，业界通常会采取COA(Color on Array)制程，即将RGB(red、green、blue，三原色)色阻层做在阵列基板上。这种制程可以减小上下基板对位偏移导致的色阻偏移以及简化CF(Color Film，彩膜)基板的制备工艺。
然而这种制程工艺将色阻层制备于像素电极和公共电极之间，这样会增加像素电极和公共电极的距离导致存储电容的下降，存储电容的下降会导致闪烁和串扰等显示不良问题。
技术问题
本申请提供一阵列基板，以解决现有技术将色阻层制备于像素电极和公共电极之间，像素电极和公共电极的距离增加导致存储电容的下降，进而导致闪烁和串扰等显示不良问题。
技术解决方案
第一方面，本申请实施例提供一种阵列基板，其包括：
衬底层，所述衬底层上形成有公共电极层；
色阻层，所述色阻层形成于所述公共电极层上，且所述色阻层背离所述衬底层的一侧表面开设有第一凹槽和第二凹槽；
数据遮蔽线层，包括数据遮蔽线，所述数据遮蔽线形成于所述色阻层上，且部分所述数据遮蔽线位于所述第一凹槽内；
像素电极层，包括像素电极，所述像素电极形成于所述色阻层上且与所述数据遮蔽线绝缘设置，部分所述像素电极位于所述第二凹槽内，以与所述第一凹槽内的所述数据遮蔽线形成第一电容。
在所述的阵列基板中，所述第一电容小于所述像素电极与所述公共电极层所形成的第二电容。
在所述的阵列基板中，所述第一凹槽的宽度等于所述第二凹槽的宽度。
在所述的阵列基板中，所述第一凹槽的深度等于所述第二凹槽的深度。
在所述的阵列基板中，所述色阻层的厚度为2至3微米。
在所述的阵列基板中，所述第一凹槽和所述第二凹槽的深度为0.5至2微米。
在所述的阵列基板中，所述数据遮蔽线与所述像素电极同层设置
在所述的阵列基板中，所述数据遮蔽线与所述像素电极材料相同。
在所述的阵列基板中，所述数据遮蔽线和所述像素电极的材料包括ITO、IGZO以及ITO/Ag/ITO叠层材料中的任意一个。
在所述的阵列基板中，所述公共电极层和色阻层之间还设置有数据线，所述数据线在所述衬底层上的投影位于所述数据线遮蔽线在所述衬底层上的投影范围内。
第二方面，本申请实施例还提供一种阵列基板的制作方法，包括以下步骤：
在所述衬底层上形成公共电极层；
在所述公共电极层上形成色阻层，并在所述色阻层背离所述衬底层的一侧表面形成第一凹槽和第二凹槽；
在所述色阻层上形成数据遮蔽线层和像素电极层，其中，部分所述数据遮蔽线层形成于所述第一凹槽内，部分所述像素电极层形成于所述第二凹槽内且与部分所述数据遮蔽线层形成第一电容。
在所述的制作方中，在所述公共电阻层上形成色阻层之前还包括：
在所述公共电极层上形成绝缘层；
在所述绝缘层上形成有源层；
在所述有源层上形成源漏极；
在所述源漏极层上形成钝化层。
在所述的制作方中，形成所述源漏极时，还会形成数据线。
在所述的制作方中，所述像素电极层包括像素电极，部分所述像素电极与所述公共电极层形成第二电容。
在所述的制作方中，所述在所述色阻层上形成数据遮蔽线层和像素电极层包括：用相同材料且在同一层形成所述数据遮蔽线层和所述像素电极层。
第三方面，本申请实施例还提供一种显示面板，包括上述实施例所述的阵列基板。
有益效果
相较于现有技术，本申请通过在色阻层上设置第一凹槽和第二凹槽，将部分数据遮蔽线形成于第一凹槽内，将部分像素电极位形成于第二凹槽内，使得位于第一凹槽内的数据 遮蔽线与位于第二凹槽内的像素电极形成第一电容，从而增加显示面板内的存储电容的容值，用于解决现有技术将色阻层制备于像素电极和公共电极之间，使得像素电极和公共电极的距离增加，导致像素电极和公共电极形成的第二电容的容值下降，即存储电容的容值下降，进而导致闪烁和串扰等显示不良问题，保证显示画面的稳定性。
附图说明
图1为本申请提供的阵列基板的俯视图本发明提供的阵列基板的剖面示意图。
图2为本申请提供的阵列基板的第一凹槽和第二凹槽的剖面示意图。
图3为本申请提供的提供的阵列基板的数据遮蔽线和像素电极的剖面示意图。
本发明的实施方式
本申请提供一种阵列基板、阵列基板的制作方法及显示面板，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1、图2和图3，本申请一实施例，提供一种阵列基板的制作方法，包括以下步骤：
在所述衬底层1上形成公共电极层；
在所述公共电极层上形成色阻层4，并在所述色阻层4背离所述衬底层1的一侧表面形成第一凹槽13和第二凹槽14；
在所述色阻层4上形成数据遮蔽线层和像素电极层，可以知道的是，所述数据遮蔽线层包括数据遮蔽线12，所述像素电极层包括像素电极11，其中，部分所述数据遮蔽线12形成于所述第一凹槽13内，部分所述像素电极11形成于所述第二凹槽14内。
可以知道的是，所述公共电极层包括公共电极2，所述第一凹槽13内的数据遮蔽线12与所述第二凹槽14内的像素电极11形成第一电容，所述像素电极11和公共电极2形成第二电容，所述第一电容和第二电容共同组成显示面板内的存储电容。
本实施例提供一种阵列基板的制作方法，通过在色阻层4设置第一凹槽13和第二凹槽14，数据遮蔽线12形成于色阻层4上且部分数据遮蔽线12位于第一凹槽13内，像素电极11形成于色阻层4上且部分像素电极11位于第二凹槽14内，位于第一凹槽13内的数据遮蔽线12与位于第二凹槽14内的像素电极11形成第一电容，用于解决现有技术将色阻层4制备于像素电极11和公共电极2之间，使得像素电极11和公共电极2的距离增加，导致第二电容的容值的下降，进而导致闪烁和串扰等显示不良问题，保证显示画面的稳定性。
具体来说，上述实施例所示的方法中，在衬底层1上形成公共电极2时，还会同时形成栅极5和栅极线，可以知道的是，栅极5和栅极线之间电性连接。
以上步骤可用本领域常用的蚀刻方法制作，如在衬底层1上沉积第一金属层，利用光阻处理后对该第一金属层进行蚀刻，以得到上述的公共电极2、栅极5和栅极线，所述第一金属层的材料通常包括Cu(铜)和Al(铝)中的一种或几种。
可以知道的是，所述衬底层1可以包括如玻璃、石英和聚合物树脂的单层绝缘材料，或者如双层聚合物树脂的多层绝缘材料。所述衬底层1可以是刚性的、或者柔性的，所述衬底层1承载设置于其上的膜层。
在所述公共电极2和所述栅极5形成后，需要形成一绝缘层3，所述绝缘层3覆盖所述第一金属层蚀刻后的结构，所述绝缘层3可采用本领域常用的化学气相沉积法制作，如在所述衬底层1上沉积一层绝缘材料，以覆盖所述公共电极2、栅极5和栅极线，绝缘材料通常包括SiNx(氮化硅)和SiOx(氧化硅)中的一种或几种。
在所述绝缘层3上形成后，利用化学气相沉积法在绝缘层3上沉积一半导体材料层，对所述半导体材料层进行蚀刻，形成有源层7，在所述有源层7上沉积第二金属层，对所述第二金属层进行蚀刻以形成源极8、漏极9和数据线6，所述数据线6与所述源极8电性连接，可以知道的是，所述数据线6可与所述漏极9连接，也可与所述源极8连接，本实施例仅做示例性描述，并不对此构成限定。可以知道的是，所述栅极5、所述有源层7、所述漏极9以及所述源极8构成TFT(Thin Film Transistor,薄膜晶体管)。可以知道的是，在所述源极8、所述漏极9和所述数据线6上形成色阻层4前还需要覆盖一钝化层，所述钝化层也可通过所述化学气相沉积法制作，在此不再赘述。
具体来说，在所述公共电极2上形成色阻层4为在所述钝化层上沉积色阻材料，并对所述色阻材料进行蚀刻，以形成所述色阻层4，并在所述色阻层4背离所述衬底层1的一侧表面形成第一凹槽13和第二凹槽14。
具体来说，为了在所述色阻层4上形成数据遮蔽线12和像素电极11，可在所述色阻层4上沉积一透明导电材料层，同样的，对所述透明导电材料层进行蚀刻后得到所述数据遮蔽线12和所述像素电极11，可以知道的是，所述数据线6在所述衬底层1上的投影位于所述数据遮蔽线12在所述衬底层1上的投影轮廓内，由于所述色阻层4上有所述第一凹槽13和所述第二凹槽14，在沉积时，所述透明导电材料也会沉积在所述第一凹槽13和所述第二凹槽14内，因此，所述数据遮蔽线12还包括沉积于所述第一凹槽13内的部分，所述像素电极11还包括沉积于所述第二凹槽14内的部分。可以知道的是，像素电极11需与所 述漏极9连接以接收所述数据线6的数据信号，故在以上步骤中，还会形成过孔10，以使像素电极11与所述漏极9电性连接。
本实施例提供一种阵列基板，包括：
衬底层1，所述衬底层1上形成有公共电极层，所述公共电极层包括公共电极2；
色阻层4，所述色阻层4形成于所述公共电极层上，且所述色阻背离所述衬底层1的一侧表面开设有第一凹槽13和第二凹槽14；
数据遮蔽线层，所述数据遮蔽线层包括数据遮蔽线12，所述数据遮蔽线12形成于所述色阻上，且部分所述数据遮蔽线12位于所述第一凹槽13内；
像素电极层，所述像素电极层包括像素电极11，所述像素电极11形成于所述色阻层4上且与所述数据遮蔽线12绝缘设置，部分所述像素电极11位于所述第二凹槽14内，以与所述第一凹槽13内的所述数据遮蔽线12形成第一电容。
本实施例提供一种阵列基板，所述阵列基板的所述色阻层4上设置有第一凹槽13和第二凹槽14，所述数据遮蔽线12形成于色阻层4上且部分数据遮蔽线12位于第一凹槽13内，所述像素电极11形成于色阻层4上且部分像素电极11位于第二凹槽14内，位于第一凹槽13内的数据遮蔽线12与位于第二凹槽14内的像素电极11形成第一电容，用于解决现有技术将色阻层4制备于像素电极11和公共电极2之间，使得像素电极11和公共电极2的距离增加，导致像素电极11和公共电极2形成的第二电容的容值的下降，进而导致闪烁和串扰等显示不良问题，保证显示画面的稳定性。
在一些实施例中，将所述第一电容设置为小于所述像素电极11与所述公共电极2所形成的第二电容，能够防止所述第一电容过大导致所述第一电容和所述第二电容的充电率变低，即在原有充电时间内不能给所述第一电容和所述第二电容充至所需电量，即达不到所需电压。
在一些实施例中，所述第一凹槽13的宽度等于所述第二凹槽14的宽度，且所述第一凹槽13的深度等于所述第二凹槽14的深度，所述宽度是指所述第一凹槽13和所述第二凹槽14相互靠近的一面的一条边的长度，该面的另一条边的长度为对应凹槽的深度，可以知道的是，由电容的容值计算公式：
c＝εs/4πkd，ε为中间介质的介电常数，s为两极板的有效正对面积，π和k为常数，d为两极板之间的间距。
可知，电容的容值通常与两极板之间的有效正对面积、间距以及两极板中间介质的介电常数有关，因此在其他参数固定的情况下，增加所述数据遮蔽线12和所述像素电极11 的有效正对面积即可增加所述数据遮蔽线12和所述像素电极11所形成的所述第一电容的容值，因此使所述第一凹槽13和所述第二凹槽14相互靠近一面的面积相等，即使有效正对面积最大，即可最大化增加所述电容的容值。
在一些实施例中，所述色阻层4的厚度为2至3微米，所述第一凹槽13和所述第二凹槽14的深度为0.5至2微米。可以知道的是，为了防止短路，所述第一凹槽13和所述第二凹槽14的深度不能超过所述色阻的厚度，具体来说，所述第一凹槽13和所述第二凹槽14的深度为0.7微米，即所述像素电极11和所述数据遮蔽线12插入所述色阻层4的深度为0.7微米，所述色阻层4的厚度为2.3微米。
在一些实施例中，所述数据遮蔽线12与所述像素电极11同层设置且材料相同，具体来说，所述数据遮蔽线12和所述像素电极11的材料包括ITO(Indium-Tin-Oxide，铟锡氧化物)、IGZO(indium gallium zinc oxide，铟镓锌氧化物)以及ITO/Ag/ITO叠层材料中的任意一个，可以知道的是，所述数据遮蔽线12和所述像素电极11的材料包括本领域常用的透明导电材料。
在一些实施例中，所述公共电极2和色阻层4之间还设置有数据线6，可以知道的是，所述数据遮蔽线12用于与所述公共电极2形成电场以使显示面板内与所述数据遮蔽线12所对应区域的液晶保持不偏转的状态，从而起到遮光的目的，则所述数据线6在所述衬底层1上的投影位于所述数据线6遮蔽线在所述衬底层1上的投影范围内，所述数据线6通常为5至10微米，具体来说，所述数据线6为8微米，而所述数据遮蔽线12通常单侧超出所述数据线6两微米，具体来说，当所述数据线6为8微米时，所述数据遮蔽线12为12微米。
本实施例提供一种显示面板，其包括上述实施例所示的阵列基板，可以知道的是，所述显示面板包括显示区和非显示区，所述显示区可以是用于设置显示图像的子像素的区域，所述非显示区可以是用于设置为子像素的像素驱动电路提供驱动信号的驱动单元如栅极驱动电路，以及连接驱动单元的一些线如电源线的区域。在所述非显示区内可能没有设置子像素。所述非显示区可以设置在显示区的至少一侧。所述非显示区可以至少部分地围绕显示区的周围。
非显示区可以设置在显示区的至少一侧。非显示区可以至少部分地围绕显示区的周围。
可以知道的是，所述显示区包括开口区和非开口区，所述栅极5、栅极线、漏极9、和源极8均位于非开口区内，所述像素电极11、公共电极2均位于开口区内，所述色阻层4同时覆盖了所述开口区和所述非开口区，膜层位置为本领域技术人员公知，仅做示例性说 明，不做赘述。
综上所述，虽然本申请已以上述实施例揭露如上，但上述实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种阵列基板，其包括：
    衬底层，所述衬底层上形成有公共电极层；
    色阻层，所述色阻层形成于所述公共电极层上，且所述色阻层背离所述衬底层的一侧表面开设有第一凹槽和第二凹槽；
    数据遮蔽线层，包括数据遮蔽线，所述数据遮蔽线形成于所述色阻层上，且部分所述数据遮蔽线位于所述第一凹槽内；
    像素电极层，包括像素电极，所述像素电极形成于所述色阻层上且与所述数据遮蔽线绝缘设置，部分所述像素电极位于所述第二凹槽内，以与所述第一凹槽内的所述数据遮蔽线形成第一电容。
  2. 根据权利要求1所述的阵列基板，其中，所述第一电容小于所述像素电极与所述公共电极层所形成的第二电容。
  3. 根据权利要求1所述的阵列基板，其中，所述第一凹槽的宽度等于所述第二凹槽的宽度。
  4. 根据权利要求3所述的阵列基板，其中，所述第一凹槽的深度等于所述第二凹槽的深度。
  5. 根据权利要求4所述的阵列基板，其中，所述色阻层的厚度为2至3微米。
  6. 根据权利要求5所述的阵列基板，其中，所述第一凹槽和所述第二凹槽的深度为0.5至2微米。
  7. 根据权利要求1所述的阵列基板，其中，所述数据遮蔽线与所述像素电极同层设置
  8. 根据权利要求7所述的阵列基板，其中，所述数据遮蔽线与所述像素电极材料相同。
  9. 根据权利要求6所述的阵列基板，其中，所述数据遮蔽线和所述像素电极的材料包括ITO、IGZO以及ITO/Ag/ITO叠层材料中的任意一个。
  10. 根据权利要求1所述的阵列基板，其中，所述公共电极层和色阻层之间还设置有数据线，所述数据线在所述衬底层上的投影位于所述数据线遮蔽线在所述衬底层上的投影范围内。
  11. 一种阵列基板的制作方法，其包括以下步骤：
    在所述衬底层上形成公共电极层；
    在所述公共电极层上形成色阻层，并在所述色阻层背离所述衬底层的一侧表面形成第一凹槽和第二凹槽；
    在所述色阻层上形成数据遮蔽线层和像素电极层，其中，部分所述数据遮蔽线层形成于所述第一凹槽内，部分所述像素电极层形成于所述第二凹槽内且与部分所述数据遮蔽线层形成第一电容。
  12. 根据权利要求11所述的制作方法，其中，在所述公共电阻层上形成色阻层之前还包括：
    在所述公共电极层上形成绝缘层；
    在所述绝缘层上形成有源层；
    在所述有源层上形成源漏极；
    在所述源漏极层上形成钝化层。
  13. 根据权利要求12所述的制作方法，其中，形成所述源漏极时，还会形成数据线。
  14. 根据权利要求12所述的制作方法，其中，所述像素电极层包括像素电极，部分所述像素电极与所述公共电极层形成第二电容。
  15. 根据权利要求12所述的制作方法，其中，所述在所述色阻层上形成数据遮蔽线层和像素电极层包括：用相同材料且在同一层形成所述数据遮蔽线层和所述像素电极层。
  16. 一种显示面板，其包括如权利要求1所述的阵列基板。
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