CN114660866B - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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CN114660866B
CN114660866B CN202210305114.1A CN202210305114A CN114660866B CN 114660866 B CN114660866 B CN 114660866B CN 202210305114 A CN202210305114 A CN 202210305114A CN 114660866 B CN114660866 B CN 114660866B
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layer
groove
pixel electrode
shielding line
data
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CN114660866A (zh
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黄磊
唐淑敏
杨柳
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2022/090107 priority patent/WO2023178794A1/zh
Priority to US17/756,636 priority patent/US20240162245A1/en
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Abstract

本发明提供一种阵列基板及显示面板，包括在衬底层上形成的公共电极层，在所述公共电极层上形成的色阻层，在所述色阻层背离所述衬底层的一侧表面开设有第一凹槽和第二凹槽，在所述色阻层上形成数据遮蔽线层和像素电极层，且部分所述数据遮蔽线层位于所述第一凹槽内，部分所述像素电极层位于所述第二凹槽内，以与所述第一凹槽内的所述数据遮蔽线层形成第一电容。解决了现有技术将色阻层制备于像素电极层和公共电极层之间，像素电极层和公共电极层的距离增加导致存储电容的容值下降，进而导致闪烁和串扰等显示不良问题。

Description

阵列基板及显示面板
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
背景技术
目前的LCD(Liquid Cystal Display，液晶显示面板)中，基于高解析度产品的开口率和穿透率，以及曲面应用场景，业界通常会采取COA(Color on Array)制程，即将RGB(red、green、blue，三原色)色阻层做在阵列基板上。这种制程可以减小上下基板对位偏移导致的色阻偏移以及简化CF(Color Film，彩膜)基板的制备工艺。
然而这种制程工艺将色阻层制备于像素电极和公共电极之间，这样会增加像素电极和公共电极的距离导致存储电容的下降，存储电容的下降会导致闪烁和串扰等显示不良问题。
发明内容
本发明提供一阵列基板，以解决现有技术将色阻层制备于像素电极和公共电极之间，像素电极和公共电极的距离增加导致存储电容的下降，进而导致闪烁和串扰等显示不良问题。
为解决上述问题，本发明提供的技术方案如下：
一种阵列基板，包括：
衬底层，所述衬底层上形成有公共电极层；
色阻层，所述色阻层形成于所述公共电极层上，且所述色阻层背离所述衬底层的一侧表面开设有第一凹槽和第二凹槽；
数据遮蔽线层，包括数据遮蔽线，所述数据遮蔽线形成于所述色阻层上，且部分所述数据遮蔽线位于所述第一凹槽内；
像素电极层，包括像素电极，所述像素电极形成于所述色阻层上且与所述数据遮蔽线绝缘设置，部分所述像素电极位于所述第二凹槽内，以与所述第一凹槽内的所述数据遮蔽线形成第一电容。
根据本发明一优选实施例，所述第一电容小于所述像素电极与所述公共电极层所形成的第二电容。
根据本发明一优选实施例，所述第一凹槽的宽度等于所述第二凹槽的宽度。
根据本发明一优选实施例，所述第一凹槽的深度等于所述第二凹槽的深度。
根据本发明一优选实施例，所述色阻层的厚度为2至3微米，所述第一凹槽和所述第二凹槽的深度为0.5至2微米。
根据本发明一优选实施例，所述数据遮蔽线与所述像素电极同层设置且材料相同。
根据本发明一优选实施例，所述数据遮蔽线和所述像素电极的材料包括ITO、IGZO以及ITO/Ag/ITO叠层材料中的任意一个。
根据本发明一优选实施例，所述公共电极层和色阻层之间还设置有数据线，所述数据线在所述衬底层上的投影位于所述数据线遮蔽线在所述衬底层上的投影范围内。
本发明还提供一种阵列基板的制作方法，包括以下步骤：
在所述衬底层上形成公共电极层；
在所述公共电极层上形成色阻层，并在所述色阻层背离所述衬底层的一侧表面形成第一凹槽和第二凹槽；
在所述色阻层上形成数据遮蔽线层和像素电极层，其中，部分所述数据遮蔽线层形成于所述第一凹槽内，部分所述像素电极层形成于所述第二凹槽内且与部分所述数据遮蔽线层形成第一电容。
本发明还提供一种显示面板，包括上述实施例所述的阵列基板，或上述制作方法所制作的阵列基板。
本发明的有益效果为：本发明通过在色阻层上设置第一凹槽和第二凹槽，将部分数据遮蔽线形成于第一凹槽内，将部分像素电极位形成于第二凹槽内，使得位于第一凹槽内的数据遮蔽线与位于第二凹槽内的像素电极形成第一电容，从而增加显示面板内的存储电容的容值，用于解决现有技术将色阻层制备于像素电极和公共电极之间，使得像素电极和公共电极的距离增加，导致像素电极和公共电极形成的第二电容的容值下降，即存储电容的容值下降，进而导致闪烁和串扰等显示不良问题，保证显示画面的稳定性。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的阵列基板的俯视图本发明提供的阵列基板的剖面示意图；
图2为本发明提供的阵列基板的第一凹槽和第二凹槽的剖面示意图；
图3为本发明提供的阵列基板的数据遮蔽线和像素电极的剖面示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1、图2和图3，本申请一实施例，提供一种阵列基板的制作方法，包括以下步骤：
在所述衬底层1上形成公共电极层；
在所述公共电极层上形成色阻层4，并在所述色阻层4背离所述衬底层1的一侧表面形成第一凹槽13和第二凹槽14；
在所述色阻层4上形成数据遮蔽线层和像素电极层，可以知道的是，所述数据遮蔽线层包括数据遮蔽线12，所述像素电极层包括像素电极11，其中，部分所述数据遮蔽线12形成于所述第一凹槽13内，部分所述像素电极11形成于所述第二凹槽14内。
可以知道的是，所述公共电极层包括公共电极2，所述第一凹槽13内的数据遮蔽线12与所述第二凹槽14内的像素电极11形成第一电容，所述像素电极11和公共电极2形成第二电容，所述第一电容和第二电容共同组成显示面板内的存储电容。
本实施例提供一种阵列基板的制作方法，通过在色阻层4设置第一凹槽13和第二凹槽14，数据遮蔽线12形成于色阻层4上且部分数据遮蔽线12位于第一凹槽13内，像素电极11形成于色阻层4上且部分像素电极11位于第二凹槽14内，位于第一凹槽13内的数据遮蔽线12与位于第二凹槽14内的像素电极11形成第一电容，用于解决现有技术将色阻层4制备于像素电极11和公共电极2之间，使得像素电极11和公共电极2的距离增加，导致第二电容的容值的下降，进而导致闪烁和串扰等显示不良问题，保证显示画面的稳定性。
具体的，上述实施例所示的方法中，在衬底层1上形成公共电极2时，还会同时形成栅极5和栅极线，可以知道的是，栅极5和栅极线之间电性连接。
以上步骤可用本领域常用的蚀刻方法制作，如在衬底层1上沉积第一金属层，利用光阻处理后对该第一金属层进行蚀刻，以得到上述的公共电极2、栅极5和栅极线，所述第一金属层的材料通常包括Cu(铜)和Al(铝)中的一种或几种。
可以知道的是，所述衬底层1可以包括如玻璃、石英和聚合物树脂的单层绝缘材料，或者如双层聚合物树脂的多层绝缘材料。所述衬底层1可以是刚性的、或者柔性的，所述衬底层1承载设置于其上的膜层。
在所述公共电极2和所述栅极5形成后，需要形成一绝缘层3，所述绝缘层3覆盖所述第一金属层蚀刻后的结构，所述绝缘层3可采用本领域常用的化学气相沉积法制作，如在所述衬底层1上沉积一层绝缘材料，以覆盖所述公共电极2、栅极5和栅极线，绝缘材料通常包括SiNx(氮化硅)和SiOx(氧化硅)中的一种或几种。
在所述绝缘层3上形成后，利用化学气相沉积法在绝缘层3上沉积一半导体材料层，对所述半导体材料层进行蚀刻，形成有源层7，在所述有源层7上沉积第二金属层，对所述第二金属层进行蚀刻以形成源极8、漏极9和数据线6，所述数据线6与所述源极8电性连接，可以知道的是，所述数据线6可与所述漏极9连接，也可与所述源极8连接，本实施例仅做示例性描述，并不对此构成限定。可以知道的是，所述栅极5、所述有源层7、所述漏极9以及所述源极8构成TFT(Thin Film Transistor,薄膜晶体管)。可以知道的是，在所述源极8、所述漏极9和所述数据线6上形成色阻层4前还需要覆盖一钝化层，所述钝化层也可通过所述化学气相沉积法制作，在此不再赘述。
具体的，在所述公共电极2上形成色阻层4为在所述钝化层上沉积色阻材料，并对所述色阻材料进行蚀刻，以形成所述色阻层4，并在所述色阻层4背离所述衬底层1的一侧表面形成第一凹槽13和第二凹槽14。
具体的，为了在所述色阻层4上形成数据遮蔽线12和像素电极11，可在所述色阻层4上沉积一透明导电材料层，同样的，对所述透明导电材料层进行蚀刻后得到所述数据遮蔽线12和所述像素电极11，可以知道的是，所述数据线6在所述衬底层1上的投影位于所述数据遮蔽线12在所述衬底层1上的投影轮廓内，由于所述色阻层4上有所述第一凹槽13和所述第二凹槽14，在沉积时，所述透明导电材料也会沉积在所述第一凹槽13和所述第二凹槽14内，因此，所述数据遮蔽线12还包括沉积于所述第一凹槽13内的部分，所述像素电极11还包括沉积于所述第二凹槽14内的部分。可以知道的是，像素电极11需与所述漏极9连接以接收所述数据线6的数据信号，故在以上步骤中，还会形成过孔10，以使像素电极11与所述漏极9电性连接。
本实施例提供一种阵列基板，包括：
衬底层1，所述衬底层1上形成有公共电极层，所述公共电极层包括公共电极2；
色阻层4，所述色阻层4形成于所述公共电极层上，且所述色阻背离所述衬底层1的一侧表面开设有第一凹槽13和第二凹槽14；
数据遮蔽线层，所述数据遮蔽线层包括数据遮蔽线12，所述数据遮蔽线12形成于所述色阻上，且部分所述数据遮蔽线12位于所述第一凹槽13内；
像素电极层，所述像素电极层包括像素电极11，所述像素电极11形成于所述色阻层4上且与所述数据遮蔽线12绝缘设置，部分所述像素电极11位于所述第二凹槽14内，以与所述第一凹槽13内的所述数据遮蔽线12形成第一电容。
本实施例提供一种阵列基板，所述阵列基板的所述色阻层4上设置有第一凹槽13和第二凹槽14，所述数据遮蔽线12形成于色阻层4上且部分数据遮蔽线12位于第一凹槽13内，所述像素电极11形成于色阻层4上且部分像素电极11位于第二凹槽14内，位于第一凹槽13内的数据遮蔽线12与位于第二凹槽14内的像素电极11形成第一电容，用于解决现有技术将色阻层4制备于像素电极11和公共电极2之间，使得像素电极11和公共电极2的距离增加，导致像素电极11和公共电极2形成的第二电容的容值的下降，进而导致闪烁和串扰等显示不良问题，保证显示画面的稳定性。
根据本发明一优选实施例，将所述第一电容设置为小于所述像素电极11与所述公共电极2所形成的第二电容，能够防止所述第一电容过大导致所述第一电容和所述第二电容的充电率变低，即在原有充电时间内不能给所述第一电容和所述第二电容充至所需电量，即达不到所需电压。
根据本发明一优选实施例，所述第一凹槽13的宽度等于所述第二凹槽14的宽度，且所述第一凹槽13的深度等于所述第二凹槽14的深度，所述宽度是指所述第一凹槽13和所述第二凹槽14相互靠近的一面的一条边的长度，该面的另一条边的长度为对应凹槽的深度，可以知道的是，由电容的容值计算公式：
c＝εs/4πkd，ε为中间介质的介电常数，s为两极板的有效正对面积，π和k为常数，d为两极板之间的间距。
可知，电容的容值通常与两极板之间的有效正对面积、间距以及两极板中间介质的介电常数有关，因此在其他参数固定的情况下，增加所述数据遮蔽线12和所述像素电极11的有效正对面积即可增加所述数据遮蔽线12和所述像素电极11所形成的所述第一电容的容值，因此使所述第一凹槽13和所述第二凹槽14相互靠近一面的面积相等，即使有效正对面积最大，即可最大化增加所述电容的容值。
根据本发明一优选实施例，所述色阻层4的厚度为2至3微米，所述第一凹槽13和所述第二凹槽14的深度为0.5至2微米。可以知道的是，为了防止短路，所述第一凹槽13和所述第二凹槽14的深度不能超过所述色阻的厚度，具体的，所述第一凹槽13和所述第二凹槽14的深度为0.7微米，即所述像素电极11和所述数据遮蔽线12插入所述色阻层4的深度为0.7微米，所述色阻层4的厚度为2.3微米。
根据本发明一优选实施例，所述数据遮蔽线12与所述像素电极11同层设置且材料相同，具体的，所述数据遮蔽线12和所述像素电极11的材料包括ITO(Indium-Tin-Oxide，铟锡氧化物)、IGZO(indium gallium zinc oxide，铟镓锌氧化物)以及ITO/Ag/ITO叠层材料中的任意一个，可以知道的是，所述数据遮蔽线12和所述像素电极11的材料包括本领域常用的透明导电材料。
根据本发明一优选实施例，所述公共电极2和色阻层4之间还设置有数据线6，可以知道的是，所述数据遮蔽线12用于与所述公共电极2形成电场以使显示面板内与所述数据遮蔽线12所对应区域的液晶保持不偏转的状态，从而起到遮光的目的，则所述数据线6在所述衬底层1上的投影位于所述数据线6遮蔽线在所述衬底层1上的投影范围内，所述数据线6通常为5至10微米，具体的，所述数据线6为8微米，而所述数据遮蔽线12通常单侧超出所述数据线6两微米，具体的，当所述数据线6为8微米时，所述数据遮蔽线12为12微米。
本实施例提供一种显示面板，其包括上述实施例所示的阵列基板，可以知道的是，所述显示面板包括显示区和非显示区，所述显示区可以是用于设置显示图像的子像素的区域，所述非显示区可以是用于设置为子像素的像素驱动电路提供驱动信号的驱动单元如栅极驱动电路，以及连接驱动单元的一些线如电源线的区域。在所述非显示区内可能没有设置子像素。所述非显示区可以设置在显示区的至少一侧。所述非显示区可以至少部分地围绕显示区的周围。
非显示区可以设置在显示区的至少一侧。非显示区可以至少部分地围绕显示区的周围。
可以知道的是，所述显示区包括开口区和非开口区，所述栅极5、栅极线、漏极9、和源极8均位于非开口区内，所述像素电极11、公共电极2均位于开口区内，所述色阻层4同时覆盖了所述开口区和所述非开口区，膜层位置为本领域技术人员公知，仅做示例性说明，不做赘述。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (7)

1.一种阵列基板，其特征在于，包括：
衬底层，所述衬底层上形成有公共电极层；
色阻层，所述色阻层形成于所述公共电极层上，且所述色阻层背离所述衬底层的一侧表面开设有第一凹槽和第二凹槽；
数据遮蔽线层，包括数据遮蔽线，所述数据遮蔽线形成于所述色阻层上，且部分所述数据遮蔽线位于所述第一凹槽内；
像素电极层，包括像素电极，所述像素电极形成于所述色阻层上且与所述数据遮蔽线绝缘设置，部分所述像素电极位于所述第二凹槽内，以与所述第一凹槽内的所述数据遮蔽线形成第一电容；
所述第一凹槽的宽度等于所述第二凹槽的宽度；
所述第一凹槽的深度等于所述第二凹槽的深度；
所述色阻层的厚度为2至3微米，所述第一凹槽和所述第二凹槽的深度为0.5至2微米。
2.根据权利要求1所述的阵列基板，其特征在于，所述第一电容小于所述像素电极与所述公共电极层所形成的第二电容。
3.根据权利要求1所述的阵列基板，其特征在于，所述数据遮蔽线与所述像素电极同层设置且材料相同。
4.根据权利要求3所述的阵列基板，其特征在于，所述数据遮蔽线和所述像素电极的材料包括ITO、IGZO以及ITO/Ag/ITO叠层材料中的任意一个。
5.根据权利要求1所述的阵列基板，其特征在于，所述公共电极层和色阻层之间还设置有数据线，所述数据线在所述衬底层上的投影位于所述数据遮蔽线在所述衬底层上的投影范围内。
6.一种阵列基板的制作方法，其特征在于，包括以下步骤：
在衬底层上形成公共电极层；
在所述公共电极层上形成色阻层，并在所述色阻层背离所述衬底层的一侧表面形成第一凹槽和第二凹槽；
在所述色阻层上形成数据遮蔽线层和像素电极层，其中，部分所述数据遮蔽线层形成于所述第一凹槽内，部分所述像素电极层形成于所述第二凹槽内且与部分所述数据遮蔽线层形成第一电容；
所述第一凹槽的宽度等于所述第二凹槽的宽度；
所述第一凹槽的深度等于所述第二凹槽的深度；
所述色阻层的厚度为2至3微米，所述第一凹槽和所述第二凹槽的深度为0.5至2微米。
7.一种显示面板，其特征在于，包括如权利要求1至5任一项所述的阵列基板，或如权利要求6所述的制作方法制作的阵列基板。
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CN103676374A (zh) * 2013-12-06 2014-03-26 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN104701302A (zh) * 2015-03-18 2015-06-10 合肥京东方光电科技有限公司 阵列基板及其制作方法以及显示装置
CN105206619A (zh) * 2015-08-27 2015-12-30 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN106125436A (zh) * 2016-08-31 2016-11-16 京东方科技集团股份有限公司 一种阵列基板、显示面板及制作方法
CN107154406A (zh) * 2017-05-12 2017-09-12 京东方科技集团股份有限公司 显示基板及其制作方法和显示装置
CN111090203A (zh) * 2020-03-22 2020-05-01 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN112433414A (zh) * 2020-12-01 2021-03-02 深圳市华星光电半导体显示技术有限公司 显示面板和显示装置
CN113504680A (zh) * 2021-06-29 2021-10-15 惠科股份有限公司 阵列基板、阵列基板的制作方法和显示面板

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