CN106125436A - 一种阵列基板、显示面板及制作方法 - Google Patents

一种阵列基板、显示面板及制作方法 Download PDF

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CN106125436A
CN106125436A CN201610799410.6A CN201610799410A CN106125436A CN 106125436 A CN106125436 A CN 106125436A CN 201610799410 A CN201610799410 A CN 201610799410A CN 106125436 A CN106125436 A CN 106125436A
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electric capacity
storage electric
plane
hearth electrode
electrode
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CN106125436B (zh
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周纪登
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to PCT/CN2017/099387 priority patent/WO2018041081A1/zh
Priority to US15/781,933 priority patent/US10615181B2/en
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    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract

本发明提供了一种阵列基板、显示面板及制作方法，用以通过在像素区域周围环绕设置存储电容底电极，像素电极和存储电容底电极在第一平面上的投影部分重叠，和/或像素电极和存储电容底电极在第二平面上的投影部分重叠，其中，第一平面垂直于衬底基板所在平面且平行于栅线，第二平面垂直于衬底基板所在平面且平行于数据线，即像素电极和存储电容底电极之间形成存储电容，通过存储电容，可实现在薄膜晶体管关闭时，为像素电极提供用于显示上一帧图像的电压；又由于存储电容底电极在衬底基板上的投影面积小于现有技术中存储电容底电极在衬底基板上的投影面积，从而在不影响存储电容工作特性的情况下，提升了像素开口率。

Description

一种阵列基板、显示面板及制作方法
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板、显示面板及制作方法。
背景技术
随着薄膜晶体管(Thin Film Transistor，TFT)的液晶显示器(Liquid CrystalDisplay，LCD)的不断发展，无论从能耗方面或从画面视觉效果方面考虑，人们对显示面板的透过率的要求也在不断地提高。一般影响显示面板的透过率的因素主要有两方面，一是材料方面，主要为偏光片材料、液晶材料或彩膜(Red Green Blue，RGB)色阻材料；然而在材料已选定的前提下，只能通过提升像素的开口率的方面改进。通常影响像素开口率的因素为阵列基板上的存储电容底电极和彩膜基板上的黑矩阵。
传统的显示装置包括：阵列基板以及与阵列基板相对设置的彩膜基板；其中，参见图1a，该阵列基板包括：栅线101、存储电容底电极102、数据线103以及像素电极104。图1b为显示装置沿图1a中的A-A’的剖开图。参见图1b，该阵列基板还包括：第一基板105、与黑矩阵109对应的存储电容底电极102、位于存储电容底电极上的存储电容底电极保护层106、位于存储电容底电极保护层上的绝缘层107、与彩色滤光片108对应的像素电极104；且该彩膜基板包括：第二基板110、黑矩阵109以及彩色滤光片108。若为保证在薄膜晶体管关闭的同时，像素电极104上仍保存有用于显示上一帧图像的电压，则该阵列基板中需存有存储电容Cst，参见图1c。为确保显示装置中存有存储电容，通常将存储电容底电极的宽度H设计的比较宽，且将彩膜基板上的黑矩阵的宽度I也设计的较宽，从而导致数据线和栅线交叉形成的像素区域的开口率较低。
综上所述，传统的显示装置为保证在薄膜晶体管关闭的同时，像素电极上仍保存有用于显示上一帧图像的电压，因此将存储电容底电极设计的较宽，导致像素区域的开口率较低。
发明内容
本发明实施例提供了一种阵列基板、显示面板及制作方法，用以在像素区域处环绕设置存储电容底电极，使得像素电极和存储电容底电极的投影部分重叠，从而保证像素电极和存储电容底电极之间的存储电容，在薄膜晶体管关闭时，仍能给像素电极提供用于显示上一帧图像的电压；又由于存储电容底电极在衬底基板所在平面上的投影面积小于现有技术中存储电容底电极在衬底基板所在平面上的投影面积，将存储电容底电极设计成宽且窄的形状，相应的也减小了黑矩阵的面积，从而在不影响存储电容工作特性的情况下，提升了像素开口率。
本发明实施例提供的一种阵列基板，包括衬底基板、形成在所述衬底基板上的数据线和栅线，以及成阵列分布的像素区域，还包括：形成在所述衬底基板上的存储电容底电极和像素电极；所述像素电极和存储电容底电极形成存储电容；其中，所述存储电容底电极环绕所述像素区域设置；
所述像素电极和所述存储电容底电极在第一平面上的投影部分重叠，和/或所述像素电极和所述存储电容底电极在第二平面上的投影部分重叠，其中，所述第一平面垂直于所述衬底基板所在平面且平行于所述栅线，所述第二平面垂直于所述衬底基板所在平面且平行于所述数据线。
本发明实施例中，在像素区域处环绕设置存储电容底电极，使得像素电极和存储电容底电极在第一平面上的投影部分重叠，和/或像素电极和存储电容底电极在第二平面上的投影部分重叠，其中，第一平面垂直于衬底基板所在平面且平行于栅线，第二平面垂直于衬底基板所在平面且平行于数据线，从而保证像素电极和存储电容底电极之间的存储电容，在薄膜晶体管关闭时，仍能给像素电极提供用于显示上一帧图像的电压；又由于存储电容底电极在基板所在平面上的投影面积小于现有技术中存储电容底电极在衬底基板所在平面上的投影面积，将存储电容底电极设计成宽且窄的形状，相应的也减小了黑矩阵的面积，实现了在不影响存储电容工作特性的情况下，提升了像素开口率。
较佳地，所述像素电极和所述存储电容底电极在第一平面上的投影的重叠面积大于或等于第二预设阈值，或所述像素电极和所述存储电容底电极在第二平面上的投影的重叠面积大于或等于第二预设阈值。
本发明实施例中，通过限定像素电极和存储电容底电极在第一平面上的投影的重叠面积，从而保证像素电极和存储电容底电极之间的存储电容，在薄膜晶体管关闭时，足够给像素电极提供用于显示上一帧图像的电压。
较佳地，所述存储电容底电极在所述衬底基板所在平面上的投影与所述像素电极在所述衬底基板所在平面上的投影不重叠。
较佳地，所述阵列基板还包括：绝缘层；其中，所述绝缘层在所述像素区域处设有凹槽结构；所述像素电极位于所述绝缘层上，且覆盖所述像素区域。
本发明实施例中，通过在绝缘层中像素区域处设置凹槽结构，从而在保证像素电极和存储电容底电极之间的存储电容足够给像素电极提供用于显示上一帧图像的电压的同时，减少了形成像素电极所用的材料。
较佳地，所述凹槽结构位于所述绝缘层上，且与靠近所述存储电容底电极的所述像素区域的边缘相对应。
本发明实施例提供的一种显示面板，包括：上述的阵列基板以及彩膜基板，其中，所述彩膜基板，包括：与所述阵列基板中存储电容底电极相对设置的黑矩阵，以及与所述阵列基板中像素电极相对设置的彩色滤光片。
本发明实施例中，在像素区域处环绕设置存储电容底电极，使得像素电极和存储电容底电极的投影部分重叠，使得像素电极和存储电容底电极的投影部分重叠，从而保证像素电极和存储电容底电极之间的存储电容，在薄膜晶体管关闭时，仍能给像素电极提供用于显示上一帧图像的电压；又由于存储电容底电极在基板所在平面上的投影面积小于现有技术中存储电容底电极在基板所在平面上的投影面积，从而实现了在不影响存储电容工作特性的情况下，提升了像素开口率。
本发明实施例提供的一种阵列基板的制作方法，包括：在衬底基板上依次形成栅线、数据线，该方法还包括：
在所述衬底基板上形成绝缘层、通过构图工艺形成存储电容底电极，其中，所述存储电容底电极环绕像素区域设置；
通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第一凹槽，其中，所述第一凹槽和所述存储电容底电极在第一平面上的投影部分重叠，和/或，通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第二凹槽，其中，所述第二凹槽和所述存储电容底电极在第二平面上的投影部分重叠，其中，所述第一平面垂直于所述衬底基板所在平面且平行于所述栅线，所述第二平面垂直于所述衬底基板所在平面且平行于所述数据线；
通过构图工艺在所述像素区域形成像素电极。
本发明实施例中，在像素区域处环绕设置存储电容底电极，使得像素电极和存储电容底电极在第一平面上的投影部分重叠，和/或像素电极和存储电容底电极在第二平面上的投影部分重叠，其中，第一平面垂直于衬底基板所在平面且平行于栅线，第二平面垂直于衬底基板所在平面且平行于数据线，从而保证像素电极和存储电容底电极之间的存储电容，在薄膜晶体管关闭时，仍能给像素电极提供用于显示上一帧图像的电压；又由于存储电容底电极在基板所在平面上的投影面积小于现有技术中存储电容底电极在基板所在平面上的投影面积，从而实现了在不影响存储电容工作特性的情况下，提升了像素开口率。
较佳地，在所述衬底基板上形成绝缘层、通过构图工艺形成存储电容底电极，包括：
在所述衬底基板上形成第一绝缘层；
通过构图工艺在所述第一绝缘层中形成环绕所述像素区域设置的第三凹槽；
通过构图工艺在第三凹槽中形成存储电容底电极；
在所述存储电容底电极上形成第二绝缘层；
通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第一凹槽，包括：
通过构图工艺在所述第一绝缘层和所述第二绝缘层中对应阵列分布的像素区域中形成第一凹槽。
较佳地，所述像素电极和所述存储电容底电极在第一平面上的投影的重叠面积大于或等于第二预设阈值，或所述像素电极和所述存储电容底电极在第二平面上的投影的重叠面积大于或等于第二预设阈值。
较佳地，所述存储电容底电极在所述衬底基板所在平面上的投影与所述像素电极在所述衬底基板所在平面上的投影不重叠。
附图说明
图1a为现有技术提供的阵列基板的平面结构示意图；
图1b为现有技术提供的阵列基板沿A-A’的剖面结构示意图；
图1c为现有技术提供的像素电极和存储电极之间形成的存储电容的原理图；
图2a为本发明实施例提供的阵列基板的平面结构示意图；
图2b为本发明实施例提供的阵列基板沿A-A’的剖面结构示意图；
图2c为本发明实施例提供的阵列基板中像素电极和存储电极之间形成的存储电容的原理图；
图2d为本发明实施例提供的阵列基板的结构示意图；
图2e为本发明实施例提供的阵列基板的结构示意图；
图2f为本发明实施例提供的阵列基板的结构示意图；
图3为本发明实施例提供的显示面板的结构示意图；
图4为本发明实施例提供的一种阵列基板的制作方法的流程示意图。
具体实施方式
本发明实施例提供了一种阵列基板、显示面板及制作方法，用以通过在像素区域处环绕设置存储电容底电极，使得像素电极和存储电容底电极的投影部分重叠，从而保证像素电极和存储电容底电极之间的存储电容，在薄膜晶体管关闭时，仍能给像素电极提供用于显示上一帧图像的电压；又由于存储电容底电极在基板所在平面上的投影面积小于现有技术中存储电容底电极在基板所在平面上的投影面积，将存储电容底电极设计成宽且窄的形状，相应的也减小了黑矩阵的面积，从而在不影响存储电容工作特性的情况下，提升了像素开口率。
下面将结合本发明实施例中的附图，对本发明中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图2a，本发明实施例提供了一种阵列基板，包括衬底基板201(参见图2b)，形成在衬底基板201上的数据线202和栅线203，数据线202和栅线203交叉形成像素区域，形成在衬底基板201上的存储电容底电极204和像素电极205，所述像素电极和存储电容底电极形成存储电容；其中，所述存储电容底电极环绕所述像素区域设置，其中每个像素区域对应一个亚像素。
其中，像素电极205和存储电容底电极204在第一平面206上的投影部分重叠，和/或像素电极205和存储电容底电极204在第二平面207上的投影部分重叠，其中，所述第一平面垂直于所述衬底基板所在平面且平行于所述栅线，所述第二平面垂直于所述衬底基板所在平面且平行于所述数据线。
其中，所述存储电容底电极204在所述衬底基板201上的投影面积小于第一预设阈值；所述第一预设阈值为传统的阵列基板中的存储电容底电极在衬底基板所在平面上的投影面积；即如图2b中存储电容底电极204的宽度h小于第三预设阈值，其中，第三预设阈值为传统显示面板中阵列基板的存储电容底电极的规定宽度H，传统显示面板中存储电容底电极的规定宽度H的范围为大于或等于7微米，且小于或等于8微米。然而，在不影响存储电容工作特性的情况下，本发明实施例中存储电容底电极204的宽度h可为3微米。
本发明实施例中，存储电容底电极在衬底基板所在平面上的投影面积小于现有技术中存储电容底电极在衬底基板所在平面上的投影面积，将存储电容底电极设计成厚且窄的结构，相应的也减小了黑矩阵的面积，从而实现了在不影响存储电容工作特性的情况下，提升了像素开口率。
为便于理解像素电极205和存储电容底电极204的位置关系，下面将结合图2b即图2a中的阵列基板沿A-A’的剖开图，介绍该阵列基板的结构。
所述阵列基板还包括：绝缘层；其中，所述绝缘层在所述像素区域处设有凹槽结构；所述像素电极位于所述绝缘层上，且覆盖所述像素区域。其中，所述绝缘层既可以与存储电容底电极同层设置，也可以在存储电容底电极之上设置。
其中，所述凹槽结构位于所述像素区域靠近存储电容底电极侧的边缘处。由于像素电极与存储电容底电极的水平距离越近，存储电容的损失越小，进一步减少了能量的损失，提升了资源的利用率。
参见图2b，具体地，本发明实施例提供的阵列基板的绝缘层可以包括：存储电容底电极保护层208、第二绝缘层209以及与存储电容底电极204同层设置的第一绝缘层210；其中，所述第一绝缘层210在所述像素区域靠近存储电容底电极侧的边缘处设有凹槽结构；所述像素电极205位于第一绝缘层210上，且覆盖像素区域。
本发明实施例中，通过本发明实施例中阵列基板的设计，如图2c所示，保证了像素电极205和存储电容底电极204之间的存储电容Cst，在薄膜晶体管关闭时，仍能给像素电极提供用于显示上一帧图像的电压。
此外，像素电极205的形状并不局限于图2b中的形状，像素电极的形状还可以为图2d中的形状。即只要满足像素电极205和存储电容底电极204在第一平面206上的投影的重叠部分506的面积大于或等于第二预设阈值，或像素电极205和存储电容底电极204在第二平面207上的投影的重叠面积大于或等于第二预设阈值的像素电极均可适用于本发明实施例提供的阵列基板，其中，第一平面垂直于衬底基板所在平面且平行于栅线，第二平面垂直于衬底基板所在平面且平行于数据线。根据电容公式可知，平板电容器的两极板正对面积越大，则平板电容器的电容值越大。像素电极与存储电容底电极之间的存储电容与投影的重叠部分的面积正相关，因此，当投影的重叠部分的面积大于或等于第二预设阈值时，像素电极与存储电容底电极之间的存储电容足够为像素电极提供用于显示上一帧图像的电压。也就是说，第二预设阈值为当像素电极与存储电容底电极之间的存储电容足够为像素电极提供用于显示上一帧图像的电压时，像素电极与存储电容底电极投影的重叠面积。
根据图2d、图2b可知，图2d中像素电极在衬底基板上的投影面积比图2b中像素电极的投影面积大，即像素电极的边界超过了像素区域。
优选地，存储电容底电极204在衬底基板201所在平面上的投影与像素电极205在衬底基板201所在平面上的投影不重叠时，能够保证在薄膜晶体管关闭时，像素电极和存储电容底电极之间的存储电容能为像素电极提供用于显示上一帧图像的电压，同时能够减少像素电极材料的使用量。
优选地，将像素电极205设置为凹槽结构，保证像素电极在第一平面206，和/或，第二平面207上的投影部分和存储电容底电极部分重合，能够保证在薄膜晶体管关闭时，像素电极和存储电容底电极之间的存储电容能为像素电极提供用于显示上一帧图像的电压。
另外，本发明实施例并不局限于图2a、图2b所示的阵列基板，当阵列基板包括多个由数据线202和栅线203交叉形成的像素区域时，参见图2e，本发明实施例提供的阵列基板包括，形成在衬底基板201上的存储电容底电极204和像素电极205，其中，像素电极205和存储电容底电极204在第一平面206上的投影部分重叠，和像素电极205和存储电容底电极204在第二平面207上的投影部分重叠。参见图2f，像素电极205和存储电容底电极204在第一平面206上的投影部分重叠，或像素电极205和存储电容底电极204在第二平面207上的投影部分重叠。
参见图3，本发明实施例提供的一种显示面板，包括：上述的阵列基板310以及彩膜基板320，其中，所述彩膜基板320，包括：与所述阵列基板中存储电容底电极204相对设置的黑矩阵321，以及与所述阵列基板中像素电极205相对设置的彩色滤光片322，衬底基板323。
其中，由于黑矩阵321与存储电容底电极204为相对设置的，且存储电容底电极204在衬底基板201上的投影面积小于传统的阵列基板中的存储电容底电极在衬底基板所在平面上的投影面积，因此，黑矩阵321在衬底基板323上的投影面积小于传统的彩膜基板中的黑矩阵在衬底基板所在平面上的投影面积，即黑矩阵321的宽度i也将小于传统显示面板中彩膜基板的黑矩阵109规定的宽度I。
此外，本发明实施例提供的另一种显示面板，该显示面板的阵列基板包括：第一衬底基板、交叉设置在所述衬底基板上的数据线和栅线，成阵列分布的像素区域，形成在所述衬底基板上的存储电容底电极和像素电极，以及与存储电容底电极相对设置的黑矩阵。此时，所述彩膜基板包括：第二衬底基板、以及与所述阵列基板中像素电极相对设置的彩色滤光片。也就是说，黑矩阵既可以设置在彩膜基板上，也可以设置在阵列基板上。
参见图4，本发明实施例提供的一种阵列基板的制作方法，包括：
S401、在衬底基板上通过构图工艺依次形成栅线、数据线；
S402、在所述衬底基板上形成绝缘层、通过构图工艺形成存储电容底电极，其中，所述存储电容底电极环绕像素区域设置；
S403、通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第一凹槽，和/或，通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第二凹槽；
S404、通过构图工艺在所述像素区域形成像素电极。
其中，所述第一凹槽和所述存储电容底电极在第一平面上的投影部分重叠，所述第二凹槽和所述存储电容底电极在第二平面上的投影部分重叠；所述第一平面垂直于所述衬底基板所在平面且平行于所述栅线，所述第二平面垂直于所述衬底基板所在平面且平行于所述数据线。
其中，所述存储电容底电极在所述衬底基板上的投影面积小于第一预设阈值，所示第一预设阈值为，小于或者等于传统的阵列基板中的存储电容底电极在衬底基板所在平面上的投影面积的预设值。
具体地，步骤S402中在所述衬底基板上形成绝缘层、通过构图工艺形成存储电容底电极，具体包括如下步骤：
在所述衬底基板上形成第一绝缘层；
通过构图工艺在所述第一绝缘层中形成环绕所述像素区域设置的第三凹槽；
通过构图工艺在第三凹槽中形成存储电容底电极；
在所述存储电容底电极上形成第二绝缘层。
具体地，通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第一凹槽，和/或，通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第二凹槽，包括：
通过构图工艺在所述第一绝缘层和所述第二绝缘层中对应阵列分布的像素区域中形成第一凹槽，和/或，通过构图工艺在所述第一绝缘层和所述第二绝缘层中对应阵列分布的像素区域中形成第二凹槽。
具体地，在步骤S402之后，在步骤S403之前，该方法还包括：
在所述第二绝缘层上依次形成存储电容底电极保护层；
在所述存储电容底电极保护层上形成。
其中，所述像素电极和所述存储电容底电极在第一平面上的投影的重叠面积大于或等于第二预设阈值，和/或，所述像素电极和所述存储电容底电极在第二平面上的投影的重叠面积大于或等于第二预设阈值。由于像素电极和存储电容底电极投影的重叠面积与像素电极和存储电容底电极之间的存储电容正相关，因此当上述重叠面积等于第二预设阈值时，像素电极和存储电容底电极之间的存储电容，能够在薄膜晶体管关闭时，刚好能够给像素电极提供用于显示上一帧图像的电压。
其中，所述存储电容底电极在所述衬底基板所在平面上的投影与所述像素电极在所述衬底基板所在平面上的投影不重叠。
综上所述，本发明实施例提供了一种阵列基板、显示面板及制作方法，用以通过在像素区域处环绕设置存储电容底电极，使得像素电极和存储电容底电极在第一平面上的投影部分重叠，和/或像素电极和存储电容底电极在第二平面上的投影部分重叠，其中，第一平面垂直于衬底基板所在平面且平行于栅线，第二平面垂直于衬底基板所在平面且平行于数据线，从而保证像素电极和存储电容底电极之间的存储电容，在薄膜晶体管关闭时，能给像素电极提供用于显示上一帧图像的电压；又由于存储电容底电极在基板所在平面上的投影面积小于现有技术中存储电容底电极在衬底基板所在平面上的投影面积，从而实现了在不影响存储电容工作特性的情况下，提升了像素开口率。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

1.一种阵列基板，包括衬底基板、交叉设置在所述衬底基板上的数据线和栅线，以及成阵列分布的像素区域，其特征在于，还包括：形成在所述衬底基板上的存储电容底电极和像素电极，所述像素电极和存储电容底电极形成存储电容；其中，所述存储电容底电极环绕所述像素区域设置；
所述像素电极和所述存储电容底电极在第一平面上的投影部分重叠，和/或，所述像素电极和所述存储电容底电极在第二平面上的投影部分重叠，其中，所述第一平面垂直于所述衬底基板所在平面且平行于所述栅线，所述第二平面垂直于所述衬底基板所在平面且平行于所述数据线。
2.根据权利要求1所述的阵列基板，其特征在于，所述像素电极和所述存储电容底电极在第一平面上的投影的重叠面积大于或等于第二预设阈值，或所述像素电极和所述存储电容底电极在第二平面上的投影的重叠面积大于或等于第二预设阈值。
3.根据权利要求1所述的阵列基板，其特征在于，所述存储电容底电极在所述衬底基板所在平面上的投影与所述像素电极在所述衬底基板所在平面上的投影不重叠。
4.根据权利要求1-3任一项所述的阵列基板，其特征在于，所述阵列基板还包括：绝缘层；其中，所述绝缘层在所述像素区域处设有凹槽结构；所述像素电极位于所述绝缘层上，且覆盖所述像素区域。
5.根据权利要求4所述的阵列基板，其特征在于，所述凹槽结构位于所述绝缘层上，且与靠近所述存储电容底电极的所述像素区域的边缘相对应。
6.一种显示面板，其特征在于，包括：权利要求1～5任一项所述的阵列基板以及彩膜基板，其中，所述彩膜基板包括：与所述阵列基板中存储电容底电极相对设置的黑矩阵，以及与所述阵列基板中像素电极相对设置的彩色滤光片。
7.一种阵列基板的制作方法，包括：在衬底基板上通过构图工艺依次形成栅线、数据线，其特征在于，该方法还包括：
在所述衬底基板上形成绝缘层、通过构图工艺形成存储电容底电极，其中，所述存储电容底电极环绕像素区域设置；
通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第一凹槽，其中，所述第一凹槽和所述存储电容底电极在第一平面上的投影部分重叠，和/或，通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第二凹槽，其中，所述第二凹槽和所述存储电容底电极在第二平面上的投影部分重叠，其中，所述第一平面垂直于所述衬底基板所在平面且平行于所述栅线，所述第二平面垂直于所述衬底基板所在平面且平行于所述数据线；
通过构图工艺在所述像素区域形成像素电极。
8.根据权利要求7所述的制作方法，其特征在于，在所述衬底基板上形成绝缘层、通过构图工艺形成存储电容底电极，包括：
在所述衬底基板上形成第一绝缘层；
通过构图工艺在所述第一绝缘层中形成环绕所述像素区域设置的第三凹槽；
通过构图工艺在第三凹槽中形成存储电容底电极；
在所述存储电容底电极上形成第二绝缘层；
通过构图工艺在所述绝缘层中对应阵列分布的像素区域中形成第一凹槽，包括：
通过构图工艺在所述第一绝缘层和所述第二绝缘层中对应阵列分布的像素区域中形成第一凹槽。
9.根据权利要求7所述的制作方法，其特征在于，所述像素电极和所述存储电容底电极在第一平面上的投影的重叠面积大于或等于第二预设阈值，或所述像素电极和所述存储电容底电极在第二平面上的投影的重叠面积大于或等于第二预设阈值。
10.根据权利要求7所述的制作方法，其特征在于，所述存储电容底电极在所述衬底基板所在平面上的投影与所述像素电极在所述衬底基板所在平面上的投影不重叠。
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