WO2022127396A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022127396A1
WO2022127396A1 PCT/CN2021/127038 CN2021127038W WO2022127396A1 WO 2022127396 A1 WO2022127396 A1 WO 2022127396A1 CN 2021127038 W CN2021127038 W CN 2021127038W WO 2022127396 A1 WO2022127396 A1 WO 2022127396A1
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Prior art keywords
auxiliary electrode
electrode
thin film
photoresist
film transistor
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PCT/CN2021/127038
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English (en)
French (fr)
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WO2022127396A9 (zh
Inventor
罗皓
吴博
韦东梅
邓银
张正东
李瑶
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority claimed from CN202011500714.0A external-priority patent/CN114647124A/zh
Priority claimed from CN202110710158.8A external-priority patent/CN115598894A/zh
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112021004328.5T priority Critical patent/DE112021004328T5/de
Priority to US17/915,173 priority patent/US20230123019A1/en
Publication of WO2022127396A1 publication Critical patent/WO2022127396A1/zh
Publication of WO2022127396A9 publication Critical patent/WO2022127396A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G02F1/16766—Electrodes for active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1685—Operation of cells; Circuit arrangements affecting the entire cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present disclosure belongs to the field of display technology, and in particular relates to a display substrate, a preparation method thereof, and a display device.
  • Electronic paper is a new type of display device, which is mainly used in electronic labels, billboards and electronic readers.
  • the display effect of the electronic paper is close to that of natural paper, which can reduce visual fatigue during reading.
  • electronic paper may generally include: a display substrate and a cover plate disposed opposite to each other, and an electrophoretic layer located between the display substrate and the cover plate.
  • the display substrate has a plurality of pixels arranged in an array, and each pixel may include: a pixel electrode, and an auxiliary electrode provided insulated from the pixel electrode.
  • the pixel electrode and the auxiliary electrode can form a storage capacitor during display, so as to maintain the stability of the voltage loaded on the pixel electrode.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate, a preparation method thereof, and a display device.
  • Embodiments of the present disclosure provide a method for fabricating a display substrate, the display substrate having a plurality of pixels, including:
  • a base substrate is provided, and pixels are formed on the base substrate; wherein,
  • Forming the pixel includes:
  • first conductive film on the base substrate, and patterning the first conductive film to form a gate electrode and a first auxiliary electrode of a thin film transistor;
  • a second conductive film and a first photoresist layer are formed in sequence, and masks with different transmittance regions are used to cover the first photoresist
  • the layer is exposed for a predetermined time to form the source and drain electrodes of the thin film transistor, and the second auxiliary electrode, wherein the orthographic projection of the first auxiliary electrode and the second auxiliary electrode on the base substrate overlaps, to form a first storage capacitor;
  • a pixel electrode is formed on the side of the second interlayer insulating layer away from the base substrate; wherein, the pixel electrode passes through a second via hole passing through the second interlayer insulating layer and the drain of the thin film transistor.
  • the pixel electrode is electrically connected to the first auxiliary electrode through a first via hole passing through the first interlayer insulating layer and the second interlayer insulating layer, and the first auxiliary electrode is connected to the first auxiliary electrode.
  • the orthographic projections of the pixel electrodes on the base substrate are at least partially overlapped to form a second storage capacitor.
  • the mask with different transmittance regions includes a completely transparent region, a non-light-transmitting region, and a plurality of partially transparent regions; the first interlayer insulating layer facing away from the base substrate On one side, a second conductive film and a first photoresist layer are formed in turn, and the first photoresist layer is exposed for a predetermined time by using the mask with different transmittance regions to form the source electrode and the first photoresist layer of the thin film transistor.
  • the drain, and the steps of the second auxiliary electrode including:
  • the photoresist in the non-reserved area of the photoresist in the first photoresist layer is removed, and the source electrode and the drain electrode of the thin film transistor and the second auxiliary electrode are formed by etching.
  • the plurality of partially transparent regions include a first partially transparent region and a second partially transparent region, and the light transmittance of the first partially transparent region is greater than that of the second partially transparent region Rate;
  • the second conductive film and the first photoresist layer are sequentially formed on the side of the first interlayer insulating layer away from the base substrate , using masks of different transmittance regions to expose the first photoresist layer, and controlling the exposure time according to the operating frequency band requirements of the pixels, forming the source and drain electrodes of the thin film transistor, and the second auxiliary electrode step ,include:
  • a second conductive film and a first photoresist layer are formed in sequence;
  • the first photoresist layer is exposed using the masks of the different transmittance regions, and the exposure time is controlled to be T1, so that the first photoresist layer and the completely transparent region are in the same
  • the area where the projections overlap on the base substrate is the photoresist non-reserved area, and the remaining areas are the photoresist reserved area;
  • the second conductive film is etched to form the source and drain electrodes of the thin film transistor and the second auxiliary electrode, and the remaining photoresist is removed; the source and drain electrodes of the thin film transistor are The length is the first distance L1; the area of the second auxiliary electrode is the first area S1;
  • the second conductive film and the first photoresist layer are sequentially formed on the side of the first interlayer insulating layer away from the base substrate , using masks with different transmittance regions to expose the first photoresist layer, and control the exposure time according to the operating frequency band requirements of the pixels to form the source and drain electrodes of the thin film transistor, and the second auxiliary electrode. steps, including:
  • a second conductive film and a first photoresist layer are formed in sequence;
  • the first photoresist layer is exposed using the masks of the different transmittance regions, and the exposure time is controlled to be T2, so that the first photoresist layer and the completely transparent region and the first photoresist layer
  • the area where a part of the light-transmitting area is projected and overlapped on the base substrate is the photoresist non-reserved area, and the rest area is the photoresist reserved area;
  • the second conductive film is etched to form the source and drain electrodes of the thin film transistor and the second auxiliary electrode, and the remaining photoresist is removed; the source and drain electrodes of the thin film transistor are The length is the second distance L2; the area of the second auxiliary electrode is the second area S2;
  • the second conductive film and the first photoresist layer are sequentially formed on the side of the first interlayer insulating layer away from the base substrate , using masks of different transmittance regions to expose the first photoresist layer, and controlling the exposure time according to the operating frequency band requirements of the pixels, forming the source and drain electrodes of the thin film transistor, and the second auxiliary electrode pattern steps, including:
  • a second conductive film and a first photoresist layer are formed in sequence;
  • the first photoresist layer is exposed using the masks of the different transmittance regions, and the exposure time is controlled to be T3, so that the first photoresist layer is connected to the completely transparent region, the first photoresist layer and the first photoresist layer.
  • the area where a part of the light-transmitting area and the second part of the light-transmitting area are projected and overlapped on the base substrate is the photoresist non-reserved area, and the rest area is the photoresist reserved area;
  • the second conductive film is etched to form the source and drain electrodes of the thin film transistor and the second auxiliary electrode, and the remaining photoresist is removed; the source and drain electrodes of the thin film transistor are The length is the third distance L3; the area of the second auxiliary electrode is the third area S3;
  • the maximum value of the first preset frequency band is smaller than the minimum value of the second preset frequency band
  • the maximum value of the second preset frequency band is smaller than the minimum value of the third preset frequency band; T1 ⁇ T2 ⁇ T3; L3 ⁇ L2 ⁇ L1; S3 ⁇ S2 ⁇ S1.
  • the gate of the thin film transistor is also formed.
  • the second auxiliary electrodes located in the same column of pixels are connected to the same auxiliary electrode line, and are configured to apply a common voltage signal.
  • a second conductive film and a first photoresist layer are formed in sequence, and masks with different transmittance regions are used to A photoresist layer is exposed, and the exposure time is controlled according to the requirements of the operating frequency band of the pixel, and before the steps of forming the source and drain electrodes of the thin film transistor, and the second auxiliary electrode, the steps further include:
  • the active layer of the thin film transistor is formed on the side of the first interlayer insulating layer away from the base substrate.
  • a second conductive film and a first photoresist layer are formed in sequence, and masks with different transmittance regions are used to A photoresist layer is exposed, and the exposure time is controlled according to the operating frequency band requirements of the pixel to form the source and drain electrodes of the thin film transistor, and the second auxiliary electrode, and also include:
  • a data line and an auxiliary electrode line are formed, and the data line is electrically connected with the source electrode of the thin film transistor; the auxiliary electrode line is connected with the second auxiliary electrode.
  • the data lines are parallel or substantially parallel to the extending direction of the auxiliary electrode lines.
  • the pixel includes two thin film transistors connected in series.
  • An embodiment of the present disclosure provides a display substrate, the display substrate has a plurality of pixels, and in at least one pixel, the display substrate includes:
  • the thin film transistor located on the base substrate, the thin film transistor comprising a gate electrode, a source electrode and a drain electrode;
  • the first auxiliary electrode, the second auxiliary electrode and the pixel electrode are sequentially arranged on the base substrate, and the orthographic projection of the first auxiliary electrode, the second auxiliary electrode and the pixel electrode on the base substrate is at least partially overlapping;
  • first interlayer insulating layer located between the layers where the first auxiliary electrode and the second auxiliary electrode are located, so as to insulate the first auxiliary electrode and the second auxiliary electrode;
  • a second interlayer insulating layer is located between the second auxiliary electrode and the layer where the pixel electrode is located, so as to insulate the first auxiliary electrode and the pixel electrode;
  • the working frequency band of the pixel is the first preset frequency band
  • the length of the source electrode and the drain electrode of the thin film transistor is the first distance L1
  • the area of the second auxiliary electrode is the first area S1;
  • the length of the source electrode and the drain electrode of the thin film transistor is the second distance L2; the area of the second auxiliary electrode is the second area S2;
  • the length of the source electrode and the drain electrode of the thin film transistor is the first distance L3; the area of the second auxiliary electrode is the first area S3;
  • the maximum value of the first preset frequency band is smaller than the minimum value of the second preset frequency band, and the maximum value of the second preset frequency band is smaller than the minimum value of the third preset frequency band; L3 ⁇ L2 ⁇ L1; S3 ⁇ S2 ⁇ S1.
  • the second auxiliary electrodes located in the same column of pixels are connected to the same auxiliary electrode line, and are configured to apply a common voltage signal.
  • the first auxiliary electrode and the gate electrode of the thin film transistor are arranged in the same layer and have the same material.
  • the data line, the auxiliary electrode line and the second auxiliary electrode are arranged in the same layer and have the same material; and the data line and the source electrode of the thin film transistor are electrically connected. connected; the auxiliary electrode line is connected with the second auxiliary electrode.
  • the data lines are parallel or substantially parallel to the extending direction of the auxiliary electrode lines.
  • the pixel includes two thin film transistors connected in series.
  • Embodiments of the present disclosure provide a display device including any of the above-mentioned display substrates.
  • the display device is an electronic paper display device, and the electronic paper display device further includes a cover plate disposed opposite to the display substrate, and an electrophoretic layer located between the display substrate and the cover plate. .
  • FIG. 1 is a schematic diagram of a film layer structure in one pixel of a display substrate provided by the related art.
  • FIG. 2 is a schematic top view of the display substrate shown in FIG. 1 .
  • FIG. 3 is a schematic diagram of a film layer structure in one pixel of a display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic top view of the display substrate shown in FIG. 3 .
  • FIG. 5 is a top view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a cross-sectional view at D-D' of the display substrate shown in FIG. 5 .
  • FIG. 7 is a top view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is a top view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view of another display device provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of exposure using masks of different precisions when the pixel is in the operating frequency band and the first preset frequency band in the manufacturing method of the display substrate according to the embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of exposure using masks of different precisions when the pixel is in the second preset frequency band in the manufacturing method of the display substrate according to the embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of exposure using masks of different precisions when a pixel is in a third preset frequency band in a manufacturing method of a display substrate according to an embodiment of the present disclosure.
  • the display substrate provided in the embodiments of the present disclosure can be used in products that do not require backlight, such as total reflection and electronic paper.
  • the pixel electrodes in the display substrate and The common electrode can be made of non-transparent material.
  • FIG. 1 is a schematic diagram of a film layer structure in one pixel of a display substrate provided by the related art.
  • a display substrate may include: a base substrate 01 ; a first conductive pattern 02 , a first interlayer insulating layer disposed on the base substrate 01 and stacked in a direction away from the base substrate 01 Layer 03 , the active layer 04 of the thin film transistor, the second conductive pattern 05 , the second interlayer insulating layer 06 and the pixel electrode 07 .
  • the first conductive pattern may include: the gate electrode 021 and the first auxiliary electrode 022 of the thin film transistor
  • the second conductive pattern 05 may include: the source electrode 051a and the drain electrode 051b of the thin film transistor and the second auxiliary electrode 052 .
  • the second auxiliary electrode 052 is electrically connected to the drain electrode 051b of the thin film transistor
  • the second auxiliary electrode 052 is electrically connected to the pixel electrode 07 through a via hole on the second interlayer insulating layer 06 .
  • FIG. 2 is a schematic top view of the display substrate shown in FIG. 1 .
  • the orthographic projection of the first auxiliary electrode 022 on the base substrate 01 and the orthographic projection of the second auxiliary electrode 052 on the base substrate 01 have an overlapping area A.
  • the second auxiliary electrode 052 Since the second auxiliary electrode 052 is connected to the pixel electrode 07 through the via hole on the second interlayer insulating layer 06, when the electronic paper prepared by the display substrate is used for display, the voltage loaded on the second auxiliary electrode 052 is The voltage applied to the pixel electrode 07 is the same as that of the pixel electrode, that is, the second auxiliary electrode 052 is equivalent to the pixel electrode. In this way, when the electronic paper prepared by the display substrate is used for display, the first auxiliary electrode 022 and the second auxiliary electrode 052 can form a storage capacitor Cst' to maintain the stability of the voltage loaded on the pixel electrode 07. The storage capacitor Cst The larger the capacitance value of ', the better the effect of maintaining the stability of the voltage loaded on the pixel electrode 07.
  • FIG. 3 is a schematic diagram of a film layer structure in one pixel of a display substrate according to an embodiment of the present disclosure.
  • the display substrate has a plurality of pixels arranged in an array.
  • the display substrate includes a base substrate 100 , a pixel electrode 200 and a first auxiliary electrode 300 arranged in sequence along the direction away from the base substrate 100 . and the second auxiliary electrode 400 .
  • the display substrate further includes: a first interlayer insulating layer 900 is arranged between the layers where the first auxiliary electrode 300 and the second auxiliary electrode 400 are located, and a second interlayer is arranged between the second auxiliary electrode 400 and the pixel electrode 200 Insulating layer 1000.
  • the pixel electrode 200 is electrically connected to the first auxiliary electrode 300 through a first via hole penetrating the first interlayer insulating layer 900 and the second interlayer insulating layer 1000 .
  • FIG. 4 is a schematic top view of the display substrate shown in FIG. 3 .
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 has an overlap region B with the orthographic projection of the pixel electrode 200 on the substrate 100 , and also exists with the orthographic projection of the first auxiliary electrode 300 on the substrate 100 Overlap area C.
  • the first auxiliary electrode 300 is electrically connected to the pixel electrode 200 , when the display substrate performs display, the voltage applied to the first auxiliary electrode 300 is the same as the voltage applied to the pixel electrode 200 , and both are pixel voltages. That is, the first auxiliary electrode 300 also corresponds to the pixel electrode 200 . In this way, when the display substrate performs display, the first storage capacitor Cst1 may be formed between the first auxiliary electrode 300 and the second auxiliary electrode 400 , and the second storage capacitor Cst2 may be formed between the pixel electrode 200 and the second auxiliary electrode 400 .
  • the second auxiliary electrode 400 is located between the pixel electrode 200 and the first auxiliary electrode 300, the first storage capacitor Cst1 formed by the second auxiliary electrode 400 and the first auxiliary electrode 300, and the second auxiliary electrode 400 and the pixel
  • the second storage capacitor Cst2 formed by the electrode 200 is connected in parallel.
  • the capacitance value of the total storage capacitor in the display substrate 000 is the sum of the capacitance value of the first storage capacitor Cst1 and the capacitance value of the second storage capacitor Cst1. Therefore, the capacitance value of the total storage capacitor in the display substrate 000 is relatively large.
  • the thickness of the first interlayer insulating layer 03 between the first auxiliary electrode 022 and the second auxiliary electrode 052 may be 4000 angstroms, and the material of the first interlayer insulating layer 03 may include: silicon nitride, whose relative dielectric constant is 6.5.
  • the capacitance value Ci' of the storage capacitor Cst' can be calculated as:
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 200 on the substrate 100 .
  • the area of B is also S
  • the area of the overlapping region C between the orthographic projection of the second auxiliary electrode 400 on the substrate 100 and the orthographic projection of the first auxiliary electrode 300 on the substrate 100 is also S.
  • the capacitance value of the first storage capacitor Cst1 is Ci 1 It is equal to the capacitance value Ci' of the storage capacitor Cst' in the related art.
  • the thickness of the insulating layer between the second auxiliary electrode 400 and the pixel electrode 200 may range from 2000 to 6000 angstroms.
  • the insulating layer is made of the same material as the first interlayer insulating layer 03 and has a relative permittivity of 6.5.
  • the maximum value Ci 2 of the capacitance value of the second storage capacitor Cst2, max is:
  • the range of the capacitance value Ci of the total storage capacitance in the display substrate 000 is:
  • the capacitance value Ci of the total storage capacitor in the display substrate 000 provided by the embodiment of the present application can be increased by 67% to 192%.
  • the first auxiliary electrode 300 in the display substrate in the embodiment of the present disclosure is electrically connected to the pixel electrode 200 , when the electronic paper using the display substrate is used for display, the load on the first auxiliary electrode 300 is loaded.
  • the voltage of which is the same as the voltage applied to the pixel electrode 200 , is the pixel voltage, that is, the first auxiliary electrode 300 is also equivalent to the pixel electrode 200 .
  • the first auxiliary electrode 300 and the second auxiliary electrode 400 can form the first storage capacitor Cst1
  • the pixel electrode 200 and the second auxiliary electrode 400 can form the second storage capacitor Cst2.
  • the first storage capacitor Cst1 and the second storage capacitor Cst2 are connected in parallel, and the total storage capacitor value in the display substrate is the sum of the capacitance value of the first storage capacitor Cst1 and the capacitance value of the second storage capacitor Cst2.
  • the electronic paper provided by the embodiments of the present disclosure increases the capacitance value of the storage capacitor without changing the PPI of the electronic paper, improves the stability of the voltage loaded on the pixel electrode 200, and further improves the performance of the electronic paper. The display effect of the electronic paper is obtained.
  • FIG. 5 is a top view of another display substrate provided by an embodiment of the present disclosure
  • FIG. 6 is a cross-sectional view of the display substrate shown in FIG. 5 at DD'
  • the pixel of the display substrate may further include: a thin film transistor 500 (English: Thin-film transistor; TFT for short), and the drain electrode of the thin film transistor 500 is electrically connected to the pixel electrode 200 .
  • a thin film transistor 500 English: Thin-film transistor; TFT for short
  • the source electrode 501a and the drain electrode 501b of the thin film transistor may be disposed in the same layer as the second auxiliary electrode 400 and use the same material. That is, the source electrode 501a and the drain electrode 501b of the thin film transistor can be formed with the second auxiliary electrode 400 through a single patterning process.
  • the source and drain electrodes 501 of the thin film transistor can also be provided in the same layer as the first auxiliary electrode 300 . That is, the source and drain electrodes 501 of the thin film transistor and the first auxiliary electrode 300 can be prepared and formed by one patterning process. In this way, the manufacturing process of the display substrate can be simplified, and the manufacturing difficulty and manufacturing cost of the display substrate can be reduced.
  • FIG. 5 schematically illustrates an example in which the source electrode 501 a and the drain electrode 501 b of the thin film transistor and the second auxiliary electrode 400 are arranged in the same layer and are made of the same material.
  • the second auxiliary electrode 400 can be multiplexed as a common electrode in the pixels, and in this way, the film thickness of the display substrate can be reduced, which is helpful to realize the lightness and thinness of the display substrate.
  • the second auxiliary electrodes 400 located in the same column of pixels are connected to the same auxiliary electrode line, and are configured to apply a common voltage signal.
  • the gate electrode 502 in the thin film transistor 500 may be disposed in the same layer as the first auxiliary electrode 300 and made of the same material; the source and drain electrodes 501 in the thin film transistor 500 may be disposed in the same layer as the second auxiliary electrode 400 , and Materials are the same.
  • the gate electrode 502 of the thin film transistor and the first auxiliary electrode 300 can be formed through a single patterning process, and the source and drain electrodes 501 of the thin film transistor can be formed with the second auxiliary electrode 400 through a single patterning process. In this way, the manufacturing process of the display substrate can be further simplified, and the manufacturing difficulty and manufacturing cost of the display substrate 000 can be further reduced.
  • the active layer 503 of the thin film transistor overlaps with the source and drain 501, and the source and drain 501 are located on the side of the active layer 503 away from the substrate 100, and the gate 502 is located on the active layer 503 close to the substrate. 100 side. That is, the thin film transistor 500 is a bottom gate thin film transistor. In other possible implementation manners, the thin film transistor 500 may also be a top-gate thin film transistor, which is not limited in this embodiment of the present disclosure.
  • the display substrate has a plurality of pixel regions 000a arranged in an array, and each pixel region 000a is provided with two thin film transistors 500 connected in series.
  • Each of the two thin film transistors 500 may include a source electrode 501a and a drain electrode 501b.
  • the drain electrode 501b of one thin film transistor 500 is electrically connected to the source electrode 501a of the other thin film transistor 500, so that the two thin film transistors 500 are connected in series. In this way, the leakage current in the thin film transistor 500 can be reduced, and the influence on the pixel voltage loaded on the pixel electrode 200 can be reduced.
  • only one thin film transistor 500 may be included in each pixel.
  • the channel region E of the active layer 503 in each thin film transistor 500 is an elongated channel region.
  • the channel region E of the active layer pattern 503 refers to the region in the active layer 503 between the region where the active layer 503 contacts the source electrode and the region where the active layer 503 contacts the drain electrode.
  • the width of the channel region E may range from 20 to 40 microns. In this way, the charging rate requirement of the display substrate 000 can be satisfied.
  • the operating frequency requirements of the pixels are also different.
  • the channel width to length ratio requirements of 500 are also different.
  • a lower operating frequency (10-20HZ) is required; when it is applied to e-books that support handwriting, there is no delay in handwriting due to the need for handwriting.
  • a higher operating frequency ( ⁇ 120HZ) is required.
  • the display substrate in the embodiments of the present disclosure can be applied to display devices such as reflective display and reflective electronic paper.
  • the length of the source electrode 501a and the drain electrode 501b of the thin film transistor in the pixel is L1
  • the area of the second auxiliary electrode 400 is S1
  • the length of the source electrode 501a and the drain electrode 501b of the thin film transistor in the pixel is L2
  • the area of the second auxiliary electrode 400 is S2.
  • the operating frequency band of the pixel is the third preset frequency band
  • the length of the source electrode 501 a and the drain electrode 501 b of the thin film transistor in the pixel is L3
  • the area of the second auxiliary electrode 400 is S3 .
  • the maximum value of the first preset frequency band is smaller than the minimum value of the second preset frequency band
  • the maximum value of the second preset frequency band is smaller than the minimum value of the third preset frequency band; L3 ⁇ L2 ⁇ L1; S3 ⁇ S2 ⁇ S1.
  • the length of the source electrode 501a and the drain electrode 501b of the thin film transistor is the channel width of the thin film transistor 500, and the greater the length of the source electrode 501a and the drain electrode 501b of the thin film transistor, the greater the channel width to length ratio. . It should be noted that, how to realize the design of the channel width-to-length ratio and the storage capacitance of the thin film transistor 500 in the pixels of different working frequency bands, see the following method for manufacturing the display substrate.
  • the display substrate may further include: a plurality of gate lines 600 , a plurality of data lines 700 , and a plurality of auxiliary electrode lines 800 .
  • the extension directions of the gate lines 600 and the data lines 700 intersect, for example, the extension directions of the two are perpendicular to each other.
  • the extension directions of the auxiliary electrode lines 800 and the data lines 700 are substantially the same or the same.
  • the gate electrodes 502 of the thin film transistors 500 located in the same row of pixels are connected to the same gate line 600
  • the source electrodes 501a of the thin film transistors 500 located in the same column of pixels are connected to the same data line 700
  • the pixels located in the same column of pixels are connected to the same data line 700.
  • the second auxiliary electrode 400 is connected to the same auxiliary electrode line 800 .
  • the gate line 600, the gate electrode 502 of the thin film transistor, and the first auxiliary electrode 300 are provided in the same layer and have the same material. That is, the gate line 600, the gate electrode 502 and the first auxiliary electrode 300 are formed through one patterning process.
  • the data line 700 , the auxiliary electrode line 800 , the source and drain electrodes 501 and the second auxiliary electrode 400 are arranged in the same layer and made of the same material. That is, the data line 700 , the auxiliary electrode line 800 , the source and drain electrodes 501 and the second auxiliary electrode 400 are formed by one patterning process.
  • the extension direction of the gate line 600 intersects with the extension direction of the data line 700
  • the extension direction of the gate line 600 intersects with the extension direction of the auxiliary electrode line 800 .
  • the gate lines 600 and the data lines 700 whose extending directions intersect may define a plurality of pixel regions 000 a in the display substrate 000 .
  • any two adjacent gate lines 600 and any two adjacent data lines 700 can enclose a pixel area 000a.
  • the extension direction of the data line 700 and the extension direction of the gate line 600 may be perpendicular, and the extension direction of the data line 700 may be parallel to the auxiliary electrode line 800 .
  • the gate lines 600 and the data lines 700 whose extending directions are vertical define a plurality of pixel regions 000 a in the display substrate 000 to be rectangular.
  • the width of the data line 700 is smaller than the width of the auxiliary electrode line 800 .
  • the width of the data line 700 is small, which can reduce the overlapping area of the data line 700 and the gate line 600, thereby reducing the capacitance value of the parasitic capacitance generated between the data line 700 and the gate line 600, thereby reducing the The influence of parasitic capacitance on the display effect of the electronic paper where the display substrate 000 is located.
  • the width of the auxiliary electrode line 800 can be larger, so as to increase the strength of the electronic paper and reduce the probability of the electronic paper being damaged during use.
  • the pixel electrode 200 is electrically connected to the first auxiliary electrode 300 through a first via hole passing through the first interlayer insulating layer 900 and the second interlayer insulating layer 100 .
  • the first via hole includes a first sub-via hole a and a second sub-via hole b.
  • the first sub-via hole a penetrates the first interlayer insulating layer
  • the second sub-via hole b penetrates the second interlayer insulating layer
  • the pixel electrode is connected to the first sub-via hole a and the second sub-via hole b through the first sub-via hole a and the second sub-via hole b.
  • the auxiliary electrode 300 is electrically connected.
  • the orthographic projection of the first via hole a on the substrate 100 is located within the orthographic projection of the second via hole b on the substrate 100 .
  • the second interlayer insulating layer further has a second via hole, and the pixel electrode 200 is electrically connected to the drain electrode of the thin film transistor 500 through the second via hole.
  • the first interlayer insulating layer 900 can also be used as a gate insulating layer, so as to realize the insulating arrangement of the active layer 503 and the gate electrode 502 in the thin film transistor 500 .
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 is located within the orthographic projection of the first auxiliary electrode 300 on the substrate 100 , and the first auxiliary electrode 300 is in the The orthographic projection on the substrate 100 is located within the orthographic projection of the pixel electrode 200 on the substrate 100 .
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 and the overlapping area B between the orthographic projection of the pixel electrode 200 on the substrate 100 , and the second auxiliary electrode 400 and the first auxiliary electrode 300 are on the substrate
  • the area of the overlapping region C between the orthographic projections on the bottom 100 is the area of the second auxiliary electrode 400 .
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 , the overlapping region B between the orthographic projection of the pixel electrode 200 on the substrate 100 , and the second auxiliary electrode 400 and the first auxiliary electrode 300 The overlapping regions C between the orthographic projections on the substrate 100 coincide.
  • the capacitance value Ci of the total storage capacitance in the display substrate 000 can be changed by changing the area of the second auxiliary electrode 400 .
  • the larger the area of the second auxiliary electrode 400 is, the larger the capacitance value Ci of the total storage capacitor in the display substrate 000 is; conversely, the smaller the area of the second auxiliary electrode 400 is, the larger the total storage capacitor in the display substrate 000 is.
  • the smaller the capacitance value Ci is.
  • the capacitance value Ci of the total storage capacitor in the display substrate 000 can also be changed.
  • the value Ci is larger.
  • the orthographic projection of the first auxiliary electrode 300 on the base substrate 100 does not have an overlapping area with the orthographic projection of the source electrode 501 a and the drain electrode 501 b of the thin film transistor on the base substrate 100 .
  • the electric field interference between the first auxiliary electrode 300 and the source and drain electrodes 501 is avoided.
  • FIG. 9 is a schematic diagram of a film layer structure of a display device provided by an embodiment of the present disclosure.
  • the display device is electronic paper, which not only includes the above-mentioned display substrate, but also includes a cover plate 001 disposed opposite to the display substrate, and an electrophoretic layer 002 disposed between the display substrate and the cover plate 001 .
  • the electrophoresis layer 002 in the electronic paper may include: a plurality of electrophoresis capsules 0021, each electrophoresis capsule 0021 may include: a capsule body, and electrophoretic liquid and charged particles located in the capsule body, and the charged particles may include: black particles, White particles and colored particles, etc.
  • the electronic paper provided by the embodiments of the present application includes: a display substrate, a cover plate 001 and an electrophoretic layer 002 . Since the first auxiliary electrode 300 in the display substrate is electrically connected to the pixel electrode 200, when the electronic paper is displayed, the voltage loaded on the first auxiliary electrode 300 is the same as the voltage loaded on the pixel electrode 200, and both are the pixel voltage , that is, the first auxiliary electrode 300 is also equivalent to the pixel electrode 200 . In this way, when the electronic paper is displayed, the first auxiliary electrode 300 and the second auxiliary electrode 400 can form the first storage capacitor Cst1, and the pixel electrode 200 and the second auxiliary electrode 400 can form the second storage capacitor Cst2.
  • the first storage capacitor Cst1 and the second storage capacitor Cst2 are connected in parallel, and the total storage capacitor value in the display substrate is the sum of the capacitance value of the first storage capacitor Cst1 and the capacitance value of the second storage capacitor Cst2.
  • the electronic paper provided by the embodiments of the present disclosure increases the capacitance value of the storage capacitor without changing the PPI of the electronic paper, improves the stability of the voltage loaded on the pixel electrode, and further improves the performance of the electronic paper.
  • the display effect of the electronic paper is adopted.
  • An embodiment of the present disclosure provides a method for manufacturing a display substrate, which can form any one of the display substrates shown in FIGS. 5 , 7 and 8 .
  • the method includes: providing a base substrate, and the steps of forming pixels on the base substrate. Wherein, the steps of forming pixels include:
  • the first auxiliary electrode is formed on the base substrate.
  • a first interlayer insulating layer is formed on the side of the first auxiliary electrode facing away from the base substrate.
  • a second conductive film and a first photoresist layer are formed in sequence, and masks in different transmittance regions are used to expose the first photoresist layer, and
  • the exposure time is controlled according to the requirements of the working frequency band of the pixel to form the source and drain electrodes of the thin film transistor and the second auxiliary electrode; the orthographic projection of the first auxiliary electrode and the second auxiliary electrode on the substrate is overlapped to form the first storage capacitance.
  • a second interlayer insulating layer is formed on the side of the layer where the second auxiliary electrode is located away from the base substrate.
  • a pixel electrode is formed on the side of the second interlayer insulating layer away from the base substrate; wherein, the pixel electrode is connected to the drain electrode of the thin film transistor through a second via hole passing through the second interlayer insulating layer; the pixel electrode passes through the first layer
  • the first via hole of the interlayer insulating layer and the second interlayer insulating layer is electrically connected to the first auxiliary electrode, and the first auxiliary electrode and the orthographic projection of the pixel electrode on the base substrate at least partially overlap and overlap, so as to form a second auxiliary electrode. storage capacitor.
  • the source and drain electrodes and the second auxiliary electrode of the thin film transistor in the pixel are formed using masks with regions of different transmittances, so the pixel can be operated according to the applied product of the display substrate.
  • the frequency band requires that by controlling the exposure time, the source and drain electrodes and the size of the second auxiliary electrode of the formed thin film transistor are controlled, thereby controlling the channel width to length ratio of the thin film transistor, the size of the first storage capacitor and the second storage capacitor, to meet product needs.
  • the masks with different transmittance regions used in the embodiments of the present disclosure may be half-exposure masks or gray-scale masks.
  • the masks are not The type is limited, as long as it is an area with three or more different light transmittances.
  • the material of the first conductive pattern may include: metal molybdenum (abbreviation: Mo), metal titanium (abbreviation: Ti), metal copper (abbreviation: Cu), metal aluminum (abbreviation: Al) or alloy materials made.
  • the first conductive pattern may include: the gate electrode 502 and the first auxiliary electrode 300 of the thin film transistor in each pixel, and the gate line 600 .
  • the gates 502 of the thin film transistors in the pixels in the same row are connected to the same gate line 600 .
  • step S11 may include forming a first conductive film on the base substrate 100 by any one of deposition, coating, sputtering, etc., and then performing a patterning process on the first conductive film to The first conductive pattern is formed, that is, the gate electrode 502 and the first auxiliary electrode 300 of the thin film transistor in each pixel, and the gate line 600 are formed.
  • the first interlayer insulating layer 900 is used as a gate insulating layer, and its material includes, but is not limited to, silicon dioxide, silicon nitride, or a high dielectric constant material.
  • step S12 may include forming a first insulating film on the base substrate 100 on which the first conductive pattern is formed by any one of deposition, coating, sputtering, etc., and then forming a first insulating film on the first conductive pattern.
  • the insulating film is subjected to a patterning process to form the first interlayer insulating layer 900 having the first sub-via.
  • the material of the active layer may be, but not limited to, semiconductor materials such as polysilicon, amorphous silicon, or oxide semiconductor.
  • step S13 may include forming an active layer thin film on the base substrate 100 on which the first interlayer insulating layer 900 is formed by any one of deposition, coating, sputtering, etc., and then applying The active layer thin film is subjected to a patterning process to form an active layer.
  • the material of the second conductive pattern may include: metal Mo, metal Ti, metal Cu, metal aluminum Al or an alloy material.
  • the second conductive pattern may include: source electrodes 501 a and drain electrodes 501 b of the thin film transistor, second auxiliary electrodes 400 , data lines 700 and auxiliary electrode lines 800 .
  • the second auxiliary electrode 400 is multiplexed with the common electrode, which in turn can reduce the film thickness of the display substrate, which is helpful for the film thickness of the display substrate to which the display substrate is applied, thereby realizing light and thin products.
  • step S14 includes a completely light-transmitting region (100% light transmittance), a non-light-transmitting region (0% light transmittance), a plurality of For the partially transparent area, at this time, step S14 may include the following steps:
  • the following masks with different transmittance areas include a fully transparent area (100% light transmittance), a non-transparent area (0% light transmittance), a first partially transparent area and a second partially transparent area
  • step S14 will be further described.
  • the light transmittances of the first partial light-transmitting area and the second partial light-transmitting area are different.
  • the light transmittance of the first partial light transmission area is 60%
  • the light transmittance of the second partial light transmission area is 30%.
  • the three different working frequency bands are the first preset frequency band, the second preset frequency band and the third preset frequency band respectively; the first preset frequency band is 10Hz-20Hz; the second preset frequency band is greater than 20Hz and less than 120Hz; the third preset frequency band is For example, the preset frequency band is not less than 120Hz.
  • step S14 may include: forming the second conductive film 40 and The first photoresist layer 10 is exposed to the first photoresist layer by using masks 10 with different transmittance regions, and the exposure time is controlled to be T1, so that the first photoresist layer 10 and the completely transparent region ( 100% light transmittance) on the base substrate 100 is projected and overlapped by the photoresist non-reserved area, and the rest area is the photoresist reserved area.
  • the first photoresist layer corresponding to the fully transparent area is The photoresist is denatured, and this part of the photoresist is removed by developing; the second conductive film layer 40 is etched to form the source electrode 501a and the drain electrode 501b, the second auxiliary electrode 400, the data line 700 and the auxiliary electrode of the thin film transistor Line 800 is removed, and the remaining photoresist 201a is removed, that is, a second conductive pattern is formed.
  • the length of the source electrode and the drain electrode of the formed thin film transistor is the first distance L1; the area of the second auxiliary electrode is the first area S1.
  • step S14 may include: forming the second conductive film 40 and The first photoresist layer 20 is exposed to the first photoresist layer 20 by using the masks 10 in different transmittance regions, and the exposure time is controlled to be T2 (T2>T1), so that the first photoresist layer 20
  • T2 T2>T1
  • the photoresist layer 20 The area overlapping with the complete transmission area (100% light transmittance) and the first partial transmission area (60% light transmittance) projected on the base substrate 100 is the photoresist non-reserved area, and the remaining areas are the The photoresist reserved area, at this time, the photoresist of the first photoresist layer 20 corresponding to the complete transmission area (100% light transmittance) and the first partial transmission area (60% light transmittance) is denatured , remove this part of the photoresist by developing; etch the second conductive film layer to form the source electrode 501a and the drain electrode 501b,
  • the length of the source electrode 501a and the drain electrode 501b of the formed thin film transistor is the second distance L2 ( L2 ⁇ L1 ); the area of the second auxiliary electrode 400 is the second area S2 ( S2 ⁇ S1 ).
  • step S14 may include: sequentially forming the second conductive film 40 and The first photoresist layer 20 is exposed to the first photoresist layer 20 by using the masks 10 in different transmittance regions, and the exposure time is controlled to be T3 (T3>T2), so that the first photoresist layer 20 Projection on the base substrate 100 with a fully transmitted area (100% light transmittance), a first partially transmitted area (60% light transmittance) and a second partially transmitted area (30% light transmittance) The overlapping area is the photoresist non-reserved area, and the rest area is the photoresist reserved area.
  • the length of the source electrode 501a and the drain electrode 501b of the formed thin film transistor is the third distance L3 (L3 ⁇ L2); the area of the second auxiliary electrode 400 is the second area S3 (S3 ⁇ S2).
  • the length of the source electrode 501a and the drain electrode 501b of the thin film transistor determines the aspect ratio of the channel, and the greater the distance, the greater the aspect ratio.
  • the size of the area of the second auxiliary electrode 400 determines the size of the first storage capacitor Cst1 formed by the second auxiliary electrode 400 and the first auxiliary electrode 300 , and the second storage capacitor Cst2 to be formed by the second auxiliary electrode 400 and the pixel electrode 200 the size of.
  • the channel width to length ratio of the formed thin film transistor 500 is the largest, and the sum of the first storage capacitor Cst1 and the second storage capacitor Cst2 is the largest, and this kind of display substrate can be used In products that work at low frequencies, such as outdoor display cards, electronic labels, etc., it can effectively reduce power consumption.
  • the channel width to length ratio of the formed thin film transistor 500 is centered, and the sum of the first storage capacitor Cst1 and the second storage capacitor Cst2 is centered, and this kind of display substrate can be used for intermediate frequency working product.
  • the channel width to length ratio of the formed thin film transistor 500 is the smallest, and the sum of the first storage capacitor Cst1 and the second storage capacitor Cst2 is the smallest. Products that work frequently, such as e-books, can effectively avoid display delays.
  • the material of the second interlayer insulating layer 1000 may be silicon dioxide, silicon nitride, or a high dielectric constant material.
  • step S15 may include forming a second insulating film on the base substrate 100 formed with the second conductive pattern by any one of deposition, coating, sputtering, etc., and then forming a second insulating film on the second conductive pattern.
  • the insulating film is subjected to a patterning process to form the second interlayer insulating layer 1000 .
  • a pixel electrode 200 is formed on the second interlayer insulating layer 1000.
  • the pixel electrode 200 is connected to the first auxiliary electrode 300 through the first sub-via hole a and the second sub-via hole b, and is connected to the first auxiliary electrode 300 through the second via hole c at the same time.
  • the drain 501b of the thin film transistor is connected.
  • the material of the pixel electrode 200 may include transparent conductive materials such as indium tin oxide (English: Indium tin oxide; ITO for short) or Indium Zinc Oxide (English: Indium Zinc Oxide; IZO for short).
  • transparent conductive materials such as indium tin oxide (English: Indium tin oxide; ITO for short) or Indium Zinc Oxide (English: Indium Zinc Oxide; IZO for short).
  • step S16 may include forming a pixel electrode film on the base substrate 100 on which the second interlayer insulating layer 1000 is formed by any one of deposition, coating, sputtering, etc.
  • the pixel electrode film is subjected to a patterning process to form the pixel electrode 200 .

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Abstract

一种显示基板及其制备方法、显示装置。显示基板的制备方法，其包括：提供一衬底基板(01，100)，并在所述衬底基板上形成像素；其中，形成像素包括：在衬底基板(01，100)上形成第一辅助电极(022，300)；在第一辅助电极(022，300)背离衬底基板(01，100)的一侧形成第一层间绝缘层(03，900)；依次形成第二导电薄膜(40)和第一光刻胶层(20)，采用不同透过率区域的掩膜版(10)对第一光刻胶层(20)进行曝光，并根据像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极(051a，501a)和漏极(051b，501b)，以及第二辅助电极(052，400)；形成第二层间绝缘层(06，1000)；形成像素电极(07，200)。

Description

显示基板及其制备方法、显示装置 技术领域
本公开属于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
电子纸是一种新型的显示器件，主要用于电子标签、广告牌和电子阅读器等设备中。该电子纸的显示效果接近自然纸张的效果，可降低阅读时的视觉疲劳。
在相关技术中，电子纸通常可以包括：相对设置的显示基板和盖板，以及位于显示基板和盖板之间的电泳层。该显示基板具有阵列排布的多个像素，每个像素可以包括：像素电极，以及与该像素电极绝缘设置的辅助电极。该像素电极和辅助电极能够在显示时形成存储电容，以维持该像素电极上加载的电压的稳定性。
但是，随着显示基板中每英寸像素个数(英文：Pixels Per Inch；简称：PPI)的不断提高，显示基板中的每个像素电极的尺寸不断减小，导致像素电极与辅助电极之间交叠面积不断减小，进而导致该像素电极与辅助电极之间形成的存储电容的电容值不断减小。如此，会影响像素电极上加载的电压的稳定性，导致采用该显示基板制备出的电子纸的显示效果较差。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及其制备方法、显示装置。
本公开实施例提供一种显示基板的制备方法，所述显示基板具有多个像素，其包括：
提供一衬底基板，并在所述衬底基板上形成像素；其中，
形成所述像素包括：
在所述衬底基板上形成第一导电薄膜，并对所述第一导电薄膜图案化形成薄膜晶体管的栅极和第一辅助电极；
在所述第一辅助电极背离所述衬底基板的一侧形成第一层间绝缘层；
在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用具有不同透过率区域的掩膜版对第一光刻胶层进行曝光预定时间，以形成薄膜晶体管的源极和漏极，以及第二辅助电极，其中，所述第一辅助电极与所述第二辅助电极在所述衬底基板上的正投影重叠，以形成第一存储电容；
在所述第二辅助电极所在层背离所述衬底基板的一侧形成第二层间绝缘层；
对所述第一层间绝缘层和所述第二层间绝缘层进行图案化，以形成贯穿所述第一层间绝缘层和所述第二层间绝缘层的第一过孔，和贯穿所述第二层间绝缘层的第二过孔，所述第一过孔暴露所述薄膜晶体管的源极和漏极，所述第二过孔暴露所述第一辅助电极；和
在所述第二层间绝缘层背离所述衬底基板的一侧形成像素电极；其中，所述像素电极通过贯穿所述第二层间绝缘层的第二过孔与所述薄膜晶体管的漏极连接；所述像素电极通过贯穿所述第一层间绝缘层和所述第二层间绝缘层的第一过孔与所述第一辅助电极电连接，且所述第一辅助电极与所述像素电极在所述衬底基板上的正投影至少部分重叠重叠，以形成第二存储电容。
其中，所述具有不同透过率区域的掩膜版包括完全透光区域、非透光区域、多个部分透光区域；所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用所述具有不同透过率区域的掩膜版对第一光刻胶层进行曝光预定时间，以形成薄膜晶体管的源极和漏极，以及第二辅助电极的步骤，包括：
根据所述显示面板的工作频段要求得到所述第一存储电容和所述第二存储电容，以得到所述第二辅助电极在所述衬底基板上的投影面积；
控制曝光时间，以控制所述多个部分透光区域的光线射出量，从而控制第一光刻胶层的光刻胶保留区的大小；
去除第一光刻胶层中光刻胶非保留区的光刻胶，并刻蚀形成薄膜晶体管的源极和漏极，以及第二辅助电极。
其中，所述多个部分透光区域包括包括第一部分透光区域和第二部分透过光区域，且所述第一部分透光区域的光线透过率大于第二部分透光区域的光线透过率；
当所述像素的工作频段要求为第一预设频段时，所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极步骤，包括：
在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层；
采用所述不同透过率区域的掩膜版对所述第一光刻胶层进行曝光，并控制曝光时间为T1，以使所述第一光刻胶层与所述完全透过区域在所述衬底基板上投影重叠的区域为所述光刻胶非保留区，其余区域为所述光刻胶保留区；
去除所述第一光刻胶层的所述光刻胶非保留区的光刻胶；
对所述第二导电薄膜进行刻蚀，形成所述薄膜晶体管的源极和漏极，以及所述第二辅助电极，并去除剩余的光刻胶；所述薄膜晶体管的源极和漏极的长度为第一距离L1；所述第二辅助电极的面积为第一面积S1；
当所述像素的工作频段要求为第二预设频段时，所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极的步骤，包括：
在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层；
采用所述不同透过率区域的掩膜版对所述第一光刻胶层进行曝光，并控制曝光时间为T2，以使所述第一光刻胶层与所述完全透过区域和第一部分透光区域在所述衬底基板上投影重叠的区域为所述光刻胶非保留区，其余区域为所述光刻胶保留区；
去除所述第一光刻胶层的所述光刻胶非保留区的光刻胶；
对所述第二导电薄膜进行刻蚀，形成所述薄膜晶体管的源极和漏极，以及所述第二辅助电极，并去除剩余的光刻胶；所述薄膜晶体管的源极和漏极的长度为第二距离L2；所述第二辅助电极的面积为第二面积S2；
当所述像素的工作频段要求为第三预设频段时，所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极图形的步骤，包括：
在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层；
采用所述不同透过率区域的掩膜版对所述第一光刻胶层进行曝光，并控制曝光时间为T3，以使所述第一光刻胶层与所述完全透过区域、第一部分透光区域和第二部分透光区域在所述衬底基板上投影重叠的区域为所述光刻胶非保留区，其余区域为所述光刻胶保留区；
去除所述第一光刻胶层的所述光刻胶非保留区的光刻胶；
对所述第二导电薄膜进行刻蚀，形成所述薄膜晶体管的源极和漏极，以及所述第二辅助电极，并去除剩余的光刻胶；所述薄膜晶体管的源极和漏极的长度为第三距离L3；所述第二辅助电极的面积为第三面积S3；
其中，所述第一预设频段的最大值小于所述第二预设频段的最小值，且所述第二预设频段的最大值小于所述第三预设频段的最小值；T1＜T2＜T3；L3＜L2＜L1；S3＜S2＜S1。
其中，所述在所述衬底基板上形成第一辅助电极的同时，还形成所述薄 膜晶体管的栅极。
其中，位于同一列像素的所述第二辅助电极连接同一条辅助电极线，被配置为施加公共电压信号。
其中，在所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极的步骤之前，还包括：
在所述第一层间绝缘层背离所述衬底基板的一侧形成所述薄膜晶体管的有源层。
其中，在所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极的同时，还包括：
形成数据线和辅助电极线，且所述数据线与所述薄膜晶体管的源极电连接；所述辅助电极线与所述第二辅助电极连接。
其中，所述数据线与所述辅助电极线的延伸方向平行或者大致平行。
其中，所述像素包括两个串接的所述薄膜晶体管。
本公开实施例提供一种显示基板，所述显示基板具有多个像素，在至少一个像素中，其包括：
衬底基板；
位于所述衬底基板上的薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极；
依次设置在所述衬底基板上的第一辅助电极、第二辅助电极和像素电极，所述第一辅助电极、所述第二辅助电极和像素电极在所述衬底基板上的正投影至少部分重叠；
第一层间绝缘层，位于所述第一辅助电极和所述第二辅助电极所在层之 间，以使所述第一辅助电极和所述第二辅助电极绝缘；和
第二层间绝缘层，位于所述第二辅助电极和所述像素电极所在层之间，以使所述第一辅助电极和所述像素电极绝缘；其中，
所述第二辅助电极和所述薄膜晶体管的源极和漏极同层设置，且材料相同，所述像素电极通过贯穿所述所述第二层间绝缘层的第一过孔与所述薄膜晶体管的漏极连接，所述像素电极通过贯穿所述第一层间绝缘层和所述第二层间绝缘层的第二过孔与所述第一辅助电极电连接。
其中，当所述像素的工作频段为第一预设频段时，所述薄膜晶体管的源极和漏极的长度为第一距离L1；所述第二辅助电极的面积为第一面积S1；
当所述像素的工作频段为第二预设频段时，所述薄膜晶体管的源极和漏极的长度为第二距离L2；所述第二辅助电极的面积为第二面积S2；
当所述像素的工作频段为第三预设频段时，所述薄膜晶体管的源极和漏极的长度为第一距离L3；所述第二辅助电极的面积为第一面积S3；
其中，所述第一预设频段的最大值小于所述第二预设频段的最小值，且所述第二预设频段的最大值小于所述第三预设频段的最小值；L3＜L2＜L1；S3＜S2＜S1。
其中，位于同一列像素的所述第二辅助电极连接同一条辅助电极线，被配置为施加公共电压信号。
其中，所述第一辅助电极与所述薄膜晶体管的栅极同层设置，且材料相同。
其中，还包括数据线和辅助电极线，所述数据线、所述辅助电极线与所述第二辅助电极同层设置，且材料相同；且所述数据线与所述薄膜晶体管的源极电连接；所述辅助电极线与所述第二辅助电极连接。
其中，所述数据线与所述辅助电极线的延伸方向平行或者大致平行。
其中，所述像素包括两个串接的所述薄膜晶体管。
本公开实施例提供一种显示装置，其包括上述的任一显示基板。
其中，所述显示装置为电子纸显示装置，所述电子纸显示装置还包括和所述显示基板相对设置的盖板，以及位于所述显示基板和所述盖板之间的电泳层。。
附图说明
图1是相关技术提供的一种显示基板的一个像素内的膜层结构示意图。
图2是图1示出的显示基板的俯视示意图。
图3为本公开实施例提供的一种显示基板一个像素内的膜层结构示意图。
图4是图3示出的显示基板的俯视示意图。
图5是本公开实施例提供另一种显示基板的俯视图。
图6是图5示出的显示基板在D-D’处的截面图。
图7是本公开实施例提供另一种显示基板的俯视图。
图8是本公开实施例提供另一种显示基板的俯视图。
图9是本公开实施例提供另一种显示装置的截面图。
图10是本公开实施例的显示基板的制备方法中，在像素为工作频段为第一预设频段时所采用的不同精度掩膜版进行曝光的示意图。
图11是本公开实施例的显示基板的制备方法中，在像素为工作频段为第二预设频段时所采用的不同精度掩膜版进行曝光的示意图。
图12是本公开实施例的显示基板的制备方法中，在像素为工作频段为第三预设频段时所采用的不同精度掩膜版进行曝光的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分 不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要说明的是，本公开实施例中所提供的显示基板可用于全反射和电子纸等不需要背光的产品中，当显示基板应用于不需要背光的产品中，该显示基板中的像素电极和公共电极可以采用非透光材料。
图1是相关技术提供的一种显示基板的一个像素内的膜层结构示意图。请参考图1，在一个像素内，显示基板可以包括：衬底基板01；设置在衬底基板01上、且沿背离衬底基板01的方向层叠设置第一导电图案02、第一层间绝缘层03、薄膜晶体管的有源层04、第二导电图案05、第二层间绝缘层06以及像素电极07。其中，该第一导电图案可以包括：薄膜晶体管的栅极021和第一辅助电极022，该第二导电图案05可以包括：薄膜晶体管的源极051a和漏极051b和第二辅助电极052。第二辅助电极052与薄膜晶体管的漏极051b电连接，且第二辅助电极052与像素电极07通过第二层间绝缘层06上的过孔电连接。
请参考图2，图2是图1示出的显示基板的俯视示意图。该显示基板中，第一辅助电极022在衬底基板01上的正投影，与第二辅助电极052在衬底基板01上的正投影存在交叠区域A。
由于第二辅助电极052与像素电极07通过第二层间绝缘层06上的过孔连接，因此，在采用该显示基板制备出的电子纸进行显示时，第二辅助电极052上加载的电压，与像素电极07上加载的电压相同，均为像素电压，也即是，第二辅助电极052相当于像素电极。如此，在采用该显示基板制备出的电子纸进行显示时，第一辅助电极022与第二辅助电极052可以形成存储电容Cst’，维持像素电极07上加载的电压的稳定性，该存储电容Cst’的电容值越大，维持像素电极07上加载的电压的稳定性的效果越好。
但是，随着显示基板中每英寸像素个数(英文：Pixels Per Inch；简称： PPI)的不断提高，显示基板中每个像素的尺寸不断减小，导致第一辅助电极022与第二辅助电极052之间交叠面积不断减小，进而导致存储电容Cst’的电容值不断减小。如此，会影响像素电极上加载的电压的稳定性，导致采用该显示基板制备出的电子纸的显示效果较差。
图3为本公开实施例提供的一种显示基板一个像素内的膜层结构示意图。显示基板具有多个阵列排布的像素，在一个像素内，请参考图3，该显示基板包括衬底基板100，沿背离衬底基板100方向上依次设置的像素电极200、第一辅助电极300以及第二辅助电极400。显示基板还包括：设置在第一辅助电极300和第二辅助电极400所在层之间设置有第一层间绝缘层900，在第二辅助电极400和像素电极200之间设置有第二层间绝缘层1000。像素电极200通过贯穿第一层间绝缘层900的和第二层间绝缘层1000的第一过孔与第一辅助电极300电连接。
请参考图4，图4是图3示出的显示基板的俯视示意图。其中，第二辅助电极400在衬底100上的正投影，与像素电极200在衬底100上的正投影存在交叠区域B，且与第一辅助电极300在衬底100上的正投影存在交叠区域C。
由于第一辅助电极300与像素电极200电连接，因此，在该显示基板进行显示时，第一辅助电极300上加载的电压，与像素电极200上加载的电压相同，均为像素电压。也即，第一辅助电极300也相当于像素电极200。如此，在该显示基板进行显示时，第一辅助电极300与第二辅助电极400之间可以形成第一存储电容Cst1，像素电极200与第二辅助电极400之间可以形成第二存储电容Cst2。由于第二辅助电极400位于像素电极200与第一辅助电极300之间，因此，通过第二辅助电极400与第一辅助电极300形成的第一存储电容Cst1，和通过第二辅助电极400与像素电极200形成的第二存储电容Cst2并联。该显示基板000中的总存储电容的电容值为第一存储电容Cst1的电容值和第二存储电容Cst1的电容值之和，因此，该显示基板000中的总存储电容的电容值较大。
在相关技术中，如图1和图2所示，假设第一辅助电极022在衬底基板01上的正投影，与第二辅助电极052在衬底基板01上的正投影之间的交叠区域A的面积为S。第一辅助电极022和第二辅助电极052之间的第一层间绝缘层03的厚度可以为4000埃，该第一层间绝缘层03的材料可以包括： 氮化硅，其相对介电常数为6.5。
则，可以计算得到存储电容Cst’的电容值Ci’为：
Figure PCTCN2021127038-appb-000001
而在本公开实施例中，如图3和图4所示，假设第二辅助电极400在衬底100上的正投影，与像素电极200在衬底100上的正投影之间的交叠区域B的面积也为S，第二辅助电极400在衬底100上的正投影，与第一辅助电极300在衬底100上的正投影之间的交叠区域C的面积也为S。且由于第一辅助电极300与第二辅助电极400之间的绝缘层，与相关技术中的第一层间绝缘层03的厚度和材料均相同，因此，第一存储电容Cst1的电容值Ci 1与相关技术中的存储电容Cst’的电容值Ci’的大小相等。第二辅助电极400与像素电极200之间的绝缘层的厚度范围可以为：2000至6000埃，该绝缘层的材料与第一层间绝缘层03相同，其相对介电常数也为6.5。
则，可以计算得到第二存储电容Cst2的电容值的最小值Ci 2，min为：
Figure PCTCN2021127038-appb-000002
第二存储电容Cst2的电容值的最大值Ci 2，max为：
Figure PCTCN2021127038-appb-000003
因此，在本申请中，显示基板000中的总存储电容的电容值Ci的范围为：
Ci＝Ci 1+Ci 2＝2.399×10 -16×S～4.21×10 -16×S      (4)
由上可知，相比于相关技术中的显示基板00中的存储电容的电容值Ci’，本申请实施例提供的显示基板000中的总存储电容的电容值Ci可以提高67％至192％。
综上所述，由于本公开实施例中的显示基板中的第一辅助电极300与像素电极200电连接，因此，在该应用该显示基板的电子纸进行显示时，第一 辅助电极300上加载的电压，与像素电极200上加载的电压相同，均为像素电压，也即是，第一辅助电极300也相当于像素电极200。如此，在该电子纸进行显示时，第一辅助电极300与第二辅助电极400可以形成第一存储电容Cst1，像素电极200与第二辅助电极400可以形成第二存储电容Cst2。该第一存储电容Cst1和第二存储电容Cst2并联，该显示基板中的总存储电容值为第一存储电容Cst1的电容值与第二存储电容Cst2的电容值之和。与相关技术相比，本公开实施例提供的电子纸，在不改变电子纸的PPI的情况下，增大了存储电容的电容值，提高了像素电极200上加载的电压的稳定性，进而提高了采用该电子纸的显示效果。
在本申请实施例中，请参考图5和图6，图5是本公开实施例提供另一种显示基板的俯视图，图6是图5示出的显示基板在D-D’处的截面图。该显示基板的像素还可以包括：薄膜晶体管500(英文：Thin-film transistor；简称：TFT)，该薄膜晶体管500的漏极与像素电极200电连接。
在一些示例中，薄膜晶体管的源极501a和漏极501b可以与第二辅助电极400同层设置，且采用相同材料。也即，薄膜晶体管的源极501a和漏极501b可以与第二辅助电极400通过一次构图工艺制备形成。当然，薄膜晶体管的源漏极501也可以与第一辅助电极300同层设置。也即，薄膜晶体管的源漏极501可以与第一辅助电极300通过一次构图工艺制备形成。如此，可以简化该显示基板的制造工艺，降低该显示基板的制造难度和制造成本。需要说明的是，图5是以薄膜晶体管的源极501a和漏极501b与第二辅助电极400同层设置，且材料相同为例进行示意性说明的。
进一步的，第二辅助电极400可以复用为像素中的公共电极，通过该种方式可以降低显示基板的膜层厚度，有助于实现显示基板的轻薄化。具体的，位于同一列像素的所述第二辅助电极400连接同一条辅助电极线，被配置为施加公共电压信号。
在一些示例中，薄膜晶体管500中的栅极502可以与第一辅助电极300同层设置，且材料相同；该薄膜晶体管500中的源漏极501可以与第二辅助电极400同层设置，且材料相同。在该种情况下，薄膜晶体管的栅极502可以与第一辅助电极300通过一次构图工艺形成，薄膜晶体管的源漏极501可以与第二辅助电极400通过一次构图工艺形成。如此，可以进一步简化该显 示基板的制造工艺，进一步降低该显示基板000的制造难度和制造成本。
在一些示例中，薄膜晶体管的有源层503与源漏极501搭接，且源漏极501位于有源层503远离衬底100的一侧，栅极502位于有源层503靠近衬底基板100的一侧。也即是，该薄膜晶体管500为底栅型薄膜晶体管。在其他可能的实现方式中，该薄膜晶体管500还可以为顶栅型薄膜晶体管，本公开实施例对此不做限定。
在公开实施例中，请参考图5和图6，该显示基板具有阵列排布的多个像素区域000a，每个像素区域000a设置有串联的两个薄膜晶体管500。
该两个薄膜晶体管500中的每一个薄膜晶体管500均可以包括：源极501a和漏极501b。其中，一个薄膜晶体管500中的漏极501b与另一个薄膜晶体管500中的源极501a电连接，以使两个薄膜晶体管500串联。如此，可以降低薄膜晶体管500中的漏电流，对像素电极200上加载的像素电压的影响。当然，每个像素中也可仅包括一个薄膜晶体管500。
示例的，如图5所示，该每个薄膜晶体管500中的有源层503的沟道区E为长条形沟道区。需要说明的是，有源层图案503的沟道区E是指：有源层503中位于有源层503与源极接触的区域，和有源层503与漏极接触的区域之间的区域。该沟道区E的宽度的范围可以为：20至40微米。如此，可以满足显示基板000的充电率需要。
在本公开实施例中，根据不同的产品的应用场景不同，像素的工作频率也要求不同，根据像素的工作频段要求，对像素中的第一存储电容Cst1、第二存储电容Cst2，以及薄膜晶体管500的沟道宽长比要求也不同。例如：柔性电子纸应用到户外显示牌或者电子标签时，为了减小功耗，需要较低的工作频率(10-20HZ)；当应用到如支持手写的电子书时，因需要手写无延迟，需要较高的工作频率(≥120HZ)。对工作频率较高的产品，因充电时间较短，需要较小的存储电容和对应较小的薄膜晶体管500的沟道宽长比；对工作频率较低的产品，因保证下一帧刷新时，漏电满足要求，需要较大的存储电容和对应较大的薄膜晶体管500的沟道宽长比。本公开实施例中的显示基板，可以应用在反射型显示、反射型电子纸等显示装置中。
在一些示例中，如图5所示，当像素的工作频段为第一预设频段时，像素中薄膜晶体管的源极501a和漏极501b的长度为L1，第二辅助电极400的面积为S1。如图7所示，当像素的工作频段为第二预设频段时，像素中 薄膜晶体管的源极501a和漏极501b的长度为L2，第二辅助电极400的面积为S2。如图8所示，当像素的工作频段为第三预设频段时，像素中薄膜晶体管的源极501a和漏极501b的长度为L3，第二辅助电极400的面积为S3。第一预设频段的最大值小于第二预设频段的最小值，且第二预设频段的最大值小于第三预设频段的最小值；L3＜L2＜L1；S3＜S2＜S1。需要说明的是，薄膜晶体管的源极501a和漏极501b的长度则为该薄膜晶体管500的沟道宽度，薄膜晶体管的源极501a和漏极501b的长度越大，沟道宽长比越大。需要说明的是，如何实现不同工作频段的像素中的薄膜晶体管500的沟道宽长比和存储电容的设计，具体见下述的显示基板的制备方法。
在本公开实施例中，如图5所示，该显示基板还可包括：多条栅线600、多条数据线700，以及多条辅助电极线800。其中，栅线600和数据线700的延伸方向相交，例如二者的延伸方向相互垂直。辅助电极线800与数据线700的延伸方向大致相同或者相同。在一些示例中，位于同一行的像素中薄膜晶体管500的栅极502连接同一条栅线600，位于同一列像素的薄膜晶体管500的源极501a连接同一条数据线700，以及位于同一列像素的第二辅助电极400连接同一条辅助电极线800。
示例的，栅线600、薄膜晶体管的栅极502和第一辅助电极300同层设置，且材料相同。也即，栅线600、栅极502和第一辅助电极300是通过一次构图工艺形成的。该数据线700、辅助电极线800、源漏极501和第二辅助电极400同层设置，且材料相同。也即，该数据线700、辅助电极线800、源漏极501和第二辅助电极400是通过一次构图工艺形成的。
其中，栅线600的延伸方向与数据线700的延伸方向相交，且该栅线600的延伸方向与辅助电极线800的延伸方向相交。该延伸方向相交的栅线600和数据线700可以在显示基板000中限定出多个像素区域000a。示例的，任意两条相邻的栅线600与任意两条相邻的数据线700能够围成一个像素区域000a。
在一些示例中，数据线700的延伸方向与栅线600的延伸方向可以垂直，该数据线700的延伸方向可以与辅助电极线800平行。该延伸方向垂直的栅线600和数据线700在显示基板000中限定出多个像素区域000a为矩形。
进一步的，数据线700的宽度小于辅助电极线800的宽度。如此，该数据线700的宽度较小，可以降低数据线700与栅线600交叠的面积，从而降 低了该数据线700与栅线600之间产生的寄生电容的电容值，进而降低了该寄生电容对显示基板000所在的电子纸的显示效果的影响。而由于在该显示基板000所在的显示装置进行显示时，辅助电极线800上加载的电压恒定不变，因此，该辅助电极线800与栅线600之间产生的寄生电容，不会影响该电子纸的显示效果，该辅助电极线800的宽度可以较大，以增加该电子纸的强度，降低该电子纸在使用过程中损坏的概率。
在一些示例中，像素电极200通过贯穿第一层间绝缘层900的和第二层间绝缘层100的第一过孔与第一辅助电极电300连接。其中，第一过孔包括第一子过孔a和第二子过孔b。其中，第一子过孔a贯穿第一层间绝缘层，第二子过孔b贯穿第二层间绝缘层，像素电极则通过第一子过孔a和第二子过孔b与第一辅助电极300电连接。
在本公开实施例中，该第一过孔a在衬底100上的正投影，位于该第二过孔b在衬底100上的正投影内。
可选的，在本公开实施例第二层间绝缘层还具有第二过孔，像素电极200通过该第二过孔与薄膜晶体管500的漏极电连接。
需要说明的是，该第一层间绝缘层900还可以作为栅极绝缘层，以实现薄膜晶体管500中的，有源层503与栅极502的绝缘设置。
在本公开实施例中，如图5所示，第二辅助电极400在衬底100上的正投影，位于第一辅助电极300在衬底100上的正投影内，且第一辅助电极300在衬底100上的正投影，位于像素电极200在衬底100上的正投影内。如此，第二辅助电极400在衬底100上的正投影，与像素电极200在衬底100上的正投影之间的交叠区域B，和第二辅助电极400与第一辅助电极300在衬底100上的正投影之间的交叠区域C的面积，均为第二辅助电极400的面积。也即是，第二辅助电极400在衬底100上的正投影，与像素电极200在衬底100上的正投影之间的交叠区域B，和第二辅助电极400与第一辅助电极300在衬底100上的正投影之间的交叠区域C重合。如此，可以通过改变第二辅助电极400的面积，改变显示基板000中的总存储电容的电容值Ci。示例的，该第二辅助电极400的面积越大，显示基板000中的总存储电容的电容值Ci越大；反之，该第二辅助电极400的面积越小，显示基板000中的总存储电容的电容值Ci越小。
需要说明的是，还可以通过改变第二绝缘层1000的厚度，改变显示基 板000中的总存储电容的电容值Ci。示例的，第二绝缘层1000的厚度越大，显示基板000中的总存储电容的电容值Ci越小；反之，第二绝缘层1000的厚度越小，显示基板000中的总存储电容的电容值Ci越大。
还需要说明的是，第一辅助电极300在衬底基板100上的正投影，与薄膜晶体管的源极501a和漏极501b在衬底基板100上的正投影不存在交叠区域，如此，可以避免该第一辅助电极300与源漏极501之间产生电场干扰。
在本公开实施例中，请参考图9，图9是本公开实施例提供的一种显示装置的膜层结构示意图。该显示装置为电子纸，其不仅包括上述的显示基板，而且包括与显示基板相对设置的盖板001，以及设置在显示基板和盖板001之间的电泳层002。
该电子纸中的电泳层002可以包括：多个电泳胶囊0021，每个电泳胶囊0021可以包括：胶囊本体，以及位于该胶囊本体内的电泳液和带电粒子，该带电粒子可以包括：黑粒子、白粒子和彩色粒子等。
在本申请中，当向显示基板000中的像素电极400施加电压时，像素电极400会与公共电极(第二辅助电极400)形成电压差，在该电压差的作用下，每个电泳胶囊0021中的带电粒子会在电泳液中进行运动，以实现该电子纸的显示。
综上所述，本申请实施例提供的电子纸，包括：显示基板、盖板001和电泳层002。由于显示基板中的第一辅助电极300与像素电极200电连接，因此，在该电子纸进行显示时，第一辅助电极300上加载的电压与像素电极200上加载的电压相同，均为像素电压，也即是，第一辅助电极300也相当于像素电极200。如此，在该电子纸进行显示时，第一辅助电极300与第二辅助电极400可以形成第一存储电容Cst1，像素电极200与第二辅助电极400可以形成第二存储电容Cst2。该第一存储电容Cst1和第二存储电容Cst2并联，该显示基板中的总存储电容值为第一存储电容Cst1的电容值与第二存储电容Cst2的电容值之和。与相关技术相比，本公开实施例提供的电子纸，在不改变电子纸的PPI的情况下，增大了存储电容的电容值，提高了像素电极上加载的电压的稳定性，进而提高了采用该电子纸的显示效果。
本公开实施例提供的一种显示基板的制造方法，该方法可以形成图5、7、8中的任意一种显示基板。该方法包括：提供一衬底基板，以及在衬底 基板上形成像素的步骤。其中，形成像素的步骤包括：
在衬底基板上形成第一辅助电极。
在第一辅助电极背离所述衬底基板的一侧形成第一层间绝缘层。
在第一层间绝缘层背离衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极；第一辅助电极与第二辅助电极在衬底基板上的正投影重叠，以形成第一存储电容。
在第二辅助电极所在层背离衬底基板的一侧形成第二层间绝缘层。
在第二层间绝缘层背离衬底基板的一侧形成像素电极；其中，像素电极通过贯穿第二层间绝缘层的第二过孔与薄膜晶体管的漏极连接；像素电极通过贯穿第一层间绝缘层和第二层间绝缘层的第一过孔与第一辅助电极电连接，且第一辅助电极与所述像素电极在衬底基板上的正投影至少部分重叠重叠，以形成第二存储电容。
由于在本公开实施例，像素中的薄膜晶体管的源极和漏极、第二辅助电极时采用不同透过率区域的掩膜版形成，因此可以根据显示基板的所应用的产品对像素的工作频段要求，通过控制曝光时间，控制所形成薄膜晶体管的源极和漏极、第二辅助电极的尺寸，进而控制薄膜晶体管的沟道宽长比、第一存储电容和第二存储电容的大小，以满足产品需求。
在一些示例中，本公开实施例中所采用的不同透过率区域的掩膜版可以是半曝光掩膜版，也可以是灰阶掩膜版，在本公开实施例中并不对掩膜版的类型进行限定，只要是具有三种以上不同的光线透过率的区域即可。
为了清楚本公开实施例的显示基板的制备方法，结合图5-8中的任意一种显示基板，以及图10-12所示，以下提供一种示例性显示基板的制备方法。该方法包括如下步骤：
S11、在衬底基板100上形成第一导电图案。
在一些示例中，该第一导电图案的材料可以包括：金属钼(简称：Mo)、金属钛(简称：Ti)、金属铜(简称：Cu)、金属铝(简称：Al)或合金材料制造而成。该第一导电图案可以包括：各个像素中的薄膜晶体管的栅极502 和第一辅助电极300，以及栅线600。其中，位于同一行的像素中的薄膜晶体管的栅极502连接同一条栅线600。
在一些示例中，步骤S11可以包括在衬底基板100上通过沉积、涂敷、溅射等多种方式中的任一种形成第一导电薄膜，然后对该第一导电薄膜进行一次构图工艺以形成第一导电图案，也即形成：各个像素中的薄膜晶体管的栅极502和第一辅助电极300，以及栅线600。
S12、在第一导电图案上形成第一层间绝缘层900，并形成贯穿第一层间绝缘层的第一子过孔a。
在一些示例中，第一层间绝缘层900作为栅极绝缘层，其材料包括但不限于二氧化硅、氮化硅或者高介电常数材料等。
在一些示例中，步骤S12可以包括在形成有第一导电图案的衬底基板100上通过沉积、涂敷、溅射等多种方式中的任一种形成第一绝缘薄膜，然后对该第一绝缘薄膜一次构图工艺以形成具有第一子过孔的第一层间绝缘层900。
S13、在第一层间绝缘层900上形成像素中的薄膜晶体管的有源层503。
在一些示例中，该有源层的材料可以但不限于多晶硅、非晶硅或氧化物半导体等半导体材料。
在一些示例中，步骤S13可以包括在形成有第一层间绝缘层900的衬底基板100上通过沉积、涂敷、溅射等多种方式中的任一种形成有源层薄膜，然后对该有源层薄膜进行一次构图工艺以形成有源层。
S14、采用不同透过率区域的掩膜版10，并根据所述像素的工作频段要求控制曝光时间，在有源层上形成第二导电图案。
在一些示例中，该第二导电图案的材料可以包括：金属Mo、金属Ti、金属Cu、金属铝Al或合金材料制造而成。该第二导电图案可以包括：薄膜晶体管的源极501a和漏极501b、第二辅助电极400、数据线700和辅助电极线800。
在一些示例中，第二辅助电极400与公共电极复用，依次可以减小显示基板的膜层厚度，有助于应用该显示基板的显示基板的膜层厚度，从而实现产品的轻薄化。
在一些示例中，步骤S14中所采用的不同透过率区域的掩膜版10包括完全透光区域(100％光线透过率)、非透光区域(0％光线透过率)、多个部 分透光区域，此时在步骤S14中可以包括如下步骤：
S141、在第一层间绝缘层900背离衬底基板100的一侧，依次形成第二导电薄膜40和第一光刻胶层20。
S142、采用不同透过率区域的掩膜版10对所述第一光刻胶层20进行曝光，并根据像素的工作频段要求控制曝光时间，以控制多个部分透光区域的光线射出量，从而控制第一光刻胶层20的光刻胶保留区的大小。
S143、去除第一光刻胶层20中光刻胶非保留区的光刻胶，并刻蚀形成第二导电图案图形。
以下以不同透过率区域的掩膜版包括完全透光区域(100％光线透过率)、非透光区域(0％光线透过率)、第一部分透光区域和第二部分透光区域为例，对步骤S14进一步说明。其中，第一部分透光区域和第二部分透光区域二者的光线透过率不同。例如：第一部分透光区域的光线透过率为60％，第二部分透光区域的光线透过率为30％。通过该种掩膜版可以实现三种不同工作频段要求像素的制备。三种不同工作频段分别为第一预设频段、第二预设频段和第三预设频段；以第一预设频段为10Hz-20Hz；第二预设频段为大于20Hz且小于120Hz；第三预设频段为不小于120Hz为例。
参照图10和图5，当像素的工作频段要求为第一预设频段，步骤S14可以包括：在第一层间绝缘,900背离衬底基板100的一侧，依次形成第二导电薄膜40和第一光刻胶层10采用不同透过率区域的掩膜版10对第一光刻胶层进行曝光，并控制曝光时间为T1，以使第一光刻胶层10与完全透过区域(100％光线透过率)在衬底基板100上投影重叠的区域为光刻胶非保留区，其余区域为光刻胶保留区，此时与完全透过区域对应的第一光刻胶层的光刻胶发生变性，通过显影去除该部分光刻胶；对第二导电膜层40进行刻蚀，形成薄膜晶体管的源极501a和漏极501b、第二辅助电极400、数据线700和辅助电极线800，并去除剩余的光刻胶201a，也即形成第二导电图案。此时，所形成薄膜晶体管的源极和漏极的长度为第一距离L1；所述第二辅助电极的面积为第一面积S1。
参照图7和图11，当像素的工作频段要求为第二预设频段，步骤S14可以包括：在第一层间绝缘层900背离衬底基板100的一侧，依次形成第二导电薄膜40和第一光刻胶层20采用不同透过率区域的掩膜版10对第一光刻胶层20进行曝光，并控制曝光时间为T2(T2＞T1)，以使第一光刻胶层20与完全透过区域(100％光线透过率)和第一部分透过区域(60％光线透过率)在衬底基板100上投影重叠的区域为光刻胶非保留区，其余区域为所述光刻胶保留区，此时与完全透过区域(100％光线透过率)和第一部分透过区域(60％光线透过率)对应的第一光刻胶层20的光刻胶发生变性，通过显影去除该部分光刻胶；对第二导电膜层进行刻蚀，形成薄膜晶体管的源极501a和漏极501b、第二辅助电极400、数据线700和辅助电极线800，并去除剩余的光刻胶201b，也即形成第二导电图案。此时，所形成薄膜晶体管的源极501a和漏极501b的长度为第二距离L2(L2＜L1)；所述第二辅助电极400的面积为第二面积S2(S2＜S1)。
参照图8和图12，当像素的工作频段要求为第三预设频段，步骤S14可以包括：在第一层间绝缘层900背离衬底基板100的一侧，依次形成第二导电薄膜40和第一光刻胶层20采用不同透过率区域的掩膜版10对第一光刻胶层20进行曝光，并控制曝光时间为T3(T3＞T2)，以使第一光刻胶层20与完全透过区域(100％光线透过率)、第一部分透过区(60％光线透过率)域和第二部分透过区域(30％光线透过率)在衬底基板100上投影重叠的区域为光刻胶非保留区，其余区域为所述光刻胶保留区，此时与完全透过区域(100％光线透过率)、第一部分透过区域(60％光线透过率)和第二部分透过区域(30％光线透过率)对应的第一光刻胶层20的光刻胶发生变性，通过显影去除该部分光刻胶；对第二导电膜层进行刻蚀，形成薄膜晶体管的源极501a和漏极501b、第二辅助电极400、数据线700和辅助电极线800，并去除剩余的光刻胶201c，也即形成第二导电图案。此时，所形成薄膜晶体管的源极501a和漏极501b的长度为第三距离L3(L3＜L2)；所述第二辅助电极400的面积为第二面积S3(S3＜S2)。
需要说明的是，薄膜晶体管的源极501a和漏极501b的长度决定了沟道 的宽长比，距离越大宽长比越大。第二辅助电极400的面积大小决定了第二辅助电极400和第一辅助电极300所形成的第一存储电容Cst1的大小，以及第二辅助电极400和像素电极200待形成的第二存储电容Cst2的大小。因此，上述在像素的工作频段要求为第一预设频段时，所形成薄膜晶体管500的沟道宽长比最大，第一存储电容Cst1和第二存储电容Cst2之和最大，该种显示基板可用于低频工作的产品中，例如：户外显示牌、电子标签等，可以有效降低功耗。上述在像素的工作频段要求为第二预设频段时，所形成薄膜晶体管500的沟道宽长比居中，第一存储电容Cst1和第二存储电容Cst2之和居中，该种显示基板可用于中频工作的产品。上述在像素的工作频段要求为第三预设频段时，所形成薄膜晶体管500的沟道宽长比最小，第一存储电容Cst1和第二存储电容Cst2之和最小，该种显示基板可用于高频工作的产品，例如：电子书等，可有效的避免显示延迟。
S15、在第二导电图案上形成第二层间绝缘层1000，并形成贯穿第二层间绝缘层100的第二过孔c和第二子过孔b；且第一子过孔a和第二子过孔b在衬底基板上的正投影至少部分重叠。
在一些示例中，该第二层间绝缘层1000的材料可以为二氧化硅、氮化硅或者高介电常数材料等。
在一些示例中，步骤S15可以包括在形成有第二导电图案的衬底基板100上通过沉积、涂敷、溅射等多种方式中的任一种形成第二绝缘薄膜，然后对该第二绝缘薄膜执行一次构图工艺以形成第二层间绝缘层1000。
S16、在第二层间绝缘层1000上形成像素电极200，该像素电极200通过第一子过孔a和第二子过孔b与第一辅助电极300连接，同时通过第二过孔c与薄膜晶体管的漏极501b连接。
在一些示例中，该像素电极200的材料可以包括：氧化铟锡(英文：Indium tin oxide；简称：ITO)或氧化铟锌(英文：Indium Zinc Oxide；简称：IZO)等透明导电材料。
在一些示例中，步骤S16可以包括在形成有第二层间绝缘层1000的衬底基板100上通过沉积、涂敷、溅射等多种方式中的任一种形成像素电极薄膜，然后对该像素电极薄膜进行一次构图工艺以形成像素电极200。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描 述的显示基板中各个结构的工作原理以及连接关系，可以参考前述显示基板的结构的实施例中的对应内容，在此不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (18)

  1. 一种显示基板的制备方法，所述显示基板具有多个像素，所述制备方法包括：
    提供一衬底基板；其中，
    在所述衬底基板上形成第一导电薄膜，并对所述第一导电薄膜图案化形成薄膜晶体管的栅极和第一辅助电极；
    在所述第一辅助电极背离所述衬底基板的一侧形成第一层间绝缘层；
    在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用具有不同透过率区域的掩膜版对第一光刻胶层曝光预定时间，以形成薄膜晶体管的源极和漏极，以及第二辅助电极，其中，所述第一辅助电极与所述第二辅助电极在所述衬底基板上的正投影重叠，以形成第一存储电容；
    在所述第二辅助电极所在层背离所述衬底基板的一侧形成第二层间绝缘层；
    对所述第一层间绝缘层和所述第二层间绝缘层进行图案化，以形成贯穿所述第一层间绝缘层和所述第二层间绝缘层的第一过孔，和贯穿所述第二层间绝缘层的第二过孔，所述第一过孔暴露所述薄膜晶体管的源极和漏极，所述第二过孔暴露所述第一辅助电极；和
    在所述第二层间绝缘层背离所述衬底基板的一侧形成像素电极；其中，
    所述像素电极通过第二过孔与所述薄膜晶体管的漏极连接；
    所述像素电极通过贯穿所述第一层间绝缘层和所述第二层间绝缘层的第一过孔与所述第一辅助电极电连接，且所述第一辅助电极与所述像素电极在所述衬底基板上的正投影至少部分重叠重叠，以形成第二存储电容。
  2. 根据权利要求1所述的显示基板的制备方法，其中，所述具有不同透过率区域的掩膜版包括完全透光区域、非透光区域、多个部分透光区域；所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用所述具有不同透过率区域的掩膜版对第一光刻胶层 进行曝光预定时间，以形成薄膜晶体管的源极和漏极，以及第二辅助电极，具体包括：
    根据所述显示面板的工作频段要求得到所述第一存储电容和所述第二存储电容，以得到所述第二辅助电极在所述衬底基板上的投影面积；
    控制曝光时间，以控制所述多个部分透光区域的光线射出量，从而控制第一光刻胶层的光刻胶保留区的大小；
    去除第一光刻胶层中光刻胶非保留区的光刻胶，并刻蚀、显影形成薄膜晶体管的源极和漏极，以及第二辅助电极。
  3. 根据权利要求2所述的显示基板的制备方法，其中，所述多个部分透光区域包括包括第一部分透光区域和第二部分透过光区域，且所述第一部分透光区域的光线透过率大于第二部分透光区域的光线透过率；
    当所述像素的工作频段要求为第一预设频段时，所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极的步骤，具体包括：
    在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层；
    采用所述具有不同透过率区域的掩膜版对所述第一光刻胶层进行曝光，并控制曝光时间为T1，以使所述第一光刻胶层与所述完全透过区域在所述衬底基板上投影重叠的区域为所述光刻胶非保留区，其余区域为所述光刻胶保留区；
    去除所述第一光刻胶层的所述光刻胶非保留区的光刻胶；
    对所述第二导电薄膜进行刻蚀、显影，形成所述薄膜晶体管的源极和漏极，以及所述第二辅助电极，并去除剩余的光刻胶；所述薄膜晶体管的源极和漏极的长度为第一距离L1；所述第二辅助电极的面积为第一面积S1；
    当所述像素的工作频段要求为第二预设频段时，所述在所述第一层间绝 缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极，具体包括：
    在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层；
    采用所述不同透过率区域的掩膜版对所述第一光刻胶层进行曝光，并控制曝光时间为T2，以使所述第一光刻胶层与所述完全透过区域和第一部分透光区域在所述衬底基板上投影重叠的区域为所述光刻胶非保留区，其余区域为所述光刻胶保留区；
    去除所述第一光刻胶层的所述光刻胶非保留区的光刻胶；
    对所述第二导电薄膜进行刻蚀，形成所述薄膜晶体管的源极和漏极，以及所述第二辅助电极，并去除剩余的光刻胶；所述薄膜晶体管的源极和漏极的长度为第二距离L2；所述第二辅助电极的面积为第二面积S2；
    当所述像素的工作频段要求为第三预设频段时，所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极图形的步骤，具体包括：
    在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层；
    采用所述不同透过率区域的掩膜版对所述第一光刻胶层进行曝光，并控制曝光时间为T3，以使所述第一光刻胶层与所述完全透过区域、第一部分透光区域和第二部分透光区域在所述衬底基板上投影重叠的区域为所述光刻胶非保留区，其余区域为所述光刻胶保留区；
    去除所述第一光刻胶层的所述光刻胶非保留区的光刻胶；
    对所述第二导电薄膜进行刻蚀，形成所述薄膜晶体管的源极和漏极，以 及所述第二辅助电极，并去除剩余的光刻胶；所述薄膜晶体管的源极和漏极的长度为第三距离L3；所述第二辅助电极的面积为第三面积S3；
    其中，所述第一预设频段的最大值小于所述第二预设频段的最小值，且所述第二预设频段的最大值小于所述第三预设频段的最小值；T1＜T2＜T3；L3＜L2＜L1；S3＜S2＜S1。
  4. 根据权利要求1-3中任一项所述的显示基板的制备方法，其中，所述在所述衬底基板上形成第一辅助电极的同时，还包括形成所述薄膜晶体管的栅极。
  5. 根据权利要求1-3中任一项所述的显示基板的制备方法，其中，
    位于同一列像素的所述第二辅助电极连接同一条辅助电极线，被配置为施加公共电压信号。
  6. 根据权利要求1-3中任一项所述的显示基板的制备方法，其中，在所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极的步骤之前，还包括：
    在所述第一层间绝缘层背离所述衬底基板的一侧形成所述薄膜晶体管的有源层。
  7. 根据权利要求1-3中任一项所述的显示基板的制备方法，其中，在所述在所述第一层间绝缘层背离所述衬底基板的一侧，依次形成第二导电薄膜和第一光刻胶层，采用不同透过率区域的掩膜版对第一光刻胶层进行曝光，并根据所述像素的工作频段要求控制曝光时间，形成薄膜晶体管的源极和漏极，以及第二辅助电极的同时，还包括：
    形成数据线和辅助电极线，且所述数据线与所述薄膜晶体管的源极电连接；所述辅助电极线与所述第二辅助电极连接。
  8. 根据权利要求7所述的显示基板的制备方法，其中，所述数据线与所述辅助电极线的延伸方向平行或者大致平行。
  9. 根据权利要求1-3中任一项所述的显示基板的制备方法，其中，所述像素包括两个串接的所述薄膜晶体管。
  10. 一种显示基板，所述显示基板具有多个像素，其特征在于，在至少一个像素中，所述显示基板包括：
    衬底基板；
    位于所述衬底基板上的薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极；
    依次设置在所述衬底基板上的第一辅助电极、第二辅助电极和像素电极，所述第一辅助电极、所述第二辅助电极和像素电极在所述衬底基板上的正投影至少部分重叠；
    第一层间绝缘层，位于所述第一辅助电极和所述第二辅助电极所在层之间，以使所述第一辅助电极和所述第二辅助电极绝缘；和
    第二层间绝缘层，位于所述第二辅助电极和所述像素电极所在层之间，以使所述第一辅助电极和所述像素电极绝缘；其中，
    所述第二辅助电极和所述薄膜晶体管的源极和漏极同层设置，且材料相同，所述像素电极通过贯穿所述所述第二层间绝缘层的第一过孔与所述薄膜晶体管的漏极连接，所述像素电极通过贯穿所述第一层间绝缘层和所述第二层间绝缘层的第二过孔与所述第一辅助电极电连接。
  11. 根据权利要求10所述的显示基板，其中，当所述像素的工作频段为第一预设频段时，所述薄膜晶体管的源极和漏极的长度为第一距离L1；所述第二辅助电极的面积为第一面积S1；
    当所述像素的工作频段为第二预设频段时，所述薄膜晶体管的源极和漏极的长度为第二距离L2；所述第二辅助电极的面积为第二面积S2；
    当所述像素的工作频段为第三预设频段时，所述薄膜晶体管的源极和漏极的长度为第一距离L3；所述第二辅助电极的面积为第一面积S3；
    其中，所述第一预设频段的最大值小于所述第二预设频段的最小值，且 所述第二预设频段的最大值小于所述第三预设频段的最小值；L3＜L2＜L1；S3＜S2＜S1。
  12. 根据权利要求10所述的显示基板，其中，位于同一列像素的所述第二辅助电极连接同一条辅助电极线，被配置为施加公共电压信号。
  13. 根据权利要求10所述的显示基板，其中，所述第一辅助电极与所述薄膜晶体管的栅极同层设置，且材料相同。
  14. 根据权利要求10所述的显示基板，其中，还包括数据线和辅助电极线，所述数据线、所述辅助电极线与所述第二辅助电极同层设置，且材料相同；且所述数据线与所述薄膜晶体管的源极电连接；所述辅助电极线与所述第二辅助电极连接。
  15. 根据权利要求14所述的显示基板，其中，所述数据线与所述辅助电极线的延伸方向平行或者大致平行。
  16. 根据权利要求10-15中任一项所述的显示基板，其中，所述像素包括两个串接的所述薄膜晶体管。
  17. 一种显示装置，其包括权利要求10-16中任一项所述的显示基板。
  18. 根据权利要求17所述的显示装置，其中，所述显示装置为电子纸显示装置，所述电子纸显示装置还包括和所述显示基板相对设置的盖板，以及位于所述显示基板和所述盖板之间的电泳层。
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