WO2022127445A1 - 电子纸 - Google Patents

电子纸 Download PDF

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Publication number
WO2022127445A1
WO2022127445A1 PCT/CN2021/129584 CN2021129584W WO2022127445A1 WO 2022127445 A1 WO2022127445 A1 WO 2022127445A1 CN 2021129584 W CN2021129584 W CN 2021129584W WO 2022127445 A1 WO2022127445 A1 WO 2022127445A1
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WO
WIPO (PCT)
Prior art keywords
auxiliary electrode
substrate
electrode
electronic paper
array substrate
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PCT/CN2021/129584
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English (en)
French (fr)
Inventor
罗皓
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/915,110 priority Critical patent/US20230152657A1/en
Priority to DE112021002242.3T priority patent/DE112021002242T5/de
Publication of WO2022127445A1 publication Critical patent/WO2022127445A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G02F1/16766—Electrodes for active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1685—Operation of cells; Circuit arrangements affecting the entire cell

Definitions

  • the present application relates to the field of display technology, and in particular, to an electronic paper.
  • Electronic paper is a new type of display device, which is mainly used in electronic labels, billboards and electronic readers.
  • the display effect of the electronic paper is close to that of natural paper, which can reduce visual fatigue during reading.
  • electronic paper may generally include: an array substrate and a cover plate arranged oppositely, and an electrophoretic layer located between the array substrate and the cover plate.
  • the array substrate has a plurality of pixels arranged in an array, and each pixel may include a pixel electrode and an auxiliary electrode insulated from the pixel electrode.
  • the pixel electrode and the auxiliary electrode can form a storage capacitor during display, so as to maintain the stability of the voltage loaded on the pixel electrode.
  • the embodiments of the present application provide an electronic paper.
  • the problem of poor display effect of electronic paper in the related art can be solved, and the technical solution is as follows:
  • an electronic paper comprising:
  • an array substrate and a cover plate arranged oppositely, and an electrophoretic layer located between the array substrate and the cover plate;
  • the array substrate includes: a substrate, a pixel electrode located on the substrate, a first auxiliary electrode located on the substrate and electrically connected to the pixel, and the pixel electrode and the first auxiliary electrode a second auxiliary electrode between electrodes, the second auxiliary electrode is insulated from the pixel electrode and the first auxiliary electrode respectively;
  • the orthographic projection of the second auxiliary electrode on the substrate has an overlapping area with the orthographic projection of the pixel electrode on the substrate, and overlaps with the orthographic projection of the first auxiliary electrode on the substrate There is an overlapping area of the orthographic projections on .
  • the array substrate further includes: a thin film transistor, and the thin film transistor includes: a source and drain electrode electrically connected to the pixel electrode;
  • the source and drain electrodes are arranged in the same layer as the first auxiliary electrode and have the same material; or, the source and drain electrodes are arranged in the same layer as the second auxiliary electrode and have the same material.
  • the thin film transistor further includes: a gate;
  • the gate electrode and the first auxiliary electrode are arranged in the same layer and have the same material; the source and drain electrodes are arranged in the same layer as the second auxiliary electrode and have the same material.
  • the thin film transistor further includes: an active layer insulated from the gate;
  • the active layer is overlapped with the source and drain, and the source and drain are located on the side of the active layer away from the substrate, and the gate is located on the active layer close to the side of the substrate.
  • the array substrate has a plurality of pixel regions arranged in an array, and each of the pixel regions is provided with two of the thin film transistors connected in series.
  • the array substrate further includes: a gate line electrically connected to the gate, a data line electrically connected to the source and drain, and an auxiliary electrode line electrically connected to the second auxiliary electrode;
  • the extension direction of the gate lines intersects with the extension direction of the data lines, and intersects with the extension direction of the auxiliary electrode lines.
  • the extension direction of the data lines is perpendicular to the extension direction of the gate lines, and is parallel to the extension direction of the auxiliary electrode lines.
  • the width of the data line is smaller than the width of the auxiliary electrode line.
  • the array substrate further includes: a first insulating layer located between the second auxiliary electrode and the first auxiliary electrode, and a first insulating layer located between the second auxiliary electrode and the pixel electrode. two insulating layers;
  • the first insulating layer has a first via hole
  • the second insulating layer has a second via hole communicating with the first via hole
  • the pixel electrode passes through the first via hole and the first via hole.
  • the two via holes are electrically connected to the first auxiliary electrode.
  • the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the second via hole on the substrate.
  • the orthographic projection of the second auxiliary electrode on the substrate is located within the orthographic projection of the first auxiliary electrode on the substrate, and the first auxiliary electrode is on the substrate.
  • the orthographic projection on the pixel electrode is located within the orthographic projection of the pixel electrode on the substrate.
  • the area of the orthographic projection of the first auxiliary electrode on the substrate is smaller than the area of the orthographic projection of the pixel electrode on the substrate.
  • the electronic paper includes: an array substrate, a cover plate and an electrophoretic layer. Since the first auxiliary electrode in the array substrate is electrically connected to the pixel electrode, when the electronic paper is displaying, the voltage applied to the first auxiliary electrode is the same as the voltage applied to the pixel electrode, which is the pixel voltage, that is, Yes, the first auxiliary electrode is also equivalent to the pixel electrode. In this way, when the electronic paper is displayed, the first auxiliary electrode and the second auxiliary electrode can form a first storage capacitor, and the pixel electrode and the second auxiliary electrode can form a second storage capacitor.
  • the electronic paper provided by the embodiment of the present application increases the capacitance value of the storage capacitor without changing the PPI of the electronic paper, improves the stability of the voltage loaded on the pixel electrode, and further improves the performance of the electronic paper.
  • the display effect of the electronic paper is adopted.
  • FIG. 1 is a schematic diagram of a film layer structure of an array substrate in an electronic paper provided by the related art
  • FIG. 2 is a top view of the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a film layer structure of an electronic paper provided in an embodiment of the present application.
  • FIG. 4 is a top view of the array substrate in the electronic paper shown in FIG. 3;
  • FIG. 5 is a top view of an array substrate in another electronic paper provided by an embodiment of the present application.
  • FIG. 6 is a cross-sectional view of the array substrate shown in FIG. 5 at D-D';
  • FIG. 7 is a schematic diagram of a film layer structure of another electronic paper provided in an embodiment of the present application.
  • FIG. 1 is a schematic diagram of the film layer structure of an array substrate in an electronic paper provided by the related art.
  • the array substrate 00 may include: a substrate 01, and a substrate 01 located on the substrate A first conductive pattern 02 , a first insulating layer 03 , an active layer 04 , a second conductive pattern 05 , a second insulating layer 06 and a pixel electrode 07 are stacked in a direction perpendicular to and away from the substrate 01 .
  • the first conductive pattern 02 may include a gate electrode 021 and a first auxiliary electrode 022
  • the second conductive pattern 05 may include a source drain 051 and a second auxiliary electrode 052 .
  • the second auxiliary electrode 052 is electrically connected to one of the source electrode and the drain electrode of the source and drain electrodes 051 , and the second auxiliary electrode 052 is electrically connected to the pixel electrode 07 through a via hole on the second insulating layer 06 .
  • FIG. 2 is a top view of the array substrate shown in FIG. 1 .
  • the orthographic projection of the first auxiliary electrode 022 on the substrate 01 and the orthographic projection of the second auxiliary electrode 052 on the substrate 01 have an overlapping area A.
  • the second auxiliary electrode 052 is connected to the pixel electrode 07 through the via hole on the second insulating layer 06, when the electronic paper prepared by the array substrate 00 is used for display, the voltage loaded on the second auxiliary electrode 052 is different from the voltage applied to the second auxiliary electrode 052.
  • the voltages applied to the pixel electrodes 07 are the same, which are the pixel voltages, that is, the second auxiliary electrodes 052 are equivalent to the pixel electrodes.
  • the first auxiliary electrode 022 and the second auxiliary electrode 052 can form a storage capacitor Cst' to maintain the stability of the voltage loaded on the pixel electrode 07.
  • the larger the capacitance value of Cst' is, the better the effect of maintaining the stability of the voltage applied to the pixel electrode 07 is.
  • FIG. 3 is a schematic diagram of a film layer structure of an electronic paper provided by an embodiment of the present application.
  • the electronic paper may include:
  • the array substrate 000 and the cover plate 001 arranged oppositely, and the electrophoretic layer 002 located between the array substrate 000 and the cover plate 001 .
  • the array substrate 000 may include:
  • the pixel electrode 200 is located on the substrate 100 .
  • the first auxiliary electrode 300 is located on the substrate 100 and is electrically connected to the pixel electrode 200 .
  • the second auxiliary electrode 400 is located between the pixel electrode 200 and the first auxiliary electrode 300 , and the second auxiliary electrode 400 is insulated from the pixel electrode 200 and the first auxiliary electrode 300 respectively.
  • FIG. 4 is a top view of the array substrate in the electronic paper shown in FIG. 3 .
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 has an overlap region B with the orthographic projection of the pixel electrode 200 on the substrate 100 , and also exists with the orthographic projection of the first auxiliary electrode 300 on the substrate 100 Overlap area C.
  • the first auxiliary electrode 300 is electrically connected to the pixel electrode 200, when the electronic paper where the array substrate is located is displayed, the voltage applied to the first auxiliary electrode 300 is the same as the voltage applied to the pixel electrode 200, and both are pixels The voltage, that is, the first auxiliary electrode 300 also corresponds to the pixel electrode. In this way, when the electronic paper is displayed, the first auxiliary electrode 300 and the second auxiliary electrode 400 can form the first storage capacitor Cst1, and the pixel electrode 200 and the second auxiliary electrode 400 can form the second storage capacitor Cst2.
  • the second auxiliary electrode 400 is between the pixel electrode 200 and the first auxiliary electrode 300, the first storage capacitor Cst1 formed by the second auxiliary electrode 400 and the first auxiliary electrode 300, and the second auxiliary electrode 400 and the pixel
  • the second storage capacitor Cst2 formed by the electrode 200 is connected in parallel.
  • the capacitance value of the total storage capacitor in the array substrate 000 is the sum of the capacitance value of the first storage capacitor Cst1 and the capacitance value of the second storage capacitor Cst1. Therefore, the capacitance value of the total storage capacitor in the array substrate 000 is relatively large.
  • the orthographic projection of the first auxiliary electrode 022 on the substrate 01 and the overlapping area A between the orthographic projection of the second auxiliary electrode 052 on the substrate 01 The area is S.
  • the thickness of the first insulating layer 03 between the first auxiliary electrode 022 and the second auxiliary electrode 052 may be 4000 angstroms, the material of the first insulating layer 03 may include silicon nitride, and the relative permittivity of the first insulating layer 03 may be 6.5.
  • the capacitance value Ci' of the storage capacitor Cst' can be calculated as:
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 and the orthographic projection of the pixel electrode 200 on the substrate 100 overlap the area B.
  • the area is also S
  • the area of the overlapping region C between the orthographic projection of the second auxiliary electrode 400 on the substrate 100 and the orthographic projection of the first auxiliary electrode 300 on the substrate 100 is also S.
  • the capacitance value Ci 1 of the first storage capacitor Cst1 is related to The capacitance values Ci' of the storage capacitors Cst' in the technology are equal in size.
  • the thickness of the insulating layer between the second auxiliary electrode 400 and the pixel electrode 200 may range from 2000 to 6000 angstroms.
  • the insulating layer has the same material as the first insulating layer 03 and has a relative permittivity of 6.5.
  • the maximum value Ci 2 of the capacitance value of the second storage capacitor Cst2, max is:
  • the range of the capacitance value Ci of the total storage capacitor in the array substrate 000 is:
  • the capacitance value Ci of the total storage capacitor in the array substrate 000 provided by the embodiment of the present application can be increased by 67% to 192%.
  • the electronic paper provided in the embodiments of the present application includes: an array substrate, a cover plate, and an electrophoretic layer. Since the first auxiliary electrode in the array substrate is electrically connected to the pixel electrode, when the electronic paper is displaying, the voltage applied to the first auxiliary electrode is the same as the voltage applied to the pixel electrode, which is the pixel voltage, that is, Yes, the first auxiliary electrode is also equivalent to the pixel electrode. In this way, when the electronic paper is displayed, the first auxiliary electrode and the second auxiliary electrode can form a first storage capacitor, and the pixel electrode and the second auxiliary electrode can form a second storage capacitor.
  • the electronic paper provided by the embodiment of the present application increases the capacitance value of the storage capacitor without changing the PPI of the electronic paper, improves the stability of the voltage loaded on the pixel electrode, and further improves the performance of the electronic paper.
  • the display effect of the electronic paper is adopted.
  • FIG. 5 is a top view of an array substrate in another electronic paper provided by the embodiment of the present application
  • FIG. 6 is the array substrate shown in FIG. 5 at D-D ' section view.
  • the array substrate 000 may further include: a thin film transistor 500 (English: Thin-film transistor; TFT for short), and the thin film transistor 500 may include: a source and drain electrode 501 electrically connected to the pixel electrode 200 .
  • the source and drain electrodes 501 and the first auxiliary electrodes 300 may be disposed in the same layer and made of the same material, that is, the source and drain electrodes 501 and the first auxiliary electrodes 300 may be formed through a single patterning process .
  • the source and drain electrodes 501 and the second auxiliary electrode 400 may also be provided in the same layer and made of the same material. That is, the source and drain electrodes 501 and the second auxiliary electrode 400 can be formed through one patterning process.
  • FIG. 5 schematically illustrates an example in which the source and drain electrodes 501 and the second auxiliary electrode 400 are provided in the same layer and are of the same material.
  • the thin film transistor 500 may further include: a gate electrode 502 .
  • the gate 502 in the thin film transistor 500 can be provided in the same layer as the first auxiliary electrode 300, and the material is the same; the source and drain electrodes 501 in the thin film transistor 500 can be provided in the same layer with the second auxiliary electrode 400, and the material is the same . That is, the gate electrode 502 and the first auxiliary electrode 300 can be formed through a single patterning process, and the source and drain electrodes 501 and the second auxiliary electrode 400 can be formed through a single patterning process. In this way, the manufacturing process of the array substrate 000 can be further simplified, and the manufacturing difficulty and manufacturing cost of the array substrate 000 can be further reduced.
  • the thin film transistor 500 may further include: an active layer 503 that is insulated from the gate electrode 502 .
  • the active layer 503 overlaps with the source and drain electrodes 501 , the source and drain electrodes 501 are located on the side of the active layer 503 away from the substrate 100 , and the gate 502 is located on the side of the active layer 503 close to the substrate 100 . That is, the thin film transistor 500 is a bottom gate thin film transistor. In other possible implementation manners, the thin film transistor 500 may also be a top-gate thin film transistor, which is not limited in this embodiment of the present application.
  • the array substrate has a plurality of pixel regions 000a arranged in an array, and each pixel region 000a is provided with two thin film transistors 500 connected in series.
  • Each of the two thin film transistors 500 may include: a source and a drain 501 .
  • Each of the source and drain electrodes 501 includes a first electrode 501a and a second electrode 501b.
  • the first electrode 501a may be one of the source electrode and the drain electrode
  • the second electrode 501b may be the other one of the source electrode and the drain electrode.
  • the first electrode 501a of one thin film transistor 500 is electrically connected to the second electrode 501b of the other thin film transistor 500, so that the two thin film transistors 500 are connected in series. In this way, the leakage current in the thin film transistor 500 can be reduced, and the influence on the pixel voltage loaded on the pixel electrode 200 can be reduced.
  • the channel region E of the active layer 503 in each thin film transistor 500 is an elongated channel region.
  • the channel region E of the active layer pattern 503 refers to the region in the active layer 503 where the active layer 503 contacts the first electrode 501a and the region where the active layer 503 contacts the second electrode 501b area in between.
  • the width of the channel region E may range from 20 to 40 microns. In this way, the charging rate requirement of the array substrate 000 can be met.
  • the array substrate may further include: a gate line 600 electrically connected to the gate electrode 502 , a data line 700 electrically connected to the source and drain electrodes 501 , and the second auxiliary electrode 400 Electrically connected auxiliary electrode lines 800 .
  • the gate line 600 , the gate electrode 502 and the first auxiliary electrode 300 are arranged in the same layer and have the same material, that is, the gate line 600 , the gate electrode 502 and the first auxiliary electrode 300 are formed through a patterning process .
  • the data line 700 , the auxiliary electrode line 800 , the source and drain electrodes 501 and the second auxiliary electrode 400 are arranged in the same layer and have the same materials, that is, the data line 700 , the auxiliary electrode line 800 , the source and drain electrodes 501 and the second auxiliary electrode
  • the electrode 400 is formed through one patterning process.
  • the extension direction of the gate line 600 intersects with the extension direction of the data line 700
  • the extension direction of the gate line 600 intersects with the extension direction of the auxiliary electrode line 800 .
  • the gate lines 600 and the data lines 700 whose extending directions intersect may define a plurality of pixel regions 000 a in the array substrate 000 .
  • any two adjacent gate lines 600 and any two adjacent data lines 700 can enclose a pixel area 000a.
  • the extension direction of the data line 700 may be perpendicular to the extension direction of the gate line 600 , and the extension direction of the data line 700 may be parallel to the auxiliary electrode line 800 .
  • the gate lines 600 and the data lines 700 whose extending directions are vertical define a plurality of pixel regions 000 a in the array substrate 000 to be rectangular.
  • the width of the data line 700 is smaller than the width of the auxiliary electrode line 800 .
  • the width of the data line 700 is small, which can reduce the overlapping area of the data line 700 and the gate line 600, thereby reducing the capacitance value of the parasitic capacitance generated between the data line 700 and the gate line 600, thereby reducing the The influence of parasitic capacitance on the display effect of the electronic paper where the array substrate 000 is located. Since the voltage loaded on the auxiliary electrode line 800 is constant when the electronic paper where the array substrate 000 is located is displayed, the parasitic capacitance generated between the auxiliary electrode line 800 and the gate line 600 will not affect the electronic paper. In view of the display effect of the paper, the width of the auxiliary electrode line 800 can be larger, so as to increase the strength of the electronic paper and reduce the probability of the electronic paper being damaged during use.
  • the array substrate 000 may further include: a first insulating layer 900 between the second auxiliary electrode 400 and the first auxiliary electrode 300 , and a first insulating layer 900 between the second auxiliary electrode 400 and the pixel The second insulating layer 1000 between the electrodes 200 .
  • the first insulating layer 900 has a first via hole a
  • the second insulating layer 1000 has a second via hole b communicating with the first via hole a
  • the pixel electrode 200 passes through the first via hole a and the second via hole b is electrically connected to the first auxiliary electrode 300 .
  • the orthographic projection of the first via hole a on the substrate 100 is located within the orthographic projection of the second via hole b on the substrate 100 .
  • the second insulating layer 1000 further has a third via hole c, and the pixel electrode 200 is electrically connected to one of the first electrode 501 a and the second electrode 501 b in the source and drain electrodes 501 through the third via hole c.
  • the first insulating layer 900 can also be used as a gate insulating layer, so as to realize the insulating arrangement of the active layer 503 and the gate electrode 502 in the thin film transistor 500 .
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 is located within the orthographic projection of the first auxiliary electrode 300 on the substrate 100
  • the first auxiliary electrode 300 is located in the The orthographic projection on the substrate 100 is located within the orthographic projection of the pixel electrode 200 on the substrate 100 .
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 and the overlapping area B between the orthographic projection of the pixel electrode 200 on the substrate 100 , and the second auxiliary electrode 400 and the first auxiliary electrode 300 are on the substrate
  • the area of the overlapping region C between the orthographic projections on the bottom 100 is the area of the second auxiliary electrode 400 .
  • the orthographic projection of the second auxiliary electrode 400 on the substrate 100 , the overlapping region B between the orthographic projection of the pixel electrode 200 on the substrate 100 , and the second auxiliary electrode 400 and the first auxiliary electrode 300 The overlapping regions C between the orthographic projections on the substrate 100 coincide.
  • the capacitance value Ci of the total storage capacitor in the array substrate 000 can be changed by changing the area of the second auxiliary electrode 400 .
  • the larger the area of the second auxiliary electrode 400 is the larger the capacitance value Ci of the total storage capacitor in the array substrate 000 is; conversely, the smaller the area of the second auxiliary electrode 400 is, the larger the total storage capacitor in the array substrate 000 is.
  • the smaller the capacitance value Ci is.
  • the capacitance value Ci of the total storage capacitor in the array substrate 000 can also be changed by changing the thickness of the second insulating layer 1000 .
  • the value Ci is larger.
  • the orthographic projection of the first auxiliary electrode 300 on the substrate 100 does not have an overlapping area with the orthographic projection of the source and drain electrodes 501 on the substrate 100 , so that the first auxiliary electrode 300 and the Electric field interference is generated between the source and drain electrodes 501 .
  • FIG. 7 is a schematic diagram of a film layer structure of another electronic paper provided by the embodiment of the present application.
  • the cover plate 001 in the electronic paper may include: a second substrate 0011 , and a common electrode 0012 located on the second substrate 0011 , wherein the common electrode 0012 faces the pixel electrode 200 in the array substrate 000 .
  • the electrophoresis layer 002 in the electronic paper may include: a plurality of electrophoresis capsules 0021, each electrophoresis capsule 0021 may include: a capsule body, and electrophoretic liquid and charged particles located in the capsule body, and the charged particles may include: black particles, White particles and colored particles, etc.
  • the area of the orthographic projection of the first auxiliary electrode 300 in the array substrate 000 on the substrate 100 is smaller than the area of the orthographic projection of the pixel electrode 200 on the substrate 100 .
  • the pixel electrode 200 can shield the first auxiliary electrode 300 from the electric field, so as to prevent the electric field from being generated between the first auxiliary electrode 300 and the common electrode 0012 in the cover plate 001 .
  • the display effect of electronic paper is affected.
  • the electronic paper provided in the embodiments of the present application includes: an array substrate, a cover plate, and an electrophoretic layer. Since the first auxiliary electrode in the array substrate is electrically connected to the pixel electrode, when the electronic paper is displaying, the voltage applied to the first auxiliary electrode is the same as the voltage applied to the pixel electrode, which is the pixel voltage, that is, Yes, the first auxiliary electrode is also equivalent to the pixel electrode. In this way, when the electronic paper is displayed, the first auxiliary electrode and the second auxiliary electrode can form a first storage capacitor, and the pixel electrode and the second auxiliary electrode can form a second storage capacitor.
  • the electronic paper provided by the embodiment of the present application increases the capacitance value of the storage capacitor without changing the PPI of the electronic paper, improves the stability of the voltage loaded on the pixel electrode, and further improves the performance of the electronic paper.
  • the display effect of the electronic paper is adopted.
  • An embodiment of the present application provides a method for manufacturing an array substrate.
  • the manufacturing method of the array substrate is used to manufacture the array substrate shown in FIG. 5 above.
  • the manufacturing method of the array substrate may include:
  • Step A forming a first conductive pattern on the substrate.
  • the material of the first conductive pattern may include: metal molybdenum (abbreviation: Mo), metal titanium (abbreviation: Ti), metal copper (abbreviation: Cu), metal aluminum (abbreviation: Al) or alloy materials. to make.
  • the first conductive pattern may include a gate electrode, a gate line and a first auxiliary electrode.
  • the first conductive thin film can be formed on the substrate by any one of deposition, coating, sputtering, etc., and then a patterning process is performed on the first conductive thin film to form a first conductive pattern, the One patterning process may include photoresist coating, exposure, development, etching, and photoresist stripping.
  • Step B forming a first insulating layer on the first conductive pattern.
  • the material of the gate insulating layer may be silicon dioxide, silicon nitride, or a high dielectric constant material, or the like.
  • a first insulating film may be formed on the substrate formed with the first conductive pattern by any one of deposition, coating, sputtering, etc., and then a patterning process is performed on the first insulating film to For forming the gate insulating layer, the one-time patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.
  • Step C forming an active layer on the first insulating layer.
  • the active layer material may include semiconductor materials such as polysilicon, amorphous silicon, or oxide semiconductor.
  • an active layer thin film may be formed on the substrate formed with the first insulating layer by any one of deposition, coating, sputtering and other methods, and then a patterning process is performed on the active layer thin film to An active layer is formed.
  • the one-time patterning process may include photoresist coating, exposure, development, etching, and photoresist stripping.
  • Step D forming a second conductive pattern on the active layer.
  • the material of the second conductive pattern may include: metal Mo, metal Ti, metal Cu, metal aluminum Al or an alloy material.
  • the second conductive pattern may include: source and drain electrodes, second auxiliary electrodes, data lines and auxiliary electrode lines.
  • the second conductive film may be formed on the substrate on which the active layer pattern is formed by any one of deposition, coating, sputtering and other methods, and then a patterning process is performed on the second conductive film to To form the second conductive pattern, the one-time patterning process may include: photoresist coating, exposure, development, etching, and photoresist stripping.
  • Step E forming a second insulating layer on the second conductive pattern.
  • the material of the second insulating layer may be silicon dioxide, silicon nitride, or a high dielectric constant material or the like.
  • a second insulating film may be formed on the substrate formed with the second conductive pattern by any one of deposition, coating, sputtering and other methods, and then a patterning process is performed on the second insulating film to To form the second insulating layer, the one-time patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.
  • Step F forming a pixel electrode on the second insulating layer.
  • the material of the pixel electrode may include transparent conductive materials such as indium tin oxide (English: Indium tin oxide; ITO for short) or indium zinc oxide (English: Indium Zinc Oxide; IZO for short).
  • transparent conductive materials such as indium tin oxide (English: Indium tin oxide; ITO for short) or indium zinc oxide (English: Indium Zinc Oxide; IZO for short).
  • a pixel electrode film can be formed on the substrate formed with the second insulating layer by any one of deposition, coating, sputtering and other methods, and then a patterning process is performed on the pixel electrode film to form a pixel. Electrodes, the one patterning process may include: photoresist coating, exposure, development, etching and photoresist stripping.
  • the embodiment of the present application also provides a display device, the display device may include the electronic paper in the above embodiments, and the display device may be an electronic label, a billboard, an electronic reader, and the like.
  • the term “same layer” refers to the relationship between layers formed simultaneously in the same step, for example, when the source and drain electrodes and the first auxiliary electrode are one or more layers that perform the same patterning process in the same layer of material When formed in one step, they are in the same layer.
  • the source and drain electrodes and the first auxiliary electrode may be formed in the same layer by simultaneously performing the step of forming the source and drain electrodes and the step of forming the first auxiliary electrode.
  • the term “same layer” does not always mean that the thickness of the layer or the layers in the cross-sectional view are the same.

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Abstract

本申请公开了一种电子纸，属于显示技术领域。该电子纸包括：阵列基板、盖板和电泳层。由于阵列基板中的第一辅助电极与像素电极电连接，因此，该第一辅助电极也相当于像素电极。如此，在该电子纸进行显示时，第一辅助电极与第二辅助电极可以形成第一存储电容，像素电极与第二辅助电极可以形成第二存储电容。该第一存储电容和第二存储电容并联，该阵列基板中的总存储电容值为第一存储电容的电容值与第二存储电容的电容值之和。与相关技术相比，本申请实施例提供的电子纸，增大了存储电容的电容值，提高了像素电极上加载的电压的稳定性，进而提高了采用该电子纸的显示效果。

Description

电子纸
本申请要求于2020年12月18日提交的申请号为202011500714.0、发明名称为“电子纸”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种电子纸。
背景技术
电子纸是一种新型的显示器件，主要用于电子标签、广告牌和电子阅读器等设备中。该电子纸的显示效果接近自然纸张的效果，可降低阅读时的视觉疲劳。
在相关技术中，电子纸通常可以包括：相对设置的阵列基板和盖板，以及位于阵列基板和盖板之间的电泳层。该阵列基板具有阵列排布的多个像素，每个像素可以包括：像素电极，以及与该像素电极绝缘设置的辅助电极。该像素电极和辅助电极能够在显示时形成存储电容，以维持该像素电极上加载的电压的稳定性。
但是，随着阵列基板中每英寸像素个数(英文：Pixels Per Inch；简称：PPI)的不断提高，阵列基板中的每个像素电极的尺寸不断减小，导致像素电极与辅助电极之间交叠面积不断减小，进而导致该像素电极与辅助电极之间形成的存储电容的电容值不断减小。如此，会影响像素电极上加载的电压的稳定性，导致采用该阵列基板制备出的电子纸的显示效果较差。
发明内容
本申请实施例提供了一种电子纸。可以解决相关技术中的电子纸的显示效果较差问题，所述技术方案如下：
一方面，提供了一种电子纸，所述电子纸包括：
相对设置的阵列基板和盖板，以及位于所述阵列基板和所述盖板之间的电泳层；
所述阵列基板包括：衬底，位于所述衬底上的像素电极，位于所述衬底上且与所述像素电连接的第一辅助电极，以及位于所述像素电极和所述第一辅助电极之间的第二辅助电极，所述第二辅助电极分别与所述像素电极以及所述第一辅助电极绝缘；
其中，所述第二辅助电极在所述衬底上的正投影，与所述像素电极在所述衬底上的正投影存在交叠区域，且与所述第一辅助电极在所述衬底上的正投影存在交叠区域。
可选的，所述阵列基板还包括：薄膜晶体管，所述薄膜晶体管包括：与所述像素电极电连接的源漏极；
其中，所述源漏极与所述第一辅助电极同层设置，且材料相同；或者，所述源漏极与所述第二辅助电极同层设置，且材料相同。
可选的，所述薄膜晶体管还包括：栅极；
其中，所述栅极与所述第一辅助电极同层设置，且材料相同；所述源漏极与所述第二辅助电极同层设置，且材料相同。
可选的，所述薄膜晶体管还包括：与所述栅极绝缘设置的有源层；
其中，所述有源层与所述源漏极搭接，且所述源漏极位于所述有源层远离所述衬底的一侧，所述栅极位于所述有源层靠近所述衬底的一侧。
可选的，所述阵列基板具有阵列排布的多个像素区域，每个所述像素区域设置有串联的两个所述薄膜晶体管。
可选的，所述阵列基板还包括：与所述栅极电连接的栅线，与所述源漏极电连接的数据线，以及与所述第二辅助电极电连接的辅助电极线；
其中，所述栅线的延伸方向与所述数据线的延伸方向相交，且与所述辅助电极线的延伸方向相交。
可选的，所述数据线的延伸方向与所述栅线的延伸方向垂直，且与所述辅助电极线的延伸方向平行。
可选的，所述数据线的宽度小于所述辅助电极线的宽度。
可选的，所述阵列基板还包括：位于所述第二辅助电极与所述第一辅助电极之间的第一绝缘层，以及位于所述第二辅助电极与所述像素电极之间的第二绝缘层；
其中，所述第一绝缘层具有第一过孔，所述第二绝缘层具有与所述第一过孔连通的第二过孔，所述像素电极通过所述第一过孔和所述第二过孔与所述第 一辅助电极电连接。
可选的，所述第一过孔在所述衬底上的正投影，位于所述第二过孔在所述衬底上的正投影内。
可选的，所述第二辅助电极在所述衬底上的正投影，位于所述第一辅助电极在所述衬底上的正投影内，且所述第一辅助电极在所述衬底上的正投影，位于所述像素电极在所述衬底上的正投影内。
可选的，所述第一辅助电极在所述衬底上的正投影的面积，小于所述像素电极在所述衬底上的正投影的面积。
本申请实施例提供的技术方案带来的有益效果至少包括：
该电子纸包括：阵列基板、盖板和电泳层。由于阵列基板中的第一辅助电极与像素电极电连接，因此，在该电子纸进行显示时，第一辅助电极上加载的电压，与像素电极上加载的电压相同，均为像素电压，也即是，第一辅助电极也相当于像素电极。如此，在该电子纸进行显示时，第一辅助电极与第二辅助电极可以形成第一存储电容，像素电极与第二辅助电极可以形成第二存储电容。该第一存储电容和第二存储电容并联，该阵列基板中的总存储电容值为第一存储电容的电容值与第二存储电容的电容值之和。与相关技术相比，本申请实施例提供的电子纸，在不改变电子纸的PPI的情况下，增大了存储电容的电容值，提高了像素电极上加载的电压的稳定性，进而提高了采用该电子纸的显示效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术提供的一种电子纸中的阵列基板的膜层结构示意图；
图2是图1示出的阵列基板的俯视图；
图3是本申请实施例提供的一种电子纸的膜层结构示意图；
图4是图3示出的电子纸中的阵列基板的俯视图；
图5是本申请实施例提供的另一种电子纸中的阵列基板的俯视图；
图6是图5示出的阵列基板在D-D’处的截面图；
图7是本申请实施例提供的另一种电子纸的膜层结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
在相关技术中，请参考图1，图1是相关技术提供的一种电子纸中的阵列基板的膜层结构示意图，该阵列基板00可以包括：衬底01，以及位于衬底01上且沿垂直且远离衬底01的方向层叠设置第一导电图案02、第一绝缘层03、有源层04、第二导电图案05、第二绝缘层06以及像素电极07。其中，该第一导电图案02可以包括：栅极021和第一辅助电极022，该第二导电图案05可以包括：源漏极051和第二辅助电极052。第二辅助电极052与源漏极051中的源极和漏极中的一个电连接，且第二辅助电极052与像素电极07通过第二绝缘层06上的过孔电连接。
请参考图2，图2是图1示出的阵列基板的俯视图。该阵列基板00中，第一辅助电极022在衬底01上的正投影，与第二辅助电极052在衬底01上的正投影存在交叠区域A。
由于第二辅助电极052与像素电极07通过第二绝缘层06上的过孔连接，因此，在采用该阵列基板00制备出的电子纸进行显示时，第二辅助电极052上加载的电压，与像素电极07上加载的电压相同，均为像素电压，也即是，第二辅助电极052相当于像素电极。如此，在采用该阵列基板00制备出的电子纸进行显示时，第一辅助电极022与第二辅助电极052可以形成存储电容Cst’，维持像素电极07上加载的电压的稳定性，该存储电容Cst’的电容值越大，维持像素电极07上加载的电压的稳定性的效果越好。
但是，随着阵列基板中每英寸像素个数(英文：Pixels Per Inch；简称：PPI)的不断提高，阵列基板00中每个像素的尺寸不断减小，导致第一辅助电极022与第二辅助电极052之间交叠面积不断减小，进而导致存储电容Cst’的电容值不断减小。如此，会影响像素电极上加载的电压的稳定性，导致采用该阵列基板制备出的电子纸的显示效果较差。
请参考图3，图3是本申请实施例提供的一种电子纸的膜层结构示意图。该电子纸可以包括：
相对设置的阵列基板000和盖板001，以及位于该阵列基板000和盖板001 之间的电泳层002。
该阵列基板000可以包括：
衬底100、像素电极200、第一辅助电极300以及第二辅助电极400。
该像素电极200位于衬底100上。
该第一辅助电极300位于衬底100上且与像素电极200电连接。
该第二辅助电极400位于像素电极200和第一辅助电极300之间，且第二辅助电极400分别与像素电极200以及第一辅助电极300绝缘。
请参考图4，图4是图3示出的电子纸中的阵列基板的俯视图。其中，第二辅助电极400在衬底100上的正投影，与像素电极200在衬底100上的正投影存在交叠区域B，且与第一辅助电极300在衬底100上的正投影存在交叠区域C。
由于第一辅助电极300与像素电极200电连接，因此，在该阵列基板所在的电子纸进行显示时，第一辅助电极300上加载的电压，与像素电极200上加载的电压相同，均为像素电压，也即是，第一辅助电极300也相当于像素电极。如此，在该电子纸进行显示时，第一辅助电极300与第二辅助电极400可以形成第一存储电容Cst1，像素电极200与第二辅助电极400可以形成第二存储电容Cst2。由于第二辅助电极400为像素电极200与第一辅助电极300之间，因此，通过第二辅助电极400与第一辅助电极300形成的第一存储电容Cst1，和通过第二辅助电极400与像素电极200形成的第二存储电容Cst2并联。该阵列基板000中的总存储电容的电容值为第一存储电容Cst1的电容值和第二存储电容Cst1的电容值之和，因此，该阵列基板000中的总存储电容的电容值较大。
在相关技术中，如图1和图2所示，假设第一辅助电极022在衬底01上的正投影，与第二辅助电极052在衬底01上的正投影之间的交叠区域A的面积为S。第一辅助电极022和第二辅助电极052之间的第一绝缘层03的厚度可以为4000埃，该第一绝缘层03的材料可以包括：氮化硅，其相对介电常数为6.5。
则，可以计算得到存储电容Cst’的电容值Ci’为：
Figure PCTCN2021129584-appb-000001
而在本申请中，如图3和图4所示，假设第二辅助电极400在衬底100上的正投影，与像素电极200在衬底100上的正投影之间的交叠区域B的面积也为S，第二辅助电极400在衬底100上的正投影，与第一辅助电极300在衬底100上的正投影之间的交叠区域C的面积也为S。且由于第一辅助电极300与第 二辅助电极400之间的绝缘层，与相关技术中的第一绝缘层03的厚度和材料均相同，因此，第一存储电容Cst1的电容值Ci 1与相关技术中的存储电容Cst’的电容值Ci’的大小相等。第二辅助电极400与像素电极200之间的绝缘层的厚度范围可以为：2000至6000埃，该绝缘层的材料与第一绝缘层03相同，其相对介电常数也为6.5。
则，可以计算得到第二存储电容Cst2的电容值的最小值Ci 2，min为：
Figure PCTCN2021129584-appb-000002
第二存储电容Cst2的电容值的最大值Ci 2，max为：
Figure PCTCN2021129584-appb-000003
因此，在本申请中，阵列基板000中的总存储电容的电容值Ci的范围为：
Ci＝Ci 1+Ci 2＝2.399×10 -16×S～4.21×10 -16×S       (4)
由上可知，相比于相关技术中的阵列基板00中的存储电容的电容值Ci’，本申请实施例提供的阵列基板000中的总存储电容的电容值Ci可以提高67％至192％。
综上所述，本申请实施例提供的电子纸，包括：阵列基板、盖板和电泳层。由于阵列基板中的第一辅助电极与像素电极电连接，因此，在该电子纸进行显示时，第一辅助电极上加载的电压，与像素电极上加载的电压相同，均为像素电压，也即是，第一辅助电极也相当于像素电极。如此，在该电子纸进行显示时，第一辅助电极与第二辅助电极可以形成第一存储电容，像素电极与第二辅助电极可以形成第二存储电容。该第一存储电容和第二存储电容并联，该阵列基板中的总存储电容值为第一存储电容的电容值与第二存储电容的电容值之和。与相关技术相比，本申请实施例提供的电子纸，在不改变电子纸的PPI的情况下，增大了存储电容的电容值，提高了像素电极上加载的电压的稳定性，进而提高了采用该电子纸的显示效果。
在本申请实施例中，请参考图5和图6，图5是本申请实施例提供的另一种电子纸中的阵列基板的俯视图，图6是图5示出的阵列基板在D-D’处的截面图。该阵列基板000还可以包括：薄膜晶体管500(英文：Thin-film transistor；简称：TFT)，该薄膜晶体管500可以包括：与像素电极200电连接的源漏极501。
在一种可能的实现方式中，该源漏极501可以与第一辅助电极300同层设 置，且材料相同，也即是，该源漏极501可以与第一辅助电极300通过一次构图工艺形成。
在另一种可能的实现方式中，该源漏极501还可以与第二辅助电极400同层设置，且材料相同。也即是，该源漏极501可以与第二辅助电极400通过一次构图工艺形成。
如此，可以简化该阵列基板000的制造工艺，降低该阵列基板000的制造难度和制造成本。需要说明的是，图5是以源漏极501与第二辅助电极400同层设置，且材料相同为例进行示意性说明的。
在本申请中，如图6所示，该薄膜晶体管500还可以包括：栅极502。
其中，该薄膜晶体管500中的栅极502可以与第一辅助电极300同层设置，且材料相同；该薄膜晶体管500中的源漏极501可以与第二辅助电极400同层设置，且材料相同。也即是，该栅极502可以与第一辅助电极300通过一次构图工艺形成，该源漏极501可以与第二辅助电极400通过一次构图工艺形成。如此，可以进一步简化该阵列基板000的制造工艺，进一步降低该阵列基板000的制造难度和制造成本。
在本申请实施例中，如图6所示，该薄膜晶体管500还可以包括：与栅极502绝缘设置的有源层503。
其中，该有源层503与源漏极501搭接，且源漏极501位于有源层503远离衬底100的一侧，栅极502位于有源层503靠近衬底100的一侧。也即是，该薄膜晶体管500为底栅型薄膜晶体管。在其他可能的实现方式中，该薄膜晶体管500还可以为顶栅型薄膜晶体管，本申请实施例对此不做限定。
在本申请中，请参考图5和图6。该阵列基板具有阵列排布的多个像素区域000a，每个像素区域000a设置有串联的两个薄膜晶体管500。
该两个薄膜晶体管500中的每一个薄膜晶体管500均可以包括：源漏极501。每个源漏极501均包括：第一极501a和第二极501b。其中，该第一极501a可以为源极和漏极中的一个，该第二极501b可以为源极和漏极中的另一个。一个薄膜晶体管500中的第一极501a，与另一个薄膜晶体管500中的第二极501b电连接，以使两个薄膜晶体管500串联。如此，可以降低薄膜晶体管500中的漏电流，对像素电极200上加载的像素电压的影响。
示例的，如图5所示，该每个薄膜晶体管500中的有源层503的沟道区E为长条形沟道区。需要说明的是，有源层图案503的沟道区E是指：有源层503 中位于有源层503与第一极501a接触的区域，和有源层503与第二极501b接触的区域之间的区域。该沟道区E的宽度的范围可以为：20至40微米。如此，可以满足阵列基板000的充电率需要。
在本申请实施例中，如图5所示，该阵列基板还可包括：与栅极502电连接的栅线600，与源漏极501电连接的数据线700，以及与第二辅助电极400电连接的辅助电极线800。示例的，该栅线600、栅极502和第一辅助电极300同层设置，且材料相同，也即是，该栅线600、栅极502和第一辅助电极300是通过一次构图工艺形成的。该数据线700、辅助电极线800、源漏极501和第二辅助电极400同层设置，且材料相同，也即是，该数据线700、辅助电极线800、源漏极501和第二辅助电极400是通过一次构图工艺形成的。
其中，栅线600的延伸方向与数据线700的延伸方向相交，且该栅线600的延伸方向与辅助电极线800的延伸方向相交。该延伸方向相交的栅线600和数据线700可以在阵列基板000中限定出多个像素区域000a。示例的，任意两条相邻的栅线600与任意两条相邻的数据线700能够围成一个像素区域000a。
可选的，数据线700的延伸方向与栅线600的延伸方向可以垂直，该数据线700的延伸方向可以与辅助电极线800平行。该延伸方向垂直的栅线600和数据线700在阵列基板000中限定出多个像素区域000a为矩形。
进一步的，数据线700的宽度小于辅助电极线800的宽度。如此，该数据线700的宽度较小，可以降低数据线700与栅线600交叠的面积，从而降低了该数据线700与栅线600之间产生的寄生电容的电容值，进而降低了该寄生电容对阵列基板000所在的电子纸的显示效果的影响。而由于在该阵列基板000所在的电子纸进行显示时，辅助电极线800上加载的电压恒定不变，因此，该辅助电极线800与栅线600之间产生的寄生电容，不会影响该电子纸的显示效果，该辅助电极线800的宽度可以较大，以增加该电子纸的强度，降低该电子纸在使用过程中损坏的概率。
在本申请实施例中，请参考图6，该阵列基板000还可以包括：位于第二辅助电极400与第一辅助电极300之间的第一绝缘层900，以及位于第二辅助电极400与像素电极200之间的第二绝缘层1000。
其中，该第一绝缘层900具有第一过孔a，第二绝缘层1000具有与第一过孔a连通的第二过孔b，像素电极200通过该第一过孔a和第二过孔b与第一辅助电极300电连接。
在本申请中，该第一过孔a在衬底100上的正投影，位于该第二过孔b在衬底100上的正投影内。
可选的，该第二绝缘层1000还具有第三过孔c，像素电极200通过该第三过孔c与源漏极501中的第一极501a和第二极501b中的一个电连接。
需要说明的是，该第一绝缘层900还可以作为栅极绝缘层，以实现薄膜晶体管500中的，有源层503与栅极502的绝缘设置。
在本申请实施例中，如图5所示，第二辅助电极400在衬底100上的正投影，位于第一辅助电极300在衬底100上的正投影内，且第一辅助电极300在衬底100上的正投影，位于像素电极200在衬底100上的正投影内。如此，第二辅助电极400在衬底100上的正投影，与像素电极200在衬底100上的正投影之间的交叠区域B，和第二辅助电极400与第一辅助电极300在衬底100上的正投影之间的交叠区域C的面积，均为第二辅助电极400的面积。也即是，第二辅助电极400在衬底100上的正投影，与像素电极200在衬底100上的正投影之间的交叠区域B，和第二辅助电极400与第一辅助电极300在衬底100上的正投影之间的交叠区域C重合。如此，可以通过改变第二辅助电极400的面积，改变阵列基板000中的总存储电容的电容值Ci。示例的，该第二辅助电极400的面积越大，阵列基板000中的总存储电容的电容值Ci越大；反之，该第二辅助电极400的面积越小，阵列基板000中的总存储电容的电容值Ci越小。
需要说明的是，还可以通过改变第二绝缘层1000的厚度，改变阵列基板000中的总存储电容的电容值Ci。示例的，第二绝缘层1000的厚度越大，阵列基板000中的总存储电容的电容值Ci越小；反之，第二绝缘层1000的厚度越小，阵列基板000中的总存储电容的电容值Ci越大。
还需要说明的是，第一辅助电极300在衬底100上的正投影，与源漏极501在衬底100上的正投影不存在交叠区域，如此，可以避免该第一辅助电极300与源漏极501之间产生电场干扰。
在本申请实施例中，请参考图7，图7是本申请实施例提供的另一种电子纸的膜层结构示意图。
该电子纸中的盖板001可以包括：第二衬底0011，以及位于第二衬底0011上的公共电极0012，其中，公共电极0012朝向阵列基板000中的像素电极200。
该电子纸中的电泳层002可以包括：多个电泳胶囊0021，每个电泳胶囊0021可以包括：胶囊本体，以及位于该胶囊本体内的电泳液和带电粒子，该带电粒 子可以包括：黑粒子、白粒子和彩色粒子等。
在本申请中，当向阵列基板000中的像素电极400施加电压时，像素电极400会与公共电极0012形成电压差，在该电压差的作用下，每个电泳胶囊0021中的带电粒子会在电泳液中进行运动，以实现该电子纸的显示。
可选的，阵列基板000中的第一辅助电极300在衬底100上的正投影的面积，小于像素电极200在衬底100上的正投影的面积。如此，在该电子纸进行显示时，该像素电极200可以对第一辅助电极300起到电场屏蔽的作用，避免第一辅助电极300与盖板001中的公共电极0012之间产生电场，对该电子纸的显示效果造成影响。
综上所述，本申请实施例提供的电子纸，包括：阵列基板、盖板和电泳层。由于阵列基板中的第一辅助电极与像素电极电连接，因此，在该电子纸进行显示时，第一辅助电极上加载的电压，与像素电极上加载的电压相同，均为像素电压，也即是，第一辅助电极也相当于像素电极。如此，在该电子纸进行显示时，第一辅助电极与第二辅助电极可以形成第一存储电容，像素电极与第二辅助电极可以形成第二存储电容。该第一存储电容和第二存储电容并联，该阵列基板中的总存储电容值为第一存储电容的电容值与第二存储电容的电容值之和。与相关技术相比，本申请实施例提供的电子纸，在不改变电子纸的PPI的情况下，增大了存储电容的电容值，提高了像素电极上加载的电压的稳定性，进而提高了采用该电子纸的显示效果。
本申请实施例提供的一种阵列基板的制造方法。该阵列基板的制造方法用于制造上述图5示出的阵列基板。该阵列基板的制造方法可以包括：
步骤A、在衬底上形成第一导电图案。
可选的，该第一导电图案的材料可以包括：金属钼(简称：Mo)、金属钛(简称：Ti)、金属铜(简称：Cu)、金属铝(简称：Al)或合金材料制造而成。该第一导电图案可以包括：栅极、栅线和第一辅助电极。
示例的，可以在衬底上通过沉积、涂敷、溅射等多种方式中的任一种形成第一导电薄膜，然后对该第一导电薄膜执行一次构图工艺以形成第一导电图案，该一次构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
步骤B、在第一导电图案上形成第一绝缘层。
可选的，该栅极绝缘层的材料可以为二氧化硅、氮化硅或者高介电常数材 料等。
示例的，可以在形成有第一导电图案的衬底上通过沉积、涂敷、溅射等多种方式中的任一种形成第一绝缘薄膜，然后对该第一绝缘薄膜执行一次构图工艺以形成栅极绝缘层，该一次构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
步骤C、在第一绝缘层上形成有源层。
可选的，该有源层材料可以包括：多晶硅、非晶硅或氧化物半导体等半导体材料。
示例的，可以在形成有第一绝缘层的衬底上通过沉积、涂敷、溅射等多种方式中的任一种形成有源层薄膜，然后对该有源层薄膜执行一次构图工艺以形成有源层。该一次构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
步骤D、在有源层上形成第二导电图案。
可选的，该第二导电图案的材料可以包括：金属Mo、金属Ti、金属Cu、金属铝Al或合金材料制造而成。该第二导电图案可以包括：源漏极、第二辅助电极、数据线和辅助电极线。
示例的，可以在形成有有源层图案的衬底上通过沉积、涂敷、溅射等多种方式中的任一种形成第二导电薄膜，然后对该第二导电薄膜执行一次构图工艺以形成第二导电图案，该一次构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
步骤E、在第二导电图案上形成第二绝缘层。
可选的，该第二绝缘层的材料可以为二氧化硅、氮化硅或者高介电常数材料等。
示例的，可以在形成有第二导电图案的衬底上通过沉积、涂敷、溅射等多种方式中的任一种形成第二绝缘薄膜，然后对该第二绝缘薄膜执行一次构图工艺以形成第二绝缘层，该一次构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
步骤F、在第二绝缘层上形成像素电极。
可选的，该像素电极的材料可以包括：氧化铟锡(英文：Indium tin oxide；简称：ITO)或氧化铟锌(英文：Indium Zinc Oxide；简称：IZO)等透明导电材料。
示例的，可以在形成有第二绝缘层的衬底上通过沉积、涂敷、溅射等多种方式中的任一种形成像素电极薄膜，然后对该像素电极薄膜执行一次构图工艺以形成像素电极，该一次构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的阵列基板中各个结构的工作原理以及连接关系，可以参考前述阵列基板的结构的实施例中的对应内容，在此不再赘述。
本申请实施例还提供了一种显示设备，该显示设备可以包括：上述实施例中的电子纸，该显示设备可以为电子标签、广告牌和电子阅读器等。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
如本文所述，术语“同层”是指在同一步骤中同时形成的层之间的关系，例如：当源漏极和第一辅助电极为在同一层材料中执行相同图案处理的一个或多个步骤而形成时，它们处于同层中。在另一个示例中，通过同时执行形成源漏极的步骤和形成第一辅助电极步骤，可以在同一层中形成源漏极和第一辅助电极。术语“同层”并不总是意味着该层的厚度或横截面视图中的图层是相同的。
在本申请中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本申请的可选的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (12)

  1. 一种电子纸，其特征在于，包括：
    相对设置的阵列基板和盖板，以及位于所述阵列基板和所述盖板之间的电泳层；
    所述阵列基板包括：衬底，位于所述衬底上的像素电极，位于所述衬底上且与所述像素电连接的第一辅助电极，以及位于所述像素电极和所述第一辅助电极之间的第二辅助电极，所述第二辅助电极分别与所述像素电极以及所述第一辅助电极绝缘；
    其中，所述第二辅助电极在所述衬底上的正投影，与所述像素电极在所述衬底上的正投影存在交叠区域，且与所述第一辅助电极在所述衬底上的正投影存在交叠区域。
  2. 根据权利要求1所述的电子纸，其特征在于，
    所述阵列基板还包括：薄膜晶体管，所述薄膜晶体管包括：与所述像素电极电连接的源漏极；
    其中，所述源漏极与所述第一辅助电极同层设置，且材料相同；或者，所述源漏极与所述第二辅助电极同层设置，且材料相同。
  3. 根据权利要求2所述的电子纸，其特征在于，
    所述薄膜晶体管还包括：栅极；
    其中，所述栅极与所述第一辅助电极同层设置，且材料相同；所述源漏极与所述第二辅助电极同层设置，且材料相同。
  4. 根据权利要求3所述的电子纸，其特征在于，
    所述薄膜晶体管还包括：与所述栅极绝缘设置的有源层；
    其中，所述有源层与所述源漏极搭接，且所述源漏极位于所述有源层远离所述衬底的一侧，所述栅极位于所述有源层靠近所述衬底的一侧。
  5. 根据权利要求2所述的电子纸，其特征在于，
    所述阵列基板具有阵列排布的多个像素区域，每个所述像素区域设置有串 联的两个所述薄膜晶体管。
  6. 根据权利要求3所述的电子纸，其特征在于，
    所述阵列基板还包括：与所述栅极电连接的栅线，与所述源漏极电连接的数据线，以及与所述第二辅助电极电连接的辅助电极线；
    其中，所述栅线的延伸方向与所述数据线的延伸方向相交，且与所述辅助电极线的延伸方向相交。
  7. 根据权利要求6所述的电子纸，其特征在于，
    所述数据线的延伸方向与所述栅线的延伸方向垂直，且与所述辅助电极线的延伸方向平行。
  8. 根据权利要求7所述的电子纸，其特征在于，
    所述数据线的宽度小于所述辅助电极线的宽度。
  9. 根据权利要求1至8任一所述的阵列基板，其特征在于，
    所述阵列基板还包括：位于所述第二辅助电极与所述第一辅助电极之间的第一绝缘层，以及位于所述第二辅助电极与所述像素电极之间的第二绝缘层；
    其中，所述第一绝缘层具有第一过孔，所述第二绝缘层具有与所述第一过孔连通的第二过孔，所述像素电极通过所述第一过孔和所述第二过孔与所述第一辅助电极电连接。
  10. 根据权利要求9所述的电子纸，其特征在于，
    所述第一过孔在所述衬底上的正投影，位于所述第二过孔在所述衬底上的正投影内。
  11. 根据权利要求1至8任一所述的电子纸，其特征在于，
    所述第二辅助电极在所述衬底上的正投影，位于所述第一辅助电极在所述衬底上的正投影内，且所述第一辅助电极在所述衬底上的正投影，位于所述像素电极在所述衬底上的正投影内。
  12. 根据权利要求11所述的电子纸，其特征在于，
    所述第一辅助电极在所述衬底上的正投影的面积，小于所述像素电极在所述衬底上的正投影的面积。
PCT/CN2021/129584 2020-12-18 2021-11-09 电子纸 WO2022127445A1 (zh)

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US20050190312A1 (en) * 2004-02-27 2005-09-01 Chien-Sheng Yang [pixel structure and manufacturing method thereof]
CN107340665A (zh) * 2017-08-31 2017-11-10 上海天马微电子有限公司 电泳显示面板和制造方法
CN107402487A (zh) * 2017-08-31 2017-11-28 武汉天马微电子有限公司 阵列基板及其制造方法、显示面板
CN108873552A (zh) * 2018-06-29 2018-11-23 上海天马微电子有限公司 一种电子纸显示基板、显示面板及显示装置
CN111739896A (zh) * 2020-07-01 2020-10-02 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板
CN215006189U (zh) * 2020-12-18 2021-12-03 京东方科技集团股份有限公司 电子纸

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US20050190312A1 (en) * 2004-02-27 2005-09-01 Chien-Sheng Yang [pixel structure and manufacturing method thereof]
CN107340665A (zh) * 2017-08-31 2017-11-10 上海天马微电子有限公司 电泳显示面板和制造方法
CN107402487A (zh) * 2017-08-31 2017-11-28 武汉天马微电子有限公司 阵列基板及其制造方法、显示面板
CN108873552A (zh) * 2018-06-29 2018-11-23 上海天马微电子有限公司 一种电子纸显示基板、显示面板及显示装置
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CN215006189U (zh) * 2020-12-18 2021-12-03 京东方科技集团股份有限公司 电子纸

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