WO2022001460A1 - 显示基板、显示面板和显示装置 - Google Patents

显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2022001460A1
WO2022001460A1 PCT/CN2021/094846 CN2021094846W WO2022001460A1 WO 2022001460 A1 WO2022001460 A1 WO 2022001460A1 CN 2021094846 W CN2021094846 W CN 2021094846W WO 2022001460 A1 WO2022001460 A1 WO 2022001460A1
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Prior art keywords
pixel
pixel unit
substrate
electrode
line
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PCT/CN2021/094846
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English (en)
French (fr)
Inventor
苏秋杰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US17/773,531 priority Critical patent/US12014696B2/en
Publication of WO2022001460A1 publication Critical patent/WO2022001460A1/zh

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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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Definitions

  • the present disclosure relates to the field of display, and in particular, to a display substrate, a display panel and a display device.
  • Advanced super-dimensional switch display mode has the advantages of wide viewing angle, fast response speed, high contrast ratio and high transmittance. It has become a popular display mode and is used by many panel manufacturers for product design. middle. However, in practical applications, it is found that the pictures displayed by the existing ADS type display device have obvious mura.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate, a display panel and a display device.
  • an embodiment of the present disclosure provides a display substrate, comprising: a first base substrate, a plurality of gate lines and a plurality of data lines located on the first base substrate, the gate lines extending along the first extending in a direction, the data lines extend along a second direction, the first direction and the second direction intersect and both are parallel to the plane where the first base substrate is located;
  • a plurality of the gate lines and a plurality of the data lines define a plurality of pixel units
  • the pixel units include: a thin film transistor, a pixel electrode and a common electrode, the pixel electrode is located on the common electrode away from the first substrate On one side of the base substrate, the area where the pixel electrode is located and the area where the thin film transistor is located in the same pixel unit are arranged along the second direction, and the end of the pixel electrode close to the thin film transistor is the first an end, the end of the pixel electrode away from the thin film transistor is a second end, and at least part of the pixel unit is configured with a conductive bridge line, and the conductive bridge line is arranged in the same layer as the pixel electrode;
  • a first hollow structure is provided on the first end portion or the first side of the second end portion of the pixel electrode, and the conductive bridge line is provided with a first hollow structure.
  • the end portion is located in the first hollow structure and is connected to the common electrode via hole, and the second side of the second end portion of the pixel electrode is provided with a second hollow structure, so that the pixel electrode is connected to the
  • the absolute value of the difference between the parasitic capacitances formed by the nearest data lines on both sides is less than or equal to the preset capacitance difference;
  • the first side and the second side are opposite sides of the pixel electrode in the first direction.
  • the length of the second hollow structure and the first hollow structure in the second direction are equal.
  • the length of the second hollow structure in the first direction is less than or equal to the length of the first hollow structure in the first direction.
  • the parasitic capacitances formed by the pixel electrodes and the nearest data lines on both sides are equal to each other.
  • the plurality of pixel units arranged along the first direction correspond to the same strip-shaped common electrode, and the strip-shaped common electrode extends along the first direction;
  • the common electrodes included in each of the plurality of pixel units corresponding to the same strip-shaped common electrode are parts of different positions on the strip-shaped common electrode.
  • it further includes: a common electrode line, the common electrode line and the gate line are provided in the same layer;
  • a plurality of pixel units arranged along the first direction correspond to the same common electrode line, the common electrodes in the pixel units are electrically connected to the corresponding common electrode lines, and the second
  • the orthographic projection of the end portion on the first base substrate overlaps with the orthographic projection of the corresponding common electrode line on the first base substrate.
  • the gate lines include: first conductive patterns and second conductive patterns are alternately arranged along a first direction, and the length of the first conductive patterns in the second direction is greater than that of the second conductive patterns a length in said second direction;
  • the orthographic projection of the first conductive pattern on the first base substrate does not overlap with the orthographic projection of the data line on the first base substrate, and a portion of the first conductive pattern is used for a gate in the thin film transistor;
  • the orthographic projection of the conductive bridge line on the first base substrate does not overlap with the orthographic projection of the first conductive pattern on the first base substrate.
  • all the pixel units in the display substrate include: red pixel units, green pixel units and blue pixel units;
  • the blue pixel unit is configured with the conductive bridge line.
  • a first limiting column and a second limiting column are provided in some of the pixel units, the pixel unit has a preset light emitting area, the first limiting column and the second limiting column The bit columns are respectively located on opposite sides of the preset light-emitting area in the second direction;
  • Both the first limit post and the second limit post include: a stacked first limit pattern and a second limit pattern, the first limit pattern and the grid line are arranged in the same layer, and the second limit pattern The limit graphics are arranged on the same layer as the data lines.
  • all the pixel units in the display substrate include: red pixel units, green pixel units and blue pixel units;
  • the red pixel unit is provided with the first limiting column and the second limiting column.
  • an embodiment of the present disclosure further provides a display panel, which includes: a display substrate and a cell assembling substrate that are arranged opposite to each other, a liquid crystal layer is filled between the display substrate and the cell assembling substrate, and the display The substrate adopts the display substrate provided in the first aspect.
  • the voltage loaded on the pixel electrode in the pixel unit is affected by The amount of change produced by the effect of the polarity reversal is ⁇ Vp:
  • Cpd1 represents the parasitic capacitance formed between the pixel electrode in the pixel unit and the data line with polarity reversal
  • ⁇ Vd represents the data voltage loaded after the polarity reversal in the data line with polarity reversal
  • the polarity reversal represents the sum of the parasitic capacitances formed by the pixel electrode in the pixel unit and the data lines located on both sides and the nearest data line respectively
  • Cst represents the pixel electrode in the pixel unit and the common Storage capacitance between electrodes
  • Clc represents the liquid crystal capacitance at the pixel unit
  • Cst represents the parasitic capacitance between the pixel electrode and the gate line in the pixel unit.
  • the cell alignment substrate is a color filter substrate
  • the color filter substrate includes: a second base substrate, a black matrix and a color filter pattern on the second base substrate;
  • the black matrix defines a plurality of pixel light exits, the pixel light exits are in one-to-one correspondence with the pixel units, and the color filter pattern is located in the pixel light exits;
  • the orthographic projection of the black matrix on the first base substrate completely covers the gate line, the data line, the thin film transistor, the first hollow structure and the second hollow structure.
  • the thin film transistor in the pixel unit is electrically connected to the data line on the second side of the pixel unit;
  • the pixel unit includes: a red pixel unit, a green pixel unit and a blue pixel unit;
  • the shape of the pixel opening corresponding to the red pixel unit includes: a first rectangular portion and a first rectangular portion formed by extending outward along the second direction and two corner regions on the second side of the first rectangular portion. a protruding part and a second protruding part;
  • the shape of the pixel opening corresponding to the green pixel unit includes: a second rectangular portion and a third rectangular portion formed by extending outward along the second direction and two corner regions on the second rectangular portion located on the first side. a protrusion and a fourth protrusion;
  • the shape of the pixel opening corresponding to the blue pixel unit includes: a third rectangular portion
  • the shape of the pixel opening corresponding to the blue pixel unit includes: a third rectangular portion, a corner region on the third rectangular portion on the first side and on the third side at the same time along the second
  • the third side and the fourth side are opposite sides of the third rectangle in the second direction.
  • the display substrate is provided with a first limiting column and a second limiting column
  • the color filter substrate further includes: a spacer, the spacer is located on the black matrix away from the On one side of the second base substrate, the projection of the spacer on the display substrate is located between the adjacent first limiting posts and the second limiting posts in the second direction, and the adjacent The first limiting column and the second limiting column are respectively located in two adjacent pixel units in the second direction.
  • an embodiment of the present disclosure further provides a display device, which includes: the display panel provided in the second aspect above.
  • FIG. 1 is a top view of a pixel unit configured to accommodate conductive bridge lines in the related art
  • FIG. 2 is another top view of a pixel unit configured to accommodate conductive bridge lines in the related art
  • FIG. 3 is a schematic diagram of the circuit structure of the pixel unit in the present disclosure when the Z inversion arrangement is adopted;
  • FIG. 4 is a schematic diagram of the circuit structure of two pixel units located in the same column and adjacent rows in FIG. 3;
  • FIG. 5 is a schematic top view of a display substrate according to an embodiment of the present disclosure.
  • Fig. 6 is the cross-sectional schematic diagram of A-A' in Fig. 5;
  • FIG. 7a is a top view of a pixel unit configured with a conductive bridge line according to an embodiment of the disclosure
  • 7b is another top view of a pixel unit configured with a conductive bridge line according to an embodiment of the disclosure.
  • FIG. 8 is a top view of a display panel according to an embodiment of the present disclosure.
  • Fig. 9 is the cross-sectional schematic diagram of C-C' in Fig. 8;
  • FIG. 10 is a schematic diagram of the shape of a pixel opening corresponding to a red pixel unit in an embodiment of the disclosure
  • FIG. 11 is a schematic diagram of a shape of a pixel opening corresponding to a green pixel unit in an embodiment of the disclosure
  • 12a is a schematic diagram of a shape of a pixel opening corresponding to a blue pixel unit in an embodiment of the disclosure
  • FIG. 12b is another schematic diagram of the shape of the pixel opening corresponding to the blue pixel unit in the embodiment of the disclosure.
  • the present disclosure analyzes the reasons for the moire in the related art, and provides a corresponding solution.
  • the polarity inversion method is used for driving in the display driving process.
  • the common polarity inversion methods include: horizontal inversion Rotation, Column Inversion and Point Inversion.
  • parasitic capacitance is formed between the pixel electrode and the nearest data lines on both sides of the pixel electrode.
  • the polarity of the data voltage loaded in the data line is reversed, the data voltage in the data line undergoes a large jump, and the parasitic capacitance coupling between the data line and the pixel electrode will cause the voltage loaded on the pixel electrode to change.
  • the polarity of the data voltages in two adjacent data lines on the display panel is often set to be opposite.
  • FIG. 1 is a top view of a pixel unit configured to accommodate conductive bridge lines in the related art
  • FIG. 2 is another top view of a pixel unit configured to accommodate conductive bridge lines 3 in the related art, as shown in FIGS. 1 and 2
  • the pixel electrode 1 in the pixel unit is in the shape of a parallelogram (for example, a rectangle) as a whole; however, in the ADS row display panel, some pixel units need to be equipped with conductive bridge lines 3 (electrically connected to the common electrode through vias),
  • the conductive bridge lines 3 are arranged on the same layer as the pixel electrodes 1 ; since the conductive bridge lines 3 occupy part of the pixel electrode 1 , the pixel electrode 1 needs to be provided with a hollow structure 2 to accommodate the ends of the conductive bridge lines 3 .
  • FIG. 1 exemplarily depicts the case where the hollow structure 2 for accommodating the ends of the conductive bridge lines 3 is located at the lower left corner of the pixel electrode 1
  • FIG. 2 exemplarily depicts the case where the ends of the conductive bridge lines 3 are accommodated
  • the hollow structure 2 is located in the upper left corner of the pixel electrode 1.
  • the length of the first part of the pixel electrode 1 that can generate parasitic capacitance with the left data line D_L is L1
  • the second part of the pixel electrode 1 that can generate parasitic capacitance with the right data line D_R The length of L2 is L2.
  • the parasitic capacitance between the first part and the left data line D_L is Cpd_L
  • the parasitic capacitance between the second part and the left data line D_L is Cpd_R.
  • FIG. 3 is a schematic diagram of the circuit structure of the pixel units in the disclosure when the Z-inversion arrangement is adopted.
  • the pixel units in the display substrate are arranged in the Z-inversion arrangement as an example; Specifically, the pixel units located in the i-th row are connected to the i-th gate line G1/G2/G3/G4, and the pixel units located in the odd-numbered rows are respectively connected to the first side (the left side of the pixel unit in the drawing) and The nearest data line is connected, and each pixel unit in the even-numbered row is respectively connected with the nearest data line on the second side thereof (the right side of the pixel unit in the drawing).
  • Fig. 3 exemplarily shows that the data voltages loaded in the odd-numbered column data lines D1, D3, D5, D7, D9 are positive (+), and the even-numbered column data lines D2, D4, D6, D8 are loaded with When the data voltage is positive (-).
  • FIG. 4 is a schematic diagram of the circuit structure of two pixel units located in the same column and adjacent rows in FIG. 3 .
  • the voltage applied to the pixel electrode 1 in the pixel unit located in the M row is positive
  • the voltage applied to the pixel electrode 1 in the M+ row is positive.
  • the voltage loaded on the pixel electrode 1 is negative
  • the data voltage loaded on the left data line D_L jumps from positive polarity to negative polarity
  • the data voltage loaded on the right data line D_R jumps from negative polarity to positive polarity.
  • ⁇ Vp_L Cpd_L* ⁇ Vd_L/(Cpd_L+Cpd_R+Cst+Clc+Cgp);
  • Cpd_L indicates the parasitic capacitance formed between the pixel electrode 1 and the left data line D_L
  • Cpd_R indicates the parasitic capacitance formed between the pixel electrode 1 and the right data line D_R
  • ⁇ Vd_L indicates that the polarity of the data voltage in the left data line D_L is reversed
  • the amount of voltage change (the absolute value of the difference between the data voltage after the polarity inversion and the data voltage before the polarity inversion)
  • Cst represents the storage capacitance between the pixel electrode 1 and the common electrode
  • Clc represents the liquid crystal at the pixel unit.
  • Capacitance Cst represents the parasitic capacitance between the pixel electrode 1 and the gate line.
  • ⁇ Vp_R Cpd_R* ⁇ Vd_R/(Cpd_L+Cpd_R+Cst+Clc+Cgp)
  • ⁇ Vd_R represents the voltage change amount (the absolute value of the difference between the data voltage after the polarity inversion and the data voltage before the polarity inversion) of the data voltage in the right data line D_R with polarity inversion.
  • the hollow structure 2 for accommodating the conductive bridge lines 3 is formed on the pixel electrode 1, resulting in a large difference in the parasitic capacitances formed by the pixel electrode 1 and the left and right data lines respectively, thereby causing the pixel electrode 1 to have a large difference.
  • the embodiments of the present disclosure provide corresponding solutions.
  • FIG. 5 is a schematic top view of a display substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional view taken along the AA' direction in FIG. 5
  • the display substrate is an ADS type display substrate
  • the display substrate includes: a first base substrate 20, a plurality of gate lines 4 and a plurality of data lines 5 located on the first base substrate 20, the gate lines 4 extend along a first direction X, and the data lines 5 extend along a second direction Y extends, and the first direction X and the second direction Y intersect and are both parallel to the plane where the first base substrate 20 is located.
  • the first direction X is the row direction and the second direction Y is the column direction as an example, for exemplary description.
  • a plurality of gate lines 4 and a plurality of data lines 5 define a plurality of pixel units.
  • the pixel units include: thin film transistors 7, pixel electrodes 8 and common electrodes 9.
  • the pixel electrodes 8 are slit electrodes and are located in the common electrode 9 away from the first substrate.
  • the area where the pixel electrode 8 is located and the area where the thin film transistor 7 is located in the same pixel unit are arranged along the second direction Y, the end of the pixel electrode 8 close to the thin film transistor 7 is the first end, and the pixel One end of the electrode 8 away from the thin film transistor 7 is the second end.
  • At least part of the pixel units are provided with conductive bridge lines 10 , and the conductive bridge lines 10 and the pixel electrodes 8 are disposed in the same layer.
  • the thin film transistor 7 includes a gate electrode, a source electrode 15 , a drain electrode 16 and an active layer 17 .
  • FIG. 5 only exemplarily shows that the gate electrode of the thin film transistor 7 in each pixel unit is connected to the corresponding row gate line 4, and the source electrode 15 of the thin film transistor 7 in each pixel unit is connected to the one to the right and closest to itself.
  • the case where the data line 5 is connected this case only serves as an example, which will not limit the technical solution of the present disclosure.
  • the arrangement of the pixel units in the present disclosure may also be arranged in other manners, for example, in a Z-inversion arrangement.
  • FIG. 5 only exemplarily shows that there is one pixel unit configured with the conductive bridge line 10 in every three pixel units, which is only for an exemplary role and does not limit the technical solution of the present disclosure.
  • conductive bridge lines 10 may be configured in each pixel unit, or conductive bridge lines 10 may be configured in some pixel units.
  • FIG. 7a is a top view of a pixel unit configured with a conductive bridge line 10 according to an embodiment of the present disclosure
  • FIG. 7b is another top view of a pixel unit configured with a conductive bridge line 10 according to an embodiment of the present disclosure, as shown in FIGS. 7a and 7b.
  • a first hollow structure 13 is provided on the first end of the pixel electrode 8 or on the first side of the second end, and the end of the conductive bridge line 10 is located in the first hollow structure 13.
  • a hollowed-out structure 13 is connected to the common electrode 9 via a via hole, and a second hollowed-out structure 14 is disposed on the second side of the second end of the pixel electrode 8, so that the pixel electrode 8 and the nearest data line 5 on both sides are respectively
  • the absolute value of the difference of the formed parasitic capacitance is less than or equal to the preset capacitance difference; the first side and the second side are opposite sides of the pixel electrode 8 in the first direction X. Taking the situation shown in FIG. 5 as an example, the first side specifically refers to the left side, and the second side specifically refers to the right side.
  • the first end portion and the second end portion of the pixel electrode 8 refer to the upper end portion and the lower end portion of the pixel electrode 8, respectively.
  • Fig. 7a exemplarily depicts the case where the first hollow structure 13 is located on the left side of the lower end (the first hollow structure 13 is located at the lower left corner of the pixel unit), and
  • Fig. 7b exemplarily depicts the first hollow structure 13 located at the upper end In the case of the left side of the upper end (the first hollow structure 13 is located at the upper left corner of the pixel unit), the second hollow structure 14 is correspondingly located on the right side of the upper end.
  • the technical solutions of the present disclosure will be limited.
  • the lengths of the second hollow structure 14 and the first hollow structure 13 in the second direction Y are equal, which is beneficial to realize the parasitic capacitance formed by the pixel electrode 8 and the data lines 5 located on both sides and closest to each other. equal or approximately equal.
  • the part of the pixel electrode 8 with the horizontal distance from the data line 5 less than 6 ⁇ m can form a parasitic capacitance with the data line 5 .
  • the part of the pixel electrode 8 that can form parasitic capacitance with the left data line 5 is called the first part
  • the part of the pixel electrode 8 that can form parasitic capacitance with the right data line 5 is called the second part.
  • the above-mentioned second hollow structure 14 is disposed on the pixel electrode 8 provided with the first hollow structure 13, and the second hollow structure 14 and the first hollow structure 13 are in the second direction Y second direction
  • the lengths on X are equal or similar so that the length L1 of the first part on the pixel electrode 8 in the second direction Y, the length L2 of the second part on the pixel electrode 8 in the second direction Y, both L1 and L2 equal or similar, so that the parasitic capacitance Cpd_L formed between the first part and the left data line 5 and the parasitic capacitance Cpd_2 formed between the second part and the right data line 5 satisfy
  • the difference in capacitance can effectively reduce or even eliminate the influence on the voltage loaded on the pixel electrode 8 when the data voltages in the data lines 5 on both sides of the pixel electrode 8 are simultaneously reversed in polarity, which is beneficial to weakening or even eliminating mura.
  • the length of the second hollow structure 14 in the second direction Y is not greater than the length of the first hollow structure in the Y direction.
  • the predetermined capacitance difference is less than or equal to 1.0 fF.
  • the part of the pixel electrode 8 with the distance from the data line 5 in the first direction X greater than 6um is relatively far away from the data line 5, so no obvious parasitic capacitance will be generated.
  • the length of the second hollow structure 14 in the first direction X should not be too large, because the longer the length of the second hollow structure 14 in the first direction X, the smaller the overall size of the pixel electrode 8, the pixel electrode 8 and the common electrode 9. The storage capacitance formed therebetween is reduced, and the ability of the pixel electrode 8 to maintain the gray-scale voltage is weakened. Based on the above factors, in the embodiment of the present disclosure, the length of the second hollow structure 14 in the first direction X is greater than or equal to 6 ⁇ m and less than or equal to the length of the first hollow structure 13 in the first direction X.
  • the plurality of pixel units arranged along the first direction X correspond to the same strip-shaped common electrode 9
  • the strip-shaped common electrode 9 extends along the first direction X
  • the plurality of pixel units corresponding to the same strip-shaped common electrode each The included common electrodes are parts of the strip-shaped common electrodes 9 at different positions. That is, the pixel units located in the same row correspond to the same strip-shaped common electrode 9 .
  • the display substrate further includes a common electrode line 6, the common electrode line 6 and the gate line 4 are disposed in the same layer, and the plurality of pixel units arranged along the first direction X correspond to the same common electrode line 6.
  • the common electrode 9 is electrically connected to the corresponding common electrode line 6, and the orthographic projection of the second end of the pixel electrode 8 on the first base substrate 20 is the same as the orthographic projection of the corresponding common electrode line 6 on the first base substrate 20. Projections overlap.
  • the two structures in the present disclosure are "disposed on the same layer" means that the two structures are obtained based on the patterning of the same material film, and the distances between the two structures and the base substrate may be equal or different. Wait.
  • the common electrode 9 is directly overlapped on the common electrode line 6 . Since the orthographic projection of the second end of the pixel electrode 8 on the first base substrate 20 overlaps with the orthographic projection of the common electrode line 6 on the first base substrate 20, the first The two hollow structures 14 overlap with the common electrode line 6 . Since the area where the common electrode line 6 is located will be covered by the black matrix, the setting of the second hollow structure 14 will not substantially affect the aperture ratio of the pixel unit.
  • the orthographic projection of the second hollow structure 14 on the first base substrate 20 is located in the area defined by the orthographic projection of the common electrode line 6 on the first base substrate 20 . At this time, the setting of the second hollow structure 14 It will not affect the aperture ratio of the pixel unit.
  • the gate line 4 includes alternately arranged first conductive patterns 4a and second conductive patterns 4b along the first direction X, and the length of the first conductive patterns 4a in the second direction Y is greater than that of the second conductive patterns 4b in the first direction Y.
  • the length of the first conductive pattern 4a in the second direction Y is relatively large, which can effectively reduce the overall resistance of the gate line 4 and facilitate the loading and transmission of signals.
  • the length of the second conductive pattern 4b in the second direction Y is relatively small, and the opposite panel between the second conductive pattern 4b and the data line 5 and the conductive bridge line 10 is relatively small, so the formed parasitic capacitance is relatively small. , the signal crosstalk between the gate line 4 , the data line 5 and the conductive bridge line 10 can be effectively reduced.
  • all pixel units in the display substrate include: red pixel units, green pixel units and blue pixel units; the blue pixel units are configured with conductive bridge lines 10 .
  • the light emitting area of the red pixel unit is smaller than the light emitting area of the blue pixel unit, and the light emitting area of the blue pixel unit is smaller than the light emitting area of the green pixel unit.
  • the aperture ratio is the same, the light transmittance of the green pixel is the highest, so the aperture ratio of the green pixel will not be sacrificed, so the conductive bridge line is selected to be arranged in the blue pixel unit.
  • a first limiting column 11 and a second limiting column 12 are provided in some pixel units, the pixel unit has a predetermined light-emitting area, and the first limiting column 11 and the second limiting column 12 are respectively located at The opposite sides of the preset light emitting area in the second direction Y; the first limiting column 11 and the second limiting column 12 both include: stacked first limiting patterns 11a, 12a and second limiting patterns 11b, 12b , the first limit patterns 11 a and 12 a are arranged on the same layer as the gate lines 4 , and the second limit patterns 11 b and 12 b are arranged on the same layer as the data lines 5 .
  • the first limiting column 11 and the second limiting column 12 are used to define the position of the spacer 18 after the display substrate and the cell assembling substrate are assembled, so as to prevent the spacer 18 from sliding.
  • the red pixel unit is provided with a first limiting column 11 and a second limiting column 12 .
  • the setting of the limit column will reduce the aperture ratio of the pixel unit where it is located, which will affect the light transmittance.
  • the human eye is most sensitive to green. Under the same aperture ratio, the green pixel unit has the highest light transmittance, so The aperture ratio of the green pixel unit will not be sacrificed.
  • the aperture ratio of the blue pixel unit has a greater influence on the color temperature. The larger the blue aperture ratio, the higher the color temperature. Therefore, the aperture ratio of the blue pixel unit is generally not sacrificed.
  • the limiting column is placed in the red pixel unit.
  • FIG. 8 is a top view of a display panel according to an embodiment of the present disclosure
  • FIG. 9 is a schematic cross-sectional view taken along the direction of CC' in FIG. 8
  • FIG. 9 is as shown in FIG. 8
  • the display panel includes: display substrates disposed oppositely
  • a liquid crystal layer 22 is filled between the display substrate and the cell matching substrate.
  • the display substrate adopts the display substrate provided in the above embodiment.
  • the description of the display substrate please refer to the content in the previous embodiment, which will not be repeated here.
  • any pixel unit when the polarity of the data voltage loaded on one side of the pixel unit and the nearest data line 5 is reversed, the voltage loaded on the pixel electrode 8 in the pixel unit is subjected to a polarity reversal.
  • the amount of change produced by the effect of sex reversal is ⁇ Vp:
  • Cpd1 represents the parasitic capacitance formed between the pixel electrode 8 in the pixel unit and the data line 5 where the polarity is reversed
  • ⁇ Vd represents the load on the data line 5 where the polarity is reversed after the polarity is reversed.
  • Cpd1+Cpd2 represents the sum of the parasitic capacitances formed by the pixel electrode 8 in the pixel unit and the nearest data line 5 on both sides
  • Cst represents the The storage capacitance between the pixel electrode 8 and the common electrode 9 in the pixel unit
  • Clc represents the liquid crystal capacitance at the pixel unit
  • Cst represents the parasitic capacitance between the pixel electrode 8 and the gate line 4 in the pixel unit.
  • the cell assembling substrate is a color filter substrate
  • the color filter substrate includes: a second base substrate 21, a black matrix 22 and a color filter pattern 19 on the second base substrate 21;
  • the black matrix 22 defines a plurality of Each pixel light outlet, the pixel light outlet corresponds to the pixel unit one-to-one to define the light output area of the pixel unit, the color filter pattern 19 is located in the pixel light outlet;
  • the orthographic projection of the black matrix 22 on the first substrate 20 completely covers the grid lines 4. Orthographic projections of the data line 5 , the thin film transistor 7 , the first hollow structure 13 and the second hollow structure 14 on the first base substrate 20 .
  • the thin film transistor in the pixel unit is electrically connected to the data line located on the second side of the pixel unit; the pixel unit includes: a red pixel unit R, a green pixel unit G and a blue pixel unit B.
  • FIG. 10 is a schematic diagram of the shape of the pixel opening corresponding to the red pixel unit in an embodiment of the disclosure.
  • the shape of the pixel opening corresponding to the red pixel unit R includes: first The rectangular portion r_1 and the first protruding portion r_2 and the second protruding portion r_3 formed by extending outward along the second direction Y at two corner regions of the first rectangular portion r_1 on the second side.
  • FIG. 11 is a schematic diagram of the shape of the pixel opening corresponding to the green pixel unit in an embodiment of the disclosure.
  • the shape of the pixel opening corresponding to the green pixel unit G includes: a second rectangle The third protruding portion g_2 and the fourth protruding portion g_3 formed by the portion g_1 and the two corner regions on the first side of the second rectangular portion g_1 extending outward along the second direction Y.
  • the shape of the pixel opening corresponding to the blue pixel unit B includes: Three rectangular parts b_1.
  • the shape of the pixel opening corresponding to the blue pixel unit B includes: a third rectangular part b_1, A fifth protruding portion b_2 formed by the third rectangular portion b_1 extending outward along the second direction Y with one corner region (corner region on the lower left side) on the first side and at the same time on the third side, the third rectangle
  • the sixth protruding portion b_3 formed by extending outward along the second direction Y from a corner region (the corner region on the upper right side) on the second side and the fourth side on the portion b_1; the third side and the fourth side are Opposite sides of the third rectangle in the second direction Y.
  • the third side specifically refers to the lower side
  • the fourth side specifically refers to the upper side.
  • FIG. 8 and FIGS. 10 to 12b are only exemplary and will not limit the technical solutions of the present disclosure. In practical applications, the pixel openings can be adjusted according to actual needs. Design and adjust.
  • all pixel units are exemplarily drawn, including: a red pixel unit R, a green pixel unit G, and a blue pixel unit B, and the green pixel unit G is configured with a conductive bridge line 10, and the red pixel unit R.
  • the first limiting column 11 and the second limiting column 12 are provided.
  • the display substrate is provided with a first limiting column 11 and a second limiting column 12, and the color filter substrate further includes: a spacer 18, and the spacer 18 is located in the black matrix 22 away from the second base substrate On one side of 21, the projection of the spacer 18 on the display substrate is located between the adjacent first limit posts 11 and the second limit posts 12 in the second direction Y, and the adjacent first limit posts 11 and the second limiting column 12 are located in two adjacent pixel units in the second direction Y respectively.
  • the position of the spacer 18 can be limited by the limiting column, so as to prevent the spacer 18 from sliding to the light emitting area of the pixel unit.
  • An embodiment of the present disclosure further provides a display device, the display device includes a display panel, and the display panel adopts the display panel in the above-mentioned embodiment.
  • the display panel please refer to the content in the previous embodiment, which will not be repeated here. .
  • the display device provided by the embodiment of the present disclosure may specifically be any product or component with a display function, such as a liquid crystal display device, electronic paper, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, and navigator.
  • a display function such as a liquid crystal display device, electronic paper, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, and navigator.

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Abstract

一种显示基板、显示面板和显示装置，其中显示基板包括：第一衬底基板（20）和位于第一衬底基板（20）上的多条栅线（4）、多条数据线（5），栅线（4）沿第一方向（X）延伸，数据线（5）沿第二方向（Y）延伸；多条栅线（4）和多条数据线（5）限定出多个像素单元，像素单元包括：薄膜晶体管（7）、像素电极（8）和公共电极（9），至少部分像素单元配置有导电桥线（10），导电桥线（10）与像素电极（8）同层设置；在配置有导电桥线（10）的像素单元内，像素电极（8）的第一端部或第二端部的第一侧设置有第一镂空结构（13），导电桥线（10）的端部位于第一镂空结构（13）内且与公共电极（9）过孔连接，像素电极（8）的第二端部的第二侧设置有第二镂空结构（14），以使得像素电极（8）与位于两侧且最近的数据线（5）分别形成的寄生电容的差的绝对值小于或等于预设电容差值。

Description

显示基板、显示面板和显示装置 技术领域
本公开涉及显示领域，特别涉及一种显示基板、显示面板和显示装置。
背景技术
高级超维场转换(Advanced super-Dimension Switch)显方式，具有宽视角、响应速度快、对比度高和透过率高等优点，成为了颇受欢迎的显示模式，被很多面板制造厂商用于产品设计中。然而，在实际应用中发现，现有的ADS型显示装置所显示出的画面存在明显的云纹(mura)。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提出了一种显示基板、显示面板和显示装置。
第一方面，本公开实施例提供了一种显示基板，其中，包括：第一衬底基板和位于第一衬底基板上的多条栅线、多条数据线，所述栅线沿第一方向延伸，所述数据线沿第二方向延伸，所述第一方向与所述第二方向交叉且均与所述第一衬底基板所处平面平行；
多条所述栅线和多条所述数据线限定出多个像素单元，所述像素单元包括：薄膜晶体管、像素电极和公共电极，所述像素电极位于所述公共电极远离所述第一衬底基板的一侧，在同一所述像素单元内的所述像素电极所处区域与所述薄膜晶体管所处区域沿第二方向排布，所述像素电极靠近所述薄膜晶体管的一端为第一端部，所述像素电极远离所述薄膜晶体管的一端为第二端部，至少部分所述像素单元配置有导电桥线，所述导电桥线与所述像素电极同层设置；
在配置有所述导电桥线的所述像素单元内，所述像素电极的所述第 一端部或所述第二端部的第一侧设置有第一镂空结构，所述导电桥线的端部位于所述第一镂空结构内且与所述公共电极过孔连接，所述像素电极的所述第二端部的第二侧设置有第二镂空结构，以使得所述像素电极与位于两侧且最近的数据线分别所形成的寄生电容的差的绝对值小于或等于预设电容差值；
所述第一侧和所述第二侧为所述像素电极在第一方向上的相对两侧。
在一些实施例中，所述第二镂空结构和与所述第一镂空结构在所述第二方向上的长度相等。
在一些实施例中，所述第二镂空结构在第一方向上的长度小于或等于所述第一镂空结构在第一方向上的长度。
在一些实施例中，所述像素电极与位于两侧且最近的数据线分别所形成的寄生电容相等。
在一些实施例中，沿所述第一方向排布的多个像素单元对应同一条状公共电极，所述条状公共电极沿所述第一方向延伸；
对应同一条状公共电极的多个像素单元各自所包含的公共电极为该条状公共电极上不同位置的部分。
在一些实施例中，还包括：公共电极线，所述公共电极线与所述栅线同层设置；
沿所述第一方向排布的多个像素单元对应同一条公共电极线，所述像素单元内的公共电极与对应的公共电极线电连接，所述像素单元内的像素电极的所述第二端部在所述第一衬底基板上的正投影与对应的所述公共电极线在所述第一衬底基板上的正投影存在交叠。
在一些实施例中，所述栅线包括：沿第一方向交替设置第一导电图形和第二导电图形，所述第一导电图形在所述第二方向上的长度大于所述第二导电图形在所述第二方向上的长度；
所述第一导电图形在所述第一衬底基板上的正投影与所述数据线在所述第一衬底基板上的正投影不交叠，所述第一导电图形中的部分用作所述薄膜晶体管中的栅极；
所述导电桥线在所述第一衬底基板上的正投影与所述第一导电图形在所述第一衬底基板上的正投影不交叠。
在一些实施例中，所述显示基板中的全部所述像素单元包括：红色像素单元、绿色像素单元和蓝色像素单元；
所述蓝色像素单元配置有所述导电桥线。
在一些实施例中，在部分所述像素单元内设置有第一限位柱和第二限位柱，所述像素单元具有预设出光区域，所述第一限位柱和所述第二限位柱分别位于所述预设出光区域在第二方向上的相对两侧；
所述第一限位柱和第二限位柱均包括：层叠的第一限位图形和第二限位图形，所述第一限位图形与所述栅线同层设置，所述第二限位图形与所述数据线同层设置。
在一些实施例中，所述显示基板中的全部所述像素单元包括：红色像素单元、绿色像素单元和蓝色像素单元；
所述红色像素单元内设置有所述第一限位柱和第二限位柱。
第二方面，本公开实施例还提供了一种显示面板，其中，包括：相对设置的显示基板和对盒基板，所述显示基板和所述对盒基板之间填充有液晶层，所述显示基板采用上述第一方面提供的显示基板。
在一些实施例中，对于任一所述像素单元，在该像素单元的一侧且最近的一条数据线所加载数据电压发生极性反转时，该像素单元中像素电极所加载的电压受所述极性反转影响所产生的变化量为ΔVp：
ΔVp＝Cpd1*ΔVd/(Cpd1+Cpd2+Cst+Clc+Cgp)
Cpd1表示该像素单元中像素电极与发生极性反转的该数据线之间形成的寄生电容，ΔVd表示发生极性反转的该数据线中发生极性反转后 所加载数据电压与发生极性反转前所加载数据电压的差值，Cpd1+Cpd2表示该像素单元中像素电极与位于两侧且最近的数据线分别所形成的寄生电容的和，Cst表示该像素单元中像素电极与公共电极之间的存储电容，Clc表示该像素单元处的液晶电容，Cst表示该像素单元中像素电极与所述栅线之间的寄生电容。
在一些实施例中，所述对盒基板为彩膜基板，所述彩膜基板包括：第二衬底基板、位于所述第二衬底基板上的黑矩阵和彩膜图形；
所述黑矩阵限定出多个像素出光口，所述像素出光口与所述像素单元一一对应，所述彩膜图形位于像素出光口内；
所述黑矩阵在所述第一衬底基板上的正投影完全覆盖所述栅线、所述数据线、所述薄膜晶体管、所述第一镂空结构和所述第二镂空结构在所述第一衬底基板上的正投影。
在一些实施例中，所述像素单元内的所述薄膜晶体管与位于该像素单元的第二侧的所述数据线电连接；
所述像素单元包括：红色像素单元、绿色像素单元和蓝色像素单元；
所述红色像素单元所对应的像素开口的形状包括：第一矩形部以及所述第一矩形部上位于所述第二侧的两个角落区域沿所述第二方向向外延伸所形成的第一凸出部和第二凸出部；
所述绿色像素单元所对应的像素开口形状包括：第二矩形部以及所述第二矩形部上位于所述第一侧的两个角落区域沿所述第二方向向外延伸所形成的第三凸出部和第四凸出部；
所述蓝色像素单元所对应的像素开口形状包括：第三矩形部；
或者，所述蓝色像素单元所对应的像素开口形状包括：第三矩形部、所述第三矩形部上在所述第一侧且同时位于第三侧的1个角落区域沿所述第二方向向外延伸所形成的第五凸出部、所述第三矩形部上在所述第二侧同时位于第四侧的一个角落区域沿所述第二方向向外延伸所形成的 第六凸出部，所述第三侧与所述第四侧为所述第三矩形在所述第二方向上的相对两侧。
在一些实施例中，所述显示基板上设置有第一限位柱和第二限位柱，所述彩膜基板还包括：隔垫物，所述隔垫物位于所述黑矩阵远离所述第二衬底基板的一侧，所述隔垫物在所述显示基板上的投影位于在第二方向上相邻的第一限位柱和第二限位柱之间，且所述相邻的第一限位柱和第二限位柱分别位于在第二方向上相邻的两个像素单元内。
第三方面，本公开实施例还提供了一种显示装置，其中，包括：如上述第二方面提供的所述显示面板。
附图说明
图1为相关技术中配置有容纳导电桥线的像素单元的一种俯视图；
图2为相关技术中配置有容纳导电桥线的像素单元的另一种俯视图；
图3为本公开中像素单元采用Z反转排布方式时的电路结构示意图；
图4为图3中位于同一列且相邻行的两个像素单元的电路结构示意图；
图5为本公开实施例提供的一种显示基板的俯视示意图；
图6为图5中A-A’向的截面示意图；
图7a为本公开实施例中配置有容纳导电桥线的像素单元的一种俯视图；
图7b为本公开实施例中配置有容纳导电桥线的像素单元的另一种俯视图；
图8为本公开实施例提供的一种显示面板的俯视图；
图9为图8中C-C’向的截面示意图；
图10为本公开实施例中红色像素单元所对应的像素开口的形状的 一种示意图；
图11为本公开实施例中绿色像素单元所对应的像素开口的形状的一种示意图；
图12a为本公开实施例中蓝色像素单元所对应的像素开口的形状的一种示意图；
图12b为本公开实施例中蓝色像素单元所对应的像素开口的形状的另一种示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种显示基板、显示面板和显示装置进行详细描述。
为解决相关技术中显示装置所显示画面存在明显云纹的问题，本公开对相关技术中产生云纹的原因进行了分析，并给出了相应的解决方案。
在液晶显示装置中，为避免液晶分子始终朝某一个方向偏转而导致液晶疲劳的问题，因而在显示驱动过程中采用极性反转的方式进行驱动，常见的极性反转方式包括：横反转、列反转和点反转。
在ADS型显示装置中，由于像素单元内的像素电极与两侧的数据之间距离(一般在3um～5um)较近，因此像素电极会与其两侧且最近的数据线之间形成寄生电容。在数据线内所加载的数据电压发生极性反转时，数据线中的数据电压发生较大跳变，通过数据线与像素电极之间的寄生电容耦合，会使得像素电极所加载电压发生变化。为尽可能的减小因数据线中数据电压极性反转对像素电极上所加载电压的影响，往往将显示面板上相邻两条数据线中数据电压的极性设置为相反。此时，对于任一像素单元而言，位于其两侧且最近的数据线中数据电压发生极性反转时，其中一条数据线中数据电压由正极性跳变为负极性(该条数据线与像素电极之间的寄生电容会将像素电极上所加载电压下拉)，另一条数据中 数据电压由负极性跳变为正极性(该条数据线与像素电极之间的寄生电容会将像素电极上所加载电压上拉)，以平衡数据线中数据电压极性反转对像素电极上所加载电压的影响。
图1为相关技术中配置有容纳导电桥线的像素单元的一种俯视图，图2为相关技术中配置有容纳导电桥线3的像素单元的另一种俯视图，如图1和图2所示，一般地，像素单元内的像素电极1整体呈平行四边形(例如，矩形)；然而，在ADS行显示面板中，部分像素单元需要配置导电桥线3(通过过孔与公共电极电连接)，导电桥线3与像素电极1同层设置；由于导电桥线3会占用像素电极1上的部分区域，因此像素电极1上需要设置镂空结构2以容纳导电桥线3的端部。图1中示例性画出了用于容纳导电桥线3的端部的镂空结构2位于像素电极1的左下角的情况，图2中示例性画出了用于容纳导电桥线3的端部的镂空结构2位于像素电极1的左上角情况。
继续参见图1和图2所示，像素电极1上能够与左侧数据线D_L产生寄生电容的第一部分的长度为L1，像素电极1上能够与右侧数据线D_R产生寄生电容的第二部分的长度为L2，此时第一部分与左侧数据线D_L之间的寄生电容为Cpd_L，第二部分与左侧数据线D_L之间的寄生电容为Cpd_R，由于L1＜L2，因此Cpd_L＜Cpd_R，Cpd_L与Cpd_R之间的差值大小记为ΔCpd，ΔCpd＝|Cpd_L-Cpd_R|。通过实际测量发现，L2-L1＞20微米(um)，ΔCpd＝|Cpd_L-Cpd_R|＞1.2飞法(fF)。由于ΔCpd值较大，导致即便左右两侧数据线中同时进行不同极性反转，像素电极1上所加载电压也会产生较大的改变，该像素单元的亮度变化大于2个灰阶，用户可明显感受到的亮度异常。
图3为本公开中像素单元采用Z反转排布方式时的电路结构示意图，如图3所示，以显示基板中的像素单元采用Z反转(Z-inversion)排布方式布置为例；具体地，位于第i行的像素单元与第i条栅线 G1/G2/G3/G4连接，位于奇数行的各像素单元分别与位于其第一侧(附图中像素单元的左侧)且最近的一条数据线连接，位于偶数行的各像素单元分别与位于其第二侧(附图中像素单元的右侧)且最近的一条数据线连接。在进行像素驱动时，采用列反转的方式进行驱动，即相邻数据线中所加载数据电压的极性相反，可使得显示面板达到点反转的效果。附图3中示例性给出了位于奇数列数据线D1、D3、D5、D7、D9中所加载数据电压为正极性(+)，位于偶数列数据线D2、D4、D6、D8中所加载数据电压为正极性(-)的情况。
图4为图3中位于同一列且相邻行的两个像素单元的电路结构示意图，如图4所示，位于M行的像素单元中像素电极1所加载的电压为正极性，位于M+1行的像素单元中像素电极1所加载的电压为负极性，左侧数据线D_L所加载数据电压由正极性跳变为负极性，右侧数据线D_R所加载数据电压由负极性跳变为正极性。
左侧数据线D_L所加载数据电压发生极性反转(由正极性跳变为负极性)时，通过左侧数据线D_L与像素电极1之间的寄生电容的耦合作用，会使得像素电极1所加载电压拉低ΔVp_L：
ΔVp_L＝Cpd_L*ΔVd_L/(Cpd_L+Cpd_R+Cst+Clc+Cgp)；
Cpd_L表示像素电极1与左侧数据线D_L之间形成的寄生电容，Cpd_R表示像素电极1与右侧数据线D_R之间形成的寄生电容，ΔVd_L表示左侧数据线D_L中数据电压发生极性反转的电压变化量(极性反转后的数据电压与极性反转前数据电压的差的绝对值)，Cst表示像素电极1与公共电极之间的存储电容，Clc表示像素单元处的液晶电容，Cst表示像素电极1与所述栅线之间的寄生电容。
右侧数据线D_R所加载数据电压发生极性反转(由负极性跳变为正极性)时，通过左侧数据线D_L与像素电极1之间的寄生电容的耦合作用，会使得像素电极1所加载电压拉高ΔVp_R：
ΔVp_R＝Cpd_R*ΔVd_R/(Cpd_L+Cpd_R+Cst+Clc+Cgp)
ΔVd_R表示右侧数据线D_R中数据电压发生极性反转的电压变化量(极性反转后的数据电压与极性反转前数据电压的差的绝对值)。
为方便描述，设定ΔVd_L＝ΔVd_R，则在左右两侧数据线中数据电压发生极性反转后，像素电极1上的电压变化量为|ΔVp_L-ΔVp_R|：|ΔVp_L-ΔVp_R|＝|Cpd_L-Cpd_R|*ΔVd_R/(Cpd_L+Cpd_R+Cst+Clc+Cgp)
以像素电极1采用图1中所示情况为例，Cpd_L＜Cpd_R，因此像素电极1上的电压会被上拉(Cpd_R-Cpd_L)*ΔVd_R/(Cpd_L+Cpd_R+Cst+Clc+Cgp)。对于M行像素单元而言，其所加载正极性电压的电压大小上升，显示亮度增大；对于M+1行像素单元而言，其所加载负极性电压的电压大小下降，显示亮度减小；相邻两行像素单元亮度差异明显，产生横向mura，且|Cpd_L-Cpd_R|的值越大，亮度差异越明显。
为解决相关技术中因在像素电极1上开设用于容纳导电桥线3的镂空结构2，而导致像素电极1与左、右两侧数据线分别形成的寄生电容的差异较大，进而使得像素单元在显示过程中存在明显异常的技术问题，本公开实施例提供了相应的解决方案。
图5为本公开实施例提供的一种显示基板的俯视示意图，图6为图5中A-A’向的截面示意图，如图5和图6所示，该显示基板为ADS型显示基板，该显示基板包括：第一衬底基板20和位于第一衬底基板20上的多条栅线4、多条数据线5，栅线4沿第一方向X延伸，数据线5沿第二方向Y延伸，第一方向X与第二方向Y交叉且均与第一衬底基板20所处平面平行。在本公开实施例中，以第一方向X为行方向、第二方向Y为列方向为例，进行示例性描述。
多条栅线4和多条数据线5限定出多个像素单元，像素单元包括：薄膜晶体管7、像素电极8和公共电极9，像素电极8为狭缝电极且位于 公共电极9远离第一衬底基板20的一侧，在同一像素单元内的像素电极8所处区域与薄膜晶体管7所处区域沿第二方向Y排布，像素电极8靠近薄膜晶体管7的一端为第一端部，像素电极8远离薄膜晶体管7的一端为第二端部，至少部分像素单元配置有导电桥线10，导电桥线10与像素电极8同层设置。
其中，薄膜晶体管7包括：栅极、源极15、漏极16和有源层17。图5中仅示例性画出了每个像素单元中的薄膜晶体管7的栅极与对应行栅线4连接，每个像素单元中的薄膜晶体管7的源极15与自身右侧且最近的一条数据线5连接的情况，这种情况仅起到示例性作用，其不会对本公开的技术方案产生限制。本公开中像素单元的排布方式还可采用其他方式，例如采用Z反转排布方式进行排布。
另外，图5中仅示例性给出了每3个像素单元中存在1个像素单元配置有导电桥线10，这种情况仅起到示例性作用，其不会对本公开的技术方案产生限制。在实际应用中，可以是每个像素单元中均配置有导电桥线10，也可以是部分像素单元中配置有导电桥线10。
图7a为本公开实施例中配置有容纳导电桥线的像素单元的一种俯视图，图7b为本公开实施例中配置有容纳导电桥线10的像素单元的另一种俯视图，如图7a和7b所示，在配置有导电桥线10的像素单元内，像素电极8的第一端部或第二端部的第一侧设置有第一镂空结构13，导电桥线10的端部位于第一镂空结构13内且与公共电极9过孔连接，像素电极8的第二端部的第二侧设置有第二镂空结构14，以使得像素电极8与位于两侧且最近的数据线5分别所形成的寄生电容的差的绝对值小于或等于预设电容差值；第一侧和第二侧为像素电极8在第一方向X上的相对两侧。以图5中所示情况为例，第一侧具体是指左侧，第二侧具体是指右侧。
需要说明的是，在图7a和图7b所示情况中，像素电极8的第一端 部和第二端部分别指像素电极8的上端部和下端部。图7a中示例性画出了第一镂空结构13位于下端部的左侧(第一镂空结构13位于像素单元的左下角)的情况，图7b中示例性画出了第一镂空结构13位于上端部左侧(第一镂空结构13位于像素单元的左上角)的情况，相应地第二镂空结构14位于上端部的右侧，图7a和图7b所示情况均起到示例性作用，其不会对本公开的技术方案产生限制。
在一些实施例中，第二镂空结构14和与第一镂空结构13在第二方向Y上的长度相等，有利于实现像素电极8与位于两侧且最近的数据线5分别所形成的寄生电容相等或近似相等。
一般而言，像素电极8上与数据线5在水平方向上距离小于6um的部分，能够与数据线5之间形成寄生电容。为方便描述，将像素电极8上能够与左侧数据线5形成寄生电容的部分称为第一部分，像素电极8上能够与右侧数据线5形成寄生电容的部分称为第二部分。
在本公开实施例中，通过在设置有第一镂空结构13的像素电极8上设置上述第二镂空结构14，且第二镂空结构14和与第一镂空结构13在第二方向Y第二方向X上的长度相等或相近，以使得像素电极8上的第一部分在第二方向Y上的长度L1，像素电极8上的第二部分在第二方向Y上的长度L2，L1与L2两者相等或相近，从而使得第一部分与左侧数据线5之间形成的寄生电容Cpd_L，第二部分与右侧数据线5之间形成的寄生电容Cpd_2，满足|Cpd_L-Cpd_R|小于或等于预设电容差值，进而能有效减小甚至消除像素电极8两侧数据线5中数据电压同时发生极性反转时对像素电极8上所加载电压的影响，有利于减弱甚至消除mura。
考虑到若第二镂空结构14在第二方向Y上的长度过长，则会对像素开口率造成一定影响；为此，在一些实施例中，可在满足|Cpd_L-Cpd_R|小于或等于预设电容差值的情况下，使得第二镂空结构14在第二方向Y上的长度不大于第一镂空结构在Y方向的长度。
在一些实施例中，预设电容差值小于或等于1.0fF。其中，当像素电极8与位于两侧且最近的数据线5分别所形成的寄生电容相等时，即Cpd_L＝Cpd_R，可有效消除像素电极8两侧数据线5中数据电压同时发生极性反转时对像素电极8上所加载电压的影响，从而能有效消除mura。
在实际应用中发现，像素电极8上与数据线5在第一方向X上的距离大于6um的部分，由于距离数据线5相对较远，因而不会产生明显的寄生电容。另外，第二镂空结构14在第一方向X上的长度也不宜过大，因为其在第一方向X上的长度越大，则像素电极8的整体尺寸越小，像素电极8与公共电极9之间所形成存储电容减小，像素电极8维持灰阶电压的能力减弱。基于对上述因素考量，在本公开实施例中，第二镂空结构14在第一方向X上的长度大于或等于6um且小于或等于第一镂空结构13在第一方向X上的长度。
在一些实施例中，沿第一方向X排布的多个像素单元对应同一条状公共电极9，条状公共电极9沿第一方向X延伸，对应同一条状公共电极的多个像素单元各自所包含的公共电极为该条状公共电极9上不同位置的部分。即，位于同一行的像素单元对应同一个条状公共电极9。
在一些实施例中，显示基板还包括公共电极线6，公共电极线6与栅线4同层设置，沿第一方向X排布的多个像素单元对应同一条公共电极线6，像素单元内的公共电极9与对应的公共电极线6电连接，像素电极8的第二端部在第一衬底基板20上的正投影与对应的公共电极线6在第一衬底基板20上的正投影存在交叠。
需要说明的是，本公开中的两个结构“同层设置”是指，该两个结构基于同一材料薄膜的构图所得到，该两个结构与衬底基板之间的距离可以相等也可以不等。
参见图6所示，在本公开实施例中，公共电极9直接搭接在公共电极线6上。由于像素电极8的第二端部在第一衬底基板20上的正投影与 公共电极线6在第一衬底基板20上的正投影存在交叠，因此在第二端部所设置的第二镂空结构14与公共电极线6存在交叠。由于公共电极线6所在区域会被黑矩阵所覆盖，因此第二镂空结构14的设置不会对像素单元的开口率造成实质影响。优选地，第二镂空结构14在第一衬底基板20上的正投影位于公共电极线6在第一衬底基板20上的正投影所限定的区域内，此时第二镂空结构14的设置不会对像素单元的开口率造成影响。
在一些实施例中，栅线4包括沿第一方向X交替设置第一导电图形4a和第二导电图形4b，第一导电图形4a在第二方向Y上的长度大于第二导电图形4b在第二方向Y上的长度；第一导电图形4a在第一衬底基板20上的正投影与数据线5在第一衬底基板20上的正投影不交叠，第一导电图形4a中的部分用作薄膜晶体管7中的栅极；导电桥线10在第一衬底基板20上的正投影与第一导电图形4a在第一衬底基板20上的正投影不交叠。
在本公开实施例中，第一导电图形4a在第二方向Y上的长度较大，可有效降低栅线4的整体电阻，有利于信号的加载与传递。与此同时，第二导电图形4b在第二方向Y上的长度较小，其与数据线5、导电桥线10之间的正对面板相对较小，因此所形成的寄生电容也相对较小，可有效减小栅线4与数据线5、导电桥线10之间的信号串扰。
在一些实施例中，显示基板中的全部像素单元包括：红色像素单元、绿色像素单元和蓝色像素单元；蓝色像素单元配置有导电桥线10。其中，红色像素单元的出光区域面积小于蓝色像素单元的出光面积，蓝色像素单元的出光面积小于绿色像素单元的出光面积。一般而言，在相同的开口率时，绿色像素的光透过率最高，因此不会牺牲绿色像素的开口率，因此选择在蓝色像素单元内配置导电桥线。
在一些实施例中，在部分像素单元内设置有第一限位柱11和第二限 位柱12，像素单元具有预设出光区域，第一限位柱11和第二限位柱12分别位于预设出光区域在第二方向Y上的相对两侧；第一限位柱11和第二限位柱12均包括：层叠的第一限位图形11a、12a和第二限位图形11b、12b，第一限位图形11a、12a与栅线4同层设置，第二限位图形11b、12b与数据线5同层设置。第一限位柱11和第二限位柱12用于在显示基板与对盒基板完成对盒后限定隔垫物18的位置，以防止隔垫物18滑动。
在一些实施例中，红色像素单元内设置有第一限位柱11和第二限位柱12。限位柱的设置会使得所在像素单元的开口率降低，影响光透过率；另外，人眼对绿色最敏感，在相同开口率的情况下，绿色像素单元的光透过率最高的，所以不会牺牲绿色像素单元的开口率。而蓝色像素单元的开口率对色温影响较大，蓝色开口率越大，色温越高，因此一般也不会牺牲蓝色像素单元的开口率。基于上述考虑，将限位柱放置于红色像素单元内。
图8为本公开实施例提供的一种显示面板的俯视图，图9为图8中C-C’向的截面示意图，图9为如图8所示，该显示面板包括：相对设置的显示基板和对盒基板，显示基板和对盒基板之间填充有液晶层22，显示基板采用上述实施例提供的显示基板，对于显示基板的描述可参见前面实施例中的内容，此处不再赘述。
在一些实施例中，对于任一像素单元，在该像素单元的一侧且最近的一条数据线5所加载数据电压发生极性反转时，该像素单元中像素电极8所加载的电压受极性反转影响所产生的变化量为ΔVp：
ΔVp＝Cpd1*ΔVd/(Cpd1+Cpd2+Cst+Clc+Cgp)
其中，Cpd1表示该像素单元中像素电极8与发生极性反转的该数据线5之间形成的寄生电容，ΔVd表示发生极性反转的该数据线5中发生极性反转后所加载数据电压与发生极性反转前所加载数据电压的差值， Cpd1+Cpd2表示该像素单元中像素电极8与位于两侧且最近的数据线5分别所形成的寄生电容的和，Cst表示该像素单元中像素电极8与公共电极9之间的存储电容，Clc表示该像素单元处的液晶电容，Cst表示该像素单元中像素电极8与栅线4之间的寄生电容。
在一些实施例中，对盒基板为彩膜基板，彩膜基板包括：第二衬底基板21、位于第二衬底基板21上的黑矩阵22和彩膜图形19；黑矩阵22限定出多个像素出光口，像素出光口与像素单元一一对应以限定出像素单元的出光区域，彩膜图形19位于像素出光口内；黑矩阵22在第一衬底基板20上的正投影完全覆盖栅线4、数据线5、薄膜晶体管7、第一镂空结构13和第二镂空结构14在第一衬底基板20上的正投影。
在一些实施例中，在一些实施例中，像素单元内的薄膜晶体管与位于该像素单元的第二侧的数据线电连接；像素单元包括：红色像素单元R、绿色像素单元G和蓝色像素单元B。
图10为本公开实施例中红色像素单元所对应的像素开口的形状的一种示意图，如图10所示，在一些实施例中，红色像素单元R所对应的像素开口的形状包括：第一矩形部r_1以及第一矩形部r_1上位于第二侧的两个角落区域沿第二方向Y向外延伸所形成的第一凸出部r_2和第二凸出部r_3。
图11为本公开实施例中绿色像素单元所对应的像素开口的形状的一种示意图，如图11所示，在一些实施例中，绿色像素单元G所对应的像素开口形状包括：第二矩形部g_1以及第二矩形部g_1上位于第一侧的两个角落区域沿第二方向Y向外延伸所形成的第三凸出部g_2和第四凸出部g_3。
图12a为本公开实施例中蓝色像素单元所对应的像素开口的形状的一种示意图，如图12a所示，在一些实施例中，蓝色像素单元B所对应的像素开口形状包括：第三矩形部b_1。
图12b为本公开实施例中蓝色像素单元所对应的像素开口的形状的另一种示意图，如图12b所示，蓝色像素单元B所对应的像素开口形状包括：第三矩形部b_1、第三矩形部b_1上在第一侧且同时位于第三侧的1个角落区域(位于左下侧的角落区域)沿第二方向Y向外延伸所形成的第五凸出部b_2、第三矩形部b_1上在第二侧同时位于第四侧的一个角落区域(位于右上侧的角落区域)沿第二方向Y向外延伸所形成的第六凸出部b_3；第三侧与第四侧为第三矩形在第二方向Y上的相对两侧。以图8、图12b中所示，第三侧具体是指下侧，第四侧具体是指上侧。
需要说明的是，图8、图10～12b所示像素开口的形状，仅起到示例性作用，其不会对本公开的技术方案产生限制，在实际应用中，可根据实际需要来对像素开口进行设计和调整。
图8所示显示面板中示例性画出了全部像素单元包括：红色像素单元R、绿色像素单元G和蓝色像素单元B，且绿色像素单元G配置有导电桥线10,红色像素单元R内设置有第一限位柱11和第二限位柱12的情况。
在一些实施例中，显示基板中设置有第一限位柱11和第二限位柱12，彩膜基板还包括：隔垫物18，隔垫物18位于黑矩阵22远离第二衬底基板21的一侧，隔垫物18在显示基板上的投影位于在第二方向Y上相邻的第一限位柱11和第二限位柱12之间，且相邻的第一限位柱11和第二限位柱12分别位于在第二方向Y上相邻的两个像素单元内。通过限位柱可实现对隔垫物18的位置进行限定，以防止隔垫物18滑动至像素单元的出光区域。
本公开实施例还提供了一种显示装置，该显示装置包括显示面板，该显示面板采用上述实施例中的显示面板，对于显示面板的描述可参见前面实施例中的内容，此处不再赘述。
本公开实施例提供的显示装置具体可以为液晶显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (16)

  1. 一种显示基板，其中，包括：第一衬底基板和位于第一衬底基板上的多条栅线、多条数据线，所述栅线沿第一方向延伸，所述数据线沿第二方向延伸，所述第一方向与所述第二方向交叉且均与所述第一衬底基板所处平面平行；
    多条所述栅线和多条所述数据线限定出多个像素单元，所述像素单元包括：薄膜晶体管、像素电极和公共电极，所述像素电极位于所述公共电极远离所述第一衬底基板的一侧，在同一所述像素单元内的所述像素电极所处区域与所述薄膜晶体管所处区域沿第二方向排布，所述像素电极靠近所述薄膜晶体管的一端为第一端部，所述像素电极远离所述薄膜晶体管的一端为第二端部，至少部分所述像素单元配置有导电桥线，所述导电桥线与所述像素电极同层设置；
    在配置有所述导电桥线的所述像素单元内，所述像素电极的所述第一端部或所述第二端部的第一侧设置有第一镂空结构，所述导电桥线的端部位于所述第一镂空结构内且与所述公共电极过孔连接，所述像素电极的所述第二端部的第二侧设置有第二镂空结构，以使得所述像素电极与位于两侧且最近的所述数据线分别所形成的寄生电容的差的绝对值小于或等于预设电容差值；
    所述第一侧和所述第二侧为所述像素电极在第一方向上的相对两侧。
  2. 根据权利要求1所述的显示基板，其中，所述第二镂空结构和与所述第一镂空结构在所述第二方向上的长度相等。
  3. 根据权利要求1所述的显示基板，其中，所述第二镂空结构在第 一方向上的长度小于或等于所述第一镂空结构在第一方向上的长度。
  4. 根据权利要求1所述的显示基板，其中，所述像素电极与位于两侧且最近的数据线分别所形成的寄生电容相等。
  5. 根据权利要求1所述的显示基板，其中，沿所述第一方向排布的多个像素单元对应同一条状公共电极，所述条状公共电极沿所述第一方向延伸；
    对应同一条状公共电极的多个像素单元各自所包含的公共电极为该条状公共电极上不同位置的部分。
  6. 根据权利要求1所述的显示基板，其中，还包括：公共电极线，所述公共电极线与所述栅线同层设置；
    沿所述第一方向排布的多个像素单元对应同一条公共电极线，所述像素单元内的公共电极与对应的公共电极线电连接，所述像素单元内的像素电极的所述第二端部在所述第一衬底基板上的正投影与对应的所述公共电极线在所述第一衬底基板上的正投影存在交叠。
  7. 根据权利要求6所述的显示基板，其中，所述栅线包括：沿第一方向交替设置第一导电图形和第二导电图形，所述第一导电图形在所述第二方向上的长度大于所述第二导电图形在所述第二方向上的长度；
    所述第一导电图形在所述第一衬底基板上的正投影与所述数据线在所述第一衬底基板上的正投影不交叠，所述第一导电图形中的部分用作所述薄膜晶体管中的栅极；
    所述导电桥线在所述第一衬底基板上的正投影与所述第一导电图形在所述第一衬底基板上的正投影不交叠。
  8. 根据权利要求1所述的显示基板，其中，所述显示基板中的全部所述像素单元包括：红色像素单元、绿色像素单元和蓝色像素单元；
    所述蓝色像素单元配置有所述导电桥线。
  9. 根据权利要求1-8中任一所述的显示基板，其中，在部分所述像素单元内设置有第一限位柱和第二限位柱，所述像素单元具有预设出光区域，所述第一限位柱和所述第二限位柱分别位于所述预设出光区域在第二方向上的相对两侧；
    所述第一限位柱和第二限位柱均包括：层叠的第一限位图形和第二限位图形，所述第一限位图形与所述栅线同层设置，所述第二限位图形与所述数据线同层设置。
  10. 根据权利要求9所述的显示基板，所述显示基板中的全部所述像素单元包括：红色像素单元、绿色像素单元和蓝色像素单元；
    所述红色像素单元内设置有所述第一限位柱和第二限位柱。
  11. 一种显示面板，其中，包括：相对设置的显示基板和对盒基板，所述显示基板和所述对盒基板之间填充有液晶层，所述显示基板采用上述权利要求1-10中任一所述的显示基板。
  12. 根据权利要求11所述的显示面板，其中，对于任一所述像素单元，在该像素单元的一侧且最近的一条数据线所加载数据电压发生极性反转时，该像素单元中像素电极所加载的电压受所述极性反转影响所产生的变化量为ΔVp：
    ΔVp＝Cpd1*ΔVd/(Cpd1+Cpd2+Cst+Clc+Cgp)
    Cpd1表示该像素单元中像素电极与发生极性反转的该数据线之间形成的寄生电容，ΔVd表示发生极性反转的该数据线中发生极性反转后所加载数据电压与发生极性反转前所加载数据电压的差值，Cpd1+Cpd2表示该像素单元中像素电极与位于两侧且最近的数据线分别所形成的寄生电容的和，Cst表示该像素单元中像素电极与公共电极之间的存储电容，Clc表示该像素单元处的液晶电容，Cst表示该像素单元中像素电极与所述栅线之间的寄生电容。
  13. 根据权利要求12所述的显示面板，其中，所述对盒基板为彩膜基板，所述彩膜基板包括：第二衬底基板、位于所述第二衬底基板上的黑矩阵和彩膜图形；
    所述黑矩阵限定出多个像素出光口，所述像素出光口与所述像素单元一一对应，所述彩膜图形位于像素出光口内；
    所述黑矩阵在所述第一衬底基板上的正投影完全覆盖所述栅线、所述数据线、所述薄膜晶体管、所述第一镂空结构和所述第二镂空结构在所述第一衬底基板上的正投影。
  14. 根据权利要求13所述的显示面板，其中，所述像素单元内的所述薄膜晶体管与位于该像素单元的第二侧的所述数据线电连接；
    所述像素单元包括：红色像素单元、绿色像素单元和蓝色像素单元；
    所述红色像素单元所对应的像素开口的形状包括：第一矩形部以及所述第一矩形部上位于所述第二侧的两个角落区域沿所述第二方向向外延伸所形成的第一凸出部和第二凸出部；
    所述绿色像素单元所对应的像素开口形状包括：第二矩形部以及所述第二矩形部上位于所述第一侧的两个角落区域沿所述第二方向向外延伸所形成的第三凸出部和第四凸出部；
    所述蓝色像素单元所对应的像素开口形状包括：第三矩形部；
    或者，所述蓝色像素单元所对应的像素开口形状包括：第三矩形部、所述第三矩形部上在所述第一侧且同时位于第三侧的1个角落区域沿所述第二方向向外延伸所形成的第五凸出部、所述第三矩形部上在所述第二侧同时位于第四侧的一个角落区域沿所述第二方向向外延伸所形成的第六凸出部，所述第三侧与所述第四侧为所述第三矩形在所述第二方向上的相对两侧。
  15. 根据权利要求13所述的显示面板，其中，所述显示基板采用上述权利要求10中所述显示基板，所述彩膜基板还包括：隔垫物，所述隔垫物位于所述黑矩阵远离所述第二衬底基板的一侧，所述隔垫物在所述显示基板上的投影位于在第二方向上相邻的第一限位柱和第二限位柱之间，且所述相邻的第一限位柱和第二限位柱分别位于在第二方向上相邻的两个像素单元内。
  16. 一种显示装置，其中，包括：如上述权利要求11-15中任一所述的显示面板。
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