WO2023201816A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023201816A1
WO2023201816A1 PCT/CN2022/093563 CN2022093563W WO2023201816A1 WO 2023201816 A1 WO2023201816 A1 WO 2023201816A1 CN 2022093563 W CN2022093563 W CN 2022093563W WO 2023201816 A1 WO2023201816 A1 WO 2023201816A1
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WO
WIPO (PCT)
Prior art keywords
data line
line connection
lines
layer
fan
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Application number
PCT/CN2022/093563
Other languages
English (en)
French (fr)
Inventor
牛艳芬
王瑞芳
李世泽
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2023201816A1 publication Critical patent/WO2023201816A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel and a display device.
  • AMOLED(Active-matrix Organic light emitting diode (active matrix organic light emitting diode) display panel has gradually replaced LCD (Liquid Crystal Display) as a new generation of display due to its display advantages such as high contrast, wide color gamut, and low power consumption. technology. Compared with traditional LCD panels, OLED display panels are easy to be flexible and are a key technology for wearable and foldable products.
  • OLED displays are not limited to the development of wearable and foldable products.
  • narrow bezel technology has gradually become a highlight to attract user groups.
  • the frame of the panel is still large.
  • This application provides a display panel and a display device.
  • the data line connection line is also arranged in the display area, which is beneficial to reducing the peripheral frame of the display area and reducing the digging area. borders, achieving extremely narrow borders.
  • the present application provides a display panel having adjacently arranged digging areas and display areas;
  • the display panel includes a driving array substrate located in the display area and a light emitting device layer located on the driving array substrate.
  • the driving array substrate includes a substrate and a driving circuit layer and a fan-out wiring layer located on the substrate in sequence;
  • the driving circuit layer includes a plurality of first data lines and a plurality of second data lines extending along a first direction; the second data lines are divided into first sub-sections in the first direction by the digging areas. data lines and second sub-data lines; the fan-out wiring layer includes a plurality of fan-out wiring lines electrically connected to the plurality of first data lines and the plurality of second data lines in a one-to-one correspondence and connected to the plurality of first data lines and the plurality of second data lines.
  • Each second data line corresponds to a plurality of electrically connected data line connection lines; both ends of the data line connection line are electrically connected to the corresponding first sub-data line and the corresponding second sub-data line respectively.
  • the data line connection lines are arranged on the same layer as at least part of the fan-out wiring lines.
  • the fan-out wiring layer includes a first wiring layer and a second wiring layer located on the driving circuit layer in sequence;
  • the fan-out wiring is located at least in one of the first wiring layer and the second wiring layer;
  • the data line connection line is located at least in one of the first wiring layer and the second wiring layer.
  • the driving circuit layer further includes a plurality of scanning lines extending in a second direction perpendicular to the first direction; the plurality of scanning lines and the plurality of first data The lines and the plurality of second data lines are insulated and intersected to form a plurality of pixel areas arranged in multiple rows and columns;
  • the data line connection line includes a first data line connection part extending along the first direction, a second data line connection part extending along the second direction, and a third data line connection part; the second data line One end of the connecting portion is electrically connected to the corresponding first sub-data line, and the other end is electrically connected to one end of the first data line connecting portion; the other end of the first data line connecting portion is electrically connected to the third data line.
  • One end of the line connection part is electrically connected; the other end of the third data line connection part is electrically connected to the corresponding second sub-data line;
  • the first data line connection part is arranged corresponding to a plurality of the pixel areas in the column direction, and the second data line connection part and the third data line connection part are connected to two different pixel areas in the row direction. A plurality of the pixel areas are set correspondingly.
  • each of the pixel areas includes at least one wiring hole extending in a direction perpendicular to the display panel and used to connect different metal layers;
  • the first data line connection part includes A bending portion is provided corresponding to the line-changing hole in the corresponding pixel area; the bending portion is bent in a direction away from the corresponding line-changing hole.
  • the shape of the bent portion includes any one of a rectangle, a triangle, and an arc.
  • the orthographic projection of at least one first data line on the substrate is located at the orthographic projection of two adjacent first data line connecting portions on the substrate. between.
  • At least part of the first data line connection portion overlaps with the corresponding middle position of the plurality of pixel areas.
  • the display area is arranged around the hole-digging area, and the hole-digging area is symmetrical about a symmetry axis extending along the first direction; the plurality of data line connecting lines are about The symmetry axis is symmetrically arranged.
  • the material of the fan-out traces and the data line connection lines includes indium tin oxide.
  • the present application also provides a display device, including the above-mentioned display panel and a driving integrated circuit; the display panel further includes a binding area located on one side of the display area; the driving integrated circuit and the driving integrated circuit The binding area is bonded and connected; the fan-out trace extends from the display area to the binding area and is electrically connected to the driving integrated circuit.
  • the data line connection lines are arranged on the same layer as at least part of the fan-out wiring lines.
  • the fan-out wiring layer includes a first wiring layer and a second wiring layer located on the driving circuit layer in sequence;
  • the fan-out wiring is located at least in one of the first wiring layer and the second wiring layer;
  • the data line connection line is located at least in one of the first wiring layer and the second wiring layer.
  • the driving circuit layer further includes a plurality of scanning lines extending in a second direction perpendicular to the first direction; the plurality of scanning lines and the plurality of first data The lines and the plurality of second data lines are insulated and intersected to form a plurality of pixel areas arranged in multiple rows and columns;
  • the data line connection line includes a first data line connection part extending along the first direction, a second data line connection part extending along the second direction, and a third data line connection part; the second data line One end of the connecting portion is electrically connected to the corresponding first sub-data line, and the other end is electrically connected to one end of the first data line connecting portion; the other end of the first data line connecting portion is electrically connected to the third data line.
  • One end of the line connection part is electrically connected; the other end of the third data line connection part is electrically connected to the corresponding second sub-data line;
  • the first data line connection part is arranged corresponding to a plurality of the pixel areas in the column direction, and the second data line connection part and the third data line connection part are connected to two different pixel areas in the row direction. A plurality of the pixel areas are set correspondingly.
  • each of the pixel areas includes at least one wiring hole extending in a direction perpendicular to the display panel and used to connect different metal layers;
  • the first data line connection part includes A bending portion is provided corresponding to the line-changing hole in the corresponding pixel area; the bending portion is bent in a direction away from the corresponding line-changing hole.
  • the shape of the bent portion includes any one of a rectangle, a triangle, and an arc.
  • the orthographic projection of at least one first data line on the substrate is located at the orthographic projection of two adjacent first data line connecting portions on the substrate. between.
  • At least part of the first data line connection portion overlaps with the corresponding middle position of the plurality of pixel areas.
  • the display area is arranged around the hole-digging area, and the hole-digging area is symmetrical about a symmetry axis extending along the first direction; the plurality of data line connecting lines are about The symmetry axis is symmetrically arranged.
  • the material of the fan-out traces and the data line connection lines includes indium tin oxide.
  • the display panel and display device provided by this application arrange the fan-out wiring and the data line connection line in the display area, specifically in the fan-out wiring layer located on the driving circuit layer, so that the fan-out wiring
  • the data line connecting line and the first data line and the second data line in the driving circuit layer are arranged in different layers; on the one hand, it is possible to avoid setting the fan-out lines in the non-display area to reduce the width of the frame around the display area; on the other hand, On the one hand, it can avoid setting the data line connecting lines at the edge of the digging area, which is helpful to reduce the frame width of the digging area; on the other hand, it can avoid setting the fan-out traces and data line connecting lines in the driving circuit layer , thereby avoiding unstable signal transmission caused by too dense wiring; therefore, this application achieves an extremely narrow frame of the display panel while ensuring a stable display effect.
  • FIG. 1 is a top view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a partial cross-sectional structural diagram of a pixel area of a display panel provided by an embodiment of the present application.
  • Figure 3 is a partial enlarged view of part A in Figure 1.
  • Figure 4 is a partial enlarged view of part B in Figure 1.
  • FIG. 5 is a top view of a partial structure of a display area of a display panel provided by an embodiment of the present application.
  • FIG. 6 is a top view of a partial structure of a display area of another display panel provided by an embodiment of the present application.
  • FIG. 7 is a top view of a data line connection provided by an embodiment of the present application.
  • FIG. 8 is a top view of a display device provided by an embodiment of the present application.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the described features.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, or indirect connection through an intermediary, it can be internal connection of two elements or interaction of two elements relation.
  • the term “above” or “below” a first feature on a second feature may include direct contact between the first and second features, or may also include the first and second features. Not in direct contact but through additional characteristic contact between them.
  • the terms “above”, “above” and “above” a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature.
  • “Below”, “under” and “under” the first feature is the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature is less horizontally than the second feature.
  • embodiments of the present application provide a display panel 1; the display panel 1 has a hole-digging area 2 and a display area 3 arranged adjacent to the hole-digging area 2; as shown in FIG. 2, the display panel 1
  • the panel 1 includes a driving array substrate 4 located in the display area 3 and a light emitting device layer 5 located on the driving array substrate 4; the driving array substrate 4 includes a substrate 6 and a driving circuit layer 7 and a fan-out wiring layer located on the substrate 6 in sequence.
  • the driving circuit layer 7 includes a plurality of first data lines 9 and a plurality of second data lines 10 extending in a first direction (such as a vertical direction, ie, the column direction below); the second data lines 10 are in the first Directionally divided by the drilling area 2 into a first sub-data line 11 and a second sub-data line 12; as shown in Figures 3 and 4, the fan-out wiring layer 8 includes a plurality of first data lines 9 and a plurality of third data lines.
  • the two data lines 10 correspond to a plurality of fan-out lines 13 that are electrically connected one to one and a plurality of data line connection lines 14 that are electrically connected to the plurality of second data lines 10; both ends of the data line connection line 14 are respectively connected to the corresponding second data lines 10.
  • One sub-data line 11 and the second sub-data line 12 are electrically connected.
  • the data line connection line 14 used to connect the first sub-data line 11 and the second sub-data line 12 is routed to the display area 3 to avoid arranging the data line connection line 14 in the hole-digging area 2 edges, which can effectively reduce the frame width of the hole-digging area 2; and, in this embodiment of the present application, the fan-out traces 13 used to transmit data signals to the first data line 9 and the second data line 10 are arranged in the display area 3 , avoid arranging the fan-out trace 13 in the non-display area, which can effectively reduce the width of the peripheral frame (non-display area) of the display area 3, that is, reduce the width of the peripheral frame of the display panel 1.
  • the display panel 1 includes a through hole located in the digging area 2 and penetrating at least the driving array substrate 4 and the light-emitting device layer 5 of the display panel 1 in a direction perpendicular to the display panel 1 for setting an under-screen camera or other optical components. device.
  • the display area 3 can be arranged around the entire hole-digging area 2 or along part of the edge of the hole-digging area 2, which is not limited here.
  • the embodiment of the present application takes as an example that the display area 3 is arranged around the hole-digging area 2 .
  • the substrate 6 of the driving array substrate 4 may be a flexible substrate.
  • the substrate 6 includes a first flexible layer 15 and a first buffer layer 16 and a second flexible layer 17 sequentially disposed on the first flexible layer 15 ; wherein, the first flexible layer
  • the material of the layer 15 and the second flexible layer 17 is an organic material, such as polyimide (PI), and the material of the first buffer layer 16 is an inorganic material, such as at least one of silicon oxide and silicon nitride.
  • PI polyimide
  • a second buffer layer 18 is provided on the side of the driving circuit layer 7 close to the substrate 6 ; of course, in other implementations, the side of the driving circuit layer 7 close to the substrate 6 is also provided.
  • a barrier layer can also be provided on one side, and the sequence of the second buffer layer 18 and the barrier layer is not limited.
  • the driving circuit layer 7 of the driving array substrate 4 includes a plurality of pixel driving circuit units 19 distributed in an array, and a plurality of data lines electrically connected to the plurality of pixel driving circuit units 19 (for example, a plurality of first data lines 9 and a plurality of second data lines 10) and a plurality of scan lines 20.
  • the driving circuit layer 7 also includes power signal lines (eg, VDD signal lines) arranged in parallel with the data lines and other signal lines (eg, EM signal lines) arranged in parallel with the scan lines 20 .
  • the scan lines 20 extend along a second direction perpendicular to the first direction (such as the horizontal direction, ie, the row direction below); the multiple scan lines 20 are connected with the multiple first data lines 9 and multiple The second data lines 10 are insulated and crossed to form a plurality of pixel areas 21 arranged in multiple rows and columns. Each pixel area 21 corresponds to one pixel driving circuit unit 19 .
  • the pixel driving circuit unit 19 includes at least one thin film transistor.
  • the pixel driving circuit unit 19 includes a 7T1C pixel driving circuit, but is of course not limited thereto.
  • the driving thin film transistor in the pixel driving circuit unit 19 includes an active layer 22 (for example, polysilicon), a first gate insulating layer 23, a first gate layer 24, and a Two gate insulating layers 25, interlayer insulating layers 27 and source and drain electrode layers; wherein, the source and drain electrodes in the source and drain electrode layers pass through the first gate insulating layer 23, the second gate insulating layer 25 and the layer
  • the through holes of the inter-insulating layer 27 are electrically connected to both ends of the active layer 22 , and the first gate electrode, the second gate electrode and the active layer 22 are arranged correspondingly.
  • the source-drain electrode layer may have a double-layer electrode structure.
  • the source-drain electrode layer includes a first source-drain electrode layer 28 and a second source-drain electrode layer 29 located on the interlayer insulating layer 27 in sequence.
  • the side of the pixel driving circuit unit 19 away from the substrate 6 is also provided with a first flat layer 30 between the first source and drain electrode layer 28 and the second source and drain electrode layer 29 and a first flat layer 30 between the second source and drain electrode layer 29 and away from the second source and drain electrode layer 29 .
  • a second flat layer 31 on one side of the source and drain electrode layer 28 is also provided with a first flat layer 30 between the first source and drain electrode layer 28 and the second source and drain electrode layer 29 and a first flat layer 30 between the second source and drain electrode layer 29 and away from the second source and drain electrode layer 29 .
  • the scan line 20 is arranged in the same layer as the gate layer (the first gate layer 24 or the second gate layer 26), and the first data line 9 and the second data line 10 are arranged in the same layer as the source-drain electrode layer (the first source-drain electrode layer).
  • the drain electrode layer 28 or the second source and drain electrode layer 29) are arranged in the same layer. It should be noted that this application does not limit the number and type of thin film transistors in the pixel driving circuit unit 19, and the structure of the driving thin film transistors described above is only an exemplary description.
  • the light-emitting device layer 5 includes a plurality of organic light-emitting devices (such as OLED devices) electrically connected to a plurality of pixel driving circuit units 19 in one-to-one correspondence.
  • organic light-emitting devices such as OLED devices
  • multiple organic light-emitting devices are arranged in one-to-one correspondence with multiple pixel areas 21 .
  • the first data line 9 does not intersect with the hole-digging area 2, that is, the first data line 9 will not be affected by the hole-digging area 2, and extends normally and continuously in the first direction; the second data line 10 and the hole-digging area 2 do not intersect.
  • the hole areas 2 are arranged correspondingly and are divided into two parts in the first direction by the hole area 2 , namely the first sub-data line 11 and the second sub-data line 12 . It can be understood that the data signals on the first sub-data line 11 and the second sub-data line 12 are the same.
  • each first data line 9 is electrically connected to a column of pixel driving circuit units 19 (or pixel areas 21 ), and each second data line 10 is connected to a column of pixel driving circuits.
  • the units 19 (or pixel areas 21 ) are electrically connected correspondingly; the first data line 9 and the second data line 10 respectively provide data signals to the corresponding pixel driving circuit unit 19 .
  • the scan line 20 includes a plurality of first scan lines 32 and a plurality of second scan lines 33 ; wherein the second scan line 33 is divided into two parts by the drilling area 2 , for example, in the second
  • the first sub-scan line and the second sub-scan line are located on both sides of the hole-digging area 2 in the direction.
  • the display panel 1 includes GOA circuits located on both sides of the display area 3 in the second direction, providing scanning signals to the scan lines 20 from both sides respectively; specifically, the first sub-scan line and the second sub-scan line
  • the scan lines are respectively connected to two GOA circuits, and the two GOA circuits provide scan signals to the first sub-scan line and the second sub-scan line from both sides respectively, so as to avoid setting up the display area 3 for connecting the first sub-scan line and the second sub-scan line.
  • the scan line connection line of the two sub-scan lines is provided to the two sub-scan lines.
  • the display panel 1 also includes a scan line connection line located in the display area 3 and located in the fan-out wiring layer 8 for connecting the first sub-scan line and the second sub-scan line, even if there is only one GOA circuit, Scanning signals can also be normally provided to the first sub-scanning line and the second sub-scanning line.
  • the embodiment of the present application does not provide a detailed description of the scan line connection lines, and its specific settings may refer to the settings of the data line connection lines 14 .
  • the display panel 1 also includes a binding area 36 located at least on one side of the display area 3 for arranging a driving integrated circuit (IC).
  • IC driving integrated circuit
  • One end of the fan-out wiring 13 in the fan-out wiring layer 8 extends to the binding area 36 and is electrically connected to the driving integrated circuit, and the other end is electrically connected to the corresponding data line or scanning line in the display area 3 .
  • the electrical connection between the fan-out trace and the data line is used as an example for description, but it is not limited to this.
  • the hole-digging area 2 is provided on the upper half of the display panel 1, and the binding area 36 is provided on the lower frame of the display panel 1, so the wiring area of the data line connection line 14 and the fan-out trace 13 can be No overlap, which is beneficial to reducing wiring density and increasing line spacing, improving signal stability.
  • the data line connection lines 14 and at least part of the fan-out lines 13 are arranged on the same layer.
  • the fan-out wiring layer 8 includes at least one wiring layer; when multiple fan-out wiring 13 are located in the same wiring layer, the data line connecting lines 14 and the fan-out wiring 13 are arranged on the same layer; when multiple fan-out wiring 13 are located in the same wiring layer, When the wires 13 are distributed in multiple wiring layers, the data line connecting wires 14 can be arranged on the same layer as only one of the wiring layers, or they can be distributed in the multi-layer wiring layers like the fan-out wiring 13 .
  • the fan-out wiring layer 8 includes a first wiring layer 37 and a second wiring layer 38 located on the driving circuit layer 7 in sequence; the fan-out wiring 13 is located at least on the first wiring layer 7 .
  • One of the wiring layer 37 and the second wiring layer 38; and the data line connection line 14 is located at least on one of the first wiring layer 37 and the second wiring layer 38.
  • part of the fan-out traces 13 is located on the first wiring layer 37, and another part of the fan-out traces 13 is located on the second wiring layer 38 to avoid multiple fan-out traces 13 being distributed on the same layer and causing too dense wiring; or, each fan-out trace 13 is located on the second wiring layer 38.
  • the outgoing trace 13 includes two electrically connected trace parts, one of which is located on the first trace layer 37 and the other trace part is located on the second trace layer 38 , which can also avoid too dense wiring.
  • the data line connection line 14 is located on the first wiring layer 37 .
  • the data line connection line 14 is located on the second wiring layer 38 .
  • part of the data line connection lines 14 among the plurality of data line connection lines 14 is located on the first wiring layer 37
  • another part of the data line connection lines 14 is located on the second wiring layer 38 .
  • part of the connection lines in each data line connection line 14 is located on the first wiring layer 37, and another part of the connection lines is located on the second wiring layer 38, and the two parts of the connection lines are connected through via holes.
  • a third flat layer 39 is also provided between the first wiring layer 37 and the second wiring layer 38 , and the second wiring layer 38 is on the side away from the first wiring layer 37
  • a fourth flat layer 40 is provided;
  • the light-emitting device layer 5 includes an anode layer 41, a pixel definition layer 42, a support layer 43, a light-emitting layer 44 and a cathode layer 45 located on the fourth flat layer 40 in sequence; the anode layer 41, the light-emitting layer 44 and the cathode layer 45 constitute an organic light-emitting device.
  • the anode layer 41 and the source-drain electrode layer are located on the first wiring layer through the first connection electrode 46 located on the second source-drain electrode layer 29 and penetrating the first planar layer 30 . 37 and penetrates the second connection electrode 47 of the second planar layer 31, the third connection electrode 48 located on the second wiring layer 38 and penetrating the third planar layer 39, and the fourth planar layer 40 and penetrating the fourth planar layer.
  • the fourth connection electrode 49 of 40 realizes electrical connection.
  • the material of the first connection electrode 46 , the second connection electrode 47 and the third connection electrode 48 includes indium tin oxide (ITO), but is not limited thereto; the material of the fourth connection electrode 49 includes indium zinc oxide (IZO), but is not limited thereto. Not limited to this.
  • the data line connection line 14 includes a first data line connection part 50 extending along the first direction, and second and third data line connection parts 51 and 52 extending along the second direction. ; One end of the second data line connecting portion 51 is electrically connected to the corresponding first sub-data line 11, and the other end is electrically connected to one end of the first data line connecting portion 50; the other end of the first data line connecting portion 50 is electrically connected to the third data line connecting portion 50; One end of the data line connection part 52 is electrically connected; the other end of the third data line connection part 52 is electrically connected to the corresponding second sub-data line 12; the first data line connection part 50 corresponds to the plurality of pixel areas 21 in the column direction.
  • the second data line connection part 51 and the third data line connection part 52 are provided corresponding to the plurality of pixel areas 21 in two different row directions.
  • first data line connection part 50, the second data line connection part 51 and the third data line connection part 52 can be located on the same wiring layer, for example, on the first wiring layer 37 or the second wiring layer 38; Of course, they can also be located on different wiring layers.
  • first data line connecting portion 50 is located on the second wiring layer 38
  • second data line connecting portion 51 and the third data line connecting portion 52 are located on the first wiring layer 37 .
  • each pixel area 21 includes at least one line exchange hole 53 extending in a direction perpendicular to the display panel 1 and used to connect different metal layers;
  • the first data line connection part 50 includes The bending portion 54 is provided corresponding to the line-changing hole 53 in the corresponding pixel area 21; the bending portion 54 is bent in a direction away from the corresponding line-changing hole 53 to avoid the line-changing hole 53.
  • the wiring hole 53 is filled with conductive material (such as ITO) for connecting the wiring or electrodes of the upper and lower layers.
  • the first data line connecting portion 50 extends in a bent shape in the first direction; specifically, the shape of the bent portion 54 includes any one of a rectangle, a triangle, and an arc.
  • This application only takes the rectangular bent portion 54 as an example for description, and the specific shape is not limited to the ones listed above.
  • the orthographic projection of at least one first data line 9 on the substrate 6 is located between the orthographic projections of two adjacent first data line connecting portions 50 on the substrate 6 .
  • multiple first data line connecting portions 50 can be provided corresponding to multiple adjacent columns of pixel areas 21 , or one first data line connecting portion 50 can be provided corresponding to at least two columns of pixel areas 21 .
  • At least part of the first data line connecting portion 50 overlaps with the middle position of the corresponding plurality of pixel areas 21 to achieve the best light shielding effect
  • the display area 3 is arranged around the hole-digging area 2 and the hole-digging area 2 is symmetrical about the symmetry axis L extending along the first direction; the plurality of data line connecting lines 14 are about the symmetry axis L Symmetrical setup. Specifically, the plurality of second data lines 10 are also arranged symmetrically about the axis of symmetry L.
  • the materials of the fan-out traces 13 and the data line connection lines 14 include ITO, but are not limited thereto.
  • the fan-out wiring 13 and the data line connection line 14 are both provided in the display area 3, specifically in the fan-out wiring layer 8 located on the drive circuit layer 7, so that the fan-out wiring 13 and the data line connection line 14 is arranged in a different layer than the first data line 9 and the second data line 10 in the driving circuit layer 7; on the one hand, it is possible to avoid arranging the fan-out trace 13 in the non-display area to reduce the width of the frame around the display area 3; On the other hand, it is possible to avoid arranging the data line connection lines 14 at the edge of the hole-digging area 2 , which is beneficial to reducing the frame width of the hole-digging area 2 ; on the other hand, it is possible to avoid placing the fan-out traces 13 and the data line connection lines 14 It is arranged in the driving circuit layer 7 to avoid unstable signal transmission caused by too dense wiring of the driving circuit layer 7; therefore, this application realizes the extremely narrow frame of the display panel 1 while ensuring a stable display effect.
  • the embodiment of the present application also provides a display device 55 .
  • the display device 55 includes the aforementioned display panel 1 and a driver integrated circuit 56 ; the display panel 1 also includes a binding area located on one side of the display area 3 36;
  • the driving integrated circuit 56 is bonded and connected to the binding area 36; the fan-out trace 13 extends from the display area 3 to the binding area 36 and is electrically connected to the driving integrated circuit 56.
  • the driver integrated circuit 56 provides signals to the data lines and scan lines 20 in the display area 3 through the fan-out traces 13 .
  • the fan-out wiring 13 and the data line connection line 14 are both provided in the display area 3, specifically in the fan-out wiring layer 8 located on the drive circuit layer 7, so that the fan-out wiring 13 and the data line connection line 14 is arranged in a different layer than the first data line 9 and the second data line 10 in the driving circuit layer 7; on the one hand, it is possible to avoid arranging the fan-out trace 13 in the non-display area to reduce the width of the frame around the display area 3; On the other hand, it is possible to avoid arranging the data line connection lines 14 at the edge of the hole-digging area 2 , which is beneficial to reducing the frame width of the hole-digging area 2 ; on the other hand, it is possible to avoid placing the fan-out traces 13 and the data line connection lines 14 It is arranged in the driving circuit layer 7 to avoid unstable signal transmission caused by too dense wiring in the driving circuit layer 7; therefore, this application realizes the extremely narrow frame of the display device 55 while ensuring a stable display effect.

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Abstract

一种显示面板(1)和显示装置(55)，具有相邻的挖孔区(2)和显示区(3)，且包括依次位于显示区(3)的驱动阵列基板(4)和发光器件层(5)；驱动阵列基板(4)包括衬底(6)、驱动电路层(7)和扇出走线层(8)；驱动电路层(7)包括第一数据线(9)和被挖孔区(2)分隔成第一子数据线(11)和第二子数据线(12)的第二数据线(10)；扇出走线层(8)包括扇出走线(13)和与第一子数据线(11)和第二子数据线(12)电连接的数据线连接线(14)。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板和显示装置。
 背景技术
AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极体)显示面板因其高对比度、广色域、低功耗等显示方面的优点，已逐渐取代LCD( Liquid Crystal Display，液晶显示器)成为新一代显示技术。与传统的LCD面板相比，OLED显示面板易于柔性化，是可穿戴、可折叠产品的关键技术。
随着OLED面板技术的发展，OLED显示不仅仅局限于可穿戴、可折叠产品的开发。为了达到更好的显示效果，为用户带来更好的视觉享受，窄边框技术逐渐成为吸引用户群体的一大亮点。但因受面板分辨率、蒸镀精度和封装等因素的限制，面板的边框仍然较大。
 技术问题
本申请提供一种显示面板和显示装置，在将扇出走线设置在显示区的基础上，将数据线连接线也设置在显示区，有利于减小显示区外围的边框以及减小挖孔区的边框，实现极致窄边框化。
 技术解决方案
第一方面，本申请提供一种显示面板，具有相邻设置的挖孔区和显示区；所述显示面板包括位于所述显示区的驱动阵列基板和位于所述驱动阵列基板上的发光器件层；所述驱动阵列基板包括衬底以及依次位于所述衬底上的驱动电路层和扇出走线层；
所述驱动电路层包括沿第一方向延伸的多条第一数据线和多条第二数据线；所述第二数据线在所述第一方向上被所述挖孔区分隔成第一子数据线和第二子数据线；所述扇出走线层包括与所述多条第一数据线和所述多条第二数据线一一对应电连接的多条扇出走线以及与所述多条第二数据线对应电连接的多条数据线连接线；所述数据线连接线的两端分别与对应的所述第一子数据线和所述第二子数据线电连接。
在本申请所提供的显示面板中，所述数据线连接线与至少部分所述扇出走线同层设置。
在本申请所提供的显示面板中，所述扇出走线层包括依次位于所述驱动电路层上的第一走线层和第二走线层；
所述扇出走线至少位于所述第一走线层和所述第二走线层中的其中一层；
且所述数据线连接线至少位于所述第一走线层和所述第二走线层中的其中一层。
在本申请所提供的显示面板中，所述驱动电路层还包括沿与所述第一方向垂直的第二方向延伸的多条扫描线；所述多条扫描线与所述多条第一数据线和所述多条第二数据线绝缘交叉形成呈多行多列设置的多个像素区；
所述数据线连接线包括沿所述第一方向延伸的第一数据线连接部、沿所述第二方向延伸的第二数据线连接部和第三数据线连接部；所述第二数据线连接部的一端与对应的所述第一子数据线电连接，另一端与所述第一数据线连接部的一端电连接；所述第一数据线连接部的另一端与所述第三数据线连接部的一端电连接；所述第三数据线连接部的另一端与对应的所述第二子数据线电连接；
所述第一数据线连接部与所述列方向上的多个所述像素区对应设置，所述第二数据线连接部和所述第三数据线连接部与两个不同的所述行方向上的多个所述像素区对应设置。
在本申请所提供的显示面板中，每个所述像素区包括至少一个沿垂直于所述显示面板方向延伸且用于连通不同层金属层的换线孔；所述第一数据线连接部包括与对应的所述像素区中的所述换线孔对应设置的弯折部；所述弯折部朝远离对应的所述换线孔的方向弯折。
在本申请所提供的显示面板中，所述弯折部的形状包括矩形、三角形和弧形中的任意一种。
在本申请所提供的显示面板中，至少一条所述第一数据线在所述衬底上的正投影位于相邻的两个所述第一数据线连接部在所述衬底上的正投影之间。
在本申请所提供的显示面板中，至少部分所述第一数据线连接部与对应的所述多个像素区的中间位置重叠设置。
在本申请所提供的显示面板中，所述显示区围绕所述挖孔区设置，且所述挖孔区关于沿所述第一方向延伸的对称轴对称；所述多条数据线连接线关于所述对称轴对称设置。
在本申请所提供的显示面板中，所述扇出走线和所述数据线连接线的材料包括氧化铟锡。
第二方面，本申请还提供一种显示装置，包括以上所述的显示面板和驱动集成电路；所述显示面板还包括位于所述显示区一侧的绑定区；所述驱动集成电路与所述绑定区绑定连接；所述扇出走线从所述显示区延伸至所述绑定区且与所述驱动集成电路电连接。
在本申请所提供的显示装置中，所述数据线连接线与至少部分所述扇出走线同层设置。
在本申请所提供的显示装置中，所述扇出走线层包括依次位于所述驱动电路层上的第一走线层和第二走线层；
所述扇出走线至少位于所述第一走线层和所述第二走线层中的其中一层；
且所述数据线连接线至少位于所述第一走线层和所述第二走线层中的其中一层。
在本申请所提供的显示装置中，所述驱动电路层还包括沿与所述第一方向垂直的第二方向延伸的多条扫描线；所述多条扫描线与所述多条第一数据线和所述多条第二数据线绝缘交叉形成呈多行多列设置的多个像素区；
所述数据线连接线包括沿所述第一方向延伸的第一数据线连接部、沿所述第二方向延伸的第二数据线连接部和第三数据线连接部；所述第二数据线连接部的一端与对应的所述第一子数据线电连接，另一端与所述第一数据线连接部的一端电连接；所述第一数据线连接部的另一端与所述第三数据线连接部的一端电连接；所述第三数据线连接部的另一端与对应的所述第二子数据线电连接；
所述第一数据线连接部与所述列方向上的多个所述像素区对应设置，所述第二数据线连接部和所述第三数据线连接部与两个不同的所述行方向上的多个所述像素区对应设置。
在本申请所提供的显示装置中，每个所述像素区包括至少一个沿垂直于所述显示面板方向延伸且用于连通不同层金属层的换线孔；所述第一数据线连接部包括与对应的所述像素区中的所述换线孔对应设置的弯折部；所述弯折部朝远离对应的所述换线孔的方向弯折。
在本申请所提供的显示装置中，所述弯折部的形状包括矩形、三角形和弧形中的任意一种。
在本申请所提供的显示装置中，至少一条所述第一数据线在所述衬底上的正投影位于相邻的两个所述第一数据线连接部在所述衬底上的正投影之间。
在本申请所提供的显示装置中，至少部分所述第一数据线连接部与对应的所述多个像素区的中间位置重叠设置。
在本申请所提供的显示装置中，所述显示区围绕所述挖孔区设置，且所述挖孔区关于沿所述第一方向延伸的对称轴对称；所述多条数据线连接线关于所述对称轴对称设置。
在本申请所提供的显示装置中，所述扇出走线和所述数据线连接线的材料包括氧化铟锡。
 有益效果
相较于现有技术，本申请提供的显示面板和显示装置，将扇出走线和数据线连接线均设置在显示区，具体设置在位于驱动电路层上的扇出走线层，使得扇出走线和数据线连接线与驱动电路层中的第一数据线和第二数据线不同层设置；一方面，可以避免将扇出走线设置在非显示区，以减小显示区外围的边框宽度；另一方面，可以避免将数据线连接线设置在挖孔区的边缘，有利于减小挖孔区的边框宽度；另一方面，可以避免将扇出走线和数据线连接线设置在驱动电路层中，从而避免布线太密导致的信号传递不稳定；因此，本申请在保证显示效果稳定的基础上实现了显示面板极致窄边框化。
 附图说明
图1为本申请实施例提供的一种显示面板的俯视图。
图2为本申请实施例提供的一种显示面板的像素区的部分截面结构示意图。
图3为图1中A部位的局部放大图。
图4为图1中B部位的局部放大图。
图5为本申请实施例提供的一种显示面板的显示区的部分结构的俯视图。
图6为本申请实施例提供的另一种显示面板的显示区的部分结构的俯视图。
图7为本申请实施例提供的一种数据线连接线的俯视图。
图8为本申请实施例提供的一种显示装置的俯视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
结合图1至图4所示，本申请实施例提供了一种显示面板1；显示面板1具有挖孔区2和与挖孔区2相邻设置的显示区3；如图2所示，显示面板1包括位于显示区3的驱动阵列基板4和位于驱动阵列基板4上的发光器件层5；驱动阵列基板4包括衬底6以及依次位于衬底6上的驱动电路层7和扇出走线层8；驱动电路层7包括沿第一方向（例如竖直方向，即下文中的列方向）延伸的多条第一数据线9和多条第二数据线10；第二数据线10在第一方向上被挖孔区2分隔成第一子数据线11和第二子数据线12；如图3和图4所示，扇出走线层8包括与多条第一数据线9和多条第二数据线10一一对应电连接的多条扇出走线13以及与多条第二数据线10对应电连接的多条数据线连接线14；数据线连接线14的两端分别与对应的第一子数据线11和第二子数据线12电连接。
可以理解的，本申请实施例将用于连接第一子数据线11和第二子数据线12的数据线连接线14绕到显示区3，避免将数据线连接线14设置在挖孔区2的边缘，可以有效的减小挖孔区2的边框宽度；并且，本申请实施例将用于向第一数据线9和第二数据线10传递数据信号的扇出走线13设置在显示区3，避免将扇出走线13设置在非显示区，可以有效的减小显示区3的外围边框（非显示区）宽度，即减小显示面板1的外围边框宽度。
具体的，显示面板1包括位于挖孔区2且在垂直于显示面板1的方向上至少贯穿显示面板1的驱动阵列基板4和发光器件层5的通孔，用于设置屏下摄像头或其他光学器件。显示区3可以围绕整个挖孔区2设置，也可以沿挖孔区2的部分边缘设置，此处不做限制。为了方便描述，本申请实施例以显示区3围绕挖孔区2设置为例进行说明。
具体的，驱动阵列基板4的衬底6可以为柔性衬底。在一具体实施方式中，如图2所示，衬底6包括第一柔性层15以及依次设置在第一柔性层15上的第一缓冲层16和第二柔性层17；其中，第一柔性层15和第二柔性层17的材料为有机材料，例如聚酰亚胺（PI），第一缓冲层16的材料为无机材料，例如氧化硅和氮化硅中的至少一种。
在一具体实施方式中，如图2所示，驱动电路层7靠近衬底6的一侧还设有第二缓冲层18；当然，在其他实施方式中，驱动电路层7靠近衬底6的一侧还可以设置阻挡层，第二缓冲层18和阻挡层的先后位置不做限制。
具体的，驱动阵列基板4的驱动电路层7包括呈阵列分布的多个像素驱动电路单元19、与多个像素驱动电路单元19电连接的多条数据线（例如多条第一数据线9和多条第二数据线10）和多条扫描线20。当然，驱动电路层7还包括与数据线平行设置的电源信号线（例如VDD信号线）以及与扫描线20平行设置的其他信号线（例如EM信号线）。
具体的，扫描线20沿与第一方向垂直的第二方向（例如水平方向，即下文的行方向）延伸的多条扫描线20；多条扫描线20与多条第一数据线9和多条第二数据线10绝缘交叉形成呈多行多列设置的多个像素区21。每个像素区21对应一个像素驱动电路单元19。
具体的，像素驱动电路单元19包括至少一个薄膜晶体管。在一具体实施方式中，像素驱动电路单元19包括7T1C像素驱动电路，当然不限于此。
在一具体实施方式中，像素驱动电路单元19中的驱动薄膜晶体管包括依次位于衬底6上的有源层22（例如多晶硅）、第一栅极绝缘层23、第一栅极层24、第二栅极绝缘层25、层间绝缘层27以及源漏电极层；其中，源漏电极层中的源极和漏极通过贯穿第一栅极绝缘层23、第二栅极绝缘层25和层间绝缘层27的通孔与有源层22的两端电连接，第一栅极、第二栅极和有源层22对应设置。具体的，源漏电极层可以为双层电极结构，例如源漏电极层包括依次位于层间绝缘层27上的第一源漏电极层28和第二源漏电极层29。像素驱动电路单元19远离衬底6的一侧还设有位于第一源漏电极层28和第二源漏电极层29之间的第一平坦层30以及位于第二源漏电极层29远离第一源漏电极层28的一侧的第二平坦层31。
可以理解的，扫描线20与栅极层（第一栅极层24或第二栅极层26）同层设置，第一数据线9和第二数据线10与源漏电极层（第一源漏电极层28或第二源漏电极层29）同层设置。需要说明的是，本申请对像素驱动电路单元19中的薄膜晶体管的数量和类型不做限制，以上所述的驱动薄膜晶体管的结构仅为示例性的描述。
具体的，发光器件层5包括与多个像素驱动电路单元19一一对应电连接的多个有机发光器件（例如OLED器件）。在一具体实施方式中，多个有机发光器件与多个像素区21一一对应设置。
具体的，第一数据线9与挖孔区2不交叉设置，即第一数据线9不会受挖孔区2的影响，且在第一方向上正常连续延伸；第二数据线10与挖孔区2对应设置，在第一方向上被挖孔区2分隔成两部分，即第一子数据线11和第二子数据线12。可以理解的，第一子数据线11和第二子数据线12上的数据信号相同。
在一具体实施方式中，如图3所示，每条第一数据线9与一列像素驱动电路单元19（或像素区21）对应电连接，且每一条第二数据线10与一列像素驱动电路单元19（或像素区21）对应电连接；第一数据线9和第二数据线10分别向对应的像素驱动电路单元19提供数据信号。
具体的，如图3所示，扫描线20包括多条第一扫描线32和多条第二扫描线33；其中，第二扫描线33被挖孔区2分隔成两部分，例如在第二方向上位于挖孔区2两侧的第一子扫描线和第二子扫描线。在一具体实施方式中，显示面板1包括在第二方向上位于显示区3两侧的GOA电路，分别从两侧向扫描线20提供扫描信号；具体的，第一子扫描线和第二子扫描线分别与两个GOA电路连接，两个GOA电路分别从两侧向第一子扫描线和第二子扫描线提供扫描信号，避免在显示区3设置用于连接第一子扫描线和第二子扫描线的扫描线连接线。在另一实施方式中，显示面板1还包括位于显示区3且位于扇出走线层8的扫描线连接线，用于连接第一子扫描线和第二子扫描线，即使只有一个GOA电路，也能向第一子扫描线和第二子扫描线正常提供扫描信号。本申请实施例不对扫描线连接线做具体的描述，其具体设置可参考数据线连接线14的设置。
具体的，如图1所示，显示面板1还包括至少位于显示区3一侧的绑定区36，用于设置驱动集成电路（IC）。扇出走线层8中的扇出走线13的一端延伸至绑定区36与驱动集成电路电连接，另一端在显示区3与对应的数据线或扫描线电连接。本申请实施例中，以扇出走线与数据线电连接为例进行说明，但不限于此。
可以理解的，通常，挖孔区2设置在显示面板1的上半部分，而绑定区36设置在显示面板1的下边框处，故数据线连接线14和扇出走线13的布线区域可以不重叠，有利于减小布线密度以及增大线距，提高信号的稳定性。
具体的，数据线连接线14与至少部分扇出走线13同层设置。
具体的，扇出走线层8包括至少一层走线层；当多条扇出走线13位于同一走线层中时，数据线连接线14与扇出走线13同层设置；当多条扇出走线13分布在多层走线层中时，数据线连接线14可以仅与其中一层走线层同层设置，也可以同扇出走线13一样分布在多层走线层中。
在一具体实施方式中，如图2所示，扇出走线层8包括依次位于驱动电路层7上的第一走线层37和第二走线层38；扇出走线13至少位于第一走线层37和第二走线层38中的其中一层；且数据线连接线14至少位于第一走线层37和第二走线层38中的其中一层。例如，部分扇出走线13位于第一走线层37，另一部分扇出走线13位于第二走线层38，避免多个扇出走线13分布在同一层造成布线太密集；或者，每条扇出走线13包括两个电连接的走线部，其中一个走线部位于第一走线层37，另一个走线部位于第二走线层38，同样可以避免布线太密集。
在一具体实施方式中，数据线连接线14位于第一走线层37。
在另一具体实施方式中，数据线连接线14位于第二走线层38。
在另一具体实施方式中，多条数据线连接线14中的部分数据线连接线14位于第一走线层37，且另一部分数据线连接线14位于第二走线层38。
在另一具体实施方式中，每条数据线连接线14中的部分连接线位于第一走线层37，且另一部分连接线位于第二走线层38，两部分连接线通过过孔连接。
具体的，如图2所示，第一走线层37和第二走线层38之间还设有第三平坦层39，且第二走线层38远离第一走线层37的一侧设有第四平坦层40；发光器件层5包括依次位于第四平坦层40上的阳极层41、像素定义层42、支撑层43、发光层44和阴极层45；阳极层41、发光层44和阴极层45构成了有机发光器件。
在一具体实施方式中，如图2所示，阳极层41与源漏电极层通过位于第二源漏电极层29且贯穿第一平坦层30的第一连接电极46、位于第一走线层37且贯穿第二平坦层31的第二连接电极47、位于第二走线层38且贯穿第三平坦层39的第三连接电极48、以及位于第四平坦层40上且贯穿第四平坦层40的第四连接电极49实现电连接。其中，第一连接电极46、第二连接电极47和第三连接电极48的材料包括氧化铟锡（ITO），但不限于此；第四连接电极49的材料包括氧化铟锌（IZO），但不限于此。
具体的，如图3所示，数据线连接线14包括沿第一方向延伸的第一数据线连接部50以及沿第二方向延伸的第二数据线连接部51和第三数据线连接部52；第二数据线连接部51的一端与对应的第一子数据线11电连接，另一端与第一数据线连接部50的一端电连接；第一数据线连接部50的另一端与第三数据线连接部52的一端电连接；第三数据线连接部52的另一端与对应的第二子数据线12电连接；第一数据线连接部50与列方向上的多个像素区21对应设置，第二数据线连接部51和第三数据线连接部52与两个不同的行方向上的多个像素区21对应设置。
可以理解的，第一数据线连接部50、第二数据线连接部51和第三数据线连接部52可以位于同一走线层，例如位于第一走线层37或第二走线层38；当然，它们还可以位于不同的走线层，例如第一数据线连接部50位于第二走线层38，第二数据线连接部51和第三数据线连接部52位于第一走线层37。
具体的，如图5和图6所示，每个像素区21包括至少一个沿垂直于显示面板1方向延伸且用于连通不同层金属层的换线孔53；第一数据线连接部50包括与对应的像素区21中的换线孔53对应设置的弯折部54；弯折部54朝远离对应的换线孔53的方向弯折，以避开换线孔53。可以理解的，换线孔53内填充有导电材料（例如ITO），用于连通上下层的走线或电极。
可以理解的，如图7所示，第一数据线连接部50在第一方向上呈弯折状延伸；具体的，弯折部54的形状包括矩形、三角形和弧形中的任意一种，本申请仅以矩形弯折部54为例进行说明，具体形状不限于以上列举的几种。
具体的，如图5和图6所示，至少一条第一数据线9在衬底6上的正投影位于相邻的两个第一数据线连接部50在衬底6上的正投影之间。可以理解的，多个第一数据线连接部50可以与依次相邻的多列像素区21对应设置，也可以至少两列像素区21对应设置一个第一数据线连接部50。
在一具体实施例中，至少部分第一数据线连接部50与对应的多个像素区21的中间位置重叠设置，以达到最佳遮光效果；
在一具体实施方式中，如图3所示，显示区3围绕挖孔区2设置且挖孔区2关于沿第一方向延伸的对称轴L对称；多条数据线连接线14关于对称轴L对称设置。具体的，多条第二数据线10也关于对称轴L对称设置。
具体的，扇出走线13和数据线连接线14的材料包括ITO，但不限于此。
本申请实施例中，将扇出走线13和数据线连接线14均设置在显示区3，具体设置在位于驱动电路层7上的扇出走线层8，使得扇出走线13和数据线连接线14与驱动电路层7中的第一数据线9和第二数据线10不同层设置；一方面，可以避免将扇出走线13设置在非显示区，以减小显示区3外围的边框宽度；另一方面，可以避免将数据线连接线14设置在挖孔区2的边缘，有利于减小挖孔区2的边框宽度；另一方面，可以避免将扇出走线13和数据线连接线14设置在驱动电路层7中，从而避免驱动电路层7布线太密导致的信号传递不稳定；因此，本申请在保证显示效果稳定的基础上实现了显示面板1极致窄边框化。
结合图1至8所示，本申请实施例还提供了一种显示装置55，显示装置55包括前述显示面板1和驱动集成电路56；显示面板1还包括位于显示区3一侧的绑定区36；驱动集成电路56与绑定区36绑定连接；扇出走线13从显示区3延伸至绑定区36且与驱动集成电路56电连接。驱动集成电路56通过扇出走线13向显示区3中的数据线和扫描线20提供信号。
本申请实施例中，将扇出走线13和数据线连接线14均设置在显示区3，具体设置在位于驱动电路层7上的扇出走线层8，使得扇出走线13和数据线连接线14与驱动电路层7中的第一数据线9和第二数据线10不同层设置；一方面，可以避免将扇出走线13设置在非显示区，以减小显示区3外围的边框宽度；另一方面，可以避免将数据线连接线14设置在挖孔区2的边缘，有利于减小挖孔区2的边框宽度；另一方面，可以避免将扇出走线13和数据线连接线14设置在驱动电路层7中，从而避免驱动电路层7布线太密导致的信号传递不稳定；因此，本申请在保证显示效果稳定的基础上实现了显示装置55极致窄边框化。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，具有相邻设置的挖孔区和显示区；所述显示面板包括位于所述显示区的驱动阵列基板和位于所述驱动阵列基板上的发光器件层；所述驱动阵列基板包括衬底以及依次位于所述衬底上的驱动电路层和扇出走线层；
    所述驱动电路层包括沿第一方向延伸的多条第一数据线和多条第二数据线；所述第二数据线在所述第一方向上被所述挖孔区分隔成第一子数据线和第二子数据线；所述扇出走线层包括与所述多条第一数据线和所述多条第二数据线一一对应电连接的多条扇出走线以及与所述多条第二数据线对应电连接的多条数据线连接线；所述数据线连接线的两端分别与对应的所述第一子数据线和所述第二子数据线电连接。
  2. 根据权利要求1所述的显示面板，其中，所述数据线连接线与至少部分所述扇出走线同层设置。
  3. 根据权利要求2所述的显示面板，其中，所述扇出走线层包括依次位于所述驱动电路层上的第一走线层和第二走线层；
    所述扇出走线至少位于所述第一走线层和所述第二走线层中的其中一层；
    且所述数据线连接线至少位于所述第一走线层和所述第二走线层中的其中一层。
  4. 根据权利要求1所述的显示面板，其中，所述驱动电路层还包括沿与所述第一方向垂直的第二方向延伸的多条扫描线；所述多条扫描线与所述多条第一数据线和所述多条第二数据线绝缘交叉形成呈多行多列设置的多个像素区；
    所述数据线连接线包括沿所述第一方向延伸的第一数据线连接部、沿所述第二方向延伸的第二数据线连接部和第三数据线连接部；所述第二数据线连接部的一端与对应的所述第一子数据线电连接，另一端与所述第一数据线连接部的一端电连接；所述第一数据线连接部的另一端与所述第三数据线连接部的一端电连接；所述第三数据线连接部的另一端与对应的所述第二子数据线电连接；
    所述第一数据线连接部与所述列方向上的多个所述像素区对应设置，所述第二数据线连接部和所述第三数据线连接部与两个不同的所述行方向上的多个所述像素区对应设置。
  5. 根据权利要求4所述的显示面板，其中，每个所述像素区包括至少一个沿垂直于所述显示面板方向延伸且用于连通不同层金属层的换线孔；所述第一数据线连接部包括与对应的所述像素区中的所述换线孔对应设置的弯折部；所述弯折部朝远离对应的所述换线孔的方向弯折。
  6. 根据权利要求5所述的显示面板，其中，所述弯折部的形状包括矩形、三角形和弧形中的任意一种。
  7. 根据权利要求4所述的显示面板，其中，至少一条所述第一数据线在所述衬底上的正投影位于相邻的两个所述第一数据线连接部在所述衬底上的正投影之间。
  8. 根据权利要求4所述的显示面板，其中，至少部分所述第一数据线连接部与对应的所述多个像素区的中间位置重叠设置。
  9. 根据权利要求1所述的显示面板，其中，所述显示区围绕所述挖孔区设置，且所述挖孔区关于沿所述第一方向延伸的对称轴对称；所述多条数据线连接线关于所述对称轴对称设置。
  10. 根据权利要求1所述的显示面板，其中，所述扇出走线和所述数据线连接线的材料包括氧化铟锡。
  11. 一种显示装置，包括如权利要求1所述的显示面板和驱动集成电路；所述显示面板还包括位于所述显示区一侧的绑定区；所述驱动集成电路与所述绑定区绑定连接；所述扇出走线从所述显示区延伸至所述绑定区且与所述驱动集成电路电连接。
  12. 根据权利要求11所述的显示装置，其中，所述数据线连接线与至少部分所述扇出走线同层设置。
  13. 根据权利要求12所述的显示装置，其中，所述扇出走线层包括依次位于所述驱动电路层上的第一走线层和第二走线层；
    所述扇出走线至少位于所述第一走线层和所述第二走线层中的其中一层；
    且所述数据线连接线至少位于所述第一走线层和所述第二走线层中的其中一层。
  14. 根据权利要求11所述的显示装置，其中，所述驱动电路层还包括沿与所述第一方向垂直的第二方向延伸的多条扫描线；所述多条扫描线与所述多条第一数据线和所述多条第二数据线绝缘交叉形成呈多行多列设置的多个像素区；
    所述数据线连接线包括沿所述第一方向延伸的第一数据线连接部、沿所述第二方向延伸的第二数据线连接部和第三数据线连接部；所述第二数据线连接部的一端与对应的所述第一子数据线电连接，另一端与所述第一数据线连接部的一端电连接；所述第一数据线连接部的另一端与所述第三数据线连接部的一端电连接；所述第三数据线连接部的另一端与对应的所述第二子数据线电连接；
    所述第一数据线连接部与所述列方向上的多个所述像素区对应设置，所述第二数据线连接部和所述第三数据线连接部与两个不同的所述行方向上的多个所述像素区对应设置。
  15. 根据权利要求14所述的显示装置，其中，每个所述像素区包括至少一个沿垂直于所述显示面板方向延伸且用于连通不同层金属层的换线孔；所述第一数据线连接部包括与对应的所述像素区中的所述换线孔对应设置的弯折部；所述弯折部朝远离对应的所述换线孔的方向弯折。
  16. 根据权利要求15所述的显示装置，其中，所述弯折部的形状包括矩形、三角形和弧形中的任意一种。
  17. 根据权利要求14所述的显示装置，其中，至少一条所述第一数据线在所述衬底上的正投影位于相邻的两个所述第一数据线连接部在所述衬底上的正投影之间。
  18. 根据权利要求14所述的显示装置，其中，至少部分所述第一数据线连接部与对应的所述多个像素区的中间位置重叠设置。
  19. 根据权利要求11所述的显示装置，其中，所述显示区围绕所述挖孔区设置，且所述挖孔区关于沿所述第一方向延伸的对称轴对称；所述多条数据线连接线关于所述对称轴对称设置。
  20. 根据权利要求11所述的显示装置，其中，所述扇出走线和所述数据线连接线的材料包括氧化铟锡。
PCT/CN2022/093563 2022-04-19 2022-05-18 显示面板和显示装置 WO2023201816A1 (zh)

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