WO2018126759A1 - 像素结构及显示面板 - Google Patents

像素结构及显示面板 Download PDF

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Publication number
WO2018126759A1
WO2018126759A1 PCT/CN2017/106315 CN2017106315W WO2018126759A1 WO 2018126759 A1 WO2018126759 A1 WO 2018126759A1 CN 2017106315 W CN2017106315 W CN 2017106315W WO 2018126759 A1 WO2018126759 A1 WO 2018126759A1
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WO
WIPO (PCT)
Prior art keywords
lines
active switch
array substrate
switch array
line
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Application number
PCT/CN2017/106315
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English (en)
French (fr)
Inventor
陈猷仁
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US16/303,753 priority Critical patent/US20200286920A1/en
Publication of WO2018126759A1 publication Critical patent/WO2018126759A1/zh
Priority to US16/425,970 priority patent/US10692898B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technologies, and in particular, to a pixel structure and a display panel.
  • a liquid crystal display is mostly a backlight type liquid crystal display, which is composed of a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is composed of two transparent substrates and a liquid crystal sealed between the substrates.
  • the active switch array substrate of the existing liquid crystal panel is provided with a source driver, a gate driver, a plurality of data lines and a plurality of scan lines, wherein the source driver and the plurality of data lines are connected, the gate driver and the plurality of scan lines connection.
  • a plurality of scan lines and a plurality of data lines are arranged on each other on the active switch array substrate, the source driver is mounted and fixed at one end position of the active switch array substrate, and the gate driver is mounted and fixed on one side of the active switch array substrate The position or the two side positions make it difficult for the existing liquid crystal panel to achieve a narrow bezel.
  • the application provides a pixel structure and a display panel to realize a narrow bezel design.
  • the present application discloses a pixel structure, the pixel structure including:
  • At least one connecting line parallel to the data line and respectively connected to the gate driver, wherein in each of the plurality of pixels, the at least one connecting line is correspondingly connected to the scan line.
  • the pixel structure further includes a plurality of active switches, and in each of the pixel regions, a plurality of the connecting lines are respectively correspondingly connected to the plurality of scan lines.
  • the pixel structure is formed on an active switch array substrate of a display panel, wherein the display panel is a liquid crystal display panel, an organic light emitting diode display panel, a light emitting diode display panel, a plasma display panel, and a field emission display.
  • the display panel is a liquid crystal display panel, an organic light emitting diode display panel, a light emitting diode display panel, a plasma display panel, and a field emission display.
  • the present application discloses a display panel, the display panel comprising:
  • the active switch array substrate includes:
  • the source driver is disposed on the active switch array substrate;
  • the gate driver is disposed on the active switch array substrate, wherein the source driver and the gate driver are disposed in the same direction of the active switch array substrate;
  • the plurality of connecting lines are respectively connected to the gate driver, and in each of the plurality of pixel regions, at least one of the connecting lines is connected to the scan line;
  • the length of the plurality of connecting lines gradually increases from a first side of the active switch array substrate to a second side of the active switch array substrate, and a plurality of the connecting lines are from the active switch array substrate.
  • One side is sequentially connected to a plurality of the scan lines, and the first side and the second side are opposite;
  • the active switch array substrate includes a first conductive layer and a second conductive layer; the scan line is located in the first conductive layer; the connection line is disposed on the second conductive layer; the connection line and corresponding Conductive holes are provided at intersections of the scan lines; the connection lines are electrically connected through the conductive holes and corresponding scan lines.
  • a length of the plurality of connecting lines gradually increases from a first side of the active switch array substrate to a second side of the active switch array substrate, and a plurality of the connecting lines are from the active switch
  • the first side of the array substrate is sequentially connected to a plurality of the scan lines, and the first side and the second side are opposite.
  • the length of the plurality of connecting lines is gradually increased from the first side of the active switch array substrate to the second side of the other side, and is sequentially connected to the scan line from the first side to the second side, which not only facilitates installation and production, but also enables active switching
  • the arrangement of the array substrate is compact.
  • a plurality of the connecting lines are disposed in parallel with each other.
  • a plurality of connecting lines are arranged in parallel with each other, and the connecting lines can be laid on the same layer of the active switch array substrate, which not only facilitates wiring, but also makes the arrangement of the active switch array substrate more compact.
  • a plurality of the connecting lines and the plurality of the data lines are disposed in parallel.
  • the application further lays a plurality of connecting lines and a plurality of data lines in parallel, so that the connecting lines and the data lines can be laid on the same layer of the active switch array substrate, which further facilitates the wiring, and further makes the arrangement of the active switch array substrate more compact.
  • the active switch array substrate includes a first conductive layer and a second conductive layer; the scan line is located at the first conductive layer; the connection line is disposed at the second conductive layer; Conductive holes are provided at intersections of the connecting lines and the corresponding scanning lines; the connecting lines are electrically connected through the conductive holes and corresponding scanning lines.
  • the scan line and the connection line are respectively disposed on the first conductive layer and the second conductive layer of the display panel, so that the scan line and the connection line are separated from each other, and the scan line and the connection line are connected through the conductive hole only at the corresponding position to prevent scanning. Lines and data lines are chaotic when routed.
  • each of the connecting lines is disposed between two adjacent ones of the data lines.
  • the respective connecting lines and the respective data lines are laid apart from each other, thereby preventing the connecting lines and the data lines from overlapping, thereby preventing the connecting lines and the data lines from overlapping and generating parasitic capacitance.
  • the data line includes adjacent first data lines and second data lines
  • the connection lines include a first connection line
  • the scan lines include a first scan line
  • the active switch array substrate The first active switch and the first pixel are respectively coupled to the first scan line, the first data line and the first pixel, and the first active switch and the first pixel are disposed in the first data Line and Between the second data lines, the first connection line is connected to the first scan line, and the first connection line is disposed between the first pixel and the second data line. Setting the first connection line between the first pixel and the second data line prevents the first connection line from being set to the first pixel position and affecting the normal development of the first pixel.
  • a vertical shift register circuit of the gate driver is disposed at a first end of the active switch array substrate. It is convenient to electrically connect the vertical shift register circuit and the connecting line.
  • the pins of the source driver are bonded to the edge of the active switch array substrate.
  • the length of the gate driver is less than or equal to the width of the display area in the display panel. Setting the length of the gate driver to be less than or equal to the width of the display area in the display panel makes the display panel have a better effect of achieving a narrow border.
  • the gate driver is located on top of the active switch array substrate, and the source driver is located at the bottom of the active switch array substrate. This is a specific way of setting the gate driver and the source driver in the present application.
  • the source driver can also be disposed on the top of the active switch array substrate, and the gate driver can be disposed on the bottom of the active switch array substrate.
  • the present application also discloses a display device including a backlight module and a display panel as described above.
  • the display panel of the present application has a source driver and a gate driver disposed opposite to the first end and the second end of the active switch array substrate, the source driver and the plurality of data lines are connected; the gate driver is connected by the connection line and the scan line.
  • Each of the connection lines is connected to one of the scan lines, so that the gate driver can normally drive the scan line through the connection line. Therefore, the gate driver of the present application is disposed on the opposite end of the source driver without occupying the space of the side position of the active switch array substrate, so that the narrow border or no border of the display panel can be realized.
  • FIG. 1 is a schematic structural view of a display panel according to an embodiment of the present application.
  • FIG. 2 is a partial structural schematic view of a display panel according to an embodiment of the present application.
  • FIG. 3 is a partial structural schematic view of a display panel according to an embodiment of the present application.
  • FIG. 4 is an equivalent circuit board diagram of FIG. 2.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection or integral connection; may be mechanical connection or electrical connection; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two components.
  • a pixel structure, a display panel, and a display device according to embodiments of the present application are described below with reference to FIGS. 1 through 5.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application
  • FIG. 2 is a partial structural diagram of a display panel according to an embodiment of the present application, that is, FIG. 1 is a schematic diagram of a part of the structure of the display panel.
  • FIG. 2 is a schematic diagram of a pixel structure in the display panel.
  • 3 is a partial schematic view of a display panel according to an embodiment of the present application
  • FIG. 4 is a circuit diagram of an embodiment of the present application, specifically, an equivalent circuit diagram of FIG.
  • the display panel of the embodiment includes an active switch array substrate 100, and the active switch array substrate 100 includes a source driver 112, a gate driver 111, a plurality of spaced-apart data lines 113, a plurality of spaced-apart scan lines 114, and a plurality of Strips 115 are arranged at intervals.
  • the source driver 112 is disposed at the first end 101 of the active switch array substrate 100; the gate driver 111 is disposed at the second end 102 of the active switch array substrate 100, the second end 102 and the One end 101 is opposite, that is, the second end 102 is the other end of the first end 101; a plurality of the data lines 113 are respectively connected to the source driver 112; a plurality of the scanning lines 114 and a plurality of The data lines 113 are arranged to be intersected; a plurality of the connecting lines 115 are respectively connected to the gate driver 111, and each of the connecting lines 115 is connected to one of the scanning lines 114.
  • the display panel has the source driver 112 and the gate driver 111 disposed opposite to the first end 101 and the second end 102 of the active switch array substrate 100, and the source driver 112 and the plurality of data lines 113 are connected; the gate driver 111 is connected to the scan line 114 through the connection line 115, and each of the connection lines 115 is connected to one scan line 114, respectively, so that the gate driver 111 can normally drive the scan line 114 through the connection line 115. Therefore, the gate driver 111 of the embodiment of the present application is provided to the source driver 112.
  • the opposite end of the active switch array substrate 100 does not occupy the space of the side position of the active switch array substrate 100, so that the narrow border or no border of the display panel can be realized.
  • the length of the plurality of connecting lines 115 gradually increases from the first side 103 of the active switch array substrate 100 to the second side 104 of the active switch array substrate 100, and the plurality of the connecting lines 115 are from the
  • the first side 103 of the active switch array substrate 100 is sequentially connected to a plurality of the scan lines 114, and the first side 103 and the second side 104 are opposite, that is, the first side 103 is the other side of the second side 104.
  • the length of the plurality of connecting lines 115 gradually increases from the first side 103 of the active switch array substrate 100 to the second side 104 of the other side, and is sequentially connected from the first side 103 to the second side 104 to the scan line 14, so that not only It is convenient to install and manufacture, and makes the arrangement of the active switch array substrate compact.
  • the wiring manner of the connection line in this embodiment is not limited thereto, for example, the length of the first side connection line from the second side of the active switch array substrate to the active switch array substrate is gradually increased.
  • the connection line is set to be the same length, and only the connection line needs to be electrically connected to the position where the scan line is connected.
  • a plurality of the connecting lines 115 are disposed in parallel with each other.
  • the plurality of connecting lines 115 are arranged in parallel with each other, and the connecting lines 115 can be laid on the same layer of the active switch array substrate, which not only facilitates wiring, but also makes the arrangement of the active switch array substrate 100 more compact.
  • the connecting lines may also be arranged in parallel.
  • a plurality of the connecting lines 115 and the plurality of the data lines 113 are arranged in parallel.
  • the plurality of connecting lines 115 and the plurality of data lines 113 are further disposed in parallel, so that the connecting lines 115 and the data lines 113 can be laid on the same layer of the active switch array substrate 100 to further facilitate the wiring, and the active switch array substrate is The arrangement of 100 is more compact.
  • the display panel includes a first conductive layer 120 and a second conductive layer 130; the scan line 114 is located at the first conductive layer 130; and the connection line 115 is disposed at the second The conductive layer 130; the conductive line 131 is disposed at an intersection of the connecting line 115 and the corresponding scan line 114; the connecting line 115 is electrically connected through the conductive hole 131 and the corresponding scan line 114.
  • the scan line 114 and the connection line 115 are respectively disposed on the first conductive layer 120 and the second conductive layer 130 of the display panel such that the scan line 114 and the connection line 115 are separated from each other, and are only connected and scanned through the conductive hole 131 at corresponding positions.
  • Line 114 And the connection line 115 prevents the scan line 114 and the data line 115 from being disordered during wiring.
  • each of the connecting lines 115 is disposed between two adjacent data lines 113.
  • the respective connecting lines and the respective data lines are laid apart from each other, thereby preventing the connecting lines and the data lines from overlapping, thereby preventing the connecting lines and the data lines from overlapping and generating parasitic capacitance.
  • the data line 113 includes adjacent first data lines 1131 and second data lines 1132, and the connection lines 115 include a first connection line 1151.
  • the scan line 114 includes a first scan line 1141 and a second scan line 1142.
  • the active switch array substrate 100 includes a first active switch 117 and a first pixel 1161, and the first active switch 117 and the first scan respectively
  • the line 1141, the first data line 1131 and the first pixel 1161 are coupled, and the first active switch 117 and the first pixel 1161 are disposed between the first data line 1131 and the second data line 1132, the first connection
  • the line 1151 is connected to the first scan line 1141, and the first connection line 1151 is disposed between the first pixel 1161 and the second data line 1132.
  • the second data line 1132 is located in the next row of the first data line 1131; wherein the second scan line 1142 is located on a row of the first scan line 1141.
  • the first connection line 1151 is disposed between the first pixel 1161 and the second data line 1132 to prevent the first connection line 1151 from being disposed at the position of the first pixel 1161 to affect the normal development of the first pixel 1161.
  • FIG. 3 only shows the structure of one pixel of the display panel, and other pixel structures in the display panel can also refer to FIG. 3, which will not be described in detail herein.
  • the active switch array substrate 100 further includes a common line 118 , and the connection line 115 covers the common line 118 .
  • the first connection line 1151 covers the common line 118.
  • the first active switch 117 and the common line 118 are coupled, and a pixel capacitor Clc and a storage capacitor Cst are disposed between the first active switch 117 and the common line 118 to drive the display panel normally.
  • the gate driver includes a vertical shift register circuit, and the vertical shift register circuit is disposed at the first end of the active switch array substrate, thereby facilitating the vertical shift register circuit Electrically connected to the cable.
  • the pin of the source driver is bonded to the side of the active switch array substrate. edge.
  • the length of the gate driver 111 is less than or equal to the width of the display area 116 in the display panel. Setting the length of the gate driver 111 to be less than or equal to the width of the display area 116 in the display panel makes the display panel more effective in achieving a narrow bezel.
  • This embodiment preferably sets the length of the gate driver 111 equal to the width of the display area 116.
  • the gate driver 111 is located at the top of the active switch array substrate 100, and the source driver 112 is located at the bottom of the active switch array substrate 100. This is a specific way of setting the gate driver and the source driver in the present application.
  • the source driver can also be disposed on the top of the active switch array substrate, and the gate driver can be disposed on the bottom of the active switch array substrate.
  • the display panel further includes a color filter substrate, and the color filter substrate and the active switch array substrate are oppositely disposed.
  • each pixel structure 1162 on the active switch array substrate can include a plurality of active switches (eg, 2 TFTs) 1171, 1172.
  • a plurality of connection lines 115 are correspondingly connected to the plurality of scan lines 114 to be electrically connected to the plurality of active switches 1171, 1172.
  • the pixel structure may be formed on an active switch array substrate of a display panel, and the display panel may be a liquid crystal display panel, an organic light emitting diode display panel, a light emitting diode display panel, a plasma display panel, and field emission.
  • the display panel may be a liquid crystal display panel, an organic light emitting diode display panel, a light emitting diode display panel, a plasma display panel, and field emission.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种像素结构及显示面板，其中，像素结构包括多条间隔布置的数据线(113)，多条数据线(113)分别和源极驱动器(112)连接；多条间隔布置的扫描线(114)，多条扫描线(114)分别和多条数据线(113)交叉设置，并形成多个像素区；多条间隔布置的连接线(115)，平行于数据线(113)且分别和栅极驱动器(111)连接，其中，在每一像素区中，至少一条连接线(115)和扫描线(114)连接。

Description

像素结构及显示面板 【技术领域】
本申请涉及显示技术领域，更具体的说，涉及一种像素结构及显示面板。
【背景技术】
近年来，随着科技的进步，许多不同的显示设备，例如液晶显示器(Liquid Crystal Display，LCD)或电激发光(Electro Luminenscence，EL)显示设备已广泛地应用于平面显示器。以液晶显示器为例，液晶显示器大部分为背光型液晶显示器，其是由液晶显示面板及背光模块(backlight module)所组成。液晶显示面板是由两片透明基板以及被封于基板之间的液晶所构成。
现有液晶面板的主动开关阵列基板上设置有源极驱动器、栅极驱动器、多条数据线和多条扫描线，其中，源极驱动器和多条数据线连接，栅极驱动器和多条扫描线连接。多条扫描线和多条数据线相互交叉排列在主动开关阵列基板上，源极驱动器安装固定在主动开关阵列基板的一个端部位置处，栅极驱动器安装固定在主动开关阵列基板的一个侧部位置或两个侧部位置，现有的液晶面板不易实现窄边框。
【发明内容】
本申请提供一种像素结构及显示面板，以实现窄边框设计。
本申请的目的是通过以下技术方案来实现的：
根据本申请的一个方面，本申请公开了一种像素结构，所述像素结构包括：
多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置，并形成多个像素区；
至少一条连接线，平行于所述数据线且分别和所述栅极驱动器连接，其中，在每一多个像素中，所述至少一条连接线是和所述扫描线对应连接。
在一些实施例中，所述像素结构还包括多个主动开关，在每一所述像素区中，多条所述连接线是分别对应地连接于多条所述扫描线。
在一些实施例中，所述像素结构是形成于一显示面板的主动开关阵列基板上，所述显示面板是液晶显示面板、有机发光二极管显示面板、发光二极管显示面板、等离子显示面板、场放射显示面板、纳米炭管显示面板、或电子墨水显示面板。
根据本申请的一个方面，本申请公开了一种显示面板，所述显示面板包括:
主动开关阵列基板；
彩色滤光片基板，相对于所述主动开关阵列基板；以及
液晶层，形成于所述主动开关阵列基板及所述彩色滤光片基板之间；
其中，所述主动开关阵列基板包括：
源极驱动器，所述源极驱动器设置在所述主动开关阵列基板上；
栅极驱动器，所述栅极驱动器设置在所述主动开关阵列基板上，其中所述源极驱动器和栅极驱动器是设置于所述主动开关阵列基板的同一方向上；
多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置，并形成多个像素区；
多条间隔布置的连接线，多条所述连接线分别和所述栅极驱动器连接，在每一所述多个像素区中，至少一条所述连接线是和所述扫描线连接；
其中，多条所述连接线的长度从所述主动开关阵列基板的第一侧至所述主动开关阵列基板的第二侧逐渐增加，多条所述连接线从所述主动开关阵列基板的第一侧依次与多条所述扫描线连接，所述第一侧和第二侧相对；
其中，所述主动开关阵列基板包括第一导电层和第二导电层；所述扫描线位于所述第一导电层；所述连接线设置在所述第二导电层；所述连接线和对应扫描线交叉位置设有导电孔；所述连接线通过所述导电孔和对应的扫描线电连接。
在一些实施例中，多条所述连接线的长度从所述主动开关阵列基板的第一侧至所述主动开关阵列基板的第二侧逐渐增加，多条所述连接线从所述主动开关阵列基板的第一侧依次与多条所述扫描线连接，所述第一侧和第二侧相对。多条连接线的长度从主动开关阵列基板的第一侧至另一侧的第二侧逐渐增加，且从第一侧至第二侧依次与扫描线连接，不仅方便安装生产，而且使得主动开关阵列基板的排布紧凑。
在一些实施例中，多条所述连接线相互平行设置。多条连接线相互之间平行设置，可在主动开关阵列基板的同一层铺设连接线，不仅方便布线，而且使得主动开关阵列基板的排布更加紧凑。
在一些实施例中，多条所述连接线和多条所述数据线平行设置。本申请进一步将多条连接线和多条数据线平行设置，就可以在主动开关阵列基板的同一层铺设连接线和数据线，进一步方便布线，而且使得主动开关阵列基板的排布更加紧凑。
在一些实施例中，所述主动开关阵列基板包括第一导电层和第二导电层；所述扫描线位于所述第一导电层；所述连接线设置在所述第二导电层；所述连接线和对应扫描线交叉位置设有导电孔；所述连接线通过所述导电孔和对应的扫描线电连接。将扫描线和连接线分别设置在显示面板的第一导电层和第二导电层，使得扫描线和连接线相互分开来，仅在对应的位置处通过导电孔连通扫描线和连接线，防止扫描线和数据线在布线时乱线。
在一些实施例中，每一个所述连接线设置在两个相邻所述数据线之间。将各个连接线及各个数据线相互分开进行铺设，这样就防止连接线和数据线重叠，进而防止连接线和数据线重叠而产生寄生电容。
在一些实施例中，所述数据线包括相邻的第一数据线和第二数据线，所述连接线包括第一连接线，所述扫描线包括第一扫描线，所述主动开关阵列基板包括第一主动开关和第一像素，所述第一主动开关分别与第一扫描线、第一数据线及第一像素耦合，所述第一主动开关和第一像素设置在所述第一数据线和 第二数据线之间，所述第一连接线和第一扫描线连接，所述第一连接线设置在所述第一像素和第二数据线之间。将第一连接线设置在第一像素和第二数据线之间，就防止第一连接线设置到第一像素位置处而影响第一像素正常显影。
在一些实施例中，所述栅极驱动器的竖向移位寄存器电路设置在所述主动开关阵列基板的第一端。方便将竖向移位寄存器电路和连接线进行电连接。
在一些实施例中，所述源极驱动器的引脚邦定到所述主动开关阵列基板的边缘。
在一些实施例中，所述栅极驱动器的长度小于或等于所述显示面板中显示区域的宽度。将栅极驱动器的长度设置小于或等于显示面板中显示区域的宽度，使得显示面板实现窄边框的效果更佳。
在一些实施例中，所述栅极驱动器位于所述主动开关阵列基板的顶部，所述源极驱动器位于所述主动开关阵列基板的底部。这是本申请设置栅极驱动器及源极驱动器的一种具体方式，当然，也可以将源极驱动器设置在主动开关阵列基板的顶部，以及将栅极驱动器设置在主动开关阵列基板的底部。
根据本申请的另一方面，本申请还公开了一种显示装置，所述显示装置包括背光模组和如上所述的显示面板。
本申请的显示面板将源极驱动器和栅极驱动器相对设置在主动开关阵列基板的第一端和第二端，源极驱动器和多条数据线连接；栅极驱动器通过连接线和扫描线连接，且每一条连接线分别和一条扫描线连接，这样栅极驱动器就可以通过连接线正常驱动扫描线。从而本申请栅极驱动器因设置到源极驱动器的相对端，而不会占用到主动开关阵列基板的侧部位置的空间，这样就可以实现显示面板的窄边框或无边框。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原 理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请一实施例显示面板的结构示意图；
图2是本申请一实施例显示面板的部分结构示意图；
图3是本申请一实施例显示面板的部分结构示意图；
图4是图2的等效电路板图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个组件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面参考图1至图5描述本申请实施例像素结构、显示面板及显示装置。
下面结合附图1至图5和具体实施例对本申请作进一步详细说明。
在本申请一实施例中，如图1至图4所示，图1为本申请一实施例显示面板的结构示意图，图2为本申请一实施例显示面板的部分结构示意图，也就是图2为图1的部分结构示意图，具体的是，图2为显示面板中一个像素结构的示意图。以及图3为本申请一实施例显示面板的部分示意图，图4为本申请一实施例的电路图，具体是图2的等效电路图。本实施例的显示面板包括主动开关阵列基板100，所述主动开关阵列基板100包括源极驱动器112、栅极驱动器111、多条间隔布置的数据线113、多条间隔布置的扫描线114及多条间隔布置的连接线115。
所述源极驱动器112设置在所述主动开关阵列基板100的第一端101；所述栅极驱动器111设置在所述主动开关阵列基板100的第二端102，所述第二端102和第一端101相对，也就是说第二端102为第一端101的另一端；多条所述数据线113分别和所述源极驱动器112连接；多条所述扫描线114分别和多条所述数据线113交叉设置；多条所述连接线115分别和所述栅极驱动器111连接，每一条所述连接线115分别和一条所述扫描线114连接。
本申请实施例显示面板将源极驱动器112和栅极驱动器111相对设置在主动开关阵列基板100的第一端101和第二端102，源极驱动器112和多条数据线113连接；栅极驱动器111通过连接线115和扫描线114连接，且每一条连接线115分别和一条扫描线114连接，这样栅极驱动器111就可以通过连接线115正常驱动扫描线114。从而本申请实施例栅极驱动器111因设置到源极驱动器112 的相对端，而不会占用到主动开关阵列基板100的侧部位置的空间，这样就可以实现显示面板的窄边框或无边框。
其中，多条所述连接线115的长度从所述主动开关阵列基板100的第一侧103至所述主动开关阵列基板100的第二侧104逐渐增加，多条所述连接线115从所述主动开关阵列基板100的第一侧103依次与多条所述扫描线114连接，所述第一侧103和第二侧104相对，也就是第一侧103为第二侧104的另一侧。多条连接线115的长度从主动开关阵列基板100的第一侧103至另一侧的第二侧104逐渐增加，且从第一侧103至第二侧104依次与扫描线14连接，这样不仅方便安装生产，而且使得主动开关阵列基板的排布紧凑。然而，需要说明的是，本实施例连接线的布线方式并不限于此，比如：从主动开关阵列基板的第二侧至主动开关阵列基板的第一侧连接线的长度逐渐增加。再比如：将连接线设置等长，而仅在连接线需要与扫描线连接的位置进行电连接。
进一步的，多条所述连接线115相互平行设置。多条连接线115相互之间平行设置，可在主动开关阵列基板的同一层铺设连接线115，不仅方便布线，而且使得主动开关阵列基板100的排布更加紧凑。然而，需要说明的是，连接线也可以不平行设置。
更进一步的，多条所述连接线115和多条所述数据线113平行设置。本申请实施例进一步将多条连接线115和多条数据线113平行设置，就可以在主动开关阵列基板100的同一层铺设连接线115和数据线113，进一步方便布线，而且使得主动开关阵列基板100的排布更加紧凑。
其中，如图4所示，所述显示面板包括第一导电层120和第二导电层130；所述扫描线114位于所述第一导电层130；所述连接线115设置在所述第二导电层130；所述连接线115和对应扫描线114交叉位置设有导电孔131；所述连接线115通过所述导电孔131和对应的扫描线114电连接。将扫描线114和连接线115分别设置在显示面板的第一导电层120和第二导电层130，使得扫描线114和连接线115相互分开来，仅在对应的位置处通过导电孔131连通扫描线114 和连接线115，防止扫描线114和数据线115在布线时乱线。
其中，每一个所述连接线115设置在两个相邻所述数据线113之间。将各个连接线及各个数据线相互分开进行铺设，这样就防止连接线和数据线重叠，进而防止连接线和数据线重叠而产生寄生电容。
具体的，如图3和图5所示，在一个像素结构中，所述数据线113包括相邻的第一数据线1131和第二数据线1132，所述连接线115包括第一连接线1151，所述扫描线114包括第一扫描线1141和第二扫描线1142，所述主动开关阵列基板100包括第一主动开关117和第一像素1161，所述第一主动开关117分别与第一扫描线1141、第一数据线1131及第一像素1161耦合，所述第一主动开关117和第一像素1161设置在所述第一数据线1131和第二数据线1132之间，所述第一连接线1151和第一扫描线1141连接，所述第一连接线1151设置在所述第一像素1161和第二数据线1132之间。其中，第二数据线1132位于第一数据线1131的下一行；其中，第二扫描线1142位于第一扫描线1141上一行。本申请实施例将第一连接线1151设置在第一像素1161和第二数据线1132之间，就防止第一连接线1151设置到第一像素1161位置处而影响第一像素1161正常显影。需要说明的是，图3仅示出了显示面板的一个像素的结构，而显示面板中其他像素结构同样可以参考图3，在此不再进行一一详述。
其中，主动开关阵列基板100还包括有共通线118，连接线115覆盖到共通线118上。具体的，如图3所示，第一连接线1151覆盖到共通线118上。
在本实施例中，第一主动开关117和共通线118耦合，且在第一主动开关117和共通线118之间设置有像素电容Clc和存储电容Cst，以正常驱动显示面板。
在本实施例中，所述栅极驱动器包括有竖向移位寄存器电路，所述竖向移位寄存器电路设置在所述主动开关阵列基板的第一端，从而方便将竖向移位寄存器电路和连接线进行电连接。
在本实施例中，所述源极驱动器的引脚邦定到所述主动开关阵列基板的边 缘。
在本实施例中，所述栅极驱动器111的长度小于或等于所述显示面板中显示区域116的宽度。将栅极驱动器111的长度设置小于或等于显示面板中显示区域116的宽度，使得显示面板实现窄边框的效果更佳。本实施例优选将栅极驱动器111的长度设置等于显示区域116的宽度。当然，需要说明的是，本实施例将栅极驱动器111的长度设置略大于显示区域也是可以的。
其中，所述栅极驱动器111位于所述主动开关阵列基板100的顶部，所述源极驱动器112位于所述主动开关阵列基板100的底部。这是本申请设置栅极驱动器及源极驱动器的一种具体方式，当然，也可以将源极驱动器设置在主动开关阵列基板的顶部，以及将栅极驱动器设置在主动开关阵列基板的底部。
在本实施例中，显示面板还包括有彩膜基板，彩膜基板和主动开关阵列基板相对设置。
如图5所示，在一些实施例中，主动开关阵列基板上的每一像素结构1162可包括多个主动开关(例如2个TFT)1171、1172。在每一像素结构1162中，多条连接线115可对应地连接于多条扫描线114，以对应电性连接于多个主动开关1171、1172。
在一些实施例中，所述像素结构可形成于一显示面板的主动开关阵列基板上，所述显示面板可以是液晶显示面板、有机发光二极管显示面板、发光二极管显示面板、等离子显示面板、场放射显示面板、纳米炭管显示面板、或电子墨水显示面板。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种像素结构，包括：
    多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
    多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置，并形成多个像素区；
    至少一条连接线，平行于所述数据线且分别和所述栅极驱动器连接，其中，在每一所述像素区中，所述至少一条连接线是和所述扫描线连接。
  2. 如权利要求1所述的像素结构，其中所述像素结构还包括多个主动开关，在每一所述像素区中，多条所述连接线是分别对应地连接于多条所述扫描线。
  3. 一种像素结构，包括：
    多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
    多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置，并形成多个像素区；
    至少一条连接线，平行于所述数据线且分别和所述栅极驱动器连接，其中，在每一所述像素区中，所述至少一条连接线是和所述扫描线连接；
    其中，所述像素结构还包括多个主动开关，在每一所述像素区中，多条所述连接线是分别对应地连接于多条所述扫描线；
    其中，所述像素结构是形成于一显示面板的主动开关阵列基板上。
  4. 一种显示面板，包括:
    主动开关阵列基板；
    彩色滤光片基板，相对于所述主动开关阵列基板；以及
    液晶层，形成于所述主动开关阵列基板及所述彩色滤光片基板之间；
    其中，所述主动开关阵列基板包括：
    源极驱动器，所述源极驱动器设置在所述主动开关阵列基板上；
    栅极驱动器，所述栅极驱动器设置在所述主动开关阵列基板上，其中所述 源极驱动器和栅极驱动器是设置于所述主动开关阵列基板的同一方向上；
    多条间隔布置的数据线，多条所述数据线分别和所述源极驱动器连接；
    多条间隔布置的扫描线，多条所述扫描线分别和多条所述数据线交叉设置，并形成多个像素区；
    多条间隔布置的连接线，多条所述连接线分别和所述栅极驱动器连接，在每一所述多个像素区中，至少一条所述连接线是和一条所述扫描线连接；
    其中，多条所述连接线的长度从所述主动开关阵列基板的第一侧至所述主动开关阵列基板的第二侧逐渐增加，多条所述连接线从所述主动开关阵列基板的第一侧依次与多条所述扫描线连接，所述第一侧和第二侧相对；
    其中，所述主动开关阵列基板包括第一导电层和第二导电层；所述扫描线位于所述第一导电层；所述连接线设置在所述第二导电层；所述连接线和对应扫描线交叉位置设有导电孔；所述连接线通过所述导电孔和对应的扫描线电连接。
  5. 如权利要求4所述的显示面板，其中所述源极驱动器设置在所述主动开关阵列基板的第一端，所述栅极驱动器设置在所述主动开关阵列基板的第二端，所述第二端和第一端相对。
  6. 如权利要求4所述的显示面板，其中多条所述连接线相互平行设置。
  7. 如权利要求4所述的显示面板，其中多条所述连接线和多条所述数据线平行设置。
  8. 如权利要求4所述的显示面板，其中每一个所述连接线设置在两个相邻所述数据线之间。
  9. 如权利要求4所述的显示面板，其中多条所述连接线相互平行设置；
    多条所述连接线和多条所述数据线平行设置；
    每一个所述连接线设置在两个相邻所述数据线之间。
  10. 如权利要求4所述的显示面板，其中所述数据线包括相邻的第一数据线和第二数据线，所述连接线包括第一连接线，所述扫描线包括第一扫描线， 所述主动开关阵列基板包括第一主动开关和第一像素，所述第一主动开关分别与所述第一扫描线、所述第一数据线及所述第一像素耦合，所述第一主动开关和所述第一像素设置在所述第一数据线和所述第二数据线之间，所述第一连接线和所述第一扫描线连接，所述第一连接线设置在所述第一像素和所述第二数据线之间。
  11. 如权利要求4所述的显示面板，其中主动开关阵列基板还包括共通线，所述连接线覆盖到共通线上。
  12. 如权利要求4所述的显示面板，其中主动开关阵列基板还包括第一主动开关和共通线，所述第一主动开关和所述共通线耦合，且在所述第一主动开关和所述共通线之间设置有像素电容和存储电容。
  13. 如权利要求5所述的显示面板，其中所述栅极驱动器包括有竖向移位寄存器电路，所述竖向移位寄存器电路设置在所述主动开关阵列基板的第一端。
  14. 如权利要求4所述的显示面板，其中所述源极驱动器设置在所述主动开关阵列基板的第一端，所述栅极驱动器设置在所述主动开关阵列基板的第二端，所述第二端和第一端相对；
    所述栅极驱动器包括有竖向移位寄存器电路，所述竖向移位寄存器电路设置在所述主动开关阵列基板的第一端。
  15. 如权利要求4所述的显示面板，其中所述源极驱动器的引脚邦定到所述主动开关阵列基板的边缘。
  16. 如权利要求4所述的显示面板，其中所述栅极驱动器的长度小于或等于所述显示面板中显示区域的宽度。
  17. 如权利要求4所述的显示面板，其中所述栅极驱动器位于所述主动开关阵列基板的顶部，所述源极驱动器位于所述主动开关阵列基板的底部。
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