WO2021207930A9 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021207930A9
WO2021207930A9 PCT/CN2020/084713 CN2020084713W WO2021207930A9 WO 2021207930 A9 WO2021207930 A9 WO 2021207930A9 CN 2020084713 W CN2020084713 W CN 2020084713W WO 2021207930 A9 WO2021207930 A9 WO 2021207930A9
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WO
WIPO (PCT)
Prior art keywords
dummy
power
layer
virtual
display substrate
Prior art date
Application number
PCT/CN2020/084713
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English (en)
French (fr)
Other versions
WO2021207930A1 (zh
Inventor
张猛
尚庭华
韩林宏
杨路路
屈忆
张鑫
和玉鹏
李慧君
姜晓峰
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/084713 priority Critical patent/WO2021207930A1/zh
Priority to US17/263,576 priority patent/US20220199733A1/en
Priority to CN202090000057.0U priority patent/CN215578564U/zh
Priority to EP20931099.4A priority patent/EP4138136A4/en
Publication of WO2021207930A1 publication Critical patent/WO2021207930A1/zh
Publication of WO2021207930A9 publication Critical patent/WO2021207930A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • Active Matrix Organic Light-Emitting Diode (English: Active Matrix Organic Light-Emitting Diode, abbreviation: AMOLED) displays self-luminous, wide color gamut, and high
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • a display substrate including:
  • the base substrate includes a display area and a non-display area surrounding the display area;
  • a plurality of power lines located in the display area and extending along a first direction, the plurality of power lines are electrically connected to the plurality of sub-pixels, and are configured to provide power signals to the plurality of sub-pixels;
  • a plurality of virtual sub-pixels in the non-display area located on one side of the display area along the first direction;
  • a plurality of virtual power lines are located in the non-display area and extend along the first direction, and the plurality of virtual power lines and the plurality of virtual sub-pixels are located on the same side of the display area; wherein, the multiple At least part of the power lines of the power lines are electrically connected to at least part of the virtual power lines of the plurality of virtual power lines.
  • the display substrate further includes at least one first power connection line located in the non-display area, and the at least one first power connection line is located between the plurality of power lines and the plurality of virtual power lines. Extending occasionally and along the first direction, the at least one first power connection line is electrically connected to at least one of the plurality of power lines and at least one of the plurality of virtual power lines.
  • the display substrate includes a plurality of first power connection wires, and the plurality of first power connection wires are connected to the plurality of power wires and the plurality of virtual power wires in a one-to-one correspondence.
  • the display substrate further includes at least one second power connection line extending in a second direction, the first direction intersects the second direction, the plurality of first power connection lines and the at least one A second power connection line at least partially overlaps and is electrically connected.
  • the number of the at least one second power connection line is one, or the number of the at least one second power connection line is multiple, and the multiple second power connection lines are parallel to each other.
  • the display substrate includes one second power connection line, and a width of the second power connection line perpendicular to the second direction ranges from 20 ⁇ m to 30 ⁇ m.
  • the second power connection line and the first power connection line are in the same layer.
  • the display substrate further includes a plurality of graphic blocks which are located in the non-display area and are arranged at intervals around the display area.
  • the orthographic projection of the first power connection line and the second power connection line on the base substrate and the orthographic projection of the pattern block on the base substrate do not overlap.
  • the display substrate further includes a plurality of virtual data lines located in the non-display area and extending along the first direction, and the plurality of virtual data lines are electrically connected to the plurality of virtual power lines.
  • the plurality of virtual data lines and the plurality of virtual power lines are electrically connected in a one-to-one correspondence.
  • one virtual data line and one virtual power line are electrically connected through a plurality of connection points, and the plurality of connection points correspond to the plurality of virtual sub-pixels in a one-to-one correspondence.
  • the dummy sub-pixel further includes a dummy active layer on the base substrate, and a dummy first gate layer on the side of the dummy active layer away from the base substrate.
  • a dummy second gate layer on a side of the dummy first gate layer away from the base substrate, and the dummy power line is located on a side of the dummy second gate layer away from the base substrate;
  • the dummy power line is electrically connected to at least one of the dummy active layer, the dummy first gate layer, and the dummy second gate layer.
  • the dummy power line is electrically connected to the dummy active layer, the dummy first gate layer, and the dummy second gate layer, respectively.
  • the dummy sub-pixel further includes a dummy first gate insulating layer, a dummy second gate insulating layer, and a dummy interlayer insulating layer, and the dummy first gate insulating layer is located between the dummy active layer and the dummy Between the first gate layer, the dummy second gate insulating layer is located between the dummy first gate layer and the dummy second gate layer, and the dummy interlayer insulating layer is located on the dummy second gate layer. Between the gate layer and the dummy power line.
  • the dummy sub-pixel further includes a first via hole penetrating the dummy second gate insulating layer and the dummy interlayer insulating layer, and the dummy power line passes through the first via hole and the dummy The first gate layer is electrically connected.
  • the dummy sub-pixel further includes a second via hole penetrating the dummy first gate insulating layer, the dummy second gate insulating layer, and the dummy interlayer insulating layer, and the dummy power line passes through the The second via is electrically connected to the dummy active layer.
  • the dummy sub-pixel further includes a third via hole penetrating the dummy interlayer insulating layer, and the dummy power line is electrically connected to the dummy second gate layer through the third via hole.
  • the dummy sub-pixel further includes a first dummy electrode, the first dummy electrode is electrically connected to the dummy power line, and the first dummy electrode is connected to the dummy active electrode through the second via hole. Layer electrical connection.
  • the dummy sub-pixel further includes a second dummy electrode, the second dummy electrode is electrically connected to the dummy power line, and the second dummy electrode is connected to the dummy second electrode through the third via hole.
  • the gate layer is electrically connected.
  • the plurality of sub-pixels include an active layer located on the base substrate, a gate layer located on a side of the active layer away from the base substrate, and a gate layer located far away from the substrate.
  • the source and drain layer on one side of the base substrate;
  • the plurality of power supply lines, the plurality of dummy power supply lines, the first power supply connection line, and the second power supply connection line are located on the same layer as the source-drain layer.
  • the plurality of sub-pixels include an active layer located on the base substrate, a gate layer located on a side of the active layer away from the base substrate, and a gate layer located far away from the substrate.
  • the source and drain layer on one side of the base substrate;
  • the plurality of pattern blocks and the active layer are located on the same layer.
  • the display substrate further includes a power bus, the power bus is located in the non-display area on a side of the display area away from the plurality of virtual sub-pixels, and the power bus is connected to the plurality of power sources. Wire electrical connection.
  • the display substrate further includes a plurality of data lines located in the display area and extending along the first direction, and the plurality of data lines and the plurality of power lines are insulated from each other .
  • a display device in another aspect, includes the display substrate as described in any one of the preceding items.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a partial structure of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of the structure of the SD layer and the virtual SD layer provided by an embodiment of the present disclosure
  • FIG. 6 is a cross-sectional view of an OLED display substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a superimposed schematic diagram of a part of the film structure in an OLED display substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an active layer and a virtual active layer shown in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a first gate layer and a dummy first gate layer shown in an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a second gate layer and a dummy second gate layer shown in an embodiment of the present disclosure
  • FIG. 11 is a superimposed schematic diagram of a part of a film structure in a virtual sub-pixel in an OLED display substrate provided by an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a superposition of a virtual first gate layer and a virtual source and drain layer provided by an embodiment of the present disclosure
  • FIG. 13 is a superimposed schematic diagram of a virtual active layer and a virtual source drain layer provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a superposition of a dummy second gate layer and a dummy source drain layer provided by an embodiment of the present disclosure.
  • OLED display panels can be divided into passive matrix driving organic light-emitting diodes (English: Passive Matrix Driving OLED, abbreviated as: PMOLED) and AMOLED according to the driving mode.
  • PMOLED Passive Matrix Driving OLED
  • AMOLED AMOLED according to the driving mode.
  • the solution provided by this application is mainly applied to AMOLED display panels, for example, it may be a flexible AMOLED display panel.
  • the OLED is driven by current, and the display brightness of OLED is proportional to the driving current.
  • the driving current formula I K*(VDD-Vdata-
  • the voltage jump of other signals in the display area will affect the VDD signal, causing a slight disturbance.
  • the disturbance of the VDD signal causes the change of the OLED display brightness, which affects the display effect.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes:
  • the base substrate 100 includes a display area 10 and a non-display area 20 surrounding the display area 10;
  • a plurality of sub-pixels 101 are located in the display area 10;
  • a plurality of dummy pixels (English: Dummy Pixel) 201 are located in the non-display area 20 on the side of the display area 10 along the first direction a. That is, the plurality of virtual sub-pixels 201 and the display area 10 are arranged in sequence along the first direction.
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate further includes:
  • a plurality of power supply lines (VDD lines) 31 are located in the display area 10 and extend along the first direction a.
  • the plurality of power supply lines 31 are electrically connected to the plurality of sub-pixels 101 and are configured to extend to the plurality of sub-pixels 101.
  • the pixel 101 provides a power signal;
  • a plurality of virtual power lines 32 are located in the non-display area 20 and extend along the first direction a, and the plurality of virtual power lines 32 and the plurality of virtual sub-pixels 201 are located on the same side of the display area 10 ;
  • At least part of the power lines 31 of the plurality of power lines 31 and at least part of the virtual power lines 32 of the plurality of virtual power lines 32 are electrically connected.
  • a capacitance is formed between the virtual power supply line of the virtual sub-pixels in the non-display area 20 and the common power supply line (VSS line) 41.
  • the virtual power supply line of the non-display area 20 is connected to the gate high level (VGH).
  • VGH gate high level
  • the capacitor can compensate for the jump of the power line of the display area 10. , Increase the stability of the power line of the display area 10, so this solution can improve the brightness stability of the display panel.
  • the plurality of dummy power lines 32 and the plurality of dummy sub-pixels 201 at least partially overlap. That is, when the virtual power line 32 is arranged along the first direction, it passes through the area where the virtual sub-pixel 201 is located and the area between the adjacent virtual sub-pixels 201, so that the part of each virtual power line 32 overlaps the virtual sub-pixel 201 .
  • This design makes the virtual power line 32 in the non-display area 20 and the VSS line form a large overlap capacitance.
  • the VSS line outputs a stable DC signal, so that when it is used as one end of the capacitor, it can effectively suppress the other end of the capacitor.
  • the voltage disturbance of the connected power line improves the voltage stability of the power line.
  • the aforementioned power line 31 may be located in the source and drain (SD) layer of the display substrate, the dummy power line 32 is located in the virtual source and drain layer of the display substrate, and the common power line (VSS) 41 may be formed by the source and drain layer ( And/or the virtual source and drain layer) and the anode layer (and/or the virtual anode layer) of the display substrate.
  • the common power line 41 may also be a single-layer wiring formed by an anode layer (and/or a dummy anode layer).
  • the source-drain layer and the virtual source-drain layer are arranged in the same layer, the virtual source-drain layer is located in the non-display area, the source-drain layer is located in the display area, the anode layer and the virtual anode layer are also arranged in the same situation, and the X layer and The virtual X layer is arranged based on the above rules.
  • the middle of the display substrate is the display area 10, and the area of the display substrate except the display area 10 is the non-display area, also called the peripheral area.
  • the non-display area also called the peripheral area.
  • a part of the non-display area where the virtual sub-pixels are arranged is above the display area 10, that is, the area indicated by the mark M in FIG. 2.
  • both the non-display area 20 and the display area 10 include sub-pixels.
  • the sub-pixels in the display area 10 are normal sub-pixels and can emit light; the sub-pixels in the non-display area 20 are virtual sub-pixels, and the virtual sub-pixels do not Glow.
  • the purpose of setting the virtual sub-pixels is to ensure the uniformity of the graphics in the display area, thereby ensuring the display effect of the display area. It is precisely because the virtual sub-pixels are not used for light emission, in the related art, the virtual power line in the non-display area and the power line in the normal area are disconnected, and this application connects them to solve the problem of the signal of the power line. Stability issues. Moreover, even though the power line is connected, the virtual sub-pixels still cannot obtain other signals, such as data signals, etc., so the virtual sub-pixels still do not emit light.
  • At least part of the power lines 31 of the plurality of power lines 31 and at least part of the virtual power lines 32 of the plurality of virtual power lines 32 are electrically connected in a one-to-one correspondence. That is, not all power cords 31 are connected to the virtual power cord 32, and each power cord 31 is connected to only one virtual power cord 32, and each virtual power cord 32 is also connected to only one power cord 31.
  • the connection mode of the power line 31 and the virtual power line 32 will be described below with reference to FIG. 2.
  • the display substrate further includes at least one first power connection line 33 located in the non-display area 20, and the at least one first power connection line 33 is located between the multiple power lines 31 and the multiple Between the virtual power lines 32 and extend along the first direction a, the at least one first power connection line 33 electrically connects at least one of the plurality of power lines 31 and the plurality of virtual power lines 32 At least one of them.
  • the display substrate includes a plurality of first power connection wires 33, and the plurality of first power connection wires 33 are connected to the plurality of power wires 31 and the plurality of virtual power wires 32 in a one-to-one correspondence.
  • the first power connection line 33 may be arranged in the same layer as the power line 31.
  • the same layer may mean that it is formed in one patterning process, or it may mean that it is located on the same side of the same layer, or it may mean that the surfaces close to the base substrate are all in contact with the same layer.
  • the display substrate further includes a power bus 300, and the non-display area 20 on the other side of the display area 10, that is, the power bus 300 and the aforementioned dummy sub-pixels 201 are arranged in the display area 10 On opposite sides, the power bus 300 is electrically connected to the multiple power lines 31.
  • the power cord 31 is connected to a flexible circuit board (English: Flexible Printed Circuit, abbreviated as: FPC) (labeled A in the figure) through the power bus 300, and the FPC is the power source for the display substrate Line 31 provides signal driving.
  • FPC Flexible Printed Circuit
  • the power bus 300 may be arranged on the same layer as the power line 31.
  • the end where the virtual sub-pixel 201 is located may also be referred to as the far (away) FPC end of the display substrate.
  • the VDD signal stability of the sub-pixels far away from the FPC end in the display area 10 is poor, and the display stability of the sub-pixels far away from the FPC end in the display area 10 is improved by the solution of the present application.
  • the display substrate further includes gate lines 71, the gate lines 71 and the power lines 31 are located in different layers, and the gate lines 71 and the power lines 31 are arranged crosswise, for example, vertically.
  • a gate line signal can be written to the gate line 71.
  • FIG. 3 is a schematic diagram of a partial structure of a display substrate provided by an embodiment of the present disclosure.
  • this part may be a structural schematic diagram showing the upper left corner of the substrate.
  • a display substrate with rounded corners is designed with virtual sub-pixels.
  • multiple graphic blocks in the non-display area 20 are also reserved. The multiple graphic blocks are arranged around the display area at intervals. For example, in the virtual active layer, the virtual source and drain layer, etc., the symbol B in FIG. 3 is the graphic block of the virtual active layer.
  • the function of the graphic block B is the same as that of the virtual sub-pixel 21 in the non-display area 20.
  • the pattern is formed on the edge portion to ensure the uniformity of the pattern of the normal pixel 11 in the display area 10. Because in the case of rounded corners on the display substrate, the etched pattern on the edge may be deviated.
  • the power line located in the middle area 10A of the display area 10 is connected to the virtual power line in the non-display area 20 through the first power connection line 33, and the power line located in the edge area 10B of the display area 10 is not Connected to the virtual power line in the non-display area 20; in the second direction b, the edge area 10B of the display area 10 is located between the middle area 10A of the display area 10 and the edge of the display substrate, and the second direction b is One direction a crosses, for example, perpendicular to each other.
  • the orthographic projection of the first power connection line 33 on the base substrate and the orthographic projection of the pattern block B on the base substrate do not overlap.
  • edge portion can form the aforementioned graphic block B, and the graphic uniformity of the display area is ensured.
  • the display substrate further includes at least one second power connection line 34 extending along the second direction b.
  • the plurality of first power connection lines 33 and the at least one second power connection line 34 are at least Partially overlapped and electrically connected.
  • the second power connection line 34 is located in the non-display area 20.
  • the orthographic projection of the second power connection line 34 on the base substrate and the orthographic projection of the pattern block B on the base substrate do not overlap.
  • the overlap area between the VDD line and the VSS line can be effectively increased, that is, the capacitor overlap area is increased, and the VDD stability is improved; on the other hand, the display substrate
  • the power lines are cross-connected through the second power connection line 34, which connects the power lines of the sub-pixels of each column together, is interwoven into a mesh, and forms a capacitor with VSS, thereby improving the signal uniformity of the power lines of each part, so the solution can be Improve the brightness uniformity of the display panel.
  • the number of the second power connection wires 34 may be one or more. As shown in FIG. 3, there is a second power connection line 34, which is convenient for design and manufacture.
  • the number of the second power connection line 34 is one, and the width of the second power connection line 34 in the first direction a may be the distance between the closest sub-pixel and the virtual sub-pixel. 1/3 ⁇ 1/2 of W.
  • the width of the second power connection line 34 is designed in this way to ensure that the overlapping area of the capacitors is as large as possible on the one hand, and on the other hand, to prevent the second power connection line 34 from being too close to the sub-pixel, which affects the operation of the sub-pixel.
  • the width of the second power connection line 34 may range from 20 to 30 microns.
  • the second power connection line 34 is provided in the same layer as the power line 31, and the second power connection line 34 is located at the virtual source drain (English: Source Drain, abbreviated as: SD) layer, so that The second power connection line 34 and the power line 31 are made together, and the connection of the second power connection line 34 and the power line 31 can be realized without additional processes.
  • SD Source Drain
  • FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the number of the second power connection wires 34 is multiple, and the multiple second power connection wires 34 are arranged in parallel at intervals.
  • FIG. 5 is a schematic diagram of the structure of the SD layer and the virtual SD layer provided by an embodiment of the present disclosure.
  • the display area is the SD layer 30, and the non-display area is the virtual SD layer 30'.
  • the power line 31 of the display area 10 is connected to the virtual power line 32 corresponding to the non-display area 20 to form a power line extending from the display area 10 to the non-display area 20.
  • the correspondence mentioned here refers to the power line 31 and the dummy power line 32 located in the same column of pixels.
  • the width of the first power connection line 33 for connecting the power line 31 and the dummy power line 32 in the non-display area 20 is larger than the width of the connected power line 31 and the dummy power line 32, where The width refers to the width in the second direction b.
  • the SD layer and the virtual SD layer in addition to power lines (power line 31 and virtual power line 32) and power connection lines (first power connection line 33 and second power connection line 34), it also includes data lines (in the display area). Data lines 35, dummy data lines 36 in the non-display area) and electrodes (electrodes 37 in the display area and dummy electrodes 38 in the non-display area).
  • the display substrate further includes a plurality of virtual data lines 36 located in the non-display area 20 and extending along the first direction a, the plurality of virtual data lines 36 and the plurality of virtual power lines 32 electrical connections.
  • the plurality of virtual data lines 36 and the plurality of virtual power lines 32 are electrically connected in a one-to-one correspondence.
  • the virtual power line 32 is electrically connected to the closest virtual data line 36.
  • the virtual power line 32 increases the capacitance overlap area with VSS when forming a capacitance with VSS, and increases the capacitance of the capacitance, thereby increasing The stability of the power cord 31 is improved.
  • one virtual data line 36 and one virtual power line 32 are electrically connected through a plurality of connection points C, and the plurality of connection points C are connected to a plurality of virtual sub-pixels 201 of a column of virtual sub-pixels 201.
  • the dashed frame 201 corresponds to the virtual sub-pixel 201
  • the virtual sub-pixel 201 corresponds to the connection point C.
  • the dummy electrode 38 is electrically connected to the power line 31, which not only further increases the capacitance overlap area, but also improves the stability of the power line 31.
  • the display substrate provided by the embodiment of the present disclosure may be an OLED display substrate.
  • at least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element, the pixel circuit is located between the base substrate and the light-emitting element; the light-emitting element includes a first electrode, an organic light-emitting layer, and a second electrode stacked in sequence, The second electrode is located on the side of the organic light-emitting layer facing the base substrate.
  • the second electrode may be an anode, and the first electrode may be a cathode.
  • the pixel circuit includes at least one thin film transistor.
  • the thin film transistor includes an active layer on a base substrate, a gate layer on the side of the active layer away from the base substrate, and a source and drain on the side of the gate layer away from the base substrate. Floor.
  • FIG. 6 is a cross-sectional view of an OLED display substrate provided by an embodiment of the present disclosure.
  • the cross-sectional view is a cross-sectional view in the direction of F-F' in FIG. 1.
  • the OLED display substrate includes a base substrate 100 and a buffer layer 200, an active layer 50, and a first gate stacked on the base substrate 100.
  • the aforementioned VSS line 41 is located in the aforementioned anode layer 40.
  • the base substrate 100 may be a glass substrate.
  • the active layer 50 may be a Low Temperature Poly-Silicon (LTPS) layer, and may also be referred to as a poly-si or P-si layer.
  • the buffer layer 200, the first gate insulating layer 60, the second gate insulating layer 80, and the interlayer insulating layer 110 may be insulating layers formed of one of silicon oxide, silicon nitride, and silicon oxynitride, or at least two of them. Kind of stacks formed.
  • the OLED display substrate may further include a protective layer (PVX) layer 160 located between the source drain layer 30 and the planarization layer 120, and located between the pixel defining layer 130 and the organic light emitting layer 140.
  • PVX protective layer
  • PS spacer
  • the encapsulation layer can be realized by a stack of the first inorganic encapsulation layer 181, the organic encapsulation layer 182, and the second inorganic encapsulation layer 183.
  • FIG. 8 is a schematic diagram showing the structure of the active layer 50 and the dummy active layer 50' according to an embodiment of the present disclosure.
  • the active layer 50 of the display area 10 and the virtual active layer 50' of the non-display area 20 have the same main structure. The only difference is that in the non-display area 20, the virtual active layer 50 may include a graphic block B.
  • FIG. 9 is a schematic diagram of the structure of the first gate layer 70 and the dummy first gate layer 70' according to an embodiment of the present disclosure.
  • the first gate layer 70 of the display area 10 may include a gate line 71, a gate 72, a first capacitor plate 73, a first signal line 74 and a second signal line 75.
  • the dummy first gate layer 70' of the non-display area 20 may include: a dummy gate line 71', a dummy gate 72', a dummy first capacitor plate 73', a dummy first signal line 74', and a dummy second signal line 75'.
  • the virtual gate line 71', the virtual gate 72', the virtual first capacitor plate 73' and the virtual second signal line 75' can all be connected together.
  • a row of virtual sub-pixels are connected together, and after being connected to the virtual power line, the overlap capacitance formed with VSS can be increased.
  • the virtual gate line 71' can also only be connected to the virtual first capacitor plate.
  • one of the dummy first signal line 74' and the dummy second signal line 75' is connected together, or with any two or three of them.
  • pixel circuits are usually 7T1C or 6T1C circuits with multiple thin film transistors (T) + capacitors.
  • T thin film transistors
  • 7T1C circuits in addition to providing GATE, VDD, DATA and other signals, it is also necessary to provide RESET ( For voltage signals such as reset), REF (reference), VINT (initial), EM (light emission control), the aforementioned first signal line 74 and second signal line 75 can be used to provide at least one of the aforementioned voltage signals.
  • the first signal line 74 is a RESET (reset) signal line
  • the second signal line 75 is an EM (emission control) signal line.
  • FIG. 10 is a schematic diagram showing the structure of the second gate layer 90 and the dummy second gate layer 90' according to an embodiment of the present disclosure.
  • the second gate layer 90 of the display area 10 and the dummy second gate layer 90' of the non-display area 20 have the same structure.
  • the second gate layer 90 includes a third signal line 91, a second capacitor plate 92 and a shielding layer 93.
  • the dummy second gate layer 90' includes a dummy third signal line 91', a dummy second capacitor plate 92' and a dummy shield layer 93'.
  • the first capacitor plate 73 and the second capacitor plate 92 together form a storage capacitor (English: Cst), and the storage capacitor may be a capacitor C in a circuit such as 7T1C.
  • the shielding layer 93 can be used to shield the active layer 50 to prevent leakage current, and form a capacitor with the active layer 50, which can be used to stabilize a certain thin film transistor in the 7T1C circuit.
  • the third signal line 91 can be used to provide voltage signals such as RESET, REF, and VINT.
  • the third signal line 91 is a VINT signal line.
  • the dummy sub-pixel includes a dummy first gate layer 70', a dummy active layer 50', and a dummy second gate layer 90'.
  • the dummy power line 32 is also connected to the dummy first gate layer 70' At least one of the dummy active layer 50' and the dummy second gate layer 90' is electrically connected, so that the overlap capacitance formed by the dummy power line 32 and the VSS can be increased.
  • FIG. 11 is a superimposed schematic diagram of a part of the film layer structure in a virtual sub-pixel in an OLED display substrate provided by an embodiment of the present disclosure. It mainly includes a dummy active layer 50', a dummy first gate layer 70', a dummy second gate layer 90', and a dummy source drain layer 30'.
  • the dummy power supply line 32 is electrically connected to the dummy first gate layer 70', the dummy active layer 50', and the dummy second gate layer 90'.
  • FIG. 12 is a schematic diagram showing the superposition of the dummy first gate layer 70' and the dummy source drain layer 30' according to an embodiment of the present disclosure. 11 and 12, the dummy power supply line 32' is electrically connected to the dummy first gate layer 70'.
  • a first via X1 is provided at the connection point C, and the dummy power line 32 is electrically connected to the dummy first gate layer 70 through the first via X1.
  • the dummy sub-pixel further includes a dummy first gate insulating layer, a dummy second gate insulating layer, and a dummy interlayer insulating layer.
  • the dummy first gate insulating layer is located between the dummy active layer 50' and the dummy first gate layer 70'.
  • the dummy second gate insulating layer is located between the dummy first gate layer 70' and the dummy second gate layer 90', and the dummy interlayer insulating layer is located between the dummy second gate layer 90' and the dummy power line 32' between.
  • the dummy first gate insulating layer is the same layer as the first gate insulating layer 60
  • the dummy second gate insulating layer is the same layer as the second gate insulating layer 80
  • the dummy interlayer insulating layer is the same layer as the interlayer insulating layer 110.
  • the dummy power line 32 is electrically connected to the dummy first signal line 74' of the dummy first gate layer 70' through the first via X1.
  • FIG. 13 is a superimposed schematic diagram of a virtual active layer 50' and a virtual source drain layer 30' provided by an embodiment of the present disclosure. 11 and 13, the dummy power line 32 is electrically connected to the dummy active layer 50'.
  • the dummy source and drain layer 30' of the display substrate includes a plurality of dummy electrodes 38, and the plurality of dummy electrodes 38 are electrically connected to the dummy power lines 32.
  • the dummy electrode 38 includes a first dummy electrode 38A, a second via X2 is provided at the first dummy electrode 38A, and the dummy power line 32 is electrically connected to the dummy active layer 50' through the second via X2.
  • the provision of the second via hole at the first dummy electrode 38A means that the dummy first gate insulating layer, the dummy second gate insulating layer and the dummy interlayer insulating layer are opened under the first dummy electrode 38A.
  • the second via hole can realize the electrical connection between the first dummy electrode 38A and the dummy active layer 50'.
  • the lowermost dummy electrode 38 is the aforementioned first dummy electrode 38A.
  • the first dummy electrode 38A may also be other dummy electrodes 38.
  • FIG. 14 is a superimposed schematic diagram of a dummy second gate layer 90' and a dummy source drain layer 30' provided by an embodiment of the present disclosure. 11 and 14, the dummy power line 32 is electrically connected to the dummy second gate layer 90'.
  • the dummy electrode 38 includes a second dummy electrode 38B, a third via X3 is provided at the second dummy electrode 38B, and the dummy power line 32 is electrically connected to the dummy second gate layer 90' through the third via X3.
  • the second dummy electrode 38B and the first dummy electrode 38A are different dummy electrodes.
  • the provision of a third via hole at the second dummy electrode 38B means that a third via hole is opened on the dummy interlayer insulating layer under the second dummy electrode 38B, and the third via hole can realize the second dummy electrode. 38B and the electrical connection of the dummy second gate layer 90'.
  • the dummy electrode adjacent to the first dummy electrode 38A is the second dummy electrode 38B.
  • the second dummy electrode 38B may also be another dummy electrode 38.
  • the dummy power line 32 is electrically connected to the dummy third signal line 91' of the dummy second gate layer 90' through the third via X3.
  • the present disclosure provides a display device, which includes a display substrate as shown in any one of the preceding drawings.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a capacitance is formed between the virtual power line and the common power line of the virtual sub-pixels in the non-display area.
  • the virtual power line in the non-display area is connected to the gate high-level signal. No contribution.
  • the capacitor can compensate for the jump of the power line of the display area and increase the stability of the power line of the display area. Therefore, This solution can improve the brightness stability of the display panel.

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Abstract

本公开提供了一种显示基板及显示装置，属于显示技术领域。显示基板包括：衬底基板，包括显示区和围绕所述显示区的非显示区；多个子像素，位于所述显示区；多条电源线，位于所述显示区且沿第一方向延伸，所述多条电源线与所述多个子像素电连接，且被配置为向所述多个子像素提供电源信号；多个虚拟子像素，沿所述第一方向位于所述显示区一侧的所述非显示区；多条虚拟电源线，位于所述非显示区且沿所述第一方向延伸，所述多条虚拟电源线与所述多个虚拟子像素位于所述显示区的同一侧；其中，所述多条电源线中的至少部分电源线和所述多条虚拟电源线中的至少部分虚拟电源线电连接。

Description

显示基板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示基板及显示装置。
背景技术
有源矩阵有机发光二极管(英文：Active Matrix Organic Light-Emitting Diode，简称：AMOLED)显示器与传统的液晶显示器(英文：Liquid Crystal Display，简称：LCD)相比，具有自发光、广色域、高对比度、轻薄等优点，使其广泛应用于手机、平板电脑等领域，另外也广泛应用于智能手表等柔性可穿戴领域。
实用新型内容
本公开实施例提供了一种显示基板及显示装置。
一方面，提供了一种显示基板，包括：
衬底基板，包括显示区和围绕所述显示区的非显示区；
多个子像素，位于所述显示区；
多条电源线，位于所述显示区且沿第一方向延伸，所述多条电源线与所述多个子像素电连接，且被配置为向所述多个子像素提供电源信号；
多个虚拟子像素，沿所述第一方向位于所述显示区一侧的所述非显示区；
多条虚拟电源线，位于所述非显示区且沿所述第一方向延伸，所述多条虚拟电源线与所述多个虚拟子像素位于所述显示区的同一侧；其中，所述多条电源线中的至少部分电源线和所述多条虚拟电源线中的至少部分虚拟电源线电连接。
可选地，所述多条电源线中的至少部分电源线和所述多条虚拟电源线中的至少部分虚拟电源线一一对应电连接。
可选地，所述显示基板还包括位于所述非显示区的至少一条第一电源连接线，所述至少一条第一电源连接线位于所述多条电源线和所述多条虚拟电源线之间且沿所述第一方向延伸，所述至少一条第一电源连接线电连接所述多条电 源线中的至少一条和所述多条虚拟电源线中的至少一条。
可选地，所述显示基板包括多条第一电源连接线，所述多条第一电源连接线一一对应连接所述多条电源线和所述多条虚拟电源线。
可选地，所述显示基板还包括沿第二方向延伸的至少一条第二电源连接线，所述第一方向与所述第二方向交叉，所述多条第一电源连接线和所述至少一条第二电源连接线至少部分交叠且电连接。
可选地，所述至少一条第二电源连接线的数量为一条，或，所述至少一条第二电源连接线的数量为多条，所述多条第二电源连接线相互平行。
可选地，所述显示基板包括一条所述第二电源连接线，且所述第二电源连接线在垂直于所述第二方向上的宽度范围为20微米～30微米。
可选地，所述第二电源连接线与所述第一电源连接线同层。
可选地，所述显示基板还包括多个图形块，所述多个图形块位于所述非显示区且间隔布置在所述显示区周围。
可选地，所述第一电源连接线和所述第二电源连接线在所述衬底基板上的正投影与所述图形块在所述衬底基板上的正投影不重叠。
可选地，所述显示基板还包括多条虚拟数据线，位于所述非显示区且沿所述第一方向延伸，所述多条虚拟数据线与所述多条虚拟电源线电连接。
可选地，所述多条虚拟数据线和所述多条虚拟电源线一一对应电连接。
可选地，一条所述虚拟数据线和一条所述虚拟电源线通过多个连接点电连接，所述多个连接点与所述多个虚拟子像素一一对应。
可选地，所述虚拟子像素还包括位于所述衬底基板上的虚拟有源层，位于所述虚拟有源层远离所述衬底基板一侧的虚拟第一栅极层，位于所述虚拟第一栅极层远离所述衬底基板一侧的虚拟第二栅极层，所述虚拟电源线位于所述虚拟第二栅极层远离所述衬底基板的一侧；
所述虚拟电源线与所述虚拟有源层、所述虚拟第一栅极层和所述虚拟第二栅极层中的至少一层电连接。
可选地，所述虚拟电源线分别与所述虚拟有源层、所述虚拟第一栅极层和所述虚拟第二栅极层电连接。
可选地，所述虚拟子像素还包括虚拟第一栅绝缘层、虚拟第二栅绝缘层和虚拟层间绝缘层，所述虚拟第一栅绝缘层位于所述虚拟有源层和所述虚拟第一栅极层之间，所述虚拟第二栅绝缘层位于所述虚拟第一栅极层和所述虚拟第二 栅极层之间，所述虚拟层间绝缘层位于所述虚拟第二栅极层和所述虚拟电源线之间。
可选地，所述虚拟子像素还包括贯穿所述虚拟第二栅绝缘层和所述虚拟层间绝缘层的第一过孔，所述虚拟电源线通过所述第一过孔与所述虚拟第一栅极层电连接。
可选地，所述虚拟子像素还包括贯穿所述虚拟第一栅绝缘层、所述虚拟第二栅绝缘层和所述虚拟层间绝缘层的第二过孔，所述虚拟电源线通过所述第二过孔与所述虚拟有源层电连接。
可选地，所述虚拟子像素还包括贯穿所述虚拟层间绝缘层的第三过孔，所述虚拟电源线通过所述第三过孔与所述虚拟第二栅极层电连接。
可选地，所述虚拟子像素还包括第一虚拟电极，所述第一虚拟电极与所述虚拟电源线电连接，所述第一虚拟电极通过所述第二过孔与所述虚拟有源层电连接。
可选地，所述虚拟子像素还包括第二虚拟电极，所述第二虚拟电极与所述虚拟电源线电连接，所述第二虚拟电极通过所述第三过孔与所述虚拟第二栅极层电连接。
可选地，所述多个子像素包括位于所述衬底基板上有源层，位于所述有源层远离所述衬底基板一侧的栅极层、位于所述栅极层远离所述衬底基板一侧的源漏极层；
所述多条电源线、所述多条虚拟电源线、所述第一电源连接线和所述第二电源连接线与所述源漏极层位于同一层。
可选地，所述多个子像素包括位于所述衬底基板上有源层，位于所述有源层远离所述衬底基板一侧的栅极层、位于所述栅极层远离所述衬底基板一侧的源漏极层；
所述多个图形块与所述有源层位于同一层。
可选地，所述显示基板还包括电源总线，所述电源总线位于所述显示区远离所述多个虚拟子像素的一侧的所述非显示区，所述电源总线与所述多条电源线电连接。
可选地，所述显示基板还包括多条数据线，所述多条数据线位于所述显示区且沿所述第一方向延伸，所述多条数据线与所述多条电源线相互绝缘。
另一方面，提供了一种显示装置，所述显示装置包括如前任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示基板的结构示意图；
图2是本公开实施例提供的一种显示基板的结构示意图；
图3是本公开实施例提供的显示基板的局部结构示意图；
图4是本公开实施例提供的另一显示基板的结构示意图；
图5是本公开实施例提供的SD层和虚拟SD层的结构示意图；
图6是本公开实施例提供的一种OLED显示基板的截面图；
图7是本公开实施例提供的OLED显示基板中部分膜层结构的叠加示意图；
图8是本公开实施例示出的有源层和虚拟有源层的结构示意图；
图9是本公开实施例示出的第一栅极层和虚拟第一栅极层的结构示意图；
图10是本公开实施例示出的第二栅极层和虚拟第二栅极层的结构示意图；
图11是本公开实施例提供的OLED显示基板中虚拟子像素中部分膜层结构的叠加示意图；
图12是本公开实施例提供的虚拟第一栅极层和虚拟源漏极层的叠加示意图；
图13是本公开实施例提供的虚拟有源层和虚拟源漏极层的叠加示意图；
图14是本公开实施例提供的虚拟第二栅极层和虚拟源漏极层的叠加示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
OLED显示面板按驱动方式可分为无源矩阵驱动有机发光二极管(英文：Passive Matrix Driving OLED，简称：PMOLED)和AMOLED两种。本申请提 供的方案主要应用于AMOLED显示面板，例如可以是柔性AMOLED显示面板。
OLED为电流驱动，OLED显示亮度与驱动电流成正比，由驱动电流公式I＝K*(VDD-Vdata-|Vth|) 2(K是晶体管的导电因子，Vth是晶体管的阈值电压)可知：当数据电压Vdata变化较小时，驱动电流I随着电源电压VDD的变化而变化，所以OLED显示亮度受到电源电压VDD的影响。
在正常显示过程中，显示区(AA区)内其他信号的电压跳变会影响VDD信号，使其产生微小扰动。VDD信号的扰动造成OLED显示亮度的变化，影响显示效果。
图1是本公开实施例提供的一种显示基板的结构示意图。参见图1，所述显示基板包括：
衬底基板100，包括显示区10以及围绕所述显示区10的非显示区20；
多个子像素101，位于显示区10；
多个虚拟子像素(英文：Dummy Pixel)201，沿第一方向a位于所述显示区10一侧的所述非显示区20。也即多个虚拟子像素201和显示区10沿第一方向依次排布。
图2是本公开实施例提供的一种显示基板的结构示意图。参见图2，所述显示基板还包括：
多条电源线(VDD线)31，位于所述显示区10且沿第一方向a延伸，所述多条电源线31与所述多个子像素101电连接，且被配置为向所述多个子像素101提供电源信号；
多条虚拟电源线32，位于所述非显示区20且沿所述第一方向a延伸，所述多条虚拟电源线32与所述多个虚拟子像素201位于所述显示区10的同一侧；
其中，所述多条电源线31中的至少部分电源线31和所述多条虚拟电源线32中的至少部分虚拟电源线32电连接。
在非显示区20的虚拟子像素的虚拟电源线和公共电源线(VSS线)41间会形成电容，在相关技术中，非显示区20的虚拟电源线接入栅极高电平(VGH)信号，由于虚拟电源线和电源线相互绝缘，这种方案不会影响电源线的信号，对显示区的显示没有贡献。在本公开实施例中，通过连接显示区10的电源线(例如正极电源线(VDD))和非显示区20的虚拟电源线，使得该电容可以对显示区10的电源线的跳变进行补偿，增加显示区10的电源线的稳定性，因此该方 案可以提高显示面板的亮度稳定性。
这里，多条虚拟电源线32与多个虚拟子像素201至少部分交叠。也即虚拟电源线32沿第一方向布置时，经过虚拟子像素201所在区域，以及相邻虚拟子像素201之间的区域，从而使得每条虚拟电源线32的部分与虚拟子像素201交叠。这种设计，使得非显示区20内的虚拟电源线32与VSS线间形成较大的交叠电容，VSS线输出稳定直流信号，使其在作为电容的一端时，可以有效抑制电容另一端所连接的电源线的电压扰动，提高电源线的电压稳定性。
示例性地，前述电源线31可以位于显示基板的源漏极(SD)层，虚拟电源线32位于显示基板的虚拟源漏极层，公共电源线(VSS)41可以是由源漏极层(和/或虚拟源漏极层)和显示基板的阳极层(和/或虚拟阳极层)构成的双层走线。在其他实施例中，公共电源线41也可以是阳极层(和/或虚拟阳极层)形成的单层走线。这里，源漏极层和虚拟源漏极层同层布置，虚拟源漏极层位于非显示区，源漏极层位于显示区，阳极层和虚拟阳极层也是相同布置情况，后续出现X层和虚拟X层均是基于上述规则布置。
如图1和图2所示，显示基板中部为显示区10，显示基板除显示区10以外的区域为非显示区，也称外围区。如图1和图2所示，布置虚拟子像素的部分非显示区在显示区10的上方，也即图2中标号M所示的区域。
在本公开实施例中，非显示区20和显示区10均包括子像素，显示区10的子像素为正常子像素，可以发光；非显示区20的子像素为虚拟子像素，虚拟子像素不发光。设置虚拟子像素的目的是，保证显示区中图形化的均一性，从而保证显示区的显示效果。正是由于虚拟子像素的不用于发光，因此在相关技术中，非显示区的虚拟电源线和正常区域的电源线之间是断开的，而本申请将其连接起来解决了电源线的信号稳定性问题。而且，虽然连接了电源线，但由于虚拟子像素依然无法获得其他信号，如数据信号等，因此虚拟子像素依然不会发光。
在本公开实施例中，所述多条电源线31中的至少部分电源线31和所述多条虚拟电源线32中的至少部分虚拟电源线32一一对应电连接。也即，并非所有电源线31均连接到虚拟电源线32，而且每根电源线31仅与一根虚拟电源线32连接，每根虚拟电源线32也仅与一根电源线31连接。下面结合附图2对电源线31和虚拟电源线32的连接方式进行说明。
如图2所示，该显示基板还包括位于所述非显示区20的至少一条第一电源 连接线33，所述至少一条第一电源连接线33位于所述多条电源线31和所述多条虚拟电源线32之间且沿所述第一方向a延伸，所述至少一条第一电源连接线33电连接所述多条电源线31中的至少一条和所述多条虚拟电源线32中的至少一条。
示例性地，所述显示基板包括多条第一电源连接线33，所述多条第一电源连接线33一一对应连接所述多条电源线31和所述多条虚拟电源线32。
示例性地，第一电源连接线33可以与电源线31同层布置。其中，同层可以是指在一次构图工艺中形成，或者可以是指位于同一层的同一侧，或者可以是指靠近衬底基板的表面均与同一层接触等。
如图2所示，该显示基板还包括电源总线300，位于所述显示区10另一侧的所述非显示区20，也即该电源总线300与前述虚拟子像素201布置在显示区10的相对两侧，所述电源总线300与所述多条电源线31电连接。
在显示区10下方的非显示区20，电源线31通过电源总线300连接到柔性电路板(英文：Flexible Printed Circuit，简称：FPC)(图中标号A)上，通过FPC为该显示基板的电源线31提供信号驱动。当然，从图2可以看出FPC除了为显示基板提供VDD信号外，还为显示基板提供VSS信号及其他信号。
示例性地，电源总线300可以与电源线31同层布置。
这里，由于虚拟子像素201和FPC分布在显示区10相对的两侧，因此，虚拟子像素201所在的一端也可以称为显示基板的远(离)FPC端。通常，显示区10中远离FPC端的子像素的VDD信号稳定性差，通过本申请的方案提高了显示区10中远离FPC端的子像素的显示稳定性。
如图2所示，该显示基板还包括栅线71，栅线71与电源线31位于不同层，且栅线71与电源线31交叉布置，例如，垂直布置。
在面板工作过程中，可以向栅线71写入栅线信号。
图3是本公开实施例提供的显示基板的局部结构示意图。参见图3，该部分可以是显示基板左上角的结构示意图。通常，具有圆角的显示基板会设计虚拟子像素，在具有圆角的显示基板中，除了会利用虚拟子像素消除图形化不均一问题外，还会保留非显示区20的多个图形块，该多个图形块间隔设置在显示区周围。例如在虚拟有源层、虚拟源漏极层等，如图3中的标号B即为虚拟有源层的图形块。这里，图形块B的作用和非显示区20中虚拟子像素21一样，都是通过在边缘部分形成图案，保证显示区10内部正常像素11的图案的均一性。 因为在显示基板存在圆角等情况下，边缘部分刻蚀的图案可能存在偏差，通过设计虚拟子像素和图形块B，相当于把边缘外移，然后牺牲掉边缘，保证内部也即显示区的图形均一性。
如图3所示，位于显示区10的中部区域10A中的电源线通过第一电源连接线33与非显示区20中的虚拟电源线连接，位于显示区10的边缘区域10B中的电源线不与非显示区20中的虚拟电源线连接；在所述第二方向b上，显示区10的边缘区域10B位于显示区10的中部区域10A和显示基板的边缘之间，第二方向b与第一方向a交叉，例如相互垂直。
如图3所示，第一电源连接线33在衬底基板上的正投影与所述图形块B在所述衬底基板上的正投影不重叠。
在该实现方式中，这样保证了边缘部分可以形成前述图形块B，保证显示区的图形均一性。
如图3所示，所述显示基板还包括沿第二方向b延伸的至少一条第二电源连接线34，所述多条第一电源连接线33和所述至少一条第二电源连接线34至少部分交叠且电连接。第二电源连接线34位于非显示区20。
如图3所示，第二电源连接线34在衬底基板上的正投影与所述图形块B在所述衬底基板上的正投影不重叠。
在该实现方式中，通过设置第二电源连接线34，一方面可有效增加VDD线和VSS线的交叠面积，也即增加电容交叠面积，提高VDD稳定性；另一方面，显示基板的电源线通过第二电源连接线34交叉相连，将各列子像素的电源线连接在一起，交织成网状，与VSS形成电容，从而提高了各个部分的电源线的信号均一性，因此该方案可以提高显示面板的亮度均一性。
在本公开实施例中，所述第二电源连接线34的数量可以为一条或多条。如图3所示即为一条第二电源连接线34，这样便于设计和制作。
如图3所示，所述第二电源连接线34的数量为一条，且所述第二电源连接线34在第一方向a上的宽度可以为距离最近的子像素和虚拟子像素之间距离W的1/3～1/2。这样设计第二电源连接线34的宽度，一方面保证电容交叠面积尽可能大，另一方面，避免第二电源连接线34与子像素距离过近，影响子像素的工作。
示例性地，所述第二电源连接线34的宽度范围可以为20～30微米。
在本公开实施例中，所述第二电源连接线34与所述电源线31同层设置， 第二电源连接线34位于虚拟源漏极(英文：Source Drain，简称：SD)层，这样可以一起制作第二电源连接线34与电源线31，无需额外工艺，即可实现第二电源连接线34和电源线31的连接。
图4是本公开实施例提供的另一显示基板的结构示意图。参见图4，在该显示基板中，第二电源连接线34的数量为多条，多条第二电源连接线34间隔平行设置。
图5是本公开实施例提供的SD层和虚拟SD层的结构示意图。参见图5，显示区为SD层30，非显示区为虚拟SD层30’。显示区10的电源线31与非显示区20对应的虚拟电源线32连接，形成一条从显示区10延伸到非显示区20的电源线。这里所说的对应指的是位于同一列像素中的电源线31和虚拟电源线32。
如图5所示，位于非显示区20中用于连接电源线31和虚拟电源线32的第一电源连接线33的宽度，大于所连接的电源线31和虚拟电源线32的宽度，这里的宽度是指在第二方向b上宽度。
在SD层和虚拟SD层，除了电源线(电源线31和虚拟电源线32)和电源连接线(第一电源连接线33和第二电源连接线34)外，还包括数据线(显示区的数据线35、非显示区的虚拟数据线36)以及电极(显示区的电极37和非显示区的虚拟电极38)。
如图5所示，显示基板还包括多条虚拟数据线36，位于所述非显示区20且沿所述第一方向a延伸，所述多条虚拟数据线36与所述多条虚拟电源线32电连接。
如图5所示，所述多条虚拟数据线36和所述多条虚拟电源线32一一对应电连接。示例性地，所述虚拟电源线32与距离最近的虚拟数据线36电连接。
在该实现方式中，通过将虚拟电源线32和虚拟数据线36连起来，使得虚拟电源线32在和VSS形成电容时，增加了与VSS的电容交叠面积，增大了电容容量，从而提高了电源线31的稳定性。
如图5所示，一条所述虚拟数据线36和一条所述虚拟电源线32通过多个连接点C电连接，所述多个连接点C与一列虚拟子像素201的多个虚拟子像素201一一对应。如图5所示，虚线框201对应虚拟子像素201，虚拟子像素201对应连接点C。
如图5所示，非显示区20内，虚拟电极38与电源线31电连接，这样不仅 进一步增加电容交叠面积，提高电源线31的稳定性。
在SD层中包括电源线31和数据线35，而前述栅线71位于其他层中，例如位于第一栅极层中。
本公开实施例提供的显示基板可以为OLED显示基板。在OLED显示基板中，多个子像素中至少一个包括像素电路和发光元件，像素电路位于衬底基板和发光元件之间；发光元件包括依次层叠设置的第一电极、有机发光层以及第二电极，第二电极位于有机发光层面向衬底基板的一侧。其中，第二电极可以为阳极，第一电极可以为阴极。像素电路包括至少一个薄膜晶体管，薄膜晶体管包括位于衬底基板上的有源层，位于有源层远离衬底基板一侧的栅极层、位于栅极层远离衬底基板一侧的源漏极层。
下面结合附图6对OLED显示基板的结构进行进一步地说明。
图6是本公开实施例提供的一种OLED显示基板的截面图。该截面图为图1中F-F’方向的截面图，参见图6，OLED显示基板包括衬底基板100以及层叠设置在衬底基板100上的缓冲层200、有源层50、第一栅极绝缘(英文：Gate Insulator，简称：GI)层60、第一栅极(英文：Gate)层70、第二栅极绝缘层80、第二栅极层90、层间绝缘层110、源漏极层30、平坦化层(英文：Planarization，简称：PLN)120、阳极层40、像素界定层(英文：Pixel Definition Layer，简称：PDL)130、有机发光层140和阴极层150。
在本公开实施例中，前述VSS线41位于上述阳极层40中。
在该OLED显示基板中，第二栅极绝缘层80位于第一栅极层70与第二栅极层90之间，通过第二栅极绝缘层80将第二栅极层90和第一栅极层70隔开，保证第二栅极层90和第一栅极层70之间相互隔开能够独立传输信号。层间绝缘层110位于第二栅极层90和源漏极层30之间，保证第二栅极层90和源漏极层30之间够独立传输信号。源漏极层30和阳极层40之间设置有平坦化层120，保证源漏极层30能够独立传输信号。
示例性地，衬底基板100可以为玻璃基板。有源层50可以为低温多晶硅(Low Temperature Poly-Silicon，LTPS)层，也可以称为poly-si或P-si层。缓冲层200、第一栅极绝缘层60、第二栅极绝缘层80、层间绝缘层110可以为氧化硅、氮化硅、氮氧化硅中的一种形成的绝缘层，或者其中至少两种形成的叠层。平坦化层120可以为树脂层，平坦化层也可以为氧化硅、氮化硅、氮氧化硅中的一种形成的平坦化层，或者其中至少两种形成的叠层。第一栅极层70、第二栅极层 90、源漏极层30可以为金属层或氧化铟锡层。阳极层40可以为金属层或氧化铟锡(英文：Indium tin oxide，简称：ITO)。阴极层150可以为氧化铟锡层或镁银合金。有机发光层140可以包括层叠设置的空穴传输层、发光层和电子传输层。
可选地，参见图6，该OLED显示基板还可以包括位于源漏极层30和平坦化层120之间的保护层(PVX)层160，位于像素界定层130和有机发光层140之间的隔垫物(PS)层170，以及覆盖在阴极层150上的封装层。其中封装层可以采用第一无机封装层181、有机封装层182和第二无机封装层183的叠层实现。
图7是本公开实施例提供的OLED显示基板中部分膜层结构的叠加示意图。参见图7，在显示区主要包括有源层50、第一栅极层70、第二栅极层90和源漏极层30。在非显示区主要包括虚拟有源层50’、虚拟第一栅极层70’、虚拟第二栅极层90’和虚拟源漏极层30’。下面结合图8-图10对图7中的有源层50(虚拟有源层50’)、第一栅极层70(虚拟第一栅极层70’)、第二栅极层90(虚拟第二栅极层90’)的结构进行说明。
图8是本公开实施例示出的有源层50和虚拟有源层50’的结构示意图。参见图8，显示区10的有源层50和非显示区20的虚拟有源层50’主体结构相同，不同仅在于，在非显示区20，虚拟有源层50可以包括图形块B。
图9是本公开实施例示出的第一栅极层70和虚拟第一栅极层70’的结构示意图。参见图9，显示区10的第一栅极层70可以包括：栅线71、栅极72、第一电容极板73、第一信号线74和第二信号线75。非显示区20的虚拟第一栅极层70’可以包括：虚拟栅线71’、虚拟栅极72’、虚拟第一电容极板73’、虚拟第一信号线74’和虚拟第二信号线75’。
其中，在显示区10内，在同一行像素中，仅栅线71和栅极72连接。而在非显示区20内，在同一行像素中，虚拟栅线71’、虚拟栅极72’、虚拟第一电容极板73’和虚拟第二信号线75’均可以连在一起，这样可以使得一行虚拟子像素连接在一起，在与虚拟电源线连接后，能够增大和VSS形成的交叠电容。当然，除了图9所示的连接方式外，在其他实现方式中，除了虚拟栅线71’和虚拟栅极72’连接在一起外，虚拟栅线71’也可以只与虚拟第一电容极板73’、虚拟第一信号线74’和虚拟第二信号线75’中的一个连接在一起，或者与其中任意两个或三个连接在一起。
在OLED显示基板中，像素电路通常为7T1C或者6T1C等具有多个薄膜晶 体管(T)+电容的电路，在7T1C等电路中，除了需要提供GATE、VDD、DATA等信号外，还需要提供RESET(重置)、REF(参考)、VINT(初始)、EM(发光控制)等电压信号，前述第一信号线74和第二信号线75即可用于提供上述电压信号中的至少一个。例如第一信号线74为RESET(重置)信号线，第二信号线75为EM(发光控制)信号线。
图10是本公开实施例示出的第二栅极层90和虚拟第二栅极层90’的结构示意图。参见图10，显示区10的第二栅极层90和非显示区20的虚拟第二栅极层90’结构相同。第二栅极层90包括第三信号线91、第二电容极板92和屏蔽层93。虚拟第二栅极层90’包括虚拟第三信号线91’、虚拟第二电容极板92’和虚拟屏蔽层93’。其中，第一电容极板73和第二电容极板92一起组成存储电容(英文：Cst)，该存储电容可以为7T1C等电路中的电容C。屏蔽层93可以用于遮挡有源层50，防止漏电流，并和有源层50间形成电容，该电容可以用于稳定7T1C电路中的某一薄膜晶体管。第三信号线91可以用来提供RESET、REF、VINT等电压信号。例如第三信号线91为VINT信号线。
在本公开实施例中，虚拟子像素包括虚拟第一栅极层70’、虚拟有源层50’和虚拟第二栅极层90’，虚拟电源线32还与虚拟第一栅极层70’、虚拟有源层50’和虚拟第二栅极层90’中的至少一层电连接，这样可以增大虚拟电源线32和VSS形成的交叠电容。
图11是本公开实施例提供的OLED显示基板中虚拟子像素中部分膜层结构的叠加示意图。其中主要包括虚拟有源层50’、虚拟第一栅极层70’、虚拟第二栅极层90’和虚拟源漏极层30’。在图11所示的结构中，虚拟电源线32与虚拟第一栅极层70’、虚拟有源层50’和虚拟第二栅极层90’均电连接。
图12是本公开实施例提供的虚拟第一栅极层70’和虚拟源漏极层30’的叠加示意图。参见图11和图12，虚拟电源线32’与虚拟第一栅极层70’电连接。
示例性地，连接点C处设置有第一过孔X1，虚拟电源线32通过第一过孔X1与虚拟第一栅极层70电连接。
例如，虚拟子像素还包括虚拟第一栅绝缘层、虚拟第二栅绝缘层和虚拟层间绝缘层，虚拟第一栅绝缘层位于虚拟有源层50’和虚拟第一栅极层70’之间，虚拟第二栅绝缘层位于虚拟第一栅极层70’和虚拟第二栅极层90’之间，虚拟层间绝缘层位于虚拟第二栅极层90’和虚拟电源线32’之间。其中，虚拟第一 栅绝缘层与第一栅极绝缘层60同层，虚拟第二栅绝缘层和第二栅极绝缘层80同层，虚拟层间绝缘层与层间绝缘层110同层。
这里，在连接点C处设置有第一过孔是指，在连接点C下方的虚拟第二栅极绝缘层和虚拟层间绝缘层上开设有第一过孔，该第一过孔可以实现连接点C和虚拟第一栅极层70’的电连接。
如图12所示，虚拟电源线32通过第一过孔X1与虚拟第一栅极层70’的虚拟第一信号线74’电连接。
图13是本公开实施例提供的虚拟有源层50’和虚拟源漏极层30’的叠加示意图。参见图11和图13，虚拟电源线32与虚拟有源层50’电连接。
显示基板的虚拟源漏极层30’包括多个虚拟电极38，多个虚拟电极38与所述虚拟电源线32电连接。
示例性地，虚拟电极38包括第一虚拟电极38A，第一虚拟电极38A处设置有第二过孔X2，虚拟电源线32通过第二过孔X2与虚拟有源层50’电连接。这里，在第一虚拟电极38A处设置有第二过孔是指，在第一虚拟电极38A下方的虚拟第一栅极绝缘层、虚拟第二栅极绝缘层和虚拟层间绝缘层上开设有第二过孔，该第二过孔可以实现第一虚拟电极38A和虚拟有源层50’的电连接。
如图13所示，最下方的虚拟电极38为前述第一虚拟电极38A。在其他实施例中，第一虚拟电极38A也可以是其他虚拟电极38。
图14是本公开实施例提供的虚拟第二栅极层90’和虚拟源漏极层30’的叠加示意图。参见图11和图14，虚拟电源线32与虚拟第二栅极层90’电连接。
示例性地，虚拟电极38包括第二虚拟电极38B，第二虚拟电极38B处设置有第三过孔X3，虚拟电源线32通过第三过孔X3与虚拟第二栅极层90’电连接。第二虚拟电极38B与第一虚拟电极38A为不同的虚拟电极。这里，在第二虚拟电极38B处设置有第三过孔是指，在第二虚拟电极38B下方的虚拟层间绝缘层上开设有第三过孔，该第三过孔可以实现第二虚拟电极38B和虚拟第二栅极层90’的电连接。
如图14所示，与第一虚拟电极38A相邻的虚拟电极为第二虚拟电极38B。在其他实施例中，第二虚拟电极38B也可以是其他虚拟电极38。
如图14所示，虚拟电源线32通过第三过孔X3与虚拟第二栅极层90’的虚拟第三信号线91’电连接。
本公开提供了一种显示装置，所述显示装置包括如前任一幅附图所示的显示基板。
在具体实施时，本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在非显示区的虚拟子像素的虚拟电源线和公共电源线间会形成电容，在相关技术中，非显示区的虚拟电源线接入栅极高电平信号，这种方案对显示区的显示没有贡献。在本公开实施例中，通过连接显示区的电源线和非显示区的虚拟电源线，使得该电容可以对显示区的电源线的跳变进行补偿，增加显示区的电源线的稳定性，因此该方案可以提高显示面板的亮度稳定性。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (26)

  1. 一种显示基板，包括：
    衬底基板，包括显示区和围绕所述显示区的非显示区；
    多个子像素，位于所述显示区；
    多条电源线，位于所述显示区且沿第一方向延伸，所述多条电源线与所述多个子像素电连接，且被配置为向所述多个子像素提供电源信号；
    多个虚拟子像素，沿所述第一方向位于所述显示区一侧的所述非显示区；
    多条虚拟电源线，位于所述非显示区且沿所述第一方向延伸，所述多条虚拟电源线与所述多个虚拟子像素位于所述显示区的同一侧；其中，所述多条电源线中的至少部分电源线和所述多条虚拟电源线中的至少部分虚拟电源线电连接。
  2. 根据权利要求1所述的显示基板，其中，所述多条电源线中的至少部分电源线和所述多条虚拟电源线中的至少部分虚拟电源线一一对应电连接。
  3. 根据权利要求1或2所述的显示基板，其中，所述显示基板还包括位于所述非显示区的至少一条第一电源连接线，所述至少一条第一电源连接线位于所述多条电源线和所述多条虚拟电源线之间且沿所述第一方向延伸，所述至少一条第一电源连接线电连接所述多条电源线中的至少一条和所述多条虚拟电源线中的至少一条。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板包括多条第一电源连接线，所述多条第一电源连接线一一对应连接所述多条电源线和所述多条虚拟电源线。
  5. 根据权利要求3或4所述的显示基板，其中，所述显示基板还包括沿第二方向延伸的至少一条第二电源连接线，所述第一方向与所述第二方向交叉，所述多条第一电源连接线和所述至少一条第二电源连接线至少部分交叠且电连接。
  6. 根据权利要求5所述的显示基板，其中，所述至少一条第二电源连接线的数量为一条，或，所述至少一条第二电源连接线的数量为多条，所述多条第二电源连接线相互平行。
  7. 根据权利要求6所述的显示基板，其中，所述显示基板包括一条所述第二电源连接线，且所述第二电源连接线在垂直于所述第二方向上的宽度范围为 20微米～30微米。
  8. 根据权利要求5至7任一项所述的显示基板，其中，所述第二电源连接线与所述第一电源连接线同层。
  9. 根据权利要求5至8任一项所述的显示基板，其中，所述显示基板还包括多个图形块，所述多个图形块位于所述非显示区且间隔布置在所述显示区周围。
  10. 根据权利要求9所述的显示基板，其中，所述第一电源连接线和所述第二电源连接线在所述衬底基板上的正投影与所述图形块在所述衬底基板上的正投影不重叠。
  11. 根据权利要求1至10任一项所述的显示基板，其中，所述显示基板还包括多条虚拟数据线，位于所述非显示区且沿所述第一方向延伸，所述多条虚拟数据线与所述多条虚拟电源线电连接。
  12. 根据权利要求11所述的显示基板，其中，所述多条虚拟数据线和所述多条虚拟电源线一一对应电连接。
  13. 根据权利要求12所述的显示基板，其中，一条所述虚拟数据线和一条所述虚拟电源线通过多个连接点电连接，所述多个连接点与所述多个虚拟子像素一一对应。
  14. 根据权利要求13所述的显示基板，其中，所述虚拟子像素还包括位于所述衬底基板上的虚拟有源层，位于所述虚拟有源层远离所述衬底基板一侧的虚拟第一栅极层，位于所述虚拟第一栅极层远离所述衬底基板一侧的虚拟第二栅极层，所述虚拟电源线位于所述虚拟第二栅极层远离所述衬底基板的一侧；
    所述虚拟电源线与所述虚拟有源层、所述虚拟第一栅极层和所述虚拟第二栅极层中的至少一层电连接。
  15. 根据权利要求14所述的显示基板，其中，所述虚拟电源线分别与所述虚拟有源层、所述虚拟第一栅极层和所述虚拟第二栅极层电连接。
  16. 根据权利要求14或15所述的显示基板，其中，所述虚拟子像素还包括虚拟第一栅绝缘层、虚拟第二栅绝缘层和虚拟层间绝缘层，所述虚拟第一栅绝缘层位于所述虚拟有源层和所述虚拟第一栅极层之间，所述虚拟第二栅绝缘层位于所述虚拟第一栅极层和所述虚拟第二栅极层之间，所述虚拟层间绝缘层位于所述虚拟第二栅极层和所述虚拟电源线之间。
  17. 根据权利要求16所述的显示基板，其中，所述虚拟子像素还包括贯穿所述虚拟第二栅绝缘层和所述虚拟层间绝缘层的第一过孔，所述虚拟电源线通过所述第一过孔与所述虚拟第一栅极层电连接。
  18. 根据权利要求16所述的显示基板，其中，所述虚拟子像素还包括贯穿所述虚拟第一栅绝缘层、所述虚拟第二栅绝缘层和所述虚拟层间绝缘层的第二过孔，所述虚拟电源线通过所述第二过孔与所述虚拟有源层电连接。
  19. 根据权利要求16所述的显示基板，其中，所述虚拟子像素还包括贯穿所述虚拟层间绝缘层的第三过孔，所述虚拟电源线通过所述第三过孔与所述虚拟第二栅极层电连接。
  20. 根据权利要求18所述的显示基板，其中，所述虚拟子像素还包括第一虚拟电极，所述第一虚拟电极与所述虚拟电源线电连接，所述第一虚拟电极通过所述第二过孔与所述虚拟有源层电连接。
  21. 根据权利要求19所述的显示基板，其中，所述虚拟子像素还包括第二虚拟电极，所述第二虚拟电极与所述虚拟电源线电连接，所述第二虚拟电极通过所述第三过孔与所述虚拟第二栅极层电连接。
  22. 根据权利要求5所述的显示基板，其中，所述多个子像素包括位于所述衬底基板上有源层，位于所述有源层远离所述衬底基板一侧的栅极层、位于所述栅极层远离所述衬底基板一侧的源漏极层；
    所述多条电源线、所述多条虚拟电源线、所述第一电源连接线和所述第二电源连接线与所述源漏极层位于同一层。
  23. 根据权利要求9或10所述的显示基板，其中，所述多个子像素包括位于所述衬底基板上有源层，位于所述有源层远离所述衬底基板一侧的栅极层、位于所述栅极层远离所述衬底基板一侧的源漏极层；
    所述多个图形块与所述有源层位于同一层。
  24. 根据权利要求1至23任一项所述的显示基板，其中，所述显示基板还包括电源总线，所述电源总线位于所述显示区远离所述多个虚拟子像素的一侧的所述非显示区，所述电源总线与所述多条电源线电连接。
  25. 根据权利要求1至24任一项所述的显示基板，其中，所述显示基板还包括多条数据线，所述多条数据线位于所述显示区且沿所述第一方向延伸，所述多条数据线与所述多条电源线相互绝缘。
  26. 一种显示装置，包括如权利要求1至25任一项所述的显示基板。
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WO2021207930A1 (zh) 2021-10-21

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