WO2019037529A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2019037529A1
WO2019037529A1 PCT/CN2018/091951 CN2018091951W WO2019037529A1 WO 2019037529 A1 WO2019037529 A1 WO 2019037529A1 CN 2018091951 W CN2018091951 W CN 2018091951W WO 2019037529 A1 WO2019037529 A1 WO 2019037529A1
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WIPO (PCT)
Prior art keywords
line
lead
array substrate
fan
disposed
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PCT/CN2018/091951
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English (en)
French (fr)
Inventor
龙春平
马永达
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18847741.8A priority Critical patent/EP3674788A4/en
Priority to US16/336,633 priority patent/US11454851B2/en
Publication of WO2019037529A1 publication Critical patent/WO2019037529A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a display panel, and a display device.
  • the liquid crystal display screen generally comprises an active matrix array substrate, a color filter substrate and a liquid crystal layer.
  • the active matrix array substrate and the color filter substrate are assembled oppositely, and the liquid crystal layer is located between the active matrix array substrate and the color filter substrate, and the liquid crystal molecules of the liquid crystal layer can be adjusted by the active elements in the active matrix array substrate. , the beam intensity transmitted through the liquid crystal layer can be adjusted to display an image.
  • At least one embodiment of the present disclosure provides an array substrate having a display area and a non-display area disposed around the display area, and including: first signal lines and second signals disposed side by side in the display area a first fan-out line and a second fan-out line disposed side by side in the non-display area, and a first lead and a second lead extending from the non-display area to the display area.
  • the first lead is disposed between the first signal line and the first fan-out line and electrically connects the first signal line and the first fan-out line
  • the second lead is disposed at the first Between the second signal line and the second fan-out line and electrically connecting the second signal line and the second fan-out line; and the first lead and the second lead are disposed in different layers.
  • the first lead when the first lead and the first signal line are disposed in different layers, the first lead is realized by the first interlayer via and the first Electrical connection between the signal lines; when the first lead and the first fan-out line are disposed in different layers, the first lead is electrically connected to the first fan-out line through the second interlayer via Connecting; when the second lead and the second signal line are disposed in different layers, the second lead is electrically connected to the second signal line through the third interlayer via; When the second lead and the second fan-out line are disposed in different layers, the second lead is electrically connected to the second fan-out line through the fourth interlayer via.
  • the first lead includes two first straps and is located between the two first straps and connects the two first straps a first connection line electrically connected;
  • the second lead includes two second connection wires and a second portion between the two second connection wires and electrically connecting the two second connection wires a connecting line; the first connecting line and the second connecting line at least partially overlapping and insulated from each other in a direction perpendicular to the array substrate.
  • the first signal line, the second signal line, the first fan-out line, the second fan-out line, and the second lead are set in the same layer a first strap located at one end of the first lead is electrically connected to the first signal line through a first via, and a first strap located at the other end of the first lead passes through a second via
  • the first fan outlet is electrically connected.
  • the first lead is disposed in the same layer as the first fan-out line and the second fan-out line, and the first bonding line at one end of the first lead passes a third via is electrically connected to the first signal line; and the second lead is disposed in the same layer as the first signal line and the second signal line, and a second overlap is provided at one end of the second lead
  • the wire is electrically connected to the second fan-out line through the fourth via.
  • an extending direction of the first connecting line is parallel to an extending direction of the second connecting line; and a direction of the first connecting line is perpendicular to the first connection
  • the width in the direction in which the line extends is equal to the width of the second connecting line in a direction perpendicular to the extending direction of the second connecting line.
  • the first connection line and the second connection line completely overlap in a direction perpendicular to the array substrate.
  • an extending direction of the first bonding wire connected to the first signal line and an extending direction of the second bonding wire connected to the second signal line intersect; a direction in which the first bonding wire connected to the first signal line extends parallel to an extending direction of the first signal line; and a direction in which the second bonding wire connected to the second signal wire extends in parallel with The direction in which the second connecting line extends.
  • the array substrate further includes: between the first lead and the first fan-out line and electrically connecting the first lead and the first fan-out line a first compensation line connected, and a second compensation line between the second lead and the second fan-out line and electrically connecting the second lead and the second fan-out line; the first The compensation line is disposed in a different layer from the first lead, and the second compensation line and the second lead are disposed in different layers.
  • the first compensation line is electrically connected to the first signal line
  • the second compensation line is electrically connected to the second signal line
  • the first The compensation line is disposed in the same layer as the second lead
  • the second compensation line is disposed in the same layer as the first lead.
  • the first compensation line is electrically connected to the first lead through a fifth interlayer via; the second compensation line passes through a sixth interlayer via The second lead is electrically connected; the first compensation line and the second compensation line partially overlap in a direction perpendicular to the array substrate.
  • the first compensation line includes two first laps and is located between the two first laps and the two first laps a first connection portion electrically connected;
  • the second compensation line includes two second overlapping portions and between the two second overlapping portions and electrically connecting the two second overlapping portions a second connection portion; and the first connection portion and the second connection portion at least partially overlap and are insulated from each other in a direction perpendicular to the array substrate.
  • an initial projection interval of the first lap portion and the second lap of the second lead in a panel face of the array substrate is disposed at an orthographic projection interval of the first lap of the first lead within the panel face.
  • the first fan-out line and the second fan-out line are arranged side by side in a first direction; the first signal line and the second signal line are along the first One direction is arranged side by side; the first connection line of the first lead and the second connection line of the second lead extend in the second direction and are juxtaposed in a third direction; and the second direction and the first The directions intersect, the third direction being perpendicular to the second direction.
  • a width of the first connection line in the third direction is greater than a width of the first signal line in the first direction.
  • the first connection line and the second connection line are repeatedly arranged in the first direction, and the first connection line and the second connection The lines are alternately arranged in the first direction; and the spacing of the adjacent first connecting lines in the third direction is greater than the adjacent first connecting lines and the second signal lines in the a spacing in the first direction, a spacing of the adjacent second connecting lines in the third direction is greater than a spacing of the adjacent first connecting lines and the second signal lines in the first direction .
  • the array substrate further includes a data line and a gate line disposed in different layers, a gate insulating layer, and a lead insulating layer, the first signal line and the second signal a line is the data line; the first lead is disposed in the same layer as the gate line, the second lead is disposed in the same layer as the data line; and the lead insulating layer is in the same layer as the gate insulating layer And disposed between the first lead and the second lead in a direction perpendicular to the array substrate.
  • the display area includes a plurality of display pixels arranged in an array, each of the display pixels being electrically connected to at least one signal line.
  • At least one embodiment of the present disclosure also provides a display panel comprising any of the array substrates provided by at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a display device comprising any of the display panels provided by at least one embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an array substrate according to at least one embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another array substrate according to at least one embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of still another array substrate according to at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another array substrate according to at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6 is an exemplary block diagram of a display panel and a display device according to at least one embodiment of the present disclosure.
  • An active matrix array substrate includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel units electrically connected to the corresponding gate lines and the data lines; where the gate lines are arranged in the peripheral edge regions of the active matrix array substrate, A signal line such as a data line is routed to connect the signal line to the bonding pad, and is connected to the control circuit chip through a bonding process, thereby implementing signal control of the pixel unit.
  • a signal line such as a data line is routed to connect the signal line to the bonding pad, and is connected to the control circuit chip through a bonding process, thereby implementing signal control of the pixel unit.
  • the inventors of the present disclosure have noted in research that in order to maintain good electrical conductivity and uniformity of the traces, dense and long and serpent-shaped dense traces can be used. However, this design is very disadvantageous for narrow borders.
  • the implementation of the display panel, and the wide and dense routing arrangement makes it easy for short circuits or interrupted circuits to occur between adjacent signal lines, which tends to cause a decrease in process yield.
  • At least one embodiment of the present disclosure provides an array substrate having a display area and a non-display area disposed around the display area, and including: a first signal line and a second signal line disposed side by side in the display area, located at a non-display The display area and the first and second fan-out lines disposed side by side, and the first and second leads extending from the non-display area to the display area.
  • the first lead is disposed between the first signal line and the first fan-out line and electrically connects the first signal line and the first fan-out line
  • the second lead is disposed between the second signal line and the second fan-out line and will be second
  • the signal line and the second fan lead are electrically connected; the first lead and the second lead are disposed in different layers.
  • the array substrate provided by the embodiment of the present disclosure is described below by way of a few examples. As described below, different features in these specific examples may be combined with each other without conflicting with each other, thereby obtaining new examples. New examples are also within the scope of the disclosure.
  • an embodiment of the present disclosure provides an array substrate having a display area 521 and a non-display area 522 disposed around the display area.
  • the array substrate includes a plurality of strips disposed in the display area and arranged side by side.
  • the signal lines, the plurality of leads located in the non-display area 522, and the plurality of fan-out lines 3 are disposed side by side and connected to, for example, a control circuit chip (not shown) by, for example, a bonding pad.
  • the plurality of fan-out lines 3 may be arranged side by side in parallel at equal intervals (for example, arranged side by side in the first direction D1), or may be arranged side by side in non-parallel non-equal spacing, such as in a divergent type (for example, a plurality of fan-out lines 3)
  • the extending directions intersect each other; for example, each signal line 1 is connected to its corresponding lead 2 and its corresponding fan-out line 3, and is finally connected to the control circuit chip through the fan-out line 3.
  • the display area may, for example, include array-arranged display pixels (not shown), each of which is electrically coupled to at least one signal line.
  • a plurality of leads may extend from the non-display area 522 to the display area 521, that is, the lead 2 further includes a portion disposed in the non-display area 522.
  • the plurality of signal lines 1 include a first signal line 11 and a second signal line 12; as shown in FIG. 5, the first signal line 11 and the second signal line 12 are arranged along the signal line 1 (ie, the first direction) D1) alternately set; in this case, a second signal line 12 may be disposed between two adjacent first signal lines 11, and a second portion may be disposed between two adjacent second signal lines 12.
  • a signal line 11. For example, the first signal line 11 and the second signal line 12.
  • the first signal line 11 and the second signal line 12 are disposed, for example, in the same layer.
  • the first signal line 11 and the second signal line 12 have, for example, the same width and shape.
  • the plurality of leads 2 include a plurality of first leads 21 corresponding to the first signal lines 11 and arranged side by side, and a plurality of second leads 22 corresponding to the second signal lines 12 and arranged side by side;
  • the first lead 21 and the second lead 22 are disposed in a different layer.
  • the plurality of leads 2 may include a plurality of connecting lines 202 extending in the second direction D2 and juxtaposed in the third direction D3; the second direction D2 intersects the first direction D1, the third direction D3 is perpendicular to the second direction D2.
  • the plurality of fan-out lines 3 include a first fan-out line 31 and a second fan-out line 32 which are arranged in the first direction D1, and the first fan-out line 31 and the second fan-out line 32 are disposed, for example, in the same layer.
  • the first fan-out line 31 and the second fan-out line 32 may have the same structure.
  • the signal lines 1 arranged side by side are divided into a first signal line 11 and a second signal line 12, and each of the first signal lines 11 is connected to a corresponding first lead 21 and a corresponding fan-out line 3 thereof.
  • Each of the second signal lines 12 is connected to its corresponding second lead 22 and its corresponding fan-out line 3; for example, as shown in FIG. 1, the first lead 21 is disposed on the first signal line 11 and the first fan-out line 31.
  • the first signal line 11 and the first fan-out line 31 are electrically connected between each other, the second lead 22 is disposed between the second signal line 12 and the second fan-out line 32, and the second signal line 12 and the second fan-out line 32 are disposed. Electrical connection; the first lead 21 and the second lead 22 are disposed in different layers.
  • the first lead 21 and the second lead 22 may at least partially overlap in a direction perpendicular to the array substrate, and thus, the first lead 21 and the second lead 22 are
  • the width (for example, the width of the connection line of the first lead 21 and the second lead 22 in the third direction D3) may be greater than the width of the signal line 1 and the fan-out line 3 (the width in the first direction D1); adjacent
  • the spacing between the first leads 21 (for example, the pitch of the first connecting line 202 of the adjacent first lead 21 in the third direction in the third direction D3) and the spacing between the second leads 22 (
  • the spacing of the second connection line 222 of the adjacent second lead 22 in the third direction D3 in the third direction D3 may also be greater than the spacing between the adjacent signal lines 1 (the first signal line 11)
  • the pitch of the axis of symmetry in the first direction D1 and the axis of symmetry of the second signal line 11 in the first direction D1 in the first direction D1) may also be
  • increasing the width of the lead 2 can reduce the resistance of the lead 2 and can improve the uniformity of the lead 2.
  • Increasing the spacing between adjacent leads 2 is advantageous for reducing the probability of short circuit between the leads 2, thereby facilitating the improvement of the array.
  • the alternate arrangement of the first signal line 11 and the second signal line 12 can facilitate the regularity and uniformity of the arrangement of the first lead 21 and the second lead 22, thereby further improving the uniformity of the lead 2, thereby facilitating the improvement of the array.
  • Process yield of the substrate can facilitate the regularity and uniformity of the arrangement of the first lead 21 and the second lead 22, thereby further improving the uniformity of the lead 2, thereby facilitating the improvement of the array.
  • the array substrate is advantageous for the high resolution and narrow bezel design of the display panel, and the lead substrate has lower lead resistance, better lead uniformity, less chance of short circuit, and higher process yield. .
  • the plurality of signal lines 1 and the plurality of fan-out lines 3 may be disposed in the same layer.
  • the plurality of signal lines 1 and the plurality of fan-out lines 3 may be combined with the second lead 22
  • the same layer setting (see FIGS. 1 and 3) can be set in the same layer as the first lead 21 (not shown).
  • the plurality of signal lines 1 and the plurality of fan-out lines 3 may be disposed in different layers; in this case, for example, as shown in FIGS. 2 and 4, the first lead 21 may be combined with a plurality of fans
  • the outgoing line 3 (the first fan outgoing line 31 and the second fan outgoing line 32) are disposed in the same layer, and the second lead 22 can be disposed in the same layer as the plurality of signal lines 1 (the first signal line 11 and the second signal line 12);
  • the first lead 21 may be disposed in the same layer as the plurality of signal lines 1, and the second lead 22 may be disposed in the same layer as the plurality of fan-out lines 3.
  • the circuit layer where the first lead 21 is located is the first circuit layer (the structural layer shown by the oblique lines in FIGS. 1 to 4), and the circuit layer where the second lead 22 is located is the second circuit layer (as shown in the figure).
  • the structural layer shown by the solid color is taken as an example, and the array substrate provided by the embodiment of the present disclosure is exemplified.
  • the insulating layer may be provided with a first interlayer via, a second interlayer via, a third interlayer via, a fourth interlayer via, a fifth interlayer via (eg, via 410), and a sixth At least one of interlayer vias (eg, vias 412).
  • the first lead 21 and the first signal line 11 when the first lead 21 and the first signal line 11 are disposed in different layers, the first lead 21 and the first signal line 11 may be connected through the first interlayer via (for example, the via 41); When the lead 21 and the fan-out line 3 are disposed in different layers, the first lead 21 and the fan-out line 3 (the first fan-out line 31) may be connected through the second interlayer via (for example, the via 42).
  • the first interlayer via for example, the via 41
  • the first lead 21 and the fan-out line 3 when the lead 21 and the fan-out line 3 are disposed in different layers, the first lead 21 and the fan-out line 3 (the first fan-out line 31) may be connected through the second interlayer via (for example, the via 42).
  • the second lead 22 and the second signal line 12 may be connected through a third interlayer via (not shown);
  • the second lead 22 and the fan-out line 3 may also be connected through the fourth interlayer via (for example, the via 44).
  • each lead 2 may include two straps at both ends of the lead 2 and between the two straps. And a connecting line connected to the two-stage connecting wire; the two-stage connecting wire and the connecting line may be integrally formed, for example, formed in the same mask process.
  • the first lead 21 includes two first connecting wires 201 and a first connecting line between the two first connecting wires 201 and electrically connecting the two first connecting wires 201.
  • the second lead 22 includes two second connecting wires 221 and a second connecting line 222 between the two second connecting wires 221 and electrically connecting the two second connecting wires 221 .
  • the two-stage connection wires are respectively connected to the signal line 1 and the fan-out line 3.
  • the two lap wires of the first lead 21 are respectively connected to the first signal line 11 and the fan-out line 3
  • the two lap lines of the second lead 22 are used for the second signal line 12 and the fan-out line 3, respectively. Connected.
  • the first connection line 202 and the second connection line 222 may be overlapped to facilitate increasing the width of the leads 2 and the spacing between adjacent leads 2, and improving the process yield of the array substrate.
  • the extending direction of the first connecting line 202 may be parallel to the extending direction of the second connecting line 222; the width of the first connecting line 202 in a direction perpendicular to the extending direction of the first connecting line 202 is equal to The width of the second connecting line 222 in a direction perpendicular to the extending direction of the second connecting line 222.
  • the first connection line 202 and the second connection line 222 may completely overlap in a direction perpendicular to the array substrate.
  • the extending direction of the first connected wires 201 is parallel to the extending direction of the first signal line 11; the extending direction of the second connecting wires 221 connected to the second signal line 12 is parallel to the extending direction of the second connecting line 222 .
  • a plurality of signal lines 1 (first signal line 11 and second signal line 12) and a plurality of fan-out lines 3 (first fan-out line 31 and second fan-out line 32) may be the same Layer settings.
  • the plurality of signal lines 1 and the plurality of fan-out lines 3 may be disposed in different layers.
  • the plurality of signal lines 1 and the plurality of fan-out lines 3 and the second lead 22 are disposed in the same layer, that is, The strip signal line 1 and the plurality of fan-out lines 3 and the second lead 22 are in the second circuit layer, and the first lead 21 is in the first circuit layer; at this time, the strap 201 at one end of the first lead 21 can pass the first
  • the first via 41 between the circuit layer and the second wiring layer is electrically connected to the first signal line 11, and the bonding wire 201 at the other end of the first lead 21 passes through the second between the first wiring layer and the second wiring layer.
  • the via 42 is electrically connected to the fan-out line 3.
  • the plurality of signal lines 1 and the second lead 22 are disposed in the same layer, and the plurality of fan-out lines 3 and the first
  • the lead wires 21 are disposed in the same layer, that is, the plurality of signal wires 1 and the second lead wires 22 are in the same second circuit layer, and the plurality of fan-out wires 3 and the first lead wires 21 are in the first circuit layer; at this time, the first lead wire 21 is at one end.
  • the strap 201 can be electrically connected to the first signal line 11 through the third via 43 between the first circuit layer and the second circuit layer, and the strap 201 at one end of the second lead 22 passes through the first circuit layer and the The fourth via 44 between the two circuit layers is electrically connected to the fanout line 3.
  • the array substrate provided by the embodiment of the present disclosure may further include a plurality of strips respectively located between the plurality of leads 2 and the plurality of fan-out lines 3 and corresponding to the plurality of leads 2 .
  • a compensation line 5 each of which is connected between its corresponding lead 2 and fan-out line 3 and for connecting a lead 2 and a fan-out line 3 corresponding to the compensation line 5; each compensation line 5 and a lead connected thereto 2 different layer settings.
  • the plurality of compensation lines 5 include a first compensation line 51 electrically connected to the first signal line 11 and a second compensation line 52 electrically connected to the second signal line 12; the first compensation line 51 is located at the first lead 21 and Between the first fan-out lines 31 and for electrically connecting the first lead 21 and the first fan-out line 31, the second compensation line 52 is located between the second lead 22 and the second fan-out line 32, and is used for the second lead 22 and the second fan-out line 32 are electrically connected; that is, the connection trace of the first signal line 11 includes three parts of the first lead 21, the first compensation line 51 and the fan-out line 3 in sequence, and the connection lines of the second signal line 12 are in turn The second lead 22, the second compensation line 52 and the fan-out line 3 are included.
  • the plurality of compensation lines 5 include a plurality of first compensation lines 51 and a plurality of second compensation lines 52
  • the plurality of first compensation lines 51 are in one-to-one correspondence with the plurality of first signal lines 11
  • the plurality of second compensation lines 52 are in one-to-one correspondence with the plurality of second signal lines 12 .
  • the first compensation line 51 is disposed in a different layer from the first lead 21, and the second compensation line 52 is disposed in a different layer from the second lead 22.
  • the first compensation line 51 is disposed in the same layer as the second lead 22, and the second compensation line 52 is disposed in the same layer as the first lead 21, that is, the first compensation line 51 and the second lead 22 are in the second circuit layer, and the second The compensation line 52 is in the same first line layer as the first lead 21; further, the difference between the resistance between the first lead 21 and the second lead 22 can be compensated by the first compensation line 51 and the second compensation line 52, The trace resistance of the first signal line 11 and the second signal line 12 can be made more uniform.
  • the first compensation line 51 may be electrically connected to the first lead 21 through the via 4 disposed between the first circuit layer and the second circuit layer; for the same reason, the second compensation line 52 may also pass through the first circuit layer and the first The via 4 disposed between the two circuit layers is electrically connected to the second lead 22; and, similarly to the arrangement of the first lead 21 and the second lead 22, the first compensation line 51 and the second compensation line 52 can also pass Its connection line 501 realizes connection with other lines.
  • each of the compensation wires 5 includes two overlapping portions and a connecting portion between the two overlapping portions and connected to the two overlapping portions.
  • the first compensation line 51 includes two first laps 501 and a first one between the two first laps 501 and electrically connecting the two first laps 501.
  • the second compensation portion 52 includes two second overlapping portions 521 and a second connecting portion 522 between the two second overlapping portions 521 and electrically connecting the two second overlapping portions 521;
  • the connecting portions (the first connecting portion 502 and the second connecting portion 522) of the intermediate portion of the first compensation line 51 and the second compensation line 52 may at least partially overlap and be insulated from each other in a direction perpendicular to the array substrate, so as to improve the compensation line
  • the width and spacing of 5 improve the process yield of the array substrate.
  • the first overlap portion 501 of the first compensation line 51 and the second overlap line 221 of the second lead 22 are disposed at an orthographic projection interval within the panel surface of the array substrate to avoid the first compensation.
  • the line 51 and the second lead 22 are electrically connected;
  • the second overlap portion 521 of the second compensation line 52 is disposed at an orthographic projection interval of the first strap 201 of the first lead 21 in the panel plane to avoid the second compensation line It is electrically connected to the first lead 21.
  • the extending direction of the overlapping portion 501 of the first compensation line 51 may be parallel to the extending direction of the second bonding wire 221 of the second lead 22.
  • the plurality of signal lines 1 and the plurality of fan-out lines 3 are disposed in the same layer as the second lead 22 and the first compensation line 51, and the first lead is provided.
  • 21 and the second compensation line 52 are disposed in the same layer, that is, the plurality of signal lines 1, the plurality of fan-out lines 3, the second lead 22, and the first compensation line 51 are in the second circuit layer, the first lead 21 and the second compensation
  • the line 52 is in the same manner as the first circuit layer; further, in the routing path of the first signal line 11, the first lead 21 and the first signal line 11 and the first lead 21 and the first compensation line 51 need to pass respectively.
  • the fifth via 45 and the sixth via 46 between the first circuit layer and the second circuit layer implement a layer-by-layer connection; similarly, in the routing path of the second signal line 12, the second lead 22 and the second Between the compensation lines 52, between the second compensation line 52 and the fan-out line 3, a layer-by-layer connection is required to be achieved through the seventh via hole 47 and the eighth via hole 48, respectively.
  • the plurality of signal lines 1 and the second lead 22 and the first compensation line 51 are disposed in the same layer, and the plurality of fan-out lines 3 and the first lead 21 are provided.
  • the second compensation line 52 is disposed in the same layer, that is, the plurality of signal lines 1, the second lead 22 and the first compensation line 51 are in the same second line layer, the plurality of fan-out lines 3, the first lead 21 and the second compensation line 52 is in the first circuit layer; further, in the routing path of the first signal line 11, between the first lead 21 and the first signal line 11, between the first lead 21 and the first compensation line 51, and the first Between the compensation line 51 and the fan-out line 3, the ninth via 49, the tenth via 410, and the eleventh via 411 need to be respectively connected to each other; and in the routing path of the second signal line 12, A layer-change connection is required between the two leads 22 and the second compensation line 52 through the twelfth via 412.
  • the array substrate further includes a data line and a gate line disposed in different layers, a gate insulating layer, and a lead insulating layer (not shown).
  • the signal line 1 can be implemented as a data line; for example, the first lead 21 can be in the same layer as the gate line, and the second lead 22 can be in the same layer as the data line, that is, the first line layer is a gate line layer, and the second line layer is The data line layer; at this time, the lead insulating layer may be disposed in the same layer as the gate insulating layer and disposed between the first lead 21 and the second lead 22 in a direction perpendicular to the array substrate.
  • the signal line 1 may also be a gate line; for example, the first lead 21 may be in the same layer as the data line, and the second lead 22 may be in the same layer as the gate line, that is, the first line layer is a data line layer, and the second line layer
  • the lead insulating layer may be disposed in the same layer as the gate insulating layer and disposed between the first lead 21 and the second lead 22 in a direction perpendicular to the array substrate.
  • the material for fabricating the gate lines and the data lines may be copper, aluminum, aluminum alloy or other suitable materials
  • the material for forming the gate insulating layer may be silicon oxide (SiOx), silicon oxynitride (SiNxOy), silicon nitride. (SiNx) or other suitable material.
  • the signal line 1, the lead 2, and the fan-out line 3 can be made of the same material.
  • the signal line 1, the lead 2, and the fan-out line 3 may be made of a metal material (for example, copper, aluminum, or aluminum alloy), whereby the electric resistance may be lowered, but the embodiment of the present disclosure is not limited thereto; according to actual application requirements,
  • the signal line 1, the lead 2, and the fan-out line 3 may also be formed of a transparent conductive material, for example, the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the wires disposed in the same layer may be made of the same material and are formed in the same process, thereby simplifying the manufacturing process, for example, the first lead 21 and the gate line are in the same layer.
  • the embodiment of the present disclosure is not limited thereto.
  • the embodiment of the present disclosure further provides a display panel 801. As shown in FIG. 5, the display panel 801 includes any of the array substrates 800 provided by the embodiments of the present disclosure.
  • An embodiment of the present disclosure further provides a display device 802, as shown in FIG. 6, which includes any of the display panels 801 provided by the embodiments of the present disclosure.
  • the display panel 801 may be a liquid crystal display panel or an organic light emitting diode display panel.
  • the display panel 801 may include a plurality of sub-pixels arranged in an array, each of the sub-pixels including one pixel circuit, and the first signal line and the second signal line may be light of the pixel circuit. Control lines, sensing lines, etc.
  • the display panel and the display device provided by the embodiments of the present disclosure are advantageous for realizing high resolution and narrow bezel, and at the same time, the preparation process yield is high.
  • the size ratio of the partial structures in the drawings may be inconsistent with respect to the size ratio in the actual product, for example, being appropriately exaggerated, and the size ratio of the partial structures may also be smaller than the actual products.
  • the size ratio in the middle that is, the size ratio of the structure in the drawing does not represent the dimensional ratio of the real structure.

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Abstract

一种阵列基板(800)、显示面板(801)及显示装置(802)；其中，阵列基板(800)具有显示区(521)和围绕显示区(521)设置的非显示区(522)，且包括：位于显示区(521)且并排设置的第一信号线(11)和第二信号线(12)，位于非显示区(522)且并排设置的第一扇出线(31)和第二扇出线(32)，以及从非显示区(522)延伸至显示区(521)的第一引线(21)和第二引线(22)。第一引线(21)设置在第一信号线(11)和第一扇出线(31)之间且将第一信号线(11)和第一扇出线(31)电连接，第二引线(22)设置在第二信号线(12)和第二扇出线(32)之间且将第二信号线(12)和第二扇出线(32)电连接；第一引线(21)和第二引线(22)异层设置。上述阵列基板有利于显示面板的高分辨率和窄边框设计，且其制备工艺良率较高。

Description

阵列基板、显示面板及显示装置
本申请要求于2017年8月22日递交的中国专利申请第201721052927.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板、显示面板及显示装置。
背景技术
由于具有轻薄、低能耗、体积小等一系列优点，液晶显示屏幕目前已被大量地用于手机、笔记本电脑及个人电脑等消费电子产品中。液晶显示屏幕一般包括有源矩阵阵列基板、彩色滤光基板以及液晶层三部分。有源矩阵阵列基板与彩色滤光基板对向组装，液晶层位于有源矩阵阵列基板及彩色滤光基板之间，通过有源矩阵阵列基板中的有源元件可以调节液晶层的液晶分子的指向，即可调整透过液晶层的光束强度以显示出影像。
发明内容
本公开的至少一个实施例提供了一种阵列基板，其具有显示区和围绕所述显示区设置的非显示区，且包括：位于所述显示区且并排设置的第一信号线和第二信号线，位于所述非显示区且并排设置的第一扇出线和第二扇出线，以及从所述非显示区延伸至所述显示区的第一引线和第二引线。所述第一引线设置在所述第一信号线和所述第一扇出线之间且将所述第一信号线和所述第一扇出线电连接，所述第二引线设置在所述第二信号线和所述第二扇出线之间且将所述第二信号线和所述第二扇出线电连接；以及所述第一引线和所述第二引线异层设置。
例如，在所述阵列基板的至少一个示例中，当所述第一引线与所述第一信号线为异层设置时，所述第一引线通过第一层间过孔实现与所述第一信号线之间的电连接；当所述第一引线与所述第一扇出线异层设置时，所述第一 引线通过第二层间过孔实现与所述第一扇出线之间的电连接；当所述第二引线与所述第二信号线为异层设置时，所述第二引线通过第三层间过孔实现与所述第二信号线之间的电连接；当所述第二引线与所述第二扇出线异层设置时，所述第二引线通过第四层间过孔实现与所述第二扇出线之间的电连接。
例如，在所述阵列基板的至少一个示例中，所述第一引线包括两段第一搭接线以及位于所述两段第一搭接线之间且将所述两段第一搭接线电连接的第一连接线；所述第二引线包括两段第二搭接线以及位于所述两段第二搭接线之间且将所述两段第二搭接线电连接的第二连接线；所述第一连接线和所述第二连接线在垂直于所述阵列基板的方向上至少部分重叠且彼此绝缘。
例如，在所述阵列基板的至少一个示例中，所述第一信号线、所述第二信号线、所述第一扇出线、所述第二扇出线以及所述第二引线为同层设置；位于所述第一引线一端的第一搭接线通过第一过孔与所述第一信号线电连接，位于所述第一引线另一端的第一搭接线通过第二过孔与所述第一扇出线电连接。
例如，在所述阵列基板的至少一个示例中，所述第一引线与所述第一扇出线和所述第二扇出线同层设置，位于所述第一引线一端的第一搭接线通过第三过孔与所述第一信号线电连接；以及所述第二引线与所述第一信号线和所述第二信号线同层设置，位于所述第二引线一端的第二搭接线通过第四过孔与所述第二扇出线电连接。
例如，在所述阵列基板的至少一个示例中，所述第一连接线的延伸方向平行于所述第二连接线的延伸方向；以及所述第一连接线的在垂直于所述第一连接线的延伸方向的方向上的宽度等于所述第二连接线在垂直于所述第二连接线的延伸方向的方向上的宽度。
例如，在所述阵列基板的至少一个示例中，所述第一连接线和所述第二连接线在垂直于所述阵列基板的方向上完全重叠。
例如，在所述阵列基板的至少一个示例中，与所述第一信号线相连的第一搭接线的延伸方向以及与所述第二信号线相连的第二搭接线的延伸方向相交；与所述第一信号线相连的第一搭接线的延伸方向平行于所述第一信号线的延伸方向；以及与所述第二信号线相连的第二搭接线的延伸方向平行于所述第二连接线的延伸方向。
例如，在所述阵列基板的至少一个示例中，所述阵列基板还包括：位于所述第一引线和所述第一扇出线之间且将所述第一引线和所述第一扇出线电连接的第一补偿线，以及位于所述第二引线和所述第二扇出线之间，且将所述第二引线和所述第二扇出线电连接的第二补偿线；所述第一补偿线与所述第一引线异层设置，且所述第二补偿线与所述第二引线异层设置。
例如，在所述阵列基板的至少一个示例中，所述第一补偿线与所述第一信号线电连接，所述第二补偿线与所述第二信号线电连接；以及所述第一补偿线与所述第二引线同层设置，所述第二补偿线与所述第一引线同层设置。
例如，在所述阵列基板的至少一个示例中，所述第一补偿线通过第五层间过孔与所述第一引线电连接；所述第二补偿线通过第六层间过孔与所述第二引线电连接；所述第一补偿线和所述第二补偿线在垂直于所述阵列基板的方向上部分重叠。
例如，在所述阵列基板的至少一个示例中，所述第一补偿线包括两个第一搭接部以及位于所述两个第一搭接部之间且将所述两个第一搭接部电连接的第一连接部；所述第二补偿线包括两个第二搭接部以及位于所述两个第二搭接部之间且将所述两个第二搭接部电连接的第二连接部；以及所述第一连接部和所述第二连接部在垂直于所述阵列基板的方向上至少部分重叠且彼此绝缘。
例如，在所述阵列基板的至少一个示例中，所述第一搭接部与所述第二引线的第二搭接线在所述阵列基板的面板面内的正投影间隔设置；以及所述第二搭接部与所述第一引线的第一搭接线在所述面板面内的正投影间隔设置。
例如，在所述阵列基板的至少一个示例中，所述第一扇出线和所述第二扇出线沿第一方向并排设置；所述第一信号线和所述第二信号线沿所述第一方向并排设置；所述第一引线的第一连接线和所述第二引线的第二连接线在第二方向延伸且在第三方向上并列布置；以及所述第二方向与所述第一方向相交，所述第三方向垂直于所述第二方向。
例如，在所述阵列基板的至少一个示例中，所述第一连接线在所述第三方向上的宽度大于所述第一信号线在所述第一方向上的宽度。
例如，在所述阵列基板的至少一个示例中，所述第一连接线和所述第二 连接线在所述第一方向上重复排布，且所述第一连接线和所述第二连接线在所述第一方向上交替排布；以及相邻的所述第一连接线在所述第三方向上的间距大于相邻的所述第一连接线和所述第二信号线在所述第一方向上的间距，相邻的所述第二连接线在所述第三方向上的间距大于相邻的所述第一连接线和所述第二信号线在所述第一方向上的间距。
例如，在所述阵列基板的至少一个示例中，所述阵列基板还包括异层设置的数据线和栅线、栅极绝缘层以及引线绝缘层，所述第一信号线和所述第二信号线为所述数据线；所述第一引线与所述栅线同层设置，所述第二引线与所述数据线同层设置；以及所述引线绝缘层与所述栅极绝缘层同层，且在垂直于所述阵列基板的方向上设置在所述第一引线和所述第二引线之间。
例如，在所述阵列基板的至少一个示例中，所述显示区域包括阵列排布的多个显示像素，每个所述显示像素与至少一根信号线电连接。
本公开的至少一个实施例还提供了一种显示面板，其包括本公开的至少一个实施例提供的任一阵列基板。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开的至少一个实施例提供的任一显示面板。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为本公开的至少一个实施例提供的一种阵列基板的结构示意图；
图2为本公开的至少一个实施例提供的另一种阵列基板的结构示意图；
图3为本公开的至少一个实施例提供的再一种阵列基板的结构示意图；
图4为本公开的至少一个实施例提供的又再一种阵列基板的结构示意图；
图5为本公开的至少一个实施例提供的又再一种阵列基板的结构示意图；以及
图6为本公开的至少一个实施例提供的一种显示面板和一种显示装置的示例性框图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
一种有源矩阵阵列基板包括多条栅线、多条数据线以及电性连接至对应的栅线及数据线的多个像素单元；在有源矩阵阵列基板的四周边缘区域需要布置栅线、数据线等信号线的走线，以将信号线连接至键合盘，并通过键合工艺与控制电路芯片连接，从而实现对像素单元的信号控制。目前，由于显示面板的分辨率越来越高，各种信号线也越来越密集，从而，阵列基板四周区域的走线也越来越密集。
本公开的发明人在研究中注意到，为了保持各走线的良好导电性以及均匀性，可以采用又宽又长且呈蛇形延伸的密集走线，然而，这种设计非常不利于窄边框显示面板的实现，并且，又宽又密集的走线布置使得相邻信号线之间很容易发生短路或者集中断路，从而容易导致工艺良率降低。
本公开的至少一个实施例提供了一种阵列基板，其具有显示区和围绕显示区设置的非显示区，且包括：位于显示区且并排设置的第一信号线和第二信号线，位于非显示区且并排设置的第一扇出线和第二扇出线，以及从非显示区延伸至显示区的第一引线和第二引线。第一引线设置在第一信号线和第 一扇出线之间且将第一信号线和第一扇出线电连接，第二引线设置在第二信号线和第二扇出线之间且将第二信号线和第二扇出线电连接；第一引线和第二引线异层设置。
下面通过几个示例对本公开实施例提供的阵列基板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例中不同特征可以相互组合，从而得到新的示例，这些新的示例也都属于本公开保护的范围。
如图1～图5所示，本公开的实施例提供的一种阵列基板，具有显示区521和围绕显示区设置的非显示区522；该阵列基板包括位于显示区内且并排设置的多条信号线、位于非显示区522内的多条引线以及多条扇出线3，该多条扇出线3并排设置、且通过例如键合盘连接于例如控制电路芯片(图中未示出)。例如，该多条扇出线3可以是平行等间距并排设置(例如，沿第一方向D1并排设置)，也可以是非平行非等间距并排设置，如呈发散型设置(例如，多条扇出线3的延伸方向彼此相交)；例如，每条信号线1通过与其对应的引线2和与其对应的扇出线3相连，并通过扇出线3最终连接于控制电路芯片。显示区例如可以包括阵列排布的显示像素(图中未示出)，每个显示像素与至少一根信号线电连接。
需要说明的是，在本公开的一些实施例中，多条引线可以从非显示区522延伸至所述显示区521，也即，引线2还包括设置于非显示区522内的部分。
上述多条信号线1包括第一信号线11和第二信号线12；如图5所示，该第一信号线11和第二信号线12沿信号线1排列方向(也即，第一方向D1)交替设置；此种情况下，两条相邻的第一信号线11之间可以设置一根第二信号线12，且两条相邻的第二信号线12之间可以设置一根第一信号线11。例如，第一信号线11和第二信号线12。第一信号线11和第二信号线12例如设置在同一层。第一信号线11和第二信号线12例如具有相同的宽度和形状。
相应地，上述多条引线2包括与第一信号线11对应、且并排设置的多条第一引线21，以及与第二信号线12对应、且并排设置的多条第二引线22；，上述第一引线21和第二引线22为异层设置。
例如，如图5所示，多条引线2可以包括在第二方向D2延伸且在第三方向D3上并列布置的多条连接线202；第二方向D2与第一方向D1相交，第三方向D3垂直于第二方向D2。
如图1所示，上述多条扇出线3包括在第一方向D1交底布置的第一扇出线31和第二扇出线32，第一扇出线31和第二扇出线32例如设置在同一层。例如，第一扇出线31和第二扇出线32可以具有相同的结构。
上述阵列基板中，并排设置的信号线1被区分为第一信号线11和第二信号线12，且每条第一信号线11通过与其对应的第一引线21和与其对应的扇出线3相连，每条第二信号线12通过与其对应的第二引线22和与其对应的扇出线3相连；例如，如图1所示，第一引线21设置在第一信号线11和第一扇出线31之间且将第一信号线11和第一扇出线31电连接，第二引线22设置在第二信号线12和第二扇出线32之间且将第二信号线12和第二扇出线32电连接；第一引线21和第二引线22异层设置。
由于第一引线21和第二引线22分别设置在不同层，第一引线21和第二引线22在垂直于阵列基板的方向上可以至少部分重叠，因此，第一引线21和第二引线22的宽度(例如，第一引线21和第二引线22的连接线在第三方向D3上的宽度)可以大于信号线1以及扇出线3的宽度(在第一方向D1上的宽度)；相邻的第一引线21之间的间距(例如，相邻的第一引线21的第一连接线202在第三方向上的对称轴在第三方向D3上的间距)以及第二引线22之间的间距(例如，相邻的第二引线22的第二连接222线在第三方向上的对称轴在第三方向D3上的间距)也可以大于相邻的信号线1之间的间距(第一信号线11在第一方向D1上对称轴与第二信号线11在第一方向D1上对称轴在第一方向D1上的间距)，还可以大于相邻的扇出线3之间的间距(第一扇出线31在第一方向D1上对称轴与第二扇出线32在第一方向D1上对称轴在第一方向D1上的间距)。进而，本公开的实施例提供的阵列基板有利于信号线1的密集设计。
并且，增大引线2的宽度可以降低引线2的电阻并可以提高引线2的均匀性，增大相邻的引线2之间的间距有利于降低引线2之间的短路几率，从而有利于提高阵列基板的工艺良率；
另外，第一信号线11和第二信号线12交替设置可以便于第一引线21和第二引线22排列设置的规律性和均匀性，从而可以进一步提高引线2的均匀性，进而有利于提高阵列基板的工艺良率。
综上所述，上述阵列基板有利于显示面板的高分辨率和窄边框设计，并 且，该阵列基板的引线电阻较低、引线均匀性较好、走线短路几率较小，工艺良率较高。
在本公开实施例的至少一个示例中，多条信号线1和多条扇出线3可以同层设置，此种情况下，多条信号线1和多条扇出线3既可以与第二引线22同层设置(参见图1和图3)，又可以与第一引线21同层设置(图中未示出)。
在本公开实施例的至少一个示例中，多条信号线1和多条扇出线3可以异层设置；此种情况下，例如，如图2和图4，第一引线21可以与多条扇出线3(第一扇出线31和第二扇出线32)同层设置，并且第二引线22可以与多条信号线1(第一信号线11和第二信号线12)同层设置；又例如，第一引线21可以与多条信号线1同层设置，并且第二引线22可以与多条扇出线3同层设置。
下面，以第一引线21所在的线路层为第一线路层(如图1～图4中的斜线所表示的结构层)、第二引线22所在的线路层为第二线路层(如图1～图4中的纯色所表示的结构层)为例，对本公开的实施例提供的阵列基板进行举例说明。
如图1～图4所示，一种具体的示例中，本公开的实施例提供的阵列基板中，异层线路层之间(例如，第一线路层和第二线路层之间)设置有绝缘层，并且，可以在位于异层线路层之间的绝缘层中设置过孔4以实现换层连接(例如，实现不同线路层中的走线之间的电连接)。例如，绝缘层可以设置第一层间过孔、第二层间过孔、第三层间过孔、第四层间过孔、第五层间过孔(例如，过孔410)和第六层间过孔(例如，过孔412)中的至少一个。
例如，当第一引线21与第一信号线11为异层设置时，第一引线21和第一信号线11可以通过第一层间过孔(例如，过孔41)实现连接；当第一引线21与扇出线3为异层设置时，第一引线21和扇出线3(第一扇出线31)可以通过第二层间过孔(例如，过孔42)实现连接。
例如，当第二引线22与第二信号线12为异层设置时，第二引线22和第二信号线12可以通过第三层间过孔(图中未示出)实现连接；当第二引线22与扇出线3为异层设置时，第二引线22和扇出线3(第二扇出线32)也可以通过第四层间过孔(例如，过孔44)实现连接。
如图1～图4所示，在上述实施例的基础上，一种具体的示例中，每条引 线2可以包括位于引线2的两端的两段搭接线和位于两段搭接线之间且与所述两段搭接线连接的连接线；两段搭接线和连接线可以一体化形成，例如，在同一掩膜工艺中形成。
例如，如图1所示，第一引线21包括两段第一搭接线201以及位于两段第一搭接线201之间且将两段第一搭接线201电连接的第一连接线202；第二引线22包括两段第二搭接线221以及位于两段第二搭接线221之间且将两段第二搭接线221电连接的第二连接线222。
两段搭接线分别用于与信号线1和扇出线3相连。例如，第一引线21的两段搭接线分别用于与第一信号线11和扇出线3相连，第二引线22的两段搭接线分别用于与第二信号线12和扇出线3相连。
如图1所示，第一连接线202和第二连接线222可以重叠设置，以便于提高引线2的宽度以及相邻引线2之间的间距，以及提高阵列基板工艺良率。
例如，如图1所示，第一连接线202的延伸方向可以平行于第二连接线222的延伸方向；第一连接线202在垂直于第一连接线202的延伸方向的方向上的宽度等于第二连接线222在垂直于第二连接线222的延伸方向的方向上的宽度。
例如，如图1所示，第一连接线202和第二连接线222可以在垂直于阵列基板的方向上完全重叠。
例如，如图1所示，与第一信号线11相连的第一搭接线201的延伸方向以及与第二信号线12相连的第二搭接线221的延伸方向相交；与第一信号线11相连的第一搭接线201的延伸方向平行于第一信号线11的延伸方向；与第二信号线12相连的第二搭接线221的延伸方向平行于第二连接线222的延伸方向。
例如，如图1和图3所示，多条信号线1(第一信号线11和第二信号线12)和多条扇出线3(第一扇出线31和第二扇出线32)可以同层设置。
又例如，如图2和图4所示，多条信号线1和多条扇出线3还可以异层设置。
例如，如图1所示，在多条信号线1和多条扇出线3同层设置的情况下，多条信号线1和多条扇出线3与第二引线22为同层设置，即多条信号线1和多条扇出线3与第二引线22同在第二线路层，第一引线21则在第一线路层；此时，第一引线21一端的搭接线201可以通过第一线路层和第二线路层 之间的第一过孔41与第一信号线11电连接，第一引线21另一端的搭接线201通过第一线路层和第二线路层之间的第二过孔42与扇出线3电连接。
例如，如图2所示，在多条信号线1和多条扇出线3异层设置的情况下，多条信号线1与第二引线22为同层设置，多条扇出线3与第一引线21为同层设置，即多条信号线1与第二引线22同在第二线路层，多条扇出线3与第一引线21同在第一线路层；此时，第一引线21一端的搭接线201可以通过第一线路层和第二线路层之间的第三过孔43与第一信号线11电连接，第二引线22一端的搭接线201通过第一线路层和第二线路层之间的第四过孔44与扇出线3电连接。
例如，如图3和图4所示，本公开的实施例提供的阵列基板还可以包括分别位于多条引线2与多条扇出线3之间、且与多条引线2一一对应的多条补偿线5，每条补偿线5连接于与其对应的引线2和扇出线3之间且用于连接与该补偿线5对应的引线2和扇出线3；每条补偿线5和与其连接的引线2异层设置。
例如，该多条补偿线5包括与第一信号线11电连接的第一补偿线51以及与第二信号线12电连接的第二补偿线52；第一补偿线51位于第一引线21和第一扇出线31之间且用于将第一引线21和第一扇出线31电连接，第二补偿线52位于第二引线22和第二扇出线32之间，且用于将第二引线22和第二扇出线32电连接；即，第一信号线11的连接走线依次包括第一引线21、第一补偿线51和扇出线3三部分，第二信号线12的连接走线依次包括第二引线22、第二补偿线52和扇出线3三部分。例如，在多条信号线1包括多条第一信号线11和多条第二信号线12的情况下，多条补偿线5包括多条第一补偿线51和多条第二补偿线52，且多条第一补偿线51与多条第一信号线11一一对应，多条第二补偿线52与多条第二信号线12一一对应。
如图3和4所示，第一补偿线51与第一引线21异层设置，且第二补偿线52与第二引线22异层设置。例如，第一补偿线51与第二引线22同层设置，第二补偿线52与第一引线21同层设置，即第一补偿线51和第二引线22同处于第二线路层，第二补偿线52与第一引线21同处于第一线路层；进而，通过该第一补偿线51和第二补偿线52可以对第一引线21和第二引线22之间的电阻差异进行补偿，以使第一信号线11和第二信号线12的走线电 阻能够更加均匀。
例如，第一补偿线51可以通过第一线路层和第二线路层之间设置的过孔4与第一引线21电连接；同理，第二补偿线52也可以通过第一线路层和第二线路层之间设置的过孔4与第二引线22电连接；并且，与第一引线21和第二引线22的设置；同理，第一补偿线51和第二补偿线52也可以通过其搭接线501实现与其他线路之间连接。
如图3和图4所示，每条补偿线5包括两个搭接部以及位于两个搭接部之间且与两个搭接部连接的连接部。
如图3和图4所示，第一补偿线51包括两个第一搭接部501以及位于两个第一搭接部501之间且将两个第一搭接部501电连接的第一连接部502；第二补偿线52包括两个第二搭接部521以及位于两个第二搭接部521之间且将两个第二搭接部521电连接的第二连接部522；位于第一补偿线51和第二补偿线52中间部分的连接部(第一连接部502和第二连接部522)在垂直于阵列基板的方向上可以至少部分重叠且彼此绝缘，以便于提高补偿线5的宽度和间距，提高阵列基板工艺良率。
例如，如图3所示，第一补偿线51的第一搭接部501与第二引线22的第二搭接线221在阵列基板的面板面内的正投影间隔设置，以避免第一补偿线51和第二引线22电连接；第二补偿线52的第二搭接部521与第一引线21的第一搭接线201在面板面内的正投影间隔设置，以避免第二补偿线和第一引线21电连接。例如，如图3所示，第一补偿线51的搭接部501的延伸方向可以平行于第二引线22的第二搭接线221的延伸方向。
例如，如图3所示，在本公开的实施例提供的阵列基板中，多条信号线1和多条扇出线3与第二引线22和第一补偿线51为同层设置，第一引线21和第二补偿线52为同层设置，即多条信号线1、多条扇出线3、第二引线22和第一补偿线51同在第二线路层，第一引线21和第二补偿线52同在第一线路层；进而，第一信号线11的走线路径中，第一引线21与第一信号线11之间、第一引线21与第一补偿线51之间需要分别通过第一线路层和第二线路层之间的第五过孔45和第六过孔46来实现换层连接；同理，第二信号线12的走线路径中，第二引线22与第二补偿线52之间、第二补偿线52与扇出线3之间需要分别通过第七过孔47和第八过孔48来实现换层连接。
例如，如图4所示，本公开的实施例提供的阵列基板中，多条信号线1与第二引线22和第一补偿线51为同层设置，多条扇出线3与第一引线21和第二补偿线52为同层设置，即多条信号线1、第二引线22和第一补偿线51同在第二线路层，多条扇出线3、第一引线21和第二补偿线52同在第一线路层；进而，第一信号线11的走线路径中，第一引线21与第一信号线11之间、第一引线21与第一补偿线51之间、以及第一补偿线51与扇出线3之间需要分别通过第九过孔49、第十过孔410和第十一过孔411来实现换层连接；而在第二信号线12的走线路径中，第二引线22与第二补偿线52之间需要通过第十二过孔412来实现换层连接。
例如，本公开的实施例提供的阵列基板中，阵列基板还包括异层设置的数据线和栅线、栅极绝缘层以及引线绝缘层(图中未示出)。
例如，信号线1可以实现为数据线；例如，第一引线21可以与栅线同层，第二引线22可以与数据线同层，即第一线路层为栅线层，第二线路层为数据线层；此时，引线绝缘层可以与栅极绝缘层同层且在垂直于阵列基板的方向上设置在第一引线21和第二引线22之间。
又例如，信号线1也可以为栅线；例如，第一引线21可以与数据线同层，第二引线22可以与栅线同层，即第一线路层为数据线层，第二线路层为栅线层，同理，此时，引线绝缘层也可以与栅极绝缘层同层且在垂直于阵列基板的方向上设置在第一引线21和第二引线22之间。
例如，制作栅线和数据线的材料可以是铜、铝、铝合金或者其它适合的材料，制作栅极绝缘层的材料可以是氧化硅(SiOx)、氧氮化硅(SiNxOy)、氮化硅(SiNx)或者其它适合的材料。
例如，信号线1、引线2和扇出线3可以使用相同的材料制成。例如，信号线1、引线2和扇出线3可以使用金属材料(例如，铜、铝或者铝合金)制成，由此可以降低电阻，但本公开的实施例不限于此；根据实际应用需求，信号线1、引线2和扇出线3还可以采用透明导电材料形成，例如，透明导电材料为氧化铟锡(ITO)或氧化铟锌(IZO)。
需要说明的是，在本公开的实施例中，同层设置的导线可以使用相同的材料且在同一工序中制成，由此可以简化制作工艺，例如，在第一引线21与栅线同层的情况下，制作第一引线21与栅线的材料可以相同，但本公开的 实施例不限于此。
本公开的实施例还提供了一种显示面板801，如图5所示，该显示面板801包括本公开的实施例提供的任一阵列基板800。
本公开的实施例还提供了一种显示装置802，如图6所示，该显示装置802包括本公开的实施例提供的任一显示面板801。
需要说明的是，对于该显示面板801和显示装置802的其它必不可少的组成部分(例如控制装置、图像数据编码/解码装置、行扫描驱动器、列扫描驱动器、时钟电路等)均可以采用适用部件，这是本领域的普通技术人员应该理解的，在此不做赘述，也不应作为对本公开实施例的限制。
需要说明的是，显示面板801可以是液晶显示面板或者有机发光二极管显示面板。在显示面板801为有机发光二极管显示面板的情况下，显示面板801可以包括阵列排布的多个子像素，每个子像素包括一个像素电路，第一信号线和第二信号线可以是像素电路的发光控制线、感测线等。
本公开的实施例提供的显示面板和显示装置有利于实现高分辨率和窄边框，同时，其制备工艺良率较高。
需要说明的是，为了清楚的说明本公开的实施例，附图中的部分结构的尺寸比例相对于实际产品中的尺寸比例可能不一致，例如被适当夸大，部分结构的尺寸比例也可能小于实际产品中的尺寸比例，也即是，附图中结构的尺寸比例不代表真实结构的尺寸比例。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开的实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种阵列基板，具有显示区和围绕所述显示区设置的非显示区，且包括：位于所述显示区且并排设置的第一信号线和第二信号线，位于所述非显示区且并排设置的第一扇出线和第二扇出线，以及从所述非显示区延伸至所述显示区的第一引线和第二引线；
    其中，所述第一引线设置在所述第一信号线和所述第一扇出线之间且将所述第一信号线和所述第一扇出线电连接，所述第二引线设置在所述第二信号线和所述第二扇出线之间且将所述第二信号线和所述第二扇出线电连接；以及所述第一引线和所述第二引线异层设置。
  2. 根据权利要求1所述的阵列基板，其中，
    当所述第一引线与所述第一信号线为异层设置时，所述第一引线通过第一层间过孔实现与所述第一信号线之间的电连接；当所述第一引线与所述第一扇出线异层设置时，所述第一引线通过第二层间过孔实现与所述第一扇出线之间的电连接；
    当所述第二引线与所述第二信号线为异层设置时，所述第二引线通过第三层间过孔实现与所述第二信号线之间的电连接；当所述第二引线与所述第二扇出线异层设置时，所述第二引线通过第四层间过孔实现与所述第二扇出线之间的电连接。
  3. 根据权利要求1或2所述的阵列基板，其中，
    所述第一引线包括两段第一搭接线以及位于所述两段第一搭接线之间且将所述两段第一搭接线电连接的第一连接线；
    所述第二引线包括两段第二搭接线以及位于所述两段第二搭接线之间且将所述两段第二搭接线电连接的第二连接线；
    所述第一连接线和所述第二连接线在垂直于所述阵列基板的方向上至少部分重叠且彼此绝缘。
  4. 根据权利要求3所述的阵列基板，其中，
    所述第一信号线、所述第二信号线、所述第一扇出线、所述第二扇出线以及所述第二引线为同层设置；
    位于所述第一引线一端的第一搭接线通过第一过孔与所述第一信号线电 连接，位于所述第一引线另一端的第一搭接线通过第二过孔与所述第一扇出线电连接。
  5. 根据权利要求3所述的阵列基板，其中，
    所述第一引线与所述第一扇出线和所述第二扇出线同层设置，位于所述第一引线一端的第一搭接线通过第三过孔与所述第一信号线电连接；以及
    所述第二引线与所述第一信号线和所述第二信号线同层设置，位于所述第二引线一端的第二搭接线通过第四过孔与所述第二扇出线电连接。
  6. 根据权利要求3～5任一所述的阵列基板，其中，
    所述第一连接线的延伸方向平行于所述第二连接线的延伸方向；以及
    所述第一连接线的在垂直于所述第一连接线的延伸方向的方向上的宽度等于所述第二连接线的在垂直于所述第二连接线的延伸方向的方向上的宽度。
  7. 根据权利要求3～6任一所述的阵列基板，其中，
    所述第一连接线和所述第二连接线在垂直于所述阵列基板的方向上完全重叠。
  8. 根据权利要求3～7任一所述的阵列基板，其中，
    与所述第一信号线相连的第一搭接线的延伸方向以及与所述第二信号线相连的第二搭接线的延伸方向相交；
    与所述第一信号线相连的第一搭接线的延伸方向平行于所述第一信号线的延伸方向；以及
    与所述第二信号线相连的第二搭接线的延伸方向平行于所述第二连接线的延伸方向。
  9. 根据权利要求1所述的阵列基板，还包括：位于所述第一引线和所述第一扇出线之间且将所述第一引线和所述第一扇出线电连接的第一补偿线，以及位于所述第二引线和所述第二扇出线之间，且将所述第二引线和所述第二扇出线电连接的第二补偿线；其中，所述第一补偿线与所述第一引线异层设置，且所述第二补偿线与所述第二引线异层设置。
  10. 根据权利要求9所述的阵列基板，其中，
    所述第一补偿线与所述第一信号线电连接，所述第二补偿线与所述第二信号线电连接；以及
    所述第一补偿线与所述第二引线同层设置，所述第二补偿线与所述第一引线同层设置。
  11. 根据权利要求10所述的阵列基板，其中，
    所述第一补偿线通过第五层间过孔与所述第一引线电连接；所述第二补偿线通过第六层间过孔与所述第二引线电连接；所述第一补偿线和所述第二补偿线在垂直于所述阵列基板的方向上部分重叠。
  12. 根据权利要求10或11所述的阵列基板，其中，
    所述第一补偿线包括两个第一搭接部以及位于所述两个第一搭接部之间且将所述两个第一搭接部电连接的第一连接部；
    所述第二补偿线包括两个第二搭接部以及位于所述两个第二搭接部之间且将所述两个第二搭接部电连接的第二连接部；以及
    所述第一连接部和所述第二连接部在垂直于所述阵列基板的方向上至少部分重叠且彼此绝缘。
  13. 根据权利要求12所述的阵列基板，其中，
    所述第一搭接部与所述第二引线的第二搭接线在所述阵列基板的面板面内的正投影间隔设置；以及
    所述第二搭接部与所述第一引线的第一搭接线在所述面板面内的正投影间隔设置。
  14. 根据权利要求1～13任一项所述的阵列基板，其中，
    所述第一扇出线和所述第二扇出线沿第一方向并排设置；
    所述第一信号线和所述第二信号线沿所述第一方向并排设置；
    所述第一引线的第一连接线和所述第二引线的第二连接线在第二方向延伸且在第三方向上并列布置；以及
    所述第二方向与所述第一方向相交，所述第三方向垂直于所述第二方向。
  15. 根据权利要求14所述的阵列基板，其中，所述第一连接线在所述第三方向上的宽度大于所述第一信号线在所述第一方向上的宽度。
  16. 根据权利要求14或15所述的阵列基板，其中，
    所述第一连接线和所述第二连接线在所述第一方向上重复排布，且所述第一连接线和所述第二连接线在所述第一方向上交替排布；以及
    相邻的所述第一连接线在所述第三方向上的间距大于相邻的所述第一连 接线和所述第二信号线在所述第一方向上的间距，相邻的所述第二连接线在所述第三方向上的间距大于相邻的所述第一连接线和所述第二信号线在所述第一方向上的间距。
  17. 根据权利要求1～16任一项所述的阵列基板，还包括异层设置的数据线和栅线、栅极绝缘层以及引线绝缘层，其中，
    所述第一信号线和所述第二信号线为所述数据线；
    所述第一引线与所述栅线同层设置，所述第二引线与所述数据线同层设置；以及
    所述引线绝缘层与所述栅极绝缘层同层，且在垂直于所述阵列基板的方向上设置在所述第一引线和所述第二引线之间。
  18. 根据权利要求1～17任一项所述的阵列基板，其中，
    所述显示区域包括阵列排布的多个显示像素，每个所述显示像素与至少一根信号线电连接。
  19. 一种显示面板，包括权利要求1～18任一项所述的阵列基板。
  20. 一种显示装置，包括权利要求19所述的显示面板。
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CN207557624U (zh) 2018-06-29
US20210305285A1 (en) 2021-09-30
EP3674788A1 (en) 2020-07-01

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