WO2023023979A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023023979A1
WO2023023979A1 PCT/CN2021/114556 CN2021114556W WO2023023979A1 WO 2023023979 A1 WO2023023979 A1 WO 2023023979A1 CN 2021114556 W CN2021114556 W CN 2021114556W WO 2023023979 A1 WO2023023979 A1 WO 2023023979A1
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Prior art keywords
line
scanning
auxiliary
substrate
coupled
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PCT/CN2021/114556
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English (en)
French (fr)
Inventor
李永谦
袁粲
冯雪欢
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/114556 priority Critical patent/WO2023023979A1/zh
Priority to CN202180002272.3A priority patent/CN116034645A/zh
Publication of WO2023023979A1 publication Critical patent/WO2023023979A1/zh

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  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • OLED display products use the direct recombination of electrons and holes to excite spectra of various wavelengths to form graphics.
  • the display device formed by the OLED display technology has a fast response speed and can achieve the maximum contrast ratio at the same time, so the OLED display device is expected to become the mainstream display product of the next generation.
  • the purpose of the present disclosure is to provide a display substrate and a display device.
  • a first aspect of the present disclosure provides a display substrate, including: a base and a plurality of pixel units disposed on the base; the pixel units include:
  • a plurality of sub-pixels the plurality of sub-pixels are arranged in sequence along the first direction, the sub-pixels include a coupled sub-pixel driving circuit and a light emitting element, and the sub-pixel driving circuit is used to provide a driving signal to the light emitting element;
  • a light-shielding layer at least part of the light-shielding layer is located between the sub-pixel driving circuit and the substrate;
  • the display substrate further includes a scan line, the scan line includes at least a portion extending along the first direction, the scan line is coupled to the corresponding sub-pixel driving circuit; the scan line is on the same layer as the light-shielding layer set up.
  • the thickness d of the scanning line in a direction perpendicular to the substrate satisfies: 0.5 ⁇ m ⁇ d ⁇ 1.5 ⁇ m.
  • the scanning lines and the light-shielding layer are arranged in the same layer and the same material.
  • the display substrate further includes:
  • a scanning auxiliary line is located on the side of the corresponding scanning line facing away from the substrate, the scanning auxiliary line is coupled to the corresponding scanning line, and the scanning auxiliary line is connected to the corresponding scanning line
  • the sub-pixel driving circuits in the sub-pixels are coupled.
  • the scan assistant line includes: a first scan assistant graphic, a second scan assistant graphic and a third scan assistant graphic, and the third scan assistant graphic is located between the first scan assistant graphic and the second scan assistant graphic.
  • the first scanning auxiliary pattern and the second scanning auxiliary pattern are respectively coupled to the sub-pixel driving circuits in the corresponding sub-pixels; the third scanning auxiliary patterns are respectively connected to the corresponding scanning lines , the first scan assist pattern is coupled to the second scan assist pattern;
  • the scan line coupled with the third scan assist pattern includes a first boundary and a second boundary arranged along a second direction, the second direction intersects the first direction; the first boundary is on the substrate
  • the orthographic projection of the first scan aiding figure partially overlaps with the orthographic projection of the first scan aiding figure on the base, and the orthographic projection of the second boundary on the base overlaps with the The orthographic projections partially overlap.
  • the display substrate further includes:
  • the data line includes at least a portion extending along a second direction, the second direction intersects the first direction; the data line is coupled to a corresponding sub-pixel driving circuit;
  • a data auxiliary line is coupled to the corresponding data line, the data auxiliary line is located between the corresponding data line and the substrate, and the data auxiliary line is on the same layer as the light-shielding layer Same material setting.
  • the scanning line includes a first scanning part and a second scanning part, both of the first scanning part and the second scanning part extend along the first direction, and at a distance perpendicular to the first direction direction, the width of the first scanning portion is smaller than the width of the second scanning portion, and the orthographic projection of the first scanning portion on the substrate is at least partly the same as the orthographic projection of the data line on the substrate overlap.
  • the data auxiliary lines include at least two data auxiliary patterns, the at least two data auxiliary patterns are arranged along the second direction, and the at least two data auxiliary patterns are respectively coupled to corresponding data lines.
  • the orthographic projections of the scan lines on the substrate are located between adjacent orthographic projections of the data aided graphics on the substrate.
  • the display substrate further includes:
  • the power line includes at least a portion extending along the second direction, the power line is coupled to a corresponding sub-pixel driving circuit
  • a power supply auxiliary line is coupled to the corresponding power supply line, the power supply auxiliary line is located between the power supply line and the substrate, and the power supply auxiliary line is of the same layer and material as the light-shielding layer set up.
  • the auxiliary power line includes at least two auxiliary power patterns, the at least two auxiliary power patterns are arranged along the second direction, and the at least two auxiliary power patterns are respectively coupled to corresponding power lines.
  • the orthographic projection of at least one scan line on the substrate is located between the orthographic projections of adjacent power assist patterns on the substrate.
  • the display substrate further includes:
  • sensing line comprising at least a portion extending along the second direction
  • Sensing auxiliary lines are coupled to the sensing lines, the sensing auxiliary lines are located between the sensing lines and the substrate, the sensing auxiliary lines are connected to the light-shielding layer
  • the auxiliary sensing line includes at least a portion extending along the first direction, and the auxiliary sensing line is coupled to a corresponding sub-pixel driving circuit.
  • the sub-pixel driving circuit includes:
  • the first pole of the driving transistor is coupled to the power line, and the second pole of the driving transistor is coupled to the light emitting element;
  • a write transistor the gate of the write transistor is coupled to the scan line, the first pole of the write transistor is coupled to the data line, the second pole of the write transistor is coupled to the drive the gate coupling of the transistor;
  • a sensing transistor the gate of the sensing transistor is coupled to the scanning line, the first pole of the sensing transistor is coupled to the second pole of the driving transistor, and the second pole of the sensing transistor coupled with the sensing line;
  • a storage capacitor, the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the driving transistor.
  • the writing transistor includes a writing active layer
  • the sensing transistor includes a sensing active layer
  • the orthographic projection of the writing active layer on the substrate located on the first side of the orthographic projection of the scanning line coupled to the write transistor on the substrate, the orthographic projection of the sensing active layer on the substrate is located at the scanning line on the substrate
  • the first side and the second side are opposite along the second direction.
  • the driving transistor includes a driving active layer, at least part of the orthographic projection of the writing active layer on the substrate is located between the orthographic projection of the driving active layer on the substrate and the between orthographic projections of the scanlines on the substrate.
  • the sub-pixel further includes a pixel defining layer, the pixel defining layer defines a pixel opening, and in the same sub-pixel, the orthographic projection of the sensing active layer on the substrate is located at the pixel opening Between an orthographic projection on the substrate and an orthographic projection of the scanline on the substrate.
  • the first pole plate and the driving active layer are provided on the same layer and the same material
  • the second pole plate is provided on the same layer and the same material as the data line
  • the second pole plate and the light-shielding layer are provided on the same layer and the same material.
  • the layer is coupled, and the orthographic projection of the second polar plate on the substrate at least partially overlaps with the orthographic projection of the light shielding layer on the substrate.
  • the driving active layer includes a driving channel portion
  • the orthographic projection of the light shielding layer on the substrate at least partially overlaps the orthographic projection of the driving channel portion on the substrate.
  • a second aspect of the present disclosure provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic layout diagram of a pixel unit provided by an embodiment of the present disclosure
  • Fig. 3 is a schematic layout diagram of the light-shielding layer in Fig. 2;
  • FIG. 4 is a schematic layout diagram of the active layer in FIG. 2;
  • FIG. 5 is a schematic layout diagram of the gate metal layer in FIG. 2;
  • FIG. 6 is a schematic diagram of a via hole formed by a CNT process provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a via hole formed by patterning an interlayer insulating layer provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic layout diagram of the source-drain metal layer in FIG. 2;
  • Fig. 9 is a schematic layout diagram of the color resistance pattern in Fig. 2;
  • Fig. 10 is a schematic layout diagram of the anode layer in Fig. 2;
  • FIG. 11 is a schematic layout diagram of the pixel opening area in FIG. 2;
  • FIG. 12 is a schematic layout diagram of a light-shielding layer and an active layer in FIG. 2;
  • FIG. 13 is a schematic diagram of adding a gate metal layer in FIG. 12;
  • FIG. 14 is a schematic diagram of adding a via hole of the CNT process in FIG. 13;
  • FIG. 15 is a schematic diagram of adding via holes in the interlayer insulating layer in FIG. 14;
  • FIG. 16 is a schematic diagram of adding a source and drain metal layer in FIG. 15;
  • Fig. 17 is a schematic diagram of adding a color resistance pattern in Fig. 16;
  • FIG. 18 is a schematic diagram of adding an anode layer in FIG. 17 .
  • an embodiment of the present disclosure provides a display substrate, including: a base and a plurality of pixel units disposed on the base; the pixel unit includes:
  • a plurality of sub-pixels the plurality of sub-pixels are arranged in sequence along the first direction, the sub-pixels include a coupled sub-pixel driving circuit and a light-emitting element EL, and the sub-pixel driving circuit is used to provide driving for the light-emitting element EL Signal;
  • a light-shielding layer 10 at least part of the light-shielding layer 10 is located between the sub-pixel driving circuit and the substrate;
  • the display substrate further includes a scanning line GA, the scanning line GA includes at least a portion extending along the first direction, the scanning line GA is coupled to a corresponding sub-pixel driving circuit; the scanning line GA is connected to the The light-shielding layer 10 is set on the same layer.
  • the plurality of pixel units are distributed on the substrate in an array.
  • the plurality of pixel units can be divided into multiple rows of pixel units and multiple columns of pixel units, the multiple rows of pixel units are arranged along the second direction, and each row of pixel units includes a plurality of pixel units arranged along the first direction;
  • a plurality of columns of pixel units are arranged along the first direction, and each column of pixel units includes a plurality of pixel units arranged along the second direction.
  • the first direction includes a horizontal direction
  • the second direction includes a vertical direction
  • the pixel unit includes red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels.
  • the sub-pixel includes a sub-pixel driving circuit and a light-emitting element EL, and the sub-pixel driving circuit is coupled to an anode of the light-emitting element EL for providing a driving signal to the anode.
  • the sub-pixel driving circuit includes a 3T1C (ie, 3 transistors and 1 capacitor) structure, but not limited thereto.
  • the cathode of the light emitting element EL receives a negative power supply signal VSS.
  • the display substrate includes a light-shielding layer 10, an active layer, and a gate insulating layer that are sequentially formed in a direction away from the substrate and arranged in layers. , a gate metal layer, an interlayer insulating layer, a source-drain metal layer, a passivation layer, a color filter layer 50, a flat layer, an anode layer 60, a pixel defining layer, a light-emitting functional layer and a cathode layer.
  • the pixel defining layer can define a pixel opening, and the region where the pixel opening is located forms a pixel opening region 30 .
  • FIG. 6 and FIG. 14 illustrate via holes formed by the CNT via hole process.
  • FIG. 7 and FIG. 15 illustrate via holes formed by masking the interlayer insulating layer.
  • the CNT process is first performed to form a half via hole that does not penetrate the interlayer insulating layer on the interlayer insulating layer, and then a mask is performed on the interlayer insulating layer to form a hole through the interlayer insulating layer. Via holes in the interlayer insulating layer. After performing the interlayer insulating layer mask, a part of via holes can penetrate the interlayer insulating layer and extend to the light-shielding layer, while the other part only penetrates the interlayer insulating layer.
  • At least part of the light shielding layer 10 is located between the active layer included in the sub-pixel driving circuit and the substrate.
  • the orthographic projection of the light shielding layer 10 on the substrate at least partially overlaps the orthographic projection of the active layer included in some transistors in the sub-pixel driving circuit on the substrate.
  • the light-shielding layer 10 is made of conductive metal material, such as metal copper.
  • the display substrate includes a plurality of scanning lines GA, the plurality of scanning lines GA are in one-to-one correspondence with the plurality of rows of pixel units, and the scanning lines GA are corresponding to the pixel units included in each row of pixel units.
  • the sub-pixel driving circuits are respectively coupled.
  • the scan line GA is used to transmit scan signals.
  • the scanning line GA is coupled to the gates of corresponding transistors in the sub-pixel driving circuit, and is used for transmitting the scanning signal to the gates of corresponding transistors.
  • the scan line GA extends along the first direction.
  • the extension of the scanning line GA along the first direction means that the scanning line GA includes a main part and a secondary part connected with the main part, the main part is a line, a line segment or a bar-shaped body, the The main portion extends along the first direction, and the length of the main portion along the first direction is greater than the length of the secondary portion along the other directions.
  • the scanning line GA and the light-shielding layer 10 are arranged on the same layer, so that the scanning line GA is close to the substrate, which can By increasing the thickness of the scanning line GA, reducing the resistance of the scanning line GA, thereby effectively reducing the load of the scanning line GA, avoiding excessive signal delay when the scanning line GA transmits scanning signals, Compatible with a high refresh rate, the display effect is optimized, the working stability of the display substrate is ensured, and the service life of the display substrate is improved.
  • the scanning line GA is close to the substrate, there is a larger distance between the scanning line GA and other conductive structures in the display substrate in a direction perpendicular to the substrate, so that the scanning line GA can be reduced. Parasitic capacitance formed with other conductive structures. Therefore, the display substrate provided by the embodiments of the present disclosure does not need to provide a thick insulating layer to reduce parasitic capacitance, which effectively reduces the difficulty of the manufacturing process of the display substrate and improves the feasibility of mass production of the display substrate.
  • the scanning line GA can be preferentially produced in the display substrate manufacturing process, thus ensuring that the substrate is not easily deformed and effectively reducing the occurrence of cracks. risks of.
  • the thickness d of the scan line GA in a direction perpendicular to the substrate satisfies: 0.5 ⁇ m ⁇ d ⁇ 1.5 ⁇ m.
  • the thickness d of the scan line GA in a direction perpendicular to the substrate includes 1 ⁇ m.
  • the scanning line GA and the light shielding layer 10 are provided in the same layer and the same material.
  • the scanning line GA and the light-shielding layer 10 are arranged in the same layer and material, so that the scanning line GA and the light-shielding layer 10 can be formed simultaneously in the same patterning process, thereby effectively simplifying the manufacturing process of the display substrate.
  • the process reduces the manufacturing cost of the display substrate.
  • the display substrate further includes:
  • a scanning auxiliary line GAF is located on the side of the corresponding scanning line GA facing away from the substrate, the scanning auxiliary line GAF is coupled to the corresponding scanning line GA, the scanning auxiliary line The GAF is coupled to the sub-pixel driving circuit in the corresponding sub-pixel.
  • the display substrate includes a plurality of scanning auxiliary lines GAF, and the scanning auxiliary lines GAF are in one-to-one correspondence with the sub-pixels included in the display substrate.
  • the plurality of scanning auxiliary lines GAF located in the same row along the first direction are respectively coupled to the corresponding same scanning line GA.
  • a plurality of scanning auxiliary lines GAF located in the same row along the first direction are arranged at intervals.
  • a plurality of scanning auxiliary lines GAF located in the same row along the first direction form an integrated structure.
  • the scanning auxiliary line GAF is made of the gate metal layer.
  • the auxiliary scanning line GAF is formed into an integral structure with the gate of the transistor in the correspondingly coupled sub-pixel driving circuit.
  • the orthographic projection of the scanning auxiliary line GAF on the substrate has an overlapping area with the orthographic projection of the scanning line GA on the substrate.
  • the pixel unit further includes a plurality of first conductive connection parts 41, and the first conductive connection parts 41 include at least a part extending along the first direction.
  • the connecting portion 41 is respectively coupled to the scanning line GA and the corresponding scanning auxiliary line GAF.
  • the first conductive connection portion 41 is located on a side of the auxiliary scanning line GAF facing away from the substrate.
  • the first conductive connection part 41 and the data line DA in the display substrate are provided in the same layer and material.
  • the above arrangement of the pixel unit also includes a scanning auxiliary line GAF coupled to the scanning line GA, which not only ensures the connection performance between the scanning line GA and the corresponding sub-pixel driving circuit, but also further reduces the speed of the scanning line GA. resistance, better avoid the excessive signal delay of the scanning line GA when transmitting the scanning signal, better compatible with high refresh frequency, optimize the display effect, and ensure the working stability of the display substrate, The lifespan of the display substrate is improved.
  • the scanning auxiliary line GAF includes: a first scanning auxiliary pattern 210, a second scanning auxiliary pattern 211 and a third scanning auxiliary pattern 212;
  • the three-scan assist pattern 212 is located between the first scan assist pattern 210 and the second scan assist pattern 211; the first scan assist pattern 210 and the second scan assist pattern 211 are respectively in corresponding sub-pixels
  • the sub-pixel driving circuit is coupled; the third scanning auxiliary pattern 212 is respectively coupled to the corresponding scanning line GA, the first scanning auxiliary pattern 210 and the second scanning auxiliary pattern 211;
  • the scan line GA coupled to the third scan assist pattern 212 includes a first boundary and a second boundary arranged along a second direction, and the second direction intersects the first direction; the first boundary is in the
  • the orthographic projection on the base partially overlaps the orthographic projection of the first scanning aid figure 210 on the base, and the orthographic projection of the second boundary on the base overlaps with the second scan aiding figure 211 on the base.
  • the orthographic projections on the above substrates partially overlap.
  • the first scan aid figure 210, the second scan aid figure 211 and the third scan aid figure 212 form an integral structure.
  • the first scanning auxiliary pattern 210 is multiplexed as the gate of the sensing transistor T2, and the second scanning auxiliary pattern 211 is multiplexed as the gate of the writing transistor T1.
  • the first scan assist pattern 210 includes at least a portion extending along the second direction
  • the second scan assist pattern 211 includes at least a portion extending along the second direction
  • the third scan assist pattern 211 includes at least a portion extending along the second direction
  • the graphic 212 includes at least a portion extending along the first direction.
  • the orthographic projection of the third scan auxiliary pattern 212 on the substrate is located inside the orthographic projection of the scan line GA on the substrate.
  • the first conductive connection portion 41 is respectively coupled to the scan line GA and the corresponding third scan auxiliary pattern 212 .
  • the orthographic projection of the first boundary on the base partially overlaps the orthographic projection of the first scanning aid figure 210 on the base, and the orthographic projection of the second boundary on the base The projection partially overlaps with the orthographic projection of the second scan assisting pattern 211 on the base.
  • the orthographic projection of the first boundary on the base partly overlaps the orthographic projection of the third scanning aid figure 212 on the base, and the orthographic projection of the second boundary on the base The projection partially overlaps with the orthographic projection of the third scan aid pattern 212 on the substrate.
  • the scanning auxiliary line GAF set above includes: the first scanning auxiliary pattern 210, the second scanning auxiliary pattern 211 and the third scanning auxiliary pattern 212, which not only ensure the connection between the scanning line GA and the sub-pixel driving circuit well. The connection performance between them also effectively reduces the layout difficulty of the display substrate.
  • the display substrate further includes:
  • a data line DA includes at least a portion extending along a second direction, the second direction intersects the first direction; the data line DA is coupled to a corresponding sub-pixel driving circuit;
  • a data auxiliary line DAF is coupled to the corresponding data line, the data auxiliary line DAF is located between the corresponding data line DA and the substrate, and the data auxiliary line DAF is connected to the corresponding data line
  • the light-shielding layer 10 is set in the same layer and the same material.
  • the data line DA is used for transmitting data signals.
  • the data line DA is coupled to a corresponding transistor in the sub-pixel driving circuit, and is used for transmitting the data signal to the corresponding transistor.
  • the display substrate further includes a plurality of data lines DA.
  • the display substrate includes a plurality of sub-pixels, the plurality of sub-pixels are divided into a plurality of sub-pixel columns, and the plurality of sub-pixel columns correspond to the plurality of data lines DA one by one.
  • the data line DA is respectively coupled to each sub-pixel driving circuit in a corresponding sub-pixel row.
  • the display substrate includes a plurality of auxiliary data lines DAF, each data line DA corresponds to a plurality of auxiliary data lines DAF, and the data lines DA are respectively coupled to the corresponding plurality of auxiliary data lines DAF .
  • each data line DA corresponds to a plurality of auxiliary data lines DAF arranged at intervals in sequence along the second direction.
  • the data line DA is made of the source-drain metal layer.
  • the orthographic projection of the data auxiliary line DAF on the substrate at least partially overlaps with the corresponding orthographic projection of the data line DA on the substrate, and the data auxiliary line DAF and the corresponding data Line DA is coupled through a via at the overlap.
  • the orthographic projection of the data auxiliary line DAF on the substrate is located inside the corresponding orthographic projection of the data line DA on the substrate.
  • the data auxiliary line DAF includes at least a portion extending along the second direction.
  • the above arrangement of the data auxiliary line DAF being coupled to the data line DA effectively reduces the resistance of the data line DA, thereby effectively reducing the load of the data line DA, and avoiding the data transmission of the data line DA.
  • the signal is delayed, compatible with high refresh rate, and ensures the working stability of the display substrate.
  • the light-shielding layer 10 is thicker in the direction perpendicular to the substrate, setting the data auxiliary line DAF and the light-shielding layer 10 on the same layer and the same material can better reduce the DA resistance.
  • the above-mentioned arrangement of the data auxiliary line DAF and the light-shielding layer 10 in the same layer and the same material enables the data auxiliary line DAF and the light-shielding layer 10 to be formed simultaneously in the same patterning process, thereby effectively simplifying the display.
  • the manufacturing process flow of the substrate reduces the manufacturing cost of the display substrate.
  • the scanning line GA includes a first scanning part 201 and a second scanning part 202, and the first scanning part 201 and The second scanning portions 202 all extend along the first direction, and in a direction perpendicular to the first direction, the width d1 of the first scanning portion 201 is smaller than the width d2 of the second scanning portion 202,
  • the orthographic projection of the first scanning part 201 on the substrate at least partially overlaps the orthographic projection of the data line DA on the substrate.
  • the first scanning part 201 and the second scanning part 202 form an integral structure.
  • the first scanning part 201 and the second scanning part 202 are arranged alternately along the first direction.
  • the width of the first scanning portion 201 is smaller than the width of the second scanning portion 202 .
  • the orthographic projection of the first scanning part 201 on the substrate at least partially overlaps the orthographic projection of the data line DA on the substrate; the second scanning part 202 is on the substrate
  • the orthographic projection of is at least partially overlapped with the orthographic projection of the data line DA on the substrate.
  • the orthographic projection of the first scanning part 201 on the substrate at least partially overlaps the orthographic projection of the data line DA on the substrate; the second scanning part 202 is on the substrate
  • the orthographic projection of and the orthographic projection of the data line DA on the substrate do not overlap.
  • the orthographic projection of the first scanning part 201 on the substrate at least partially overlaps with the orthographic projection of the power line VDD on the substrate.
  • the width of the first scanning part 201 is set to be smaller than the width of the second scanning part 202, and the orthographic projection of the first scanning part 201 on the substrate is the same as the orthographic projection of the data line DA on the substrate.
  • the projections overlap at least partially, which is beneficial to reduce the overlapping area between the scan line GA and the data line DA, and reduce the parasitic capacitance formed between the scan line GA and the data line DA.
  • the data auxiliary line DAF includes at least two data auxiliary patterns DAF1, the at least two data auxiliary patterns DAF1 are arranged along the second direction, and the at least two data auxiliary patterns DAF1
  • the auxiliary patterns DAF1 are respectively coupled to corresponding data lines DA.
  • the at least two data auxiliary graphics DAF1 are arranged at intervals along the second direction.
  • the data aided graphic DAF1 includes at least a portion extending along the second direction.
  • the orthographic projection of the data-assisted graphic DAF1 on the substrate at least partially overlaps with the corresponding orthographic projection of the data line DA on the substrate.
  • the orthographic projection of the data-assisted graphic DAF1 on the substrate is located inside the corresponding orthographic projection of the data line DA on the substrate.
  • the data auxiliary line DAF includes at least two data auxiliary patterns DAF1 can not only effectively reduce the resistance of the data line DA, but also reduce the contact between the data auxiliary line DAF and other conductive structures (such as: light shielding layer 10, and The risk of a short circuit between the conductive structures disposed on the same layer as the light-shielding layer 10 effectively reduces the layout difficulty of the data auxiliary pattern DAF1.
  • the orthographic projection of the scanning line GA on the substrate is located in the Between orthographic projections on the base.
  • the orthographic projection of the scanning line GA on the substrate is located between the orthographic projections of the adjacent data-aided graphics DAF1 on the substrate, which not only reduces the layout difficulty of the display substrate, but also facilitates Guarantee the reliability and stability of the display substrate.
  • the display substrate further includes:
  • the power line VDD including at least a portion extending along the second direction, the power line VDD being coupled to a corresponding sub-pixel driving circuit
  • auxiliary power line VDDF An auxiliary power line VDDF, the auxiliary power line VDDF is coupled to the corresponding power line VDD, the auxiliary power line VDDF is located between the power line VDD and the substrate, the auxiliary power line VDDF is connected to the
  • the light-shielding layer 10 is provided with the same layer and the same material.
  • the power line VDD is used to transmit a power signal (such as a positive power signal).
  • the power line VDD is coupled to corresponding transistors in the sub-pixel driving circuit, and is used for transmitting the power signal to corresponding transistors.
  • the power line VDD is made using the source-drain metal layer.
  • the orthographic projection of the auxiliary power supply line VDDF on the substrate at least partially overlaps the orthographic projection of the corresponding power supply line VDD on the substrate, and the auxiliary power supply line VDDF and the corresponding power supply Line VDD is coupled through vias at the overlap.
  • the orthographic projection of the auxiliary power supply line VDDF on the substrate is located inside the corresponding orthographic projection of the power supply line VDD on the substrate.
  • the power auxiliary line VDDF includes at least a portion extending along the second direction.
  • auxiliary power line VDDF being coupled to the power line VDD effectively reduces the resistance of the power line VDD, thereby effectively reducing the load of the power line VDD.
  • the power supply auxiliary line VDDF and the light-shielding layer 10 are arranged on the same layer and the same material, which can better reduce the power supply lines. resistor to VDD.
  • the above-mentioned arrangement of the auxiliary power line VDDF and the light-shielding layer 10 in the same layer and the same material enables the auxiliary power line VDDF and the light-shielding layer 10 to be formed simultaneously in the same patterning process, thereby effectively simplifying the display.
  • the manufacturing process flow of the substrate reduces the manufacturing cost of the display substrate.
  • the power supply auxiliary line VDDF includes at least two power supply auxiliary patterns VDDF1, and the at least two power supply auxiliary patterns VDDF1 are along the second Arranged in a direction, the at least two auxiliary power supply patterns VDDF1 are respectively coupled to corresponding power supply lines VDD.
  • the at least two power supply auxiliary patterns VDDF1 are arranged at intervals along the second direction.
  • the power auxiliary pattern VDDF1 includes at least a portion extending along the second direction.
  • the orthographic projection of the auxiliary power supply pattern VDDF1 on the substrate at least partially overlaps with the corresponding orthographic projection of the power supply line VDD on the substrate.
  • the orthographic projection of the auxiliary power supply pattern VDDF1 on the substrate is located inside the corresponding orthographic projection of the power supply line VDD on the substrate.
  • the above setting of the auxiliary power line VDDF includes at least two auxiliary power patterns VDDF1 can not only effectively reduce the resistance of the power line VDD, but also reduce the contact between the auxiliary power line VDDF and other conductive structures (such as: the light shielding layer 10, and The risk of a short circuit between the conductive structures disposed on the same layer as the light-shielding layer 10 effectively reduces the layout difficulty of the power supply auxiliary pattern VDDF1.
  • the orthographic projection of at least one scan line GA on the substrate is located adjacent to the power auxiliary pattern VDDF1 in the Between orthographic projections on the base.
  • the orthographic projection of the scanning line GA on the substrate in the above layout is located between the orthographic projections of the adjacent power supply auxiliary graphics VDDF1 on the substrate, which can not only reduce the layout difficulty of the display substrate, but also It is beneficial to ensure the reliability and stability of the display substrate.
  • the display substrate further includes:
  • a sensing line SE including at least a portion extending in the second direction
  • a sensing auxiliary line SEF is coupled to the sensing line SE, the sensing auxiliary line SEF is located between the sensing line SE and the substrate, the sensing auxiliary line SEF is provided in the same layer and material as the light shielding layer 10 ; the auxiliary sensing line SEF includes at least a portion extending along the first direction, and the auxiliary sensing line SEF is coupled to a corresponding sub-pixel driving circuit.
  • the display substrate includes a plurality of sensing lines SE, and the plurality of pixel units in the display substrate are divided into a plurality of columns of pixel units, and the plurality of sensing lines SE are connected to the plurality of columns of pixel units one by one
  • the sensing line SE is respectively coupled to each sub-pixel driving circuit included in the corresponding pixel unit column.
  • the sensing line SE is made of a source-drain metal layer.
  • the sensing line SE can provide a reference signal for resetting the anode layer 60 of the light emitting element EL during the period of writing the data signal.
  • the sensing line SE is also capable of transmitting a sensing signal sensed from the anode layer 60 during a sensing period.
  • the sensing auxiliary line SEF includes at least a portion extending along the first direction.
  • the display substrate includes a plurality of auxiliary sensing lines SEF, the plurality of auxiliary sensing lines SEF correspond to a plurality of pixel units in the display substrate one by one, and the auxiliary sensing lines SEF correspond to Each sub-pixel driving circuit in the pixel unit is coupled to the corresponding sensing line SE respectively.
  • the orthographic projection of the sensing auxiliary line SEF on the substrate at least partially overlaps the corresponding orthographic projection of the sensing line SE on the substrate, and at the overlap, the sensing The sensing auxiliary line SEF is coupled to the sensing line SE.
  • the auxiliary sensing line SEF is respectively coupled to corresponding transistors included in each sub-pixel driving circuit in the corresponding pixel unit.
  • auxiliary sensing line SEF being coupled to the sensing line SE effectively reduces the resistance of the sensing line SE, thereby effectively reducing the load on the sensing line SE.
  • the light-shielding layer 10 is thicker in the direction perpendicular to the substrate, setting the sensing auxiliary line SEF and the light-shielding layer 10 in the same layer and the same material can better reduce the sensitivity. Resistance of measuring wire SE.
  • the aforementioned arrangement of the auxiliary sensing lines SEF and the light-shielding layer 10 in the same layer and the same material enables the auxiliary sensing lines SEF and the light-shielding layer 10 to be formed simultaneously in the same patterning process, thereby effectively simplifying the process.
  • the manufacturing process flow of the display substrate is simplified, and the manufacturing cost of the display substrate is reduced.
  • the resistances of the scanning line GA, the data line DA, the sensing line SE, and the power line VDD are effectively reduced, improving It eliminates the delay phenomenon that occurs when the signal line transmits the corresponding signal.
  • the IR Drop of the power line VDD when transmitting power signals is also well reduced.
  • the sub-pixel driving circuit includes:
  • a driving transistor T3, the first pole of the driving transistor T3 is coupled to the power supply line VDD, and the second pole of the driving transistor T3 is coupled to the light emitting element EL;
  • the gate of the write transistor T1 is coupled to the scan line GA, the first pole of the write transistor T1 is coupled to the data line DA, the first electrode of the write transistor T1
  • the diode is coupled to the gate T3-G of the drive transistor T3;
  • Sensing transistor T2 the gate of the sensing transistor T2 is coupled to the scanning line GA, the first pole of the sensing transistor T2 is coupled to the second pole of the driving transistor T3, the sensing The second pole of the transistor T2 is coupled to the sensing line SE;
  • the first plate Cst1 of the storage capacitor Cst is coupled to the gate T3-G of the driving transistor T3, the second plate Cst2 of the storage capacitor Cst is connected to the second electrode of the driving transistor T3 pole coupling.
  • the areas of the first plate Cst1 of the storage capacitor Cst included in at least two sub-pixels may be different, so as to meet the requirements of different sub-pixels for the storage capacitor capacitance.
  • the first pole of the driving transistor T3 is coupled to the power line VDD, and the second pole of the driving transistor T3 is coupled to the anode layer 60 of the light emitting element EL.
  • both the writing transistor T1 and the sensing transistor T2 are used as switch transistors.
  • the writing transistor T1 under the control of the scanning signal provided by the scanning line GA, the writing transistor T1 is turned on or off. Under the control of the scan signal provided by the scan line GA, the sensing transistor T2 is turned on or off.
  • the sub-pixel driving circuit includes a 3T1C structure, and the pixel unit includes a scanning line GA.
  • the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate at least partially overlaps the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate.
  • the scanning line GA By reducing the load of the scanning line GA, it is possible to avoid the delay of the scanning signal transmission by the scanning line GA, and ensure the charging rate of the data line DA to write the data signal to the gate T3-G of the driving transistor T3, so that the The display substrate can meet the requirement of high refresh rate. At the same time, the transmission of the sensing signal and the reference signal is also guaranteed.
  • the write transistor T1 includes a write active layer T1-S
  • the sense transistor T2 includes a sense active layer T2-S, in the same pixel
  • the orthographic projection of the writing active layer T1-S on the substrate is located on the first side of the orthographic projection of the scanning line GA coupled to the writing transistor T1 on the substrate
  • the orthographic projection of the sensing active layer T2-S on the substrate is located on the second side of the orthographic projection of the scanning line GA on the substrate, and the first side and the second side are along the The second direction is opposite.
  • At least part of the orthographic projection of the scanning line GA on the substrate is located between the orthographic projection of the writing active layer T1-S on the substrate and the Between the orthographic projections of the sensing active layer T2-S on the substrate.
  • both the writing active layer T1-S and the sensing active layer T2-S are made of transparent materials.
  • both the writing active layer T1-S and the sensing active layer T2-S are made of transparent metal oxide materials.
  • the writing active layer T1-S includes at least a portion extending along the first direction.
  • the writing active layer T1-S is formed as an integral structure with the first plate Cst1 of the storage capacitor Cst.
  • the sensing active layer T2-S includes at least a portion extending along the first direction.
  • the orthographic projection of the scanning line GA on the substrate does not overlap with the orthographic projection of the writing active layer T1-S on the substrate.
  • the orthographic projection of the scan line GA on the substrate does not overlap with the orthographic projection of the sensing active layer T2-S on the substrate.
  • the above setting of the orthographic projection of the scanning line GA on the substrate is located between the orthographic projection of the writing active layer T1-S on the substrate and the sensing active layer T2-S on the substrate. Between the orthographic projections above, it is beneficial to reduce the layout difficulty of the pixel unit in a limited layout space and ensure that the display substrate has a higher resolution.
  • setting the driving transistor T3 includes driving the active layer T3-S, and writing at least part of the orthographic projection of the active layer T1-S on the substrate , located between the orthographic projection of the driving active layer T3-S on the substrate and the orthographic projection of the scanning line GA on the substrate.
  • the driving active layer T3-S includes at least a portion extending along the second direction.
  • the driving active layer T3-S is made of transparent material.
  • the driving active layer T3-S is made of a transparent metal oxide material.
  • the gate T3-G of the driving transistor T3 includes at least a portion extending along the first direction.
  • the above setting method is beneficial to reduce the layout difficulty of the pixel unit in a limited layout space, and ensure that the display substrate has a higher resolution.
  • the sub-pixel further includes a pixel defining layer, and the pixel defining layer defines a pixel opening.
  • the sensing active layer T2- The orthographic projection of S on the substrate is located between the orthographic projection of the pixel opening on the substrate and the orthographic projection of the scan line GA on the substrate.
  • the position where the pixel opening is located forms a pixel opening area 30, and the pixel opening area 30 includes at least a portion extending along the second direction.
  • the orthographic projection of the pixel opening on the substrate does not overlap with the orthographic projection of the sub-pixel driving circuit on the substrate.
  • the orthographic projection of the sensing active layer T2-S on the substrate is located at the same location as the orthographic projection of the pixel opening on the substrate and the scanning line GA on the substrate Between the orthographic projections; so that the orthographic projection of the pixel opening on the substrate and the orthographic projection of the sub-pixel driving circuit on the substrate are arranged along the second direction, which can ensure that the pixel opening occupies
  • the large enough layout space ensures the pixel aperture ratio of the display substrate.
  • the above setting method also reduces the layout difficulty of the pixel unit.
  • the first polar plate Cst1 and the driving active layer T3-S are arranged in the same layer and the same material, and the second polar plate Cst2 is in the same layer as the data line DA. Arranged with the same material, the second polar plate Cst2 is coupled to the light-shielding layer 10, and the orthographic projection of the second polar plate Cst2 on the substrate is at least partially overlap.
  • the first pole plate Cst1 and the driving active layer T3-S are arranged in the same layer and the same material, so that the first pole plate Cst1 and the driving active layer T3-S can be formed in the same patterning process. Simultaneously formed, thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.
  • the above-mentioned setting of the second pole plate Cst2 and the data line DA in the same layer and the same material enables the second pole plate Cst2 and the data line DA to be formed simultaneously in the same patterning process, thereby effectively
  • the manufacturing process flow of the display substrate is simplified, and the manufacturing cost of the display substrate is reduced.
  • the above setting method is beneficial to improve the working stability of the storage capacitor Cst.
  • the driving active layer T3-S includes a driving channel part, the orthographic projection of the light shielding layer 10 on the substrate, and the driving channel part The orthographic projections of the portions on the substrate at least partially overlap.
  • the driving active layer T3-S includes: a driving channel part, a part for forming the first pole of the driving transistor T3, and a part for forming the second pole of the driving transistor T3 .
  • the orthographic projection of the driving channel portion on the substrate is located inside the orthographic projection of the gate T3-G of the driving transistor T3 on the substrate.
  • the orthographic projection of the light-shielding layer 10 on the substrate is at least partially overlapped with the orthographic projection of the driving channel part on the substrate, which can effectively reduce the influence of the driving transistor T3 from light leakage, The working stability of the driving transistor T3 is guaranteed.
  • Embodiments of the present disclosure also provide a display device, including the display substrate provided in the above embodiments.
  • the display device includes a super-sized, high-resolution, bottom-emitting OLED display device.
  • the display device includes an active matrix organic light emitting diode display device.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a back panel. board etc.
  • the scanning line GA and the light-shielding layer 10 are arranged in the same layer, so that the scanning line GA is close to the substrate, so that the thickness of the scanning line GA can be increased to reduce the The resistance of the scanning line GA, thereby effectively reducing the load of the scanning line GA, avoiding the excessive signal delay of the scanning line GA when transmitting the scanning signal, compatible with high refresh rate, optimizing the display effect, ensuring The working stability of the display substrate is improved, and the service life of the display substrate is improved.
  • the scanning line GA is close to the substrate, there is a larger distance between the scanning line GA and other conductive structures in the display substrate in a direction perpendicular to the substrate, so that the scanning line GA can be reduced.
  • the display substrate provided by the above embodiment does not need to be provided with a thick insulating layer to reduce parasitic capacitance, which effectively reduces the manufacturing process difficulty of the display substrate and improves the mass production feasibility of the display substrate.
  • the scanning line GA can be preferentially produced in the display substrate manufacturing process, thus ensuring that the substrate is not easily deformed and effectively reducing the occurrence of cracks. risks of.
  • the display device provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

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Abstract

本公开提供一种显示基板和显示装置。所述显示基板包括：基底，设置于所述基底上的多个像素单元和扫描线；所述像素单元包括：多个子像素和遮光层，所述多个子像素沿第一方向依次排列，所述子像素包括相耦接的子像素驱动电路和发光元件，所述子像素驱动电路用于向所述发光元件提供驱动信号；所述遮光层的至少部分位于所述子像素驱动电路与所述基底之间；所述扫描线包括沿所述第一方向延伸的至少部分，所述扫描线与对应的子像素驱动电路耦接；所述扫描线与所述遮光层同层设置。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
目前显示领域较成熟的技术包括液晶显示技术和主动矩阵式有机发光二极管(英文：Organic Light-Emitting Diode，简称OLED)显示技术。OLED显示产品是通过借助电子与空穴直接的复合，激发出各种波长的光谱，从而形成图形。通过OLED显示技术形成的显示装置具有快速的响应速度，同时可以达到对比度最大化，因此OLED显示装置有望成为下一代显示主流产品。
OLED显示器件在应用于大尺寸高分辨率的领域时，像素的布局空间有限，而且受到线宽、线间距等规则的影响，会导致信号线的阻容延迟(RC Delay)过大，从而影响显示器件的性能。
发明内容
本公开的目的在于提供一种显示基板和显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：基底和设置于所述基底上的多个像素单元；所述像素单元包括：
多个子像素，所述多个子像素沿第一方向依次排列，所述子像素包括相耦接的子像素驱动电路和发光元件，所述子像素驱动电路用于向所述发光元件提供驱动信号；
遮光层，所述遮光层的至少部分位于所述子像素驱动电路与所述基底之间；
所述显示基板还包括扫描线，所述扫描线包括沿所述第一方向延伸的至少部分，所述扫描线与对应的子像素驱动电路耦接；所述扫描线与所述遮光层同层设置。
可选的，所述扫描线在垂直于所述基底的方向上的厚度d满足：0.5μm ≤d≤1.5μm。
可选的，所述扫描线与所述遮光层同层同材料设置。
可选的，所述显示基板还包括：
扫描辅助线，所述扫描辅助线位于对应的所述扫描线背向所述基底的一侧，所述扫描辅助线与对应的所述扫描线耦接，所述扫描辅助线与对应的所述子像素中的子像素驱动电路耦接。
可选的，所述扫描辅助线包括：第一扫描辅助图形，第二扫描辅助图形和第三扫描辅助图形，所述第三扫描辅助图形位于所述第一扫描辅助图形与所述第二扫描辅助图形之间；所述第一扫描辅助图形和所述第二扫描辅助图形分别与对应的子像素中的子像素驱动电路耦接；所述第三扫描辅助图形分别与对应的所述扫描线，所述第一扫描辅助图形和所述第二扫描辅助图形耦接；
所述第三扫描辅助图形耦接的扫描线包括沿第二方向排列的第一边界和第二边界，所述第二方向与所述第一方向相交；所述第一边界在所述基底上的正投影与所述第一扫描辅助图形在所述基底上的正投影部分交叠，所述第二边界在所述基底上的正投影与所述第二扫描辅助图形在所述基底上的正投影部分交叠。
可选的，所述显示基板还包括：
数据线，所述数据线包括沿第二方向延伸的至少部分，所述第二方向与所述第一方向相交；所述数据线与对应的子像素驱动电路耦接；
数据辅助线，所述数据辅助线与对应的所述数据线耦接，所述数据辅助线位于对应的所述数据线与所述基底之间，所述数据辅助线与所述遮光层同层同材料设置。
可选的，所述扫描线包括第一扫描部分和第二扫描部分，所述第一扫描部分和所述第二扫描部分均沿所述第一方向延伸，在垂直于所述第一方向的方向上，所述第一扫描部分的宽度小于所述第二扫描部分的宽度，所述第一扫描部分在所述基底上的正投影与所述数据线在所述基底上的正投影至少部分交叠。
可选的，所述数据辅助线包括至少两个数据辅助图形，所述至少两个数 据辅助图形沿所述第二方向排列，所述至少两个数据辅助图形分别与对应的数据线耦接。
可选的，所述扫描线在所述基底上的正投影位于相邻的所述数据辅助图形在所述基底上的正投影之间。
可选的，所述显示基板还包括：
电源线，所述电源线包括沿所述第二方向延伸的至少部分，所述电源线与对应的子像素驱动电路耦接；
电源辅助线，所述电源辅助线与对应的所述电源线耦接，所述电源辅助线位于所述电源线与所述基底之间，所述电源辅助线与所述遮光层同层同材料设置。
可选的，所述电源辅助线包括至少两个电源辅助图形，所述至少两个电源辅助图形沿所述第二方向排列，所述至少两个电源辅助图形分别与对应的电源线耦接。
可选的，至少一条所述扫描线在所述基底上的正投影，位于相邻的所述电源辅助图形在所述基底上的正投影之间。
可选的，所述显示基板还包括：
感测线，所述感测线包括沿所述第二方向延伸的至少部分；
感测辅助线，所述感测辅助线与所述感测线耦接，所述感测辅助线位于所述感测线与所述基底之间，所述感测辅助线与所述遮光层同层同材料设置；所述感测辅助线包括沿所述第一方向延伸的至少部分，所述感测辅助线与对应的子像素驱动电路耦接。
可选的，所述子像素驱动电路包括：
驱动晶体管，所述驱动晶体管的第一极与所述电源线耦接，所述驱动晶体管的第二极与所述发光元件耦接；
写入晶体管，所述写入晶体管的栅极与所述扫描线耦接，所述写入晶体管的第一极与所述数据线耦接，所述写入晶体管的第二极与所述驱动晶体管的栅极耦接；
感测晶体管，所述感测晶体管的栅极与所述扫描线耦接，所述感测晶体管的第一极与所述驱动晶体管的第二极耦接，所述感测晶体管的第二极与所 述感测线耦接；
存储电容，所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与所述驱动晶体管的第二极耦接。
可选的，所述写入晶体管包括写入有源层，所述感测晶体管包括感测有源层，在同一个像素单元中，所述写入有源层在所述基底上的正投影，位于所述写入晶体管耦接的所述扫描线在所述基底上的正投影的第一侧，所述感测有源层在所述基底上的正投影位于该扫描线在所述基底上的正投影的第二侧，所述第一侧和所述第二侧沿所述第二方向相对。
可选的，所述驱动晶体管包括驱动有源层，所述写入有源层在所述基底上的正投影的至少部分，位于所述驱动有源层在所述基底上的正投影与所述扫描线在所述基底上的正投影之间。
可选的，所述子像素还包括像素界定层，所述像素界定层限定出像素开口，在同一个子像素中，所述感测有源层在所述基底上的正投影位于所述像素开口在所述基底上的正投影与所述扫描线在所述基底上的正投影之间。
可选的，所述第一极板与所述驱动有源层同层同材料设置，所述第二极板与所述数据线同层同材料设置，所述第二极板与所述遮光层耦接，所述第二极板在所述基底上正投影与所述遮光层在所述基底上的正投影至少部分交叠。
可选的，所述驱动有源层包括驱动沟道部分，所述遮光层在所述基底上的正投影，与所述驱动沟道部分在所述基底上的正投影至少部分交叠。
基于上述显示基板的技术方案，本公开的第二方面提供了一种显示装置，包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的子像素驱动电路的电路图；
图2为本公开实施例提供的像素单元的布局示意图；
图3为图2中遮光层的布局示意图；
图4为图2中有源层的布局示意图；
图5为图2中栅金属层的布局示意图；
图6为本公开实施例提供的CNT工艺形成的过孔示意图；
图7为本公开实施例提供的对层间绝缘层构图形成的过孔示意图；
图8为图2中源漏金属层的布局示意图；
图9为图2中色阻图形的布局示意图；
图10为图2中阳极层的布局示意图；
图11为图2中像素开口区的布局示意图；
图12为图2中遮光层和有源层的布局示意图；
图13为在图12中增加栅金属层的示意图；
图14为在图13中增加CNT工艺的过孔的示意图；
图15为在图14中增加层间绝缘层过孔的示意图；
图16为在图15中增加源漏金属层的示意图；
图17为在图16中增加色阻图形的示意图；
图18为在图17中增加阳极层的示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板和显示装置，下面结合说明书附图进行详细描述。
请参阅图1，图2和图3，本公开实施例提供了一种显示基板，包括：基底和设置于所述基底上的多个像素单元；所述像素单元包括：
多个子像素，所述多个子像素沿第一方向依次排列，所述子像素包括相耦接的子像素驱动电路和发光元件EL，所述子像素驱动电路用于向所述发光元件EL提供驱动信号；
遮光层10，所述遮光层10的至少部分位于所述子像素驱动电路与所述基底之间；
所述显示基板还包括扫描线GA，所述扫描线GA包括沿所述第一方向延 伸的至少部分，所述扫描线GA与对应的子像素驱动电路耦接；所述扫描线GA与所述遮光层10同层设置。
示例性的，所述多个像素单元呈阵列分布在所述基底上。所述多个像素单元能够划分为多行像素单元和多列像素单元，所述多行像素单元沿第二方向排列，每行像素单元均包括沿第一方向排列的多个像素单元；所述多列像素单元沿所述第一方向排列，每列像素单元均包括沿所述第二方向排列的多个像素单元。
示例性的，所述第一方向包括水平方向，所述第二方向包括竖直方向。
示例性的，所述像素单元包括红色子像素，绿色子像素，蓝色子像素和白色子像素。
示例性的，所述子像素包括子像素驱动电路和发光元件EL，所述子像素驱动电路与所述发光元件EL中的阳极耦接，用于为所述阳极提供驱动信号。示例性的，所述子像素驱动电路包括3T1C(即3个晶体管和1个电容)结构，但不仅限于此。所述发光元件EL的阴极接收负电源信号VSS。
如图2至图11，图17和图18所示，示例性的，所述显示基板包括沿远离所述基底的方向依次形成的，层叠设置的遮光层10，有源层，栅极绝缘层，栅金属层，层间绝缘层，源漏金属层，钝化层，彩膜层50，平坦层，阳极层60，像素界定层，发光功能层和阴极层。像素界定层能够限定出像素开口，该像素开口所在的区域形成像素开口区30。
需要说明，图6和图14中示意了CNT过孔工艺形成的过孔。图7和图15中示意了对层间绝缘层进行mask形成的过孔。
在形成层间绝缘层后，先进行CNT工艺，在所述层间绝缘层上制作没有贯穿所述层间绝缘层的半过孔，然后对所述层间绝缘层进行一次mask，形成贯穿所述层间绝缘层的过孔。进行层间绝缘层mask后，一部分过孔能够贯穿层间绝缘层并延伸至遮光层，另一部分仅贯穿层间绝缘层。
示例性的，所述遮光层10的至少部分位于所述子像素驱动电路包括的有源层与所述基底之间。
示例性的，所述遮光层10在所述基底上的正投影，与所述子像素驱动电路中部分晶体管包括的有源层在所述基底上的正投影至少部分交叠。
示例性的，所述遮光层10采用导电金属材料制作，如：金属铜。
示例性的，所述显示基板包括多条扫描线GA，所述多条扫描线GA与所述多行像素单元一一对应，所述扫描线GA与对应的一行像素单元中各子像素包括的子像素驱动电路分别耦接。
示例性的，所述扫描线GA用于传输扫描信号。所述扫描线GA与子像素驱动电路中相应的晶体管的栅极耦接，用于将所述扫描信号传输至相应的晶体管的栅极。
示例性的，所述扫描线GA沿所述第一方向延伸。所述扫描线GA沿所述第一方向延伸是指：所述扫描线GA包括主要部分和与所述主要部分连接的次要部分，所述主要部分是线、线段或条形状体，所述主要部分沿所述第一方向延展，且所述主要部分沿所述第一方向延展的长度大于次要部分沿其它方向伸展的长度。
根据本公开实施例提供的显示基板可知，本公开实施例提供的显示基板中，将所述扫描线GA与所述遮光层10同层设置，使得所述扫描线GA靠近所述基底，这样可以通过增加所述扫描线GA的厚度，降低所述扫描线GA的电阻，从而有效降低了所述扫描线GA的负载，避免了所述扫描线GA在传输扫描信号时出现过大的信号延迟，兼容了高刷新频率，优化了显示效果，保证了所述显示基板的工作稳定性，提升了显示基板的寿命。
而且，由于所述扫描线GA靠近基底，使得在垂直于基底的方向上，所述扫描线GA与所述显示基板中其他导电结构之间具有较大的距离，能够减小所述扫描线GA与其他导电结构之间形成的寄生电容。因此，本公开实施例提供的显示基板无需设置较厚的绝缘层来降低寄生电容，有效降低了所述显示基板的制作工艺难度，提高了所述显示基板的量产可行性。
另外，由于较厚的扫描线GA靠近所述基底，使得所述扫描线GA能够在显示基板制作工艺流程中优先制作，从而很好的保证了所述基底不易发生形变，以及有效降低了发生破片的风险。
在一些实施例中，所述扫描线GA在垂直于所述基底的方向上的厚度d满足：0.5μm≤d≤1.5μm。
示例性的，所述扫描线GA在垂直于所述基底的方向上的厚度d包括1μm。
将所述扫描线GA设置在上述厚度范围，有效降低了所述扫描线GA的负载，避免了所述扫描线GA在传输扫描信号时出现过大的信号延迟，兼容了高刷新频率，优化了显示效果，保证了所述显示基板的工作稳定性，提升了显示基板的寿命。
如图3所示，在一些实施例中，所述扫描线GA与所述遮光层10同层同材料设置。
上述将所述扫描线GA与所述遮光层10同层同材料设置，使得所述扫描线GA与所述遮光层10能够在同一次构图工艺中同时形成，从而有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
如图3，图5和图13所示，在一些实施例中，所述显示基板还包括：
扫描辅助线GAF，所述扫描辅助线GAF位于对应的所述扫描线GA背向所述基底的一侧，所述扫描辅助线GAF与对应的所述扫描线GA耦接，所述扫描辅助线GAF与对应的所述子像素中的子像素驱动电路耦接。
示例性的，所述显示基板包括多条扫描辅助线GAF，所述扫描辅助线GAF与所述显示基板包括的子像素一一对应。
示例性的，沿所述第一方向位于同一行的多条扫描辅助线GAF与对应的同一条扫描线GA分别耦接。示例性的，沿所述第一方向位于同一行的多条扫描辅助线GAF间隔排列。示例性的，沿所述第一方向位于同一行的多条扫描辅助线GAF形成为一体结构。
示例性的，所述扫描辅助线GAF采用所述栅金属层制作。
示例性的，所述扫描辅助线GAF与对应耦接的子像素驱动电路中的晶体管的栅极形成为一体结构。
示例性的，所述扫描辅助线GAF在所述基底上的正投影，与所述扫描线GA在所述基底上的正投影具有交叠区域。
如图8所示，示例性的，所述像素单元还包括多个第一导电连接部41，所述第一导电连接部41包括沿所述第一方向延伸的至少部分，所述第一导电连接部41分别与所述扫描线GA和对应的所述扫描辅助线GAF耦接。示例性的，所述第一导电连接部41位于所述扫描辅助线GAF背向所述基底的一侧。示例性的，所述第一导电连接部41与所述显示基板中的数据线DA同层同材 料设置。
上述设置所述像素单元还包括与所述扫描线GA耦接的扫描辅助线GAF，不仅保证了所述扫描线GA与相应的子像素驱动电路的连接性能，还进一步降低了所述扫描线GA的电阻，更好的避免了所述扫描线GA在传输扫描信号时出现过大的信号延迟，更好的兼容了高刷新频率，优化了显示效果，保证了所述显示基板的工作稳定性，提升了显示基板的寿命。
如图2，图5和图13所示，在一些实施例中，所述扫描辅助线GAF包括：第一扫描辅助图形210，第二扫描辅助图形211和第三扫描辅助图形212；所述第三扫描辅助图形212位于所述第一扫描辅助图形210与所述第二扫描辅助图形211之间；所述第一扫描辅助图形210和所述第二扫描辅助图形211分别与对应的子像素中的子像素驱动电路耦接；所述第三扫描辅助图形212分别与对应的所述扫描线GA，所述第一扫描辅助图形210和所述第二扫描辅助图形211耦接；
所述第三扫描辅助图形212耦接的扫描线GA包括沿第二方向排列的第一边界和第二边界，所述第二方向与所述第一方向相交；所述第一边界在所述基底上的正投影与所述第一扫描辅助图形210在所述基底上的正投影部分交叠，所述第二边界在所述基底上的正投影与所述第二扫描辅助图形211在所述基底上的正投影部分交叠。
示例性的，所述第一扫描辅助图形210，所述第二扫描辅助图形211和所述第三扫描辅助图形212形成为一体结构。
示例性的，所述第一扫描辅助图形210复用为感测晶体管T2的栅极，所述第二扫描辅助图形211复用为写入晶体管T1的栅极。
示例性的，所述第一扫描辅助图形210包括沿所述第二方向延伸的至少部分，所述第二扫描辅助图形211包括沿所述第二方向延伸的至少部分，所述第三扫描辅助图形212包括沿所述第一方向延伸的至少部分。
示例性的，所述第三扫描辅助图形212在所述基底上的正投影，位于所述扫描线GA在所述基底上的正投影的内部。
示例性的，所述第一导电连接部41分别与所述扫描线GA和对应的所述第三扫描辅助图形212耦接。
示例性的，所述第一边界在所述基底上的正投影与所述第一扫描辅助图形210在所述基底上的正投影部分交叠，所述第二边界在所述基底上的正投影与所述第二扫描辅助图形211在所述基底上的正投影部分交叠。
示例性的，所述第一边界在所述基底上的正投影与所述第三扫描辅助图形212在所述基底上的正投影部分交叠，所述第二边界在所述基底上的正投影与所述第三扫描辅助图形212在所述基底上的正投影部分交叠。
上述设置所述扫描辅助线GAF包括：第一扫描辅助图形210，第二扫描辅助图形211和第三扫描辅助图形212，不仅很好的保证了所述扫描线GA与所述子像素驱动电路之间的连接性能，还有效降低了所述显示基板的布局难度。
如图1，图2，图3，图8和图16所示，在一些实施例中，所述显示基板还包括：
数据线DA，所述数据线DA包括沿第二方向延伸的至少部分，所述第二方向与所述第一方向相交；所述数据线DA与对应的子像素驱动电路耦接；
数据辅助线DAF，所述数据辅助线DAF与对应的所述数据线耦接，所述数据辅助线DAF位于对应的所述数据线DA与所述基底之间，所述数据辅助线DAF与所述遮光层10同层同材料设置。
示例性的，所述数据线DA用于传输数据信号。所述数据线DA与子像素驱动电路中相应的晶体管耦接，用于将所述数据信号传输至相应的晶体管。
示例性的，所述显示基板还包括多条数据线DA。所述显示基板包括的多个子像素，所述多个子像素划分为多列子像素列，所述多列子像素列与所述多条数据线DA一一对应。所述数据线DA与对应的一列子像素列中各子像素驱动电路分别耦接。
示例性的，所述显示基板包括多条数据辅助线DAF，每条数据线DA对应多条所述数据辅助线DAF，所述数据线DA分别与对应的多条所述数据辅助线DAF耦接。示例性的，每条数据线DA对应多条所述数据辅助线DAF沿所述第二方向依次间隔排列。
示例性的，所述数据线DA采用所述源漏金属层制作。
示例性的，所述数据辅助线DAF在所述基底上的正投影，与对应的所述 数据线DA在所述基底上的正投影至少部分交叠，所述数据辅助线DAF与对应的数据线DA在交叠处通过过孔耦接。
示例性的，所述数据辅助线DAF在所述基底上的正投影，位于对应的所述数据线DA在所述基底上的正投影的内部。
示例性的，所述数据辅助线DAF包括沿所述第二方向延伸的至少部分。
上述设置所述数据辅助线DAF与所述数据线DA耦接，有效降低了所述数据线DA的电阻，从而有效降低了所述数据线DA的负载，避免了所述数据线DA在传输数据信号时出现延迟，兼容了高刷新频率，保证了所述显示基板的工作稳定性。
而且，由于所述遮光层10在垂直于所述基底的方向上的厚度较厚，将所述数据辅助线DAF与所述遮光层10同层同材料设置，能够更好的降低所述数据线DA的电阻。
另外，上述将所述数据辅助线DAF与所述遮光层10同层同材料设置，使得所述数据辅助线DAF能够与所述遮光层10在同一次构图工艺中同时形成，从而有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
如图1，图2，图3，图8和图16所示，在一些实施例中，所述扫描线GA包括第一扫描部分201和第二扫描部分202，所述第一扫描部分201和所述第二扫描部分202均沿所述第一方向延伸，在垂直于所述第一方向的方向上，所述第一扫描部分201的宽度d1小于所述第二扫描部分202的宽度d2，所述第一扫描部分201在所述基底上的正投影与所述数据线DA在所述基底上的正投影至少部分交叠。
示例性的，所述第一扫描部分201与所述第二扫描部分202形成为一体结构。
示例性的，同一条扫描线GA中，所述第一扫描部分201与所述第二扫描部分202沿所述第一方向交替设置。
示例性的，在平行于所述基底的方向上，在垂直于所述第一方向的方向上，所述第一扫描部分201的宽度小于所述第二扫描部分202的宽度。
示例性的，所述第一扫描部分201在所述基底上的正投影与所述数据线DA在所述基底上的正投影至少部分交叠；所述第二扫描部分202在所述基底 上的正投影与所述数据线DA在所述基底上的正投影至少部分交叠。
示例性的，所述第一扫描部分201在所述基底上的正投影与所述数据线DA在所述基底上的正投影至少部分交叠；所述第二扫描部分202在所述基底上的正投影与所述数据线DA在所述基底上的正投影不交叠。
示例性的，所述第一扫描部分201在所述基底上的正投影与电源线VDD在所述基底上的正投影至少部分交叠。
上述设置所述第一扫描部分201的宽度小于所述第二扫描部分202的宽度，所述第一扫描部分201在所述基底上的正投影与所述数据线DA在所述基底上的正投影至少部分交叠，有利于减小所述扫描线GA与所述数据线DA之间的交叠面积，减小所述扫描线GA与所述数据线DA之间形成的寄生电容。
如图3所示，在一些实施例中，所述数据辅助线DAF包括至少两个数据辅助图形DAF1，所述至少两个数据辅助图形DAF1沿所述第二方向排列，所述至少两个数据辅助图形DAF1分别与对应的数据线DA耦接。
示例性的，所述至少两个数据辅助图形DAF1沿所述第二方向间隔排列。
示例性的，所述数据辅助图形DAF1包括沿所述第二方向延伸的至少部分。
示例性的，所述数据辅助图形DAF1在所述基底上的正投影，与对应的所述数据线DA在所述基底上的正投影至少部分交叠。
示例性的，所述数据辅助图形DAF1在所述基底上的正投影，位于对应的所述数据线DA在所述基底上的正投影的内部。
上述设置所述数据辅助线DAF包括至少两个数据辅助图形DAF1，不仅能够有效降低所述数据线DA的电阻，还能够降低所述数据辅助线DAF与其他导电结构(如：遮光层10，以及与所述遮光层10同层设置的导电结构)之间发生短路的风险，有效降低了所述数据辅助图形DAF1的布局难度。
如图1，图2，图3，图8和图16所示，在一些实施例中，所述扫描线GA在所述基底上的正投影位于相邻的所述数据辅助图形DAF1在所述基底上的正投影之间。
上述布局所述扫描线GA在所述基底上的正投影位于相邻的所述数据辅助图形DAF1在所述基底上的正投影之间，不仅能够降低所述显示基板的布局 难度，还有利于保证显示基板的信赖性和稳定性。
如图2，图3，图8和图16所示，在一些实施例中，所述显示基板还包括：
电源线VDD，所述电源线VDD包括沿所述第二方向延伸的至少部分，所述电源线VDD与对应的子像素驱动电路耦接；
电源辅助线VDDF，所述电源辅助线VDDF与对应的所述电源线VDD耦接，所述电源辅助线VDDF位于所述电源线VDD与所述基底之间，所述电源辅助线VDDF与所述遮光层10同层同材料设置。
示例性的，所述电源线VDD用于传输电源信号(如：正电源信号)。所述电源线VDD与子像素驱动电路中相应的晶体管耦接，用于将所述电源信号传输至相应的晶体管。
示例性的，所述电源线VDD采用所述源漏金属层制作。
示例性的，所述电源辅助线VDDF在所述基底上的正投影，与对应的所述电源线VDD在所述基底上的正投影至少部分交叠，所述电源辅助线VDDF与对应的电源线VDD在交叠处通过过孔耦接。
示例性的，所述电源辅助线VDDF在所述基底上的正投影，位于对应的所述电源线VDD在所述基底上的正投影的内部。
示例性的，所述电源辅助线VDDF包括沿所述第二方向延伸的至少部分。
上述设置所述电源辅助线VDDF与所述电源线VDD耦接，有效降低了所述电源线VDD的电阻，从而有效降低了所述电源线VDD的负载。
而且，由于所述遮光层10在垂直于所述基底的方向上的厚度较厚，将所述电源辅助线VDDF与所述遮光层10同层同材料设置，能够更好的降低所述电源线VDD的电阻。
另外，上述将所述电源辅助线VDDF与所述遮光层10同层同材料设置，使得所述电源辅助线VDDF能够与所述遮光层10在同一次构图工艺中同时形成，从而有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
如图2，图3，图8和图16所示，在一些实施例中，所述电源辅助线VDDF包括至少两个电源辅助图形VDDF1，所述至少两个电源辅助图形VDDF1沿所述第二方向排列，所述至少两个电源辅助图形VDDF1分别与对应的电源线VDD 耦接。
示例性的，所述至少两个电源辅助图形VDDF1沿所述第二方向间隔排列。
示例性的，所述电源辅助图形VDDF1包括沿所述第二方向延伸的至少部分。
示例性的，所述电源辅助图形VDDF1在所述基底上的正投影，与对应的所述电源线VDD在所述基底上的正投影至少部分交叠。
示例性的，所述电源辅助图形VDDF1在所述基底上的正投影，位于对应的所述电源线VDD在所述基底上的正投影的内部。
上述设置所述电源辅助线VDDF包括至少两个电源辅助图形VDDF1，不仅能够有效降低所述电源线VDD的电阻，还能够降低所述电源辅助线VDDF与其他导电结构(如：遮光层10，以及与所述遮光层10同层设置的导电结构)之间发生短路的风险，有效降低了所述电源辅助图形VDDF1的布局难度。
如图2，图3，图8和图16所示，在一些实施例中，至少一条所述扫描线GA在所述基底上的正投影，位于相邻的所述电源辅助图形VDDF1在所述基底上的正投影之间。
上述布局所述扫描线GA在所述基底上的正投影，位于相邻的所述电源辅助图形VDDF1在所述基底上的正投影之间，不仅能够降低所述显示基板的布局难度，还有利于保证显示基板的信赖性和稳定性。
如图2，图3，图8和图16所示，在一些实施例中，所述显示基板还包括：
感测线SE，所述感测线SE包括沿所述第二方向延伸的至少部分；
感测辅助线SEF，所述感测辅助线SEF与所述感测线SE耦接，所述感测辅助线SEF位于所述感测线SE与所述基底之间，所述感测辅助线SEF与所述遮光层10同层同材料设置；所述感测辅助线SEF包括沿所述第一方向延伸的至少部分，所述感测辅助线SEF与对应的子像素驱动电路耦接。
示例性的，所述显示基板包括多条感测线SE，所述显示基板中的多个像素单元划分为多列像素单元列，所述多条感测线SE与多列像素单元列一一对应，所述感测线SE与对应的像素单元列中包括的各子像素驱动电路分别耦接。
示例性的，所述感测线SE采用源漏金属层制作。
示例性的，所述感测线SE能够在写入数据信号的时段，提供基准信号，用于对发光元件EL的阳极层60进行复位。所述感测线SE还能够在感测时段，传输从所述阳极层60感测到的感测信号。
示例性的，感测辅助线SEF包括沿所述第一方向延伸的至少部分。
示例性的，所述显示基板包括多条感测辅助线SEF，所述多条感测辅助线SEF与所述显示基板中的多个像素单元一一对应，所述感测辅助线SEF与对应的像素单元中的各子像素驱动电路和对应的感测线SE分别耦接。
示例性的，所述感测辅助线SEF在所述基底上的正投影，与对应的所述感测线SE在所述基底上的正投影至少部分交叠，在交叠处，所述感测辅助线SEF与所述感测线SE相耦接。
示例性的，所述感测辅助线SEF与对应的所述像素单元中各子像素驱动电路包括的相应晶体管分别耦接。
上述设置所述感测辅助线SEF与所述感测线SE耦接，有效降低了所述感测线SE的电阻，从而有效降低了所述感测线SE的负载。
而且，由于所述遮光层10在垂直于所述基底的方向上的厚度较厚，将所述感测辅助线SEF与所述遮光层10同层同材料设置，能够更好的降低所述感测线SE的电阻。
另外，上述将所述感测辅助线SEF与所述遮光层10同层同材料设置，使得所述感测辅助线SEF能够与所述遮光层10在同一次构图工艺中同时形成，从而有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
上述实施例提供的显示基板中，在不需要新增加制程的前提下，有效降低了所述扫描线GA，所述数据线DA，所述感测线SE和所述电源线VDD的电阻，改善了信号线在传输相应信号时出现的延迟现象。同时还很好的减少了所述电源线VDD在传输电源信号时的IR Drop。
如图1，图2，和图13所示，在一些实施例中，所述子像素驱动电路包括：
驱动晶体管T3，所述驱动晶体管T3的第一极与所述电源线VDD耦接，所述驱动晶体管T3的第二极与所述发光元件EL耦接；
写入晶体管T1，所述写入晶体管T1的栅极与所述扫描线GA耦接，所述写入晶体管T1的第一极与所述数据线DA耦接，所述写入晶体管T1的第二极与所述驱动晶体管T3的栅极T3-G耦接；
感测晶体管T2，所述感测晶体管T2的栅极与所述扫描线GA耦接，所述感测晶体管T2的第一极与所述驱动晶体管T3的第二极耦接，所述感测晶体管T2的第二极与所述感测线SE耦接；
存储电容Cst，所述存储电容Cst的第一极板Cst1与所述驱动晶体管T3的栅极T3-G耦接，所述存储电容Cst的第二极板Cst2与所述驱动晶体管T3的第二极耦接。
需要说明，如图4所示，每个像素单元中，至少两个子像素包括的存储电容Cst的第一极板Cst1面积可以不同，以适应不同子像素对存储电容容值的需求。
示例性的，所述驱动晶体管T3的第一极与所述电源线VDD耦接，所述驱动晶体管T3的第二极与所述发光元件EL的阳极层60耦接。
示例性的，所述写入晶体管T1和所述感测晶体管T2均作为开关晶体管。
示例性的，在所述扫描线GA提供的扫描信号的控制下，所述写入晶体管T1导通或截止。在所述扫描线GA提供的扫描信号的控制下，所述感测晶体管T2导通或截止。
示例性的，所述子像素驱动电路包括3T1C结构，所述像素单元包括一条扫描线GA。
示例性的，所述存储电容Cst的第一极板Cst1在所述基底上的正投影，与所述存储电容Cst的第二极板Cst2在所述基底上的正投影至少部分交叠。
通过降低所述扫描线GA的负载，能够避免所述扫描线GA传输扫描信号时发生延，保证了数据线DA向驱动晶体管T3的栅极T3-G写入数据信号的充电率，使得所述显示基板能够满足高刷新频率的要求。同时还保证了感测信号和基准信号的传输。
如2至图4所示，在一些实施例中，所述写入晶体管T1包括写入有源层T1-S，所述感测晶体管T2包括感测有源层T2-S，在同一个像素单元中，所述写入有源层T1-S在所述基底上的正投影，位于所述写入晶体管T1耦接的 所述扫描线GA在所述基底上的正投影的第一侧，所述感测有源层T2-S在所述基底上的正投影位于该扫描线GA在所述基底上的正投影的第二侧，所述第一侧和所述第二侧沿所述第二方向相对。
示例性的，在同一个像素单元中，所述扫描线GA在所述基底上的正投影的至少部分，位于所述写入有源层T1-S在所述基底上的正投影与所述感测有源层T2-S在所述基底上的正投影之间。
示例性的，所述写入有源层T1-S和所述感测有源层T2-S均采用透明材料制作。示例性的，所述写入有源层T1-S和所述感测有源层T2-S均采用透明金属氧化物材料制作。
示例性的，所述写入有源层T1-S包括沿所述第一方向延伸的至少部分。
示例性的，所述写入有源层T1-S与所述存储电容Cst的第一极板Cst1形成为一体结构。
示例性的，所述感测有源层T2-S包括沿所述第一方向延伸的至少部分。
示例性的，所述扫描线GA在所述基底上的正投影，与所述写入有源层T1-S在所述基底上的正投影不交叠。
示例性的，所述扫描线GA在所述基底上的正投影，与所述感测有源层T2-S在所述基底上的正投影不交叠。
上述设置所述扫描线GA在所述基底上的正投影，位于所述写入有源层T1-S在所述基底上的正投影与所述感测有源层T2-S在所述基底上的正投影之间，有利于在有限的布局空间内降低所述像素单元的布局难度，保证所述显示基板具有较高的分辨率。
如2至图4所示，在一些实施例中，设置所述驱动晶体管T3包括驱动有源层T3-S，所述写入有源层T1-S在所述基底上的正投影的至少部分，位于所述驱动有源层T3-S在所述基底上的正投影与所述扫描线GA在所述基底上的正投影之间。
示例性的，所述驱动有源层T3-S包括沿所述第二方向延伸的至少部分。
示例性的，所述驱动有源层T3-S采用透明材料制作。示例性的，所述驱动有源层T3-S采用透明金属氧化物材料制作。
示例性的，所述驱动晶体管T3的栅极T3-G包括沿所述第一方向延伸的 至少部分。
上述设置方式有利于在有限的布局空间内降低所述像素单元的布局难度，保证所述显示基板具有较高的分辨率。
如图2和图11所示，在一些实施例中，所述子像素还包括像素界定层，所述像素界定层限定出像素开口，在同一个子像素中，所述感测有源层T2-S在所述基底上的正投影位于所述像素开口在所述基底上的正投影与所述扫描线GA在所述基底上的正投影之间。
示例性的，所述像素开口所在的位置形成像素开口区30，所述像素开口区30包括沿所述第二方向延伸的至少部分。
示例性的，所述像素开口在所述基底上的正投影，与所述子像素驱动电路在所述基底上的正投影不交叠。
上述设置在同一个子像素中，所述感测有源层T2-S在所述基底上的正投影位于所述像素开口在所述基底上的正投影与所述扫描线GA在所述基底上的正投影之间；使得所述像素开口在所述基底上的正投影，与所述子像素驱动电路在所述基底上的正投影沿所述第二方向排列，能够保证所述像素开口占用足够大的布局空间，保证了显示基板的像素开口率。同时上述设置方式还降低了所述像素单元的布局难度。
如图4所示，在一些实施例中，所述第一极板Cst1与所述驱动有源层T3-S同层同材料设置，所述第二极板Cst2与所述数据线DA同层同材料设置，所述第二极板Cst2与所述遮光层10耦接，所述第二极板Cst2在所述基底上正投影与所述遮光层10在所述基底上的正投影至少部分交叠。
上述将所述第一极板Cst1与所述驱动有源层T3-S同层同材料设置，使得所述第一极板Cst1能够与所述驱动有源层T3-S在同一次构图工艺中同时形成，从而有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
同样的，上述将所述第二极板Cst2与所述数据线DA同层同材料设置，使得所述第二极板Cst2能够与所述数据线DA在同一次构图工艺中同时形成，从而有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
上述设置方式有利于提升所述存储电容Cst的工作稳定性。
如图2至图4所示，在一些实施例中，所述驱动有源层T3-S包括驱动沟道部分，所述遮光层10在所述基底上的正投影，与所述驱动沟道部分在所述基底上的正投影至少部分交叠。
示例性的，所述驱动有源层T3-S包括：驱动沟道部分，用于形成所述驱动晶体管T3的第一极的部分，以及用于形成所述驱动晶体管T3的第二极的部分。所述驱动沟道部分在所述基底上的正投影位于所述驱动晶体管T3的栅极T3-G在所述基底上的正投影的内部。
上述设置所述遮光层10在所述基底上的正投影，与所述驱动沟道部分在所述基底上的正投影至少部分交叠，能够有效降低所述驱动晶体管T3受漏光照的影响，保证了所述驱动晶体管T3的工作稳定性。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
示例性的，所述显示装置包括超大尺寸，高分辨率，底发射OLED显示装置。示例性的，所述显示装置包括有源矩阵有机发光二极管显示装置。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
上述实施例提供的显示基板中，将所述扫描线GA与所述遮光层10同层设置，使得所述扫描线GA靠近所述基底，这样可以通过增加所述扫描线GA的厚度，降低所述扫描线GA的电阻，从而有效降低了所述扫描线GA的负载，避免了所述扫描线GA在传输扫描信号时出现过大的信号延迟，兼容了高刷新频率，优化了显示效果，保证了所述显示基板的工作稳定性，提升了显示基板的寿命。而且，由于所述扫描线GA靠近基底，使得在垂直于基底的方向上，所述扫描线GA与所述显示基板中其他导电结构之间具有较大的距离，能够减小所述扫描线GA与其他导电结构之间形成的寄生电容。因此，上述实施例提供的显示基板无需设置较厚的绝缘层来降低寄生电容，有效降低了所述显示基板的制作工艺难度，提高了所述显示基板的量产可行性。
另外，由于较厚的扫描线GA靠近所述基底，使得所述扫描线GA能够在显示基板制作工艺流程中优先制作，从而很好的保证了所述基底不易发生形变，以及有效降低了发生破片的风险。
因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，包括：基底和设置于所述基底上的多个像素单元；所述像素单元包括：
    多个子像素，所述多个子像素沿第一方向依次排列，所述子像素包括相耦接的子像素驱动电路和发光元件，所述子像素驱动电路用于向所述发光元件提供驱动信号；
    遮光层，所述遮光层的至少部分位于所述子像素驱动电路与所述基底之间；
    所述显示基板还包括扫描线，所述扫描线包括沿所述第一方向延伸的至少部分，所述扫描线与对应的子像素驱动电路耦接；所述扫描线与所述遮光层同层设置。
  2. 根据权利要求1所述的显示基板，其中，所述扫描线在垂直于所述基底的方向上的厚度d满足：0.5μm≤d≤1.5μm。
  3. 根据权利要求1所述的显示基板，其中，所述扫描线与所述遮光层同层同材料设置。
  4. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    扫描辅助线，所述扫描辅助线位于对应的所述扫描线背向所述基底的一侧，所述扫描辅助线与对应的所述扫描线耦接，所述扫描辅助线与对应的所述子像素中的子像素驱动电路耦接。
  5. 根据权利要求4所述的显示基板，其中，所述扫描辅助线包括：第一扫描辅助图形，第二扫描辅助图形和第三扫描辅助图形，所述第三扫描辅助图形位于所述第一扫描辅助图形与所述第二扫描辅助图形之间；所述第一扫描辅助图形和所述第二扫描辅助图形分别与对应的子像素中的子像素驱动电路耦接；所述第三扫描辅助图形分别与对应的所述扫描线，所述第一扫描辅助图形和所述第二扫描辅助图形耦接；
    所述第三扫描辅助图形耦接的扫描线包括沿第二方向排列的第一边界和第二边界，所述第二方向与所述第一方向相交；所述第一边界在所述基底上的正投影与所述第一扫描辅助图形在所述基底上的正投影部分交叠，所述第 二边界在所述基底上的正投影与所述第二扫描辅助图形在所述基底上的正投影部分交叠。
  6. 根据权利要求4所述的显示基板，其中，所述显示基板还包括：
    数据线，所述数据线包括沿第二方向延伸的至少部分，所述第二方向与所述第一方向相交；所述数据线与对应的子像素驱动电路耦接；
    数据辅助线，所述数据辅助线与对应的所述数据线耦接，所述数据辅助线位于对应的所述数据线与所述基底之间，所述数据辅助线与所述遮光层同层同材料设置。
  7. 根据权利要求6所述的显示基板，其中，所述扫描线包括第一扫描部分和第二扫描部分，所述第一扫描部分和所述第二扫描部分均沿所述第一方向延伸，在垂直于所述第一方向的方向上，所述第一扫描部分的宽度小于所述第二扫描部分的宽度，所述第一扫描部分在所述基底上的正投影与所述数据线在所述基底上的正投影至少部分交叠。
  8. 根据权利要求6所述的显示基板，其中，所述数据辅助线包括至少两个数据辅助图形，所述至少两个数据辅助图形沿所述第二方向排列，所述至少两个数据辅助图形分别与对应的数据线耦接。
  9. 根据权利要求8所述的显示基板，其中，所述扫描线在所述基底上的正投影位于相邻的所述数据辅助图形在所述基底上的正投影之间。
  10. 根据权利要求6所述的显示基板，其中，所述显示基板还包括：
    电源线，所述电源线包括沿所述第二方向延伸的至少部分，所述电源线与对应的子像素驱动电路耦接；
    电源辅助线，所述电源辅助线与对应的所述电源线耦接，所述电源辅助线位于所述电源线与所述基底之间，所述电源辅助线与所述遮光层同层同材料设置。
  11. 根据权利要求10所述的显示基板，其中，所述电源辅助线包括至少两个电源辅助图形，所述至少两个电源辅助图形沿所述第二方向排列，所述至少两个电源辅助图形分别与对应的电源线耦接。
  12. 根据权利要求11所述的显示基板，其中，至少一条所述扫描线在所述基底上的正投影，位于相邻的所述电源辅助图形在所述基底上的正投影之 间。
  13. 根据权利要求10所述的显示基板，其中，所述显示基板还包括：
    感测线，所述感测线包括沿所述第二方向延伸的至少部分；
    感测辅助线，所述感测辅助线与所述感测线耦接，所述感测辅助线位于所述感测线与所述基底之间，所述感测辅助线与所述遮光层同层同材料设置；所述感测辅助线包括沿所述第一方向延伸的至少部分，所述感测辅助线与对应的子像素驱动电路耦接。
  14. 根据权利要求13所述的显示基板，其中，所述子像素驱动电路包括：
    驱动晶体管，所述驱动晶体管的第一极与所述电源线耦接，所述驱动晶体管的第二极与所述发光元件耦接；
    写入晶体管，所述写入晶体管的栅极与所述扫描线耦接，所述写入晶体管的第一极与所述数据线耦接，所述写入晶体管的第二极与所述驱动晶体管的栅极耦接；
    感测晶体管，所述感测晶体管的栅极与所述扫描线耦接，所述感测晶体管的第一极与所述驱动晶体管的第二极耦接，所述感测晶体管的第二极与所述感测线耦接；
    存储电容，所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与所述驱动晶体管的第二极耦接。
  15. 根据权利要求14所述的显示基板，其中，
    所述写入晶体管包括写入有源层，所述感测晶体管包括感测有源层，在同一个像素单元中，所述写入有源层在所述基底上的正投影，位于所述写入晶体管耦接的所述扫描线在所述基底上的正投影的第一侧，所述感测有源层在所述基底上的正投影位于该扫描线在所述基底上的正投影的第二侧，所述第一侧和所述第二侧沿所述第二方向相对。
  16. 根据权利要求15所述的显示基板，其中，所述驱动晶体管包括驱动有源层，所述写入有源层在所述基底上的正投影的至少部分，位于所述驱动有源层在所述基底上的正投影与所述扫描线在所述基底上的正投影之间。
  17. 根据权利要求16所述的显示基板，其中，所述子像素还包括像素界定层，所述像素界定层限定出像素开口，在同一个子像素中，所述感测有源 层在所述基底上的正投影位于所述像素开口在所述基底上的正投影与所述扫描线在所述基底上的正投影之间。
  18. 根据权利要求15所述的显示基板，其中，
    所述第一极板与所述驱动有源层同层同材料设置，所述第二极板与所述数据线同层同材料设置，所述第二极板与所述遮光层耦接，所述第二极板在所述基底上正投影与所述遮光层在所述基底上的正投影至少部分交叠。
  19. 根据权利要求1所述的显示基板，其中，所述驱动有源层包括驱动沟道部分，所述遮光层在所述基底上的正投影，与所述驱动沟道部分在所述基底上的正投影至少部分交叠。
  20. 一种显示装置，包括如权利要求1～19中任一项所述的显示基板。
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CN107799565A (zh) * 2016-08-31 2018-03-13 乐金显示有限公司 用于平板显示器的薄膜晶体管基板
CN108122537A (zh) * 2016-11-30 2018-06-05 乐金显示有限公司 有机发光显示装置

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CN101051645A (zh) * 2007-04-29 2007-10-10 友达光电股份有限公司 像素阵列基板
CN102033370A (zh) * 2009-09-25 2011-04-27 北京京东方光电科技有限公司 液晶显示基板及其制造方法
CN107799565A (zh) * 2016-08-31 2018-03-13 乐金显示有限公司 用于平板显示器的薄膜晶体管基板
CN108122537A (zh) * 2016-11-30 2018-06-05 乐金显示有限公司 有机发光显示装置

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