WO2023130440A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023130440A1
WO2023130440A1 PCT/CN2022/070991 CN2022070991W WO2023130440A1 WO 2023130440 A1 WO2023130440 A1 WO 2023130440A1 CN 2022070991 W CN2022070991 W CN 2022070991W WO 2023130440 A1 WO2023130440 A1 WO 2023130440A1
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WO
WIPO (PCT)
Prior art keywords
substrate
orthographic projection
pixel
power supply
compensation
Prior art date
Application number
PCT/CN2022/070991
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English (en)
French (fr)
Inventor
张跳梅
青海刚
张振华
王梦奇
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000018.4A priority Critical patent/CN116830184A/zh
Priority to PCT/CN2022/070991 priority patent/WO2023130440A1/zh
Publication of WO2023130440A1 publication Critical patent/WO2023130440A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • Organic Light-Emitting Diode (English: Organic Light-Emitting Diode, referred to as: OLED) display is widely used in various fields due to its advantages of thinness, high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency. . With the continuous improvement of consumers' requirements for display quality, displays are gradually developing in the direction of high pixel density.
  • the purpose of the present disclosure is to provide a display substrate and a display device.
  • a first aspect of the present disclosure provides a display substrate, including: a base, a plurality of data lines disposed on the base, and a plurality of first sub-pixels disposed on the base; the first sub-pixels include :
  • the first pixel opening, the orthographic projection of the first pixel opening on the substrate partially overlaps the orthographic projection of a target data line among the plurality of data lines on the substrate;
  • a flattening compensation pattern at least part of the flattening compensation pattern extends along a first direction, an orthographic projection of the flattening compensation pattern on the substrate, and an orthographic projection of the first pixel opening on the substrate At least partially overlapping, the flattening compensation pattern and the target data line are arranged along a second direction, and the second direction intersects the first direction.
  • the first sub-pixel further includes a first sub-pixel driving circuit and a first anode pattern; the flattening compensation pattern is coupled to the first sub-pixel driving circuit and the first anode pattern respectively.
  • the flattening compensation pattern includes a first compensation part and a second compensation part
  • the first compensation portion is a strip-shaped structure extending along the first direction, the orthographic projection of the first compensation portion on the substrate is the same as the orthographic projection of the first pixel opening on the substrate overlap;
  • the orthographic projection of the second compensation portion on the substrate does not overlap with the orthographic projection of the first pixel opening on the substrate.
  • the orthographic projection of the first compensation part on the substrate is located inside the orthographic projection of the first anode pattern on the substrate;
  • the orthographic projection of the second compensation portion on the substrate overlaps with the orthographic projection of the first anode pattern on the substrate.
  • the display substrate further includes a plurality of second sub-pixels, and the second sub-pixels include second pixel openings;
  • Orthographic projections of at least part of the second pixel openings on the substrate are located between orthographic projections of adjacent data lines on the substrate.
  • the display substrate further includes a plurality of third sub-pixels; the third sub-pixels include third pixel openings, and the orthographic projections of the third pixel openings on the substrate are located at adjacent data lines between orthographic projections on said substrate;
  • the plurality of first sub-pixels, the plurality of second sub-pixels and the plurality of third sub-pixels are divided into a plurality of pixel units, each pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel; in a pixel unit, the second pixel opening and the third pixel opening are located in the same column along the first direction, and the first pixel opening is located in another column.
  • the second subpixel includes a second connection part, a second subpixel driving circuit and a second anode pattern, and the second connection part is connected to the second subpixel driving circuit and the second anode respectively.
  • the second connection part and the data line are arranged on the same layer and the same material, and the orthographic projection of the second connection part on the substrate is located between the orthographic projection of the second pixel opening on the substrate and the Between the orthographic projections of the third pixel opening on the substrate; the second pixel opening and the third pixel opening are located in the same column along the first direction.
  • the display substrate further includes:
  • a plurality of power supply compensation lines correspond to at least some of the power supply lines one by one, and the orthographic projection of the power supply compensation lines on the substrate corresponds to the orthographic projection of the corresponding power supply lines on the substrate
  • the projections are at least partially overlapped, and the power supply compensation line is coupled to a corresponding power line.
  • the multiple power supply lines include multiple first power supply lines
  • the multiple power supply compensation lines include multiple first power supply compensation lines
  • the orthographic projection of the first power supply compensation lines on the substrate At least partially overlapping with the orthographic projection of the corresponding first power line on the substrate, the first power compensation line is coupled to the corresponding first power line;
  • the orthographic projection of the first power supply line on the substrate does not overlap with the orthographic projection of the first pixel opening on the substrate, and the orthographic projection of the first power supply compensation line on the substrate, does not overlap with the orthographic projection of the first pixel opening on the substrate.
  • the plurality of power supply lines include a plurality of second power supply lines
  • the plurality of power supply compensation lines include a plurality of second power supply compensation lines
  • the orthographic projection of the second power supply compensation lines on the substrate At least partially overlapping with the orthographic projection of the corresponding second power line on the substrate, the second power compensation line is coupled to the corresponding second power line;
  • the orthographic projection of the second power supply line on the substrate partially overlaps the orthographic projection of the first pixel opening on the substrate, and the orthographic projection of the second power supply compensation line on the substrate, does not overlap with the orthographic projection of the first pixel opening on the substrate.
  • the plurality of power supply lines include a plurality of second power supply lines
  • the plurality of power supply compensation lines include a plurality of second power supply compensation lines
  • the orthographic projection of the second power supply compensation lines on the substrate At least partially overlapping with the orthographic projection of the corresponding second power line on the substrate, the second power compensation line is coupled to the corresponding second power line;
  • the orthographic projection of the second power supply line on the substrate partially overlaps the orthographic projection of the first pixel opening on the substrate, and the orthographic projection of the second power supply compensation line on the substrate, overlapping with an orthographic projection of the first pixel opening on the substrate;
  • At least part of the orthographic projection of the target data line on the substrate is located between the orthographic projection of the second power supply compensation line on the substrate and the orthographic projection of the flattening compensation pattern on the substrate .
  • the plurality of power lines include a plurality of third power lines
  • the orthographic projection of the third power lines on the substrate is at least partly the same as the orthographic projection of the second pixel opening on the substrate.
  • the display substrate further includes:
  • a plurality of initialization compensation patterns, at least part of the initialization compensation patterns extend along the first direction; adjacent first initialization signal lines are coupled through at least one initialization compensation pattern.
  • the plurality of power lines includes a plurality of second power lines; the orthographic projection of the initialization compensation pattern on the substrate at least partially overlaps the orthographic projection of the second power lines on the substrate .
  • the orthographic projection of the initialization compensation pattern on the substrate partially overlaps the orthographic projection of the first pixel opening on the substrate, and the orthographic projection of the target data line on the substrate At least part of is located between the orthographic projection of the initialization compensation pattern on the substrate and the orthographic projection of the flattening compensation pattern on the substrate.
  • the orthographic projection of the second power line on the substrate partly overlaps the orthographic projection of the first pixel opening on the substrate.
  • the plurality of power lines includes a plurality of first power lines; the orthographic projection of the initialization compensation pattern on the substrate at least partially overlaps the orthographic projection of the first power line on the substrate .
  • the orthographic projection of the initialization compensation pattern on the base does not overlap with the orthographic projection of the first pixel opening on the base.
  • the plurality of pixel units are divided into multiple columns of pixel units, each column of pixel units includes a plurality of pixel units arranged along the first direction;
  • the display substrate further includes a plurality of first power lines, a plurality of second power lines and a plurality of third power lines; the first power lines are respectively coupled to the first sub-pixels in a corresponding row of pixel units;
  • the second power line is respectively coupled to each second sub-pixel in a corresponding column of pixel units
  • the third power line is respectively coupled to the third sub-pixels in a corresponding row of pixel units.
  • the first subpixel includes a blue subpixel
  • the second subpixel includes a red subpixel
  • the third subpixel includes a green subpixel
  • the third power supply line, the second power supply line wires and the first power wires are arranged in sequence along the second direction.
  • the data line, the flattening compensation pattern, the power supply compensation line and the initialization compensation pattern are arranged in the same layer and the same material, and the power supply line and the power supply compensation line are arranged in different layers.
  • the display substrate further includes a plurality of second initialization signal lines, the second initialization signal lines include at least a portion extending along the second direction; the first sub-pixel, the second sub-pixel and the third sub-pixel both include a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor, a first reset transistor, a second reset transistor and a light emitting element;
  • the first pole of the first reset transistor is coupled to the corresponding first initialization signal line, and the second pole of the first reset transistor is coupled to the gate of the driving transistor;
  • the first pole of the second reset transistor is coupled to the corresponding second initialization signal line, and the second pole of the second reset transistor is coupled to the light emitting element.
  • a second aspect of the present disclosure provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a circuit structural diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a driving timing diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic layout diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic layout diagram of the active layer in FIG. 3;
  • FIG. 5 is a schematic layout diagram of the first gate metal layer in FIG. 3;
  • FIG. 6 is a schematic layout diagram of a second gate metal layer in FIG. 3;
  • FIG. 7 is a schematic layout diagram of the first source-drain metal layer in FIG. 3;
  • FIG. 8 is a schematic layout diagram of a second source-drain metal layer in FIG. 3;
  • Fig. 9 is a schematic layout diagram of the anode layer in Fig. 3.
  • FIG. 10 is a schematic layout diagram of the active layer and the first gate metal layer in FIG. 3;
  • FIG. 11 is a schematic layout diagram of the active layer, the first gate metal layer and the second gate metal layer in FIG. 3;
  • FIG. 12 is a schematic layout diagram of the active layer to the first source-drain metal layer in FIG. 3;
  • FIG. 13 is a schematic layout diagram of the active layer to the second source-drain metal layer in FIG. 3;
  • FIG. 14 is a schematic layout diagram of a second source-drain metal layer and an anode layer in a pixel unit according to an embodiment of the present disclosure
  • FIG. 15 is a schematic layout diagram of a first source-drain metal layer and an anode layer in a pixel unit provided by an embodiment of the present disclosure
  • 16 is a schematic layout diagram of the first source-drain metal layer, the second source-drain metal layer and the anode layer in the pixel unit provided by an embodiment of the present disclosure
  • FIG. 17 is a partial cross-sectional schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • the flatness of the anode pattern under the pixel opening will affect the color shift parameters of the display, thereby affecting the display quality of the display.
  • an embodiment of the present disclosure provides a display substrate, including: a substrate, a plurality of data lines DA arranged on the substrate, and a set A plurality of first sub-pixels on the base; the first sub-pixels include:
  • a flattening compensation pattern 20, at least part of the flattening compensation pattern 20 extends along a first direction, the orthographic projection of the flattening compensation pattern 20 on the substrate, and the first pixel opening 11 on the substrate Orthographic projections on at least partially overlap, the flattening compensation pattern 20 and the target data line DA are arranged along a second direction, and the second direction intersects the first direction.
  • the target data line includes a data line DA coupled to adjacent sub-pixels of the first sub-pixel along the second direction.
  • At least part of the flattening compensation pattern 20 extending along the first direction means that at least part of the flattening compensation pattern 20 is a line, a line segment or a bar-shaped body, and the at least part of the flattening compensation pattern 20 extends along the first direction. , and the length of the at least part extending along the first direction is greater than the length extending of other parts along other directions.
  • the display substrate includes a plurality of data lines DA arranged along the second direction, and the data lines DA include at least a portion extending along the first direction.
  • the display substrate includes a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels
  • the first sub-pixels include a first sub-pixel driving circuit
  • the second sub-pixels Including a second sub-pixel driving circuit
  • the third sub-pixel includes a third sub-pixel driving circuit
  • the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit all include 7T1C circuit structure.
  • the plurality of first sub-pixels includes a plurality of first sub-pixel driving circuits, and the plurality of first sub-pixel driving circuits are divided into multiple columns of first sub-pixel driving circuits, and each column of first sub-pixel
  • the driving circuit column includes a plurality of first sub-pixel driving circuits arranged along the first direction.
  • the multiple second sub-pixels include multiple second sub-pixel drive circuits, the multiple second sub-pixel drive circuits are divided into multiple columns of second sub-pixel drive circuits, and each column of second sub-pixel drive circuits includes A plurality of second sub-pixel driving circuits arranged along the first direction.
  • the multiple third sub-pixels include multiple third sub-pixel drive circuits, the multiple third sub-pixel drive circuits are divided into multiple third sub-pixel drive circuit columns, and each third sub-pixel drive circuit column includes A plurality of third sub-pixel driving circuits arranged along the first direction.
  • the third sub-pixel driving circuit column, the second sub-pixel driving circuit column and the first sub-pixel driving circuit column are arranged circularly in sequence along the second direction.
  • the plurality of data lines DA and the plurality of columns of sub-pixel driving circuits in the display substrate (including the plurality of columns of first sub-pixel driving circuits, the plurality of columns of second sub-pixel driving circuits and the plurality of columns of third sub-pixels drive circuit columns) in one-to-one correspondence
  • the data lines DA correspond to each of the sub-pixel drive circuit columns (the first sub-pixel drive circuit column, the second sub-pixel drive circuit column or the third sub-pixel drive circuit column)
  • the sub-pixel driving circuits are respectively coupled.
  • the first sub-pixel further includes a first light-emitting element, the first light-emitting element includes a first anode pattern 51 and a first light-emitting functional layer, and the first anode pattern 51 and the first sub-pixel to which it belongs
  • the first sub-pixel driving circuit in is coupled to receive the driving signal provided by the first sub-pixel driving circuit.
  • the first sub-pixel further includes a first pixel opening 11 , and the pixel defining layer in the display substrate defines the first pixel opening 11 .
  • the orthographic projection of the first pixel opening 11 on the substrate is located inside the orthographic projection of the first anode pattern 51 in the first sub-pixel to which it belongs.
  • the orthographic projection of the first pixel opening 11 on the substrate refers to the orthographic projection of the figure enclosed by the boundary of the first pixel opening 11 on the substrate.
  • the orthographic projection of the first pixel opening 11 on the substrate is set to overlap with the orthographic projection of the target data line on the substrate, so that the portion overlapping the first pixel opening 11
  • the orthographic projection of part of the anode pattern on the substrate partially overlaps the orthographic projection of the target data line on the substrate.
  • the target data line includes a data line DA coupled to a second sub-pixel adjacent to the first sub-pixel along the second direction.
  • the orthographic projection of the flattening compensation pattern 20 on the substrate at least partially overlaps with the orthographic projection of the first pixel opening 11 on the substrate, so that it overlaps with the first pixel opening 11
  • the orthographic projection of the overlapped part of the anode pattern on the substrate partially overlaps the orthographic projection of the flattening compensation pattern 20 on the substrate.
  • the orthographic projection of the flattening compensation pattern 20 on the substrate and at least part of the orthographic projection of the target data line on the substrate are arranged along the second direction.
  • the first direction includes a vertical direction
  • the second direction includes a horizontal direction.
  • the orthographic projection of the left part of the first pixel opening 11 on the substrate overlaps with the orthographic projection of the target data line among the plurality of data lines DA on the substrate.
  • the orthographic projection of the right part of the first pixel opening 11 on the substrate overlaps with the orthographic projection of the flattening compensation pattern 20 on the substrate.
  • the left side portion and the right side portion are opposed along the second direction.
  • the display substrate provided by the embodiment of the present disclosure, by setting the orthographic projection of the first pixel opening 11 on the substrate, the target data line among the plurality of data lines DA
  • the orthographic projection on the base partially overlaps; and the orthographic projection of the first pixel opening 11 on the base is set to overlap with the orthographic projection of the flattening compensation pattern 20 on the base;
  • the orthographic projection of the portion of the first anode pattern 51 overlapping the first pixel opening 11 on the substrate is the same as the orthographic projection of the target data line among the plurality of data lines DA on the substrate.
  • the flattening compensation pattern 20 compensates the level difference generated by the target data line under the first anode pattern 51, so that the structure under the first anode pattern 51 can be evenly and symmetrically distributed, and the first anode pattern 51 is improved.
  • the flatness of the anode pattern 51 effectively improves the color shift parameter of the display substrate and ensures the display quality of the display substrate.
  • the first sub-pixel further includes a first sub-pixel driving circuit and a first anode pattern 51; the flattening compensation pattern 20 is respectively connected with the The first sub-pixel driving circuit is coupled to the first anode pattern 51 .
  • the first anode pattern 51 is located on the side of the first sub-pixel driving circuit facing away from the substrate, and the flattening compensation pattern 20 is located between the first sub-pixel driving circuit and the first Between the anode patterns 51.
  • first anode pattern 51 is far away from the first sub-pixel driving circuit, switching between the flattening compensation pattern 20 can better ensure that the first anode pattern 51 and the first sub-pixel driving circuit The connection stability and reliability between the above-mentioned first sub-pixel driving circuits.
  • planarization compensation pattern 20 has both a planarization compensation function and a transfer function, which effectively reduces the layout difficulty of the display substrate.
  • the flattening compensation pattern 20 is set to include a first compensation part 201 and a second compensation part 202;
  • the first compensation part 201 is a strip structure extending along the first direction, and the orthographic projection of the first compensation part 201 on the substrate is the same as that of the first pixel opening 11 on the substrate.
  • the orthographic projections partially overlap;
  • the orthographic projection of the second compensation portion 202 on the substrate does not overlap with the orthographic projection of the first pixel opening 11 on the substrate.
  • the second compensation part 202 is coupled to the first sub-pixel driving circuit and the first anode pattern 51 respectively.
  • the orthographic projection of the first compensation part 201 on the substrate is set inside the orthographic projection of the first anode pattern 51 on the substrate.
  • the orthographic projection of the second compensation portion 202 on the substrate overlaps with the orthographic projection of the first anode pattern 51 on the substrate.
  • the above setting method not only ensures the stability and reliability of the connection between the first anode pattern 51 and the first sub-pixel driving circuit, but also ensures the flatness of the first anode pattern 51, effectively reducing the Displays the layout difficulty of the substrate.
  • the display substrate is set to further include a plurality of second sub-pixels, and the second sub-pixels include second pixel openings 12; at least part of the first sub-pixels
  • the orthographic projections of the two pixel openings 12 on the substrate are located between the orthographic projections of adjacent data lines DA on the substrate.
  • the orthographic projection of the second pixel opening 12 on the substrate does not overlap with the orthographic projection of the data line DA on the substrate.
  • the second subpixel includes a second subpixel driving circuit and a second anode pattern 52, and the second anode pattern 52 is coupled to the second subpixel driving circuit and receives the second subpixel The driving signal provided by the driving circuit.
  • the orthographic projection of the second pixel opening 12 on the substrate is located inside the orthographic projection of the second anode pattern 52 on the substrate.
  • the orthographic projection of the portion of the second anode pattern 52 overlapping the second pixel opening 12 on the substrate does not overlap the orthographic projection of the data line DA on the substrate.
  • the above arrangement makes the flatness of the overlapping portion of the second anode pattern 52 and the second pixel opening 12 not affected by the data line DA, which further ensures the color shift parameters of the display substrate.
  • the display substrate further includes a plurality of third sub-pixels; the third sub-pixels include third pixel openings 13, and the third pixel openings 13
  • the orthographic projection on the substrate is located between the orthographic projections of adjacent data lines DA on the substrate;
  • the plurality of first sub-pixels, the plurality of second sub-pixels and the plurality of third sub-pixels are divided into a plurality of pixel units, each pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel; in a pixel unit, the second pixel opening 12 and the third pixel opening 13 are located in the same column along the first direction, and the first pixel opening 11 is located in another column.
  • the orthographic projection of the third pixel opening 13 on the substrate does not overlap with the orthographic projection of the data line DA on the substrate.
  • the third subpixel includes a third subpixel driving circuit and a third anode pattern 53, and the third anode pattern 53 is coupled to the third subpixel driving circuit and receives the third subpixel The driving signal provided by the driving circuit.
  • the orthographic projection of the third pixel opening 13 on the substrate is located inside the orthographic projection of the third anode pattern 53 on the substrate.
  • the orthographic projection of the portion of the third anode pattern 53 overlapping the third pixel opening 13 on the substrate does not overlap the orthographic projection of the data line DA on the substrate.
  • the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit are arranged in sequence along the first direction.
  • the display substrate includes a plurality of pixel units, and the plurality of pixel units are divided into multiple columns of pixel units, and in each column of pixel units: the second pixel opening 12 and the third pixel opening 13 along the The first direction is located in the same column, and the second pixel openings 12 and the third pixel openings 13 are arranged alternately; the first pixel openings 11 are located in another column.
  • the display substrate adopts a real RGB pixel arrangement.
  • the above arrangement makes the flatness of the overlapping portion of the third anode pattern 53 and the third pixel opening 13 not affected by the data line DA, which further ensures the color shift parameters of the display substrate.
  • the second subpixel includes a second connection part 30, a second subpixel driving circuit and a second anode pattern 52, and the second connection part 30 are respectively coupled to the second sub-pixel driving circuit and the second anode pattern 52;
  • the second connection portion 30 is provided on the same layer and the same material as the data line DA, and the orthographic projection of the second connection portion 30 on the substrate is located at the orthographic projection of the second pixel opening 12 on the substrate. between the projection and the orthographic projection of the third pixel opening 13 on the substrate; the second pixel opening 12 and the third pixel opening 13 are located in the same column along the first direction.
  • the second connecting portion 30 is made of a second source-drain metal layer.
  • both the second pixel opening 12 and the third pixel opening 13 can avoid the second source-drain metal layer, and the structure formed with the second source-drain metal layer will not be vertical to the substrate. directions overlap.
  • At least part of the second connecting portion 30 is located between the second sub-pixel driving circuit and the second anode pattern 52 .
  • the orthographic projection of the second connecting portion 30 on the substrate does not overlap with the orthographic projection of the second pixel opening 12 on the substrate.
  • the orthographic projection of the second connecting portion 30 on the base does not overlap with the orthographic projection of the third pixel opening 13 on the base.
  • the orthographic projection of the second connecting portion 30 on the substrate partly overlaps the orthographic projection of the second anode pattern 52 on the substrate.
  • the orthographic projection of the second connecting portion 30 on the substrate partly overlaps the orthographic projection of the third anode pattern 53 on the substrate.
  • the orthographic projection of the second connecting portion 30 on the substrate, the orthographic projection of the second pixel opening 12 on the substrate and the orthographic projection of the third pixel opening 13 on the substrate are set above. Between, the flatness of the overlapping portion of the second anode pattern 52 and the second pixel opening 12 and the flatness of the overlapping portion of the third anode pattern 53 and the third pixel opening 13 are avoided. performance, which is affected by the second connecting portion 30, thereby well ensuring the color shift parameters of the display substrate.
  • the display substrate further includes:
  • a plurality of power supply compensation lines VDD-B, the plurality of power supply compensation lines VDD-B are in one-to-one correspondence with at least some of the power supply lines VDD, and the orthographic projection of the power supply compensation lines VDD-B on the substrate corresponds to the corresponding Orthographic projections of the power supply line VDD on the substrate at least partially overlap, and the power supply compensation line VDD-B is coupled to the corresponding power supply line VDD.
  • the multiple power lines VDD are loaded with the same power signal.
  • the plurality of power supply lines VDD are arranged along the second direction.
  • the power line VDD is made of the first source-drain metal layer.
  • the minimum line width of the power line VDD is less than or equal to 3 microns.
  • the power compensation line VDD-B is located on a side of the power line VDD facing away from the substrate.
  • the power compensation line VDD-B is coupled to the corresponding power line VDD through a via hole.
  • the power supply compensation line VDD-B includes at least a portion extending along the first direction.
  • the display substrate includes a plurality of pixel units, and the plurality of pixel units are divided into columns of pixel units.
  • the multiple columns of pixel units correspond to the multiple power supply compensation lines VDD-B one to one. At least part of the power supply compensation line VDD-B is located in the layout area of a corresponding row of pixel units.
  • the extension length of the power supply compensation line VDD-B is approximately the same as the extension length of the power supply line VDD; or, the extension length of the power supply compensation line VDD-B is shorter than the extension length of the power supply line VDD.
  • the display substrate set above also includes the power supply compensation line VDD-B, so that the power supply line VDD and the power supply compensation line VDD-B implement a double-layer design, which reduces the resistance of the power supply line VDD, and can In the case of narrowing the line width of the power supply line VDD, the display uniformity of the display substrate can be well guaranteed.
  • the multiple power supply lines VDD include multiple first power supply lines VDD1
  • the multiple power supply compensation lines VDD-B include multiple a first power supply compensation line
  • the orthographic projection of the first power supply compensation line on the substrate at least partially overlaps the orthographic projection of the corresponding first power supply line VDD1 on the substrate, and the first power supply compensation line The line is coupled to the corresponding first power line VDD1;
  • the orthographic projection of the first power supply line VDD1 on the substrate does not overlap with the orthographic projection of the first pixel opening 11 on the substrate, and the orthographic projection of the first power supply compensation line on the substrate The projection does not overlap with the orthographic projection of the first pixel opening 11 on the substrate.
  • the multiple power lines include multiple first power lines VDD1, multiple second power lines VDD2 and multiple third power lines VDD3.
  • the first power line VDD1, the second power line VDD2 and the third power line VDD3 are electrically connected.
  • the second plates Cst2 of the storage capacitors Cst included in the sub-pixel driving circuits located in the same row along the second direction are sequentially coupled, and the second plates Cst2 in each sub-pixel driving circuit are Coupling with corresponding power lines.
  • the power line in the display substrate, the power supply compensation line VDD-B, and the second plate Cst2 together form a grid structure.
  • the multiple first power supply lines VDD1 correspond to the multiple columns of first sub-pixel driving circuit columns one by one, and the first power supply line VDD1 corresponds to each first sub-pixel in a corresponding column of first sub-pixel driving circuit columns.
  • the driving circuits are respectively coupled.
  • the multiple second power supply lines VDD2 correspond to the multiple columns of second sub-pixel driving circuit columns one by one, and the second power supply line VDD2 corresponds to each second sub-pixel in a corresponding column of second sub-pixel driving circuit columns.
  • the driving circuits are respectively coupled.
  • the plurality of third power supply lines VDD3 correspond to the plurality of columns of third sub-pixel driving circuit columns one by one, and the third power supply line VDD3 corresponds to each third sub-pixel in a corresponding column of third sub-pixel driving circuit columns.
  • the driving circuits are respectively coupled.
  • the plurality of first power supply compensation lines correspond to the plurality of first power supply lines VDD1 one by one
  • the orthographic projection of the first power supply compensation lines on the substrate corresponds to the corresponding first power supply line
  • the orthographic projection of VDD1 on the substrate has an overlapping area
  • the first power compensation line is coupled to the corresponding first power line VDD1 through a via hole in the overlapping area.
  • the above arrangement of the display substrate including the first power supply line VDD1 and the first power supply compensation line effectively reduces the overall resistance of the display substrate power supply line and improves the display uniformity of the display substrate.
  • the orthographic projection of the first power supply line VDD1 on the substrate does not overlap with the orthographic projection of the first pixel opening 11 on the substrate, and the first power supply compensation line is on the substrate
  • the orthographic projection of the first pixel opening 11 does not overlap with the orthographic projection of the first pixel opening 11 on the substrate, avoiding the interference of the first power supply line VDD1 and the first power supply compensation line to the first anode pattern 51 Flatness has an effect.
  • the plurality of power supply lines include a plurality of second power supply lines VDD2
  • the plurality of power supply compensation lines include a plurality of second power supply compensation lines
  • the orthographic projection of the second power supply compensation line on the substrate at least partially overlaps the orthographic projection of the corresponding second power supply line VDD2 on the substrate, and the second power supply compensation line and the corresponding second power supply Line VDD2 coupling;
  • the orthographic projection of the second power supply line VDD2 on the substrate overlaps with the orthographic projection of the first pixel opening 11 on the substrate, and the orthographic projection of the second power supply compensation line on the substrate The projection does not overlap with the orthographic projection of the first pixel opening 11 on the substrate.
  • the plurality of second power supply compensation lines correspond to the plurality of second power supply lines VDD2 one by one
  • the orthographic projection of the second power supply compensation lines on the substrate corresponds to the corresponding second power supply lines
  • the orthographic projection of VDD2 on the substrate has an overlapping area
  • the second power compensation line is coupled to the corresponding second power line VDD2 through a via hole in the overlapping area.
  • the above arrangement of the display substrate including the second power supply line VDD2 and the second power supply compensation line effectively reduces the overall resistance of the display substrate power supply line and improves the display uniformity of the display substrate.
  • the above setting of the orthographic projection of the second power supply compensation line on the substrate does not overlap with the orthographic projection of the first pixel opening 11 on the substrate, avoiding the impact of the second power supply compensation line on the
  • the flatness of the first anode pattern 51 has an influence.
  • the plurality of power supply lines include a plurality of second power supply lines VDD2
  • the plurality of power supply compensation lines include a plurality of second power supply compensation lines
  • the orthographic projection of the second power supply compensation line on the substrate at least partially overlaps the orthographic projection of the corresponding second power supply line VDD2 on the substrate, and the second power supply compensation line and the corresponding second power supply Line VDD2 coupling;
  • the orthographic projection of the second power supply line VDD2 on the substrate overlaps with the orthographic projection of the first pixel opening 11 on the substrate, and the orthographic projection of the second power supply compensation line on the substrate a projection that partially overlaps the orthographic projection of the first pixel opening 11 on the substrate;
  • At least part of the orthographic projection of the target data line DA on the substrate is located in the orthographic projection of the second power supply compensation line on the substrate and the orthographic projection of the flattening compensation pattern 20 on the substrate between.
  • the plurality of second power supply compensation lines correspond to the plurality of second power supply lines VDD2 one-to-one
  • the orthographic projection of the second power supply compensation lines on the substrate corresponds to the corresponding
  • the orthographic projection of the second power line VDD2 on the substrate has an overlapping area, and the second power compensation line is coupled to the corresponding second power line VDD2 through a via hole in the overlapping area.
  • the above arrangement of the display substrate including the second power supply line VDD2 and the second power supply compensation line effectively reduces the overall resistance of the display substrate power supply line and improves the display uniformity of the display substrate.
  • the above-mentioned orthographic projection of the second power compensation line on the substrate overlaps with the orthographic projection of the first pixel opening 11 on the substrate; the orthographic projection of the target data line on the substrate At least part of the projection is located between the orthographic projection of the second power supply compensation line on the substrate and the orthographic projection of the flattening compensation pattern 20 on the substrate; effectively improving the first anode pattern 51 flatness.
  • the plurality of power supply lines include a plurality of third power supply lines VDD3, and the orthographic projection of the third power supply line VDD3 on the substrate, at least partially overlap with the orthographic projection of the second pixel opening 12 on the substrate; the orthographic projection of the third power supply line VDD3 on the substrate overlaps with the orthographic projection of the third pixel opening 13 on the substrate
  • the orthographic projections of are at least partially overlapping.
  • the first power line VDD1, the second power line VDD2 and the third power line VDD3 are all made of a first source-drain metal layer, and the gap between the first source-drain metal layer and the anode pattern The distance is far, and there are two flat layers between the first source-drain metal layer and the anode pattern, therefore, the first power line VDD1, the second power line VDD2 and the third power line VDD3 are The flatness of the anode pattern has little effect.
  • the display substrate further includes:
  • a plurality of initialization compensation patterns Vinit-B, at least part of the initialization compensation pattern Vinit-B extends along the first direction; between adjacent first initialization signal lines Vinit1, at least one initialization compensation pattern Vinit- B is coupled.
  • the first initialization signal line Vinit1 is made of the second gate metal layer.
  • the initialization compensation pattern Vinit-B is made by using the second source-drain metal layer.
  • the first initialization signal line Vinit1 is used to transmit a first initialization signal.
  • connection between the one initialization signal line and the initialization compensation pattern Vinit-B can be realized through a transfer pattern and a via hole.
  • the transfer pattern is made using the first source-drain metal layer.
  • adjacent first initialization signal lines Vinit1 are coupled through a plurality of initialization compensation patterns Vinit-B.
  • the plurality of pixel units located in the same row along the second direction correspond to the plurality of initialization compensation patterns Vinit-B one by one. At least part of the initialization compensation pattern Vinit-B is located in the layout area of the corresponding pixel unit.
  • the initialization compensation patterns Vinit-B located in the same column along the first direction are sequentially coupled to form an integrated structure.
  • the display substrate is set above to include the first initialization signal line Vinit1 and the initialization compensation pattern Vinit-B, so that the first initialization signal line Vinit1 and the initialization compensation pattern Vinit-B together form a grid structure, thereby improving The resistance of the first initialization signal line Vinit1 is increased, and the display uniformity of the display substrate under high gray scale is improved.
  • the plurality of power lines include a plurality of second power lines VDD2; the orthographic projection of the initialization compensation pattern Vinit-B on the substrate is consistent with the The orthographic projections of VDD2 on the substrate at least partially overlap.
  • the line width of the initialization compensation pattern Vinit-B in a direction perpendicular to its own extension is smaller than the line width of the second power line VDD2 in a direction perpendicular to its own extension.
  • the orthographic projection of the initialization compensation pattern Vinit-B on the substrate and the orthographic projection of the second power line VDD2 on the substrate at least partially overlap, and the second power line VDD2 can be used to
  • the signal shielding of the initialization compensation pattern Vinit-B effectively avoids the formation of additional parasitic capacitance between the initialization compensation pattern Vinit-B and other structures in the display substrate.
  • the orthographic projection of the initialization compensation pattern Vinit-B on the substrate is set to overlap with the orthographic projection of the first pixel opening 11 on the substrate, and the target data line DA At least part of the orthographic projection on the substrate is located between the orthographic projection of the initialization compensation pattern Vinit-B on the substrate and the orthographic projection of the flattening compensation pattern 20 on the substrate.
  • the arrangement above further improves the flatness of the part of the first anode pattern 51 located below the first pixel opening 11 .
  • the orthographic projection of the second power line VDD2 on the substrate partly overlaps the orthographic projection of the first pixel opening 11 on the substrate.
  • the plurality of power lines include a plurality of first power lines VDD1; the orthographic projection of the initialization compensation pattern Vinit-B on the substrate is the same as that of the first power line VDD1 on the substrate
  • the orthographic projections of are at least partially overlapping.
  • the line width of the initialization compensation pattern Vinit-B in a direction perpendicular to its own extension is smaller than the line width of the first power line VDD1 in a direction perpendicular to its own extension.
  • the initialization compensation pattern Vinit-B and the power compensation line VDD-B overlap with different power lines.
  • the orthographic projection of the initialization compensation pattern Vinit-B on the substrate at least partially overlaps with the orthographic projection of the first power line VDD1 on the substrate, and the first power line VDD1 can
  • the signal shielding of the initialization compensation pattern Vinit-B effectively avoids the formation of additional parasitic capacitance between the initialization compensation pattern Vinit-B and other structures in the display substrate.
  • the orthographic projection of the initialization compensation pattern Vinit-B on the substrate is set not to overlap the orthographic projection of the first pixel opening 11 on the substrate.
  • the above arrangement makes the flatness of the part of the first anode pattern 51 below the first pixel opening 11 not affected by the initialization compensation pattern Vinit-B.
  • the plurality of pixel units are divided into multiple columns of pixel units, and each column of pixel units includes a plurality of pixel units arranged along the first direction;
  • the display substrate further includes a plurality of first power lines VDD1, a plurality of second power lines VDD2 and a plurality of third power lines VDD3;
  • the first power supply line VDD1 is respectively coupled to each first sub-pixel in a corresponding row of pixel units;
  • the second power supply line VDD2 is respectively coupled to the second sub-pixels in a corresponding row of pixel units;
  • the third power line VDD3 is respectively coupled to the third sub-pixels in a corresponding row of pixel units.
  • the plurality of first power supply lines VDD1 correspond to the plurality of columns of pixel units one-to-one
  • the plurality of second power supply lines VDD2 correspond to the plurality of columns of pixel units one-to-one
  • the plurality of third power supply lines VDD2 correspond to the plurality of columns of pixel units.
  • the power supply line VDD3 is in one-to-one correspondence with the multi-column pixel units; the first power supply line VDD1, the second power supply line VDD2 and the third power supply line VDD3 are loaded with the same power supply signal;
  • the first power line VDD1 , the second power line VDD2 and the third power line VDD3 are loaded with the same power signal.
  • the display substrate further includes a power bus in the non-display area, and the first power line VDD1 , the second power line VDD2 and the third power line VDD3 are all coupled to the power bus.
  • the first sub-pixel includes a blue sub-pixel
  • the second sub-pixel includes a red sub-pixel
  • the third sub-pixel includes a green sub-pixel
  • the power line VDD3, the second power line VDD2 and the first power line VDD1 are arranged in sequence along the second direction.
  • the data line DA, the flattening compensation pattern 20, the power supply compensation line VDD-B and the initialization compensation pattern Vinit-B are set in the same layer and the same material , the power line and the power compensation line VDD-B are arranged in different layers.
  • the data line DA, the flattening compensation pattern 20 , the power supply compensation line VDD-B and the initialization compensation pattern Vinit-B are all made of the second source-drain metal layer.
  • the power line is made of the first source-drain metal layer.
  • the display substrate further includes a plurality of second initialization signal lines Vinit2, and the second initialization signal lines Vinit2 include At least partially;
  • the first sub-pixel, the second sub-pixel and the third sub-pixel all include a sub-pixel driving circuit;
  • the sub-pixel driving circuit includes a driving transistor, a first reset transistor, a second reset transistor and light emitting element;
  • the first pole of the first reset transistor is coupled to the corresponding first initialization signal line Vinit1, and the second pole of the first reset transistor is coupled to the gate of the drive transistor;
  • a first pole of the second reset transistor is coupled to the corresponding second initialization signal line Vinit2, and a second pole of the second reset transistor is coupled to the light emitting element.
  • the second initialization signal line Vinit2 is made of a second gate metal layer.
  • the display substrate includes a plurality of gate lines GA, a plurality of reset lines Rst and a plurality of emission control lines EM; at least part of the gate line GA, at least part of the reset line Rst and the emission control lines At least part of the line EM each extends along said second direction.
  • the sub-pixel driving circuit includes a first transistor T1 to a seventh transistor T7.
  • the gate of the first transistor T1 is coupled to the corresponding gate line GA, the first pole of the first transistor T1 is coupled to the second pole of the third transistor T3 (ie, the driving transistor), and the first The second pole of the transistor T1 is coupled to the gate of the third transistor T3.
  • the gate of the second transistor T2 (that is, the first reset transistor) is coupled to the corresponding reset line Rst, and the first pole of the second transistor T2 is coupled to the corresponding first initialization signal line Vinit1, so The second pole of the second transistor T2 is coupled to the gate of the third transistor T3.
  • the gate of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power line.
  • the gate of the fourth transistor T4 is coupled to the corresponding gate line GA, the first pole of the fourth transistor T4 is coupled to the corresponding data line DA, the second pole of the fourth transistor T4 is coupled to the third The first pole of the transistor T3 is coupled.
  • the gate of the fifth transistor T5 is coupled to the corresponding light emission control line EM, the first pole of the fifth transistor T5 is coupled to the power line, the second pole of the fifth transistor T5 is coupled to the third transistor T3 first pole coupling.
  • the gate of the sixth transistor T6 is coupled to the corresponding light emission control line EM, the first pole of the sixth transistor T6 is coupled to the second pole of the third transistor T3, and the second pole of the sixth transistor T6 The pole is coupled to the anode of the light emitting element EL.
  • a seventh transistor T7 (that is, a second reset transistor), the gate of the seventh transistor T7 is coupled to the reset line Rst coupled to the adjacent sub-pixels along the first direction, and the second reset transistor of the seventh transistor T7 One pole is coupled to the second initialization signal line Vinit2, the second pole of the seventh transistor T7 is coupled to the anode of the light emitting element EL, and the cathode of the light emitting element EL receives the negative power supply signal VSS.
  • the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, and a second gate insulating layer that are sequentially stacked along a direction away from the substrate 60 , the second gate metal layer Gate2, the interlayer insulating layer ILD, the first source-drain metal layer SD1, the first flat layer PLN1, the second source-drain metal layer SD2, the second flat layer PLN2, the anode layer 50, and the pixel definition layer PDL , light-emitting functional layer, cathode layer and encapsulation layer.
  • the active layer is used to form the first active layer 41 included in the first transistor T1, the second active layer 42 included in the second transistor T2, and the
  • the third transistor T3 includes a third active layer 43
  • the fourth transistor T4 includes a fourth active layer 44
  • the fifth transistor T5 includes a fifth active layer 45
  • the sixth transistor T6 includes The sixth active layer 46 and the seventh transistor T7 include a seventh active layer 47.
  • the first gate metal layer is used to form the reset line Rst, the gate line GA, the light emission control line EM, and the gates of each transistor.
  • the second gate metal layer Gate2 is used to form the first initialization signal line Vinit1 , the second initialization signal line Vinit2 and the second plate Cst2 of the storage capacitor Cst.
  • the first source-drain metal layer SD1 is used to form the power line VDD and some conductive patterns.
  • the second source-drain metal layer is used to form the data line DA and some conductive patterns.
  • the anode layer 50 is used to form an anode pattern included in each light emitting element EL.
  • the base of the display substrate includes an organic PI base.
  • the manufacturing process of the display substrate includes:
  • An active material layer is deposited on the substrate, and the active material layer is patterned to form the active layer. It should be noted that the patterning process includes: forming a photoresist on the side of the active material layer facing away from the substrate, exposing and developing the photoresist, and then etching the remaining photoresist as a mask The active material layer forms the active layer.
  • the interlayer insulating layer ILD is deposited on the side of the second gate metal layer Gate2 facing away from the substrate.
  • a patterning process is performed to form a plurality of via holes.
  • the first part of the plurality of via holes only penetrates the interlayer insulating layer ILD, the first part of the via holes can expose the second gate metal layer Gate2, and the first source-drain metal layer SD1 can pass through the first part
  • the via hole is coupled to the second gate metal layer Gate2.
  • a second part of the plurality of via holes can penetrate through the interlayer insulating layer ILD, the second gate insulating layer and the first gate insulating layer, and the second part of the via holes can expose In the active layer, the first source-drain metal layer SD1 can be coupled to the active layer through a second partial via hole.
  • the plurality of via holes may further include a third part of via holes, the third part of via holes can penetrate through the interlayer insulating layer ILD and the second gate insulating layer, and the third part of via holes can expose The first gate metal layer, the first source-drain metal layer SD1 can be coupled to the first gate metal layer through a third partial via hole.
  • a metal material layer is deposited on the side of the interlayer insulating layer ILD facing away from the substrate, and the metal material layer is patterned to form the first source-drain metal layer SD1.
  • a first flat layer PLN1 is deposited on the side of the first source-drain metal layer SD1 facing away from the substrate.
  • a metal material layer is deposited on the side of the first flat layer PLN1 facing away from the substrate, and the metal material layer is patterned to form the second source-drain metal layer SD2.
  • a second planar layer PLN2 is deposited on the side of the second source-drain metal layer SD2 facing away from the substrate.
  • An anode material layer is deposited on the side of the second flat layer PLN2 facing away from the substrate, and the anode material layer is patterned to form the anode layer 50 .
  • a pixel defining layer is formed on a side of the anode layer 50 facing away from the substrate, and the pixel defining layer includes a plurality of pixel openings.
  • each working cycle includes a first reset period P1 , a writing compensation period P2 , a second reset period P3 and a light emitting period P4 .
  • the reset signal input by the reset line Rst is at an active level
  • the second transistor T2 is turned on
  • the first initialization signal transmitted by the first initialization signal line Vinit1 is input to the gate of the third transistor T3 T3-g, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared to reset the gate T3-g of the third transistor T3.
  • the reset signal is at an inactive level
  • the second transistor T2 is turned off
  • the gate scanning signal input from the gate line GA is at an active level
  • the first transistor T1 and the fourth transistor T4 are controlled to be turned on
  • the data signal is written into the data line DA, and transmitted to the first electrode of the third transistor T3 through the fourth transistor T4, and at the same time, the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure , so through the cooperation of the first transistor T1, the third transistor T3 and the fourth transistor T4, the threshold voltage compensation for the third transistor T3 is realized.
  • the gate T3- The g potential finally reaches Vdata+Vth, wherein Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the gate scanning signal is at an inactive level
  • the first transistor T1 and the fourth transistor T4 are both turned off
  • the reset signal input from the reset line Rst' coupled to the sub-pixels in the next row is at Active level, to control the seventh transistor T7 to turn on, input the initialization signal input by the second initialization signal line Vinit2 to the anode of the light emitting element EL, and control the light emitting element EL not to emit light.
  • the light-emitting control signal written in the light-emitting control line EM is at an active level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power line VDD is input to the third transistor T3.
  • the third transistor T3 since the gate T3-g of the third transistor T3 is kept at Vdata+Vth, the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is the power signal For the corresponding voltage value, the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.
  • Embodiments of the present disclosure also provide a display device, including the display substrate provided in the above embodiments.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a back panel. board etc.
  • the display substrate provided by the above embodiment, by setting the orthographic projection of the first pixel opening 11 on the substrate to intersect with the orthographic projection part of the target data line among the plurality of data lines DA on the substrate and set the orthographic projection of the first pixel opening 11 on the substrate to partially overlap the orthographic projection of the flattening compensation pattern 20 on the substrate; so that the first anode pattern 51 and the first anode pattern 51 The orthographic projection of the overlapping portion of the first pixel opening 11 on the substrate overlaps with the orthographic projection of the target data line in the plurality of data lines DA on the substrate; and the first anode The orthographic projection of the portion of the pattern 51 overlapping the first pixel opening 11 on the substrate overlaps with the orthographic projection of the flattening compensation pattern 20 on the substrate.
  • the flattening compensation pattern 20 compensates the level difference generated by the target data line under the first anode pattern 51, so that the structure under the first anode pattern 51 can be evenly and symmetrically distributed, and the first anode pattern 51 is improved.
  • the flatness of the anode pattern 51 effectively improves the color shift parameter of the display substrate and ensures the display quality of the display substrate.
  • the display device provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous.
  • These specific graphics may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

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Abstract

一种显示基板和显示装置。显示基板包括：基底，设置于基底上的多条数据线（DA），以及设置于基底上的多个第一子像素；第一子像素包括：第一像素开口（11）和平坦化补偿图形（20）；第一像素开口（11）在基底上的正投影，与多条数据线（DA）中的目标数据线（DA）在基底上的正投影部分交叠；平坦化补偿图形（20）的至少部分沿第一方向延伸，平坦化补偿图形（20）在基底上的正投影，与第一像素开口（11）在基底上的正投影至少部分交叠，平坦化补偿图形（20）与目标数据线（DA）沿第二方向排列，第二方向与第一方向相交。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示器以其轻薄、亮度高、功耗低、响应快、清晰度高、柔性好、发光效率高等优点，被广泛的应用于各个领域。而随着消费者对于显示画质要求的不断提升，显示器逐渐向着高像素密度的方向发展。
发明内容
本公开的目的在于提供一种显示基板和显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：基底，设置于所述基底上的多条数据线，以及设置于所述基底上的多个第一子像素；所述第一子像素包括：
第一像素开口，所述第一像素开口在所述基底上的正投影，与所述多条数据线中的目标数据线在所述基底上的正投影部分交叠；
平坦化补偿图形，所述平坦化补偿图形的至少部分沿第一方向延伸，所述平坦化补偿图形在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影至少部分交叠，所述平坦化补偿图形与所述目标数据线沿第二方向排列，所述第二方向与所述第一方向相交。
可选的，所述第一子像素还包括第一子像素驱动电路和第一阳极图形；所述平坦化补偿图形分别与所述第一子像素驱动电路和所述第一阳极图形耦接。
可选的，所述平坦化补偿图形包括第一补偿部分和第二补偿部分；
所述第一补偿部分为沿所述第一方向延伸的条形结构，所述第一补偿部分在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分 交叠；
所述第二补偿部分在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠。
可选的，所述第一补偿部分在所述基底上的正投影，位于所述第一阳极图形在所述基底上的正投影的内部；
所述第二补偿部分在所述基底上的正投影，与所述第一阳极图形在所述基底上的正投影部分交叠。
可选的，所述显示基板还包括多个第二子像素，所述第二子像素包括第二像素开口；
至少部分所述第二像素开口在所述基底上的正投影，位于相邻的数据线在所述基底上的正投影之间。
可选的，所述显示基板还包括多个第三子像素；所述第三子像素包括第三像素开口，所述第三像素开口在所述基底上的正投影位于相邻的数据线在所述基底上的正投影之间；
所述多个第一子像素，所述多个第二子像素和所述多个第三子像素划分为多个像素单元，每个像素单元均包括一个第一子像素，一个第二子像素和一个第三子像素；在一个像素单元中，所述第二像素开口和所述第三像素开口沿所述第一方向位于同一列，所述第一像素开口位于另一列。
可选的，所述第二子像素包括第二连接部，第二子像素驱动电路和第二阳极图形，所述第二连接部分别与所述第二子像素驱动电路和所述第二阳极图形耦接；
所述第二连接部与所述数据线同层同材料设置，所述第二连接部在所述基底上的正投影，位于所述第二像素开口在所述基底上的正投影和所述第三像素开口在所述基底上的正投影之间；该第二像素开口和该第三像素开口沿所述第一方向位于同一列。
可选的，所述显示基板还包括：
多条电源线，所述电源线的至少部分沿所述第一方向延伸；
多条电源补偿线，所述多条电源补偿线与至少部分所述电源线一一对应，所述电源补偿线在所述基底上的正投影，与对应的电源线在所述基底上的正 投影至少部分交叠，所述电源补偿线与对应的电源线耦接。
可选的，所述多条电源线包括多条第一电源线，所述多条电源补偿线包括多条第一电源补偿线，所述第一电源补偿线在所述基底上的正投影，与对应的第一电源线在所述基底上的正投影至少部分交叠，所述第一电源补偿线与对应的第一电源线耦接；
所述第一电源线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠，所述第一电源补偿线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠。
可选的，所述多条电源线包括多条第二电源线，所述多条电源补偿线包括多条第二电源补偿线，所述第二电源补偿线在所述基底上的正投影，与对应的第二电源线在所述基底上的正投影至少部分交叠，所述第二电源补偿线与对应的第二电源线耦接；
所述第二电源线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠，所述第二电源补偿线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠。
可选的，所述多条电源线包括多条第二电源线，所述多条电源补偿线包括多条第二电源补偿线，所述第二电源补偿线在所述基底上的正投影，与对应的第二电源线在所述基底上的正投影至少部分交叠，所述第二电源补偿线与对应的第二电源线耦接；
所述第二电源线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠，所述第二电源补偿线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠；
所述目标数据线在所述基底上的正投影的至少部分，位于所述第二电源补偿线在所述基底上的正投影和所述平坦化补偿图形在所述基底上的正投影之间。
可选的，所述多条电源线包括多条第三电源线，所述第三电源线在所述基底上的正投影，与所述第二像素开口在所述基底上的正投影至少部分交叠；所述第三电源线在所述基底上的正投影，与所述第三像素开口在所述基底上的正投影至少部分交叠。
可选的，所述显示基板还包括：
多条第一初始化信号线，所述第一初始化信号线的至少部分沿所述第二方向延伸；
多个初始化补偿图形，所述初始化补偿图形的至少部分沿所述第一方向延伸；相邻的所述第一初始化信号线之间，通过至少一个初始化补偿图形耦接。
可选的，所述多条电源线包括多条第二电源线；所述初始化补偿图形在所述基底上的正投影与所述第二电源线在所述基底上的正投影至少部分交叠。
可选的，所述初始化补偿图形在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠，所述目标数据线在所述基底上的正投影的至少部分，位于所述初始化补偿图形在所述基底上的正投影和所述平坦化补偿图形在所述基底上的正投影之间。
可选的，所述第二电源线在所述基底上的正投影与所述第一像素开口在所述基底上的正投影部分交叠。
可选的，所述多条电源线包括多条第一电源线；所述初始化补偿图形在所述基底上的正投影与所述第一电源线在所述基底上的正投影至少部分交叠。
可选的，所述初始化补偿图形在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠。
可选的，所述多个像素单元划分为多列像素单元，每列像素单元均包括沿所述第一方向排列的多个像素单元；
所述显示基板还包括多条第一电源线，多条第二电源线和多条第三电源线；所述第一电源线与对应的一列像素单元中各第一子像素分别耦接；
所述第二电源线与对应的一列像素单元中各第二子像素分别耦接；
所述第三电源线与对应的一列像素单元中各第三子像素分别耦接。
可选的，所述第一子像素包括蓝色子像素，所述第二子像素包括红色子像素，所述第三子像素包括绿色子像素；所述第三电源线，所述第二电源线和所述第一电源线沿所述第二方向依次排列。
可选的，所述数据线，所述平坦化补偿图形，所述电源补偿线和所述初始化补偿图形同层同材料设置，所述电源线与所述电源补偿线异层设置。
可选的，所述显示基板还包括多条第二初始化信号线，所述第二初始化信号线包括沿所述第二方向延伸的至少部分；所述第一子像素，所述第二子像素和所述第三子像素均包括子像素驱动电路；所述子像素驱动电路包括驱动晶体管，第一复位晶体管，第二复位晶体管和发光元件；
所述第一复位晶体管的第一极与对应的所述第一初始化信号线耦接，所述第一复位晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第二复位晶体管的第一极与对应的所述第二初始化信号线耦接，所述第二复位晶体管的第二极与所述发光元件耦接。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的子像素驱动电路的电路结构图；
图2为本公开实施例提供的子像素驱动电路的驱动时序图；
图3为本公开实施例提供的子像素驱动电路的布局示意图；
图4为图3中有源层的布局示意图；
图5为图3中第一栅金属层的布局示意图；
图6为图3中第二栅金属层的布局示意图；
图7为图3中第一源漏金属层的布局示意图；
图8为图3中第二源漏金属层的布局示意图；
图9为图3中阳极层的布局示意图；
图10为图3中有源层和第一栅金属层的布局示意图；
图11为图3中有源层和第一栅金属层和第二栅金属层的布局示意图；
图12为图3中有源层至第一源漏金属层的布局示意图；
图13为图3中有源层至第二源漏金属层的布局示意图；
图14为本公开实施例提供的像素单元中第二源漏金属层和阳极层的布局示意图；
图15为本公开实施例提供的像素单元中第一源漏金属层和阳极层的布局示意图；
图16为本公开实施例提供的像素单元中第一源漏金属层和第二源漏金属层和阳极层的布局示意图；
图17为本公开实施例提供的显示基板的部分截面示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板和显示装置，下面结合说明书附图进行详细描述。
显示器的像素密度越大，每个子像素占用的布局空间越小，子像素的布局难度越大，子像素的像素开口下方的阳极图形的平坦性越难保证。而像素开口下方阳极图形的平坦性会影响显示器的色偏参数，进而影响了显示器的显示质量。
请参阅图3，图8，图9，图13，图14和图16，本公开实施例提供了一种显示基板，包括：基底，设置于所述基底上的多条数据线DA，以及设置于所述基底上的多个第一子像素；所述第一子像素包括：
第一像素开口11，所述第一像素开口11在所述基底上的正投影，与所述多条数据线DA中的目标数据线在所述基底上的正投影部分交叠；
平坦化补偿图形20，所述平坦化补偿图形20的至少部分沿第一方向延伸，所述平坦化补偿图形20在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影至少部分交叠，所述平坦化补偿图形20与所述目标数据线DA沿第二方向排列，所述第二方向与所述第一方向相交。
示例性的，所述目标数据线包括所述第一子像素沿第二方向相邻的子像素耦接的数据线DA。
需要说明，所述平坦化补偿图形20的至少部分沿第一方向延伸是指：所 述平坦化补偿图形20的至少部分是线、线段或条形状体，该至少部分沿所述第一方向延展，且该至少部分沿所述第一方向延展的长度大于其他部分沿其它方向伸展的长度。
示例性的，所述显示基板包括多条数据线DA，所述多条数据线DA沿所述第二方向排列，所述数据线DA包括沿所述第一方向延伸的至少部分。
示例性的，所述显示基板包括多个第一子像素，多个第二子像素和多个第三子像素，所述第一子像素包括第一子像素驱动电路，所述第二子像素包括第二子像素驱动电路，所述第三子像素包括第三子像素驱动电路，所述第一子像素驱动电路，所述第二子像素驱动电路和所述第三子像素驱动电路均包括7T1C电路结构。
示例性的，所述多个第一子像素包括多个第一子像素驱动电路，所述多个第一子像素驱动电路划分为多列第一子像素驱动电路列，每列第一子像素驱动电路列包括沿所述第一方向排列的多个第一子像素驱动电路。所述多个第二子像素包括多个第二子像素驱动电路，所述多个第二子像素驱动电路划分为多列第二子像素驱动电路列，每列第二子像素驱动电路列包括沿所述第一方向排列的多个第二子像素驱动电路。所述多个第三子像素包括多个第三子像素驱动电路，所述多个第三子像素驱动电路划分为多列第三子像素驱动电路列，每列第三子像素驱动电路列包括沿所述第一方向排列的多个第三子像素驱动电路。
所述第三子像素驱动电路列，所述第二子像素驱动电路列和所述第一子像素驱动电路列沿所述第二方向依次循环排列。
示例性的，所述多条数据线DA与显示基板中的多列子像素驱动电路列(包括多列第一子像素驱动电路列，多列第二子像素驱动电路列和多列第三子像素驱动电路列)一一对应，所述数据线DA与对应的一列子像素驱动电路列(第一子像素驱动电路列，第二子像素驱动电路列或者第三子像素驱动电路列)中的各子像素驱动电路分别耦接。
示例性的，所述第一子像素还包括第一发光元件，所述第一发光元件包括第一阳极图形51和第一发光功能层，所述第一阳极图形51与其所属的第一子像素中的第一子像素驱动电路耦接，接收该第一子像素驱动电路提供的 驱动信号。
示例性的，所述第一子像素还包括第一像素开口11，所述显示基板中的像素界定层限定出所述第一像素开口11。所述第一像素开口11在所述基底上的正投影，位于其所属第一子像素中的第一阳极图形51在所述基底上的正投影的内部。
需要说明，所述第一像素开口11在所述基底上的正投影指：所述第一像素开口11的边界围成的图形在所述基底上的正投影。
示例性的，设置所述第一像素开口11在所述基底上的正投影，与所述目标数据线在所述基底上的正投影部分交叠，使得与所述第一像素开口11重叠的部分阳极图形在所述基底上的正投影，与所述目标数据线在所述基底上的正投影部分交叠。示例性的，所述目标数据线包括所述第一子像素沿第二方向相邻的第二子像素耦接的数据线DA。
示例性的，所述平坦化补偿图形20在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影至少部分交叠，使得与所述第一像素开口11重叠的部分阳极图形在所述基底上的正投影，与所述平坦化补偿图形20在所述基底上的正投影部分交叠。
示例性的，所述平坦化补偿图形20在所述基底上的正投影，与所述目标数据线的至少部分在所述基底上的正投影沿第二方向排列。示例性的，所述第一方向包括竖直方向，所述第二方向包括水平方向。
示例性的，所述第一像素开口11的左侧部分在所述基底上的正投影，与所述多条数据线DA中的目标数据线在所述基底上的正投影部分交叠。所述第一像素开口11的右侧部分在所述基底上的正投影，与所述平坦化补偿图形20在所述基底上的正投影部分交叠。所述左侧部分和所述右侧部分沿所述第二方向相对。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，通过设置所述第一像素开口11在所述基底上的正投影，与所述多条数据线DA中的目标数据线在所述基底上的正投影部分交叠；以及设置所述第一像素开口11在所述基底上的正投影，与所述平坦化补偿图形20在所述基底上的正投影部分交叠；使得所述第一阳极图形51与所述第一像素开口11重叠的 部分在所述基底上的正投影，与所述多条数据线DA中的目标数据线在所述基底上的正投影部分交叠；并使得所述第一阳极图形51与所述第一像素开口11重叠的部分在所述基底上的正投影，与所述平坦化补偿图形20在所述基底上的正投影部分交叠。所述平坦化补偿图形20补偿了所述目标数据线在所述第一阳极图形51下方产生的段差，使得所述第一阳极图形51下方的结构能够均匀的对称分布，提升了所述第一阳极图形51的平坦性，从而有效改善了所述显示基板的色偏参数，保证了显示基板的显示质量。
如图3，图13至图16所示，在一些实施例中，所述第一子像素还包括第一子像素驱动电路和第一阳极图形51；所述平坦化补偿图形20分别与所述第一子像素驱动电路和所述第一阳极图形51耦接。
示例性的，所述第一阳极图形51位于所述第一子像素驱动电路背向所述基底的一侧，所述平坦化补偿图形20位于所述第一子像素驱动电路和所述第一阳极图形51之间。
由于所述第一阳极图形51与所述第一子像素驱动电路之间相距较远，通过所述平坦化补偿图形20在中间转接，能够更好的保证所述第一阳极图形51与所述第一子像素驱动电路之间的连接稳定性和信赖性。
而且，所述平坦化补偿图形20同时具备了平坦化补偿作用和转接作用，有效降低了所述显示基板的布局难度。
如图8和图14所示，在一些实施例中，设置所述平坦化补偿图形20包括第一补偿部分201和第二补偿部分202；
所述第一补偿部分201为沿所述第一方向延伸的条形结构，所述第一补偿部分201在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影部分交叠；
所述第二补偿部分202在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影不交叠。
示例性的，所述第二补偿部分202分别与所述第一子像素驱动电路和所述第一阳极图形51耦接。
如图8和图14所示，在一些实施例中，设置所述第一补偿部分201在所述基底上的正投影，位于所述第一阳极图形51在所述基底上的正投影的内 部；
所述第二补偿部分202在所述基底上的正投影，与所述第一阳极图形51在所述基底上的正投影部分交叠。
上述设置方式不仅保证所述第一阳极图形51与所述第一子像素驱动电路之间的连接稳定性和信赖性，还保证了所述第一阳极图形51的平坦度，有效降低了所述显示基板的布局难度。
如图3，图13至图16所示，在一些实施例中，设置所述显示基板还包括多个第二子像素，所述第二子像素包括第二像素开口12；至少部分所述第二像素开口12在所述基底上的正投影，位于相邻的数据线DA在所述基底上的正投影之间。
示例性的，所述第二像素开口12在所述基底上的正投影，与所述数据线DA在所述基底上的正投影不交叠。
示例性的，所述第二子像素包括第二子像素驱动电路和第二阳极图形52，所述第二阳极图形52与所述第二子像素驱动电路耦接，接收所述第二子像素驱动电路提供的驱动信号。
示例性的，所述第二像素开口12在所述基底上的正投影，位于所述第二阳极图形52在所述基底上的正投影的内部。
示例性的，所述第二阳极图形52与所述第二像素开口12交叠的部分在所述基底上的正投影，与所述数据线DA在所述基底上的正投影不交叠。
上述设置方式使得所述第二阳极图形52与所述第二像素开口12重叠的部分的平坦性，不会受到所述数据线DA的影响，进一步保证了所述显示基板的色偏参数。
如图3，图13至图16所示，在一些实施例中，所述显示基板还包括多个第三子像素；所述第三子像素包括第三像素开口13，所述第三像素开口13在所述基底上的正投影位于相邻的数据线DA在所述基底上的正投影之间；
所述多个第一子像素，所述多个第二子像素和所述多个第三子像素划分为多个像素单元，每个像素单元均包括一个第一子像素，一个第二子像素和一个第三子像素；在一个像素单元中，所述第二像素开口12和所述第三像素开口13沿所述第一方向位于同一列，所述第一像素开口11位于另一列。
示例性的，所述第三像素开口13在所述基底上的正投影，与所述数据线DA在所述基底上的正投影不交叠。
示例性的，所述第三子像素包括第三子像素驱动电路和第三阳极图形53，所述第三阳极图形53与所述第三子像素驱动电路耦接，接收所述第三子像素驱动电路提供的驱动信号。
示例性的，所述第三像素开口13在所述基底上的正投影，位于所述第三阳极图形53在所述基底上的正投影的内部。
示例性的，所述第三阳极图形53与所述第三像素开口13交叠的部分在所述基底上的正投影，与所述数据线DA在所述基底上的正投影不交叠。
示例性的，在一个像素单元中，第一子像素驱动电路，第二子像素驱动电路和第三子像素驱动电路沿所述第一方向依次排列。
示例性的，所述显示基板包括多个像素单元，所述多个像素单元划分为多列像素单元，每列像素单元中：所述第二像素开口12和所述第三像素开口13沿所述第一方向位于同一列，且所述第二像素开口12和所述第三像素开口13交替设置；所述第一像素开口11位于另一列。
示例性的，所述显示基板采用real RGB的像素排列方式。
上述设置方式使得所述第三阳极图形53与所述第三像素开口13重叠的部分的平坦性，不会受到所述数据线DA的影响，进一步保证了所述显示基板的色偏参数。
如图3，图13至图16所示，在一些实施例中，所述第二子像素包括第二连接部30，第二子像素驱动电路和第二阳极图形52，所述第二连接部30分别与所述第二子像素驱动电路和所述第二阳极图形52耦接；
所述第二连接部30与所述数据线DA同层同材料设置，所述第二连接部30在所述基底上的正投影，位于所述第二像素开口12在所述基底上的正投影和所述第三像素开口13在所述基底上的正投影之间；该第二像素开口12和该第三像素开口13沿所述第一方向位于同一列。
示例性的，所述第二连接部30采用第二源漏金属层制作。
示例性的，所述第二像素开口12和所述第三像素开口13均能够避开所述第二源漏金属层，不会与所述第二源漏金属层形成的结构在垂直于基底的 方向交叠。
示例性的，所述第二连接部30的至少部分位于所述第二子像素驱动电路和所述第二阳极图形52之间。
示例性的，所述第二连接部30在所述基底上的正投影与所述第二像素开口12在所述基底上的正投影不交叠。所述第二连接部30在所述基底上的正投影与所述第三像素开口13在所述基底上的正投影不交叠。
示例性的，所述第二连接部30在所述基底上的正投影与所述第二阳极图形52在所述基底上的正投影部分交叠。所述第二连接部30在所述基底上的正投影与所述第三阳极图形53在所述基底上的正投影部分交叠。
上述设置所述第二连接部30在所述基底上的正投影，位于所述第二像素开口12在所述基底上的正投影和所述第三像素开口13在所述基底上的正投影之间，避免了所述第二阳极图形52与所述第二像素开口12交叠的部分的平坦性，以及所述第三阳极图形53与所述第三像素开口13交叠的部分的平坦性，受到所述第二连接部30的影响，从而很好的保证了显示基板的色偏参数。
如图3，图7，图8，图12至图16，在一些实施例中，所述显示基板还包括：
多条电源线VDD，所述电源线VDD的至少部分沿所述第一方向延伸；
多条电源补偿线VDD-B，所述多条电源补偿线VDD-B与至少部分所述电源线VDD一一对应，所述电源补偿线VDD-B在所述基底上的正投影，与对应的电源线VDD在所述基底上的正投影至少部分交叠，所述电源补偿线VDD-B与对应的电源线VDD耦接。
示例性的，所述多条电源线VDD加载的电源信号相同。
示例性的，所述多条电源线VDD沿所述第二方向排列。
示例性的，所述电源线VDD采用所述第一源漏金属层制作。
示例性的，所述电源线VDD的最小线宽小于或等于3微米。
示例性的，所述电源补偿线VDD-B位于所述电源线VDD背向所述基底的一侧。
示例性的，所述电源补偿线VDD-B与对应的电源线VDD通过过孔耦接。
示例性的，所述电源补偿线VDD-B包括沿所述第一方向延伸的至少部分。
示例性的，所述显示基板包括多个像素单元，所述多个像素单元划分为多列像素单元。所述多列像素单元与所述多条电源补偿线VDD-B一一对应。所述电源补偿线VDD-B的至少部分位于对应的一列像素单元的布局区域内。
示例性的，所述电源补偿线VDD-B的延伸长度与所述电源线VDD的延伸长度大致相同；或者，所述电源补偿线VDD-B的延伸长度小于所述电源线VDD的延伸长度。
由于高像素密度的显示基板的子像素布局空间有限，因此需要适当缩小所述电源线VDD的线宽。而上述设置所述显示基板还包括所述电源补偿线VDD-B，使得所述电源线VDD和所述电源补偿线VDD-B实现双层设计，降低了所述电源线VDD的电阻，能够在缩窄所述电源线VDD线宽的情况下，很好的保证所述显示基板的显示均一性。
如图3，图7，图8，图12至图16，在一些实施例中，所述多条电源线VDD包括多条第一电源线VDD1，所述多条电源补偿线VDD-B包括多条第一电源补偿线，所述第一电源补偿线在所述基底上的正投影，与对应的第一电源线VDD1在所述基底上的正投影至少部分交叠，所述第一电源补偿线与对应的第一电源线VDD1耦接；
所述第一电源线VDD1在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影不交叠，所述第一电源补偿线在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影不交叠。
示例性的，所述多条电源线包括多条第一电源线VDD1，多条第二电源线VDD2和多条第三电源线VDD3。所述第一电源线VDD1，所述第二电源线VDD2和所述第三电源线VDD3电连接。示例性的，沿所述第二方向位于同一行的子像素驱动电路中包括的各存储电容Cst的第二极板Cst2依次耦接，每个子像素驱动电路中的所述第二极板Cst2均与对应的电源线耦接。所述显示基板中的电源线，电源补偿线VDD-B，以及所述第二极板Cst2共同形成网格状结构。
所述多条第一电源线VDD1与所述多列第一子像素驱动电路列一一对应，所述第一电源线VDD1与对应的一列第一子像素驱动电路列中的各第一子像素驱动电路分别耦接。
所述多条第二电源线VDD2与所述多列第二子像素驱动电路列一一对应，所述第二电源线VDD2与对应的一列第二子像素驱动电路列中的各第二子像素驱动电路分别耦接。
所述多条第三电源线VDD3与所述多列第三子像素驱动电路列一一对应，所述第三电源线VDD3与对应的一列第三子像素驱动电路列中的各第三子像素驱动电路分别耦接。
示例性的，所述多条第一电源补偿线与所述多条第一电源线VDD1一一对应，所述第一电源补偿线在所述基底上的正投影，与对应的第一电源线VDD1在所述基底上的正投影具有交叠区，所述第一电源补偿线与对应的第一电源线VDD1在交叠区通过过孔耦接。
上述设置所述显示基板包括所述第一电源线VDD1和所述第一电源补偿线，有效降低了显示基板电源线整体的电阻，提升了显示基板的显示均一性。
上述设置所述第一电源线VDD1在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影不交叠，所述第一电源补偿线在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影不交叠，避免了所述第一电源线VDD1和所述第一电源补偿线对所述第一阳极图形51的平坦性产生影响。
如图3，图7，图12和图15，在一些实施例中，所述多条电源线包括多条第二电源线VDD2，所述多条电源补偿线包括多条第二电源补偿线，所述第二电源补偿线在所述基底上的正投影，与对应的第二电源线VDD2在所述基底上的正投影至少部分交叠，所述第二电源补偿线与对应的第二电源线VDD2耦接；
所述第二电源线VDD2在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影部分交叠，所述第二电源补偿线在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影不交叠。
示例性的，所述多条第二电源补偿线与所述多条第二电源线VDD2一一对应，所述第二电源补偿线在所述基底上的正投影，与对应的第二电源线VDD2在所述基底上的正投影具有交叠区，所述第二电源补偿线与对应的第二电源线VDD2在交叠区通过过孔耦接。
上述设置所述显示基板包括所述第二电源线VDD2和所述第二电源补偿线，有效降低了显示基板电源线整体的电阻，提升了显示基板的显示均一性。
上述设置所述第二电源补偿线在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影不交叠，避免了所述第二电源补偿线对所述第一阳极图形51的平坦性产生影响。
如图3，图7，图12和图15，在一些实施例中，所述多条电源线包括多条第二电源线VDD2，所述多条电源补偿线包括多条第二电源补偿线，所述第二电源补偿线在所述基底上的正投影，与对应的第二电源线VDD2在所述基底上的正投影至少部分交叠，所述第二电源补偿线与对应的第二电源线VDD2耦接；
所述第二电源线VDD2在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影部分交叠，所述第二电源补偿线在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影部分交叠；
所述目标数据线DA在所述基底上的正投影的至少部分，位于所述第二电源补偿线在所述基底上的正投影和所述平坦化补偿图形20在所述基底上的正投影之间。
示例性的，示例性的，所述多条第二电源补偿线与所述多条第二电源线VDD2一一对应，所述第二电源补偿线在所述基底上的正投影，与对应的第二电源线VDD2在所述基底上的正投影具有交叠区，所述第二电源补偿线与对应的第二电源线VDD2在交叠区通过过孔耦接。
上述设置所述显示基板包括所述第二电源线VDD2和所述第二电源补偿线，有效降低了显示基板电源线整体的电阻，提升了显示基板的显示均一性。
上述设置所述第二电源补偿线在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影部分交叠；所述目标数据线在所述基底上的正投影的至少部分，位于所述第二电源补偿线在所述基底上的正投影和所述平坦化补偿图形20在所述基底上的正投影之间；有效提升了所述第一阳极图形51的平坦性。
如图3，图7，图12和图15，在一些实施例中，所述多条电源线包括多条第三电源线VDD3，所述第三电源线VDD3在所述基底上的正投影，与所述 第二像素开口12在所述基底上的正投影至少部分交叠；所述第三电源线VDD3在所述基底上的正投影，与所述第三像素开口13在所述基底上的正投影至少部分交叠。
示例性的，所述第一电源线VDD1，所述第二电源线VDD2和所述第三电源线VDD3均采用第一源漏金属层制作，所述第一源漏金属层与阳极图形之间距离较远，且所述第一源漏金属层与阳极图形之间具有两层平坦层，因此，所述第一电源线VDD1，所述第二电源线VDD2和所述第三电源线VDD3对阳极图形的平坦影响不大。
如图3，图6，图7，图8，图10至图16，在一些实施例中，所述显示基板还包括：
多条第一初始化信号线Vinit1，所述第一初始化信号线Vinit1的至少部分沿所述第二方向延伸；
多个初始化补偿图形Vinit-B，所述初始化补偿图形Vinit-B的至少部分沿所述第一方向延伸；相邻的所述第一初始化信号线Vinit1之间，通过至少一个初始化补偿图形Vinit-B耦接。
示例性的，所述第一初始化信号线Vinit1采用第二栅金属层制作。所述初始化补偿图形Vinit-B采用第二源漏金属层制作。
示例性的，所述第一初始化信号线Vinit1用于传输第一初始化信号。
示例性的，所述一初始化信号线与所述初始化补偿图形Vinit-B之间可以通过转接图形和过孔实现耦接。示例性的，所述转接图形采用第一源漏金属层制作。
示例性的，相邻的所述第一初始化信号线Vinit1之间通过多个初始化补偿图形Vinit-B耦接。沿所述第二方向位于同一行的多个像素单元与所述多个初始化补偿图形Vinit-B一一对应。所述初始化补偿图形Vinit-B的至少部分位于对应的像素单元的布局区域内。
示例性的，沿所述第一方向位于同一列的所述初始化补偿图形Vinit-B依次耦接，形成为一体结构。
上述设置所述显示基板包括所述第一初始化信号线Vinit1和初始化补偿图形Vinit-B，使得所述第一初始化信号线Vinit1和所述初始化补偿图形 Vinit-B共同形成网格状结构，从而改善了第一初始化信号线Vinit1的电阻，提高了显示基板在高灰阶下的显示均一性。
如图16所示，在一些实施例中，所述多条电源线包括多条第二电源线VDD2；所述初始化补偿图形Vinit-B在所述基底上的正投影与所述第二电源线VDD2在所述基底上的正投影至少部分交叠。
示例性的，所述初始化补偿图形Vinit-B在垂直于其自身延伸方向上的线宽，小于所述第二电源线VDD2在垂直于其自身延伸方向上的线宽。
上述设置所述初始化补偿图形Vinit-B在所述基底上的正投影与所述第二电源线VDD2在所述基底上的正投影至少部分交叠，能够通过所述第二电源线VDD2对所述初始化补偿图形Vinit-B进行信号屏蔽，有效避免了所述初始化补偿图形Vinit-B与显示基板中的其他结构之间形成额外的寄生电容。
在一些实施例中，设置所述初始化补偿图形Vinit-B在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影部分交叠，所述目标数据线DA在所述基底上的正投影的至少部分，位于所述初始化补偿图形Vinit-B在所述基底上的正投影和所述平坦化补偿图形20在所述基底上的正投影之间。
上述设置方式进一步提升了所述第一阳极图形51位于所述第一像素开口11下方的部分的平坦性。
在一些实施例中，所述第二电源线VDD2在所述基底上的正投影与所述第一像素开口11在所述基底上的正投影部分交叠。
在一些实施例中，所述多条电源线包括多条第一电源线VDD1；所述初始化补偿图形Vinit-B在所述基底上的正投影与所述第一电源线VDD1在所述基底上的正投影至少部分交叠。
示例性的，所述初始化补偿图形Vinit-B在垂直于其自身延伸方向上的线宽，小于所述第一电源线VDD1在垂直于其自身延伸方向上的线宽。
如图16所示，示例性的，所述初始化补偿图形Vinit-B和所述电源补偿线VDD-B与不同的电源线交叠。
上述设置所述初始化补偿图形Vinit-B在所述基底上的正投影与所述第一电源线VDD1在所述基底上的正投影至少部分交叠，能够通过所述第一电源 线VDD1对所述初始化补偿图形Vinit-B进行信号屏蔽，有效避免了所述初始化补偿图形Vinit-B与显示基板中的其他结构之间形成额外的寄生电容。
如图16所示，在一些实施例中，设置所述初始化补偿图形Vinit-B在所述基底上的正投影，与所述第一像素开口11在所述基底上的正投影不交叠。
上述设置方式使得所述第一阳极图形51中位于所述第一像素开口11下方的部分的平坦性，不会受到所述初始化补偿图形Vinit-B影响。
如图16所示，在一些实施例中，所述多个像素单元划分为多列像素单元，每列像素单元均包括沿所述第一方向排列的多个像素单元；
所述显示基板还包括多条第一电源线VDD1，多条第二电源线VDD2和多条第三电源线VDD3；
所述第一电源线VDD1与对应的一列像素单元中各第一子像素分别耦接；
所述第二电源线VDD2与对应的一列像素单元中各第二子像素分别耦接；
所述第三电源线VDD3与对应的一列像素单元中各第三子像素分别耦接。
示例性的，所述多条第一电源线VDD1与所述多列像素单元一一对应，所述多条第二电源线VDD2与所述多列像素单元一一对应，所述多条第三电源线VDD3与所述多列像素单元一一对应；所述第一电源线VDD1，所述第二电源线VDD2和所述第三电源线VDD3加载相同的电源信号；
示例性的，所述第一电源线VDD1，所述第二电源线VDD2和所述第三电源线VDD3加载相同的电源信号。
示例性的，所述显示基板还包括位于非显示区域的电源总线，所述第一电源线VDD1，所述第二电源线VDD2和所述第三电源线VDD3均与所述电源总线耦接。
如图16所示，在一些实施例中，所述第一子像素包括蓝色子像素，所述第二子像素包括红色子像素，所述第三子像素包括绿色子像素；所述第三电源线VDD3，所述第二电源线VDD2和所述第一电源线VDD1沿所述第二方向依次排列。
如图7和8所示，在一些实施例中，所述数据线DA，所述平坦化补偿图形20，所述电源补偿线VDD-B和所述初始化补偿图形Vinit-B同层同材料设置，所述电源线与所述电源补偿线VDD-B异层设置。
示例性的，所述数据线DA，所述平坦化补偿图形20，所述电源补偿线VDD-B和所述初始化补偿图形Vinit-B均采用第二源漏金属层制作。所述电源线采用第一源漏金属层制作。
如图6，图10至图13所示，在一些实施例中，所述显示基板还包括多条第二初始化信号线Vinit2，所述第二初始化信号线Vinit2包括沿所述第二方向延伸的至少部分；所述第一子像素，所述第二子像素和所述第三子像素均包括子像素驱动电路；所述子像素驱动电路包括驱动晶体管，第一复位晶体管，第二复位晶体管和发光元件；
所述第一复位晶体管的第一极与对应的所述第一初始化信号线Vinit1耦接，所述第一复位晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第二复位晶体管的第一极与对应的所述第二初始化信号线Vinit2耦接，所述第二复位晶体管的第二极与所述发光元件耦接。
示例性的，所述第二初始化信号线Vinit2采用第二栅金属层制作。
示例性的，所述显示基板包括多条栅线GA，多条复位线Rst和多条发光控制线EM；所述栅线GA的至少部分，所述复位线Rst的至少部分和所述发光控制线EM的至少部分均沿所述第二方向延伸。
如图1，图3至图13所示，所述子像素驱动电路包括第一晶体管T1至第七晶体管T7。
所述第一晶体管T1的栅极与对应的栅线GA耦接，所述第一晶体管T1第一极与第三晶体管T3(即所述驱动晶体管)的第二极耦接，所述第一晶体管T1的第二极与所述第三晶体管T3的栅极耦接。
第二晶体管T2(即所述第一复位晶体管)的栅极与对应的复位线Rst耦接，所述第二晶体管T2的第一极与对应的所述第一初始化信号线Vinit1耦接，所述第二晶体管T2的第二极与所述第三晶体管T3的栅极耦接。所述第三晶体管T3的栅极复用为存储电容Cst的第一极板Cst1，所述存储电容Cst的第二极板Cst2与电源线耦接。
第四晶体管T4的栅极与对应的栅线GA耦接，所述第四晶体管T4的第一极与对应的数据线DA耦接，所述第四晶体管T4的第二极与所述第三晶体管T3的第一极耦接。
第五晶体管T5的栅极与对应的发光控制线EM耦接，所述第五晶体管T5第一极与电源线耦接，所述第五晶体管T5的第二极与所述第三晶体管T3的第一极耦接。
第六晶体管T6的栅极与对应的发光控制线EM耦接，所述第六晶体管T6的第一极与所述第三晶体管T3的第二极耦接，所述第六晶体管T6的第二极与发光元件EL的阳极耦接。
第七晶体管T7(即第二复位晶体管)，所述第七晶体管T7的栅极与沿所述第一方向相邻的子像素耦接的复位线Rst耦接，所述第七晶体管T7的第一极与所述第二初始化信号线Vinit2耦接，所述第七晶体管T7的第二极与所述发光元件EL的阳极耦接，发光元件EL的阴极接收负电源信号VSS。
如图17所示，示例性的，所述显示基板包括沿远离所述基底60的方向依次层叠设置的有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层Gate2，层间绝缘层ILD，第一源漏金属层SD1，第一平坦层PLN1，第二源漏金属层SD2，第二平坦层PLN2，阳极层50，像素界定层PDL，发光功能层，阴极层和封装层。
如图4所示，示例性的，所述有源层用于形成所述第一晶体管T1包括的第一有源层41，所述第二晶体管T2包括的第二有源层42，所述第三晶体管T3包括的第三有源层43，所述第四晶体管T4包括的第四有源层44，所述第五晶体管T5包括的第五有源层45，所述第六晶体管T6包括的第六有源层46和所述第七晶体管T7包括的第七有源层47。
示例性的，所述第一栅金属层用于形成所述复位线Rst，所述栅线GA，所述发光控制线EM，以及各晶体管的栅极。
示例性的，所述第二栅金属层Gate2用于形成所述第一初始化信号线Vinit1，所述第二初始化信号线Vinit2和所述存储电容Cst的第二极板Cst2。
示例性的，所述第一源漏金属层SD1用于形成所述电源线VDD和一些导电图形。
示例性的，所述第二源漏金属层用于形成所述数据线DA和一些导电图形。
示例性的，所述阳极层50用于形成各发光元件EL包括的阳极图形。
示例性的，所述显示基板的基底包括有机PI基底。所述显示基板的制作工艺流程包括：
在所述基底上沉积有源材料层，对所述有源材料层进行图形化，形成所述有源层。需要说明，图形化的过程包括：在有源材料层背向所述基底的一侧形成光刻胶，对所述光刻胶进行曝光，显影，然后以剩余的光刻胶为掩膜刻蚀所述有源材料层，形成所述有源层。
在所述有源层背向所述基底的一侧沉积无机材料，形成所述第一栅极绝缘层。
在所述第一栅极绝缘层背向所述基底的一侧沉积金属材料，形成第一栅金属材料层，对所述第一栅金属材料层进行图形化，形成所述第一栅金属层。
在所述第一栅金属层背向所述基底的一侧沉积无机材料，形成所述第二栅极绝缘层。
在所述第二栅极绝缘层背向所述基底的一侧沉积金属材料，形成第二栅金属材料层，对所述第二栅金属材料层进行图形化，形成所述第二栅金属层Gate2。
在所述第二栅金属层Gate2背向所述基底的一侧沉积形成所述层间绝缘层ILD。进行构图工艺，形成多个过孔。该多个过孔中的第一部分过孔仅贯穿所述层间绝缘层ILD，该第一部分过孔能够暴露所述第二栅金属层Gate2，所述第一源漏金属层SD1能够通过第一部分过孔与所述第二栅金属层Gate2耦接。所述多个过孔中的第二部分过孔能够贯穿所述层间绝缘层ILD，所述第二栅极绝缘层和所述第一栅极绝缘层，所述第二部分过孔能够暴露所述有源层，所述第一源漏金属层SD1能够通过第二部分过孔与所述有源层耦接。所述多个过孔还可以包括第三部分过孔，所述第三部分过孔能够贯穿所述层间绝缘层ILD和所述第二栅极绝缘层，所述第三部分过孔能够暴露所述第一栅金属层，所述第一源漏金属层SD1能够通过第三部分过孔与所述第一栅金属层耦接。
在所述层间绝缘层ILD背向所述基底的一侧沉积形成金属材料层，对所述金属材料层进行图形化，形成所述第一源漏金属层SD1。
在所述第一源漏金属层SD1背向所述基底的一侧沉积形成第一平坦层 PLN1。
在所述第一平坦层PLN1背向所述基底的一侧沉积形成金属材料层，对所述金属材料层进行图形化，形成所述第二源漏金属层SD2。
在所述第二源漏金属层SD2背向所述基底的一侧沉积形成第二平坦层PLN2。
在所述第二平坦层PLN2背向所述基底的一侧沉积形成阳极材料层，对所述阳极材料层进行图形化，形成所述阳极层50。
在所述阳极层50背向所述基底的一侧形成像素界定层，所述像素界定层包括多个像素开口。
如图1和图2所示，上述结构的子像素驱动电路在工作时，每个工作周期均包括第一复位时段P1、写入补偿时段P2、第二复位时段P3和发光时段P4。
在所述第一复位时段P1，复位线Rst输入的复位信号处于有效电平，第二晶体管T2导通，由第一初始化信号线Vinit1传输的第一初始化信号输入至第三晶体管T3的栅极T3-g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极T3-g复位。
在写入补偿时段P2，所述复位信号处于非有效电平，第二晶体管T2截止，栅线GA输入的栅极扫描信号处于有效电平，控制第一晶体管T1和第四晶体管T4导通，数据线DA写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的第一极，同时，第一晶体管T1和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极T3-g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在第二复位时段P3，所述栅极扫描信号处于非有效电平，第一晶体管T1和第四晶体管T4均截止，相邻的下一行子像素耦接的复位线Rst’输入的复位信号处于有效电平，控制第七晶体管T7导通，将所述第二初始化信号线Vinit2输入的初始化信号输入至发光元件EL的阳极，控制发光元件EL不发 光。
在发光时段P4，发光控制线EM写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源线VDD传输的电源信号输入至第三晶体管T3的第一极，同时由于第三晶体管T3的栅极T3-g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极，驱动对应的发光元件EL发光。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
上述实施例提供的显示基板中，通过设置所述第一像素开口11在所述基底上的正投影，与所述多条数据线DA中的目标数据线在所述基底上的正投影部分交叠；以及设置所述第一像素开口11在所述基底上的正投影，与所述平坦化补偿图形20在所述基底上的正投影部分交叠；使得所述第一阳极图形51与所述第一像素开口11重叠的部分在所述基底上的正投影，与所述多条数据线DA中的目标数据线在所述基底上的正投影部分交叠；并使得所述第一阳极图形51与所述第一像素开口11重叠的部分在所述基底上的正投影，与所述平坦化补偿图形20在所述基底上的正投影部分交叠。所述平坦化补偿图形20补偿了所述目标数据线在所述第一阳极图形51下方产生的段差，使得所述第一阳极图形51下方的结构能够均匀的对称分布，提升了所述第一阳极图形51的平坦性，从而有效改善了所述显示基板的色偏参数，保证了显示基板的显示质量。
本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显 影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种显示基板，包括：基底，设置于所述基底上的多条数据线，以及设置于所述基底上的多个第一子像素；所述第一子像素包括：
    第一像素开口，所述第一像素开口在所述基底上的正投影，与所述多条数据线中的目标数据线在所述基底上的正投影部分交叠；
    平坦化补偿图形，所述平坦化补偿图形的至少部分沿第一方向延伸，所述平坦化补偿图形在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影至少部分交叠，所述平坦化补偿图形与所述目标数据线沿第二方向排列，所述第二方向与所述第一方向相交。
  2. 根据权利要求1所述的显示基板，其中，所述第一子像素还包括第一子像素驱动电路和第一阳极图形；所述平坦化补偿图形分别与所述第一子像素驱动电路和所述第一阳极图形耦接。
  3. 根据权利要求2所述的显示基板，其中，所述平坦化补偿图形包括第一补偿部分和第二补偿部分；
    所述第一补偿部分为沿所述第一方向延伸的条形结构，所述第一补偿部分在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠；
    所述第二补偿部分在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠。
  4. 根据权利要求3所述的显示基板，其中，所述第一补偿部分在所述基底上的正投影，位于所述第一阳极图形在所述基底上的正投影的内部；
    所述第二补偿部分在所述基底上的正投影，与所述第一阳极图形在所述基底上的正投影部分交叠。
  5. 根据权利要求1所述的显示基板，其中，所述显示基板还包括多个第二子像素，所述第二子像素包括第二像素开口；
    至少部分所述第二像素开口在所述基底上的正投影，位于相邻的数据线在所述基底上的正投影之间。
  6. 根据权利要求5所述的显示基板，其中，所述显示基板还包括多个第 三子像素；所述第三子像素包括第三像素开口，所述第三像素开口在所述基底上的正投影位于相邻的数据线在所述基底上的正投影之间；
    所述多个第一子像素，所述多个第二子像素和所述多个第三子像素划分为多个像素单元，每个像素单元均包括一个第一子像素，一个第二子像素和一个第三子像素；在一个像素单元中，所述第二像素开口和所述第三像素开口沿所述第一方向位于同一列，所述第一像素开口位于另一列。
  7. 根据权利要求6所述的显示基板，其中，所述第二子像素包括第二连接部，第二子像素驱动电路和第二阳极图形，所述第二连接部分别与所述第二子像素驱动电路和所述第二阳极图形耦接；
    所述第二连接部与所述数据线同层同材料设置，所述第二连接部在所述基底上的正投影，位于所述第二像素开口在所述基底上的正投影和所述第三像素开口在所述基底上的正投影之间；该第二像素开口和该第三像素开口沿所述第一方向位于同一列。
  8. 根据权利要求6所述的显示基板，其中，所述显示基板还包括：
    多条电源线，所述电源线的至少部分沿所述第一方向延伸；
    多条电源补偿线，所述多条电源补偿线与至少部分所述电源线一一对应，所述电源补偿线在所述基底上的正投影，与对应的电源线在所述基底上的正投影至少部分交叠，所述电源补偿线与对应的电源线耦接。
  9. 根据权利要求8所述的显示基板，其中，所述多条电源线包括多条第一电源线，所述多条电源补偿线包括多条第一电源补偿线，所述第一电源补偿线在所述基底上的正投影，与对应的第一电源线在所述基底上的正投影至少部分交叠，所述第一电源补偿线与对应的第一电源线耦接；
    所述第一电源线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠，所述第一电源补偿线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠。
  10. 根据权利要求8所述的显示基板，其中，所述多条电源线包括多条第二电源线，所述多条电源补偿线包括多条第二电源补偿线，所述第二电源补偿线在所述基底上的正投影，与对应的第二电源线在所述基底上的正投影至少部分交叠，所述第二电源补偿线与对应的第二电源线耦接；
    所述第二电源线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠，所述第二电源补偿线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠。
  11. 根据权利要求8所述的显示基板，其中，所述多条电源线包括多条第二电源线，所述多条电源补偿线包括多条第二电源补偿线，所述第二电源补偿线在所述基底上的正投影，与对应的第二电源线在所述基底上的正投影至少部分交叠，所述第二电源补偿线与对应的第二电源线耦接；
    所述第二电源线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠，所述第二电源补偿线在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠；
    所述目标数据线在所述基底上的正投影的至少部分，位于所述第二电源补偿线在所述基底上的正投影和所述平坦化补偿图形在所述基底上的正投影之间。
  12. 根据权利要求8所述的显示基板，其中，所述多条电源线包括多条第三电源线，所述第三电源线在所述基底上的正投影，与所述第二像素开口在所述基底上的正投影至少部分交叠；所述第三电源线在所述基底上的正投影，与所述第三像素开口在所述基底上的正投影至少部分交叠。
  13. 根据权利要求8所述的显示基板，其中，所述显示基板还包括：
    多条第一初始化信号线，所述第一初始化信号线的至少部分沿所述第二方向延伸；
    多个初始化补偿图形，所述初始化补偿图形的至少部分沿所述第一方向延伸；相邻的所述第一初始化信号线之间，通过至少一个初始化补偿图形耦接。
  14. 根据权利要求13所述的显示基板，其中，所述多条电源线包括多条第二电源线；所述初始化补偿图形在所述基底上的正投影与所述第二电源线在所述基底上的正投影至少部分交叠。
  15. 根据权利要求14所述的显示基板，其中，所述初始化补偿图形在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影部分交叠，所述目标数据线在所述基底上的正投影的至少部分，位于所述初始化补偿图 形在所述基底上的正投影和所述平坦化补偿图形在所述基底上的正投影之间。
  16. 根据权利要求14所述的显示基板，其中，所述第二电源线在所述基底上的正投影与所述第一像素开口在所述基底上的正投影部分交叠。
  17. 根据权利要求13所述的显示基板，其中，所述多条电源线包括多条第一电源线；所述初始化补偿图形在所述基底上的正投影与所述第一电源线在所述基底上的正投影至少部分交叠。
  18. 根据权利要求14或17所述的显示基板，其中，所述初始化补偿图形在所述基底上的正投影，与所述第一像素开口在所述基底上的正投影不交叠。
  19. 根据权利要求6所述的显示基板，其中，所述多个像素单元划分为多列像素单元，每列像素单元均包括沿所述第一方向排列的多个像素单元；
    所述显示基板还包括多条第一电源线，多条第二电源线和多条第三电源线；所述第一电源线与对应的一列像素单元中各第一子像素分别耦接；
    所述第二电源线与对应的一列像素单元中各第二子像素分别耦接；
    所述第三电源线与对应的一列像素单元中各第三子像素分别耦接。
  20. 根据权利要求19所述的显示基板，其中，所述第一子像素包括蓝色子像素，所述第二子像素包括红色子像素，所述第三子像素包括绿色子像素；所述第三电源线，所述第二电源线和所述第一电源线沿所述第二方向依次排列。
  21. 根据权利要求13所述的显示基板，其中，所述数据线，所述平坦化补偿图形，所述电源补偿线和所述初始化补偿图形同层同材料设置，所述电源线与所述电源补偿线异层设置。
  22. 根据权利要求13所述的显示基板，其中，所述显示基板还包括多条第二初始化信号线，所述第二初始化信号线包括沿所述第二方向延伸的至少部分；所述第一子像素，所述第二子像素和所述第三子像素均包括子像素驱动电路；所述子像素驱动电路包括驱动晶体管，第一复位晶体管，第二复位晶体管和发光元件；
    所述第一复位晶体管的第一极与对应的所述第一初始化信号线耦接，所 述第一复位晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第二复位晶体管的第一极与对应的所述第二初始化信号线耦接，所述第二复位晶体管的第二极与所述发光元件耦接。
  23. 一种显示装置，包括如权利要求1～22中任一项所述的显示基板。
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