WO2023279374A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023279374A1
WO2023279374A1 PCT/CN2021/105495 CN2021105495W WO2023279374A1 WO 2023279374 A1 WO2023279374 A1 WO 2023279374A1 CN 2021105495 W CN2021105495 W CN 2021105495W WO 2023279374 A1 WO2023279374 A1 WO 2023279374A1
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Prior art keywords
sub
pixel
pixels
transistor
substrate
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PCT/CN2021/105495
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English (en)
French (fr)
Inventor
袁粲
李永谦
徐攀
袁志东
张大成
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/105495 priority Critical patent/WO2023279374A1/zh
Priority to CN202180001839.5A priority patent/CN115804262A/zh
Priority to US17/789,210 priority patent/US20240179968A1/en
Priority to DE112021007946.8T priority patent/DE112021007946T5/de
Publication of WO2023279374A1 publication Critical patent/WO2023279374A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • OLED Organic Light-Emitting Diode
  • the purpose of the present disclosure is to provide a display substrate and a display device.
  • a first aspect of the present disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels are arranged in an array;
  • the sub-pixel includes a sub-pixel driving circuit and a light-emitting element
  • the sub-pixel driving circuit includes a coupled driving sub-circuit and a light-emitting control sub-circuit
  • the light-emitting element includes an anode pattern
  • the plurality of sub-pixels are divided into multiple groups of sub-pixels, each group of sub-pixels includes two sub-pixels arranged along the first direction, and the two sub-pixel driving circuits included in the two sub-pixels multiplex the same light emission control sub-circuit,
  • the light emission control sub-circuit is used to respectively control the driving sub-circuit in the two sub-pixels to write a driving signal to the anode pattern;
  • the sub-pixel also includes a data line including a portion extending in the first direction.
  • the sub-pixels also include:
  • the light emission control signal line including a portion extending along a second direction intersecting the first direction
  • the two subpixel drive circuits included in the two subpixels multiplex the same light emission control signal line, and the light emission control signal line is coupled to the light emission control subcircuit for controlling the light emission control subcircuit;
  • the orthographic projection of the light emission control signal line on the substrate is located between the orthographic projections of the two anode patterns included in the two sub-pixels on the substrate.
  • the light emission control subcircuit includes a light emission control transistor, the gate of the light emission control transistor is coupled to the light emission control signal line, and the second pole of the light emission control transistor is coupled to the driving subcircuit ;
  • the light emission control transistor includes a light emission control active layer, the light emission control active layer includes a portion extending along the second direction, and the orthographic projection of the light emission control active layer on the substrate is located between the two sides between the orthographic projections of the two anode patterns included in the sub-pixels on the substrate.
  • the sub-pixels also include:
  • the power line includes a portion extending along the first direction, and the power lines included in the two sub-pixels are coupled;
  • the first electrode of the light emission control transistor is coupled to the power line, and the light emission control transistor is used to turn on or off the power line and the two sub-pixels under the control of the light emission control signal line. connections between the driver subcircuits in the
  • the sub-pixels also include:
  • a power connection part the power connection part includes a part extending along the second direction; the two subpixel driving circuits included in the two subpixels multiplex the same power connection part;
  • the orthographic projection of the power line on the substrate is located on one side of the orthographic projection of the luminescence control active layer on the substrate, and the first pole of the luminescence control transistor is connected to the power supply line through the power connection part. coupling.
  • the power connection part and the lighting control signal line are provided in the same layer and the same material.
  • the plurality of sub-pixels are divided into a plurality of pixel units, and the pixel units include at least two sub-pixels arranged along the second direction;
  • the at least two sub-pixels multiplex the same power line, and the power connection parts included in the at least two sub-pixels are sequentially coupled.
  • the driving sub-circuit includes a driving transistor, the first pole of the driving transistor is coupled to the second pole of the light emission control transistor, the second pole of the driving transistor is connected to the anode pattern of the light emitting element coupling;
  • the driving transistor includes a driving active layer; in the two sub-pixel driving circuits, the driving active layers included in the two driving transistors are arranged axially symmetrically, and the axis of symmetry extends along the second direction, and the axis of symmetry
  • the orthographic projection on the substrate is located between the orthographic projections of the two anode patterns included in the two sub-pixels on the substrate.
  • the orthographic projection of the symmetry axis on the substrate overlaps with the orthographic projection of the light emission control active layer on the substrate.
  • the sub-pixel further includes a first scan line, and the first scan line includes a portion extending along the second direction;
  • the sub-pixel driving circuit further includes a first transistor, the gate of the first transistor is coupled to the first scan line, the first pole of the first transistor is coupled to the data line, and the first transistor is coupled to the first scan line. the second pole of a transistor is coupled to the gate of the drive transistor;
  • the first transistor includes a first active layer, and the first active layer includes a portion extending along the second direction; in the same sub-pixel, the first active layer, the driving active layer and the light emission control active layer are sequentially arranged along the first direction.
  • the first active layers included in the two first transistors are disposed symmetrically with respect to the symmetry axis.
  • the plurality of sub-pixels are divided into a plurality of pixel units, at least some of the pixel units include first sub-pixels, second sub-pixels and third sub-pixels arranged along the second direction, and the first The sub-pixel includes a first data line, the second sub-pixel includes a second data line, and the third sub-pixel includes a third data line;
  • the first data line is located on the side of the first sub-pixel away from the second sub-pixel along the second direction, and the second data line and the third data line are located between the second sub-pixel and the third sub-pixel; there is a first space between the first sub-pixel and the second sub-pixel;
  • the first data line and the second data line are both located between the first sub-pixel and the second sub-pixel, and the third data line is located in the third
  • the sub-pixel is away from the side of the second sub-pixel along the second direction; there is a second spacer between the second sub-pixel and the third sub-pixel.
  • the multiple groups of sub-pixels are divided into multiple rows of sub-pixel groups arranged along the first direction, and each row of sub-pixel groups includes multiple groups of sub-pixels arranged along the second direction;
  • the display substrate also includes a plurality of gate drive circuit layout areas and a plurality of gate drive wiring layout areas;
  • each gate drive circuit layout area corresponds one-to-one to the multiple rows of sub-pixel groups, each gate drive circuit layout area includes a first layout area and a second layout area, along the first direction, the The first layout area is located on the first side of the corresponding row of sub-pixel groups, and the second layout area is located on the second side of the corresponding row of sub-pixel groups;
  • the plurality of gate driving circuit layout areas correspond to the plurality of gate driving wiring layout areas one by one, and the gate driving wiring layout areas include at least two third layouts arranged along the second direction Area;
  • At least one of the third layout areas is located in the first interval area in a corresponding row of sub-pixel groups; at least one of the third layout areas is located in a corresponding row of sub-pixel groups The second spacer in .
  • the sub-pixel further includes a reference signal line and a second scanning line, the reference signal line includes a portion extending along the first direction, the second scanning line includes a portion extending along the second direction part;
  • the sub-pixel driving circuit further includes a second transistor, the gate of the second transistor is coupled to the second scanning line, the first electrode of the second transistor is coupled to the reference signal line, and the second pole of the second transistor is coupled to the gate of the drive transistor;
  • the second transistor includes a second active layer, and the second active layer includes a portion extending along the second direction; in the same sub-pixel, the second active layer, the first active layers and the light emission control active layer are sequentially arranged along the first direction.
  • the second active layers included in the two second transistors are arranged symmetrically with respect to the symmetry axis.
  • the sub-pixel further includes a reference connection part, and the reference connection part includes a part extending along the second direction; the first electrode of the second transistor is connected to the reference signal via the reference connection part. line coupling.
  • the plurality of sub-pixels are divided into a plurality of pixel units, and the pixel units include at least two sub-pixels arranged along the second direction;
  • the sub-pixels included in two adjacent pixel units arranged along the second direction are multiplexed with one reference signal line, and the reference signal line is located between the two adjacent pixel units.
  • the reference connection parts included in the sub-pixels are sequentially coupled.
  • the orthographic projection of the reference connection part on the substrate, the orthographic projection of the second scanning line on the substrate, and the first scanning line on the substrate Orthographic projections of the light emission control signal lines on the substrate are sequentially arranged along the first direction.
  • the sub-pixel further includes an initialization signal line and a third scanning line, and each of the initialization signal line and the third scanning line includes a portion extending along the second direction;
  • the sub-pixel driving circuit further includes a third transistor, the gate of the third transistor is coupled to the third scanning line, the first electrode of the third transistor is coupled to the initialization signal line, and the gate of the third transistor is coupled to the initialization signal line.
  • the second pole of the third transistor is coupled to the anode pattern of the light emitting element;
  • the third transistor includes a third active layer; in the same sub-pixel, the first active layer, the third active layer and the light emission control active layer are arranged in sequence along the first direction.
  • the third active layers included in the two third transistors are disposed symmetrically with respect to the symmetry axis.
  • At least one of the first transistor, the second transistor and the third transistor includes a double gate structure.
  • the sub-pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first pole plate and a second pole plate oppositely arranged, and the first pole plate is located between the base and the second pole plate. Between; the first plate is coupled to the gate of the drive transistor, and the second plate is respectively coupled to the second pole of the drive transistor and the anode pattern of the light-emitting element;
  • the two first polar plates are arranged symmetrically about the axis of symmetry; and/or, the two second polar plates are arranged symmetrically about the axis of symmetry.
  • the sub-pixel further includes a first conductive connection part and a second conductive connection part arranged in different layers, the first conductive connection part is located between the base and the second conductive connection part, the The anode pattern is located on the side of the second conductive connection part facing away from the substrate;
  • the second pole plate is coupled to the first conductive connection part
  • the orthographic projection on the substrate has a second overlapping area with the orthographic projection of the anode pattern on the substrate;
  • the second conductive connection part is coupled to the first conductive connection part through a first via hole, and the orthographic projection of the first via hole on the substrate is located in the first overlapping area; the second The conductive connection part is coupled to the anode pattern through a second via hole, and the orthographic projection of the second via hole on the substrate is located in the second overlapping area.
  • At least a part of the orthographic projection of the first conductive connection part on the substrate is located at the orthographic projection of the third active pattern on the substrate, and the driving active layer is located on the substrate. Between orthographic projections on the base.
  • the third active layer includes a coupled first portion and a second portion, the first portion includes a portion extending along the first direction, the second portion includes a portion extending along the second direction
  • the first part and the second part are formed into an L-shaped structure; in the same sub-pixel, the third active layer and the driving active layer are arranged along a third direction, so The third direction intersects both the first direction and the second direction; the 90-degree included angle of the L-shaped structure faces the driving active layer.
  • the display substrate further includes data fan-out lines arranged on the substrate, the data fan-out lines are coupled to corresponding data lines, and the data fan-out lines are on the same layer as the second conductive connection portion. Material settings.
  • the display substrate further includes a pixel defining layer, the pixel defining layer defines a plurality of pixel openings, and the plurality of pixel openings correspond to the plurality of sub-pixels included in the display substrate;
  • the orthographic projection of the first active layer on the substrate is located inside the orthographic projection of the corresponding pixel opening on the substrate;
  • the orthographic projection of the second active layer on the substrate is located inside the orthographic projection of the corresponding pixel opening on the substrate;
  • the orthographic projection of the third active layer on the substrate is inside the orthographic projection of the pixel defining layer on the substrate;
  • an orthographic projection of the luminescence-controlling active layer on the substrate is located inside an orthographic projection of the pixel defining layer on the substrate;
  • the orthographic projection of the driving active layer on the substrate partially overlaps the orthographic projection of the pixel defining layer on the substrate and the corresponding orthographic projection of the pixel opening on the substrate.
  • a second aspect of the present disclosure provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a circuit diagram corresponding to the smallest repeating unit in a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a driving timing diagram of a sub-pixel driving circuit in a group of sub-pixels provided by an embodiment of the present disclosure
  • Fig. 3 is a schematic layout diagram corresponding to the circuit diagram in Fig. 1;
  • FIG. 4 is a schematic diagram of a gate drive circuit layout area and a gate drive wiring layout area provided by an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of the active layer in Figure 3.
  • FIG. 6 is a schematic layout diagram of the first gate metal layer in FIG. 3;
  • FIG. 7 is a schematic layout diagram of a second gate metal layer in FIG. 3;
  • FIG. 8 is a schematic layout diagram of the first source-drain metal layer in FIG. 3;
  • FIG. 9 is a schematic layout diagram of a second source-drain metal layer in FIG. 3;
  • Fig. 10 is a schematic layout diagram of the anode layer in Fig. 3;
  • FIG. 11 is a schematic layout diagram of openings formed by the pixel defining layer in FIG. 3;
  • FIG. 12 is a schematic layout diagram of the active layer and the first gate metal layer in FIG. 3;
  • FIG. 13 is a schematic layout diagram of the active layer, the first gate metal layer and the second gate metal layer in FIG. 3;
  • FIG. 14 is a schematic layout diagram of adding a first source-drain metal layer on the basis of FIG. 13;
  • FIG. 15 is a schematic layout diagram of adding a second source and drain metal layer on the basis of FIG. 14;
  • Fig. 16 is a schematic layout diagram of adding an anode layer on the basis of Fig. 15;
  • 17 is a schematic layout diagram of the active layer, the second gate metal layer, and the first source-drain metal layer in FIG. 3;
  • FIG. 18 is a schematic layout diagram of the second gate metal layer and the first source-drain metal layer in FIG. 3;
  • FIG. 19 is a schematic layout diagram of the first source-drain metal layer and the second source-drain metal layer in FIG. 3;
  • FIG. 20 is a schematic layout diagram of a second source-drain metal layer and an anode layer in FIG. 3;
  • FIG. 21 is a schematic cross-sectional view of a first via hole and a second via hole provided by an embodiment of the present disclosure.
  • the gate drive circuit in the OLED display product in the display area that is, to use GIA (Gate Driver In AA) technology, but this gate drive circuit will Occupies part of the space in the display area and affects the resolution of the display product.
  • GIA Gate Driver In AA
  • an embodiment of the present disclosure provides a display substrate, including: a base and a plurality of sub-pixels 20 arranged on the base, and the plurality of sub-pixels 20 are arranged in an array ;
  • the sub-pixel includes a sub-pixel driving circuit 201 and a light-emitting element EL
  • the sub-pixel driving circuit 201 includes a coupled driving sub-circuit and a light-emitting control sub-circuit
  • the light-emitting element EL includes an anode pattern 80;
  • the multiple sub-pixels are divided into multiple groups of sub-pixels, each group of sub-pixels A includes two sub-pixels arranged along the first direction, and the two sub-pixel driving circuits 201 included in the two sub-pixels multiplex the same light emission control sub-pixel A circuit, the light emission control sub-circuit is used to respectively control the driving sub-circuit in the two sub-pixels to write a driving signal to the anode pattern 80;
  • the sub-pixel also includes a data line including a portion extending in the first direction.
  • the display substrate includes a display area and a peripheral area surrounding the display area.
  • the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels are distributed in the display area in an array.
  • the sub-pixel includes a sub-pixel driving circuit 201 and a light emitting element
  • the sub-pixel driving circuit 201 is coupled to the light emitting element, and is used to provide a driving signal for the light emitting element, so as to drive the light emitting element to emit light
  • the sub-pixel driving circuit 201 includes a 5T1C circuit structure, that is, includes 5 thin film transistors and a storage capacitor Cst.
  • the light-emitting element includes an anode pattern 80, a light-emitting functional layer and a cathode layer that are sequentially stacked along a direction away from the substrate; the light-emitting functional layer includes a stacked electron injection layer, an electron transport layer, and an organic light emitting layer. Material layer, hole transport layer and hole injection layer.
  • the cathode layer receives a negative power supply signal VSS.
  • the electron injection layer included in each sub-pixel is formed into an integrated structure, capable of covering the entire display area; similarly, the electron transport layer included in each sub-pixel, the hole Both the transport layer and the hole injection layer can also be formed as an integral structure, which can cover the entire display area.
  • the cathode layer included in each sub-pixel is formed as an integral structure, which can cover the entire display area.
  • the multiple sub-pixels are divided into multiple groups of sub-pixels, the multiple groups of sub-pixels are distributed in an array, and each sub-pixel can only belong to one group of sub-pixels.
  • each group of sub-pixels includes two sub-pixels arranged along a first direction, and the first direction includes a vertical direction.
  • the two sub-pixels arranged along the first direction include: the layout areas of the two sub-pixel driving circuits 201 included in the two sub-pixels are arranged along the first direction; and/or, the two sub-pixels included The anode patterns 80 in the two light emitting elements are arranged along the first direction.
  • each subpixel driving circuit 201 includes a driving subcircuit and a light emission control subcircuit, the light emission control subcircuit is coupled to the driving subcircuit, and the light emission control subcircuit is used to control the driving subcircuit Write a driving signal to the anode pattern 80, so as to realize the control of the light emitting condition of the light emitting element.
  • each group of sub-pixels includes two sub-pixels arranged along the first direction, and the two sub-pixel driving circuits 201 included in the two sub-pixels multiplex the same light-emitting control sub-circuit, that is, the multiplexed light-emitting
  • the control sub-circuits are respectively coupled to the two driving sub-circuits in the two sub-pixel driving circuits 201, and the multiplexed light emission control sub-circuits respectively control the two driving sub-circuits to the corresponding anode pattern 80 Write drive signal.
  • the display substrate provided by the embodiment of the present disclosure by dividing the plurality of sub-pixels into multiple groups of sub-pixels, and setting the two sub-pixel driving circuits 201 included in each group of sub-pixels to multiplex the same
  • One light emission control sub-circuit reduces the number of light emission control sub-circuits and effectively reduces the layout space occupied by each group of sub-pixels. Therefore, the display substrate provided by the embodiment of the present disclosure optimizes the layout of multiple sub-pixels. It not only ensures that the display substrate can realize high-resolution display, but also is better compatible with GOA (English: Gate On Array) logic resources, and provides technical support for special-shaped display products to realize high-resolution GIA display.
  • GOA Gate On Array
  • the sub-pixels further include:
  • the light emission control signal line 44 includes a portion extending along a second direction intersecting the first direction;
  • the two subpixel drive circuits 201 included in the two subpixels multiplex the same light emission control signal line 44, and the light emission control signal line 44 is coupled to the light emission control subcircuit for controlling the light emission control subcircuit.
  • Circuit; the orthographic projection of the light emission control signal line 44 on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate.
  • the first direction includes a vertical direction
  • the second direction includes a horizontal direction
  • the two sub-pixel drive circuits 201 included in the two sub-pixels multiplex the same light emission control signal line 44, and the light emission control signal line 44 is respectively connected to the light emission control sub-circuit and the corresponding gate driver.
  • the light emission control signal line 44 is used to transmit the light emission control signal EM provided by the gate drive circuit to the light emission control subcircuit
  • the light emission control subcircuit is used to transmit the light emission control signal EM in the light emission control signal EM Under control, respectively control the two driving sub-circuits coupled thereto to write a driving signal to the corresponding anode pattern 80 .
  • the two sub-pixel driving circuits 201 included in the above setting of the two sub-pixels multiplex the same light emission control signal line 44, which reduces the number of light emission control signal lines 44 and effectively reduces the layout space occupied by each group of sub-pixels .
  • the orthographic projection of the luminescence control signal line 44 on the substrate By setting the orthographic projection of the luminescence control signal line 44 on the substrate to be located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate, so that the luminescence control signal
  • the line 44 is roughly located between the two sub-pixels, so that the light emission control subcircuit is arranged near the light emission control signal line 44, which not only ensures that the light emission control subcircuit and the light emission control signal
  • the good connection performance of the line 44 and the two driving sub-circuits also effectively reduces the layout difficulty of the light-emitting control signal line 44 and the light-emitting control sub-circuit.
  • the light emission control subcircuit includes a light emission control transistor T4, and the gate of the light emission control transistor T4 is connected to the light emission control transistor T4.
  • the light emission control signal line 44 is coupled, and the second pole of the light emission control transistor T4 is coupled to the driving sub-circuit;
  • the light emission control transistor T4 includes a light emission control active layer 34, the light emission control active layer 34 includes a portion extending along the second direction, the orthographic projection of the light emission control active layer 34 on the substrate, It is located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate.
  • the light emission control transistor T4 when the light emission control signal EM provided by the light emission control signal line 44 is at an active level, the light emission control transistor T4 is turned on; when the light emission control signal EM provided by the light emission control signal line 44 is at an inactive level, Normally, the light emission control transistor T4 is turned off.
  • the gate of the light emission control transistor T4 and the light emission control signal line 44 coupled thereto form an integral structure.
  • the second pole of the light emission control transistor T4 is coupled to the driving sub-circuit through the first conductive pattern 64 .
  • the second electrode of the light emission control transistor T4 is connected to two electrodes of the group of sub-pixels through the first conductive pattern 64 respectively.
  • the driving subcircuit is coupled.
  • the first conductive pattern 64 includes a portion extending along the first direction.
  • the first conductive pattern 64 and the data lines in the display substrate are arranged in the same layer and the same material.
  • the orthographic projection of the first conductive pattern 64 on the substrate partially overlaps the orthographic projection of the light emission control signal line 44 on the substrate.
  • the light emission control active layer 34 includes a portion extending along the second direction.
  • the width of the two ends of the light emission control active layer 34 in the first direction is larger than the width of the middle part of the light emission control active layer 34 between the two ends in the first direction.
  • the orthographic projection of the middle part of the luminescence control active layer 34 on the substrate at least partially overlaps the orthographic projection of the gate of the luminescence control transistor T4 on the substrate, and the luminescence control The middle part of the active layer 34 is used to form the channel region of the light emission control transistor T4.
  • the above setting of the orthographic projection of the luminescence control active layer 34 on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate, so that the luminescence control
  • the transistor T4 is entirely located between two sub-pixels in a group of sub-pixels, which not only ensures the good connection performance of the light-emitting control transistor T4, the light-emitting control signal line 44, and the two driving sub-circuits, but also effectively The layout difficulty of the light emission control signal line 44 and the light emission control transistor T4 is reduced.
  • the sub-pixels further include:
  • a power supply line VDD, the power supply line VDD includes a portion extending along the first direction, and the power supply lines VDD included in the two sub-pixels are coupled;
  • the first pole of the light emission control transistor T4 is coupled to the power line VDD, and the light emission control transistor T4 is used to turn on or off the power line VDD and the power line VDD under the control of the light emission control signal line 44.
  • the power lines VDD included in the two sub-pixels are coupled to form an integrated structure.
  • the power lines VDD in all the sub-pixels located in the same column along the first direction are sequentially coupled to form an integrated structure.
  • the power supply line VDD includes a positive power supply line for providing a positive power supply signal Vd.
  • the light emission control transistor T4 is turned on or off under the control of the light emission control signal EM provided by the light emission control signal line 44 to control whether to transmit the power signal Vd provided by the power line VDD to the driving sub-circuit.
  • the sub-pixels further include:
  • the power connection part 45 includes a part extending along the second direction; the two subpixel driving circuits 201 included in the two subpixels multiplex the same power connection part 45; along the second In two directions, the orthographic projection of the power supply line VDD on the substrate is located on one side of the orthographic projection of the luminescence control active layer 34 on the substrate, and the first electrode of the luminescence control transistor T4 passes through the power supply
  • the connection part 45 is coupled to the power line VDD.
  • the power connection part 45 is arranged in a different layer from the light emission control active layer 34, the power connection part 45 is arranged in a different layer from the power line VDD, and the power connection part 45 passes through the second conductive pattern 65 is coupled to the first pole of the light emitting control transistor T4, and the power supply connection part 45 is coupled to the power supply line VDD through a via hole, and the via hole is located between the power supply connection part 45 and the power supply line. Insulation layer between VDD.
  • the power connection portion 45 and the light emission control signal line 44 are arranged along the first direction.
  • Setting the first pole of the light emission control transistor T4 to be coupled to the power supply line VDD through the power supply connection part 45 not only ensures the connection performance between the light emission control transistor T4 and the power supply line VDD, but also avoids This prevents the light emission control transistor T4 from being short-circuited with other conductive structures in order to be connected to the power supply line VDD, and effectively reduces the layout difficulty of the light emission control transistor T4.
  • the power connection part 45 and the lighting control signal line 44 are provided in the same layer and the same material.
  • the above arrangement enables the power connection portion 45 and the light emission control signal line 44 to be formed in the same patterning process, which effectively simplifies the manufacturing process of the display substrate and reduces the manufacturing cost of the display substrate.
  • the plurality of sub-pixels are divided into a plurality of pixel units B, and the pixel unit B includes at least two sub-pixels arranged along the second direction
  • the at least two sub-pixels are multiplexed with the same power line VDD, and the power connection parts 45 included in the at least two sub-pixels are sequentially coupled.
  • the plurality of sub-pixels are divided into a plurality of pixel units B, and the plurality of pixel units B are distributed in an array.
  • the pixel unit B includes at least two sub-pixels arranged along the second direction; the at least two sub-pixels multiplex the same power line VDD, and along the second direction, the power line VDD is located at one side of the at least two sub-pixels.
  • the power supply connection parts 45 included in the at least two sub-pixels are sequentially coupled to form an integrated structure.
  • the power connection parts 45 in each pixel unit B are sequentially coupled to form an integrated structure.
  • the at least two sub-pixels are multiplexed with the same power supply line VDD, and the power supply connection parts 45 included in the at least two sub-pixels are sequentially coupled, which not only realizes that each sub-pixel can be connected to the multiplexed power supply through the power supply connection part 45
  • the line VDD coupling also effectively saves the layout space occupied by each sub-pixel, which is beneficial to improving the resolution of the display substrate.
  • the power supply connection parts 45 in each pixel unit B are sequentially coupled, so that the power supply line VDD in the display substrate and the power supply connection part 45 A network structure can be formed, which is beneficial to the overall uniformity of the power signal Vd.
  • the driving sub-circuit includes a driving transistor T5, and the first pole of the driving transistor T5 is connected to the light emission control transistor T4 The second pole of the driving transistor T5 is coupled to the anode pattern 80 of the light emitting element;
  • the driving transistor T5 includes a driving active layer 35; in the two sub-pixel driving circuits 201, the driving active layers 35 included in the two driving transistors T5 are arranged axisymmetrically, and the symmetry axis C is along the second direction Extending, the orthographic projection of the symmetry axis C on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two sub-pixels on the substrate.
  • the first pole of the driving transistor T5 is coupled to the second pole of the light emission control transistor T4 through the first conductive pattern 64, and the second pole of the driving transistor T5 is coupled to the first pole of the storage capacitor Cst.
  • the second electrode plate Cst2 is coupled, and is coupled with the anode pattern 80 through the second electrode plate Cst2.
  • the second pole of the driving transistor T5 is arranged in a different layer from the second plate Cst2 of the storage capacitor Cst, and the second pole of the driving transistor T5 is connected to the second pole through the third conductive pattern 66 Board Cst2 is coupled.
  • the driving active layer 35 includes a U-shaped portion, and two end portions respectively extending from the two ends of the U-shaped portion.
  • the U-shaped portion is used to form a channel region of the driving transistor T5, and the two ends serve as the first pole and the second pole of the driving transistor T5.
  • gates included in the two driving transistors T5 are arranged symmetrically with respect to the symmetry axis C.
  • the two driving active layers 35 included in two adjacent sub-pixels along the second direction are symmetrical about the longitudinal axis, and the longitudinal axis is located between the two driving active layers 35,
  • the longitudinal axis extends along the first direction; the gates of the two driving transistors T5 included in two adjacent sub-pixels along the second direction are symmetrical with respect to the longitudinal axis.
  • the above-mentioned symmetrical arrangement method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • the orthographic projection of the symmetry axis C on the substrate overlaps with the orthographic projection of the light emission control active layer 34 on the substrate.
  • the above arrangement makes the light emission control transistor T4 located at the center of a group of sub-pixels along the first direction, which not only ensures that the light emission control transistor T4 and the light emission control signal line 44, but also the two driving sub-circuits
  • the good connection performance effectively reduces the layout difficulty of the light emission control signal line 44 and the light emission control transistor T4, and is also conducive to reducing the layout space occupied by sub-pixels, which is beneficial to the display substrate to achieve high display resolution.
  • the sub-pixel further includes a data line 62 and a first scan line 41, and the data line 62 includes A portion extending in one direction, the first scanning line 41 includes a portion extending in the second direction;
  • the sub-pixel driving circuit 201 further includes a first transistor T1, the gate of the first transistor T1 is coupled to the first scanning line 41 , the first electrode of the first transistor T1 is connected to the data line 62 coupling, the second pole of the first transistor T1 is coupled to the gate of the driving transistor T5;
  • the first transistor T1 includes a first active layer 31, and the first active layer 31 includes a portion extending along the second direction; in the same sub-pixel, the first active layer 31, the The driving active layer 35 and the light emission control active layer 34 are sequentially arranged along the first direction.
  • the data lines included in the sub-pixels located in the same column along the first direction are sequentially coupled to form an integrated structure.
  • the first scanning lines 41 included in the sub-pixels located in the same row along the second direction are sequentially coupled to form an integrated structure.
  • the data line receives a data signal provided by a driving chip in the display substrate.
  • the first scanning line 41 is coupled to a corresponding gate driving circuit, and receives a first scanning signal provided by the corresponding gate driving circuit.
  • the first transistor T1 is turned on or off under the control of the first scanning signal transmitted by the first scanning line 41, so as to realize the connection between the data line and the gate of the driving transistor T5. Make a connection or disconnect it.
  • the first active layer 31 includes a portion extending along the second direction.
  • the width of the two ends of the first active layer 31 in the first direction is larger than the width of the middle part of the first active layer 31 between the two ends in the first direction.
  • the orthographic projection of the middle part of the first active layer 31 on the substrate at least partially overlaps the orthographic projection of the gate of the first transistor T1 on the substrate, and the first The middle part of the active layer 31 is used to form the channel region of the first transistor T1.
  • the first active layer 31 is disposed in a different layer from the data line, and the first active layer 31 is disposed in a different layer from the gate of the driving transistor T5.
  • the first pole of the first transistor T1 is coupled to the data line through a via hole, and the via hole penetrates the insulating layer between the first pole of the first transistor T1 and the data line.
  • the second pole of a transistor T1 is respectively coupled to the gate of the driving transistor T5 and the second pole of the second transistor T2 through the sixth conductive connection portion.
  • the first active layer 31, the driving active layer 35 and the light emission control active layer 34 are arranged from top to bottom along the first direction.
  • the first active layer 31, the driving active layer 35 and the light emission control active layer 34 are arranged from bottom to top along the first direction Arranged in order.
  • the above layout method enables the first transistor T1, the driving transistor T5 and the light emission control transistor T4 to be arranged sequentially along the second direction, which not only helps to reduce the layout difficulty of the sub-pixels , it is also beneficial to reduce the layout space occupied by the sub-pixels, and it is beneficial for the display substrate to achieve high display resolution.
  • the first active layer 31 comprised by the two first transistors T1 is symmetrical about the Axis C is arranged symmetrically.
  • the above arrangement method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • the plurality of sub-pixels are divided into a plurality of pixel units B, at least some of the pixel units B include first sub-pixels 202 arranged along the second direction, The second sub-pixel 203 and the third sub-pixel 204, the first sub-pixel 202 includes a first data line 621, the second sub-pixel 203 includes a second data line 622, and the third sub-pixel 204 includes a third data line 623;
  • the first data line 621 is located on the side of the first sub-pixel 202 away from the second sub-pixel 203 along the second direction, and the second data line 622 and the The third data lines 623 are located between the second sub-pixel 203 and the third sub-pixel 204; there is a first interval between the first sub-pixel 202 and the second sub-pixel 203;
  • the first data line 621 and the second data line 622 are located between the first sub-pixel 202 and the second sub-pixel 203, and the third data line 623 is located on the side of the third sub-pixel 204 away from the second sub-pixel 203 along the second direction; there is a second interval between the second sub-pixel 203 and the third sub-pixel 204 .
  • the pixel unit B includes a first sub-pixel 202, a second sub-pixel 203, and a third sub-pixel 204 arranged along the second direction, and the four pixel units B constitute the display substrate. smallest repeating unit.
  • FIG. 3 schematically illustrates the minimum repeating unit in the display substrate.
  • the colors of the first sub-pixel 202 , the second sub-pixel 203 and the third sub-pixel 204 are different.
  • the first sub-pixel 202 includes a red sub-pixel
  • the second sub-pixel 203 includes a green sub-pixel
  • the third sub-pixel 204 includes a blue sub-pixel.
  • FIG. 1 shows red data signals DATAR1 and DATAR2 received by the red sub-pixel, green data signals DATAG1 and DATAG2 received by the green sub-pixel, and blue data signals DATAB1 and DATAB2 received by the blue sub-pixel.
  • the first sub-pixel 202 includes a first sub-pixel driving circuit
  • the second sub-pixel 203 includes a second sub-pixel driving circuit
  • the third sub-pixel 204 includes a third sub-pixel driving circuit.
  • the orthographic projection of the first data line 621 on the substrate is located along the second The direction is away from the side of the orthographic projection of the second subpixel driving circuit on the substrate, the orthographic projection of the second data line 622 on the substrate and the third data line 623 on the substrate.
  • the orthographic projections of are located between the orthographic projection of the second sub-pixel driving circuit on the substrate and the orthographic projection of the third sub-pixel driving circuit on the substrate.
  • the orthographic projection of the first data line 621 on the substrate and the orthographic projection of the second data line 622 on the substrate are both located at the first Between the orthographic projection of a sub-pixel driving circuit on the substrate and the orthographic projection of the second sub-pixel driving circuit on the substrate, the orthographic projection of the third data line 623 on the substrate is located at The orthographic projection of the third sub-pixel driving circuit on the substrate is away from a side of the orthographic projection of the second sub-pixel driving circuit on the substrate along the second direction.
  • the orthographic projection of the first spacer on the substrate is located at the same location as the orthographic projection of the first subpixel driving circuit on the substrate and the second subpixel driving circuit on the substrate between the orthographic projections of .
  • the orthographic projection of the first spacer on the substrate is located between the orthographic projection of the anode pattern 80 included in the first sub-pixel 202 on the substrate and the orthographic projection of the anode pattern 80 included in the second sub-pixel 203.
  • the anode pattern 80 is between the orthographic projections on the substrate.
  • the orthographic projection of the second spacer on the substrate is located at the same level as the orthographic projection of the second subpixel driving circuit on the substrate and the third subpixel driving circuit on the substrate. between the orthographic projections of .
  • the orthographic projection of the second spacer on the substrate is located between the orthographic projection of the anode pattern 80 included in the second sub-pixel 203 on the substrate and the orthographic projection of the anode pattern 80 included in the third sub-pixel 204.
  • the anode pattern 80 is between the orthographic projections on the substrate.
  • the above layout method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • the multiple groups of sub-pixels are divided into multiple rows of sub-pixel groups arranged along the first direction, and each row of sub-pixel groups includes Multiple groups of sub-pixels arranged in two directions;
  • the display substrate also includes a plurality of gate drive circuit layout areas 90 and a plurality of gate drive wiring layout areas 91;
  • each gate drive circuit layout area 90 corresponds to the multiple rows of sub-pixel groups, each gate drive circuit layout area 90 includes a first layout area 901 and a second layout area 902, along the first direction, the first layout area 901 is located on the first side of the corresponding row of sub-pixel groups, and the second layout area 902 is located on the second side of the corresponding row of sub-pixel groups;
  • the plurality of gate driving circuit layout areas 90 correspond one-to-one to the plurality of gate driving wiring layout areas 91, and the gate driving wiring layout area 91 includes at least two gate driving wiring layout areas arranged along the second direction. the third layout area 910;
  • At least one of the third layout areas 910 is located in the first interval area in a corresponding row of sub-pixel groups; at least one of the third layout areas 910 is located in a corresponding row The second spacer in the sub-pixel group.
  • the gate driving circuit layout area 90 is used to layout the gate driving circuit
  • the gate driving wiring layout area 91 is used to layout the gate driving wiring
  • the gate driving wiring and the corresponding The gate drive circuit is coupled to provide corresponding signals for the gate drive circuit, or to transmit the signal provided by the gate drive circuit to the sub-pixels.
  • both the first layout area 901 and the second layout area 902 extend along the second direction
  • the third layout area 910 extends along the first direction
  • the first layout area 901 is located on the first side of the corresponding row of sub-pixel groups
  • the second layout area 902 is located on the second side of the corresponding row of sub-pixel groups, so The first side and the second side are opposite along the first direction.
  • the plurality of gate driving circuit layout areas 90 correspond one-to-one to the plurality of gate driving wiring layout areas 91, and the gate driving wiring layout areas 91 include There are at least two third layout regions 910, and the at least two third layout regions 910 are located between the corresponding first layout region 901 and the second layout region 902.
  • the above setting method enables the layout of the gate driving circuit and the gate driving wiring in the display area, optimizes the layout of the gate driving circuit and the gate driving wiring, and is well compatible GOA logic resources have been provided, and technical support has been provided for special-shaped display products to realize high-resolution GIA display.
  • the sub-pixel further includes a reference signal line 63 and a second scanning line 42, and the reference signal line 63 includes The portion extending in the first direction, the second scanning line 42 includes a portion extending in the second direction;
  • the sub-pixel driving circuit 201 further includes a second transistor T2, the gate of the second transistor T2 is coupled to the second scanning line 42, the first electrode of the second transistor T2 is connected to the reference signal line 63, the second pole of the second transistor T2 is coupled to the gate of the drive transistor T5;
  • the second transistor T2 includes a second active layer 32, and the second active layer 32 includes a portion extending along the second direction; in the same sub-pixel, the second active layer 32, the The first active layer 31 and the light emission control active layer 34 are sequentially arranged along the first direction.
  • the reference signal lines 63 included in the sub-pixels located in the same column along the first direction are sequentially coupled to form an integrated structure.
  • the second scanning lines 42 included in the sub-pixels located in the same row along the second direction are sequentially coupled to form an integrated structure.
  • the reference signal line 63 is used to provide a reference signal Vref.
  • the second scanning line 42 is coupled to a corresponding gate driving circuit, and receives a second scanning signal provided by the corresponding gate driving circuit.
  • the second transistor T2 is turned on or off under the control of the second scanning signal transmitted by the second scanning line 42, so as to realize the connection between the reference signal line 63 and the gate of the driving transistor T5. connected or disconnected.
  • the second active layer 32 includes a portion extending along the second direction.
  • the width of the two ends of the second active layer 32 in the first direction is larger than the width of the middle part of the second active layer 32 between the two ends in the first direction.
  • the orthographic projection of the middle part of the second active layer 32 on the substrate at least partially overlaps the orthographic projection of the gate of the second transistor T2 on the substrate, and the second The middle part of the active layer 32 is used to form the channel region of the second transistor T2.
  • the second active layer 32, the first active layer 31 and the light emission control active layer 34 start from above along the first direction arranged in sequence downward; in another sub-pixel of the same group of sub-pixels, the second active layer 32, the first active layer 31 and the light emission control active layer 34 are automatically Arranged in order from bottom to top.
  • the above layout method enables the second transistor T2, the first transistor T1 and the light emission control transistor T4 to be arranged sequentially along the second direction, which not only helps to reduce the layout difficulty of the sub-pixel, but also helps to reduce the size of the sub-pixel.
  • the layout space occupied by the sub-pixels is beneficial for the display substrate to achieve high display resolution.
  • the second active layers 32 included in the two second transistors T2 are symmetrical about the symmetry axis C set up.
  • the above arrangement method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • the sub-pixel further includes a reference connection portion 36, and the reference connection portion 36 includes a portion extending along the second direction; the second The first pole of the transistor T2 is coupled to the reference signal line 63 through the reference connection portion 36 .
  • the reference connection part 36 and the second active layer 32 are provided in the same layer and the same material, the reference connection part 36 is provided in a different layer from the reference signal line 63, and the reference connection part 36 passes through the second active layer 32.
  • the four conductive patterns 67 are coupled to the first pole of the second transistor T2, the reference connection part 36 is coupled to the reference signal line 63 through a via hole, and the via hole is located between the reference connection part 36 and the reference signal line 63.
  • An insulating layer between the reference signal lines 63 is provided in the same layer and the same material, the reference connection part 36 is provided in a different layer from the reference signal line 63, and the reference connection part 36 passes through the second active layer 32.
  • the four conductive patterns 67 are coupled to the first pole of the second transistor T2
  • the reference connection part 36 is coupled to the reference signal line 63 through a via hole, and the via hole is located between the reference connection part 36 and the reference signal line 63.
  • An insulating layer between the reference signal lines 63 are
  • the two reference connection portions 36 included in two sub-pixels are symmetrical about the axis C of symmetry.
  • the above arrangement of the first pole of the second transistor T2 coupled to the reference signal line 63 through the reference connection portion 36 not only ensures the connection performance between the second transistor T2 and the reference signal line 63 , avoiding the short circuit between the second transistor T2 and other conductive structures in order to realize the connection with the reference signal line 63, and effectively reducing the layout difficulty of the second transistor T2.
  • the plurality of sub-pixels are divided into a plurality of pixel units B, and the pixel unit B includes at least two pixels arranged along the second direction sub-pixels; each sub-pixel included in two adjacent pixel units B arranged along the second direction multiplexes a reference signal line 63, and the reference signal line 63 is located in the two adjacent pixel units Between B, the reference connection portions 36 included in the sub-pixels are sequentially coupled.
  • the orthographic projection of the reference signal line 63 on the substrate overlaps the orthographic projection of an anode pattern 80 included in an adjacent pixel unit B on the substrate, and overlaps with the orthographic projection of an anode pattern 80 included in an adjacent pixel unit B.
  • the orthographic projections of any anode pattern 80 included in the pixel unit B on the substrate do not overlap.
  • the reference connection parts 36 included in each sub-pixel are coupled in sequence to form an integrated structure.
  • the power connection parts 45 in each pixel unit B are sequentially coupled to form an integrated structure.
  • each sub-pixel included in two adjacent pixel units B arranged along the second direction multiplexes a reference signal line 63, and the reference connection portion 36 included in each sub-pixel is sequentially coupled, which not only realizes Each sub-pixel can be coupled to the multiplexed reference signal line 63 through the reference connection portion 36 , which effectively saves the layout space occupied by each sub-pixel and is beneficial to improve the resolution of the display substrate.
  • the reference connection parts 36 in each pixel unit B are sequentially coupled, so that the reference signal line 63 in the display substrate and the reference connection part 36 can form a mesh structure, which is beneficial to the overall uniformity of the reference signal Vref.
  • the orthographic projection of the reference connection portion 36 on the substrate, the orthographic projection of the second scan line 42 on the substrate, Orthographic projections of the first scanning lines 41 on the substrate, and orthographic projections of the light emission control signal lines 44 on the substrate are arranged in sequence along the first direction.
  • the above setting method not only effectively reduces the layout space occupied by the sub-pixels, but also helps the display substrate to achieve a high display resolution, and is also beneficial to reduce the layout difficulty of the sub-pixels.
  • the sub-pixels further include an initialization signal line 51 and a third scan line 43, and the initialization Both the signal line 51 and the third scanning line 43 include a portion extending along the second direction;
  • the sub-pixel driving circuit 201 further includes a third transistor T3, the gate of the third transistor T3 is coupled to the third scanning line 43, the first electrode of the third transistor T3 is connected to the initialization signal line 51, the second pole of the third transistor T3 is coupled to the anode pattern 80 of the light emitting element;
  • the third transistor T3 includes a third active layer 33; in the same sub-pixel, the first active layer 31, the third active layer 33 and the light emission control active layer 34 are arranged along the Arranged sequentially in one direction.
  • the initialization signal line 51 includes a portion extending along the second direction, and the initialization signal lines 51 included in the sub-pixels located in the same row along the second direction are sequentially coupled to form an integrated structure.
  • the initialization signal line 51 is used to provide an initialization signal Vinit.
  • the third scanning line 43 includes a portion extending along the second direction, and the third scanning lines 43 included in the sub-pixels located in the same row along the second direction are sequentially coupled to form an integral body structure.
  • the third scanning line 43 is coupled to a corresponding gate driving circuit, and receives a third scanning signal provided by the corresponding gate driving circuit.
  • the third transistor T3 is turned on or off under the control of the third scanning signal transmitted by the third scanning line 43, so as to realize the connection between the initialization signal line 51 and the third transistor T3. Conductive connection or disconnection between one pole.
  • the third active layer 33 is arranged in a different layer from the initialization signal line 51 , and the third active layer 33 is arranged in a different layer from the third scanning line 43 .
  • the first electrode of the third transistor T3 is coupled to the initialization signal line 51 through the fifth conductive pattern 68, and the second electrode of the third transistor T3 is connected to the second electrode of the storage capacitor Cst through the first conductive connection part 60.
  • the plate Cst2 is coupled.
  • the above arrangement is in the same sub-pixel, the first active layer 31, the third active layer 33 and the light emission control active layer 34 are arranged in sequence along the first direction, effectively reducing the layout occupied by sub-pixels space, it is beneficial for the display substrate to achieve high display resolution, and it is also beneficial to reduce the layout difficulty of the sub-pixels.
  • the third active layer 33 included in the two third transistors T3 is symmetrical about the symmetry axis C set up.
  • the above arrangement method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • At least one of the first transistor T1 , the second transistor T2 and the third transistor T3 includes a double-gate structure.
  • the first transistor T1, the second transistor T2, the third transistor T3, the light emission control transistor T4 and the driving transistor T5 are all N-type low temperature polysilicon transistors.
  • the above arrangement of the first transistor T1, the second transistor T2 and the third transistor T3 includes a double-gate structure, which is beneficial to reduce the leakage current of the transistors and ensure the correctness of the function and the stability of the operation of the sub-pixel driving circuit 201 .
  • the sub-pixel driving circuit 201 further includes a storage capacitor Cst, and the storage capacitor Cst includes a relatively arranged first A pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 is located between the base and the second pole plate Cst2; the first pole plate Cst1 is coupled to the gate of the drive transistor T5 connected, the second electrode plate Cst2 is respectively coupled to the second electrode of the driving transistor T5 and the anode pattern 80 of the light emitting element; in the two sub-pixel driving circuits 201, the two first electrode plates Cst1 is arranged symmetrically with respect to the axis of symmetry C; and/or, the two second plates Cst2 are arranged symmetrically with respect to the axis of symmetry C.
  • the first plate Cst1 is multiplexed as the gate of the driving transistor T5.
  • the second plate Cst2 is coupled to the second pole of the driving transistor T5 through the third conductive pattern 66 .
  • the orthographic projection of the second polar plate Cst2 on the substrate at least partially overlaps with the orthographic projection of the driving active layer 35 on the substrate.
  • the orthographic projection of the second polar plate Cst2 on the substrate is located on the orthographic projection of the first active layer 31 on the substrate and the third active layer 33 is on the substrate. between the orthographic projections on .
  • the orthographic projection of the first polar plate Cst1 on the substrate is located at the orthographic projection of the first active layer 31 on the substrate and the third active layer 33 on the substrate between the orthographic projections on .
  • the two first pole plates Cst1 are arranged symmetrically about the symmetry axis C; and/or, the two second pole plates Cst2 are symmetrical about the symmetry axis C
  • the arrangement can effectively reduce the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • the sub-pixel further includes a first conductive connection part 60 and a second conductive connection part arranged in different layers.
  • the connection part 70, the first conductive connection part 60 is located between the base and the second conductive connection part 70, and the anode pattern 80 is located on the side of the second conductive connection part 70 facing away from the base ;
  • the second pole plate Cst2 is coupled to the first conductive connection part 60;
  • the second conductive connection part 70 is coupled to the first conductive connection part 60 through a first via hole Via1, and the orthographic projection of the first via hole Via1 on the substrate 10 is located in the first overlapping region
  • the second conductive connection part 70 is coupled to the anode pattern 80 through the second via hole Via2, and the orthographic projection of the second via hole Via2 on the substrate 10 is located in the second overlapping area.
  • the first conductive connection part 60 is respectively coupled to the second plate Cst2 , the second pole of the third transistor T3 and the second conductive connection part 70 .
  • the first via hole Via1 penetrates through the insulating layer located between the first conductive connection part 60 and the second conductive connection part 70
  • the second via hole Via2 penetrates through the insulating layer located between the second conductive connection part 60 and the second conductive connection part 70.
  • the second plate Cst2 is coupled to the anode pattern 80 through the first conductive connection part 60 and the second conductive connection part 70, so that the first via hole Via1 and the second via hole
  • the depths of the holes Via2 are relatively shallow, and the first via hole Via1 and the second via hole Via2 can be staggered to form a stepped hole with a gentle slope, avoiding the gap between the second plate Cst2 and the anode pattern 80 A deeper via hole is formed between them, which effectively reduces the risk of the anode pattern 80 breaking at the second via hole Via2.
  • At least part of the orthographic projection of the first conductive connection part 60 on the substrate is set, located on the third active pattern on the substrate. Between the orthographic projection and the orthographic projection of the driving active layer 35 on the substrate.
  • the above setting method effectively reduces the layout space occupied by the sub-pixels, which is beneficial to reducing the difficulty of sub-pixel layout and improving the resolution of the display substrate.
  • the third active layer 33 includes a coupled first portion 331 and a second portion 332, the first portion 331 includes a portion extending along the first direction, The second portion 332 includes a portion extending along the second direction, the first portion 331 and the second portion 332 are formed into an L-shaped structure; in the same sub-pixel, the third active Layer 33 and the driving active layer 35 are arranged along a third direction, and the third direction intersects both the first direction and the second direction; the 90-degree included angle of the L-shaped structure faces the driving active layer 35 .
  • the orthographic projection of the first part 331 on the substrate and the orthographic projection of the second part 332 on the substrate are respectively related to the gate of the third transistor T3 on the substrate.
  • the orthographic projections are partially overlapped, so that the third transistor T3 is formed into a double-gate structure.
  • the first direction is perpendicular to the second direction, and the angle between the third direction and the first direction is between 30 degrees and 45 degrees, which may include endpoint values.
  • the above setting method effectively reduces the layout space occupied by the sub-pixels, which is beneficial to reducing the difficulty of sub-pixel layout and improving the resolution of the display substrate.
  • the display substrate further includes data fan-out lines disposed on the substrate, the data fan-out lines are coupled to corresponding data lines, and the data fan-out lines are connected to the second conductive connection portion 70 Same layer same material setting.
  • the display substrate includes a plurality of data fan-out lines, one end of the data fan-out line is coupled to the corresponding data line, and the other end of the data fan-out line is coupled to the corresponding pin in the driver chip, so
  • the data fan-out lines are used to transmit the data signals provided by the driving chip to corresponding data lines.
  • the display substrate includes an active layer sequentially stacked along a direction away from the base, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, Interlayer insulating layer, first source-drain metal layer, first passivation layer PVX1, first planar layer PLN1, second source-drain metal layer, second passivation layer PVX2, second planar layer PLN2, anode layer, pixel definition layer, light-emitting functional layer, cathode layer, encapsulation structure.
  • the display substrate may not include the first passivation layer PVX1 and/or the second passivation layer PVX2.
  • the second source-drain metal layer includes the data fan-out line and the second conductive connection part 70.
  • the thickness of the data fan-out line is about 5500 angstroms.
  • the data fan-out line is arranged in the display area, that is, FIA (Fanout In AA) technology is adopted.
  • the above arrangement of the second source-drain metal layer includes the data fan-out line and the second conductive connection portion 70, so that the data fan-out line and the conductive structure below it are at least separated from the first passivation layer PVX1 and the The first flat layer PLN1 effectively reduces the resistance-capacitance load (RC Loading) generated by the data fan-out lines.
  • RC Loading resistance-capacitance load
  • the display substrate is formed through 12 patterning processes (Mask process), specifically including: the patterning process of the active layer, the patterning process of the first gate metal layer, the patterning process of the second gate metal layer, the interlayer The patterning process of the insulating layer, the patterning process of the first source-drain metal layer, the patterning process of the first flat layer PLN1, the patterning process of the first passivation layer PVX1, the patterning process of the second source-drain metal layer, the second flat layer PLN2 The patterning process of the second passivation layer PVX2, the patterning process of the anode layer and the patterning process of the pixel defining layer.
  • Mask process patterning processes
  • the active layer includes the driving active layer 35 , the light emission control active layer 34 , the first active layer 31 , and the second active layer 32 , the third active layer 33 and the reference connection portion 36 .
  • the first gate metal layer includes the gate of the driving transistor T5, the gate of the light emission control transistor T4, the gate of the first transistor T1, and the gate of the first transistor T1.
  • the gate of the second transistor T2, the gate of the third transistor T3, the first scan line 41, the second scan line 42, the third scan line 43, the light emission control signal line 44 and the The power connection part 45 is described above.
  • the second gate metal layer includes the second plate Cst2 of the storage capacitor Cst and the initialization signal line 51 .
  • the first source-drain metal layer includes a power line VDD, a data line, a reference signal line 63 , a first conductive connection portion 60 , and a first conductive pattern 64 to a sixth conductive pattern 69 .
  • the second source-drain metal layer includes a second conductive connection portion 70 and a data fan-out line.
  • the anode layer includes an anode pattern 80 .
  • the pixel defining layer forms a pixel opening 81 .
  • the pixel opening 81 is designed for equal-pitch arc printing, which can increase the printing rate for making organic light-emitting materials, and can improve the device performance of the display substrate.
  • the two first conductive connecting parts 60 are symmetrical about the axis of symmetry C
  • the two first conductive patterns 64 are symmetrical about the axis of symmetry C
  • the two first conductive patterns 64 are symmetrical about the axis of symmetry C.
  • the second conductive pattern 65 is symmetrical about the axis of symmetry C
  • the two third conductive patterns 66 are symmetrical about the axis of symmetry C
  • the two fourth conductive patterns 67 are symmetrical about the axis of symmetry C
  • the two of the third conductive patterns 66 are symmetrical about the axis of symmetry C.
  • the fifth conductive pattern 68 is symmetrical about the axis of symmetry C
  • the two sixth conductive patterns 69 are symmetrical about the axis of symmetry C
  • the two second conductive connections are symmetrical about the axis of symmetry C
  • the two The anode pattern is symmetrical about the axis of symmetry C
  • the two pixel openings 81 are symmetrical about the axis of symmetry C.
  • the two first conductive connecting parts 60 are symmetrical about the longitudinal axis, and the two first conductive patterns 64 are symmetrical about the longitudinal axis.
  • the two second conductive patterns 65 are symmetrical about the longitudinal axis
  • the two third conductive patterns 66 are symmetrical about the longitudinal axis
  • the two fourth conductive patterns 67 are symmetrical about the longitudinal axis.
  • One of the fifth conductive patterns 68 is symmetrical about the longitudinal axis
  • two of the sixth conductive patterns 69 are symmetrical about the longitudinal axis
  • two of the second conductive connecting parts are symmetrical about the longitudinal axis
  • two of the sixth conductive patterns 69 are symmetrical about the longitudinal axis.
  • the anode pattern is symmetrical about the longitudinal axis
  • the two pixel openings 81 are symmetrical about the longitudinal axis
  • the two first pole plates Cst1 are symmetrical about the longitudinal axis
  • the two second pole plates Cst2 are symmetrical about the longitudinal axis.
  • the longitudinal axis is symmetrical, the two first active layers 31 are symmetrical about the longitudinal axis, the two second active layers 32 are symmetrical about the longitudinal axis, and the two third active layers 33 It is symmetrical about the longitudinal axis, the two light emission control active layers 34 are symmetrical about the longitudinal axis, and the two driving active layers 35 are symmetrical about the longitudinal axis.
  • the longitudinal axis is located between two adjacent sub-pixels along the second direction, and the longitudinal axis extends along the first direction.
  • the sub-pixel driving circuit 201 includes a driving transistor T5, a light emission control transistor T4, a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst.
  • the working process of the sub-pixels in the first row and the sub-pixels in the second row in each group of sub-pixels includes: reset period P1, compensation period P2, data writing period P3 and light emitting period P4.
  • the reset periods of the first row of subpixels and the second row of subpixels are staggered, the compensation periods of the first row of subpixels and the second row of subpixels are partially staggered, and the data writing periods of the first row of subpixels and the second row of subpixels are completely stagger.
  • the light emission control signal EM is at an inactive level, which can avoid the second sub-pixel 203 in the process of writing data signals.
  • the first electrode of the driving transistor T5 of a row of sub-pixels continues to receive the power signal Vd, which avoids the drop of the gate-source voltage of the driving transistor T5 of the first row of sub-pixels, which affects the compensation of the sub-pixel driving circuit 201 in the first sub-pixel 202 Effect.
  • FIG. 2 shows the first scan signal G11 input from the first scan line 41, the second scan signal G21 input from the second scan line 42, and the third scan signal input from the third scan line 43 in the first row of sub-pixels.
  • FIG. 2 also shows the first scan signal G12 input from the first scan line 41, the second scan signal G22 input from the second scan line 42, and the third scan signal G22 input from the third scan line 43 in the second row of sub-pixels.
  • the light emission control signal EM is also illustrated in FIG. 2 .
  • the display substrate further includes a pixel defining layer, and the pixel defining layer defines a plurality of pixel openings 81, and the plurality of pixel openings 81 are connected to the pixel openings.
  • the plurality of sub-pixels included in the display substrate are in one-to-one correspondence;
  • the orthographic projection of the first active layer 31 on the substrate is located inside the orthographic projection of the corresponding pixel opening 81 on the substrate;
  • the orthographic projection of the second active layer 32 on the substrate is located inside the orthographic projection of the corresponding pixel opening 81 on the substrate;
  • the orthographic projection of the third active layer 33 on the substrate is located inside the orthographic projection of the pixel defining layer on the substrate;
  • the orthographic projection of the light emission control active layer 34 on the substrate is located inside the orthographic projection of the pixel defining layer on the substrate;
  • the orthographic projection of the driving active layer 35 on the substrate partially overlaps the orthographic projection of the pixel defining layer on the substrate and the corresponding orthographic projection of the pixel opening on the substrate.
  • the above setting method effectively reduces the layout space occupied by the sub-pixels, which is beneficial to reducing the difficulty of sub-pixel layout and improving the resolution of the display substrate.
  • Embodiments of the present disclosure also provide a display device, including the display substrate provided in the above embodiments.
  • the display substrate provided by the above embodiments by dividing the plurality of sub-pixels into multiple groups of sub-pixels, and setting the two sub-pixel driving circuits 201 included in each group of sub-pixels to multiplex the same light emission control sub-circuit, effectively reducing the The layout space occupied by each group of sub-pixels is reduced. Therefore, the display substrate provided by the above embodiment optimizes the layout of multiple sub-pixels, which not only ensures that the display substrate can achieve high-resolution display, but also is better compatible with GOA (English: Gate On Array) logic resources, providing technical support for special-shaped display products to achieve high-resolution GIA display.
  • GOA Gate On Array
  • the display device provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a back panel. board etc.
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

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Abstract

本公开提供一种显示基板和显示装置。所述显示基板包括基底和设置于所述基底上的多个子像素，所述多个子像素呈阵列分布；所述子像素包括子像素驱动电路和发光元件，所述子像素驱动电路包括相耦接的驱动子电路和发光控制子电路；所述发光元件包括阳极图形；所述多个子像素划分为多组子像素，每组子像素包括沿第一方向排列的两个子像素，所述两个子像素包括的两个子像素驱动电路复用同一个所述发光控制子电路，所述发光控制子电路用于分别控制所述两个子像素中的所述驱动子电路向所述阳极图形写入驱动信号；所述子像素还包括数据线，所述数据线包括沿所述第一方向延伸的部分。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示产品以其亮度高、功耗低、响应快、清晰度高、柔性好、发光效率高等优点被广泛应用。而随着OLED显示产品市场逐步打开，OLED异型显示产品的需求也越来越大。
发明内容
本公开的目的在于提供一种显示基板和显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：基底和设置于所述基底上的多个子像素，所述多个子像素呈阵列分布；
所述子像素包括子像素驱动电路和发光元件，所述子像素驱动电路包括相耦接的驱动子电路和发光控制子电路；所述发光元件包括阳极图形；
所述多个子像素划分为多组子像素，每组子像素包括沿第一方向排列的两个子像素，所述两个子像素包括的两个子像素驱动电路复用同一个所述发光控制子电路，所述发光控制子电路用于分别控制所述两个子像素中的所述驱动子电路向所述阳极图形写入驱动信号；
所述子像素还包括数据线，所述数据线包括沿所述第一方向延伸的部分。
可选的，所述子像素还包括：
发光控制信号线，所述发光控制信号线包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交；
所述两个子像素包括的两个子像素驱动电路复用同一条所述发光控制信号线，所述发光控制信号线与所述发光控制子电路耦接，用于控制所述发光控制子电路；所述发光控制信号线在所述基底上的正投影，位于所述两个子 像素包括的两个所述阳极图形在所述基底上的正投影之间。
可选的，所述发光控制子电路包括发光控制晶体管，所述发光控制晶体管的栅极与所述发光控制信号线耦接，所述发光控制晶体管的第二极与所述驱动子电路耦接；
所述发光控制晶体管包括发光控制有源层，所述发光控制有源层包括沿所述第二方向延伸的部分，所述发光控制有源层在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形在所述基底上的正投影之间。
可选的，所述子像素还包括：
电源线，所述电源线包括沿所述第一方向延伸的部分，所述两个子像素包括的电源线相耦接；
所述发光控制晶体管的第一极与所述电源线耦接，所述发光控制晶体管用于在所述发光控制信号线的控制下，导通或断开所述电源线与所述两个子像素中的所述驱动子电路之间的连接。
可选的，所述子像素还包括：
电源连接部，所述电源连接部包括沿所述第二方向延伸的部分；所述两个子像素包括的两个子像素驱动电路复用同一个所述电源连接部；沿所述第二方向所述电源线在所述基底上的正投影位于所述发光控制有源层在所述基底上的正投影的一侧，所述发光控制晶体管的第一极通过所述电源连接部与所述电源线耦接。
可选的，所述电源连接部与所述发光控制信号线同层同材料设置。
可选的，所述多个子像素划分为多个像素单元，所述像素单元包括沿所述第二方向排列的至少两个子像素；
所述至少两个子像素复用同一条电源线，所述至少两个子像素包括的电源连接部依次耦接。
可选的，所述驱动子电路包括驱动晶体管，所述驱动晶体管的第一极与所述发光控制晶体管的第二极耦接，所述驱动晶体管的第二极与所述发光元件的阳极图形耦接；
所述驱动晶体管包括驱动有源层；所述两个子像素驱动电路中，两个所述驱动晶体管包括的驱动有源层呈轴对称设置，对称轴沿所述第二方向延伸， 所述对称轴在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形在所述基底上的正投影之间。
可选的，所述对称轴在所述基底上的正投影与所述发光控制有源层在所述基底上的正投影交叠。
可选的，所述子像素还包括第一扫描线，所述第一扫描线包括沿所述第二方向延伸的部分；
所述子像素驱动电路还包括第一晶体管，所述第一晶体管的栅极与所述第一扫描线耦接，所述第一晶体管的第一极与所述数据线耦接，所述第一晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第一晶体管包括第一有源层，所述第一有源层包括沿所述第二方向延伸的部分；在同一个子像素中，所述第一有源层，所述驱动有源层和所述发光控制有源层沿所述第一方向依次排列。
可选的，所述两个子像素驱动电路中，两个所述第一晶体管包括的所述第一有源层关于所述对称轴对称设置。
可选的，所述多个子像素划分为多个像素单元，至少部分所述像素单元包括沿所述第二方向排列的第一子像素，第二子像素和第三子像素，所述第一子像素包括第一数据线，第二子像素包括第二数据线，第三子像素包括第三数据线；
在第一部分像素单元中，所述第一数据线位于所述第一子像素沿所述第二方向远离所述第二子像素的一侧，所述第二数据线和所述第三数据线均位于所述第二子像素和所述第三子像素之间；所述第一子像素与所述第二子像素之间具有第一间隔区；
在第二部分像素单元中，所述第一数据线和所述第二数据线均位于所述第一子像素和所述第二子像素之间，所述第三数据线位于所述第三子像素沿所述第二方向远离所述第二子像素的一侧；所述第二子像素与所述第三子像素之间具有第二间隔区。
可选的，所述多组子像素划分为沿所述第一方向排列的多行子像素组，每行子像素组包括沿所述第二方向排列的多组子像素；
所述显示基板还包括多个栅极驱动电路布局区和多个栅极驱动走线布局 区；
所述多个栅极驱动电路布局区与所述多行子像素组一一对应，每个栅极驱动电路布局区包括第一布局区和第二布局区，沿所述第一方向，所述第一布局区位于对应的一行子像素组的第一侧，所述第二布局区位于对应的一行子像素组的第二侧；
所述多个栅极驱动电路布局区与所述多个栅极驱动走线布局区一一对应，所述栅极驱动走线布局区包括沿所述第二方向排列的至少两个第三布局区；
所述至少两个第三布局区中：至少一个所述第三布局区位于对应的一行子像素组中的所述第一间隔区；至少一个所述第三布局区位于对应的一行子像素组中的所述第二间隔区。
可选的，所述子像素还包括基准信号线和第二扫描线，所述基准信号线包括沿所述第一方向延伸的部分，所述第二扫描线包括沿所述第二方向延伸的部分；
所述子像素驱动电路还包括第二晶体管，所述第二晶体管的栅极与所述第二扫描线耦接，所述第二晶体管的第一极与所述基准信号线耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第二晶体管包括第二有源层，所述第二有源层包括沿所述第二方向延伸的部分；在同一个子像素中，所述第二有源层，所述第一有源层和所述发光控制有源层沿所述第一方向依次排列。
可选的，所述两个子像素驱动电路中，两个所述第二晶体管包括的所述第二有源层关于所述对称轴对称设置。
可选的，所述子像素还包括基准连接部，所述基准连接部包括沿所述第二方向延伸的部分；所述第二晶体管的第一极通过所述基准连接部与所述基准信号线耦接。
可选的，所述多个子像素划分为多个像素单元，所述像素单元包括沿所述第二方向排列的至少两个子像素；
沿所述第二方向排列的相邻两个所述像素单元包括的各子像素复用一条基准信号线，所述基准信号线位于所述相邻两个所述像素单元之间，所述各 子像素包括的基准连接部依次耦接。
可选的，在同一个子像素中，所述基准连接部在所述基底上的正投影，所述第二扫描线在所述基底上的正投影，所述第一扫描线在所述基底上的正投影，所述发光控制信号线在所述基底上的正投影沿所述第一方向依次排列。
可选的，所述子像素还包括初始化信号线和第三扫描线，所述初始化信号线和所述第三扫描线均包括沿所述第二方向延伸的部分；
所述子像素驱动电路还包括第三晶体管，所述第三晶体管的栅极与所述第三扫描线耦接，所述第三晶体管的第一极与所述初始化信号线耦接，所述第三晶体管的第二极与所述发光元件的阳极图形耦接；
所述第三晶体管包括第三有源层；在同一个子像素中，所述第一有源层，所述第三有源层和所述发光控制有源层沿所述第一方向依次排列。
可选的，所述两个子像素驱动电路中，两个所述第三晶体管包括的所述第三有源层关于所述对称轴对称设置。
可选的，所述第一晶体管，所述第二晶体管和所述第三晶体管中的至少一个包括双栅结构。
可选的，所述子像素驱动电路还包括存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板位于所述基底和所述第二极板之间；所述第一极板与所述驱动晶体管的栅极耦接，所述第二极板分别与所述驱动晶体管的第二极和所述发光元件的阳极图形耦接；
所述两个子像素驱动电路中，两个所述第一极板关于所述对称轴对称设置；和/或，两个所述第二极板关于所述对称轴对称设置。
可选的，所述子像素还包括异层设置的第一导电连接部和第二导电连接部，所述第一导电连接部位于所述基底和所述第二导电连接部之间，所述阳极图形位于所述第二导电连接部背向所述基底的一侧；
所述第二极板与所述第一导电连接部耦接；
所述第二导电连接部在所述基底上的正投影，与所述第一导电连接部在所述基底上的正投影之间具有第一交叠区域，所述第二导电连接部在所述基底上的正投影，与所述阳极图形在所述基底上的正投影之间具有第二交叠区域；
所述第二导电连接部通过第一过孔与所述第一导电连接部耦接，所述第一过孔在所述基底上的正投影位于所述第一交叠区域；所述第二导电连接部通过第二过孔与所述阳极图形耦接，所述第二过孔在所述基底上的正投影位于所述第二交叠区域。
可选的，所述第一导电连接部在所述基底上的正投影的至少部分，位于所述第三有源图形在所述基底上的正投影，与所述驱动有源层在所述基底上的正投影之间。
可选的，所述第三有源层包括相耦接的第一部分和第二部分，所述第一部分包括沿所述第一方向延伸的部分，所述第二部分包括沿所述第二方向延伸的部分，所述第一部分和所述第二部分形成为L型结构；在同一个所述子像素中，所述第三有源层和所述驱动有源层沿第三方向排列，所述第三方向与所述第一方向和所述第二方向均相交；所述L型结构的90度夹角朝向所述驱动有源层。
可选的，所述显示基板还包括设置于所述基底上的数据扇出线，所述数据扇出线与相应的数据线耦接，所述数据扇出线与所述第二导电连接部同层同材料设置。
可选的，所述显示基板还包括像素界定层，所述像素界定层限定出多个像素开口，所述多个像素开口与所述显示基板包括的多个子像素一一对应；
所述第一有源层在所述基底上的正投影，位于对应的像素开口在所述基底上的正投影的内部；
所述第二有源层在所述基底上的正投影，位于对应的像素开口在所述基底上的正投影的内部；
所述第三有源层在所述基底上的正投影，位于所述像素界定层在所述基底上的正投影的内部；
所述发光控制有源层在所述基底上的正投影，位于所述像素界定层在所述基底上的正投影的内部；
所述驱动有源层在所述基底上的正投影，分别与所述像素界定层在所述基底上的正投影和对应的所述像素开口在所述基底上的正投影部分交叠。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置， 包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的显示基板中最小重复单元对应的电路图；
图2为本公开实施例提供的一组子像素中子像素驱动电路的驱动时序图；
图3为图1中电路图对应的布局示意图；
图4为本公开实施例提供的栅极驱动电路布局区和栅极驱动走线布局区示意图；
图5为图3中有源层的示意图；
图6为图3中第一栅金属层的布局示意图；
图7为图3中第二栅金属层的布局示意图；
图8为图3中第一源漏金属层的布局示意图；
图9为图3中第二源漏金属层的布局示意图；
图10为图3中阳极层的布局示意图；
图11为图3中像素界定层形成的开口的布局示意图；
图12为图3中有源层和第一栅金属层的布局示意图；
图13为图3中有源层和第一栅金属层和第二栅金属层的布局示意图；
图14为图13的基础上增加第一源漏金属层的布局示意图；
图15为图14的基础上增加第二源漏金属层的布局示意图；
图16为图15的基础上增加阳极层的布局示意图；
图17为图3中有源层和第二栅金属层和第一源漏金属层的布局示意图；
图18为图3中第二栅金属层和第一源漏金属层的布局示意图；
图19为图3中第一源漏金属层和第二源漏金属层的布局示意图；
图20为图3中第二源漏金属层和阳极层的布局示意图；
图21为本公开实施例提供的第一过孔和第二过孔的截面示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板和显示装置，下面结合说明书附图进行详细描述。
为了更好的保证异型OLED显示产品的定制化需求，可以考虑将OLED显示产品中的栅极驱动电路设置于显示区域内，即采用GIA(Gate Driver In AA)技术，但是这样栅极驱动电路会占用显示区域内的部分空间，影响显示产品的分辨率。
请参阅图1，图3，图15和图16，本公开实施例提供了一种显示基板，包括：基底和设置于所述基底上的多个子像素20，所述多个子像素20呈阵列分布；
所述子像素包括子像素驱动电路201和发光元件EL，所述子像素驱动电路201包括相耦接的驱动子电路和发光控制子电路；所述发光元件EL包括阳极图形80；
所述多个子像素划分为多组子像素，每组子像素A包括沿第一方向排列的两个子像素，所述两个子像素包括的两个子像素驱动电路201复用同一个所述发光控制子电路，所述发光控制子电路用于分别控制所述两个子像素中的所述驱动子电路向所述阳极图形80写入驱动信号；
所述子像素还包括数据线，所述数据线包括沿所述第一方向延伸的部分。
示例性的，所述显示基板包括显示区域和包围所述显示区域的周边区域。所述显示基板包括多个子像素，所述多个子像素呈阵列分布在所述显示区域。
示例性的，所述子像素包括子像素驱动电路201和发光元件，所述子像素驱动电路201与所述发光元件耦接，用于为所述发光元件提供驱动信号，以实现驱动发光元件发光。示例性的，所述子像素驱动电路201包括5T1C电路结构，即包括5个薄膜晶体管和一个存储电容Cst。示例性的，所述发光元件包括沿远离所述基底的方向依次层叠设置的阳极图形80，发光功能层和阴极层；所述发光功能层包括层叠设置的电子注入层，电子传输层，有机发光材料层，空穴传输层和空穴注入层。示例性的，所述阴极层接收负电源信号VSS。
示例性的，所述多个子像素中，各子像素包括的电子注入层形成为一体 结构，能够覆盖整个所述显示区域；同样的，各子像素包括的所述电子传输层，所述空穴传输层和所述空穴注入层也均可以形成为一体结构，能够覆盖整个所述显示区域。示例性的，所述多个子像素中，各子像素包括的阴极层形成为一体结构，能够覆盖整个所述显示区域。
示例性的，所述多个子像素划分为多组子像素，所述多组子像素呈阵列分布，每个子像素仅能够属于一组子像素。示例性的，每组子像素包括沿第一方向排列的两个子像素，所述第一方向包括竖直方向。示例性的，沿第一方向排列的两个子像素包括：所述两个子像素包括的两个子像素驱动电路201的布局区域沿所述第一方向排列；和/或，所述两个子像素包括的两个发光元件中的阳极图形80沿所述第一方向排列。
示例性的，每个子像素驱动电路201均包括驱动子电路和发光控制子电路，所述发光控制子电路与所述驱动子电路耦接，所述发光控制子电路用于控制所述驱动子电路向所述阳极图形80写入驱动信号，从而实现控制所述发光元件的发光情况。
示例性的，每组子像素包括沿第一方向排列的两个子像素，所述两个子像素包括的两个子像素驱动电路201复用同一个所述发光控制子电路，即复用的所述发光控制子电路分别与所述两个子像素驱动电路201中的两个驱动子电路分别耦接，复用的所述发光控制子电路分别控制所述两个驱动子电路向相应的所述阳极图形80写入驱动信号。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，通过将所述多个子像素划分为多组子像素，并设置每组子像素包括的两个子像素驱动电路201复用同一个所述发光控制子电路，减少了发光控制子电路的数量，有效缩小了每组子像素占用的布局空间，因此，本公开实施例提供的显示基板对多个子像素的布局进行了优化设计，不仅保证了显示基板能够实现高分辨率的显示，还较好的兼容了GOA(英文：Gate On Array)逻辑资源，为异型显示产品实现高分辨率GIA显示提供了技术支持。
如图1，图3，图6和图16所示，在一些实施例中，所述子像素还包括：
发光控制信号线44，所述发光控制信号线44包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交；
所述两个子像素包括的两个子像素驱动电路201复用同一条所述发光控制信号线44，所述发光控制信号线44与所述发光控制子电路耦接，用于控制所述发光控制子电路；所述发光控制信号线44在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形80在所述基底上的正投影之间。
示例性的，所述第一方向包括竖直方向，所述第二方向包括水平方向。
示例性的，所述两个子像素包括的两个子像素驱动电路201复用同一条所述发光控制信号线44，所述发光控制信号线44分别与所述发光控制子电路和相应的栅极驱动电路耦接，所述发光控制信号线44用于将该栅极驱动电路提供的发光控制信号EM传输至所述发光控制子电路，所述发光控制子电路用于在所述发光控制信号EM的控制下，分别控制其耦接的两个驱动子电路向对应的所述阳极图形80写入驱动信号。
上述设置所述两个子像素包括的两个子像素驱动电路201复用同一条所述发光控制信号线44，减少了所述发光控制信号线44的数量，有效缩小了每组子像素占用的布局空间。
通过设置所述发光控制信号线44在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形80在所述基底上的正投影之间，使得所述发光控制信号线44大致位于所述两个子像素之间的位置，这样再将所述发光控制子电路布局在所述发光控制信号线44的附近，不仅保证了所述发光控制子电路与所述发光控制信号线44，以及两个驱动子电路的良好连接性能，还有效降低了所述发光控制信号线44和所述发光控制子电路的布局难度。
如图1，图3，图5，图6，图10和图12所示，在一些实施例中，所述发光控制子电路包括发光控制晶体管T4，所述发光控制晶体管T4的栅极与所述发光控制信号线44耦接，所述发光控制晶体管T4的第二极与所述驱动子电路耦接；
所述发光控制晶体管T4包括发光控制有源层34，所述发光控制有源层34包括沿所述第二方向延伸的部分，所述发光控制有源层34在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形80在所述基底上的正投影之间。
示例性的，当所述发光控制信号线44提供的发光控制信号EM为有效电 平时，所述发光控制晶体管T4导通，当所述发光控制信号线44提供的发光控制信号EM为非有效电平时，所述发光控制晶体管T4截止。
示例性的，所述发光控制晶体管T4的栅极与其耦接的发光控制信号线44形成为一体结构。示例性的，所述发光控制晶体管T4的第二极通过第一导电图形64与所述驱动子电路耦接。如图3，图8和图12所示，示例性的，在一组子像素中，所述发光控制晶体管T4的第二极通过第一导电图形64分别与该一组子像素中的两个驱动子电路耦接。示例性的，所述第一导电图形64包括沿所述第一方向延伸的部分。示例性的，所述第一导电图形64与所述显示基板中的数据线同层同材料设置。示例性的，所述第一导电图形64在所述基底上的正投影，与所述发光控制信号线44在所述基底上的正投影部分交叠。
示例性的，所述发光控制有源层34包括沿所述第二方向延伸的部分。示例性的，所述发光控制有源层34的两个端部在所述第一方向的宽度，大于所述发光控制有源层34位于两个端部之间的中间部分在所述第一方向的宽度。示例性的，所述发光控制有源层34的中间部分在所述基底上的正投影与所述发光控制晶体管T4的栅极在所述基底上的正投影至少部分交叠，所述发光控制有源层34的中间部分用于形成所述发光控制晶体管T4的沟道区。
上述设置所述发光控制有源层34在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形80在所述基底上的正投影之间，使得所述发光控制晶体管T4整体位于一组子像素中的两个子像素之间的位置，这样不仅保证了所述发光控制晶体管T4与所述发光控制信号线44，以及两个驱动子电路的良好连接性能，还有效降低了所述发光控制信号线44和所述发光控制晶体管T4的布局难度。
如图3，图8，图12所示，在一些实施例中，所述子像素还包括：
电源线VDD，所述电源线VDD包括沿所述第一方向延伸的部分，所述两个子像素包括的电源线VDD相耦接；
所述发光控制晶体管T4的第一极与所述电源线VDD耦接，所述发光控制晶体管T4用于在所述发光控制信号线44的控制下，导通或断开所述电源线VDD与所述两个子像素中的所述驱动子电路之间的连接。
示例性的，在同一组子像素中，所述两个子像素包括的电源线VDD相耦接，形成为一体结构。
示例性的，所述显示基板中，沿所述第一方向位于同一列的全部子像素中的电源线VDD依次耦接，形成为一体结构。
示例性的，所述电源线VDD包括正电源线，所述正电源线用于提供正电源信号Vd。所述发光控制晶体管T4在所述发光控制信号线44提供的发光控制信号EM在控制下导通或者截止，以控制是否将所述电源线VDD提供的电源信号Vd传输至所述驱动子电路。
如图3，图6，图8，图12和图15所示，在一些实施例中，所述子像素还包括：
电源连接部45，所述电源连接部45包括沿所述第二方向延伸的部分；所述两个子像素包括的两个子像素驱动电路201复用同一个所述电源连接部45；沿所述第二方向所述电源线VDD在所述基底上的正投影位于所述发光控制有源层34在所述基底上的正投影的一侧，所述发光控制晶体管T4的第一极通过所述电源连接部45与所述电源线VDD耦接。
示例性的，所述电源连接部45与所述发光控制有源层34异层设置，所述电源连接部45与所述电源线VDD异层设置，所述电源连接部45通过第二导电图形65与所述发光控制晶体管T4的第一极耦接，所述电源连接部45通过过孔与所述电源线VDD耦接，所述过孔贯穿位于所述电源连接部45与所述电源线VDD之间的绝缘层。
示例性的，所述电源连接部45与所述发光控制信号线44沿所述第一方向排列。
上述设置所述发光控制晶体管T4的第一极通过所述电源连接部45与所述电源线VDD耦接，不仅保证了所述发光控制晶体管T4与所述电源线VDD之间的连接性能，避免了所述发光控制晶体管T4为了实现与所述电源线VDD连接而与其他导电结构发生短路，还有效降低了所述发光控制晶体管T4的布局难度。
如图6所示，在一些实施例中，所述电源连接部45与所述发光控制信号线44同层同材料设置。
上述设置方式使得所述电源连接部45能够与所述发光控制信号线44在同一次构图工艺中形成，有效简化了显示基板的制作工艺流程，降低了显示基板的制作成本。
如图3，图6,和图14所示，在一些实施例中，所述多个子像素划分为多个像素单元B，所述像素单元B包括沿所述第二方向排列的至少两个子像素；所述至少两个子像素复用同一条电源线VDD，所述至少两个子像素包括的电源连接部45依次耦接。
示例性的，所述多个子像素划分为多个像素单元B，所述多个像素单元B呈阵列分布。
示例性的，所述像素单元B包括沿所述第二方向排列的至少两个子像素；所述至少两个子像素复用同一条电源线VDD，沿所述第二方向，所述电源线VDD位于所述至少两个子像素的一侧。
示例性的，所述至少两个子像素包括的电源连接部45依次耦接，形成为一体结构。示例性的，沿所述第二方向位于同一行的像素单元B中，各像素单元B中的所述电源连接部45依次耦接，形成为一体结构。
上述设置所述至少两个子像素复用同一条电源线VDD，所述至少两个子像素包括的电源连接部45依次耦接，不仅实现了各子像素均能够通过电源连接部45与复用的电源线VDD耦接，还有效节省了各子像素占用的布局空间，有利于提升显示基板的分辨率。
而且，上述将沿所述第二方向位于同一行的像素单元B中，各像素单元B中的所述电源连接部45依次耦接，使得所述显示基板中的电源线VDD和电源连接部45能够形成网状结构，有利于电源信号Vd整体的均一性。
如图1，图3，图5，图8，图12所示，在一些实施例中，所述驱动子电路包括驱动晶体管T5，所述驱动晶体管T5的第一极与所述发光控制晶体管T4的第二极耦接，所述驱动晶体管T5的第二极与所述发光元件的阳极图形80耦接；
所述驱动晶体管T5包括驱动有源层35；所述两个子像素驱动电路201中，两个所述驱动晶体管T5包括的驱动有源层35呈轴对称设置，对称轴C沿所述第二方向延伸，所述对称轴C在所述基底上的正投影，位于所述两个 子像素包括的两个所述阳极图形80在所述基底上的正投影之间。
示例性的，所述驱动晶体管T5的第一极通过所述第一导电图形64与所述发光控制晶体管T4的第二极耦接，所述驱动晶体管T5的第二极与存储电容Cst的第二极板Cst2耦接，通过所述第二极板Cst2实现与阳极图形80耦接。示例性的，所述驱动晶体管T5的第二极与存储电容Cst的第二极板Cst2异层设置，所述驱动晶体管T5的第二极通过所述第三导电图形66与所述第二极板Cst2耦接。
示例性的，所述驱动有源层35包括U形部，和由所述U形部的两端分别延伸出的两个端部。示例性的，所述U形部用于形成所述驱动晶体管T5的沟道区，所述两个端部作为所述驱动晶体管T5的第一极和第二极。
示例性的，在同一组子像素包括的所述两个子像素驱动电路201中，两个所述驱动晶体管T5包括的栅极关于所述对称轴C对称设置。
示例性的，沿所述第二方向相邻的两个子像素中包括的两个所述驱动有源层35关于纵轴线对称，所述纵轴线位于两个所述驱动有源层35之间，所述纵轴线沿所述第一方向延伸；沿所述第二方向相邻的两个子像素中包括的两个所述驱动晶体管T5的栅极关于纵轴线对称。
上述对称的设置方式有效缩小了子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图3和图5所示，在一些实施例中，所述对称轴C在所述基底上的正投影与所述发光控制有源层34在所述基底上的正投影交叠。
上述设置方式使得所述发光控制晶体管T4位于一组子像素沿所述第一方向的中心位置，这样不仅保证了所述发光控制晶体管T4与所述发光控制信号线44，以及两个驱动子电路的良好连接性能，有效降低了所述发光控制信号线44和所述发光控制晶体管T4的布局难度，还有利于缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图1，图3，图5，图6，图12所示，在一些实施例中，所述子像素还包括数据线62和第一扫描线41，所述数据线62包括沿所述第一方向延伸的部分，所述第一扫描线41包括沿所述第二方向延伸的部分；
所述子像素驱动电路201还包括第一晶体管T1，所述第一晶体管T1的 栅极与所述第一扫描线41耦接，所述第一晶体管T1的第一极与所述数据线62耦接，所述第一晶体管T1的第二极与所述驱动晶体管T5的栅极耦接；
所述第一晶体管T1包括第一有源层31，所述第一有源层31包括沿所述第二方向延伸的部分；在同一个子像素中，所述第一有源层31，所述驱动有源层35和所述发光控制有源层34沿所述第一方向依次排列。
示例性的，沿所述第一方向位于同一列的子像素包括的数据线依次耦接，形成为一体结构。沿所述第二方向位于同一行的子像素包括的第一扫描线41依次耦接，形成为一体结构。
示例性的，所述数据线接收所述显示基板中驱动芯片提供的数据信号。
示例性的，所述第一扫描线41与相应的栅极驱动电路耦接，接收相应的栅极驱动电路提供的第一扫描信号。
示例性的，所述第一晶体管T1在所述第一扫描线41传输的第一扫描信号的控制下导通或者截止，以实现将所述数据线与所述驱动晶体管T5的栅极之间导通连接或断开连接。
示例性的，所述第一有源层31包括沿所述第二方向延伸的部分。示例性的，所述第一有源层31的两个端部在所述第一方向的宽度，大于所述第一有源层31位于两个端部之间的中间部分在所述第一方向的宽度。示例性的，所述第一有源层31的中间部分在所述基底上的正投影与所述第一晶体管T1的栅极在所述基底上的正投影至少部分交叠，所述第一有源层31的中间部分用于形成所述第一晶体管T1的沟道区。
示例性的，所述第一有源层31与所述数据线异层设置，所述第一有源层31与所述驱动晶体管T5的栅极异层设置。所述第一晶体管T1的第一极与所述数据线通过过孔耦接，该过孔贯穿位于所述第一晶体管T1的第一极与所述数据线之间的绝缘层，所述第一晶体管T1的第二极通过第六导电连接部分别与所述驱动晶体管T5的栅极和第二晶体管T2的第二极耦接。
示例性的，在同一组子像素的其中一个子像素中，所述第一有源层31，所述驱动有源层35和所述发光控制有源层34沿所述第一方向自上向下依次排列；在同一组子像素的另一个子像素中，所述第一有源层31，所述驱动有源层35和所述发光控制有源层34沿所述第一方向自下向上依次排列。
如图12所示，上述布局方式使得所述第一晶体管T1，所述驱动晶体管T5和所述发光控制晶体管T4能够沿所述第二方向依次排列，不仅有利于降低所述子像素的布局难度，还有利于缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图3，图5和图13所示，在一些实施例中，所述两个子像素驱动电路201中，两个所述第一晶体管T1包括的所述第一有源层31关于所述对称轴C对称设置。
上述设置方式有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图3和图16所示，在一些实施例中，所述多个子像素划分为多个像素单元B，至少部分所述像素单元B包括沿所述第二方向排列的第一子像素202，第二子像素203和第三子像素204，所述第一子像素202包括第一数据线621，第二子像素203包括第二数据线622，第三子像素204包括第三数据线623；
在第一部分像素单元B中，所述第一数据线621位于所述第一子像素202沿所述第二方向远离所述第二子像素203的一侧，所述第二数据线622和所述第三数据线623均位于所述第二子像素203和所述第三子像素204之间；所述第一子像素202与所述第二子像素203之间具有第一间隔区；
在第二部分像素单元B中，所述第一数据线621和所述第二数据线622均位于所述第一子像素202和所述第二子像素203之间，所述第三数据线623位于所述第三子像素204沿所述第二方向远离所述第二子像素203的一侧；所述第二子像素203与所述第三子像素204之间具有第二间隔区。
示例性的，所述像素单元B包括沿所述第二方向排列的第一子像素202，第二子像素203和第三子像素204，四个所述像素单元B构成所述显示基板中的最小重复单元。图3示意了所述显示基板中的最小重复单元。
示例性的，所述第一子像素202，所述第二子像素203和所述第三子像素204的颜色各不相同。示例性的，所述第一子像素202包括红色子像素，所述第二子像素203包括绿色子像素，所述第三子像素204包括蓝色子像素。需要说明，图1中示意了红色子像素接收的红色数据信号DATAR1和 DATAR2，绿色子像素接收的绿色数据信号DATAG1和DATAG2，蓝色子像素接收的蓝色数据信号DATAB1和DATAB2。
示例性的，所述第一子像素202包括第一子像素驱动电路，所述第二子像素203包括第二子像素驱动电路，所述第三子像素204包括第三子像素驱动电路。
示例性的，在第一部分像素单元B中，所述第一数据线621在所述基底上的正投影，位于所述第一子像素驱动电路在所述基底上的正投影沿所述第二方向远离所述第二子像素驱动电路在所述基底上的正投影的一侧，所述第二数据线622在所述基底上的正投影和所述第三数据线623在所述基底上的正投影，均位于所述第二子像素驱动电路在所述基底上的正投影和所述第三子像素驱动电路在所述基底上的正投影之间。
示例性的，在第二部分像素单元B中，所述第一数据线621在所述基底上的正投影和所述第二数据线622在所述基底上的正投影，均位于所述第一子像素驱动电路在所述基底上的正投影和所述第二子像素驱动电路在所述基底上的正投影之间，所述第三数据线623在所述基底上的正投影，位于所述第三子像素驱动电路在所述基底上的正投影沿所述第二方向远离所述第二子像素驱动电路在所述基底上的正投影的一侧。
示例性的，所述第一间隔区在所述基底上的正投影，位于所述第一子像素驱动电路在所述基底上的正投影与所述第二子像素驱动电路在所述基底上的正投影之间。
示例性的，所述第一间隔区在所述基底上的正投影，位于所述第一子像素202包括的阳极图形80在所述基底上的正投影与所述第二子像素203包括的阳极图形80在所述基底上的正投影之间。
示例性的，所述第二间隔区在所述基底上的正投影，位于所述第二子像素驱动电路在所述基底上的正投影与所述第三子像素驱动电路在所述基底上的正投影之间。
示例性的，所述第二间隔区在所述基底上的正投影，位于所述第二子像素203包括的阳极图形80在所述基底上的正投影与所述第三子像素204包括的阳极图形80在所述基底上的正投影之间。
上述布局方式有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图3，图4，图16所示，在一些实施例中，所述多组子像素划分为沿所述第一方向排列的多行子像素组，每行子像素组包括沿所述第二方向排列的多组子像素；
所述显示基板还包括多个栅极驱动电路布局区90和多个栅极驱动走线布局区91；
所述多个栅极驱动电路布局区90与所述多行子像素组一一对应，每个栅极驱动电路布局区90包括第一布局区901和第二布局区902，沿所述第一方向，所述第一布局区901位于对应的一行子像素组的第一侧，所述第二布局区902位于对应的一行子像素组的第二侧；
所述多个栅极驱动电路布局区90与所述多个栅极驱动走线布局区91一一对应，所述栅极驱动走线布局区91包括沿所述第二方向排列的至少两个第三布局区910；
所述至少两个第三布局区910中：至少一个所述第三布局区910位于对应的一行子像素组中的所述第一间隔区；至少一个所述第三布局区910位于对应的一行子像素组中的所述第二间隔区。
示例性的，所述栅极驱动电路布局区90用于布局栅极驱动电路，所述栅极驱动走线布局区91用于布局栅极驱动走线，所述栅极驱动走线与相应的栅极驱动电路耦接，用于为栅极驱动电路提供相应的信号，或者用于将所述栅极驱动电路提供的信号传输至子像素。
示例性的，所述第一布局区901和所述第二布局区902均沿所述第二方向延伸，所述第三布局区910沿所述第一方向延伸。
示例性的，沿所述第一方向，所述第一布局区901位于对应的一行子像素组的第一侧，所述第二布局区902位于对应的一行子像素组的第二侧，所述第一侧和所述第二侧沿所述第一方向相对。
示例性的，所述多个栅极驱动电路布局区90与所述多个栅极驱动走线布局区91一一对应，所述栅极驱动走线布局区91包括沿所述第二方向排列的至少两个第三布局区910，所述至少两个第三布局区910位于对应的第一布 局区901和第二布局区902之间。
上述设置方式使得所述栅极驱动电路和所述栅极驱动走线均能够布局在显示区域内，将所述栅极驱动电路和所述栅极驱动走线的布局最优化，很好的兼容了GOA逻辑资源，为异型显示产品实现高分辨率GIA显示提供了技术支持。
如图1，图3，图5，图6，图12所示，在一些实施例中，所述子像素还包括基准信号线63和第二扫描线42，所述基准信号线63包括沿所述第一方向延伸的部分，所述第二扫描线42包括沿所述第二方向延伸的部分；
所述子像素驱动电路201还包括第二晶体管T2，所述第二晶体管T2的栅极与所述第二扫描线42耦接，所述第二晶体管T2的第一极与所述基准信号线63耦接，所述第二晶体管T2的第二极与所述驱动晶体管T5的栅极耦接；
所述第二晶体管T2包括第二有源层32，所述第二有源层32包括沿所述第二方向延伸的部分；在同一个子像素中，所述第二有源层32，所述第一有源层31和所述发光控制有源层34沿所述第一方向依次排列。
示例性的，沿所述第一方向位于同一列的子像素包括的基准信号线63依次耦接，形成为一体结构。沿所述第二方向位于同一行的子像素包括的第二扫描线42依次耦接，形成为一体结构。
示例性的，所述基准信号线63用于提供基准信号Vref。
示例性的，所述第二扫描线42与相应的栅极驱动电路耦接，接收相应的栅极驱动电路提供的第二扫描信号。
示例性的，所述第二晶体管T2在所述第二扫描线42传输的第二扫描信号的控制下导通或者截止，以实现将所述基准信号线63与所述驱动晶体管T5的栅极之间导通连接或断开连接。
示例性的，所述第二有源层32包括沿所述第二方向延伸的部分。示例性的，所述第二有源层32的两个端部在所述第一方向的宽度，大于所述第二有源层32位于两个端部之间的中间部分在所述第一方向的宽度。示例性的，所述第二有源层32的中间部分在所述基底上的正投影与所述第二晶体管T2的栅极在所述基底上的正投影至少部分交叠，所述第二有源层32的中间部分用 于形成所述第二晶体管T2的沟道区。
示例性的，在同一组子像素的其中一个子像素中，所述第二有源层32，所述第一有源层31和所述发光控制有源层34沿所述第一方向自上向下依次排列；在同一组子像素的另一个子像素中，所述第二有源层32，所述第一有源层31和所述发光控制有源层34沿所述第一方向自下向上依次排列。
上述布局方式使得所述第二晶体管T2，所述第一晶体管T1和所述发光控制晶体管T4能够沿所述第二方向依次排列，不仅有利于降低所述子像素的布局难度，还有利于缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图3和图5所示，在一些实施例中，所述两个子像素驱动电路201中，两个所述第二晶体管T2包括的所述第二有源层32关于所述对称轴C对称设置。
上述设置方式有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图5，图12，图14所示，在一些实施例中，所述子像素还包括基准连接部36，所述基准连接部36包括沿所述第二方向延伸的部分；所述第二晶体管T2的第一极通过所述基准连接部36与所述基准信号线63耦接。
示例性的，所述基准连接部36与所述第二有源层32同层同材料设置，所述基准连接部36与所述基准信号线63异层设置，所述基准连接部36通过第四导电图形67与所述第二晶体管T2的第一极耦接，所述基准连接部36通过过孔与所述基准信号线63耦接，所述过孔贯穿位于所述基准连接部36与所述基准信号线63之间的绝缘层。
示例性的，在同一组子像素中，两个子像素包括的两个基准连接部36关于所述对称轴C对称。
上述设置所述第二晶体管T2的第一极通过所述基准连接部36与所述基准信号线63耦接，不仅保证了所述第二晶体管T2与所述基准信号线63之间的连接性能，避免了所述第二晶体管T2为了实现与所述基准信号线63连接而与其他导电结构发生短路，还有效降低了所述第二晶体管T2的布局难度。
如图5，图12，图14，图17所示，在一些实施例中，所述多个子像素 划分为多个像素单元B，所述像素单元B包括沿所述第二方向排列的至少两个子像素；沿所述第二方向排列的相邻两个所述像素单元B包括的各子像素复用一条基准信号线63，所述基准信号线63位于所述相邻两个所述像素单元B之间，所述各子像素包括的基准连接部36依次耦接。
示例性的，所述基准信号线63在所述基底上的正投影，与相邻的一个像素单元B包括的一个阳极图形80在所述基底上的正投影交叠，与相邻的另一个像素单元B包括的任意阳极图形80在所述基底上的正投影均不交叠。
示例性的，所述各子像素包括的基准连接部36依次耦接，形成为一体结构。示例性的，沿所述第二方向位于同一行的像素单元B中，各像素单元B中的所述电源连接部45依次耦接，形成为一体结构。
上述设置沿所述第二方向排列的相邻两个所述像素单元B包括的各子像素复用一条基准信号线63，所述各子像素包括的基准连接部36依次耦接，不仅实现了各子像素均能够通过基准连接部36与复用的基准信号线63耦接，还有效节省了各子像素占用的布局空间，有利于提升显示基板的分辨率。
而且，上述将沿所述第二方向位于同一行的像素单元B中，各像素单元B中的所述基准连接部36依次耦接，使得所述显示基板中的基准信号线63和基准连接部36能够形成网状结构，有利于基准信号Vref整体的均一性。
如图12所示，在一些实施例中，在同一个子像素中，所述基准连接部36在所述基底上的正投影，所述第二扫描线42在所述基底上的正投影，所述第一扫描线41在所述基底上的正投影，所述发光控制信号线44在所述基底上的正投影沿所述第一方向依次排列。
上述设置方式不仅有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率，还有利于降低所述子像素的布局难度。
如图1，图3，图5，图6，图7，图10，图18所示，在一些实施例中，所述子像素还包括初始化信号线51和第三扫描线43，所述初始化信号线51和所述第三扫描线43均包括沿所述第二方向延伸的部分；
所述子像素驱动电路201还包括第三晶体管T3，所述第三晶体管T3的栅极与所述第三扫描线43耦接，所述第三晶体管T3的第一极与所述初始化信号线51耦接，所述第三晶体管T3的第二极与所述发光元件的阳极图形80 耦接；
所述第三晶体管T3包括第三有源层33；在同一个子像素中，所述第一有源层31，所述第三有源层33和所述发光控制有源层34沿所述第一方向依次排列。
示例性的，所述初始化信号线51包括沿所述第二方向延伸的部分，沿所述第二方向位于同一行的子像素包括的所述初始化信号线51依次耦接，形成为一体结构。
示例性的，所述初始化信号线51用于提供初始化信号Vinit。
示例性的，所述第三扫描线43包括沿所述第二方向延伸的部分，沿所述第二方向位于同一行的子像素包括的所述第三扫描线43依次耦接，形成为一体结构。
示例性的，所述第三扫描线43与相应的栅极驱动电路耦接，接收相应的栅极驱动电路提供的第三扫描信号。
示例性的，所述第三晶体管T3在所述第三扫描线43传输的第三扫描信号的控制下导通或者截止，以实现将所述初始化信号线51与所述第三晶体管T3的第一极之间导通连接或断开连接。
示例性的，所述第三有源层33与所述初始化信号线51异层设置，所述第三有源层33与所述第三扫描线43异层设置。所述第三晶体管T3的第一极通过第五导电图形68与所述初始化信号线51耦接，所述第三晶体管T3的第二极通过第一导电连接部60与存储电容Cst的第二极板Cst2耦接。
上述设置在同一个子像素中，所述第一有源层31，所述第三有源层33和所述发光控制有源层34沿所述第一方向依次排列，有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率，还有利于降低所述子像素的布局难度。
如图3和图5所示，在一些实施例中，所述两个子像素驱动电路201中，两个所述第三晶体管T3包括的所述第三有源层33关于所述对称轴C对称设置。
上述设置方式有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图5，图6，图12所示，在一些实施例中，所述第一晶体管T1，所述第二晶体管T2和所述第三晶体管T3中的至少一个包括双栅结构。
示例性的，所述第一晶体管T1，所述第二晶体管T2，所述第三晶体管T3，所述发光控制晶体管T4和所述驱动晶体管T5均采用N型低温多晶硅晶体管。
上述设置所述第一晶体管T1，所述第二晶体管T2和所述第三晶体管T3包括双栅结构，有利于减少晶体管的漏电流，确保子像素驱动电路201功能正确性和工作的稳定性。
如图1，图3，图6，图7，图10，图16所示，在一些实施例中，所述子像素驱动电路201还包括存储电容Cst，所述存储电容Cst包括相对设置的第一极板Cst1和第二极板Cst2，所述第一极板Cst1位于所述基底和所述第二极板Cst2之间；所述第一极板Cst1与所述驱动晶体管T5的栅极耦接，所述第二极板Cst2分别与所述驱动晶体管T5的第二极和所述发光元件的阳极图形80耦接；所述两个子像素驱动电路201中，两个所述第一极板Cst1关于所述对称轴C对称设置；和/或，两个所述第二极板Cst2关于所述对称轴C对称设置。
示例性的，所述第一极板Cst1复用为所述驱动晶体管T5的栅极。
示例性的，所述第二极板Cst2通过所述第三导电图形66与所述驱动晶体管T5的第二极耦接。
示例性的，所述第二极板Cst2在所述基底上的正投影，与所述驱动有源层35在所述基底上的正投影至少部分交叠。
示例性的，所述第二极板Cst2在所述基底上的正投影，位于所述第一有源层31在所述基底上的正投影与所述第三有源层33在所述基底上的正投影之间。
示例性的，所述第一极板Cst1在所述基底上的正投影，位于所述第一有源层31在所述基底上的正投影与所述第三有源层33在所述基底上的正投影之间。
上述设置所述两个子像素驱动电路201中，两个所述第一极板Cst1关于所述对称轴C对称设置；和/或，两个所述第二极板Cst2关于所述对称轴C 对称设置，有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图8，图9，图10，图12，图13，图18至图21所示，在一些实施例中，所述子像素还包括异层设置的第一导电连接部60和第二导电连接部70，所述第一导电连接部60位于所述基底和所述第二导电连接部70之间，所述阳极图形80位于所述第二导电连接部70背向所述基底的一侧；
所述第二极板Cst2与所述第一导电连接部60耦接；
所述第二导电连接部70在所述基底10上的正投影，与所述第一导电连接部60在所述基底10上的正投影之间具有第一交叠区域，所述第二导电连接部70在所述基底10上的正投影，与所述阳极图形80在所述基底10上的正投影之间具有第二交叠区域；
所述第二导电连接部70通过第一过孔Via1与所述第一导电连接部60耦接，所述第一过孔Via1在所述基底10上的正投影位于所述第一交叠区域；所述第二导电连接部70通过第二过孔Via2与所述阳极图形80耦接，所述第二过孔Via2在所述基底10上的正投影位于所述第二交叠区域。
示例性的，所述第一导电连接部60分别与所述第二极板Cst2，所述第三晶体管T3的第二极和所述第二导电连接部70耦接。
示例性的，所述第一过孔Via1贯穿位于所述第一导电连接部60和所述第二导电连接部70之间的绝缘层，所述第二过孔Via2贯穿位于所述第二导电连接部70和所述阳极图形80之间的绝缘层。
上述设置所述第二极板Cst2通过所述第一导电连接部60和所述第二导电连接部70与所述阳极图形80耦接，使得所述第一过孔Via1和所述第二过孔Via2的深度均较浅，所述第一过孔Via1和所述第二过孔Via2能够错开，形成坡度较缓的台阶孔，避免了在所述第二极板Cst2和所述阳极图形80之间形成较深的过孔，有效降低了阳极图形80在所述第二过孔Via2处发生断裂的风险。
如图5和图17所示，在一些实施例中，设置所述第一导电连接部60在所述基底上的正投影的至少部分，位于所述第三有源图形在所述基底上的正投影，与所述驱动有源层35在所述基底上的正投影之间。
上述设置方式有效缩小了子像素占用的布局空间，有利于降低子像素的布局难度，提升显示基板的分辨率。
如图5所示，在一些实施例中，所述第三有源层33包括相耦接的第一部分331和第二部分332，所述第一部分331包括沿所述第一方向延伸的部分，所述第二部分332包括沿所述第二方向延伸的部分，所述第一部分331和所述第二部分332形成为L型结构；在同一个所述子像素中，所述第三有源层33和所述驱动有源层35沿第三方向排列，所述第三方向与所述第一方向和所述第二方向均相交；所述L型结构的90度夹角朝向所述驱动有源层35。
示例性的，所述第一部分331在所述基底上的正投影和所述第二部分332在所述基底上的正投影，分别与所述第三晶体管T3的栅极在所述基底上的正投影部分交叠，使所述第三晶体管T3形成为双栅结构。
示例性的，所述第一方向与所述第二方向垂直，所述所述第三方向与所述第一方向之间的夹角在30度至45度之间，可以包括端点值。
上述设置方式有效缩小了子像素占用的布局空间，有利于降低子像素的布局难度，提升显示基板的分辨率。
在一些实施例中，所述显示基板还包括设置于所述基底上的数据扇出线，所述数据扇出线与相应的数据线耦接，所述数据扇出线与所述第二导电连接部70同层同材料设置。
示例性的，所述显示基板包括多条数据扇出线，所述数据扇出线的一端与相应的数据线耦接，所述数据扇出线的另一端与驱动芯片中相应的引脚耦接，所述数据扇出线用于将所述驱动芯片提供的数据信号传输至相应的数据线。
示例性的，所述显示基板包括沿远离所述基底的方向依次层叠设置的有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层，第一源漏金属层，第一钝化层PVX1，第一平坦层PLN1，第二源漏金属层，第二钝化层PVX2，第二平坦层PLN2，阳极层，像素界定层，发光功能层，阴极层，封装结构。示例性的，所述显示基板也可以不包括所述第一钝化层PVX1和/或所述第二钝化层PVX2。
示例性的，所述第二源漏金属层包括所述数据扇出线和所述第二导电连 接部70。
示例性的，所述数据扇出线的厚度约为5500埃。
示例性的，异型设计的显示基板中，所述数据扇出线设置于所述显示区域，即采用FIA(Fanout In AA)技术。
上述设置所述第二源漏金属层包括所述数据扇出线和所述第二导电连接部70，使得所述数据扇出线与其下方的导电结构至少相隔所述第一钝化层PVX1和所述第一平坦层PLN1，从而有效降低了所述数据扇出线产生的阻容负载(RC Loading)。
更详细地说，所述显示基板经历12道构图工艺(Mask工艺)形成，具体包括：有源层的构图工艺，第一栅金属层的构图工艺，第二栅金属层的构图工艺，层间绝缘层的构图工艺，第一源漏金属层的构图工艺，第一平坦层PLN1的构图工艺，第一钝化层PVX1的构图工艺，第二源漏金属层的构图工艺，第二平坦层PLN2的构图工艺，第二钝化层PVX2的构图工艺，阳极层的构图工艺和像素界定层的构图工艺。
如图5所示，示例性的，所述有源层包括所述驱动有源层35，所述发光控制有源层34，所述第一有源层31，所述第二有源层32，所述第三有源层33和所述基准连接部36。
如图6所示，示例性的，所述第一栅金属层包括所述驱动晶体管T5的栅极，所述发光控制晶体管T4的栅极，所述第一晶体管T1的栅极，所述第二晶体管T2的栅极，所述第三晶体管T3的栅极，所述第一扫描线41，所述第二扫描线42，所述第三扫描线43，所述发光控制信号线44和所述电源连接部45。
如图7所示，示例性的，所述第二栅金属层包括所述存储电容Cst的第二极板Cst2和所述初始化信号线51。
如图8所示，示例性的，所述第一源漏金属层包括电源线VDD，数据线，基准信号线63，第一导电连接部60，第一导电图形64至第六导电图形69。
如图9所示，示例性的，所述第二源漏金属层包括第二导电连接部70和数据扇出线。
如图10所示，示例性的，所述阳极层包括阳极图形80。
如图11所示，示例性的，所述像素界定层形成像素开口81。示例性的，像素开口81为等Pitch圆弧打印设计，能够提升制作有机发光材料的打印速率，并能够提升显示基板的器件性能。
示例性的，在同一组子像素中，两个所述第一导电连接部60关于所述对称轴C对称，两个所述第一导电图形64关于所述对称轴C对称，两个所述第二导电图形65关于所述对称轴C对称，两个所述第三导电图形66关于所述对称轴C对称，两个所述第四导电图形67关于所述对称轴C对称，两个所述第五导电图形68关于所述对称轴C对称，两个所述第六导电图形69关于所述对称轴C对称，两个所述第二导电连接部关于所述对称轴C对称，两个所述阳极图形关于所述对称轴C对称，两个所述像素开口81关于所述对称轴C对称。
示例性的，沿所述第二方向相邻的两个子像素中，两个所述第一导电连接部60关于所述纵轴线对称，两个所述第一导电图形64关于所述纵轴线对称，两个所述第二导电图形65关于所述纵轴线对称，两个所述第三导电图形66关于所述纵轴线对称，两个所述第四导电图形67关于所述纵轴线对称，两个所述第五导电图形68关于所述纵轴线对称，两个所述第六导电图形69关于所述纵轴线对称，两个所述第二导电连接部关于所述纵轴线对称，两个所述阳极图形关于所述纵轴线对称，两个所述像素开口81关于所述纵轴线对称，两个所述第一极板Cst1关于所述纵轴线对称，两个所述第二极板Cst2关于所述纵轴线对称，两个所述第一有源层31关于所述纵轴线对称，两个所述第二有源层32关于所述纵轴线对称，两个所述第三有源层33关于所述纵轴线对称，两个所述发光控制有源层34关于所述纵轴线对称，两个所述驱动有源层35关于所述纵轴线对称。
需要说明，所述纵轴线位于沿所述第二方向相邻的两个子像素之间，所述纵轴线沿所述第一方向延伸。
如图1和图2所示，上述实施例提供的显示基板中，子像素驱动电路201包括驱动晶体管T5，发光控制晶体管T4，第一晶体管T1，第二晶体管T2，第三晶体管T3和存储电容Cst。
每组子像素中位于第一行的子像素和位于第二行的子像素的工作过程均 包括：复位时段P1，补偿时段P2，数据写入时段P3和发光时段P4。
第一行子像素和第二行子像素的复位时段错开，第一行子像素和第二行子像素的补偿时段部分错开，第一行子像素和第二行子像素的数据写入时段完全错开。
需要说明，在第一行子像素和第二子像素203的数据写入时段中，发光控制信号EM处于非有效电平，这样能够避免在第二子像素203写入数据信号的过程中，第一行子像素的驱动晶体管T5的第一极持续接收电源信号Vd，避免了第一行子像素的驱动晶体管T5的栅源电压下降，影响对第一子像素202中子像素驱动电路201的补偿效果。
图2中示意了第一行子像素中，第一扫描线41输入的第一扫描信号G11，第二扫描线42输入的第二扫描信号G21，以及第三扫描线43输入的第三扫描信号G31。图2中还示意了第二行子像素中，第一扫描线41输入的第一扫描信号G12，第二扫描线42输入的第二扫描信号G22，以及第三扫描线43输入的第三扫描信号G32。图2中还示意了发光控制信号EM。
如图3，图5和图11所示，在一些实施例中，所述显示基板还包括像素界定层，所述像素界定层限定出多个像素开口81，所述多个像素开口81与所述显示基板包括的多个子像素一一对应；
所述第一有源层31在所述基底上的正投影，位于对应的像素开口81在所述基底上的正投影的内部；
所述第二有源层32在所述基底上的正投影，位于对应的像素开口81在所述基底上的正投影的内部；
所述第三有源层33在所述基底上的正投影，位于所述像素界定层在所述基底上的正投影的内部；
所述发光控制有源层34在所述基底上的正投影，位于所述像素界定层在所述基底上的正投影的内部；
所述驱动有源层35在所述基底上的正投影，分别与所述像素界定层在所述基底上的正投影和对应的所述像素开口在所述基底上的正投影部分交叠。
上述设置方式有效缩小了子像素占用的布局空间，有利于降低子像素的布局难度，提升显示基板的分辨率。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
上述实施例提供的显示基板中，通过将所述多个子像素划分为多组子像素，并设置每组子像素包括的两个子像素驱动电路201复用同一个所述发光控制子电路，有效缩小了每组子像素占用的布局空间，因此，上述实施例提供的显示基板对多个子像素的布局进行了优化设计，不仅保证了显示基板能够实现高分辨率的显示，还较好的兼容了GOA(英文：Gate On Array)逻辑资源，为异型显示产品实现高分辨率GIA显示提供了技术支持。
本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元 件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种显示基板，包括：基底和设置于所述基底上的多个子像素，所述多个子像素呈阵列分布；
    所述子像素包括子像素驱动电路和发光元件，所述子像素驱动电路包括相耦接的驱动子电路和发光控制子电路；所述发光元件包括阳极图形；
    所述多个子像素划分为多组子像素，每组子像素包括沿第一方向排列的两个子像素，所述两个子像素包括的两个子像素驱动电路复用同一个所述发光控制子电路，所述发光控制子电路用于分别控制所述两个子像素中的所述驱动子电路向所述阳极图形写入驱动信号；
    所述子像素还包括数据线，所述数据线包括沿所述第一方向延伸的部分。
  2. 根据权利要求1所述的显示基板，其中，所述子像素还包括：
    发光控制信号线，所述发光控制信号线包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交；
    所述两个子像素包括的两个子像素驱动电路复用同一条所述发光控制信号线，所述发光控制信号线与所述发光控制子电路耦接，用于控制所述发光控制子电路；所述发光控制信号线在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形在所述基底上的正投影之间。
  3. 根据权利要求2所述的显示基板，其中，所述发光控制子电路包括发光控制晶体管，所述发光控制晶体管的栅极与所述发光控制信号线耦接，所述发光控制晶体管的第二极与所述驱动子电路耦接；
    所述发光控制晶体管包括发光控制有源层，所述发光控制有源层包括沿所述第二方向延伸的部分，所述发光控制有源层在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形在所述基底上的正投影之间。
  4. 根据权利要求3所述的显示基板，其中，所述子像素还包括：
    电源线，所述电源线包括沿所述第一方向延伸的部分，所述两个子像素包括的电源线相耦接；
    所述发光控制晶体管的第一极与所述电源线耦接，所述发光控制晶体管用于在所述发光控制信号线的控制下，导通或断开所述电源线与所述两个子 像素中的所述驱动子电路之间的连接。
  5. 根据权利要求4所述的显示基板，其中，所述子像素还包括：
    电源连接部，所述电源连接部包括沿所述第二方向延伸的部分；所述两个子像素包括的两个子像素驱动电路复用同一个所述电源连接部；沿所述第二方向所述电源线在所述基底上的正投影位于所述发光控制有源层在所述基底上的正投影的一侧，所述发光控制晶体管的第一极通过所述电源连接部与所述电源线耦接。
  6. 根据权利要求5所述的显示基板，其中，所述电源连接部与所述发光控制信号线同层同材料设置。
  7. 根据权利要求6所述的显示基板，其中，所述多个子像素划分为多个像素单元，所述像素单元包括沿所述第二方向排列的至少两个子像素；
    所述至少两个子像素复用同一条电源线，所述至少两个子像素包括的电源连接部依次耦接。
  8. 根据权利要求3所述的显示基板，其中，所述驱动子电路包括驱动晶体管，所述驱动晶体管的第一极与所述发光控制晶体管的第二极耦接，所述驱动晶体管的第二极与所述发光元件的阳极图形耦接；
    所述驱动晶体管包括驱动有源层；所述两个子像素驱动电路中，两个所述驱动晶体管包括的驱动有源层呈轴对称设置，对称轴沿所述第二方向延伸，所述对称轴在所述基底上的正投影，位于所述两个子像素包括的两个所述阳极图形在所述基底上的正投影之间。
  9. 根据权利要求8所述的显示基板，其中，所述对称轴在所述基底上的正投影与所述发光控制有源层在所述基底上的正投影交叠。
  10. 根据权利要求8所述的显示基板，其中，所述子像素还包括第一扫描线，所述第一扫描线包括沿所述第二方向延伸的部分；
    所述子像素驱动电路还包括第一晶体管，所述第一晶体管的栅极与所述第一扫描线耦接，所述第一晶体管的第一极与所述数据线耦接，所述第一晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第一晶体管包括第一有源层，所述第一有源层包括沿所述第二方向延伸的部分；在同一个子像素中，所述第一有源层，所述驱动有源层和所述 发光控制有源层沿所述第一方向依次排列。
  11. 根据权利要求10所述的显示基板，其中，所述两个子像素驱动电路中，两个所述第一晶体管包括的所述第一有源层关于所述对称轴对称设置。
  12. 根据权利要求10或11所述的显示基板，其中，所述多个子像素划分为多个像素单元，至少部分所述像素单元包括沿所述第二方向排列的第一子像素，第二子像素和第三子像素，所述第一子像素包括第一数据线，第二子像素包括第二数据线，第三子像素包括第三数据线；
    在第一部分像素单元中，所述第一数据线位于所述第一子像素沿所述第二方向远离所述第二子像素的一侧，所述第二数据线和所述第三数据线均位于所述第二子像素和所述第三子像素之间；所述第一子像素与所述第二子像素之间具有第一间隔区；
    在第二部分像素单元中，所述第一数据线和所述第二数据线均位于所述第一子像素和所述第二子像素之间，所述第三数据线位于所述第三子像素沿所述第二方向远离所述第二子像素的一侧；所述第二子像素与所述第三子像素之间具有第二间隔区。
  13. 根据权利要求12所述的显示基板，其中，所述多组子像素划分为沿所述第一方向排列的多行子像素组，每行子像素组包括沿所述第二方向排列的多组子像素；
    所述显示基板还包括多个栅极驱动电路布局区和多个栅极驱动走线布局区；
    所述多个栅极驱动电路布局区与所述多行子像素组一一对应，每个栅极驱动电路布局区包括第一布局区和第二布局区，沿所述第一方向，所述第一布局区位于对应的一行子像素组的第一侧，所述第二布局区位于对应的一行子像素组的第二侧；
    所述多个栅极驱动电路布局区与所述多个栅极驱动走线布局区一一对应，所述栅极驱动走线布局区包括沿所述第二方向排列的至少两个第三布局区；
    所述至少两个第三布局区中：至少一个所述第三布局区位于对应的一行子像素组中的所述第一间隔区；至少一个所述第三布局区位于对应的一行子 像素组中的所述第二间隔区。
  14. 根据权利要求10所述的显示基板，其中，所述子像素还包括基准信号线和第二扫描线，所述基准信号线包括沿所述第一方向延伸的部分，所述第二扫描线包括沿所述第二方向延伸的部分；
    所述子像素驱动电路还包括第二晶体管，所述第二晶体管的栅极与所述第二扫描线耦接，所述第二晶体管的第一极与所述基准信号线耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第二晶体管包括第二有源层，所述第二有源层包括沿所述第二方向延伸的部分；在同一个子像素中，所述第二有源层，所述第一有源层和所述发光控制有源层沿所述第一方向依次排列。
  15. 根据权利要求14所述的显示基板，其中，所述两个子像素驱动电路中，两个所述第二晶体管包括的所述第二有源层关于所述对称轴对称设置。
  16. 根据权利要求15所述的显示基板，其中，所述子像素还包括基准连接部，所述基准连接部包括沿所述第二方向延伸的部分；所述第二晶体管的第一极通过所述基准连接部与所述基准信号线耦接。
  17. 根据权利要求16所述的显示基板，其中，所述多个子像素划分为多个像素单元，所述像素单元包括沿所述第二方向排列的至少两个子像素；
    沿所述第二方向排列的相邻两个所述像素单元包括的各子像素复用一条基准信号线，所述基准信号线位于所述相邻两个所述像素单元之间，所述各子像素包括的基准连接部依次耦接。
  18. 根据权利要求16所述的显示基板，其中，在同一个子像素中，所述基准连接部在所述基底上的正投影，所述第二扫描线在所述基底上的正投影，所述第一扫描线在所述基底上的正投影，所述发光控制信号线在所述基底上的正投影沿所述第一方向依次排列。
  19. 根据权利要求14所述的显示基板，其中，所述子像素还包括初始化信号线和第三扫描线，所述初始化信号线和所述第三扫描线均包括沿所述第二方向延伸的部分；
    所述子像素驱动电路还包括第三晶体管，所述第三晶体管的栅极与所述第三扫描线耦接，所述第三晶体管的第一极与所述初始化信号线耦接，所述 第三晶体管的第二极与所述发光元件的阳极图形耦接；
    所述第三晶体管包括第三有源层；在同一个子像素中，所述第一有源层，所述第三有源层和所述发光控制有源层沿所述第一方向依次排列。
  20. 根据权利要求19所述的显示基板，其中，所述两个子像素驱动电路中，两个所述第三晶体管包括的所述第三有源层关于所述对称轴对称设置。
  21. 根据权利要求19所述的显示基板，其中，所述第一晶体管，所述第二晶体管和所述第三晶体管中的至少一个包括双栅结构。
  22. 根据权利要求19所述的显示基板，其中，所述子像素驱动电路还包括存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板位于所述基底和所述第二极板之间；所述第一极板与所述驱动晶体管的栅极耦接，所述第二极板分别与所述驱动晶体管的第二极和所述发光元件的阳极图形耦接；
    所述两个子像素驱动电路中，两个所述第一极板关于所述对称轴对称设置；和/或，两个所述第二极板关于所述对称轴对称设置。
  23. 根据权利要求22所述的显示基板，其中，
    所述子像素还包括异层设置的第一导电连接部和第二导电连接部，所述第一导电连接部位于所述基底和所述第二导电连接部之间，所述阳极图形位于所述第二导电连接部背向所述基底的一侧；
    所述第二极板与所述第一导电连接部耦接；
    所述第二导电连接部在所述基底上的正投影，与所述第一导电连接部在所述基底上的正投影之间具有第一交叠区域，所述第二导电连接部在所述基底上的正投影，与所述阳极图形在所述基底上的正投影之间具有第二交叠区域；
    所述第二导电连接部通过第一过孔与所述第一导电连接部耦接，所述第一过孔在所述基底上的正投影位于所述第一交叠区域；所述第二导电连接部通过第二过孔与所述阳极图形耦接，所述第二过孔在所述基底上的正投影位于所述第二交叠区域。
  24. 根据权利要求23所述的显示基板，其中，所述第一导电连接部在所述基底上的正投影的至少部分，位于所述第三有源图形在所述基底上的正投 影，与所述驱动有源层在所述基底上的正投影之间。
  25. 根据权利要求24所述的显示基板，其中，所述第三有源层包括相耦接的第一部分和第二部分，所述第一部分包括沿所述第一方向延伸的部分，所述第二部分包括沿所述第二方向延伸的部分，所述第一部分和所述第二部分形成为L型结构；在同一个所述子像素中，所述第三有源层和所述驱动有源层沿第三方向排列，所述第三方向与所述第一方向和所述第二方向均相交；所述L型结构的90度夹角朝向所述驱动有源层。
  26. 根据权利要求23所述的显示基板，其中，所述显示基板还包括设置于所述基底上的数据扇出线，所述数据扇出线与相应的数据线耦接，所述数据扇出线与所述第二导电连接部同层同材料设置。
  27. 根据权利要求19所述的显示基板，其中，所述显示基板还包括像素界定层，所述像素界定层限定出多个像素开口，所述多个像素开口与所述显示基板包括的多个子像素一一对应；
    所述第一有源层在所述基底上的正投影，位于对应的像素开口在所述基底上的正投影的内部；
    所述第二有源层在所述基底上的正投影，位于对应的像素开口在所述基底上的正投影的内部；
    所述第三有源层在所述基底上的正投影，位于所述像素界定层在所述基底上的正投影的内部；
    所述发光控制有源层在所述基底上的正投影，位于所述像素界定层在所述基底上的正投影的内部；
    所述驱动有源层在所述基底上的正投影，分别与所述像素界定层在所述基底上的正投影和对应的所述像素开口在所述基底上的正投影部分交叠。
  28. 一种显示装置，包括如权利要求1～27中任一项所述的显示基板。
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CN109004012A (zh) * 2018-08-03 2018-12-14 上海天马有机发光显示技术有限公司 显示面板及其显示装置
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CN111816123A (zh) * 2020-07-21 2020-10-23 合肥京东方卓印科技有限公司 显示基板及显示装置
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