WO2021258318A9 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021258318A9
WO2021258318A9 PCT/CN2020/097902 CN2020097902W WO2021258318A9 WO 2021258318 A9 WO2021258318 A9 WO 2021258318A9 CN 2020097902 W CN2020097902 W CN 2020097902W WO 2021258318 A9 WO2021258318 A9 WO 2021258318A9
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WIPO (PCT)
Prior art keywords
line pattern
signal line
transistor
sub
dummy
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PCT/CN2020/097902
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English (en)
French (fr)
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WO2021258318A1 (zh
Inventor
张波
董向丹
王俊喜
杨益祥
魏玉龙
苟结
王蓉
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/280,122 priority Critical patent/US20220045141A1/en
Priority to EP20942139.5A priority patent/EP4113612A4/en
Priority to PCT/CN2020/097902 priority patent/WO2021258318A1/zh
Priority to CN202080001076.XA priority patent/CN114586163A/zh
Publication of WO2021258318A1 publication Critical patent/WO2021258318A1/zh
Publication of WO2021258318A9 publication Critical patent/WO2021258318A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • each sub-pixel corresponds to its own sub-pixel driving circuit
  • the sub-pixel driving circuit generally includes a driving transistor, and the driving transistor can be turned on under the control of its gate to realize its corresponding sub-pixel.
  • the pixel provides a driving signal, therefore, the gate potential of the driving transistor plays a very important role in the operation of the entire sub-pixel driving circuit, and is an important factor affecting the yield and display quality of the display panel.
  • the purpose of the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display substrate including a substrate and a plurality of sub-pixels arranged in an array on the substrate; the plurality of sub-pixels include a plurality of display sub-pixels located in a display area in a display panel, and at least part of a plurality of virtual sub-pixels adjacent to the plurality of display sub-pixels;
  • the display sub-pixel includes: a display sub-pixel drive circuit, the display sub-pixel drive circuit includes a drive transistor, a first transistor and a second transistor; the gate of the drive transistor is respectively connected to the second pole of the first transistor coupled to the second pole of the second transistor;
  • the virtual subpixels include:
  • a dummy subpixel drive circuit including a dummy drive transistor, and a first conductive connection coupled to a gate of the dummy drive transistor;
  • a second conductive connection portion, the second conductive connection portion is respectively coupled to the first conductive connection portion and the first potential signal line pattern.
  • the first conductive connection portion extends along the first direction
  • the first potential signal line pattern includes a first power supply signal line pattern, and the first power supply signal line pattern includes a first portion extending along the first direction;
  • the second conductive connection portion extends along a second direction, the second direction intersects with the first direction, and the second conductive connection portion is respectively connected to the first conductive connection portion and the first power signal line The first part of the graph is coupled.
  • the first potential signal line pattern includes a first power supply signal line pattern
  • the first power supply signal line pattern includes a first part and a second part coupled to each other, and the first part extends along the first direction, the second portion extends in a second direction that intersects the first direction;
  • the first conductive connection portion extends along the first direction
  • the second conductive connection portion extends along the first direction, and the second conductive connection portion is respectively coupled to the first conductive connection portion and the second portion of the first power signal line pattern.
  • the second portions included in at least two of the dummy sub-pixels are coupled along the second direction.
  • the first part and the second part included in at least one target virtual sub-pixel form an integrated structure
  • the target virtual sub-pixel is a virtual sub-pixel located at the outermost side of the display area along the first direction.
  • the first potential signal line pattern includes a first power supply signal line pattern, and the first conductive connection portion, the second conductive connection portion, and the first power supply signal line pattern form an integrated structure.
  • the virtual sub-pixel further includes:
  • the orthographic projection of the grid on the substrate is located between the orthographic projection of the first grid line pattern on the substrate and the orthographic projection of the first light-emitting control signal line pattern on the substrate;
  • the display sub-pixels include:
  • the first grid line pattern included in at least one of the dummy sub-pixels along the second direction, and the dummy sub-pixels are located in the same row along the second direction and are in the same row as the at least one of the dummy sub-pixels.
  • the second gate line patterns included in the display sub-pixels adjacent to the pixels form an integrated structure;
  • the first light-emitting control signal line pattern included in at least one of the dummy sub-pixels along the second direction, and the dummy sub-pixels are located in the same row along the second direction and are in the same row as the at least one of the dummy sub-pixels.
  • the second light-emitting control signal line patterns included in the display sub-pixels adjacent to the dummy sub-pixels form an integrated structure.
  • the first potential signal line pattern includes a first power supply signal line pattern; the virtual sub-pixel driving circuit further includes:
  • the gate of the dummy drive transistor is multiplexed as the first plate of the first storage capacitor, and the second plate of the first storage capacitor is located on the first plate facing away from the On one side of the substrate, the orthographic projection of the second electrode plate on the substrate has an overlapping area with the orthographic projection of the first portion of the first power signal line pattern extending along the first direction on the substrate , the second plate is coupled with the first part in the overlapping region;
  • the display sub-pixels also include:
  • the second power signal line pattern including a third portion extending along the first direction
  • the display sub-pixel drive circuit further includes a second storage capacitor, the gate of the drive transistor is multiplexed as the third electrode plate of the second storage capacitor, and the fourth electrode plate of the second storage capacitor is located in the second storage capacitor.
  • the side of the third electrode plate facing away from the substrate, the orthographic projection of the fourth electrode plate on the substrate and the orthographic projection of the third part of the second power signal line pattern on the substrate have an intersection. an overlapping region, in which the fourth plate is coupled to the third portion;
  • the second polar plate included in each of the virtual sub-pixels located in the same row along the second direction, and the fourth polar plate included in each of the display sub-pixels located in the row form an integrated structure .
  • the display sub-pixels include:
  • the second power signal line pattern including a third portion extending along the first direction
  • the virtual sub-pixel further includes: a first data line pattern extending along a first direction;
  • the display sub-pixel includes a second data line pattern extending along the first direction;
  • the first data line pattern included in each of the dummy sub-pixels located in the same column along the first direction, and the second data line pattern included in each of the display sub-pixels located in the column are formed as All-in-one structure.
  • the virtual sub-pixel includes an active layer pattern, and the active layer pattern includes:
  • the first active sub-pattern and the second active sub-pattern are arranged oppositely, and both the first active sub-pattern and the second active sub-pattern extend along the first direction;
  • the second active sub-pattern is coupled, and the orthographic projection of at least part of the third active sub-pattern on the substrate overlaps the orthographic projection of the gate of the dummy drive transistor on the substrate ;
  • the orthographic projection of the portion of the first conductive connection portion away from the gate of the dummy driving transistor on the substrate does not overlap with the orthographic projection of the active layer pattern on the substrate.
  • the virtual sub-pixel further includes a first data line pattern extending along the first direction, and the orthographic projection of the second active sub-pattern on the substrate is located in the first data line pattern. between an orthographic projection on the substrate and an orthographic projection of the first active sub-pattern on the substrate;
  • the orthographic projection of the first data line pattern on the substrate does not overlap with the orthographic projection of the active layer pattern on the substrate.
  • the first potential signal line pattern includes a first power supply signal line pattern; the virtual sub-pixel also includes:
  • the dummy sub-pixel driving circuit further includes: a second dummy transistor, a fifth dummy transistor and a sixth dummy transistor;
  • the gate of the dummy driving transistor is coupled to the first power supply signal line pattern, the first pole of the dummy driving transistor is coupled to the second pole of the fifth dummy transistor, and the first pole of the dummy driving transistor is coupled to the second pole of the fifth dummy transistor.
  • a diode is coupled to the first electrode of the sixth dummy transistor;
  • the gate of the second dummy transistor is coupled to the first reset signal line pattern, the first electrode of the second dummy transistor is coupled to the first initialization signal line pattern, and the second dummy transistor is The second pole is floating;
  • the gate of the fifth dummy transistor is coupled to the first light-emitting control signal line pattern, and the first electrode of the fifth dummy transistor is coupled to the first power supply signal line pattern;
  • the gate of the sixth dummy transistor is coupled to the first light emission control signal line pattern.
  • the display sub-pixel driving circuit further includes a third conductive connection portion extending along the first direction, a first end of the third conductive connection portion is coupled to the gate of the driving transistor, and the first end of the third conductive connection portion is coupled to the gate of the driving transistor.
  • the second ends of the three conductive connection parts are respectively coupled to the second pole of the first transistor and the second pole of the second transistor.
  • the second pole of the first transistor is coupled to the second pole of the second transistor to form a common connection terminal, and the orthographic projection of the second terminal of the third conductive connection portion on the substrate overlapping with the orthographic projection of the common connection end on the substrate, where the second end of the third conductive connection part is coupled with the common connection end.
  • the display sub-pixels include: a second power signal line pattern, a second data line pattern, a second gate line pattern, a second light-emitting control signal line pattern, a second reset signal line pattern, and a third reset signal line pattern pattern, a second initialization signal line pattern, and a third initialization signal line pattern; at least part of the second power signal line pattern and the second data line pattern extend along the first direction; the second gate line pattern, all The second light emission control signal line pattern, the second reset signal line pattern, the third reset signal line pattern, the second initialization signal line pattern and the third initialization signal line pattern all extend in the second direction , the second direction intersects the first direction;
  • the display sub-pixel driving circuit further includes: a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;
  • the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor;
  • the gate of the first transistor is coupled to the second gate line pattern
  • the gate of the second transistor is coupled to the second reset signal line pattern, and the first electrode of the second transistor is coupled to the second initialization signal line pattern;
  • the gate of the fourth transistor is coupled to the second gate line pattern, the first electrode of the fourth transistor is coupled to the second data line pattern, and the second electrode of the fourth transistor is coupled to the second data line pattern.
  • the first pole of the driving transistor is coupled;
  • the gate of the fifth transistor is coupled to the second light-emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the second power signal line pattern;
  • the gate of the sixth transistor is coupled to the second light-emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the second electrode of the driving transistor.
  • the pole is coupled to the light-emitting element in the display sub-pixel;
  • the second electrode of the seventh transistor is coupled to the light-emitting element in the display sub-pixel, the gate of the seventh transistor is coupled to the third reset signal line pattern, and the first The pole is coupled to the third initialization signal line pattern.
  • first conductive connection portion and the second conductive connection portion are of an integral structure.
  • a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.
  • a third aspect of the present disclosure provides a manufacturing method of a display substrate, the manufacturing method comprising:
  • a plurality of sub-pixels arranged in an array are fabricated on a substrate; the plurality of sub-pixels include a plurality of display sub-pixels located in the display area of the display panel, and a plurality of dummy sub-pixels at least partially adjacent to the plurality of display sub-pixels ;
  • the display sub-pixel includes: a display sub-pixel drive circuit, the display sub-pixel drive circuit includes a drive transistor, a first transistor and a second transistor; the gate of the drive transistor is respectively connected to the second pole of the first transistor coupled to the second pole of the second transistor;
  • the virtual subpixels include:
  • the dummy sub-pixel drive circuit includes a dummy drive transistor, and a first conductive connection portion coupled to a gate of the dummy drive transistor;
  • a second conductive connection portion, the second conductive connection portion is respectively coupled to the first conductive connection portion and the first potential signal line pattern.
  • the first potential signal line pattern includes a first power supply signal line pattern; the step of making the first conductive connection portion, the second conductive connection portion and the first potential signal line pattern specifically includes:
  • the first conductive connection portion, the second conductive connection portion and the first power signal line pattern of an integrated structure are formed.
  • FIG. 1 is a schematic diagram of a display substrate provided by an embodiment of the present disclosure
  • Fig. 2 is the first enlarged schematic diagram of part C in Fig. 1;
  • Fig. 3 is the second enlarged schematic diagram of C part in Fig. 1;
  • FIG. 4 is a schematic diagram of a first structure of a virtual sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a first layout of a virtual sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a second structure of a virtual sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a second layout of a virtual sub-pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the layout of the active layer in FIG. 7;
  • FIG. 9 is a schematic diagram of the layout of the first gate metal layer in FIG. 7;
  • FIG. 10 is a schematic diagram of the layout of the second gate metal layer in FIG. 7;
  • FIG. 11 is a schematic diagram of the layout of the source-drain metal layer in FIG. 7;
  • FIG. 12 is a schematic diagram of a third layout of a virtual sub-pixel driving circuit provided by an embodiment of the present disclosure.
  • Figure 13a is an enlarged schematic view of part B in Figure 2;
  • Figure 13b is a schematic cross-sectional view along the direction A1A2 in Figure 13a;
  • Fig. 13c is a schematic cross-sectional view along the direction B1B2 in Fig. 13a;
  • Figure 13d is an enlarged schematic view of part C in Figure 2;
  • FIG. 14 is a schematic diagram of a first structure of a display sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 15 is a schematic diagram of a first layout of a display sub-pixel driving circuit according to an embodiment of the present disclosure
  • Fig. 16 is a schematic diagram of the active layer layout in Fig. 15;
  • FIG. 17 is a schematic diagram of the layout of the first gate metal layer in FIG. 15;
  • FIG. 18 is a schematic diagram of the layout of the second gate metal layer in FIG. 15;
  • FIG. 19 is a schematic diagram of the layout of the source-drain metal layer in FIG. 15 .
  • the display substrate provided by the present disclosure includes a display area and a non-display area located around the display area.
  • the display area includes a center portion and an edge portion.
  • the edge portion is a portion of the display area close to the boundary of the display area, and is displayed in a rectangle with rounded corners.
  • the edge part includes the parts located on the upper, lower, left and right sides of the display area, and the parts located at the four rounded corners of the display area.
  • virtual sub-pixels are set at the periphery of the normal display sub-pixels at the edge of the display area.
  • the sub-pixel will not undergo evaporation of organic light-emitting materials, that is, will not emit light. Its function is to maintain the etching uniformity with the circuit etching of the normal display pixel during the etching process, and prevent the edge display sub-pixel from being etched.
  • the uneven etching causes the line width and line spacing of the local lines to change.
  • the structure of the corresponding virtual sub-pixel driving circuit in the virtual sub-pixel is more simplified than the normal display sub-pixel driving circuit structure.
  • the dummy sub-pixels provided in the display substrate do not exist independently, and the writing of the signals is consistent with the design of the normal display sub-pixels, and the simplified dummy sub-pixel driving circuit structure in the dummy sub-pixels may
  • the stability of the dummy sub-pixels in the driving process cannot be guaranteed, so that there may be floating nodes in the dummy sub-pixel driving circuit, resulting in poor stability and poor display quality of the display substrate during operation.
  • the layout structure of the display sub-pixel and the dummy sub-pixel will be described below by taking a display sub-pixel drive circuit in which the display sub-pixel includes 7T1C (ie, seven thin film transistors and one capacitor) as an example.
  • 7T1C ie, seven thin film transistors and one capacitor
  • the dummy sub-pixel 80 includes: a first data line pattern 808 , a first gate line pattern 802 , a first light-emitting control signal line pattern 803 , a first A reset signal line pattern 805 and a first initialization signal line pattern 804; at least a portion of the first power signal line pattern 801 (eg, the first portion 8011) and the first data line pattern 808 are both along a first direction (eg, the Y direction) ) extending, the first gate line pattern 802, the first light-emitting control signal line pattern 803, the first reset signal line pattern 805 and the first initialization signal line pattern 804 are all along the second direction (eg X direction) extension.
  • the dummy sub-pixel driving circuit in the dummy sub-pixel 80 includes: a dummy driving transistor (ie, the third dummy transistor T3'), the second dummy transistor T2', the fifth dummy transistor T5', the sixth dummy transistor T6', the third dummy transistor Seven dummy transistors T7' and a first storage capacitor Cst'.
  • a dummy driving transistor ie, the third dummy transistor T3'
  • the second dummy transistor T2' the fifth dummy transistor T5'
  • the sixth dummy transistor T6' the third dummy transistor Seven dummy transistors T7'
  • a first storage capacitor Cst' a first storage capacitor
  • the second dummy transistor T2' has a double gate structure, the gate 202g' of the second dummy transistor T2' is coupled to the first reset signal line pattern 805, and the source S2' of the second dummy transistor T2' is connected to the first reset signal line pattern 805.
  • the first initialization signal line pattern 804 is coupled, and the drain D2' of the second dummy transistor T2' is floating.
  • the gate 205g' of the fifth dummy transistor T5' is coupled to the first light-emitting control signal line pattern 803, the source S5' of the fifth dummy transistor T5' is coupled to the first power signal line pattern 801, and the fifth dummy transistor T5
  • the drain D5' of ' is coupled to the source S3' of the third dummy transistor T3'.
  • the gate 206g' of the sixth dummy transistor T6' is coupled to the first light-emitting control signal line pattern 803, the source S6' of the sixth dummy transistor T6' is coupled to the drain D3' of the third dummy transistor T3', and the first The drain D6' of the six dummy transistor T6' is coupled to the anode of the light emitting element EL.
  • the gate 207g' of the seventh dummy transistor T7' is coupled to the first reset signal line pattern 805' in the next dummy sub-pixel 80 adjacent in the first direction, and the drain D7 of the seventh dummy transistor T7' ' is coupled to the anode of the light-emitting element EL, and the source S7' of the seventh dummy transistor T7' is coupled to the first initialization signal line pattern 804' in the next dummy sub-pixel 80 adjacent in the first direction connected; the cathode of the light-emitting element EL is coupled to the negative power supply signal line VSS.
  • the first plate Cst1' of the first storage capacitor Cst' is multiplexed as the gate 203g' of the third dummy transistor T3', and the second plate Cst2' of the first storage capacitor Cst' is coupled to the first power signal Line pattern 801 is coupled.
  • the dummy sub-pixel driving circuit does not include the first dummy transistor T1 ′ and the fourth dummy transistor T4 ′, the data signal provided by the first data line pattern 808 Writing to the N1 node cannot be performed through the fourth dummy transistor T4', the third dummy transistor T3' and the first dummy transistor T1' in sequence, resulting in the N1 node being in a floating state. It should be noted that the gate of the dummy driving transistor is coupled to the N1 node.
  • the N1 node and the first power signal line pattern 801 are coupled through the first storage capacitor Cst' and other parasitic capacitances in the dummy sub-pixel driving circuit, so that N1
  • the variation of the node voltage will cause the variation of the voltage on the first power signal line pattern 801 .
  • the voltage change on the first power supply signal line pattern 801 will affect the power supply change on the second power supply signal line pattern 901 in the display sub-pixel 90, and the voltage VDD on the second power supply signal line pattern 901 will affect the current
  • the current flowing through the light-emitting element of the display sub-pixel 90 affects the normal light emission of the light-emitting element in the display sub-pixel 90, resulting in the phenomenon of uneven display brightness locally on the display substrate.
  • the voltage of the N1 node in the virtual sub-pixel drive circuit plays a very important role in the operation of the entire display sub-pixel drive circuit, and is an important factor affecting the performance of the display sub-pixel drive circuit; Design and improvement to improve the yield of display products and enhance the competitiveness of display products have become the current focus.
  • an embodiment of the present disclosure provides a display substrate 1 , which includes a substrate and a plurality of sub-pixels arranged in an array on the substrate; the plurality of sub-pixels include a plurality of display sub-pixels 90 located in the display area of the display panel, and a plurality of dummy sub-pixels 80 at least partially adjacent to the plurality of display sub-pixels;
  • the display sub-pixel 90 includes: a display sub-pixel drive circuit, the display sub-pixel drive circuit includes a drive transistor (ie a third transistor T3), a first transistor T1 and a second transistor T2; the gates of the drive transistors are respectively is coupled to the second pole (ie the drain D1) of the first transistor T1 and the second pole (ie the drain D2) of the second transistor T2;
  • a drive transistor ie a third transistor T3
  • the gates of the drive transistors are respectively is coupled to the second pole (ie the drain D1) of the first transistor T1 and the second pole (ie the drain D2) of the second transistor T2;
  • the dummy sub-pixel 80 includes: a first potential signal line pattern, a dummy sub-pixel drive circuit and a second conductive connection part 8062; the dummy sub-pixel drive circuit includes a dummy drive transistor, and a gate connected to the dummy drive transistor
  • the coupled first conductive connection portion 8061; the second conductive connection portion 8062 is respectively coupled to the first conductive connection portion 8061 and the first potential signal line pattern.
  • the plurality of dummy sub-pixels 80 included in the display substrate 1 may be distributed along the boundary of the plurality of display sub-pixels 90, and at a certain boundary, along the first direction and the second A plurality of virtual sub-pixels 80 may be distributed in both directions.
  • the plurality of dummy sub-pixels 80 included in the display substrate 1 may be distributed along the boundary of the plurality of display sub-pixels 90, and at a certain boundary, along the first direction and the second A plurality of virtual sub-pixels 80 may be distributed in both directions.
  • the dummy sub-pixel driving circuit includes the dummy driving transistor and the first conductive connection part 8061, and one end of the first conductive connection part 8061 is coupled to the gate of the dummy driving transistor Then, the potential on the first conductive connection portion 8061 is the potential of the N1 node.
  • the dummy sub-pixel 80 further includes the first potential signal line pattern and the second conductive connection portion 8062.
  • one end of the second conductive connection portion 8062 is connected to the first conductive connection portion 8062.
  • the other end of the conductive connection portion 8061 is coupled, and the other end of the second conductive connection portion 8062 is coupled to the first potential signal line pattern, so that the N1 node is kept connected to the first potential signal line graph the same potential.
  • Coupled includes direct electrical connection and indirect electrical connection through a conductive layer.
  • the first conductive connection portion 8061 and the second conductive connection portion 8062 may be formed as an integral structure. It is worth noting that the one-piece structure includes: the first conductive connection portion 8061 and the second conductive connection portion 8062 that are simultaneously formed in contact with the same material through a single patterning process; or, the first conductive connection portion 8061 Direct contact with the second conductive connection portion 8062 is possible.
  • the first conductive connection portion 8061 extends in a first direction
  • the second conductive connection portion 8062 extends in a second direction
  • the first conductive connection portion 8061 extends in a direction perpendicular to the first direction
  • the width of the upper part is smaller than the width of the second conductive connection part 8062 in the direction perpendicular to the second direction.
  • the first conductive connection portion 8061 extends along a first direction
  • the second conductive connection portion 8062 extends along a second direction
  • the first conductive connection portion 8061 extends in a direction perpendicular to the first direction.
  • the width is equal to the width of the second conductive connection portion 8062 in the direction perpendicular to the second direction.
  • the orthographic projection of the first conductive connection portion 8061 on the substrate and the orthographic projection of the first grid line pattern 802 on the substrate have a first overlapping area, and the first conductive connection portion
  • the width of the portion of the first overlapping region 8061 perpendicular to the first direction is smaller than the width of the rest of the first conductive connection portion 8061 perpendicular to the first direction.
  • the orthographic projection of the second conductive connection portion 8062 on the substrate and the orthographic projection of the first grid line pattern 802 on the substrate have a second overlapping area, and the second conductive connection portion
  • the width of the portion of the second overlapping region 8062 in the direction perpendicular to the second direction is smaller than the width of the rest of the second conductive connection portion 8062 in the direction perpendicular to the second direction.
  • the orthographic projection of the first power signal line pattern 801 on the substrate and the orthographic projection of the first grid line pattern 802 on the substrate have a third overlapping area, and the first power signal
  • the width of the portion of the line pattern 801 located in the third overlapping region perpendicular to the first direction is smaller than the width of the rest of the first power signal line pattern 801 perpendicular to the first direction.
  • the above arrangement can better reduce the gap between the first gate line pattern 802 and the first conductive connection portion 8061 , the second conductive connection portion 8062 and/or the first power signal line pattern 801 . overlapping area, so as to better reduce the load of the first gate line pattern 802 .
  • first conductive connection portion 8061 and the second conductive connection portion 8062 are disposed in different layers.
  • the first conductive connection portion 8061 and the first power signal line pattern 801 are disposed in the same layer, and the first conductive connection portion 8061 and the second conductive connection portion 8062 are disposed in different layers.
  • the first potential signal line pattern includes a first initialization signal line pattern
  • one end of the second conductive connection part 8062 is coupled to the other end of the first conductive connection part 8061, and the second conductive connection part 8061
  • the other end of the connection part 8062 is coupled to the first initialization signal line pattern, so that the N1 node can be kept at the same potential as the first initialization signal line pattern.
  • the first potential signal line pattern includes a first power supply signal line pattern 801.
  • one end of the second conductive connection portion 8062 is connected to the first conductive connection portion 8061. The other end is coupled, and the other end of the second conductive connection part 8062 is coupled with the first power signal line pattern 801, so that the N1 node is kept the same as the first power signal line pattern 801 potential.
  • the first conductive connection portion 8061 is coupled with the first potential signal line pattern connection, so that the N1 node in the virtual sub-pixel driving circuit always maintains the same stable potential as the first potential signal line pattern, thereby avoiding the local display brightness difference of the display substrate 1 caused by the floating connection of the N1 node. uniform phenomenon.
  • the first potential signal line pattern includes a first power signal line pattern 801, and the first conductive connection portion 8061 extends along a first direction; the first power signal line pattern 801 includes a first power signal line pattern 801 along the The first portion 8011 extending in the first direction; the second conductive connection portion 8062 extends along the second direction, the second direction intersects the first direction, and the second conductive connection portion 8062 is respectively connected to the first direction
  • the conductive connection portion 8061 is coupled to the first portion 8011 of the first power signal line pattern 801 .
  • the first conductive connection portion 8061 can be arranged to extend along the first direction, the first portion 8011 in the first power signal line pattern 801 extends along the first direction, and the first conductive connection portion 8061 and the first power signal line pattern 801 are arranged along the second direction.
  • the second conductive connection portion 8062 can be arranged to extend along the second direction, and the orthographic projection of the second conductive connection portion 8062 on the substrate is located at the position of the first conductive connection portion 8061 on the substrate. Between the orthographic projection and the orthographic projection of the first portion 8011 of the first power signal line pattern 801 on the substrate, one end of the second conductive connection portion 8062 close to the first conductive connection portion 8061 and the The first conductive connection portion 8061 is coupled, and one end of the second conductive connection portion 8062 close to the first portion 8011 is coupled to the first power signal line pattern 801 .
  • the first potential signal line pattern includes a first power supply signal line pattern 801
  • the first power supply signal line pattern 801 includes a first portion 8011 and a second portion 8012 that are coupled to each other.
  • the first portion 8011 extends along the first direction
  • the second portion 8012 extends along the second direction
  • the second direction intersects the first direction
  • the first conductive connection portion 8061 extends along the extending in the first direction
  • the second conductive connection portion 8062 extends along the first direction
  • the second conductive connection portion 8062 is respectively connected to the first conductive connection portion 8061 and the first power signal line pattern 801
  • the second portion 8012 is coupled.
  • the first power signal line pattern 801 may specifically include a first portion 8011 and a second portion 8012 that are coupled to each other.
  • the first power signal line pattern 801 in this structure has a large area and can be well to reduce the voltage drop generated on the first power signal line pattern 801 .
  • the second portion 8012 of the power signal line pattern can be arranged to extend along the second direction, the first conductive connection portion 8061 and the second conductive connection portion 8062 both extend along the first direction, and the The orthographic projection of the second conductive connection portion 8062 on the substrate is located at the orthographic projection of the first conductive connection portion 8061 on the substrate, and the second portion 8012 of the first power signal line pattern 801 is located on the substrate. Between the orthographic projections on the substrate, one end of the second conductive connection part 8062 close to the first conductive connection part 8061 is coupled to the first conductive connection part 8061, and the second conductive connection part 8062 is close to the One end of the second portion 8012 is coupled to the second portion 8012 .
  • the first direction can be selected as the Y direction
  • the second direction can be selected as the X direction
  • the second conductive connection portion 8062 can be minimized
  • the layout space occupied by the 8062 can better reduce the layout space occupied by the virtual sub-pixels 80 as a whole, which is more conducive to improving the resolution of the display substrate.
  • At least two of the second portions 8012 included in the dummy sub-pixels 80 are coupled along the second direction.
  • the plurality of sub-pixels included in the display substrate are distributed in an array and can be divided into multi-row sub-pixels and multi-column sub-pixels, the multi-row sub-pixels are arranged in sequence along the first direction, and each row of sub-pixels is arranged in sequence.
  • Each of them includes a plurality of sub-pixels arranged in sequence along the second direction, and the plurality of sub-pixels includes a virtual sub-pixel 80 located in an edge portion and a display sub-pixel 90 located in a central portion.
  • the plurality of columns of sub-pixels are arranged in sequence along the second direction, and each column of sub-pixels includes a plurality of sub-pixels arranged in sequence along the first direction.
  • Subpixels 90 are displayed.
  • the second portions 8012 included in each of the dummy sub-pixels 80 located in the same row along the second direction are coupled in sequence.
  • the above-mentioned coupling of at least two of the second portions 8012 included in the dummy sub-pixels 80 along the second direction enables the first power line pattern of at least a portion of the dummy sub-pixels 80 included in the display substrate to be able to It is formed into a mesh structure with a larger area, which is more conducive to reducing the voltage drop of the first power signal line pattern 801, thereby better improving the display quality of the display substrate.
  • the dummy sub-pixels 80 coupled together along the second direction are located on the same side of the display substrate.
  • the dummy sub-pixels 80 coupled together along the second direction are located on the same side of the display substrate.
  • the dummy sub-pixels 80 coupled together along the second direction are coupled in sequence.
  • the first part 8011 and the second part 8012 included in at least one target dummy sub-pixel 80 ′ form an integrated structure; the target dummy sub-pixel 80 ′ is an edge
  • the first direction is located at the outermost virtual sub-pixel 80 of the display area.
  • the target dummy sub-pixels 80' can be formed into an integrated structure.
  • the length of the first data line pattern 808 included in the sub-pixel 80 ′ is shortened along the first direction to avoid a short circuit between the first data line pattern 808 and the second portion 8012 .
  • the first part 8011 and the second part 8012 included in each target dummy sub-pixel 80' are formed as an integral structure.
  • the first portion 8011 and the second portion 8012 included in the target dummy sub-pixels 80 ′ located in the same row along the second direction are both formed as an integral structure.
  • the target dummy sub-pixel 80' may not include the first initialization signal line pattern 804, the first reset signal line pattern 805 and the second dummy transistor T2'.
  • the first potential signal line pattern includes a first power supply signal line pattern 801 , the first conductive connection part 8061 , the second conductive connection part 8062 and the The first power supply signal line pattern 801 is formed in an integrated structure.
  • the first conductive connection part 8061, the second conductive connection part 8062 and the first power signal line pattern 801 are formed into an integrated structure, so that the first conductive connection part 8061, the second conductive connection part 8062 and the first power signal line pattern 801 can be formed simultaneously in one patterning process, thereby better simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.
  • first conductive connection portion 8061, the second conductive connection portion 8062 and the first power signal line pattern 801 can all be fabricated by using the first source-drain metal layer in the display substrate.
  • the virtual sub-pixel 80 further includes:
  • the specific layout positions of the second conductive connection portion 8062 are various.
  • the orthographic projection of the first grid line pattern 802 on the substrate can be set, located in the second conductive connection portion between the orthographic projection of 8062 on the substrate and the orthographic projection of the first light-emitting control signal line pattern 803 on the substrate; so that the second conductive connection portion 8062 can be located on the first grid line pattern 802 A side away from the first light-emitting control signal line pattern 803 and the dummy driving transistor makes the second conductive connection part 8062 have a larger layout space, and can better avoid the second conductive connection part 8062 A short circuit occurs with other conductive structures except the first conductive connection portion 8061 and the first power signal line pattern 801, thereby better improving the stability of the display substrate.
  • the display sub-pixel 90 includes:
  • the first grid line pattern 802 included in at least one of the dummy sub-pixels 80 along the second direction is located in the same row as the dummy sub-pixel along the second direction, and is in the same row as the at least one of the dummy sub-pixels.
  • the second gate line patterns 902 included in the display sub-pixels 90 adjacent to the dummy sub-pixels 80 form an integrated structure;
  • the first light-emitting control signal line pattern 803 included in at least one of the dummy sub-pixels 80 along the second direction is located in the same row as the dummy sub-pixel along the second direction, and is in the same row as the at least one dummy sub-pixel along the second direction.
  • the second light-emitting control signal line patterns 903 included in the display sub-pixels 90 adjacent to the dummy sub-pixels form an integrated structure.
  • the display sub-pixel 90 includes the second grid line pattern 902 and the second light-emitting control signal line pattern 903 , and the second grid line pattern 902 is along the second light-emitting control signal line pattern 903 .
  • the first directions are opposite to each other, and at least part of the second gate line patterns 902 extend along the second direction.
  • the first grid line pattern 802 included in each of the virtual sub-pixels 80 located in the same row along the second direction may be , and the second grid line patterns 902 included in each of the display sub-pixels 90 located in this row are laid out on the same straight line; similarly, each of the virtual sub-pixels located in the same row along the second direction can be arranged
  • the first light emission control signal line pattern 803 included in the pixel 80 and the second light emission control signal line pattern 903 included in each of the display sub-pixels 90 located in the row are arranged on the same straight line.
  • the first grid line pattern 802 included in each of the dummy sub-pixels 80 located in the same row along the second direction, and the The second gate line patterns 902 are coupled in sequence and form an integrated structure;
  • the first light emission control signal line pattern 803 included in each of the dummy sub-pixels 80 in the same row along the second direction, and the second light-emitting control signal line pattern 803 included in each of the display sub-pixels 90 in the row The light-emitting control signal line patterns 903 are coupled in sequence and form an integrated structure.
  • first grid line pattern 802, the first light emission control signal line pattern 803, the second grid line pattern 902 and the second light emission control signal line pattern 903 can also be made of the same layer and the same material
  • the setting is such that all the first gate line patterns 802, all the first light emission control signal line patterns 803, all the second gate line patterns 902, and all the second light emission control signal lines in the display substrate All of the patterns 903 can be simultaneously formed through a single patterning process, thereby better simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.
  • the first potential signal line pattern includes a first power supply signal line pattern 801 ; the dummy sub-pixel driving circuit further includes:
  • the first storage capacitor Cst', the gate of the dummy driving transistor is multiplexed as the first plate Cst1' of the first storage capacitor Cst', and the second plate Cst2' of the first storage capacitor Cst' is located in the The side of the first pole plate Cst1 ′ facing away from the substrate, the orthographic projection of the second pole plate Cst2 ′ on the substrate, and the first power signal line pattern 801 extend along the first direction
  • the orthographic projection of the first portion 8011 on the substrate has an overlapping area in which the second plate is coupled to the first portion 8011;
  • the display sub-pixel 90 further includes:
  • the second power signal line pattern 901 includes a third portion extending along the first direction;
  • the display sub-pixel drive circuit further includes a drive transistor and a second storage capacitor Cst, the gate of the drive transistor is multiplexed as the third plate Cst1 of the second storage capacitor Cst, and the second storage capacitor Cst
  • the fourth pole plate Cst2 is located on the side of the third pole plate Cst1 facing away from the substrate.
  • the orthographic projection of the fourth pole plate Cst2 on the substrate is the same as the third pole of the second power signal line pattern 901.
  • the orthographic projection of part on the substrate has an overlapping area, and the fourth plate Cst2 is coupled to the third part in the overlapping area;
  • the second electrode plate Cst2 included in each of the dummy sub-pixels 80 located in the same row along the second direction, and the fourth electrode plate Cst2 included in each of the display sub-pixels 90 located in the row form a single structure.
  • the dummy sub-pixel drive circuit further includes a first storage capacitor
  • the display sub-pixel drive circuit further includes a second storage capacitor
  • the second plate of the first storage capacitor and the second storage capacitor The fourth electrode plate can be set in the same layer and the same material, so that all the second electrode plates of the first storage capacitor and the fourth electrode plate of the second storage capacitor included in the display substrate can be patterned at the same time. It is formed at the same time in the process, thereby better simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.
  • the above-mentioned setting is positioned along the second direction in the second polar plate included in each of the virtual sub-pixels 80 in the same row, and the fourth polar plate included in each of the display sub-pixels 90 in the row.
  • Forming an integrated structure can minimize the layout space occupied by the second electrode plate and the fourth electrode plate, which is more conducive to the development trend of high-resolution display substrates.
  • the display sub-pixel 90 includes: a second power supply signal line pattern 901 , the second power supply signal line pattern 901 includes a third portion extending in the first direction;
  • the third portion of the second power signal line pattern 901 is formed as an integral structure.
  • the above arrangement minimizes the layout space occupied by the first power supply signal line pattern 801 and the second power supply signal line pattern 901 , which is more conducive to the development trend of high-resolution display substrates. Moreover, all the first power supply signal line patterns 801 included in the dummy sub-pixel 80 and all the second power supply signal line patterns 901 included in the display sub-pixel 90 can be simultaneously formed through one patterning process, so that it is better The manufacturing process of the display substrate is simplified, and the manufacturing cost of the display substrate is reduced.
  • the virtual sub-pixel 80 further includes:
  • the first light-emitting control signal line pattern 803, the first initialization signal line pattern 804 and the first reset signal line pattern 805 are arranged in sequence;
  • the display sub-pixel 90 further includes: a second initialization signal line pattern 9041, a third initialization signal line pattern 9042, a second reset signal line pattern 9051 and a third reset signal line pattern 9052 all extending along the second direction;
  • the first initialization signal line pattern 804 included in each of the dummy sub-pixels 80 in the same row along the second direction, and the second initialization included in each of the display sub-pixels 90 in the row The signal line patterns 9041 are coupled in sequence and form an integrated structure;
  • the first reset signal line pattern 805 included in each of the dummy sub-pixels 80 in the same row along the second direction, and the second reset included in each of the display sub-pixels 90 in the row The signal line patterns 9051 are coupled in sequence and form an integral structure.
  • the second initialization signal line pattern 9041, the second reset signal line pattern 9051, the third initialization signal line pattern 9042 and the third reset signal line may be sequentially arranged along the first direction.
  • the two initialization signal line patterns 9041 are sequentially coupled to form an integrated structure; and the first reset signal line pattern 805 included in each of the dummy sub-pixels 80 located in the same row along the second direction, and the first reset signal line pattern 805 located in the same row along the second direction
  • the second reset signal line patterns 9051 included in each of the display sub-pixels 90 in the row are coupled in sequence and form an integrated structure; this not only effectively reduces the layout space occupied by the dummy sub-pixels 80 and the display sub-pixels 90 , the first initialization signal line pattern 804 and the second initialization signal line pattern 9041 can be simultaneously formed by one patterning process; and the first reset signal line pattern 805 and the second reset signal line pattern 805 can be simultaneously formed by one patterning process Signal line pattern 9051
  • the second initialization signal line pattern 9041 and the third initialization signal line pattern 9042 are provided with the same layer and the same material, and can be formed simultaneously in the same patterning process; the second initialization signal line pattern 9042 The reset signal line pattern 9051 and the third reset signal line pattern 9052 are provided in the same layer and with the same material, and can be formed simultaneously in the same patterning process.
  • the dummy sub-pixel 80 further includes: a first data line pattern 808 extending along a first direction; the display sub-pixel 90 includes a first data line pattern extending along the first direction The second data line pattern 908; the first data line pattern 808 included in each of the virtual sub-pixels 80 located in the same column along the first direction, and each of the display sub-pixels 90 located in the column include The second data line pattern 908 is formed into an integrated structure.
  • the first data line pattern 808 included in each of the dummy sub-pixels 80 located in the same column along the first direction and the first data line pattern 808 included in each of the display sub-pixels 90 located in the column are set as described above.
  • the second data line pattern 908 is formed into an integrated structure, so that the layout space occupied by the first data line pattern 808 and the second data line pattern 908 is minimized, which is more conducive to the development trend of high resolution of display substrates.
  • all the first data line patterns 808 included in the dummy sub-pixels 80 and all the second data line patterns 908 included in the display sub-pixels 90 can be simultaneously formed through one patterning process, so as to be more simplified
  • the manufacturing process of the display substrate is improved, and the manufacturing cost of the display substrate is reduced.
  • the virtual sub-pixel 80 includes an active layer pattern, and the active layer pattern includes:
  • a third active sub-pattern 8073 is disposed between the first active sub-pattern 8071 and the second active sub-pattern 8072, and both ends of the third active sub-pattern 8073 are connected to the first active sub-pattern 8073.
  • the source sub-pattern 8071 is coupled to the second active sub-pattern 8072, and the orthographic projection of at least part of the third active sub-pattern 8073 on the substrate is connected to the gate of the dummy drive transistor in the orthographic overlap on the base;
  • the orthographic projection of the portion of the first conductive connection portion 8061 away from the gate of the dummy driving transistor on the substrate is different from the orthographic projection of the active layer pattern on the substrate. overlap.
  • setting the active layer pattern includes: the first active sub-pattern 8071, the second active layer pattern The sub-pattern 8072 and the third active sub-pattern 8073; this arrangement makes the orthographic projection of the first conductive connection portion 8061 on the substrate, located on the substrate of the first active sub-pattern 8071 between the orthographic projection on the substrate and the orthographic projection of the second active sub-pattern 8072 on the substrate; the positive side of the first conductive connection portion 8061 coupled with the dummy driving transistor is on the substrate The projection overlaps with the orthographic projection of the third active sub-pattern 8073 on the substrate; the orthographic projection of the portion of the first conductive connection portion 8061 away from the gate of the dummy driving transistor on the substrate , which does not overlap with the orthographic projection of the active layer pattern on the substrate.
  • the above setting method simplifies the structure of the active layer graphics included in the virtual sub-pixel 80, effectively reduces the layout space occupied by the active layer graphics, thereby better reducing the virtual sub-pixel 80 in the edge area. layout difficulty.
  • the dummy sub-pixel 80 further includes a first data line pattern 808 extending along the first direction, and the second active sub-pattern 8072 is in the the orthographic projection on the substrate, located between the orthographic projection of the first data line pattern 808 on the substrate and the orthographic projection of the first active sub-pattern 8071 on the substrate;
  • the orthographic projection of the first data line pattern 808 on the substrate does not overlap with the orthographic projection of the active layer pattern on the substrate.
  • the orthographic projection of the portion of the first power signal line pattern 801 extending along the first direction on the substrate can cover the second active sub-pattern At least part of the orthographic projection of 8072 on the substrate, the first data line pattern 808 and the first power signal line pattern 801 are spaced apart, and the orthographic projection of the first data line pattern 808 on the substrate It does not overlap with the orthographic projection of the active layer pattern on the substrate, and does not provide data signals for the dummy sub-pixel driving circuit.
  • the above setting method makes the first data line pattern 808 not The dummy sub-pixel 80 is provided with a data signal, thereby avoiding the problem that the dummy sub-pixel driving circuit operates abnormally due to receiving the data signal, which affects the stability of the operation of the display substrate.
  • the display sub-pixel driving circuit further includes a third conductive connection portion 8063 extending along the first direction, and the first end of the third conductive connection portion 8063 is connected to the The gate of the driving transistor (ie, the gate 203g of the third transistor T3) is coupled, and the second end of the third conductive connection part 8063 is respectively connected to the second pole of the first transistor T1 and the second pole of the second transistor T1.
  • the second pole of the transistor T2 is coupled.
  • the second pole of the first transistor T1 is coupled to the second pole of the second transistor T2 to form a common connection terminal (located at the N1 node in FIG. 15 ) position nearby), the orthographic projection of the second end of the third conductive connection portion 8063 on the substrate overlaps with the orthographic projection of the common connection end on the substrate, where the first The second end of the three conductive connection parts 8063 is coupled to the common connection end.
  • the display sub-pixel 90 includes: a second power signal line pattern 901 , a second data line pattern 908 , a second gate line pattern 902 , and a second light-emitting control signal Line pattern 903, second reset signal line pattern 9051, third reset signal line pattern 9052, second initialization signal line pattern 9041 and third initialization signal line pattern 9042; at least part of and all of the second power signal line pattern 901.
  • the second data line pattern 908 extends along the first direction;
  • the pattern 9052, the second initialization signal line pattern 9041 and the third initialization signal line pattern 9042 all extend along a second direction, and the second direction intersects the first direction;
  • the display sub-pixel 90 further includes a display sub-pixel drive circuit, the display sub-pixel drive circuit includes: a drive transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to the second electrode of the fifth transistor.
  • the first pole of the first transistor is coupled;
  • the gate of the first transistor is coupled to the second gate line pattern 902;
  • the gate of the second transistor is coupled to the second reset signal line pattern 9051, the first electrode of the second transistor is coupled to the second initialization signal line pattern 9041, and the first electrode of the second transistor is coupled to the second reset signal line pattern 9041.
  • a diode is coupled to the gate of the drive transistor;
  • the gate of the fourth transistor is coupled to the second gate line pattern 902, the first electrode of the fourth transistor is coupled to the second data line pattern 908, and the second electrode of the fourth transistor coupled to the first pole of the driving transistor;
  • the gate of the fifth transistor is coupled to the second light-emitting control signal line pattern 903, and the first electrode of the fifth transistor is coupled to the second power signal line pattern 901;
  • the gate of the sixth transistor is coupled to the second light-emitting control signal line pattern 903, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor.
  • the diode is coupled to the light-emitting element in the display sub-pixel 90;
  • the second pole of the seventh transistor is coupled to the light-emitting element in the display sub-pixel 90, the gate of the seventh transistor is coupled to the third reset signal line pattern 9052, and the seventh transistor The first pole is coupled to the third initialization signal line pattern 9042 .
  • each transistor included in the display sub-pixel driving circuit adopts P-type transistors.
  • the gate 201g of a transistor T1 is coupled to the second gate line pattern 902, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3 (ie, the driving transistor), and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 has a double gate structure, the gate 202g of the second transistor T2 is coupled to the second reset signal line pattern 9051, the source S2 of the second transistor T2 is coupled to the second initialization signal line pattern 9041, and the first The drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.
  • the gate 204g of the fourth transistor T4 is coupled to the second gate line pattern 902, the source S4 of the fourth transistor T4 is coupled to the second data line pattern 908, and the drain D4 of the fourth transistor T4 is coupled to the third transistor The source S3 of T3 is coupled.
  • the gate 205g of the fifth transistor T5 is coupled to the second light-emitting control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the second power signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the third power supply signal line pattern 901.
  • the source S3 of the transistor T3 is coupled.
  • the gate 206g of the sixth transistor T6 is coupled to the second light-emitting control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the light-emitting The anode of the element EL is coupled.
  • the gate 207g of the seventh transistor T7 is coupled to the third reset signal line pattern 9052, the drain D7 of the seventh transistor T7 is coupled to the anode of the light-emitting element EL, and the source S7 of the seventh transistor T7 is coupled to the The third initialization signal line pattern 9042 is coupled.
  • the third plate Cst1 of the second storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3 , and the fourth plate Cst2 of the second storage capacitor Cst is coupled to the second power signal line pattern 901 .
  • each working cycle includes a first reset period P1, a write compensation period P2, a second reset period P3 and a light-emitting period P4.
  • the second reset signal input from the second reset signal line pattern 9051 is at an active level, the second transistor T2 is turned on, and the initialization signal transmitted by the second initialization signal line pattern 9041 is turned on. It is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared to zero, and the gate 203g of the third transistor T3 is reset.
  • the second reset signal is at an inactive level
  • the second transistor T2 is turned off
  • the gate scan signal input from the second gate line pattern 902 is at an active level, which controls the first transistor T1 and the fourth transistor T1 and the fourth transistor T1.
  • the transistor T4 is turned on, and the second data line pattern 908 writes a data signal, which is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4.
  • the first transistor T1 and the fourth transistor T4 are turned on, so that the The third transistor T3 is formed as a diode structure, so the first transistor T1, the third transistor T3 and the fourth transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the third transistor T3 can be controlled.
  • the potential of the gate 203g of the third transistor T3 finally reaches Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the gate scan signal is at an inactive level
  • the first transistor T1 and the fourth transistor T4 are both turned off
  • the third reset signal input from the third reset signal line pattern 9052 is at an active level
  • the seventh transistor T7 is controlled to be turned on
  • the initialization signal transmitted by the third initialization signal line pattern 9042 is input to the anode of the light-emitting element EL
  • the light-emitting element EL is controlled not to emit light.
  • the light-emitting control signal written by the second light-emitting control signal line pattern 903 is at an active level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the second power-supply signal line pattern 901 input to the source S3 of the third transistor T3, at the same time, since the gate 203g of the third transistor T3 is kept at Vdata+Vth, the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD , where VDD is the voltage value corresponding to the power supply signal, and the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL to drive the corresponding light-emitting element EL to emit light.
  • VDD is the voltage value corresponding to the power supply signal
  • each film layer corresponding to the display sub-pixel driving circuit is as follows:
  • the first source-drain metal layer; and the source-drain metal layer is also provided with an inorganic insulating layer, a flat layer, an anode and other film layers.
  • the inorganic layer can be made of inorganic materials such as silicon nitride and silicon oxide; the organic layer, such as the flat layer, the pixel defining layer, etc., can be made of organic materials such as polyimide, which is not limited in the present disclosure .
  • the active film layer is used to form the channel region (eg: 101pg ⁇ 107pg), the source electrode formation region (eg: 101ps ⁇ 107ps) and the drain electrode formation region ( For example: 101pd ⁇ 107pd), due to the doping effect of the active film layer corresponding to the source electrode formation area and the drain formation area, the conductivity will be better than that of the active film layer corresponding to the channel area; the active film layer can be made of amorphous Silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active film layer corresponding to the source electrode formation region and the drain electrode formation region can be directly used as the corresponding source electrode or drain electrode, or a metal material can also be used to make a metal material in contact with the source electrode formation region.
  • a metal material is used to make the drain electrode in contact with the drain formation region.
  • the first gate metal layer is used to form gates (eg, 201g-207g) of the transistors in the display sub-pixel driving circuit, as well as the second gate line pattern 902 and the second light-emitting control signal included in the display substrate.
  • the second gate metal layer is used to form the fourth electrode plate Cst2 of the second storage capacitor Cst, and the second initialization signal line pattern 9041 and the third initialization signal line pattern 9042 included in the display substrate.
  • the first source-drain metal layer is used to form the source (eg: S1 - S7 ) and the drain (eg: D1 - D7 ) of each transistor in the display sub-pixel driving circuit, and
  • the display substrate includes a second data line pattern 908, a second power signal line pattern 901 and some conductive connection parts.
  • the gate electrode 201g of the first transistor T1 covers the first channel region 101pg, the source electrode S1 of the first transistor T1 is located in the first source electrode formation region 101ps, and the first transistor T1 is located in the first source electrode formation region 101ps.
  • the drain D1 of T1 is located in the first drain formation region 101pd.
  • the gate electrode 202g of the second transistor T2 covers the second channel region 102pg, the source electrode S2 of the second transistor T2 is located in the second source electrode formation region 102ps, and the drain electrode D2 of the second transistor T2 is located in the second drain electrode formation region 102pd.
  • the gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.
  • the gate electrode 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source electrode S4 of the fourth transistor T4 is located in the fourth source electrode formation region 104ps, and the drain electrode D4 of the fourth transistor T4 is located in the fourth drain electrode formation region 104pd.
  • the gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.
  • the gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.
  • the gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.
  • the gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.
  • the plurality of display sub-pixels 90 included may be distributed in an array, and the plurality of display sub-pixels 90 may be divided into a plurality of rows of display sub-pixels 90 and a plurality of columns of display sub-pixels 90, each row
  • Each of the display sub-pixels 90 includes a plurality of display sub-pixels 90 arranged along a second direction
  • each column of display sub-pixels 90 includes a plurality of display sub-pixels 90 arranged along a first direction. directions intersect.
  • the third reset signal line pattern 9052 included in one row of display sub-pixels 90 can be multiplexed into the second reset signal line pattern 9051 included in the next adjacent row of display sub-pixels 90;
  • the third initialization signal line pattern 9042 corresponding to the display sub-pixels 90 in one row is multiplexed into the second initialization signal line pattern 9041 corresponding to the display sub-pixels 90 in the next adjacent row.
  • the gate 204g of the fourth transistor T4 in the first direction (eg, the Y direction), the gate 204g of the fourth transistor T4 , the first The gate 201g of the transistor T1 and the gate 202g of the second transistor T2 are both located on the first side of the gate of the driving transistor (ie the gate 203g of the third transistor T3), the gate of the seventh transistor T7, the gate of the sixth transistor T6
  • the gate 206g and the gate of the fifth transistor T5 are both located on the second side of the gate of the driving transistor.
  • the first side and the second side of the gate of the driving transistor are opposite sides along the first direction, and further, the first side of the gate of the driving transistor may be the upper side of the gate of the driving transistor. side, the second side of the gate of the driving transistor may be the lower side of the gate of the driving transistor T1.
  • the lower side for example, the side of the display substrate used to bind the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor that is closer to the IC.
  • the upper side is the opposite side to the lower side, eg the side of the gate of the drive transistor that is further away from the IC.
  • the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located at the third position of the gate of the driving transistor.
  • the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor.
  • the third side and the fourth side of the gate of the driving transistor are opposite sides along the second direction; further, the third side of the gate of the driving transistor may be the right side of the gate of the driving transistor, The fourth side of the gate of the driving transistor may be the left side of the gate of the driving transistor.
  • the second data line pattern 908 is located on the right side of the second power signal line pattern 901
  • the second power signal line pattern 901 is located on the right side of the second data line pattern 908 .
  • the first potential signal line pattern includes a first power supply signal line pattern 801; the dummy sub-pixel 80 further includes:
  • the dummy sub-pixel driving circuit further includes: a second dummy transistor, a fifth dummy transistor and a sixth dummy transistor;
  • the gate of the dummy driving transistor is coupled to the first power supply signal line pattern 801, the first pole of the dummy driving transistor is coupled to the second pole of the fifth dummy transistor, and the The second pole is coupled to the first pole of the sixth dummy transistor;
  • the gate of the second dummy transistor is coupled to the first reset signal line pattern 805, the first electrode of the second dummy transistor is coupled to the first initialization signal line pattern 804, and the second dummy transistor
  • the second pole of the transistor is floating;
  • the gate of the fifth dummy transistor is coupled to the first light-emitting control signal line pattern 803, and the first electrode of the fifth dummy transistor is coupled to the first power signal line pattern 801;
  • the gate of the sixth dummy transistor is coupled to the first light emission control signal line pattern 803 .
  • the dummy transistors included in the dummy sub-pixel driving circuit are all P-type transistors
  • the second dummy transistor T2' is a double-gate structure
  • the second dummy transistor T2' has a double-gate structure.
  • the gate 202g' is coupled to the first reset signal line pattern 805
  • the source S2' of the second dummy transistor T2' is coupled to the first initialization signal line pattern 804, and the drain D2' of the second dummy transistor T2' Floating.
  • the gate 205g' of the fifth dummy transistor T5' is coupled to the first light-emitting control signal line pattern 803, the source S5' of the fifth dummy transistor T5' is coupled to the first power signal line pattern 801, and the fifth dummy transistor T5
  • the drain D5' of ' is coupled to the source S3' of the third dummy transistor T3'.
  • the gate 206g ′ of the sixth dummy transistor T6 ′ is coupled to the first light emission control signal line pattern 803 .
  • the source S6' of the sixth dummy transistor T6' can be set to be coupled to the drain D3' of the third dummy transistor T3', and the drain D6' of the sixth dummy transistor T6' can be coupled to the anode of the light-emitting element EL .
  • the dummy sub-pixel driving circuit further includes a seventh dummy transistor T7', and the gate 207g' of the seventh dummy transistor T7' is connected to the first dummy sub-pixel 80 adjacent to the next dummy sub-pixel 80 along the first direction.
  • a reset signal line pattern 805' is coupled, the drain D7' of the seventh dummy transistor T7' is coupled to the anode of the light-emitting element EL, and the source S7' of the seventh dummy transistor T7' is connected to the first initialization
  • the signal line pattern 804' is coupled.
  • the first plate Cst1' of the first storage capacitor Cst' is multiplexed as the gate 203g' of the third dummy transistor T3', and the second plate Cst2' of the first storage capacitor Cst' is coupled to the first power signal Line pattern 801 is coupled.
  • the N1 node can be coupled to the active pattern (Poly pattern) corresponding to the drain D1 of the first transistor T1 through a hole, and the data signal can pass through the fourth transistor T4, the third transistor T3 and the The first transistor T1 is written to the N1 node.
  • the leakage current will pass through the fifth transistor T5, the third transistor T3 and the sixth transistor T6 to reach the light-emitting element EL, so that the light-emitting element EL emits light.
  • the N1 node in the dummy sub-pixel 80 cannot normally receive the data signal, so that the dummy sub-pixel driving circuit corresponding to the dummy sub-pixel 80 cannot be realized normal drive function.
  • the N1 node is coupled to the corresponding first power signal line pattern 801 by setting the second conductive connection portion 8062, so as to avoid the N1 node being in a floating state and adversely affecting the power signal in the display substrate , the stability of the power supply signal in the display substrate is effectively improved, and the good working performance of the display sub-pixel drive circuit is ensured.
  • the specific structure of the virtual sub-pixel driving circuit can be determined according to the actual layout situation.
  • the virtual sub-pixel driving circuit does not lack virtual transistors, or the missing virtual transistors are not limited to those shown in FIG. 6 .
  • the specific structures included in the dummy sub-pixel driving circuits at different positions may be different.
  • some dummy sub-pixel driving circuits are set to include complete transistor structures (for example, including the first dummy transistor T1' to The seventh dummy transistor T7') is set to include some dummy transistors in other dummy sub-pixel driving circuits.
  • each film layer corresponding to the virtual sub-pixel driving circuit is as follows:
  • the active film layer the first gate insulating layer GI1, the first gate metal layer, the second gate insulating layer GI2, the second gate metal layer, the interlayer insulating layer ILD, The first source-drain metal layer.
  • the active film layer is used to form the channel region (eg: 102pg'-107pg') of each dummy transistor in the dummy sub-pixel driving circuit, the source formation region (eg: 102ps'-107ps') and In the drain formation region (eg: 102pd' to 107pd'), the active film layers corresponding to the source electrode formation region and the drain formation region have better conductivity than the active film layers corresponding to the channel region due to doping;
  • the source film layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials and the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active film layer corresponding to the source electrode formation region and the drain electrode formation region can be directly used as the corresponding source electrode or drain electrode, or a metal material can also be used to make a metal material in contact with the source electrode formation region.
  • a metal material is used to make the drain electrode in contact with the drain formation region.
  • the first gate metal layer is used to form the gates of each dummy transistor in the dummy sub-pixel driving circuit (eg, 202g'-207g'), and the first gate line pattern 802, the first gate line pattern 802, the first The structure of the light-emitting control signal line pattern 803, the first reset signal line pattern 805, etc., the gate 203g' of the third dummy transistor T3' in each dummy sub-pixel driving circuit is multiplexed as the third dummy sub-pixel driving circuit.
  • the second gate metal layer is used to form the second electrode plate Cst2 ′ of the first storage capacitor Cst′ and the first initialization signal line pattern 804 included in the display substrate.
  • the first source-drain metal layer is used to form the source (eg: S2 ′ ⁇ S7 ′) and the drain (eg: D2 ′ ⁇ S7 ′) of each dummy transistor in the dummy sub-pixel driving circuit D7'), and the first data line pattern 808, the first power signal line pattern 801, the first conductive connection part 8061 and the second conductive connection part 8062 included in the display substrate.
  • the gate 202g' of the second dummy transistor T2' covers the second channel region 102pg', and the source S2' of the second dummy transistor T2' is located at the second source A region 102ps' is formed, and the drain D2' of the second dummy transistor T2' is located in the second drain forming region 102pd'.
  • the gate 203g' of the third dummy transistor T3' covers the third channel region 103pg', the source S3' of the third dummy transistor T3' is located in the third source formation region 103ps', and the drain of the third dummy transistor T3' D3' is located in the third drain formation region 103pd'.
  • the gate 205g' of the fifth dummy transistor T5' covers the fifth channel region 105pg', the source S5' of the fifth dummy transistor T5' is located in the fifth source formation region 105ps', and the drain of the fifth dummy transistor T5' D5' is located in the fifth drain formation region 105pd'.
  • the gate 206g' of the sixth dummy transistor T6' covers the sixth channel region 106pg', the source S6' of the sixth dummy transistor T6' is located in the sixth source formation region 106ps', and the drain of the sixth dummy transistor T6' D6' is located in the sixth drain formation region 106pd'.
  • the gate 207g' of the seventh dummy transistor T7' covers the seventh channel region 107pg', the source S7' of the seventh dummy transistor T7' is located in the seventh source formation region 107ps', and the drain of the seventh dummy transistor T7' D7' is located in the seventh drain formation region 107pd'.
  • the gate 203g' of the third dummy transistor T3' is multiplexed as the first plate Cst1' of the first storage capacitor Cst', and the second plate Cst2' of the first storage capacitor Cst' is coupled to the first power signal line pattern 801 catch.
  • the plurality of dummy sub-pixels 80 included may be distributed in an array, and the plurality of dummy sub-pixels 80 may be divided into a plurality of rows of dummy sub-pixels 80 and a plurality of columns of dummy sub-pixels 80, each row
  • Each of the dummy sub-pixels 80 includes a plurality of dummy sub-pixels 80 arranged along a second direction
  • each column of virtual sub-pixels 80 includes a plurality of dummy sub-pixels 80 arranged along a first direction. directions intersect.
  • a row of dummy sub-pixels 80 may include the gate 207g' of the seventh dummy transistor T7' and the second reset signal line pattern 9051 included in the next display sub-pixel 90 adjacent in the first direction. coupled.
  • the gate 202g' of the second dummy transistor T2' On the first side of the gate of the dummy driving transistor (ie the gate 203g' of the third dummy transistor T3'), the gate 207g' of the seventh dummy transistor T7', the gate 206g' of the sixth dummy transistor T6',
  • the gates 205g' of the fifth dummy transistors T5' are all located on the second side of the gates of the dummy driving transistors.
  • the first side and the second side of the gate of the dummy driving transistor are opposite sides along the first direction.
  • the first side of the gate of the dummy driving transistor may be the gate of the dummy driving transistor.
  • the upper side of the electrode, the second side of the gate of the dummy driving transistor may be the lower side of the gate of the dummy driving transistor T1.
  • the lower side for example, the side of the dummy substrate for binding the IC is the lower side of the dummy substrate, and the lower side of the gate of the dummy driving transistor is the side of the gate of the dummy driving transistor closer to the IC.
  • the upper side is the opposite side to the lower side, eg the side of the gate of the dummy drive transistor that is further away from the IC.
  • the gates 205g' of the fifth dummy transistors T5' are located on the third side of the gates of the dummy driving transistors, and the sixth dummy transistors T5'
  • the gate 206g' of the transistor T6' is located on the fourth side of the gate of the dummy drive transistor.
  • the third side and the fourth side of the gate of the dummy driving transistor are opposite sides along the second direction; further, the third side of the gate of the dummy driving transistor may be the side of the gate of the dummy driving transistor.
  • the fourth side of the gate of the dummy drive transistor may be the left side of the gate of the dummy drive transistor.
  • the first data line pattern 808 is located on the right side of the first power signal line pattern 801
  • the first power signal line pattern 801 is located on the right side of the first data line pattern 808 .
  • Embodiments of the present disclosure further provide a display device including the display substrate provided by the above embodiments.
  • the second conductive connection portion 8062 is provided, and the first conductive connection portion 8061 is coupled to the first power signal line pattern 801, so that the dummy sub-pixels are
  • the N1 node in the driving circuit always maintains the same stable potential as the first power signal line pattern 801 , thereby avoiding the phenomenon of uneven display brightness locally on the display substrate 1 caused by the floating connection of the N1 node. Therefore, when the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer.
  • Embodiments of the present disclosure also provide a method for fabricating a display substrate, the fabrication method comprising:
  • a plurality of sub-pixels arranged in an array are fabricated on a substrate; the plurality of sub-pixels include a plurality of display sub-pixels 90 located in the display area of the display panel, and a plurality of dummy sub-pixels at least partially adjacent to the plurality of display sub-pixels pixel 80;
  • the display sub-pixel 90 includes: a display sub-pixel drive circuit, the display sub-pixel drive circuit includes a drive transistor (ie a third transistor T3), a first transistor T1 and a second transistor T2; the gates of the drive transistors are respectively is coupled to the second pole (ie the drain D1) of the first transistor T1 and the second pole (ie the drain D2) of the second transistor T2;
  • a drive transistor ie a third transistor T3
  • the gates of the drive transistors are respectively is coupled to the second pole (ie the drain D1) of the first transistor T1 and the second pole (ie the drain D2) of the second transistor T2;
  • the virtual sub-pixels 80 include:
  • the dummy sub-pixel drive circuit includes a dummy drive transistor, and a first conductive connection portion 8061 coupled to a gate of the dummy drive transistor;
  • a second conductive connection portion 8062, the second conductive connection portion 8062 is respectively coupled to the first conductive connection portion 8061 and the first potential signal line pattern.
  • the second conductive connection portion 8062 is provided, and the first conductive connection portion 8061 is coupled with the first potential signal line pattern, so that the The N1 node in the dummy sub-pixel driving circuit always maintains the same stable potential as the first potential signal line pattern, thereby avoiding the phenomenon of uneven display brightness locally on the display substrate 1 due to the floating connection of the N1 node.
  • the first potential signal line pattern includes a first power supply signal line pattern 801; the first conductive connection portion 8061, the second conductive connection portion 8062 and the first potential signal line pattern are fabricated
  • the steps specifically include:
  • the first conductive connection portion 8061 , the second conductive connection portion 8062 and the first power signal line pattern 801 are formed in an integrated structure.
  • the first conductive connection part 8061, the second conductive connection part 8062 and the first power signal line pattern 801 can be formed simultaneously in one patterning process, which simplifies the production process of the display substrate and reduces the cost of the display substrate. production cost.

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Abstract

本公开提供一种显示基板及其制作方法、显示装置，所述显示基板包括基底和在所述基底上阵列排布的多个子像素；所述多个子像素包括位于显示面板中显示区域的多个显示子像素，以及至少部分与所述多个显示子像素相邻的多个虚拟子像素；所述虚拟子像素包括：第一电位信号线图形；虚拟子像素驱动电路，所述虚拟子像素驱动电路包括虚拟驱动晶体管，以及与所述虚拟驱动晶体管的栅极耦接的第一导电连接部；第二导电连接部，所述第二导电连接部分别与所述第一导电连接部和所述第一电位信号线图形耦接。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
随着显示技术的不断发展，柔性有机发光二极管(英文：Organic Light-Emitting Diode，以下简称OLED)显示面板的应用越来越广泛，而为了在未来的市场竞争中占有一定的比重，企业对显示面板良率和显示质量的提升越发的重视。
柔性OLED显示面板中，每个子像素对应自己的子像素驱动电路，该子像素驱动电路中一般包括驱动晶体管，所述驱动晶体管能够在其栅极的控制下导通，以实现为其对应的子像素提供驱动信号，因此，所述驱动晶体管的栅极电位对整个子像素驱动电路的工作起到了十分重要的作用，是影响显示面板良率和显示质量的重要因素。
发明内容
本公开的目的在于提供一种显示基板及其制作方法、显示装置。
本公开的第一方面提供一种显示基板，包括基底和在所述基底上阵列排布的多个子像素；所述多个子像素包括位于显示面板中显示区域的多个显示子像素，以及至少部分与所述多个显示子像素相邻的多个虚拟子像素；
所述显示子像素包括：显示子像素驱动电路，所述显示子像素驱动电路包括驱动晶体管、第一晶体管和第二晶体管；所述驱动晶体管的栅极分别与所述第一晶体管的第二极和所述第二晶体管的第二极耦接；
所述虚拟子像素包括：
第一电位信号线图形；
虚拟子像素驱动电路，所述虚拟子像素驱动电路包括虚拟驱动晶体管，以及与所述虚拟驱动晶体管的栅极耦接的第一导电连接部；以及，
第二导电连接部，所述第二导电连接部分别与所述第一导电连接部和所述第一电位信号线图形耦接。
可选的，所述第一导电连接部沿第一方向延伸；
所述第一电位信号线图形包括第一电源信号线图形，所述第一电源信号线图形包括沿所述第一方向延伸的第一部分；
所述第二导电连接部沿第二方向延伸，所述第二方向与所述第一方向相交，所述第二导电连接部分别与所述第一导电连接部和所述第一电源信号线图形的第一部分耦接。
可选的，第一电位信号线图形包括第一电源信号线图形，所述第一电源信号线图形包括相耦接的第一部分和第二部分，所述第一部分沿所述第一方向延伸，所述第二部分沿第二方向延伸，所述第二方向与所述第一方向相交；
所述第一导电连接部沿所述第一方向延伸；
所述第二导电连接部沿所述第一方向延伸，所述第二导电连接部分别与所述第一导电连接部和所述第一电源信号线图形的第二部分耦接。
可选的，沿所述第二方向至少两个所述虚拟子像素中包括的所述第二部分耦接。
可选的，至少一个目标虚拟子像素中包括的所述第一部分和所述第二部分形成为一体结构；
所述目标虚拟子像素为沿所述第一方向位于显示区域最外侧的虚拟子像素。
可选的，第一电位信号线图形包括第一电源信号线图形，所述第一导电连接部、所述第二导电连接部和所述第一电源信号线图形形成为一体结构。
可选的，所述虚拟子像素还包括：
均沿第二方向延伸的第一栅线图形和第一发光控制信号线图形，所述第一栅线图形与所述第一发光控制信号线图形沿第一方向设置，所述虚拟驱动晶体管的栅极在所述基底上的正投影位于所述第一栅线图形在所述基底上的 正投影与所述第一发光控制信号线图形在所述基底上的正投影之间；
所述第一栅线图形在所述基底上的正投影，位于所述第二导电连接部在所述基底上的正投影与所述第一发光控制信号线图形在所述基底上的正投影之间。
可选的，所述显示子像素包括：
均沿第二方向延伸的第二栅线图形和第二发光控制信号线图形；
沿所述第二方向至少一个所述虚拟子像素中包括的所述第一栅线图形，以及沿所述第二方向与该虚拟子像素位于同一行，且与所述至少一个所述虚拟子像素相邻的显示子像素中包括的所述第二栅线图形形成为一体结构；
沿所述第二方向至少一个所述虚拟子像素中包括的所述第一发光控制信号线图形，以及沿所述第二方向与该虚拟子像素位于同一行，且与所述至少一个所述虚拟子像素相邻的所述显示子像素中包括的所述第二发光控制信号线图形形成为一体结构。
可选的，第一电位信号线图形包括第一电源信号线图形；所述虚拟子像素驱动电路还包括：
第一存储电容，所述虚拟驱动晶体管的栅极复用为所述第一存储电容的第一极板，所述第一存储电容的第二极板位于所述第一极板背向所述基底的一侧，所述第二极板在所述基底上的正投影，与所述第一电源信号线图形中沿第一方向延伸的第一部分在所述基底上的正投影具有交叠区域，在该交叠区域所述第二极板与所述第一部分耦接；
所述显示子像素还包括：
第二电源信号线图形，所述第二电源信号线图形包括沿所述第一方向延伸的第三部分；
所述显示子像素驱动电路还包括第二存储电容，所述驱动晶体管的栅极复用为所述第二存储电容的第三极板，所述第二存储电容的第四极板位于所述第三极板背向所述基底的一侧，所述第四极板在所述基底上的正投影与所述第二电源信号线图形的第三部分在所述基底上的正投影具有交叠区域，在该交叠区域所述第四极板与所述第三部分耦接；
沿所述第二方向位于同一行的各所述虚拟子像素中包括的所述第二极板，以及位于该行的各所述显示子像素中包括的所述第四极板形成为一体结构。
可选的，所述显示子像素包括：
第二电源信号线图形，所述第二电源信号线图形包括沿所述第一方向延伸的第三部分；
沿所述第一方向位于同一列的各所述虚拟子像素中包括的第一电源信号线图形的第一部分，以及位于该列的各所述显示子像素中包括的所述第二电源信号线图形的第三部分形成为一体结构。
可选的，所述虚拟子像素还包括：沿第一方向延伸的第一数据线图形；
所述显示子像素包括沿第一方向延伸的第二数据线图形；
沿所述第一方向位于同一列的各所述虚拟子像素中包括的所述第一数据线图形，以及位于该列的各所述显示子像素中包括的所述第二数据线图形形成为一体结构。
可选的，所述虚拟子像素包括有源层图形，所述有源层图形包括：
相对设置的第一有源子图形和第二有源子图形，所述第一有源子图形和所述第二有源子图形均沿第一方向延伸；
设置于所述第一有源子图形与所述第二有源子图形之间的第三有源子图形，所述第三有源子图形的两端与所述第一有源子图形和所述第二有源子图形耦接，所述第三有源子图形的至少部分在所述基底上的正投影，与所述虚拟驱动晶体管的栅极在所述基底上的正投影交叠；
所述第一导电连接部远离所述虚拟驱动晶体管的栅极的部分在所述基底上的正投影，与所述有源层图形在所述基底上的正投影不交叠。
可选的，所述虚拟子像素还包括沿所述第一方向延伸的第一数据线图形，所述第二有源子图形在所述基底上的正投影，位于所述第一数据线图形在所述基底上的正投影与所述第一有源子图形在所述基底上的正投影之间；
所述第一数据线图形在所述基底上的正投影与所述有源层图形在所述基底上的正投影不交叠。
可选的，第一电位信号线图形包括第一电源信号线图形；所述虚拟子像 素还包括：
第一数据线图形、第一栅线图形、第一发光控制信号线图形、第一复位信号线图形和第一初始化信号线图形；所述第一电源信号线图形的至少部分和所述第一数据线图形均沿第一方向延伸，所述第一栅线图形、所述第一发光控制信号线图形、所述第一复位信号线图形和所述第一初始化信号线图形均沿第二方向延伸；
所述虚拟子像素驱动电路还包括：第二虚拟晶体管、第五虚拟晶体管和第六虚拟晶体管；
所述虚拟驱动晶体管的栅极与所述第一电源信号线图形耦接，所述虚拟驱动晶体管的第一极与所述第五虚拟晶体管的第二极耦接，所述虚拟驱动晶体管的第二极与所述第六虚拟晶体管的第一极耦接；
所述第二虚拟晶体管的栅极与所述第一复位信号线图形耦接，所述第二虚拟晶体管的第一极与所述第一初始化信号线图形耦接，所述第二虚拟晶体管的第二极浮接；
所述第五虚拟晶体管的栅极与所述第一发光控制信号线图形耦接，所述第五虚拟晶体管的第一极与所述第一电源信号线图形耦接；
所述第六虚拟晶体管的栅极与所述第一发光控制信号线图形耦接。
可选的，所述显示子像素驱动电路还包括沿第一方向延伸的第三导电连接部，所述第三导电连接部的第一端与所述驱动晶体管的栅极耦接，所述第三导电连接部的第二端分别与所述第一晶体管的第二极和所述第二晶体管的第二极耦接。
可选的，所述第一晶体管的第二极与所述第二晶体管的第二极耦接，形成公共连接端，所述第三导电连接部的第二端在所述基底上的正投影与所述公共连接端在所述基底上的正投影交叠，在该交叠处所述第三导电连接部的第二端与所述公共连接端耦接。
可选的，所述显示子像素包括：第二电源信号线图形、第二数据线图形、第二栅线图形、第二发光控制信号线图形、第二复位信号线图形、第三复位信号线图形、第二初始化信号线图形和第三初始化信号线图形；所述第二电 源信号线图形的至少部分和所述第二数据线图形沿第一方向延伸；所述第二栅线图形、所述第二发光控制信号线图形、所述第二复位信号线图形、所述第三复位信号线图形、所述第二初始化信号线图形和所述第三初始化信号线图形均沿第二方向延伸，所述第二方向与所述第一方向相交；
所述显示子像素驱动电路还包括：第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述第二栅线图形耦接；
所述第二晶体管的栅极与所述第二复位信号线图形耦接，所述第二晶体管的第一极与所述第二初始化信号线图形耦接；
所述第四晶体管的栅极与所述第二栅线图形耦接，所述第四晶体管的第一极与所述第二数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述第二发光控制信号线图形耦接，所述第五晶体管的第一极与所述第二电源信号线图形耦接；
所述第六晶体管的栅极与所述第二发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述显示子像素中的发光元件耦接；
所述第七晶体管的第二极与所述显示子像素中的发光元件耦接，所述第七晶体管的栅极与所述第三复位信号线图形耦接，所述第七晶体管的第一极与所述第三初始化信号线图形耦接。
可选的，所述第一导电连接部与所述第二导电连接部为一体结构。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示基板的制作方法，所述制作方法包括：
在基底上制作阵列排布的多个子像素；所述多个子像素包括位于显示面 板中显示区域的多个显示子像素，以及至少部分与所述多个显示子像素相邻的多个虚拟子像素；
所述显示子像素包括：显示子像素驱动电路，所述显示子像素驱动电路包括驱动晶体管、第一晶体管和第二晶体管；所述驱动晶体管的栅极分别与所述第一晶体管的第二极和所述第二晶体管的第二极耦接；
所述虚拟子像素包括：
第一电位信号线图形；
虚拟子像素驱动电路，所述虚拟子像素驱动电路包括虚拟驱动晶体管，以及与所述虚拟驱动晶体管的栅极耦接的第一导电连接部；
第二导电连接部，所述第二导电连接部分别与所述第一导电连接部和所述第一电位信号线图形耦接。
可选的，所述第一电位信号线图形包括第一电源信号线图形；制作所述第一导电连接部、所述第二导电连接部和所述第一电位信号线图形的步骤具体包括：
通过一次构图工艺，形成一体结构的所述第一导电连接部、所述第二导电连接部和所述第一电源信号线图形。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的显示基板的示意图；
图2为图1中C部分的第一放大示意图；
图3为图1中C部分的第二放大示意图；
图4为本公开实施例提供的虚拟子像素驱动电路的第一结构示意图；
图5为本公开实施例提供的虚拟子像素驱动电路的第一布局示意图；
图6为本公开实施例提供的虚拟子像素驱动电路的第二结构示意图；
图7为本公开实施例提供的虚拟子像素驱动电路的第二布局示意图；
图8为图7中有源层布局示意图；
图9为图7中第一栅金属层布局示意图；
图10为图7中第二栅金属层布局示意图；
图11为图7中源漏金属层布局示意图；
图12为本公开实施例提供的虚拟子像素驱动电路的第三布局示意图；
图13a为图2中B部分的放大示意图；
图13b为图13a中沿A1A2方向的截面示意图；
图13c为图13a中沿B1B2方向的截面示意图；
图13d为图2中C部分的放大示意图；
图14为本公开实施例提供的显示子像素驱动电路的第一结构示意图；
图15为本公开实施例提供的显示子像素驱动电路的第一布局示意图；
图16图15中有源层布局示意图；
图17为图15中第一栅金属层布局示意图；
图18为图15中第二栅金属层布局示意图；
图19为图15中源漏金属层布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
本公开提供的显示基板包括显示区域和位于显示区域周边的非显示区域，所述显示区域包括中心部分和边缘部分，边缘部分为显示区域中靠近显示区域边界的部分，以具有圆角的矩形显示区域为例，该边缘部分包括位于显示区域上、下、左，右四边的部分，以及位于显示区域四个圆角的部分。
在所述显示基板中，在对显示区域的实际布局过程中，为了保证显示基板工艺过程的均一性，会在显示区域边缘处，正常显示用子像素的外围设置虚拟的子像素，这些虚拟的子像素不会进行有机发光材料的蒸镀，即不会发光，其作用是为了在刻蚀工艺过程中与正常显示用像素的电路刻蚀保持刻蚀均一性，防止边缘显示用子像素因刻蚀不均造成局部线路的线宽与线距的变 化。
而在实际布局虚拟的子像素和显示用子像素时，由于显示区域的边缘处布局空间较小，无法实现布局与显示用子像素结构完全相同的虚拟的子像素，因此在布局虚拟的子像素时，该虚拟的子像素中对应的虚拟子像素驱动电路的结构相对于正常的显示子像素驱动电路结构更加简化。但是所述显示基板中设置的虚拟子像素并不是独立存在的，其信号的写入与正常显示用子像素的设计是保持一致的，而虚拟子像素中简化的虚拟子像素驱动电路结构，可能无法保证虚拟子像素在驱动过程中的稳定性，使得虚拟子像素驱动电路中可能存在浮接的节点，从而导致显示基板在工作时稳定性较差，显示质量较差。
下面以显示用子像素包括7T1C(即7个薄膜晶体管和1个电容)的显示子像素驱动电路为例，对显示子像素和虚拟子像素的布局结构进行说明。
如图1、图2、图4、图5和图13d所示，所述虚拟子像素80包括：第一数据线图形808、第一栅线图形802、第一发光控制信号线图形803、第一复位信号线图形805和第一初始化信号线图形804；第一电源信号线图形801的至少部分(如：第一部分8011)和所述第一数据线图形808均沿第一方向(如Y方向)延伸，所述第一栅线图形802、所述第一发光控制信号线图形803、所述第一复位信号线图形805和所述第一初始化信号线图形804均沿第二方向(如X方向)延伸。
所述虚拟子像素80中的虚拟子像素驱动电路包括：虚拟驱动晶体管(即第三虚拟晶体管T3')、第二虚拟晶体管T2'、第五虚拟晶体管T5'、第六虚拟晶体管T6'、第七虚拟晶体管T7'和第一存储电容Cst'。需要说明的是，上述虚拟驱动晶体管和虚拟晶体管中的“虚拟”可以理解为虚设等，即不用做驱动发光层发光。
所述第二虚拟晶体管T2'为双栅结构，第二虚拟晶体管T2'的栅极202g'与所述第一复位信号线图形805耦接，第二虚拟晶体管T2'的源极S2'与所述第一初始化信号线图形804耦接，第二虚拟晶体管T2'的漏极D2'浮接。
第五虚拟晶体管T5'的栅极205g'与第一发光控制信号线图形803耦接， 第五虚拟晶体管T5'的源极S5'与第一电源信号线图形801耦接，第五虚拟晶体管T5'的漏极D5'与第三虚拟晶体管T3'的源极S3'耦接。
第六虚拟晶体管T6'的栅极206g'与第一发光控制信号线图形803耦接，第六虚拟晶体管T6'的源极S6'与第三虚拟晶体管T3'的漏极D3'耦接，第六虚拟晶体管T6'的漏极D6'与发光元件EL的阳极耦接。
第七虚拟晶体管T7'的栅极207g'与沿第一方向相邻的下一个虚拟子像素80中的所述第一复位信号线图形805'耦接，第七虚拟晶体管T7'的漏极D7'与所述发光元件EL的阳极耦接，第七虚拟晶体管T7'的源极S7'与沿第一方向相邻的下一个虚拟子像素80中的所述第一初始化信号线图形804'耦接；所述发光元件EL的阴极与负电源信号线VSS耦接。
第一存储电容Cst'的第一极板Cst1'复用为第三虚拟晶体管T3'的栅极203g'耦接，第一存储电容Cst'的第二极板Cst2'与所述第一电源信号线图形801耦接。
值得注意，如图4所示，由于所述虚拟子像素驱动电路中，不包括第一虚拟晶体管T1'和第四虚拟晶体管T4'，因此，由所述第一数据线图形808提供的数据信号无法依次通过所述第四虚拟晶体管T4'、所述第三虚拟晶体管T3'和所述第一虚拟晶体管T1'，写入到N1节点，导致该N1节点处于浮接状态。需要说明，所述虚拟驱动晶体管的栅极与该N1节点耦接。
由于所述虚拟子像素驱动电路中，N1节点与所述第一电源信号线图形801之间会通过第一存储电容Cst'，以及该虚拟子像素驱动电路中的其它寄生电容发生耦合，使得N1节点电压的变化会引起所述第一电源信号线图形801上的电压变化。而所述第一电源信号线图形801上的电压变化会影响显示子像素90中的第二电源信号线图形901上的电源变化，所述第二电源信号线图形901上的电压VDD会影响流过显示子像素90的发光元件的电流，从而影响显示子像素90中发光元件的正常发光，导致显示基板出现局部显示亮度不均匀的现象。
更详细地说，流过所述显示子像素90的发光元件的电流I满足如下关系式：I＝1/2×K(Vdata-VDD)2，式中K为常数，Vdata为数据电压，因此，当 VDD变化时，就会引起电流I的变化，从而影响发光元件的发光效率。
基于上述分析可知，虚拟子像素驱动电路中N1节点的电压对整个显示子像素驱动电路的工作起到了十分重要的作用，是影响显示子像素驱动电路工作性能的重要因素；因此通过对N1节点的设计和改进，来提升显示产品的良率，增强显示产品的竞争力成为目前的焦点。
请参阅图1、图2、图6和图7所示，本公开实施例提供了一种显示基板1，包括基底和在所述基底上阵列排布的多个子像素；所述多个子像素包括位于显示面板中显示区域的多个显示子像素90，以及至少部分与所述多个显示子像素相邻的多个虚拟子像素80；
所述显示子像素90包括：显示子像素驱动电路，所述显示子像素驱动电路包括驱动晶体管(即第三晶体管T3)、第一晶体管T1和第二晶体管T2；所述驱动晶体管的栅极分别与所述第一晶体管T1的第二极(即漏极D1)和所述第二晶体管T2的第二极(即漏极D2)耦接；
所述虚拟子像素80包括：第一电位信号线图形、虚拟子像素驱动电路和第二导电连接部8062；所述虚拟子像素驱动电路包括虚拟驱动晶体管，以及与所述虚拟驱动晶体管的栅极耦接的第一导电连接部8061；所述第二导电连接部8062分别与所述第一导电连接部8061和所述第一电位信号线图形耦接。
具体地，所述显示基板1中包括的所述多个虚拟子像素80可沿所述多个显示子像素90的边界分布，且在某一边界处，沿所述第一方向和所述第二方向均可以分布多个虚拟子像素80。示例性的，在图2中的A边界，沿所述第一方向分布有三个虚拟子像素80，沿所述第二方向分布有两个虚拟子像素80。
如图7所示，所述虚拟子像素驱动电路中包括所述虚拟驱动晶体管和所述第一导电连接部8061，所述第一导电连接部8061的一端与所述虚拟驱动晶体管的栅极耦接，所述第一导电连接部8061上的电位即为所述N1节点的电位。
所述虚拟子像素80还包括所述第一电位信号线图形和所述第二导电连接部8062，在同一个虚拟子像素80中，所述第二导电连接部8062的一端与所述第一导电连接部8061的另一端耦接，所述第二导电连接部8062的另一 端与所述第一电位信号线图形耦接，从而实现了将所述N1节点保持与所述第一电位信号线图形相同的电位。
需要说明，上述“耦接”包括直接电连接，以及通过导电层间接电连接。
示例性的，所述第一导电连接部8061与所述第二导电连接部8062可形成为一体结构。值得注意，所述一体结构包括：采用同种材料，通过一次构图工艺同时形成接触的所述第一导电连接部8061与所述第二导电连接部8062；或者，所述第一导电连接部8061与所述第二导电连接部8062能够直接接触。
示例性的，所述第一导电连接部8061沿第一方向延伸，所述第二导电连接部8062沿第二方向延伸，所述第一导电连接部8061在垂直于所述第一方向的方向上的宽度，小于所述第二导电连接部8062在垂直于所述第二方向的方向上的宽度。当所述第一电位信号线图形包括第一电源信号线图形801时，这种方式能够更好的降低第一电源信号线图形801上的电阻。
示例性的，所述第一导电连接部8061沿第一方向延伸，所述第二导电连接部8062沿第二方向延伸，所述第一导电连接部8061在垂直于所述第一方向上的宽度，等于所述第二导电连接部8062在垂直于所述第二方向上的宽度。
示例性的，所述第一导电连接部8061在所述基底上的正投影，与第一栅线图形802在所述基底上的正投影具有第一交叠区域，所述第一导电连接部8061位于所述第一交叠区域的部分在垂直于所述第一方向上的宽度，小于所述第一导电连接部8061其余部分在垂直于所述第一方向上的宽度。
示例性的，所述第二导电连接部8062在所述基底上的正投影，与第一栅线图形802在所述基底上的正投影具有第二交叠区域，所述第二导电连接部8062位于所述第二交叠区域的部分在垂直于所述第二方向上的宽度，小于所述第二导电连接部8062其余部分在垂直于所述第二方向上的宽度。
示例性的，所述第一电源信号线图形801在所述基底上的正投影，与第一栅线图形802在所述基底上的正投影具有第三交叠区域，所述第一电源信号线图形801位于所述第三交叠区域的部分在垂直于所述第一方向上的宽度，小于所述第一电源信号线图形801其余部分在垂直于所述第一方向上的宽度。
上述设置方式能够更好的减小所述第一栅线图形802与所述第一导电连接部8061、所述第二导电连接部8062和/或所述第一电源信号线图形801之间的交叠面积，从而更好的降低所述第一栅线图形802负载。
示例性的，所述第一导电连接部8061与所述第二导电连接部8062异层设置。
示例性的，所述第一导电连接部8061与所述第一电源信号线图形801同层设置，所述第一导电连接部8061与所述第二导电连接部8062异层设置。
示例性的，所述第一电位信号线图形包括第一初始化信号线图形，所述第二导电连接部8062的一端与所述第一导电连接部8061的另一端耦接，所述第二导电连接部8062的另一端与所述第一初始化信号线图形耦接，从而实现了将所述N1节点保持与所述第一初始化信号线图形相同的电位。
示例性的，所述第一电位信号线图形包括第一电源信号线图形801，在同一个虚拟子像素80中，所述第二导电连接部8062的一端与所述第一导电连接部8061的另一端耦接，所述第二导电连接部8062的另一端与所述第一电源信号线图形801耦接，从而实现了将所述N1节点保持与所述第一电源信号线图形801相同的电位。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板1中，通过设置所述第二导电连接部8062，将所述第一导电连接部8061与所述第一电位信号线图形耦接，使得所述虚拟子像素驱动电路中的N1节点始终保持与所述第一电位信号线图形相同的稳定电位，从而避免了由于所述N1节点浮接导致的显示基板1出现局部显示亮度不均匀的现象。
所述第一导电连接部8061、所述第一电位信号线图形和所述第二导电连接部8062图形的具体结构多种多样。在一些实施例中，所述第一电位信号线图形包括第一电源信号线图形801，所述第一导电连接部8061沿第一方向延伸；所述第一电源信号线图形801包括沿所述第一方向延伸的第一部分8011；所述第二导电连接部8062沿第二方向延伸，所述第二方向与所述第一方向相交，所述第二导电连接部8062分别与所述第一导电连接部8061和所述第一电源信号线图形801的第一部分8011耦接。
具体地，可设置所述第一导电连接部8061沿所述第一方向延伸，所述第一电源信号线图形801中的第一部分8011沿所述第一方向延伸，所述第一导电连接部8061与所述第一电源信号线图形801沿所述第二方向排列。
同时可设置所述第二导电连接部8062沿所述第二方向延伸，所述第二导电连接部8062在所述基底上的正投影位于所述第一导电连接部8061在所述基底上的正投影，与所述第一电源信号线图形801的第一部分8011在所述基底上的正投影之间，所述第二导电连接部8062靠近所述第一导电连接部8061的一端与所述第一导电连接部8061耦接，所述第二导电连接部8062靠近所述第一部分8011一端与所述第一电源信号线图形801耦接。
如图12所示，在另外一些实施例中，第一电位信号线图形包括第一电源信号线图形801，所述第一电源信号线图形801包括相耦接的第一部分8011和第二部分8012，所述第一部分8011沿所述第一方向延伸，所述第二部分8012沿第二方向延伸，所述第二方向与所述第一方向相交；所述第一导电连接部8061沿所述第一方向延伸；所述第二导电连接部8062沿所述第一方向延伸，所述第二导电连接部8062分别与所述第一导电连接部8061和所述第一电源信号线图形801的第二部分8012耦接。
具体地，所述第一电源信号线图形801可具体包括相耦接的第一部分8011和第二部分8012，这种结构的所述第一电源信号线图形801具有较大的面积，能够很好的降低所述第一电源信号线图形801上产生的压降。
同时可设置所述电源信号线图形的第二部分8012沿所述第二方向延伸，所述第一导电连接部8061和所述第二导电连接部8062均沿所述第一方向延伸，所述第二导电连接部8062在所述基底上的正投影位于所述第一导电连接部8061在所述基底上的正投影，与所述第一电源信号线图形801的第二部分8012在所述基底上的正投影之间，所述第二导电连接部8062靠近所述第一导电连接部8061的一端与所述第一导电连接部8061耦接，所述第二导电连接部8062靠近所述第二部分8012的一端与所述第二部分8012耦接。
需要说明，上述实施例中，所述第一方向可选为Y方向，所述第二方向可选为X方向。
所述第一电源信号线图形801、所述第一导电连接部8061和所述第二导电连接部8062采用上述实施例提供的的具体结构时，能够最大限度的缩小所述第二导电连接部8062占用的布局空间，从而更好的缩小了所述虚拟子像素80整体占用的布局空间，更有利于提升显示基板的分辨率。
如图13a所示，在一些实施例中，沿所述第二方向至少两个所述虚拟子像素80中包括的所述第二部分8012耦接。
具体的，所述显示基板中包括的所述多个子像素呈阵列分布，能够划分为多行子像素和多列子像素，所述多行子像素沿所述第一方向依次排列，每行子像素均包括沿所述第二方向依次排列的多个子像素，该多个子像素包括位于边缘部分的虚拟子像素80和位于中心部分显示子像素90。所述多列子像素沿所述第二方向依次排列，每列子像素均包括沿所述第一方向依次排列的多个子像素，该多个子像素同样包括位于边缘部分的虚拟子像素80和位于中心部分显示子像素90。
示例性的，沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第二部分8012依次耦接。
上述将沿所述第二方向至少两个所述虚拟子像素80中包括的所述第二部分8012耦接，使得所述显示基板中包括的至少部分虚拟子像素80的第一电源线图形能够形成为具有较大面积的网状结构，这样更有利于降低所述第一电源信号线图形801的压降，从而更好的提升了显示基板的显示质量。
需要说明，上述沿所述第二方向耦接在一起的各所述虚拟子像素80均位于所述显示基板的同一侧，示例性的，在所述显示基板的左侧或者右侧，沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第二部分8012依次耦接。
如图3所示，在一些实施例中，至少一个目标虚拟子像素80'中包括的所述第一部分8011和所述第二部分8012形成为一体结构；所述目标虚拟子像素80'为沿所述第一方向位于显示区域最外侧的虚拟子像素80。
具体地，如图13a所示，在设置位于同一行的多个目标虚拟子像素80'中包括的所述第一部分8011和所述第二部分8012形成为一体结构时，可将 所述目标虚拟子像素80'中包括的第一数据线图形808沿所述第一方向的长度缩短，以避免所述第一数据线图形808与所述第二部分8012之间发生短路。
示例性的，每一个目标虚拟子像素80'中包括的所述第一部分8011和所述第二部分8012均形成为一体结构。
示例性的，沿所述第二方向位于同一行的目标虚拟子像素80'中包括的所述第一部分8011和所述第二部分8012均形成为一体结构。
另外，值得注意，所述目标虚拟子像素80'中可以不包括第一初始化信号线图形804、第一复位信号线图形805和第二虚拟晶体管T2'。
如图7和图12所示，在一些实施例中，第一电位信号线图形包括第一电源信号线图形801，所述第一导电连接部8061、所述第二导电连接部8062和所述第一电源信号线图形801形成为一体结构。
将所述第一导电连接部8061、所述第二导电连接部8062和所述第一电源信号线图形801形成为一体结构，使得所述第一导电连接部8061、所述第二导电连接部8062和所述第一电源信号线图形801能够在一次构图工艺中同时形成，从而更好的简化显示基板的制作流程，降低显示基板的制作成本。
需要说明，所述第一导电连接部8061、所述第二导电连接部8062和所述第一电源信号线图形801均可采用显示基板中的第一源漏金属层制作。
如图7和图12所示，在一些实施例中，所述虚拟子像素80还包括：
均沿第二方向延伸的第一栅线图形802和第一发光控制信号线图形803，所述第一栅线图形802与所述第一发光控制信号线图形803沿第一方向设置，所述虚拟驱动晶体管的栅极在所述基底上的正投影位于所述第一栅线图形802在所述基底上的正投影与所述第一发光控制信号线图形803在所述基底上的正投影之间；
所述第一栅线图形802在所述基底上的正投影，位于所述第二导电连接部8062在所述基底上的正投影与所述第一发光控制信号线图形803在所述基底上的正投影之间。
具体地，所述第二导电连接部8062的具体布局位置多种多样，示例性的，可设置所述第一栅线图形802在所述基底上的正投影，位于所述第二导电连 接部8062在所述基底上的正投影与所述第一发光控制信号线图形803在所述基底上的正投影之间；这样所述第二导电连接部8062能够位于所述第一栅线图形802远离所述第一发光控制信号线图形803和所述虚拟驱动晶体管的一侧，使得所述第二导电连接部8062具有更大的布局空间，能够更好的避免所述第二导电连接部8062与除所述第一导电连接部8061和所述第一电源信号线图形801之外的其它导电结构发生短路，从而更好的提升了所述显示基板的稳定性。
如图13a和图15所示，在一些实施例中，所述显示子像素90包括：
均沿第二方向延伸的第二栅线图形902和第二发光控制信号线图形903；
沿所述第二方向至少一个所述虚拟子像素80中包括的所述第一栅线图形802，以及沿所述第二方向与该虚拟子像素位于同一行，且与所述至少一个所述虚拟子像素80相邻的显示子像素90中包括的所述第二栅线图形902形成为一体结构；
沿所述第二方向至少一个所述虚拟子像素80中包括的所述第一发光控制信号线图形803，以及沿所述第二方向与该虚拟子像素位于同一行，且与所述至少一个所述虚拟子像素相邻的显示子像素90中包括的所述第二发光控制信号线图形903形成为一体结构。
具体地，所述显示子像素90包括所述第二栅线图形902和所述第二发光控制信号线图形903，所述第二栅线图形902与所述第二发光控制信号线图形903沿第一方向相对设置，所述第二栅线图形902中的至少部分沿所述第二方向延伸。
在布局所述虚拟子像素80和所述显示子像素90时，示例性的，可将沿所述第二方向位于同一行各所述虚拟子像素80中包括的所述第一栅线图形802，以及位于该行的各所述显示子像素90中包括的所述第二栅线图形902布局在同一条直线上；同样的可以将沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第一发光控制信号线图形803，以及位于该行的各所述显示子像素90中包括的所述第二发光控制信号线图形903布局在同一条直线上。
示例性的，沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第一栅线图形802，以及位于该行的各所述显示子像素90中包括的所述第二栅线图形902依次耦接，且形成为一体结构；
沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第一发光控制信号线图形803，以及位于该行的各所述显示子像素90中包括的所述第二发光控制信号线图形903依次耦接，且形成为一体结构。
进一步地，也可将所述第一栅线图形802，所述第一发光控制信号线图形803，所述第二栅线图形902和所述第二发光控制信号线图形903均同层同材料设置，这样所述显示基板中的全部所述第一栅线图形802、全部所述第一发光控制信号线图形803和全部所述第二栅线图形902、全部所述第二发光控制信号线图形903均可以通过一次构图工艺同时形成，从而更好的简化显示基板的制作流程，降低显示基板的制作成本。
如图12、图13a、图14和图15所示，在一些实施例中，第一电位信号线图形包括第一电源信号线图形801；所述虚拟子像素驱动电路还包括：
第一存储电容Cst'，所述虚拟驱动晶体管的栅极复用为所述第一存储电容Cst'的第一极板Cst1'，所述第一存储电容Cst'的第二极板Cst2'位于所述第一极板Cst1'背向所述基底的一侧，所述第二极板Cst2'在所述基底上的正投影，与所述第一电源信号线图形801中沿第一方向延伸的第一部分8011在所述基底上的正投影具有交叠区域，在该交叠区域所述第二极板与所述第一部分8011耦接；
所述显示子像素90还包括：
第二电源信号线图形901，所述第二电源信号线图形901包括沿所述第一方向延伸的第三部分；
所述显示子像素驱动电路还包括驱动晶体管和第二存储电容Cst，所述驱动晶体管的栅极复用为所述第二存储电容Cst的第三极板Cst1，所述第二存储电容Cst的第四极板Cst2位于所述第三极板Cst1背向所述基底的一侧，所述第四极板Cst2在所述基底上的正投影与所述第二电源信号线图形901的第三部分在所述基底上的正投影具有交叠区域，在该交叠区域所述第四极板 Cst2与所述第三部分耦接；
沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第二极板Cst2，以及位于该行的各所述显示子像素90中包括的所述第四极板Cst2形成为一体结构。
具体地，所述虚拟子像素驱动电路还包括第一存储电容，所述显示子像素驱动电路还包括第二存储电容，所述第一存储电容的第二极板和所述第二存储电容的第四极板可以同层同材料设置，从而使得所述显示基板中包括的全部所述第一存储电容的第二极板和所述第二存储电容的第四极板均能够在同一次构图工艺中同时形成，从而更好的简化了显示基板的制作流程，降低了显示基板的制作成本。
上述设置沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第二极板，以及位于该行的各所述显示子像素90中包括的所述第四极板形成为一体结构，能够最大限度的减少所述第二极板和所述第四极板占用的布局空间，更有利于显示基板的高分辨率发展趋势。
如图12、图13a、图14和图15所示，在一些实施例中，所述显示子像素90包括：第二电源信号线图形901，所述第二电源信号线图形901包括沿所述第一方向延伸的第三部分；
沿所述第一方向位于同一列的各所述虚拟子像素80中包括的所述第一电源信号线图形801的第一部分8011，以及位于该列的各所述显示子像素90中包括的所述第二电源信号线图形901的第三部分形成为一体结构。
上述设置方式使得所述第一电源信号线图形801和所述第二电源信号线图形901占用的布局空间最小化，更有利于显示基板的高分辨率发展趋势。而且，还能够通过一次构图工艺同时形成所述虚拟子像素80中包括的全部第一电源信号线图形801，以及所述显示子像素90中包括的全部第二电源信号线图形901，从而更好的简化了显示基板的制作流程，降低了显示基板的制作成本。
如图12、图13a、图14和图15所示，在一些实施例中，所述虚拟子像素80还包括：
均沿第二方向延伸的第一栅线图形802、第一发光控制信号线图形803、第一初始化信号线图形804和第一复位信号线图形805；沿第一方向所述第一栅线图形802、所述第一发光控制信号线图形803、所述第一初始化信号线图形804和所述第一复位信号线图形805依次排列；
所述显示子像素90还包括：均沿第二方向延伸的第二初始化信号线图形9041、第三初始化信号线图形9042、第二复位信号线图形9051和第三复位信号线图形9052；
沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第一初始化信号线图形804，以及位于该行的各所述显示子像素90中包括的所述第二初始化信号线图形9041依次耦接，且形成为一体结构；
沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第一复位信号线图形805，以及位于该行的各所述显示子像素90中包括的所述第二复位信号线图形9051依次耦接，且形成为一体结构。
具体地，在一个所述显示子像素90中，所述第二初始化信号线图形9041、所述第二复位信号线图形9051、所述第三初始化信号线图形9042和所述第三复位信号线图形9052可以沿所述第一方向依次排列。
上述设置沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第一初始化信号线图形804，以及位于该行的各所述显示子像素90中包括的所述第二初始化信号线图形9041依次耦接，且形成为一体结构；以及沿所述第二方向位于同一行的各所述虚拟子像素80中包括的所述第一复位信号线图形805，以及位于该行的各所述显示子像素90中包括的所述第二复位信号线图形9051依次耦接，且形成为一体结构；不仅有效减小了各虚拟子像素80和显示子像素90占用的布局空间，还能够通过一次构图工艺同时形成所述第一初始化信号线图形804和所述第二初始化信号线图形9041；以及能够通过一次构图工艺同时形成第一复位信号线图形805和所述第二复位信号线图形9051。
值得注意，所述显示子像素90中，所述第二初始化信号线图形9041与所述第三初始化信号线图形9042同层同材料设置，能够在同一次构图工艺中 同时形成；所述第二复位信号线图形9051与所述第三复位信号线图形9052同层同材料设置，能够在同一次构图工艺中同时形成。
如图13a和图15所示，在一些实施例中，所述虚拟子像素80还包括：沿第一方向延伸的第一数据线图形808；所述显示子像素90包括沿第一方向延伸的第二数据线图形908；沿所述第一方向位于同一列的各所述虚拟子像素80中包括的所述第一数据线图形808，以及位于该列的各所述显示子像素90中包括的所述第二数据线图形908形成为一体结构。
具体地，上述设置沿所述第一方向位于同一列的各所述虚拟子像素80中包括的所述第一数据线图形808，以及位于该列的各所述显示子像素90中包括的所述第二数据线图形908形成为一体结构，使得所述第一数据线图形808和所述第二数据线图形908占用的布局空间最小化，更有利于显示基板的高分辨率发展趋势。而且，还能够通过一次构图工艺同时形成所述虚拟子像素80中包括的全部第一数据线图形808，以及所述显示子像素90中包括的全部第二数据线图形908，从而更好的简化了显示基板的制作流程，降低了显示基板的制作成本。
如图8所示，在一些实施例中，所述虚拟子像素80包括有源层图形，所述有源层图形包括：
相对设置的第一有源子图形8071和第二有源子图形8072，所述第一有源子图形8071和所述第二有源子图形8072均沿第一方向延伸；
设置于所述第一有源子图形8071与所述第二有源子图形8072之间的第三有源子图形8073，所述第三有源子图形8073的两端与所述第一有源子图形8071和所述第二有源子图形8072耦接，所述第三有源子图形8073的至少部分在所述基底上的正投影，与所述虚拟驱动晶体管的栅极在所述基底上的正投影交叠；
如图7所示，所述第一导电连接部8061远离所述虚拟驱动晶体管的栅极的部分在所述基底上的正投影，与所述有源层图形在所述基底上的正投影不交叠。
具体地，所述虚拟子像素80包括的有源层图形的具体结构多种多样，示 例性的，设置该有源层图形包括：所述第一有源子图形8071、所述第二有源子图形8072和所述第三有源子图形8073；这种设置方式使得所述第一导电连接部8061在所述基底上的正投影，位于所述第一有源子图形8071在所述基底上的正投影与所述第二有源子图形8072在所述基底上的正投影之间；所述第一导电连接部8061与所述虚拟驱动晶体管耦接的一端在所述基底上的正投影，与所述第三有源子图形8073在所述基底上的正投影交叠；所述第一导电连接部8061远离所述虚拟驱动晶体管的栅极的部分在所述基底上的正投影，与所述有源层图形在所述基底上的正投影不交叠。
上述设置方式简化了所述虚拟子像素80中包括的有源层图形的结构，有效缩小了该有源层图形占用的布局空间，从而更好的降低了所述虚拟子像素80在边缘区域的布局难度。
如图7和图8所示，在一些实施例中，所述虚拟子像素80还包括沿所述第一方向延伸的第一数据线图形808，所述第二有源子图形8072在所述基底上的正投影，位于所述第一数据线图形808在所述基底上的正投影与所述第一有源子图形8071在所述基底上的正投影之间；
所述第一数据线图形808在所述基底上的正投影与所述有源层图形在所述基底上的正投影不交叠。
具体地，在所述虚拟子像素80中，所述第一电源信号线图形801中沿所述第一方向延伸的部分在所述基底上的正投影，能够覆盖所述第二有源子图形8072在所述基底上的正投影的至少部分，所述第一数据线图形808与所述第一电源信号线图形801间隔设置，所述第一数据线图形808在所述基底上的正投影与所述有源层图形在所述基底上的正投影不交叠，不会为所述虚拟子像素驱动电路提供数据信号。
由于所述虚拟子像素80中包括的虚拟子像素驱动电路不是完整的电路结构，即所述虚拟子像素驱动电路无法实现正常的驱动功能，上述设置方式使得所述第一数据线图形808不会为所述虚拟子像素80提供数据信号，从而避免了所述虚拟子像素驱动电路由于接受了所述数据信号而异常工作，影响所述显示基板工作的稳定性的问题。
如图14和图15所示，在一些实施例中，所述显示子像素驱动电路还包括沿第一方向延伸的第三导电连接部8063，所述第三导电连接部8063的第一端与所述驱动晶体管的栅极(即第三晶体管T3的栅极203g)耦接，所述第三导电连接部8063的第二端分别与所述第一晶体管T1的第二极和所述第二晶体管T2的第二极耦接。
如图14和图15所示，在一些实施例中，所述第一晶体管T1的第二极与所述第二晶体管T2的第二极耦接，形成公共连接端(位于图15中N1节点附近的位置)，所述第三导电连接部8063的第二端在所述基底上的正投影与所述公共连接端在所述基底上的正投影交叠，在该交叠处所述第三导电连接部8063的第二端与所述公共连接端耦接。
如图14～图15所示，在一些实施例中，所述显示子像素90包括：第二电源信号线图形901、第二数据线图形908、第二栅线图形902、第二发光控制信号线图形903、第二复位信号线图形9051、第三复位信号线图形9052、第二初始化信号线图形9041和第三初始化信号线图形9042；所述第二电源信号线图形901的至少部分和所述第二数据线图形908沿第一方向延伸；所述第二栅线图形902、所述第二发光控制信号线图形903、所述第二复位信号线图形9051、所述第三复位信号线图形9052、所述第二初始化信号线图形9041和所述第三初始化信号线图形9042均沿第二方向延伸，所述第二方向与所述第一方向相交；
所述显示子像素90还包括显示子像素驱动电路，所述显示子像素驱动电路包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述第二栅线图形902耦接；
所述第二晶体管的栅极与所述第二复位信号线图形9051耦接，所述第二晶体管的第一极与所述第二初始化信号线图形9041耦接，所述第二晶体管的 第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与所述第二栅线图形902耦接，所述第四晶体管的第一极与所述第二数据线图形908耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述第二发光控制信号线图形903耦接，所述第五晶体管的第一极与所述第二电源信号线图形901耦接；
所述第六晶体管的栅极与所述第二发光控制信号线图形903耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述显示子像素90中的发光元件耦接；
所述第七晶体管的第二极与所述显示子像素90中的发光元件耦接，所述第七晶体管的栅极与所述第三复位信号线图形9052耦接，所述第七晶体管的第一极与所述第三初始化信号线图形9042耦接。
具体地，如图14和图15所示，以一个显示子像素驱动电路为例，该显示子像素驱动电路包括的各晶体管均采用P型晶体管，其中，第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与第二栅线图形902耦接，第一晶体管T1的源极S1与第三晶体管T3(即驱动晶体管)的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。
第二晶体管T2为双栅结构，第二晶体管T2的栅极202g与所述第二复位信号线图形9051耦接，第二晶体管T2的源极S2与第二初始化信号线图形9041耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
第四晶体管T4的栅极204g与所述第二栅线图形902耦接，第四晶体管T4的源极S4与第二数据线图形908耦接，第四晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。
第五晶体管T5的栅极205g与第二发光控制信号线图形903耦接，第五晶体管T5的源极S5与第二电源信号线图形901耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与第二发光控制信号线图形903耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏 极D6与发光元件EL的阳极耦接。
第七晶体管T7的栅极207g与所述第三复位信号线图形9052耦接，第七晶体管T7的漏极D7与所述发光元件EL的阳极耦接，第七晶体管T7的源极S7与所述第三初始化信号线图形9042耦接。
第二存储电容Cst的第三极板Cst1复用为第三晶体管T3的栅极203g，第二存储电容Cst的第四极板Cst2与所述第二电源信号线图形901耦接。
上述结构的显示子像素驱动电路在工作时，每个工作周期均包括第一复位时段P1、写入补偿时段P2、第二复位时段P3和发光时段P4。
在所述第一复位时段P1，所述第二复位信号线图形9051输入的第二复位信号处于有效电平，第二晶体管T2导通，将由所述第二初始化信号线图形9041传输的初始化信号输入至第三晶体管T3的栅极203g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位。
在写入补偿时段P2，所述第二复位信号处于非有效电平，第二晶体管T2截止，第二栅线图形902输入的栅极扫描信号处于有效电平，控制第一晶体管T1和第四晶体管T4导通，第二数据线图形908写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的源极S3，同时，第一晶体管T1和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在第二复位时段P3，所述栅极扫描信号处于非有效电平，第一晶体管T1和第四晶体管T4均截止，所述第三复位信号线图形9052输入的第三复位信号处于有效电平，控制第七晶体管T7导通，由所述第三初始化信号线图形9042传输的初始化信号输入至发光元件EL的阳极，控制发光元件EL不发光。
在发光时段P4，第二发光控制信号线图形903写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由第二电源信号 线图形901传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极，驱动对应的发光元件EL发光。
如图13a、图13c、图16～19所示，在制作上述显示子像素驱动电路时，显示子像素驱动电路对应的各膜层的布局如下：
沿远离基底40的方向上依次层叠设置的有源膜层、第一栅极绝缘层GI1、第一栅金属层、第二栅极绝缘层GI2、第二栅金属层、层间绝缘层ILD、第一源漏金属层；以及源漏金属层上还设置有无机绝缘层，平坦层以及阳极等膜层。
需要说明的是，本公开实施例中无机层可以采用氮化硅，氧化硅等无机材料；有机层，如平坦层，像素限定层等可以采用聚酰亚胺等有机材料，本公开不做限制。
如图16所示，有源膜层用于形成显示子像素驱动电路中各晶体管的沟道区(如：101pg～107pg)，源极形成区(如：101ps～107ps)和漏极形成区(如：101pd～107pd)，源极形成区和漏极形成区对应的有源膜层由于掺杂作用，导电性能会优于沟道区对应的有源膜层；有源膜层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
另外，值得注意，所述源极形成区和漏极形成区对应的有源膜层可直接作为对应的源极或漏极，或者，也可以采用金属材料制作与所述源极形成区接触的源极，采用金属材料制作与所述漏极形成区接触的漏极。
如图17所示，第一栅金属层用于形成显示子像素驱动电路中各晶体管的栅极(如：201g～207g)，以及显示基板包括的第二栅线图形902、第二发光控制信号线图形903、第二复位信号线图形9051和第三复位信号线图形9052等结构，每个显示子像素驱动电路中的第三晶体管T3的栅极203g均复用为该显示子像素驱动电路中的第二存储电容Cst的第三极板Cst1。
如图18所示，第二栅金属层用于形成第二存储电容Cst的第四极板Cst2，以及显示基板包括的第二初始化信号线图形9041和第三初始化信号线图形9042。
如图14、图15和19所示，第一源漏金属层用于形成显示子像素驱动电路中各晶体管的源极(如：S1～S7)和漏极(如：D1～D7)，以及显示基板包括的第二数据线图形908、第二电源信号线图形901和一些导电连接部。
更详细地说，请继续参阅图14～图17，第一晶体管T1的栅极201g覆盖第一沟道区101pg，第一晶体管T1的源极S1位于第一源极形成区101ps，第一晶体管T1的漏极D1位于第一漏极形成区101pd。
第二晶体管T2的栅极202g覆盖第二沟道区102pg，第二晶体管T2的源极S2位于第二源极形成区102ps，第二晶体管T2的漏极D2位于第二漏极形成区102pd。
第三晶体管T3的栅极203g覆盖第三沟道区103pg，第三晶体管T3的源极S3位于第三源极形成区103ps，第三晶体管T3的漏极D3位于第三漏极形成区103pd。
第四晶体管T4的栅极204g覆盖第四沟道区104pg，第四晶体管T4的源极S4位于第四源极形成区104ps，第四晶体管T4的漏极D4位于第四漏极形成区104pd。
第五晶体管T5的栅极205g覆盖第五沟道区105pg，第五晶体管T5的源极S5位于第五源极形成区105ps，第五晶体管T5的漏极D5位于第五漏极形成区105pd。
第六晶体管T6的栅极206g覆盖第六沟道区106pg，第六晶体管T6的源极S6位于第六源极形成区106ps，第六晶体管T6的漏极D6位于第六漏极形成区106pd。
第七晶体管T7的栅极207g覆盖第七沟道区107pg，第七晶体管T7的源极S7位于第七源极形成区107ps，第七晶体管T7的漏极D7位于第七漏极形成区107pd。
第三晶体管T3的栅极203g复用为存储电容Cst的第一极板Cst1，存储 电容Cst的第二极板Cst2与电源信号线图形VDD耦接。
另外，本公开提供的显示基板中，包括的多个显示子像素90可呈阵列分布，所述多个显示子像素90可划分为多行显示子像素90和多列显示子像素90，每行显示子像素90均包括沿第二方向排列的多个显示子像素90，每列显示子像素90均包括沿第一方向排列的多个显示子像素90，所述第一方向与所述第二方向相交。
为了简化子像素的布局空间，可将一行显示子像素90包括的第三复位信号线图形9052复用为相邻的下一行显示子像素90包括的第二复位信号线图形9051；同样的，可将一行显示子像素90对应的第三初始化信号线图形9042复用为相邻的下一行显示子像素90对应的第二初始化信号线图形9041。
如图15所示，在一些实施例中，以一个显示子像素90中包括的子像素驱动电路为例，在第一方向(如Y方向)上，第四晶体管T4的栅极204g、第一晶体管T1的栅极201g和第二晶体管T2的栅极202g均位于驱动晶体管的栅极(即第三晶体管T3的栅极203g)的第一侧，第七晶体管T7的栅极、第六晶体管T6的栅极206g、第五晶体管T5的栅极均位于驱动晶体管的栅极的第二侧。示例性的，所述驱动晶体管的栅极的第一侧和第二侧为沿第一方向相对的两侧，进一步地，驱动晶体管的栅极的第一侧可以为驱动晶体管的栅极的上侧，驱动晶体管的栅极的第二侧可以为驱动晶体管T1的栅极的下侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管的栅极的下侧，为驱动晶体管的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管的栅极的更远离IC的一侧。
在一些实施例中，如图15所示，在第二方向(如X方向)上，第四晶体管T4的栅极204g和第五晶体管T5的栅极205g均位于驱动晶体管的栅极的第三侧，第一晶体管T1的栅极201g和第六晶体管T6的栅极206g均位于驱动晶体管的栅极的第四侧。示例性的，驱动晶体管的栅极的第三侧和第四侧为沿第二方向相对的两侧；进一步地，驱动晶体管的栅极的第三侧可以为驱动晶体管的栅极的右侧，驱动晶体管的栅极的第四侧可以为驱动晶体管的栅极的左侧。所述左侧和右侧，例如在同一子像素中，第二数据线图形908 位于第二电源信号线图形901右侧，第二电源信号线图形901位于第二数据线图形908右侧。
如图6和图7所示，在一些实施例中，第一电位信号线图形包括第一电源信号线图形801；所述虚拟子像素80还包括：
第一数据线图形808、第一栅线图形802、第一发光控制信号线图形803、第一复位信号线图形805和第一初始化信号线图形804；所述第一电源信号线图形801的至少部分和所述第一数据线图形808均沿第一方向延伸，所述第一栅线图形802、所述第一发光控制信号线图形803、所述第一复位信号线图形805和所述第一初始化信号线图形804均沿第二方向延伸；
所述虚拟子像素驱动电路还包括：第二虚拟晶体管、第五虚拟晶体管和第六虚拟晶体管；
所述虚拟驱动晶体管的栅极与所述第一电源信号线图形801耦接，所述虚拟驱动晶体管的第一极与所述第五虚拟晶体管的第二极耦接，所述虚拟驱动晶体管的第二极与所述第六虚拟晶体管的第一极耦接；
所述第二虚拟晶体管的栅极与所述第一复位信号线图形805耦接，所述第二虚拟晶体管的第一极与所述第一初始化信号线图形804耦接，所述第二虚拟晶体管的第二极浮接；
所述第五虚拟晶体管的栅极与所述第一发光控制信号线图形803耦接，所述第五虚拟晶体管的第一极与所述第一电源信号线图形801耦接；
所述第六虚拟晶体管的栅极与所述第一发光控制信号线图形803耦接。
具体地，以一个虚拟子像素驱动电路为例，该虚拟子像素驱动电路包括的各虚拟晶体管均采用P型晶体管，所述第二虚拟晶体管T2'为双栅结构，第二虚拟晶体管T2'的栅极202g'与所述第一复位信号线图形805耦接，第二虚拟晶体管T2'的源极S2'与第一初始化信号线图形804耦接，第二虚拟晶体管T2'的漏极D2'浮接。
第五虚拟晶体管T5'的栅极205g'与第一发光控制信号线图形803耦接，第五虚拟晶体管T5'的源极S5'与第一电源信号线图形801耦接，第五虚拟晶体管T5'的漏极D5'与第三虚拟晶体管T3'的源极S3'耦接。
第六虚拟晶体管T6'的栅极206g'与第一发光控制信号线图形803耦接。
进一步地，可设置第六虚拟晶体管T6'的源极S6'与第三虚拟晶体管T3'的漏极D3'耦接，第六虚拟晶体管T6'的漏极D6'与发光元件EL的阳极耦接。
示例性的，所述虚拟子像素驱动电路还包括第七虚拟晶体管T7'，第七虚拟晶体管T7'的栅极207g'与沿第一方向相邻的下一个虚拟子像素80中的所述第一复位信号线图形805'耦接，第七虚拟晶体管T7'的漏极D7'与所述发光元件EL的阳极耦接，第七虚拟晶体管T7'的源极S7'与'所述第一初始化信号线图形804'耦接。
第一存储电容Cst'的第一极板Cst1'复用为第三虚拟晶体管T3'的栅极203g'耦接，第一存储电容Cst'的第二极板Cst2'与所述第一电源信号线图形801耦接。
正常的显示子像素90中，N1节点能够通过打孔与第一晶体管T1的漏极D1对应的有源图形(Poly图形)耦接，数据信号能够依次经过第四晶体管T4、第三晶体管T3和第一晶体管T1写入到N1节点，在该显示子像素90的发光阶段，漏电流会依次经过第五晶体管T5、第三晶体管T3和第六晶体管T6到达发光元件EL，使得发光元件EL发光。
在虚拟子像素80中，由于并未形成正常的第一虚拟晶体管T1'，使得虚拟子像素80中的N1节点无法正常接收数据信号，从而使得虚拟子像素80对应的虚拟子像素驱动电路无法实现正常的驱动功能。本申请中，通过设置所述第二导电连接部8062将N1节点与对应的第一电源信号线图形801耦接，避免了该N1节点处于浮接状态，对显示基板中的电源信号产生不良影响，有效提升了显示基板中电源信号的稳定性，保证了显示子像素驱动电路良好的工作性能。
需要说明，所述虚拟子像素驱动电路的具体结构可视实际布局情况来定，示例性的，所述虚拟子像素驱动电路不缺少虚拟晶体管，或者缺少的虚拟晶体管不限于如图6中的第一虚拟晶体管T1'和第四虚拟晶体管T4'。
另外，根据实际布局需要，位于不同的位置的虚拟子像素驱动电路包括的具体结构可能不同，示例性的，设置一些虚拟子像素驱动电路包括完整的 晶体管结构(如包括第一虚拟晶体管T1'至第七虚拟晶体管T7')，设置另一些虚拟子像素驱动电路包括部分虚拟晶体管。
如图7、图13a和图13b所示，在制作上述虚拟子像素驱动电路时，虚拟子像素驱动电路对应的各膜层的布局如下：
沿远离基底40的方向上依次层叠设置的有源膜层、第一栅极绝缘层GI1、第一栅金属层、第二栅极绝缘层GI2、第二栅金属层、层间绝缘层ILD、第一源漏金属层。
如图8所示，有源膜层用于形成虚拟子像素驱动电路中各虚拟晶体管的沟道区(如：102pg'～107pg')，源极形成区(如：102ps'～107ps')和漏极形成区(如：102pd'～107pd')，源极形成区和漏极形成区对应的有源膜层由于掺杂作用，导电性能会优于沟道区对应的有源膜层；有源膜层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
另外，值得注意，所述源极形成区和漏极形成区对应的有源膜层可直接作为对应的源极或漏极，或者，也可以采用金属材料制作与所述源极形成区接触的源极，采用金属材料制作与所述漏极形成区接触的漏极。
如图9所示，第一栅金属层用于形成虚拟子像素驱动电路中各虚拟晶体管的栅极(如：202g'～207g')，以及显示基板包括的第一栅线图形802、第一发光控制信号线图形803、第一复位信号线图形805等结构，每个虚拟子像素驱动电路中的第三虚拟晶体管T3'的栅极203g'均复用为该虚拟子像素驱动电路中的第一存储电容Cst'的第一极板Cst1'。
如图10所示，第二栅金属层用于形成第一存储电容Cst'的第二极板Cst2'，以及显示基板包括的第一初始化信号线图形804。
如图6、图7和11所示，第一源漏金属层用于形成虚拟子像素驱动电路中各虚拟晶体管的源极(如：S2'～S7')和漏极(如：D2'～D7')，以及显示基板包括的第一数据线图形808、第一电源信号线图形801、第一导电连接部8061和第二导电连接部8062。
更详细地说，请继续参阅图6～图9，第二虚拟晶体管T2'的栅极202g'覆 盖第二沟道区102pg'，第二虚拟晶体管T2'的源极S2'位于第二源极形成区102ps'，第二虚拟晶体管T2'的漏极D2'位于第二漏极形成区102pd'。
第三虚拟晶体管T3'的栅极203g'覆盖第三沟道区103pg'，第三虚拟晶体管T3'的源极S3'位于第三源极形成区103ps'，第三虚拟晶体管T3'的漏极D3'位于第三漏极形成区103pd'。
第五虚拟晶体管T5'的栅极205g'覆盖第五沟道区105pg'，第五虚拟晶体管T5'的源极S5'位于第五源极形成区105ps'，第五虚拟晶体管T5'的漏极D5'位于第五漏极形成区105pd'。
第六虚拟晶体管T6'的栅极206g'覆盖第六沟道区106pg'，第六虚拟晶体管T6'的源极S6'位于第六源极形成区106ps'，第六虚拟晶体管T6'的漏极D6'位于第六漏极形成区106pd'。
第七虚拟晶体管T7'的栅极207g'覆盖第七沟道区107pg'，第七虚拟晶体管T7'的源极S7'位于第七源极形成区107ps'，第七虚拟晶体管T7'的漏极D7'位于第七漏极形成区107pd'。
第三虚拟晶体管T3'的栅极203g'复用为第一存储电容Cst'的第一极板Cst1'，第一存储电容Cst'的第二极板Cst2'与第一电源信号线图形801耦接。
另外，本公开提供的显示基板中，包括的多个虚拟子像素80可呈阵列分布，所述多个虚拟子像素80可划分为多行虚拟子像素80和多列虚拟子像素80，每行虚拟子像素80均包括沿第二方向排列的多个虚拟子像素80，每列虚拟子像素80均包括沿第一方向排列的多个虚拟子像素80，所述第一方向与所述第二方向相交。
为了简化子像素的布局空间，可将一行虚拟子像素80包括第七虚拟晶体管T7'的栅极207g'与沿第一方向相邻的下一个显示子像素90包括的第二复位信号线图形9051耦接。
如图7所示，在一些实施例中，以一个虚拟子像素80中包括的子像素驱动电路为例，在第一方向(如Y方向)上，第二虚拟晶体管T2'的栅极202g'位于虚拟驱动晶体管的栅极(即第三虚拟晶体管T3'的栅极203g')的第一侧，第七虚拟晶体管T7'的栅极207g'、第六虚拟晶体管T6'的栅极206g'、第五虚 拟晶体管T5'的栅极205g'均位于虚拟驱动晶体管的栅极的第二侧。示例性的，所述虚拟驱动晶体管的栅极的第一侧和第二侧为沿第一方向相对的两侧，进一步地，虚拟驱动晶体管的栅极的第一侧可以为虚拟驱动晶体管的栅极的上侧，虚拟驱动晶体管的栅极的第二侧可以为虚拟驱动晶体管T1的栅极的下侧。所述下侧，例如虚拟基板的用于绑定IC的一侧为虚拟基板的下侧，虚拟驱动晶体管的栅极的下侧，为虚拟驱动晶体管的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为虚拟驱动晶体管的栅极的更远离IC的一侧。
在一些实施例中，如图7所示，在第二方向(如X方向)上，第五虚拟晶体管T5'的栅极205g'均位于虚拟驱动晶体管的栅极的第三侧，第六虚拟晶体管T6'的栅极206g'位于虚拟驱动晶体管的栅极的第四侧。示例性的，虚拟驱动晶体管的栅极的第三侧和第四侧为沿第二方向相对的两侧；进一步地，虚拟驱动晶体管的栅极的第三侧可以为虚拟驱动晶体管的栅极的右侧，虚拟驱动晶体管的栅极的第四侧可以为虚拟驱动晶体管的栅极的左侧。所述左侧和右侧，例如在同一子像素中，第一数据线图形808位于第一电源信号线图形801右侧，第一电源信号线图形801位于第一数据线图形808右侧。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
由于上述实施例提供的显示基板1中，通过设置所述第二导电连接部8062，将所述第一导电连接部8061与所述第一电源信号线图形801耦接，使得所述虚拟子像素驱动电路中的N1节点始终保持与所述第一电源信号线图形801相同的稳定电位，从而避免了由于所述N1节点浮接导致的显示基板1出现局部显示亮度不均匀的现象。因此，本公开实施例提供的显示装置在包括上述显示基板时同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，所述制作方法包括：
在基底上制作阵列排布的多个子像素；所述多个子像素包括位于显示面板中显示区域的多个显示子像素90，以及至少部分与所述多个显示子像素相邻的多个虚拟子像素80；
所述显示子像素90包括：显示子像素驱动电路，所述显示子像素驱动电路包括驱动晶体管(即第三晶体管T3)、第一晶体管T1和第二晶体管T2；所述驱动晶体管的栅极分别与所述第一晶体管T1的第二极(即漏极D1)和所述第二晶体管T2的第二极(即漏极D2)耦接；
所述虚拟子像素80包括：
第一电位信号线图形；
虚拟子像素驱动电路，所述虚拟子像素驱动电路包括虚拟驱动晶体管，以及与所述虚拟驱动晶体管的栅极耦接的第一导电连接部8061；
第二导电连接部8062，所述第二导电连接部8062分别与所述第一导电连接部8061和所述第一电位信号线图形耦接。
采用本公开实施例提供的制作方法制作的显示基板1中，通过设置所述第二导电连接部8062，将所述第一导电连接部8061与所述第一电位信号线图形耦接，使得所述虚拟子像素驱动电路中的N1节点始终保持与所述第一电位信号线图形相同的稳定电位，从而避免了由于所述N1节点浮接导致的显示基板1出现局部显示亮度不均匀的现象。
在一些实施例中，所述第一电位信号线图形包括第一电源信号线图形801；制作所述第一导电连接部8061、所述第二导电连接部8062和所述第一电位信号线图形的步骤具体包括：
通过一次构图工艺，形成一体结构的所述第一导电连接部8061、所述第二导电连接部8062和所述第一电源信号线图形801。
所述第一导电连接部8061、所述第二导电连接部8062和所述第一电源信号线图形801能够在一次构图工艺中同时形成，更好的简化了显示基板的制作流程，降低显示基板的制作成本。
需要说明，本公开的附图中，带有交叉线的小方框代表过孔的大致位置。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种显示基板，包括基底和在所述基底上阵列排布的多个子像素；所述多个子像素包括位于显示面板中显示区域的多个显示子像素，以及至少部分与所述多个显示子像素相邻的多个虚拟子像素；
    所述显示子像素包括：显示子像素驱动电路，所述显示子像素驱动电路包括驱动晶体管、第一晶体管和第二晶体管；所述驱动晶体管的栅极分别与所述第一晶体管的第二极和所述第二晶体管的第二极耦接；
    所述虚拟子像素包括：
    第一电位信号线图形；
    虚拟子像素驱动电路，所述虚拟子像素驱动电路包括虚拟驱动晶体管，以及与所述虚拟驱动晶体管的栅极耦接的第一导电连接部；以及，
    第二导电连接部，所述第二导电连接部分别与所述第一导电连接部和所述第一电位信号线图形耦接。
  2. 根据权利要求1所述的显示基板，其中，
    所述第一导电连接部沿第一方向延伸；
    所述第一电位信号线图形包括第一电源信号线图形，所述第一电源信号线图形包括沿所述第一方向延伸的第一部分；
    所述第二导电连接部沿第二方向延伸，所述第二方向与所述第一方向相交，所述第二导电连接部分别与所述第一导电连接部和所述第一电源信号线图形的第一部分耦接。
  3. 根据权利要求1所述的显示基板，其中，
    第一电位信号线图形包括第一电源信号线图形，所述第一电源信号线图形包括相耦接的第一部分和第二部分，所述第一部分沿第一方向延伸，所述第二部分沿第二方向延伸，所述第二方向与所述第一方向相交；
    所述第一导电连接部沿所述第一方向延伸；
    所述第二导电连接部沿所述第一方向延伸，所述第二导电连接部分别与所述第一导电连接部和所述第一电源信号线图形的第二部分耦接。
  4. 根据权利要求3所述的显示基板，其中，
    沿所述第二方向至少两个所述虚拟子像素中包括的所述第二部分耦接。
  5. 根据权利要求3所述的显示基板，其中，
    至少一个目标虚拟子像素中包括的所述第一部分和所述第二部分形成为一体结构；
    所述目标虚拟子像素为沿所述第一方向位于显示区域最外侧的虚拟子像素。
  6. 根据权利要求1所述的显示基板，其中，第一电位信号线图形包括第一电源信号线图形，所述第一导电连接部、所述第二导电连接部和所述第一电源信号线图形形成为一体结构。
  7. 根据权利要求1所述的显示基板，其中，所述虚拟子像素还包括：
    均沿第二方向延伸的第一栅线图形和第一发光控制信号线图形，所述第一栅线图形与所述第一发光控制信号线图形沿第一方向设置，所述虚拟驱动晶体管的栅极在所述基底上的正投影位于所述第一栅线图形在所述基底上的正投影与所述第一发光控制信号线图形在所述基底上的正投影之间；
    所述第一栅线图形在所述基底上的正投影，位于所述第二导电连接部在所述基底上的正投影与所述第一发光控制信号线图形在所述基底上的正投影之间。
  8. 根据权利要求7所述的显示基板，其中，所述显示子像素包括：
    均沿第二方向延伸的第二栅线图形和第二发光控制信号线图形；
    沿所述第二方向至少一个所述虚拟子像素中包括的所述第一栅线图形，以及沿所述第二方向与该虚拟子像素位于同一行，且与所述至少一个所述虚拟子像素相邻的显示子像素中包括的所述第二栅线图形形成为一体结构；
    沿所述第二方向至少一个所述虚拟子像素中包括的所述第一发光控制信号线图形，以及沿所述第二方向与该虚拟子像素位于同一行，且与所述至少一个所述虚拟子像素相邻的所述显示子像素中包括的所述第二发光控制信号线图形形成为一体结构。
  9. 根据权利要求1所述的显示基板，其中，第一电位信号线图形包括第 一电源信号线图形；所述虚拟子像素驱动电路还包括：
    第一存储电容，所述虚拟驱动晶体管的栅极复用为所述第一存储电容的第一极板，所述第一存储电容的第二极板位于所述第一极板背向所述基底的一侧，所述第二极板在所述基底上的正投影，与所述第一电源信号线图形中沿第一方向延伸的第一部分在所述基底上的正投影具有交叠区域，在该交叠区域所述第二极板与所述第一部分耦接；
    所述显示子像素还包括：
    第二电源信号线图形，所述第二电源信号线图形包括沿所述第一方向延伸的第三部分；
    所述显示子像素驱动电路还包括第二存储电容，所述驱动晶体管的栅极复用为所述第二存储电容的第三极板，所述第二存储电容的第四极板位于所述第三极板背向所述基底的一侧，所述第四极板在所述基底上的正投影与所述第二电源信号线图形的第三部分在所述基底上的正投影具有交叠区域，在该交叠区域所述第四极板与所述第三部分耦接；
    沿第二方向位于同一行的各所述虚拟子像素中包括的所述第二极板，以及位于该行的各所述显示子像素中包括的所述第四极板形成为一体结构。
  10. 根据权利要求1所述的显示基板，其中，所述显示子像素包括：
    第二电源信号线图形，所述第二电源信号线图形包括沿第一方向延伸的第三部分；
    沿所述第一方向位于同一列的各所述虚拟子像素中包括的第一电源信号线图形的第一部分，以及位于该列的各所述显示子像素中包括的所述第二电源信号线图形的第三部分形成为一体结构。
  11. 根据权利要求1所述的显示基板，其中，
    所述虚拟子像素还包括：沿第一方向延伸的第一数据线图形；
    所述显示子像素包括沿第一方向延伸的第二数据线图形；
    沿所述第一方向位于同一列的各所述虚拟子像素中包括的所述第一数据线图形，以及位于该列的各所述显示子像素中包括的所述第二数据线图形成为一体结构。
  12. 根据权利要求1所述的显示基板，其中，所述虚拟子像素包括有源层图形，所述有源层图形包括：
    相对设置的第一有源子图形和第二有源子图形，所述第一有源子图形和所述第二有源子图形均沿第一方向延伸；
    设置于所述第一有源子图形与所述第二有源子图形之间的第三有源子图形，所述第三有源子图形的两端与所述第一有源子图形和所述第二有源子图形耦接，所述第三有源子图形的至少部分在所述基底上的正投影，与所述虚拟驱动晶体管的栅极在所述基底上的正投影交叠；
    所述第一导电连接部远离所述虚拟驱动晶体管的栅极的部分在所述基底上的正投影，与所述有源层图形在所述基底上的正投影不交叠。
  13. 根据权利要求12所述的显示基板，其中，所述虚拟子像素还包括沿所述第一方向延伸的第一数据线图形，所述第二有源子图形在所述基底上的正投影，位于所述第一数据线图形在所述基底上的正投影与所述第一有源子图形在所述基底上的正投影之间；
    所述第一数据线图形在所述基底上的正投影与所述有源层图形在所述基底上的正投影不交叠。
  14. 根据权利要求1所述的显示基板，其中，第一电位信号线图形包括第一电源信号线图形；所述虚拟子像素还包括：
    第一数据线图形、第一栅线图形、第一发光控制信号线图形、第一复位信号线图形和第一初始化信号线图形；所述第一电源信号线图形的至少部分和所述第一数据线图形均沿第一方向延伸，所述第一栅线图形、所述第一发光控制信号线图形、所述第一复位信号线图形和所述第一初始化信号线图形均沿第二方向延伸；
    所述虚拟子像素驱动电路还包括：第二虚拟晶体管、第五虚拟晶体管和第六虚拟晶体管；
    所述虚拟驱动晶体管的栅极与所述第一电源信号线图形耦接，所述虚拟驱动晶体管的第一极与所述第五虚拟晶体管的第二极耦接，所述虚拟驱动晶体管的第二极与所述第六虚拟晶体管的第一极耦接；
    所述第二虚拟晶体管的栅极与所述第一复位信号线图形耦接，所述第二虚拟晶体管的第一极与所述第一初始化信号线图形耦接，所述第二虚拟晶体管的第二极浮接；
    所述第五虚拟晶体管的栅极与所述第一发光控制信号线图形耦接，所述第五虚拟晶体管的第一极与所述第一电源信号线图形耦接；
    所述第六虚拟晶体管的栅极与所述第一发光控制信号线图形耦接。
  15. 根据权利要求1所述的显示基板，其中，所述显示子像素驱动电路还包括沿第一方向延伸的第三导电连接部，所述第三导电连接部的第一端与所述驱动晶体管的栅极耦接，所述第三导电连接部的第二端分别与所述第一晶体管的第二极和所述第二晶体管的第二极耦接。
  16. 根据权利要求15所述的显示基板，其中，所述第一晶体管的第二极与所述第二晶体管的第二极耦接，形成公共连接端，所述第三导电连接部的第二端在所述基底上的正投影与所述公共连接端在所述基底上的正投影交叠，在该交叠处所述第三导电连接部的第二端与所述公共连接端耦接。
  17. 根据权利要求1所述的显示基板，其中，所述显示子像素包括：第二电源信号线图形、第二数据线图形、第二栅线图形、第二发光控制信号线图形、第二复位信号线图形、第三复位信号线图形、第二初始化信号线图形和第三初始化信号线图形；所述第二电源信号线图形的至少部分和所述第二数据线图形沿第一方向延伸；所述第二栅线图形、所述第二发光控制信号线图形、所述第二复位信号线图形、所述第三复位信号线图形、所述第二初始化信号线图形和所述第三初始化信号线图形均沿第二方向延伸，所述第二方向与所述第一方向相交；
    所述显示子像素驱动电路还包括：第四晶体管、第五晶体管、第六晶体管和第七晶体管；
    所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
    所述第一晶体管的栅极与所述第二栅线图形耦接；
    所述第二晶体管的栅极与所述第二复位信号线图形耦接，所述第二晶体 管的第一极与所述第二初始化信号线图形耦接；
    所述第四晶体管的栅极与所述第二栅线图形耦接，所述第四晶体管的第一极与所述第二数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第五晶体管的栅极与所述第二发光控制信号线图形耦接，所述第五晶体管的第一极与所述第二电源信号线图形耦接；
    所述第六晶体管的栅极与所述第二发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述显示子像素中的发光元件耦接；
    所述第七晶体管的第二极与所述显示子像素中的发光元件耦接，所述第七晶体管的栅极与所述第三复位信号线图形耦接，所述第七晶体管的第一极与所述第三初始化信号线图形耦接。
  18. 根据权利要求1所述的显示基板，其中，所述第一导电连接部与所述第二导电连接部为一体结构。
  19. 一种显示装置，包括如权利要求1～18中任一项所述的显示基板。
  20. 一种显示基板的制作方法，所述制作方法包括：
    在基底上制作阵列排布的多个子像素；所述多个子像素包括位于显示面板中显示区域的多个显示子像素，以及至少部分与所述多个显示子像素相邻的多个虚拟子像素；
    所述显示子像素包括：显示子像素驱动电路，所述显示子像素驱动电路包括驱动晶体管、第一晶体管和第二晶体管；所述驱动晶体管的栅极分别与所述第一晶体管的第二极和所述第二晶体管的第二极耦接；
    所述虚拟子像素包括：
    第一电位信号线图形；
    虚拟子像素驱动电路，所述虚拟子像素驱动电路包括虚拟驱动晶体管，以及与所述虚拟驱动晶体管的栅极耦接的第一导电连接部；
    第二导电连接部，所述第二导电连接部分别与所述第一导电连接部和所述第一电位信号线图形耦接。
  21. 根据权利要求20所述的显示基板的制作方法，其中，所述第一电位信号线图形包括第一电源信号线图形；制作所述第一导电连接部、所述第二导电连接部和所述第一电位信号线图形的步骤具体包括：
    通过一次构图工艺，形成一体结构的所述第一导电连接部、所述第二导电连接部和所述第一电源信号线图形。
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