WO2022111172A1 - 一种显示基板、显示装置 - Google Patents

一种显示基板、显示装置 Download PDF

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Publication number
WO2022111172A1
WO2022111172A1 PCT/CN2021/125811 CN2021125811W WO2022111172A1 WO 2022111172 A1 WO2022111172 A1 WO 2022111172A1 CN 2021125811 W CN2021125811 W CN 2021125811W WO 2022111172 A1 WO2022111172 A1 WO 2022111172A1
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Prior art keywords
transistor
substrate
signal line
coupled
orthographic projection
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PCT/CN2021/125811
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English (en)
French (fr)
Inventor
刘果
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/909,418 priority Critical patent/US20230097504A1/en
Publication of WO2022111172A1 publication Critical patent/WO2022111172A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • Organic Light-Emitting Diode (English: Organic Light-Emitting Diode, OLED for short) display devices are widely used in various fields due to their high brightness, low power consumption, fast response, high definition, good flexibility and high luminous efficiency.
  • the purpose of the present disclosure is to provide a display substrate and a display device.
  • a first aspect of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate; the sub-pixels include:
  • a reset signal line at least a part of the reset signal line extends along the first direction
  • an initialization signal line at least a portion of the initialization signal line extends along the first direction
  • the gate of the first transistor is coupled to the reset signal line
  • the first electrode of the first transistor is coupled to the initialization signal line
  • at least the first electrode of the first transistor is connected to the reset signal line.
  • the orthographic projection of the part on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate.
  • the sub-pixel further includes a conductive connection portion, the conductive connection portion is respectively coupled to the first electrode of the first transistor and the initialization signal line, and the conductive connection portion is on the substrate.
  • the orthographic projection is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate; along the second direction, the length of the conductive connection portion is smaller than the The distance between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate.
  • the orthographic projection of the conductive connection portion on the substrate does not overlap with the orthographic projection of the reset signal line on the substrate.
  • the orthographic projection of the first electrode of the first transistor on the substrate partially overlaps the orthographic projection of the initialization signal line on the substrate.
  • the initialization signal line includes a main body part and a protruding part, the main body part extends along the first direction, and the orthographic projection of the protruding part on the substrate is the same as the first part of the first transistor. Orthographic projections of the poles on the substrate at least partially overlap.
  • the sub-pixel further includes a grid line, and at least part of the grid line extends along the first direction;
  • the orthographic projection of the initialization signal line on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the gate line on the substrate.
  • the sub-pixel further includes a second transistor, the gate of the second transistor is coupled to the gate line, and the first electrode of the second transistor is coupled to the second electrode of the driving transistor , the second electrode of the second transistor is coupled to the gate of the driving transistor.
  • the orthographic projection of the initialization signal line on the substrate at least partially overlaps the orthographic projection of the gate of the second transistor on the substrate.
  • the second transistor includes a second active pattern, the second active pattern includes a conductor portion and two semiconductor portions, the conductor portion is respectively coupled to the two semiconductor portions;
  • the sub-pixel further includes a shielding pattern, the shielding pattern is coupled to the initialization signal line, the orthographic projection of the shielding pattern on the substrate, and the orthographic projection of the conductor portion on the substrate at least partially overlap.
  • the shielding pattern and the initialization signal line are formed into an integrated structure.
  • the shielding pattern includes a first sub-pattern and a second sub-pattern, the first sub-pattern extends along a second direction, the second direction intersects the first direction, and the second sub-pattern Extending in a first direction, an orthographic projection of the second sub-pattern on the substrate at least partially overlaps an orthographic projection of the conductor portion on the substrate.
  • the sub-pixel further includes a light-emitting element and a seventh transistor
  • the gate of the seventh transistor is coupled to the reset signal line in the next sub-pixel adjacent along the second direction
  • the seventh transistor The first electrode of the seventh transistor is coupled to the initialization signal line in the next sub-pixel adjacent along the second direction
  • the second electrode of the seventh transistor is coupled to the light-emitting element
  • the second direction is connected to the first intersect in one direction
  • the orthographic projection of the first pole of the seventh transistor on the substrate, the orthographic projection of the reset signal line located in the next sub-pixel adjacent along the second direction on the substrate, is the same as the orthographic projection along the second direction.
  • the initialization signal line in the adjacent next sub-pixel is between the orthographic projections on the substrate.
  • the first electrode of the seventh transistor and the first electrode of the first transistor in the next sub-pixel adjacent along the second direction form an integral structure.
  • the sub-pixels further include:
  • a light-emitting control signal line at least part of the light-emitting control signal line extends along the first direction;
  • the gate of the fourth transistor is coupled to the gate line, the first electrode of the fourth transistor is coupled to the data line, and the second electrode of the fourth transistor is coupled to the driver the first pole of the transistor is coupled;
  • the gate of the fifth transistor is coupled to the light-emitting control signal line, the first electrode of the fifth transistor is coupled to the power line, and the second electrode of the fifth transistor is coupled to the power line the first pole of the driving transistor is coupled;
  • the gate of the sixth transistor is coupled to the light-emitting control signal line, the first pole of the sixth transistor is coupled to the second pole of the driving transistor, the sixth transistor A diode is coupled to the light-emitting element;
  • a storage capacitor, the gate of the driving transistor is multiplexed as the first plate of the storage capacitor, and the second plate of the storage capacitor is coupled to the power line.
  • a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.
  • FIG. 1 is a schematic structural diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure
  • Fig. 2 is the working flow chart of the sub-pixel drive circuit in Fig. 1;
  • FIG. 3 is a first layout flowchart of the sub-pixel driving circuit in FIG. 1;
  • FIG. 4 is a second layout flowchart of the sub-pixel driving circuit in FIG. 1;
  • FIGS. 1 and 2 are schematic diagrams of the layout of the active layer and the first gate metal layer in FIGS. 1 and 2;
  • FIG. 6 is a schematic diagram of the layout of the active layer and the first source-drain metal layer in FIG. 2;
  • FIG. 7 is a schematic diagram of the layout of the second gate metal layer and the first source-drain metal layer in FIG. 2;
  • FIG. 8 is a schematic diagram of the layout of the active layer in FIG. 2;
  • FIG. 9 is a schematic diagram of the layout of the first gate metal layer in FIG. 2;
  • FIG. 10 is a schematic diagram of the layout of the second gate metal layer in FIG. 2;
  • FIG. 11 is a schematic diagram of the layout of the first source-drain metal layer in FIG. 2;
  • FIG. 12 is a schematic layout diagram of four sub-pixel driving circuits distributed in an array.
  • the present disclosure provides a display substrate, the display substrate includes a base and a plurality of sub-pixels disposed on the base, each sub-pixel includes a first transistor T1 , a second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the storage capacitor Cst.
  • Each sub-pixel further includes an initialization signal line VINT(N), a reset signal line RST(N), a gate line GA, an emission control signal line EM, a power supply line ELVDD, a data line DA, a first connection portion, a second connection portion and a first connection portion.
  • the initialization signal line VINT(N), the reset signal line RST(N), the gate line GA and the light emission control signal line EM all extend at least partially along the first direction.
  • Both the power supply line ELVDD and the data line DA extend at least partially along a second direction, and the second direction intersects with the first direction.
  • the orthographic projection of the initialization signal line VINT(N) on the substrate, the orthographic projection of the reset signal line RST(N) on the substrate, and the gate line GA on the substrate are sequentially arranged along the second direction.
  • the gate of the first transistor T1 is coupled to the reset signal line RST(N), and the first electrode of the first transistor T1 is coupled to the initialization signal line VINT(N) through the third connection portion 403 , the second pole of the first transistor T1 is coupled to the gate of the third transistor T3.
  • the gate of the second transistor T2 is coupled to the gate line GA, the first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3, and the first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3.
  • the diode is coupled to the gate of the third transistor T3 through the first connection portion 401 .
  • the gate of the fourth transistor T4 is coupled to the gate line GA, the first electrode of the fourth transistor T4 is coupled to the data line DA, and the second electrode of the fourth transistor T4 is coupled to the third electrode The first pole of the transistor T3 is coupled.
  • the gate of the fifth transistor T5 is coupled to the light-emitting control signal line EM, the first electrode of the fifth transistor T5 is coupled to the power line ELVDD, and the second electrode of the fifth transistor T5 is coupled to the power line ELVDD.
  • the first pole of the third transistor T3 is coupled.
  • the gate of the sixth transistor T6 is coupled to the light-emitting control signal line EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the third transistor T3, and the sixth transistor T6 The second pole of is coupled to the light-emitting element in the sub-pixel.
  • the gate of the seventh transistor T7 is coupled to the reset signal line RST(N+1) in the next sub-pixel adjacent along the second direction, and the first pole of the seventh transistor T7 is connected through the second connection part 402 is coupled to the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction, and the second pole of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.
  • the gate of the third transistor T3 is multiplexed as the first plate of the storage capacitor, and the second plate of the storage capacitor is coupled to the power line ELVDD.
  • connection portion is multiplexed into the third connection portion in the next sub-pixel adjacent in the second direction.
  • the third connection portion 403 since the distance between the first pole of the first transistor T1 and the initialization signal line VINT(N) is relatively long, it is necessary to set the third connection portion 403 to extend along the second direction
  • the length of the third connection portion 403 is relatively large, which not only affects the transmittance of the display substrate to a certain extent, is not conducive to the working stability of the display substrate, but also increases the difficulty of the layout of the display substrate.
  • an embodiment of the present disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate; the sub-pixels include:
  • a first transistor T1 the gate of the first transistor T1 is coupled to the reset signal line RST(N), the first pole of the first transistor T1 is coupled to the initialization signal line VINT(N), The second pole of the first transistor T1 is coupled to the gate of the driving transistor (ie, the third transistor T3 ); the orthographic projection of at least part of the first pole of the first transistor T1 on the substrate is located at the between the orthographic projection of the reset signal line RST(N) on the substrate and the orthographic projection of the initialization signal line VINT(N) on the substrate;
  • the first direction includes a horizontal inversion
  • the second direction includes a vertical direction
  • the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, and an interlayer that are sequentially stacked along a direction away from the substrate. Insulation layer, first source-drain metal layer and flat layer, etc.
  • the first gate metal layer includes the reset signal line RST(N) and the gate line GA
  • the second gate metal layer includes the initialization signal line VINT(N).
  • the sub-pixel includes a pixel driving circuit and a light-emitting element, and the pixel driving circuit is coupled to an anode of the light-emitting element for driving the light-emitting element to emit light.
  • the plurality of pixel driving circuits included in the plurality of sub-pixels are distributed on the substrate in an array.
  • the plurality of pixel driving circuits can be divided into multi-row pixel driving circuits and multi-column pixel driving circuits.
  • the plurality of rows of pixel driving circuits are arranged along the second direction, and each row of pixel driving circuits includes a plurality of pixel driving circuits arranged along the first direction.
  • the plurality of columns of pixel driving circuits are arranged along the first direction, and each column of pixel driving circuits includes a plurality of pixel driving circuits arranged along the second direction.
  • the pixel driving circuit includes a driving transistor, a first transistor T1 and a seventh transistor T7, the first transistor T1 is used for resetting the gate of the driving transistor, and the first transistor T1 is used to reset the gate of the driving transistor.
  • One pole is coupled to the initialization signal line VINT(N)
  • the seventh transistor T7 is used for resetting the anode of the light-emitting element
  • the first pole of the seventh transistor T7 is connected to the lower side adjacent to the second direction.
  • the initialization signal line VINT(N+1) in one sub-pixel is coupled.
  • the reset signal lines RST(N) correspondingly coupled to each pixel driving circuit are sequentially coupled to form an integrated structure, and the correspondingly coupled initialization signal lines VINT(N) of each pixel driving circuit are sequentially coupled.
  • the coupling forms an integrated structure, and the correspondingly coupled gate lines GA of each pixel driving circuit are sequentially coupled to form an integrated structure.
  • each sub-pixel further includes a light-emitting control signal line EM, a power supply line ELVDD and a data line DA
  • the correspondingly coupled light-emitting control signal lines EM of each pixel driving circuit are sequentially coupled to form: All-in-one structure.
  • the correspondingly coupled power lines ELVDD of each pixel driving circuit are sequentially coupled to form an integrated structure.
  • the corresponding data lines DA coupled to each pixel driving circuit are sequentially coupled to form an integrated structure.
  • At least a part of the first electrode of the first transistor T1 is located at the reset signal line RST by setting the orthographic projection of the first electrode on the substrate.
  • the shielding area of the conductive connection portion 404 is reduced, so that the display substrate has good transmittance, and the display substrate is applied under a screen that requires transmittance When used in a sensor product, it can ensure that the sensor product has good functionality.
  • the display substrate provided by the embodiment of the present disclosure by reducing the size of the conductive connection portion 404, it is more beneficial to avoid crosstalk between the conductive connection portion 404 and other structures around it, thereby effectively improving the working efficiency of the display substrate. stability.
  • the layout airborne occupied by the conductive connection portion 404 is reduced, thereby better reducing the overall layout difficulty of the display substrate.
  • the sub-pixel further includes a conductive connection portion 404 , and the conductive connection portion 404 is respectively connected to the first electrode of the first transistor T1 and the initialization signal line.
  • VINT(N) coupling, the orthographic projection of the conductive connection portion on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate ;
  • the length of the conductive connection portion 404 is smaller than the orthographic projection of the reset signal line RST(N) on the substrate and the initialization signal line VINT(N) on the substrate The distance between the orthographic projections.
  • the conductive connection portion 404 is provided with the same layer and material as the power line ELVDD and the data line DA.
  • the conductive connection portion 404 extends along the second direction.
  • the length of the conductive connection portion 404 in the second direction is less than or equal to the maximum width of the initialization signal line VINT(N) in the second direction.
  • the orthographic projection of the first end of the conductive connection portion 404 on the substrate and the orthographic projection of the first pole of the first transistor T1 on the substrate Having a first overlapping area
  • the first end of the conductive connection part 404 is coupled with the first electrode of the first transistor T1 through the first via hole 801;
  • the second end of the conductive connection part 404 is in the
  • the orthographic projection on the substrate has a second overlapping area with the orthographic projection of the main body portion 61 on the substrate and the orthographic projection of the protruding portion 60 on the substrate respectively.
  • the ends are coupled with the main body portion 61 and the protruding portion 60 through a second via hole 802 .
  • the first via hole penetrates the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer; the second via hole penetrates the interlayer insulating layer and the second gate insulating layer.
  • the length of the conductive connection portion 404 is smaller than the orthographic projection of the reset signal line RST(N) on the substrate and the initialization signal
  • the distance between the orthographic projections of the line VINT(N) on the substrate effectively reduces the size of the conductive connection portion 404 . Therefore, in the display substrate provided by the above-mentioned embodiment, the shielding area of the conductive connection portion 404 is reduced, so that the display substrate has good transmittance, and the display substrate is applied to the screen with a requirement for transmittance.
  • the display substrate provided by the embodiment of the present disclosure, by reducing the size of the conductive connection portion 404, it is more beneficial to avoid crosstalk between the conductive connection portion 404 and other structures around it, thereby effectively improving the working efficiency of the display substrate. stability.
  • the layout airborne occupied by the conductive connection portion 404 is reduced, thereby better reducing the overall layout difficulty of the display substrate.
  • the orthographic projection of the conductive connection portion 404 on the substrate is not intersected with the orthographic projection of the reset signal line RST(N) on the substrate stack.
  • the above arrangement avoids the generation of overlapping capacitance between the conductive connection portion 404 and the reset signal line RST(N), which is beneficial to avoid generation of the conductive connection portion 404 and the reset signal line RST(N).
  • the crosstalk effectively improves the stability of the display substrate.
  • the sub-pixel further includes: a driving transistor, the first transistor T1 and the second transistor T2;
  • the gate of the second transistor T2 is coupled to the gate line GA, the first electrode of the second transistor T2 is coupled to the second electrode of the driving transistor, and the second electrode of the second transistor T2 coupled to the gate of the driving transistor.
  • the reset signal line RST(N) is multiplexed as the gate of the first transistor T1.
  • the first transistor T1 is a double gate structure, the first transistor T1 includes a first active pattern 101, at least a part of the first active pattern 101 is an n-shaped structure, the first active pattern 101
  • the orthographic projection of the active pattern 101 on the substrate and the orthographic projection of the reset signal line RST(N) on the substrate can form two independent overlapping regions.
  • the first end of the first active pattern 101 serves as the first pole of the first transistor T1
  • the second end of the second active pattern 102 serves as the second end of the first transistor T1. pole.
  • the second transistor T2 is a double gate structure, the second transistor T2 includes a second active pattern 102, and the second active pattern 102 is similar shape structure.
  • the second transistor T2 is a compensation transistor for compensating the threshold voltage of the driving transistor.
  • the orthographic projection of the reset signal line RST(N) on the substrate is the same as the orthographic projection of the reset signal line RST(N) on the substrate.
  • the distance between the first pole of the first transistor T1 and the initialization signal line VINT(N) is relatively close, so that the conductive connection part 404
  • the initialization signal line VINT(N) is connected to the first electrode of the first transistor T1 in the sub-pixel to which it belongs, the size of the conductive connection portion 404 can be effectively reduced, and the shielding area of the conductive connection portion 404 can be reduced. Therefore, the display substrate provided by the above embodiments has good transmittance, and when the display substrate is applied to an under-screen sensor product requiring transmittance, the sensor product can be guaranteed to have good functionality.
  • the orthographic projection of the first electrode of the first transistor T1 on the substrate is set, and the initialization signal line VINT(N) is on the substrate The orthographic portion of the overlap.
  • the above setting method further reduces the distance between the first pole of the first transistor T1 and the initialization signal line VINT(N), and the initialization signal line VINT(N) is connected to the initialization signal line VINT(N) through the conductive connection portion 404.
  • the size of the conductive connection part 404 can be further reduced, and the shielding area of the conductive connection part 404 can be reduced.
  • the initialization signal line VINT(N) includes a main body portion 61 and a protruding portion 60 , and the main body portion 61 extends along the first direction,
  • the orthographic projection of the protrusion 60 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first transistor T1 on the substrate.
  • the main body portion 61 and the protruding portion 60 are formed as an integral structure.
  • the orthographic projection of the protruding portion 60 on the substrate the orthographic projection of the main body portion 61 on the substrate and the orthographic projection of the reset signal line RST(N) on the substrate between.
  • the orthographic projection of the main body portion 61 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the first transistor T1 on the substrate.
  • the display substrate provided by the above embodiment, by setting the orthographic projection of the protruding portion 60 on the substrate to at least partially overlap with the orthographic projection of the first electrode of the first transistor T1 on the substrate, reducing The distance between the first pole of the first transistor T1 and the initialization signal line VINT(N) is reduced, and the initialization signal line VINT(N) is connected to the first in the sub-pixels to which it belongs through the conductive connection part 404 .
  • the size of the conductive connection portion 404 can be effectively reduced, and the shielding area of the conductive connection portion 404 can be reduced.
  • the above arrangement also avoids a large overlapping area between the first electrode of the first transistor T1 and the initialization signal line VINT(N), and avoids that the first electrode of the first transistor T1 and the The initialization signal line VINT(N) generates a large parasitic capacitance, which affects the working stability of the display substrate.
  • the sub-pixel further includes: a gate line GA, at least a part of the gate line GA extends along the first direction; the initialization signal line
  • the orthographic projection of VINT(N) on the substrate is located between the orthographic projection of the reset signal line RST(N) on the substrate and the orthographic projection of the gate line GA on the substrate.
  • the orthographic projection of the reset signal line RST(N) on the substrate is the same as the normal projection of the first electrode of the first transistor T1 on the substrate.
  • the distance between the first pole of the first transistor T1 and the initialization signal line VINT(N) is close, so that the conductive connection portion 404 is connected to the initialization signal line VINT(N) and the first electrode of the first transistor T1 in the sub-pixel to which it belongs, the size of the conductive connection portion 404 can be effectively reduced.
  • the orthographic projection of the initialization signal line VINT(N) on the substrate is the same as the gate 202g of the second transistor T2
  • the orthographic projections on the substrate at least partially overlap.
  • the orthographic projection of the main body portion 61 on the substrate is set to at least partially overlap with the orthographic projection of the gate 202g of the second transistor T2 on the substrate.
  • the above arrangement makes the main body portion 61 closer to the second pole of the second transistor T2, which is beneficial to the stability of the second pole of the second transistor T2.
  • the gates of the driving transistors are coupled, so that the potential of the gates of the driving transistors is not easily affected by external crosstalk.
  • the second transistor T2 includes a second active pattern 102 , and the second active pattern 102 includes a conductor portion 1021 and two semiconductor portions 1022, the conductor portions 1021 are respectively coupled to the two semiconductor portions 1022;
  • the sub-pixel further includes a shielding pattern 62, the shielding pattern 62 is coupled to the initialization signal line VINT(N), and the orthographic projection of the shielding pattern 62 on the substrate is where the conductor portion 1021 is located.
  • the orthographic projections on the substrates at least partially overlap.
  • the second active pattern 102 includes a conductor part 1021 and two semiconductor parts 1022, and the conductor part 1021 has better electrical conductivity than the two semiconductor parts 1022, where the two semiconductor parts 1022 are located.
  • the orthographic projection on the substrate is located inside the orthographic projection of the gate of the second transistor T2 on the substrate.
  • an initialization signal with a fixed potential is transmitted on the initialization signal line VINT(N), and the shield pattern 62 is coupled to the initialization signal line VINT(N), so that the shield pattern 62 has a fixed potential .
  • the shielding pattern 62 by setting the orthographic projection of the shielding pattern 62 on the substrate to at least partially overlap with the orthographic projection of the conductor portion 1021 on the substrate, so that the shielding pattern 62 It has a good shielding effect on the conductor part 1021, and avoids the influence of the data signal jump on the data line DA in the adjacent sub-pixels along the first direction on the conductor part 1021, thus ensuring the The stability of the operation of the second transistor T2 and its coupled driving transistor.
  • the shielding pattern 62 is effectively reduced, the shielding area of the shielding pattern 62 is reduced, and the display substrate has good transparency.
  • the display substrate is applied to an under-screen sensor product that requires transmittance, it can ensure that the sensor product has good functionality.
  • the display substrate provided by the above-mentioned embodiment, by reducing the size of the shielding pattern 62, it is more beneficial to avoid parasitic capacitance between the shielding pattern 62 and other surrounding structures, which effectively improves the stability of the display substrate. .
  • the layout space occupied by the shielding pattern 62 is reduced, thereby better reducing the overall layout difficulty of the display substrate.
  • the shield pattern 62 and the initialization signal line VINT(N) are arranged to form an integral structure.
  • the above arrangement enables the shielding pattern 62 and the initialization signal line VINT(N) to be formed in the same patterning process, thereby simplifying the manufacturing process of the display substrate and saving the manufacturing cost of the display substrate. .
  • the shielding pattern 62 includes a first sub-graphic 620 and a second sub-graphic 621 , and the first sub-graphic 620 is along the The second direction extends in a second direction, the second direction intersects with the first direction, the second sub-pattern 621 extends along the first direction, and the orthographic projection of the second sub-pattern 621 on the substrate corresponds to the conductor The orthographic projections of portion 1021 on the substrate at least partially overlap.
  • the first sub-pattern 620 and the second sub-pattern 621 form an integral structure.
  • the shielding pattern 62 is formed in an L-shaped structure.
  • the width of the first sub-pattern 620 in the direction perpendicular to its own extension is smaller than the width of the second sub-pattern 621 in the direction perpendicular to its own extension.
  • the shielding pattern 62 can play a good shielding role while occupying A smaller layout space is provided, which is beneficial to improve the resolution of the display substrate.
  • the sub-pixel further includes a light-emitting element and a seventh transistor T7, and the gate of the seventh transistor T7 is adjacent to the next sub-pixel along the second direction.
  • the reset signal line RST(N+1) in the transistor T7 is coupled to the first pole of the seventh transistor T7 and the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction is coupled,
  • the second pole of the seventh transistor T7 is coupled to the light emitting element, and the second direction intersects the first direction;
  • the seventh transistor T7 is turned on under the control of the reset signal line RST(N+1) in the next sub-pixel adjacent along the second direction, and connects the anode of the light-emitting element with the second sub-pixel along the second direction.
  • the initialization signal lines VINT(N+1) in the next sub-pixel adjacent in the direction are coupled together to realize the anode reset of the light-emitting element.
  • the orthographic projection of the initialization signal line VINT(N+1) on the substrate is located where the reset signal line RST(N+1) is located. between the orthographic projection on the substrate and the orthographic projection of the grid line GA on the substrate.
  • the display substrate provided by the above embodiment, by setting the orthographic projection of the first pole of the seventh transistor T7 on the substrate, the reset signal line RST (N +1) The orthographic projection on the substrate, and the orthographic projection of the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction on the substrate, so that the first The distance between the first pole of the seven transistor T7 and the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction is relatively close, so that the seventh transistor is connected through the conductive connection part 404
  • the size of the conductive connection portion 404 can be effectively reduced, and the size of the conductive connection portion 404 can be reduced. Covered area.
  • the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 in the next sub-pixel adjacent to the second direction are formed as All-in-one structure.
  • the above arrangement enables the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 in the next sub-pixel adjacent to the second direction to be connected to the initialization signal through the same conductive connection portion 404 line VINT(N), thereby further improving the transmittance of the array substrate.
  • the sub-pixels further include:
  • a light-emitting control signal line EM at least part of the light-emitting control signal line EM extends along the first direction;
  • a power supply line ELVDD at least a portion of the power supply line ELVDD extends along the second direction;
  • a data line DA at least a portion of the data line DA extends along the second direction;
  • the fourth transistor T4 the gate of the fourth transistor T4 is coupled to the gate line GA, the first electrode of the fourth transistor T4 is coupled to the data line DA, the fourth transistor T4 is A diode is coupled to the first electrode of the driving transistor;
  • a fifth transistor T5 the gate of the fifth transistor T5 is coupled to the light-emitting control signal line EM, the first electrode of the fifth transistor T5 is coupled to the power line ELVDD, the fifth transistor T5 The second pole of is coupled to the first pole of the driving transistor;
  • a sixth transistor T6 the gate of the sixth transistor T6 is coupled to the light-emitting control signal line EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor.
  • the second pole of the six transistors T6 is coupled to the light-emitting element;
  • a storage capacitor, the gate of the driving transistor is multiplexed as the first plate of the storage capacitor, and the second plate of the storage capacitor is coupled to the power line ELVDD.
  • the sub-pixels include sub-pixel driving circuits distributed in an array.
  • the sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor.
  • the transistors included in the sub-pixel driving circuit are all P-type transistors, the first electrode of each transistor includes a source electrode, and the second electrode of each transistor includes a drain electrode.
  • the first transistor T1 (ie, the reset transistor) has a double-gate structure, the gate 201g of the first transistor T1 is coupled to the reset signal line RST(N), and the source S1 of the first transistor T1 passes through the first via 801,
  • the conductive connection portion 404 and the second via hole 802 are coupled to the initialization signal line VINT(N), and the drain D1 of the first transistor T1 is coupled to the drain D2 of the second transistor T2.
  • the first via hole 801 penetrates the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer; the second via hole 802 penetrates the interlayer insulating layer.
  • the second transistor T2 has a double gate structure, the gate 202g of the second transistor T2 (ie the compensation transistor) is coupled to the gate line GA, the source S2 of the second transistor T2 and the drain of the third transistor T3 (ie the driving transistor) D3 is coupled, and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3 through the third via hole 803 , the first connection portion 401 and the fourth via hole 804 .
  • the third via hole 803 penetrates the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer; the fourth via hole 804 penetrates the second gate insulating layer and the interlayer insulating layer.
  • the gate 204g of the fourth transistor T4 (ie, the data writing transistor) is coupled to the gate line GA, the source S4 of the fourth transistor T4 is coupled to the data line DA through the fifth via 805, and the fourth transistor T4 The drain D4 is coupled to the source S3 of the third transistor T3.
  • the fifth via hole 805 penetrates through the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer.
  • the gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line EM, the source S5 of the fifth transistor T5 is coupled to the power line ELVDD through the sixth via 806, and the drain D5 of the fifth transistor T5 is coupled to the third transistor The source S3 of T3 is coupled.
  • the sixth via hole 806 penetrates through the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer.
  • the gate 206g of the sixth transistor T6 is coupled to the light-emitting control signal line EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 passes through the seventh via hole 807.
  • the fourth connection portion 405 and the via hole penetrating the flat layer are coupled to the anode of the light emitting element EL.
  • the seventh via hole 807 penetrates through the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer.
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line RST(N+1) in the next sub-pixel adjacent along the second direction, and the drain D7 of the seventh transistor T7 is connected to the drain D7 of the sixth transistor T6.
  • the drain electrode D6 is coupled, and the source electrode S7 of the seventh transistor T7 is coupled to the initialization signal line VINT(N+1) in the next sub-pixel adjacent along the second direction through the eighth via hole 808 .
  • the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the power line ELVDD through at least one ninth via 809 .
  • the ninth via hole 809 penetrates through the interlayer insulating layer.
  • each working cycle includes a first reset period P1 , a write compensation period P2 , a second reset period P3 and a light-emitting period P4 .
  • the reset signal input from the reset signal line RST(N) is at an active level
  • the first transistor T1 is turned on
  • the initialization signal transmitted from the initialization signal line VINT(N) is input to the third transistor T3
  • the gate 203g of the third transistor T3 is reset, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared to reset the gate 203g of the third transistor T3.
  • the reset signal is at an inactive level
  • the first transistor T1 is turned off
  • the gate scan signal input from the gate line GA is at an active level
  • the second transistor T2 and the fourth transistor T4 are controlled to be turned on
  • the data line DA writes a data signal and transmits it to the source S3 of the third transistor T3 through the fourth transistor T4, and at the same time, the second transistor T2 and the fourth transistor T4 are turned on, so that the third transistor T3 is formed into a diode structure , so the second transistor T2, the third transistor T3 and the fourth transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled.
  • Vdata+Vth is reached, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the gate scan signal is at an inactive level
  • the second transistor T2 and the fourth transistor T4 are both turned off
  • the reset signal input from the reset signal line RST(N+1) is at an active level
  • the control The seventh transistor T7 is turned on, the initialization signal transmitted from the initialization signal line pattern VINT(N+1) is input to the anode of the light-emitting element EL, and the light-emitting element EL is controlled not to emit light.
  • the light-emitting control signal written in the light-emitting control signal line pattern EM is at an active level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power line is input to the third transistor T3.
  • each film layer corresponding to the sub-pixels is as follows:
  • It includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source A drain metal layer, a first flat layer, a second source-drain metal layer, a second flat layer, an anode layer, an organic light-emitting functional layer and a cathode layer.
  • the cathode is connected to the negative power signal ELVSS.
  • the gate electrode 204g of the fourth transistor T4 , the gate electrode 201g of the first transistor T1 , and the gate electrode of the second transistor T2 The electrode 202g is located on the first side of the gate of the driving transistor (ie, the gate 203g of the third transistor T3), the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all on the first side. on the second side of the gate of the drive transistor.
  • the first side and the second side of the gate of the driving transistor are opposite sides along the second direction, and further, the first side of the gate of the driving transistor may be the upper side of the gate of the driving transistor.
  • the second side of the gate of the driving transistor may be the lower side of the gate of the driving transistor.
  • the lower side for example, the side of the display substrate used to bind the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor that is closer to the IC.
  • the upper side is the opposite side to the lower side, eg the side of the gate of the drive transistor that is further away from the IC.
  • the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, the gate 202g of the second transistor T2 and the gate of the sixth transistor T6
  • the poles 206g are all located on the fourth side of the gate of the drive transistor.
  • the third side and the fourth side of the gate of the driving transistor are opposite sides along the first direction; further, the third side of the gate of the driving transistor may be the left side of the gate of the driving transistor, The fourth side of the gate of the driving transistor may be the right side of the gate of the driving transistor.
  • Embodiments of the present disclosure also provide a display device, including the display substrate provided by the above embodiments.
  • the orthographic projection of the reset signal line on the substrate is the same as the orthographic projection of the gate line on the substrate.
  • the distance between the initialization signal line and the first pole of the first transistor in the sub-pixel to which it belongs, and the first pole of the seventh transistor in the previous sub-pixel adjacent in the second direction are relatively close, so that the initialization signal line is connected to the first electrode of the first transistor in the sub-pixel to which it belongs through the conductive connection portion 404, and the initialization signal line is connected to the adjacent in the second direction through the conductive connection portion 404.
  • the size of the conductive connection portion 404 can be effectively reduced, and the shielding area of the conductive connection portion 404 can be reduced. Therefore, the display substrate provided by the above embodiments has good transmittance, and when the display substrate is applied to an under-screen sensor product requiring transmittance, the sensor product can be guaranteed to have good functionality.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer.
  • An embodiment of the present disclosure also provides a method for fabricating a display substrate, the fabrication method includes: fabricating a plurality of sub-pixels on a substrate, and the step of fabricating each sub-pixel specifically includes:
  • a first transistor is fabricated, the gate of the first transistor is coupled to the reset signal line, the first electrode of the first transistor is coupled to the initialization signal line, and the first electrode of the first transistor is connected to the reset signal line. At least part of the orthographic projection on the substrate is located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the initialization signal line on the substrate.
  • the reset signal line RST(N) is located at the bottom of the substrate. Between the orthographic projection on the substrate and the orthographic projection of the initialization signal line VINT(N) on the substrate, the initialization signal line VINT(N) and the first transistor T1 in the sub-pixel to which the initialization signal line VINT(N) belongs.
  • the distance between one pole and the first pole of the seventh transistor T7 in the adjacent previous sub-pixel along the second direction is relatively close, so that the initialization signal line VINT(N) is connected through the conductive connection part 404
  • the first pole of the first transistor T1 in the sub-pixel to which it belongs, and the connection between the initialization signal line VINT(N) and the seventh transistor T7 in the previous sub-pixel adjacent in the second direction through the conductive connection part 404 When the first pole is used, the size of the conductive connection portion 404 can be effectively reduced. Therefore, in the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, the shielding area of the conductive connection portion 404 is reduced, so that the display substrate has good transmittance.
  • the display substrate When the display substrate is applied to the transmittance When it is required to be used in a sensor product under the screen, it can ensure that the sensor product has good functionality. Moreover, in the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, by reducing the size of the conductive connection portion 404, it is more beneficial to avoid crosstalk between the conductive connection portion 404 and other structures around it, effectively improving the The stability of the display substrate operation is improved. In addition, by reducing the size of the conductive connection portion 404, the layout air drop occupied by the conductive connection portion 404 is reduced, thereby better reducing the overall layout difficulty of the display substrate.

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Abstract

本公开提供一种显示基板、显示装置。所述显示基板包括：基底和设置于所述基底上的多个子像素；所述子像素包括：复位信号线，初始化信号线和第一晶体管，所述复位信号线的至少部分沿第一方向延伸；所述初始化信号线的至少部分沿所述第一方向延伸；第一晶体管的栅极与复位信号线耦接，第一晶体管的第一极与初始化信号线耦接，第一晶体管的第一极的至少部分在基底上的正投影，位于复位信号线在基底上的正投影与初始化信号线在基底上的正投影之间。

Description

一种显示基板、显示装置
相关申请的交叉引用
本申请主张在2020年11月25日在中国提交的中国专利申请号No.202011337907.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示装置。
背景技术
有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示器件以其亮度高、功耗低、响应快、清晰度高、柔性好和发光效率高等优点被广泛应用在各个领域。
在将OLED显示器件应用于对透过率有要求的屏下感测(sensor)产品中时，若OLED显示器件的透过率不达标，可能会导致sensor产品功能性不良。
发明内容
本公开的目的在于提供一种显示基板、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：基底和设置于所述基底上的多个子像素；所述子像素包括：
复位信号线，所述复位信号线的至少部分沿第一方向延伸；
初始化信号线，所述初始化信号线的至少部分沿所述第一方向延伸；
第一晶体管，所述第一晶体管的栅极与所述复位信号线耦接，所述第一晶体管的第一极与所述初始化信号线耦接，所述第一晶体管的第一极的至少部分在所述基底上的正投影，位于所述复位信号线在所述基底上的正投影与所述初始化信号线在所述基底上的正投影之间。
可选的，所述子像素还包括导电连接部，所述导电连接部分别与所述第 一晶体管的第一极和所述初始化信号线耦接，所述导电连接部在所述基底上的正投影位于所述复位信号线在所述基底上的正投影与所述初始化信号线在所述基底上的正投影之间；沿所述第二方向，所述导电连接部的长度，小于所述复位信号线在所述基底上的正投影与所述初始化信号线在所述基底上的正投影之间的距离。
可选的，所述导电连接部在所述基底上的正投影与所述复位信号线在所述基底上的正投影不交叠。
可选的，所述第一晶体管的第一极在所述基底上的正投影，与所述初始化信号线在所述基底上的正投影部分交叠。
可选的，所述初始化信号线包括主体部和突出部，所述主体部沿所述第一方向延伸，所述突出部在所述基底上的正投影，与所述第一晶体管的第一极在所述基底上的正投影至少部分交叠。
可选的，所述子像素还包括栅线，所述栅线的至少部分沿所述第一方向延伸；
所述初始化信号线在所述基底上的正投影，位于所述复位信号线在所述基底上的正投影与所述栅线在所述基底上的正投影之间。
可选的，所述子像素还包括第二晶体管，所述第二晶体管的栅极与所述栅线耦接，所述第二晶体管的第一极与所述驱动晶体管的第二极耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接。
可选的，所述初始化信号线在所述基底上的正投影，与所述第二晶体管的栅极在所述基底上的正投影至少部分交叠。
可选的，所述第二晶体管包括第二有源图形，所述第二有源图形包括导体部分和两个半导体部分，所述导体部分分别与所述两个半导体部分耦接；
所述子像素还包括屏蔽图形，所述屏蔽图形与所述初始化信号线耦接，所述屏蔽图形在所述基底上的正投影，与所述导体部分在所述基底上的正投影至少部分交叠。
可选的，所述屏蔽图形与所述初始化信号线形成为一体结构。
可选的，所述屏蔽图形包括第一子图形和第二子图形，所述第一子图形沿第二方向延伸，所述第二方向与所述第一方向相交，所述第二子图形沿第 一方向延伸，所述第二子图形在所述基底上的正投影与所述导体部分在所述基底上的正投影至少部分交叠。
可选的，所述子像素还包括发光元件和第七晶体管，所述第七晶体管的栅极与沿第二方向相邻的下一个子像素中的复位信号线耦接，所述第七晶体管的第一极与沿第二方向相邻的下一个子像素中的初始化信号线耦接，所述第七晶体管的第二极与所述发光元件耦接，所述第二方向与所述第一方向相交；
所述第七晶体管的第一极在所述基底上的正投影，位于沿第二方向相邻的下一个子像素中的复位信号线在所述基底上的正投影，与沿第二方向相邻的下一个子像素中的初始化信号线在所述基底上的正投影之间。
可选的，所述第七晶体管的第一极与沿第二方向相邻的下一个子像素中的第一晶体管的第一极形成为一体结构。
可选的，所述子像素还包括：
发光控制信号线，所述发光控制信号线的至少部分沿第一方向延伸；
电源线，所述电源线的至少部分沿第二方向延伸；
数据线，所述数据线的至少部分沿所述第二方向延伸；
第四晶体管，所述第四晶体管的栅极与所述栅线耦接，所述第四晶体管的第一极与所述数据线耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
第五晶体管，所述第五晶体管的栅极与所述发光控制信号线耦接，所述第五晶体管的第一极与所述电源线耦接，所述第五晶体管的第二极与所述驱动晶体管的第一极耦接；
第六晶体管，所述第六晶体管的栅极与所述发光控制信号线耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述发光元件耦接；
存储电容，所述驱动晶体管的栅极复用为所述存储电容的第一极板，所述存储电容的第二极板与所述电源线耦接。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的子像素驱动电路的结构示意图；
图2为图1中子像素驱动电路的工作流程图；
图3为图1中子像素驱动电路的第一布局流程图；
图4为图1中子像素驱动电路的第二布局流程图；
图5为图1和图2中有源层和第一栅金属层的布局示意图；
图6为图2中有源层和第一源漏金属层的布局示意图；
图7为图2中第二栅金属层和第一源漏金属层的布局示意图；
图8为图2中有源层的布局示意图；
图9为图2中第一栅金属层的布局示意图；
图10为图2中第二栅金属层的布局示意图；
图11为图2中第一源漏金属层的布局示意图；
图12为阵列分布的四个子像素驱动电路的布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板、显示装置，下面结合说明书附图进行详细描述。
请参阅图1、图3和图5，本公开提供一种显示基板，所述显示基板包括基底和设置于所述基底上的多个子像素，每个子像素均包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和存储电容Cst。
每个子像素还包括初始化信号线VINT(N)、复位信号线RST(N)、栅线GA、发光控制信号线EM，电源线ELVDD、数据线DA、第一连接部、第二连接部和第三连接部。初始化信号线VINT(N)、复位信号线RST(N)、栅线 GA和发光控制信号线EM均有至少部分沿第一方向延伸。所述电源线ELVDD和所述数据线DA均有至少部分沿第二方向延伸，所述第二方向与所述第一方向相交。
在同一个子像素中，所述初始化信号线VINT(N)在所述基底上的正投影，所述复位信号线RST(N)在所述基底上的正投影，所述栅线GA在所述基底上的正投影，所述发光控制信号线EM在所述基底上的正投影沿所述第二方向依次排列。
所述第一晶体管T1的栅极与所述复位信号线RST(N)耦接，所述第一晶体管T1的第一极通过第三连接部403与所述初始化信号线VINT(N)耦接，所述第一晶体管T1的第二极与所述第三晶体管T3的栅极耦接。
所述第二晶体管T2的栅极与所述栅线GA耦接，所述第二晶体管T2的第一极与所述第三晶体管T3的第二极耦接，所述第二晶体管T2的第二极通过第一连接部401与所述第三晶体管T3的栅极耦接。
所述第四晶体管T4的栅极与所述栅线GA耦接，所述第四晶体管T4的第一极与数据线DA耦接，所述第四晶体管T4的第二极与所述第三晶体管T3的第一极耦接。
所述第五晶体管T5的栅极与所述发光控制信号线EM耦接，所述第五晶体管T5的第一极与电源线ELVDD耦接，所述第五晶体管T5的第二极与所述第三晶体管T3的第一极耦接。
所述第六晶体管T6的栅极与所述发光控制信号线EM耦接，所述第六晶体管T6的第一极与所述第三晶体管T3的第二极耦接，所述第六晶体管T6的第二极与子像素中的发光元件耦接。
所述第七晶体管T7的栅极与沿第二方向相邻的下一个子像素中的复位信号线RST(N+1)耦接，所述第七晶体管T7的第一极通过第二连接部402与沿第二方向相邻的下一个子像素中的初始化信号线VINT(N+1)耦接，所述第七晶体管T7的第二极与子像素中的发光元件耦接。
所述第三晶体管T3的栅极复用为所述存储电容的第一极板，所述存储电容的第二极板与所述电源线ELVDD耦接。
需要说明，所述第二连接部复用为沿第二方向相邻的下一个子像素中的 第三连接部。
上述显示基板中，由于所述第一晶体管T1的第一极与所述初始化信号线VINT(N)之间的距离较远，因此需要设置所述第三连接部403沿所述第二方向延伸的长度较长，导致所述第三连接部403的尺寸较大，这样不仅对显示基板的透过率造成一定的影响，不利于显示基板的工作稳定性，而且增加了显示基板的布局难度。
请参阅图4和图5，本公开实施例提供一种显示基板，包括：基底和设置于所述基底上的多个子像素；所述子像素包括：
复位信号线RST(N)，所述复位信号线RST(N)的至少部分沿第一方向延伸；
初始化信号线VINT(N)，所述初始化信号线VINT(N)的至少部分沿所述第一方向延伸；
第一晶体管T1，所述第一晶体管T1的栅极与所述复位信号线RST(N)耦接，所述第一晶体管T1的第一极与所述初始化信号线VINT(N)耦接，所述第一晶体管T1的第二极与驱动晶体管(即第三晶体管T3)的栅极耦接；所述第一晶体管T1的第一极的至少部分在所述基底上的正投影，位于所述复位信号线RST(N)在所述基底上的正投影与所述初始化信号线VINT(N)在所述基底上的正投影之间；
示例性的，所述第一方向包括水平反向，所述第二方向包括竖直方向。
示例性的，所述显示基板包括沿远离所述基底的方向依次层叠设置的有源层，第一栅绝缘层，第一栅金属层，第二栅绝缘层，第二栅金属层，层间绝缘层，第一源漏金属层和平坦层等。
示例性的，所述第一栅金属层包括所述复位信号线RST(N)和栅线GA，所述第二栅金属层包括所述初始化信号线VINT(N)。
示例性的，所述子像素包括像素驱动电路和发光元件，所述像素驱动电路与所述发光元件的阳极耦接，用于驱动发光元件发光。所述多个子像素中包括的多个像素驱动电路呈阵列分布在所述基底上。
示例性的，所述多个像素驱动电路能够划分为多行像素驱动电路和多列像素驱动电路。所述多行像素驱动电路沿所述第二方向排列，每行像素驱动 电路包括沿所述第一方向排列的多个像素驱动电路。所述多列像素驱动电路沿所述第一方向排列，每列像素驱动电路包括沿所述第二方向排列的多个像素驱动电路。
示例性的，所述像素驱动电路包括驱动晶体管、第一晶体管T1和第七晶体管T7，所述第一晶体管T1用于对所述驱动晶体管的栅极进行复位，所述第一晶体管T1的第一极与所述初始化信号线VINT(N)耦接，所述第七晶体管T7用于对发光元件的阳极进行复位，所述第七晶体管T7的第一极与沿第二方向相邻的下一个子像素中的初始化信号线VINT(N+1)耦接。
示例性的，同一行像素驱动电路中，各像素驱动电路对应耦接的复位信号线RST(N)依次耦接形成为一体结构，各像素驱动电路对应耦接的初始化信号线VINT(N)依次耦接形成为一体结构，各像素驱动电路对应耦接的栅线GA依次耦接形成为一体结构。
示例性的，当各子像素还包括发光控制信号线EM，电源线ELVDD和数据线DA时，同一行像素驱动电路中，各像素驱动电路对应耦接的发光控制信号线EM依次耦接形成为一体结构。同一列像素驱动电路中，各像素驱动电路对应耦接的电源线ELVDD依次耦接形成为一体结构。同一列像素驱动电路中，各像素驱动电路对应耦接的数据线DA依次耦接形成为一体结构。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，通过设置所述第一晶体管T1的第一极的至少部分在所述基底上的正投影，位于所述复位信号线RST(N)在所述基底上的正投影与所述初始化信号线VINT(N)在所述基底上的正投影之间，使得所述初始化信号线VINT(N)与其所属子像素中的第一晶体管T1的第一极，以及沿第二方向相邻的上一个子像素中的第七晶体管T7的第一极之间的距离均较近，这样在通过导电连接部404连接所述初始化信号线VINT(N)与其所属子像素中的第一晶体管T1的第一极，以及通过导电连接部404连接所述初始化信号线VINT(N)与沿第二方向相邻的上一个子像素中的第七晶体管T7的第一极时，能够有效缩小所述导电连接部404的尺寸。因此，本公开实施例提供的显示基板中，减少所述导电连接部404的遮挡面积，使显示基板具有良好的透过率，在将所述显示基板应用于对透过率有要求的屏下感测(sensor)产品中时，能够保证sensor 产品功能性良好。而且，本公开实施例提供的显示基板中，通过缩小所述导电连接部404的尺寸，更有利于避免所述导电连接部404与其周边的其他结构之间产生串扰，有效提升了显示基板工作的稳定性。此外，通过缩小所述导电连接部404的尺寸，降低了所述导电连接部404占用的布局空降，从而更好的降低了显示基板整体的布局难度。
如图4～图7所示，在一些实施例中，所述子像素还包括导电连接部404，所述导电连接部404分别与所述第一晶体管T1的第一极和所述初始化信号线VINT(N)耦接，所述导电连接部在所述基底上的正投影位于所述复位信号线在所述基底上的正投影与所述初始化信号线在所述基底上的正投影之间；沿所述第二方向，所述导电连接部404的长度，小于所述复位信号线RST(N)在所述基底上的正投影与所述初始化信号线VINT(N)在所述基底上的正投影之间的距离。
示例性的，所述导电连接部404与所述电源线ELVDD和所述数据线DA均同层同材料设置。
示例性的，所述导电连接部404沿所述第二方向延伸。
示例性的，所述导电连接部404在所述第二方向的长度小于或等于所述初始化信号线VINT(N)在所述第二方向的最大宽度。
如图4～图7所示，示例性的，所述导电连接部404的第一端在所述基底上的正投影与所述第一晶体管T1的第一极在所述基底上的正投影具有第一交叠区域，所述导电连接部404的第一端与所述第一晶体管T1的第一极通过第一过孔801耦接；所述导电连接部404的第二端在所述基底上的正投影分别与所述主体部61在所述基底上的正投影和所述突出部60在所述基底上的正投影具有第二交叠区域，所述导电连接部404的第二端与所述主体部61和所述突出部60通过第二过孔802耦接。
示例性的，所述第一过孔贯穿层间绝缘层、第二栅绝缘层和第一栅绝缘层；所述第二过孔贯穿层间绝缘层和第二栅绝缘层。
上述实施例提供的显示基板中，通过设置沿所述第二方向，所述导电连接部404的长度，小于所述复位信号线RST(N)在所述基底上的正投影与所述初始化信号线VINT(N)在所述基底上的正投影之间的距离，有效缩小所述导 电连接部404的尺寸。因此，上述实施例提供的显示基板中，减少所述导电连接部404的遮挡面积，使显示基板具有良好的透过率，在将所述显示基板应用于对透过率有要求的屏下感测(sensor)产品中时，能够保证sensor产品功能性良好。而且，本公开实施例提供的显示基板中，通过缩小所述导电连接部404的尺寸，更有利于避免所述导电连接部404与其周边的其他结构之间产生串扰，有效提升了显示基板工作的稳定性。此外，通过缩小所述导电连接部404的尺寸，降低了所述导电连接部404占用的布局空降，从而更好的降低了显示基板整体的布局难度。
如图4～图7所示，在一些实施例中，设置所述导电连接部404在所述基底上的正投影与所述复位信号线RST(N)在所述基底上的正投影不交叠。
上述设置方式避免了所述导电连接部404与所述复位信号线RST(N)之间产生交叠电容，有利于避免所述导电连接部404与所述复位信号线RST(N)之间产生串扰，有效提升了显示基板工作的稳定性。
如图4～图8、图11所示，在一些实施例中，所述子像素还包括：驱动晶体管、所述第一晶体管T1和第二晶体管T2；
所述第二晶体管T2的栅极与所述栅线GA耦接，所述第二晶体管T2的第一极与所述驱动晶体管的第二极耦接，所述第二晶体管T2的第二极与所述驱动晶体管的栅极耦接。
示例性的，所述复位信号线RST(N)复用为所述第一晶体管T1的栅极。
示例性的，所述第一晶体管T1为双栅结构，所述第一晶体管T1包括第一有源图形101，所述第一有源图形101的至少部分为类似n形结构，所述第一有源图形101在所述基底上的正投影与所述复位信号线RST(N)在所述基底上的正投影能够形成两个独立的交叠区域。
示例性的，所述第一有源图形101的第一端作为所述第一晶体管T1的第一极，所述第二有源图形102的第二端作为所述第一晶体管T1的第二极。
示例性的，所述第二晶体管T2为双栅结构，所述第二晶体管T2包括第二有源图形102，所述第二有源图形102为类似
Figure PCTCN2021125811-appb-000001
形结构。
示例性的，所述第二晶体管T2为补偿晶体管，用于对驱动晶体管的阈值电压进行补偿。
上述实施例提供的显示基板中，通过设置所述第一晶体管T1的第一极在所述基底上的正投影，位于所述复位信号线RST(N)在所述基底上的正投影与所述栅线GA在所述基底上的正投影之间，使得所述第一晶体管T1的第一极与所述初始化信号线VINT(N)之间的距离较近，这样在通过导电连接部404连接所述初始化信号线VINT(N)与其所属子像素中的第一晶体管T1的第一极时，能够有效缩小所述导电连接部404的尺寸，减少所述导电连接部404的遮挡面积。因此，上述实施例提供的显示基板具有良好的透过率，在将所述显示基板应用于对透过率有要求的屏下感测(sensor)产品中时，能够保证sensor产品功能性良好。
如图4和图5所示，在一些实施例中，设置所述第一晶体管T1的第一极在所述基底上的正投影，与所述初始化信号线VINT(N)在所述基底上的正投影部分交叠。
上述设置方式进一步减小了所述第一晶体管T1的第一极与所述初始化信号线VINT(N)之间的距离，在通过导电连接部404连接所述初始化信号线VINT(N)与其所属子像素中的第一晶体管T1的第一极时，能够进一步缩小所述导电连接部404的尺寸，减少所述导电连接部404的遮挡面积。
如图4、图5和图10所示，在一些实施例中，设置所述初始化信号线VINT(N)包括主体部61和突出部60，所述主体部61沿所述第一方向延伸，所述突出部60在所述基底上的正投影，与所述第一晶体管T1的第一极在所述基底上的正投影至少部分交叠。
示例性的，所述主体部61和所述突出部60形成为一体结构。
示例性的，所述突出部60在所述基底上的正投影，位于所述主体部61在所述基底上的正投影与所述复位信号线RST(N)在所述基底上的正投影之间。
示例性的，所述主体部61在所述基底上的正投影，与所述第一晶体管T1的第一极在所述基底上的正投影至少部分交叠。
上述实施例提供的显示基板中，通过设置所述突出部60在所述基底上的正投影，与所述第一晶体管T1的第一极在所述基底上的正投影至少部分交叠，减小了所述第一晶体管T1的第一极与所述初始化信号线VINT(N)之间的 距离，在通过导电连接部404连接所述初始化信号线VINT(N)与其所属子像素中的第一晶体管T1的第一极时，能够有效缩小所述导电连接部404的尺寸，减少所述导电连接部404的遮挡面积。
而且，上述设置方式还避免了所述第一晶体管T1的第一极与所述初始化信号线VINT(N)形成较大的交叠面积，避免了所述第一晶体管T1的第一极与所述初始化信号线VINT(N)产生较大的寄生电容，影响显示基板的工作稳定性。
如图4、图5和图9所示，在一些实施例中，所述子像素还包括：栅线GA，所述栅线GA的至少部分沿所述第一方向延伸；所述初始化信号线VINT(N)在所述基底上的正投影，位于所述复位信号线RST(N)在所述基底上的正投影与所述栅线GA在所述基底上的正投影之间。
上述实施例提供的显示基板中，通过设置所述第一晶体管T1的第一极在所述基底上的正投影，位于所述复位信号线RST(N)在所述基底上的正投影与所述栅线GA在所述基底上的正投影之间；以及所述初始化信号线VINT(N)在所述基底上的正投影，位于所述复位信号线RST(N)在所述基底上的正投影与所述栅线GA在所述基底上的正投影之间；使得所述第一晶体管T1的第一极与所述初始化信号线VINT(N)之间的距离较近，这样在通过导电连接部404连接所述初始化信号线VINT(N)与其所属子像素中的第一晶体管T1的第一极时，能够有效缩小所述导电连接部404的尺寸。
如图4、图5、图9和图10所示，在一些实施例中，所述初始化信号线VINT(N)在所述基底上的正投影，与所述第二晶体管T2的栅极202g在所述基底上的正投影至少部分交叠。
示例性的，设置所述主体部61在所述基底上的正投影，与所述第二晶体管T2的栅极202g在所述基底上的正投影至少部分交叠。
上述设置方式使得所述主体部61更靠近所述第二晶体管T2的第二极，有利于所述第二晶体管T2的第二极的稳定性，而所述第二晶体管T2的第二极与所述驱动晶体管的栅极耦接，从而使得所述驱动晶体管的栅极的电位也不容易受到外界串扰。
如图4、图5、图7、图8和图10所示，在一些实施例中，所述第二晶 体管T2包括第二有源图形102，所述第二有源图形102包括导体部分1021和两个半导体部分1022，所述导体部分1021分别与所述两个半导体部分1022耦接；
所述子像素还包括屏蔽图形62，所述屏蔽图形62与所述初始化信号线VINT(N)耦接，所述屏蔽图形62在所述基底上的正投影，与所述导体部分1021在所述基底上的正投影至少部分交叠。
示例性的，所述第二有源图形102包括导体部分1021和两个半导体部分1022，所述导体部分1021的导电性能优于所述两个半导体部分1022，所述两个半导体部分1022在所述基底上的正投影，位于所述第二晶体管T2的栅极在所述基底上的正投影的内部。
示例性的，所述初始化信号线VINT(N)上传输具有固定电位的初始化信号，将所述屏蔽图形62与所述初始化信号线VINT(N)耦接，使得所述屏蔽图形62具有固定电位。
上述实施例提供的显示基板中，通过设置所述屏蔽图形62在所述基底上的正投影，与所述导体部分1021在所述基底上的正投影至少部分交叠，使得所述屏蔽图形62对所述导体部分1021具有良好的屏蔽作用，避免了沿第一方向相邻子像素中的数据线DA上的数据信号跳变对所述导体部分1021产生影响，从而很好的保证了所述第二晶体管T2和其耦接的驱动晶体管工作的稳定性。
另外，通过设置所述屏蔽图形62与所述初始化信号线VINT(N)耦接，有效缩小了所述屏蔽图形62的尺寸，减少所述屏蔽图形62的遮挡面积，使显示基板具有良好的透过率，在将所述显示基板应用于对透过率有要求的屏下感测(sensor)产品中时，能够保证sensor产品功能性良好。而且，上述实施例提供的显示基板中，通过缩小所述屏蔽图形62的尺寸，更有利于避免所述屏蔽图形62与其周边的其他结构之间产生寄生电容，有效提升了显示基板工作的稳定性。此外，通过缩小所述屏蔽图形62的尺寸，降低了所述屏蔽图形62占用的布局空降，从而更好的降低了显示基板整体的布局难度。
在一些实施例中，设置所述屏蔽图形62与所述初始化信号线VINT(N)形成为一体结构。
上述设置方式使得所述屏蔽图形62能够与所述初始化信号线VINT(N)在同一次构图工艺中形成，从而很好的简化了所述显示基板的制作工艺流程，节约了显示基板的制作成本。
如图4、图5、图7、图8和图10所示，在一些实施例中，所述屏蔽图形62包括第一子图形620和第二子图形621，所述第一子图形620沿第二方向延伸，所述第二方向与所述第一方向相交，所述第二子图形621沿第一方向延伸，所述第二子图形621在所述基底上的正投影与所述导体部分1021在所述基底上的正投影至少部分交叠。
示例性的，所述第一子图形620和所述第二子图形621形成为一体结构。
示例性的，所述屏蔽图形62形成为L形结构。
示例性的，所述第一子图形620在垂直于其自身延伸方向上的宽度，小于所述第二子图形621在垂直于其自身延伸方向上的宽度。
上述实施例提供的显示基板中，通过设置所述屏蔽图形62包括所述第一子图形620和所述第二子图形621，使得所述屏蔽图形62在起到良好的屏蔽作用的同时，占用了较小的布局空间，有利于提升所述显示基板的分辨率。
如图5和图12所示，在一些实施例中，所述子像素还包括发光元件和第七晶体管T7，所述第七晶体管T7的栅极与沿第二方向相邻的下一个子像素中的复位信号线RST(N+1)耦接，所述第七晶体管T7的第一极与沿第二方向相邻的下一个子像素中的初始化信号线VINT(N+1)耦接，所述第七晶体管T7的第二极与所述发光元件耦接，所述第二方向与所述第一方向相交；
所述第七晶体管T7的第一极在所述基底上的正投影，位于沿第二方向相邻的下一个子像素中的复位信号线RST(N+1)在所述基底上的正投影，与沿第二方向相邻的下一个子像素中的初始化信号线VINT(N+1)在所述基底上的正投影之间。
示例性的，所述第七晶体管T7在沿第二方向相邻的下一个子像素中的复位信号线RST(N+1)的控制下导通，将所述发光元件的阳极与沿第二方向相邻的下一个子像素中的初始化信号线VINT(N+1)耦接在一起，实现对发光元件的阳极复位。
示例性的，在所述沿第二方向相邻的下一个子像素中，初始化信号线 VINT(N+1)在所述基底上的正投影，位于复位信号线RST(N+1)在所述基底上的正投影与栅线GA在所述基底上的正投影之间。
上述实施例提供的显示基板中，通过设置所述第七晶体管T7的第一极在所述基底上的正投影，位于沿第二方向相邻的下一个子像素中的复位信号线RST(N+1)在所述基底上的正投影，与沿第二方向相邻的下一个子像素中的初始化信号线VINT(N+1)在所述基底上的正投影之间，使得所述第七晶体管T7的第一极与沿第二方向相邻的下一个子像素中的初始化信号线VINT(N+1)之间的距离较近，这样在通过导电连接部404连接所述第七晶体管T7的第一极和沿第二方向相邻的下一个子像素中的初始化信号线VINT(N+1)时，能够有效缩小所述导电连接部404的尺寸，减少所述导电连接部404的遮挡面积。
如图5和图12所示，在一些实施例中，设置所述第七晶体管T7的第一极与沿第二方向相邻的下一个子像素中的第一晶体管T1的第一极形成为一体结构。
上述设置方式使得所述第七晶体管T7的第一极，以及沿第二方向相邻的下一个子像素中的第一晶体管T1的第一极，能够通过同一个导电连接部404连接至初始化信号线VINT(N)，从而进一步提升了所述阵列基板的透过率。
如图1、图4和图12所示，在一些实施例中，所述子像素还包括：
发光控制信号线EM，所述发光控制信号线EM的至少部分沿第一方向延伸；
电源线ELVDD，所述电源线ELVDD的至少部分沿第二方向延伸；
数据线DA，所述数据线DA的至少部分沿所述第二方向延伸；
第四晶体管T4，所述第四晶体管T4的栅极与所述栅线GA耦接，所述第四晶体管T4的第一极与所述数据线DA耦接，所述第四晶体管T4的第二极与所述驱动晶体管的第一极耦接；
第五晶体管T5，所述第五晶体管T5的栅极与所述发光控制信号线EM耦接，所述第五晶体管T5的第一极与所述电源线ELVDD耦接，所述第五晶体管T5的第二极与所述驱动晶体管的第一极耦接；
第六晶体管T6，所述第六晶体管T6的栅极与所述发光控制信号线EM耦接，所述第六晶体管T6的第一极与所述驱动晶体管的第二极耦接，所述第 六晶体管T6的第二极与所述发光元件耦接；
存储电容，所述驱动晶体管的栅极复用为所述存储电容的第一极板，所述存储电容的第二极板与所述电源线ELVDD耦接。
如图1、图4和图12所示，所述子像素包括阵列分布的子像素驱动电路，以一个子像素驱动电路为例，该子像素驱动电路包括7个薄膜晶体管和1个电容。该子像素驱动电路包括的各晶体管均采用P型晶体管，每个晶体管的第一极包括源极，每个晶体管的第二极包括漏极。
第一晶体管T1(即复位晶体管)为双栅结构，第一晶体管T1的栅极201g与所述复位信号线RST(N)耦接，第一晶体管T1的源极S1通过第一过孔801、导电连接部404和第二过孔802与所述初始化信号线VINT(N)耦接，第一晶体管T1的漏极D1与第二晶体管T2的漏极D2耦接。所述第一过孔801贯穿第一栅极绝缘层、第二栅极绝缘层和层间绝缘层；所述第二过孔802贯穿层间绝缘层。
第二晶体管T2为双栅结构，第二晶体管T2(即补偿晶体管)的栅极202g与栅线GA耦接，第二晶体管T2的源极S2与第三晶体管T3(即驱动晶体管)的漏极D3耦接，第二晶体管T2的漏极D2通过第三过孔803、第一连接部401和第四过孔804与第三晶体管T3的栅极203g耦接。所述第三过孔803贯穿第一栅极绝缘层、第二栅极绝缘层和层间绝缘层；所述第四过孔804贯穿第二栅极绝缘层和层间绝缘层。
第四晶体管T4(即数据写入晶体管)的栅极204g与所述栅线GA耦接，第四晶体管T4的源极S4通过第五过孔805与数据线DA耦接，第四晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。所述第五过孔805贯穿第一栅极绝缘层、第二栅极绝缘层和层间绝缘层。
第五晶体管T5的栅极205g与发光控制信号线EM耦接，第五晶体管T5的源极S5通过第六过孔806与电源线ELVDD耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。所述第六过孔806贯穿第一栅极绝缘层、第二栅极绝缘层和层间绝缘层。
第六晶体管T6的栅极206g与发光控制信号线EM耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6通过 第七过孔807、第四连接部405、贯穿平坦层的过孔与发光元件EL的阳极耦接。所述第七过孔807贯穿第一栅极绝缘层、第二栅极绝缘层和层间绝缘层。
第七晶体管T7的栅极207g与沿所述第二方向相邻的下一个子像素中的复位信号线RST(N+1)耦接，第七晶体管T7的漏极D7与第六晶体管T6的漏极D6耦接，第七晶体管T7的源极S7通过第八过孔808与沿所述第二方向相邻的下一个子像素中的所述初始化信号线VINT(N+1)耦接。
存储电容Cst的第一极板Cst1复用为第三晶体管T3的栅极203g，存储电容Cst的第二极板Cst2通过至少一个第九过孔809与电源线ELVDD耦接。所述第九过孔809贯穿层间绝缘层。
如图2所示，上述结构的子像素驱动电路在工作时，每个工作周期均包括第一复位时段P1、写入补偿时段P2、第二复位时段P3和发光时段P4。
在所述第一复位时段P1，复位信号线RST(N)输入的复位信号处于有效电平，第一晶体管T1导通，由初始化信号线VINT(N)传输的初始化信号输入至第三晶体管T3的栅极203g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位。
在写入补偿时段P2，所述复位信号处于非有效电平，第一晶体管T1截止，栅线GA输入的栅极扫描信号处于有效电平，控制第二晶体管T2和第四晶体管T4导通，数据线DA写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的源极S3，同时，第二晶体管T2和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第二晶体管T2、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在第二复位时段P3，所述栅极扫描信号处于非有效电平，第二晶体管T2和第四晶体管T4均截止，复位信号线RST(N+1)输入的复位信号处于有效电平，控制第七晶体管T7导通，由初始化信号线图形VINT(N+1)传输的初始化信号输入至发光元件EL的阳极，控制发光元件EL不发光。
在发光时段P4，发光控制信号线图形EM写入的发光控制信号处于有效 电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源线传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极，驱动对应的发光元件EL发光。
在制作上述子像素时，子像素对应的各膜层的布局如下：
包括沿远离所述基底的方向依次层叠设置的有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层，第一源漏金属层，第一平坦层，第二源漏金属层，第二平坦层，阳极层，有机发光功能层和阴极层。所述阴极接入负电源信号ELVSS。
如图1、图4和图5所示，本公开提供的显示基板中，在第二方向上，第四晶体管T4的栅极204g、第一晶体管T1的栅极201g和第二晶体管T2的栅极202g均位于驱动晶体管的栅极(即第三晶体管T3的栅极203g)的第一侧，第七晶体管T7的栅极、第六晶体管T6的栅极206g、第五晶体管T5的栅极均位于驱动晶体管的栅极的第二侧。示例性的，所述驱动晶体管的栅极的第一侧和第二侧为沿第二方向相对的两侧，进一步地，驱动晶体管的栅极的第一侧可以为驱动晶体管的栅极的上侧，驱动晶体管的栅极的第二侧可以为驱动晶体管的栅极的下侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管的栅极的下侧，为驱动晶体管的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管的栅极的更远离IC的一侧。
在第一方向上，第四晶体管T4的栅极204g和第五晶体管T5的栅极205g均位于驱动晶体管的栅极的第三侧，第二晶体管T2的栅极202g和第六晶体管T6的栅极206g均位于驱动晶体管的栅极的第四侧。示例性的，驱动晶体管的栅极的第三侧和第四侧为沿第一方向相对的两侧；进一步地，驱动晶体管的栅极的第三侧可以为驱动晶体管的栅极的左侧，驱动晶体管的栅极的第四侧可以为驱动晶体管的栅极的右侧。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
上述实施例提供的显示基板中，通过设置所述初始化信号线在所述基底上的正投影，位于所述复位信号线在所述基底上的正投影与所述栅线在所述基底上的正投影之间，使得所述初始化信号线与其所属子像素中的第一晶体管的第一极，以及沿第二方向相邻的上一个子像素中的第七晶体管的第一极之间的距离均较近，这样在通过导电连接部404连接所述初始化信号线与其所属子像素中的第一晶体管的第一极，以及通过导电连接部404连接所述初始化信号线与沿第二方向相邻的上一个子像素中的第七晶体管的第一极时，能够有效缩小所述导电连接部404的尺寸，减少所述导电连接部404的遮挡面积。因此，上述实施例提供的显示基板具有良好的透过率，在将所述显示基板应用于对透过率有要求的屏下感测(sensor)产品中时，能够保证sensor产品功能性良好。
本公开实施例提供的显示装置在包括上述显示基板时同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，所述制作方法包括：在基底上制作多个子像素，制作每个子像素的步骤具体包括：
制作复位信号线，所述复位信号线的至少部分沿第一方向延伸；
制作初始化信号线，所述初始化信号线的至少部分沿所述第一方向延伸；
制作第一晶体管，所述第一晶体管的栅极与所述复位信号线耦接，所述第一晶体管的第一极与所述初始化信号线耦接，所述第一晶体管的第一极的至少部分在所述基底上的正投影，位于所述复位信号线在所述基底上的正投影与所述初始化信号线在所述基底上的正投影之间。
采用本公开实施例提供的制作方法制作的显示基板中，通过设置所述第一晶体管T1的第一极的至少部分在所述基底上的正投影，位于所述复位信号线RST(N)在所述基底上的正投影与所述初始化信号线VINT(N)在所述基底上的正投影之间，使得所述初始化信号线VINT(N)与其所属子像素中的第一晶体管T1的第一极，以及沿第二方向相邻的上一个子像素中的第七晶体管T7的第一极之间的距离均较近，这样在通过导电连接部404连接所述初始化 信号线VINT(N)与其所属子像素中的第一晶体管T1的第一极，以及通过导电连接部404连接所述初始化信号线VINT(N)与沿第二方向相邻的上一个子像素中的第七晶体管T7的第一极时，能够有效缩小所述导电连接部404的尺寸。因此，采用本公开实施例提供的制作方法制作的显示基板中，减少所述导电连接部404的遮挡面积，使显示基板具有良好的透过率，在将所述显示基板应用于对透过率有要求的屏下感测(sensor)产品中时，能够保证sensor产品功能性良好。而且，采用本公开实施例提供的制作方法制作的显示基板中，通过缩小所述导电连接部404的尺寸，更有利于避免所述导电连接部404与其周边的其他结构之间产生串扰，有效提升了显示基板工作的稳定性。此外，通过缩小所述导电连接部404的尺寸，降低了所述导电连接部404占用的布局空降，从而更好的降低了显示基板整体的布局难度。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种显示基板，包括：基底和设置于所述基底上的多个子像素；所述子像素包括：
    复位信号线，所述复位信号线的至少部分沿第一方向延伸；
    初始化信号线，所述初始化信号线的至少部分沿所述第一方向延伸；
    第一晶体管，所述第一晶体管的栅极与所述复位信号线耦接，所述第一晶体管的第一极与所述初始化信号线耦接，所述第一晶体管的第一极的至少部分在所述基底上的正投影，位于所述复位信号线在所述基底上的正投影与所述初始化信号线在所述基底上的正投影之间。
  2. 根据权利要求1所述的显示基板，其中，所述子像素还包括导电连接部，所述导电连接部分别与所述第一晶体管的第一极和所述初始化信号线耦接，所述导电连接部在所述基底上的正投影位于所述复位信号线在所述基底上的正投影与所述初始化信号线在所述基底上的正投影之间；沿所述第二方向，所述导电连接部的长度，小于所述复位信号线在所述基底上的正投影与所述初始化信号线在所述基底上的正投影之间的距离。
  3. 根据权利要求2所述的显示基板，其中，所述导电连接部在所述基底上的正投影与所述复位信号线在所述基底上的正投影不交叠。
  4. 根据权利要求2所述的显示基板，其中，所述第一晶体管的第一极在所述基底上的正投影，与所述初始化信号线在所述基底上的正投影部分交叠。
  5. 根据权利要求4所述的显示基板，其中，所述初始化信号线包括主体部和突出部，所述主体部沿所述第一方向延伸，所述突出部在所述基底上的正投影，与所述第一晶体管的第一极在所述基底上的正投影至少部分交叠。
  6. 根据权利要求1所述的显示基板，其中，所述子像素还包括栅线，所述栅线的至少部分沿所述第一方向延伸；
    所述初始化信号线在所述基底上的正投影，位于所述复位信号线在所述基底上的正投影与所述栅线在所述基底上的正投影之间。
  7. 根据权利要求6所述的显示基板，其中，
    所述子像素还包括第二晶体管，所述第二晶体管的栅极与所述栅线耦接， 所述第二晶体管的第一极与所述驱动晶体管的第二极耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接。
  8. 根据权利要求6所述的显示基板，其中，所述初始化信号线在所述基底上的正投影，与所述第二晶体管的栅极在所述基底上的正投影至少部分交叠。
  9. 根据权利要求7所述的显示基板，其中，所述第二晶体管包括第二有源图形，所述第二有源图形包括导体部分和两个半导体部分，所述导体部分分别与所述两个半导体部分耦接；
    所述子像素还包括屏蔽图形，所述屏蔽图形与所述初始化信号线耦接，所述屏蔽图形在所述基底上的正投影，与所述导体部分在所述基底上的正投影至少部分交叠。
  10. 根据权利要求9所述的显示基板，其中，所述屏蔽图形与所述初始化信号线形成为一体结构。
  11. 根据权利要求9所述的显示基板，其中，所述屏蔽图形包括第一子图形和第二子图形，所述第一子图形沿第二方向延伸，所述第二方向与所述第一方向相交，所述第二子图形沿第一方向延伸，所述第二子图形在所述基底上的正投影与所述导体部分在所述基底上的正投影至少部分交叠。
  12. 根据权利要求7所述的显示基板，其中，所述子像素还包括发光元件和第七晶体管，所述第七晶体管的栅极与沿第二方向相邻的下一个子像素中的复位信号线耦接，所述第七晶体管的第一极与沿第二方向相邻的下一个子像素中的初始化信号线耦接，所述第七晶体管的第二极与所述发光元件耦接，所述第二方向与所述第一方向相交；
    所述第七晶体管的第一极在所述基底上的正投影，位于沿第二方向相邻的下一个子像素中的复位信号线在所述基底上的正投影，与沿第二方向相邻的下一个子像素中的初始化信号线在所述基底上的正投影之间。
  13. 根据权利要求12所述的显示基板，其中，所述第七晶体管的第一极与沿第二方向相邻的下一个子像素中的第一晶体管的第一极形成为一体结构。
  14. 根据权利要求12所述的显示基板，其中，所述子像素还包括：
    发光控制信号线，所述发光控制信号线的至少部分沿第一方向延伸；
    电源线，所述电源线的至少部分沿第二方向延伸；
    数据线，所述数据线的至少部分沿所述第二方向延伸；
    第四晶体管，所述第四晶体管的栅极与所述栅线耦接，所述第四晶体管的第一极与所述数据线耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
    第五晶体管，所述第五晶体管的栅极与所述发光控制信号线耦接，所述第五晶体管的第一极与所述电源线耦接，所述第五晶体管的第二极与所述驱动晶体管的第一极耦接；
    第六晶体管，所述第六晶体管的栅极与所述发光控制信号线耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述发光元件耦接；
    存储电容，所述驱动晶体管的栅极复用为所述存储电容的第一极板，所述存储电容的第二极板与所述电源线耦接。
  15. 一种显示装置，包括如权利要求1～14中任一项所述的显示基板。
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