WO2021227759A1 - 一种显示面板及其制作方法、显示装置 - Google Patents

一种显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2021227759A1
WO2021227759A1 PCT/CN2021/087367 CN2021087367W WO2021227759A1 WO 2021227759 A1 WO2021227759 A1 WO 2021227759A1 CN 2021087367 W CN2021087367 W CN 2021087367W WO 2021227759 A1 WO2021227759 A1 WO 2021227759A1
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Prior art keywords
signal line
sub
transistor
coupled
line pattern
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PCT/CN2021/087367
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English (en)
French (fr)
Inventor
陈义鹏
皇甫鲁江
刘利宾
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京东方科技集团股份有限公司
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Priority to US17/762,962 priority Critical patent/US11751460B2/en
Publication of WO2021227759A1 publication Critical patent/WO2021227759A1/zh
Priority to US17/948,576 priority patent/US11903289B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • AMOLED Active matrix organic light-emitting diode
  • the AMOLED display panel includes a sub-pixel drive circuit and a light-emitting unit, and the corresponding light-emitting unit is driven to emit light through the sub-pixel drive circuit to realize the display function of the display panel.
  • the layout space in the display panel becomes smaller and smaller.
  • the initialization signal line pattern used to provide the initialization signal for the sub-pixel drive circuit the initialization signal line located in the same row The graphics are not easily connected together, which leads to an increase in the production cost of the display panel.
  • the purpose of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display panel, including: a substrate, and an initialization signal line layer, a transfer layer, and an anode layer that are sequentially stacked on the substrate in a direction away from the substrate;
  • the sub-pixel areas in the same row along the first direction are divided into a plurality of independent sub-pixel area groups, and each sub-pixel area group includes at least two adjacent sub-pixel areas;
  • the initialization signal line layer includes initialization signal line patterns arranged in each of the sub-pixel regions;
  • the transfer layer includes a transfer pattern disposed in each of the sub-pixel regions, at least a part of the transfer pattern extends along the first direction, and the transfer pattern and the initialization signal in the sub-pixel region where it is located Line pattern coupling; each of the transfer patterns located in the same sub-pixel area group is sequentially coupled along the first direction to form a transfer portion;
  • the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel regions one-to-one, the plurality of anode patterns are arranged at intervals, and an anode spacer region is formed between the adjacent anode patterns;
  • the display panel further includes: a first auxiliary signal line layer, the first auxiliary signal line layer has a grid-like structure, and at least a part of the first auxiliary signal line layer is located in the anode spacer region and is in contact with the The anode pattern is insulated, and the connecting portion in each sub-pixel area group is respectively coupled with the first auxiliary signal line layer.
  • the display panel further includes:
  • a conductive connection portion layer includes a first conductive connection portion located in each of the sub-pixel areas, in the same sub-pixel area, the orthographic projection of the first conductive connection portion on the substrate, and
  • the orthographic projection of the initialization signal line pattern on the substrate has a first overlap area, and the first conductive connection portion is connected to the initialization signal line pattern through a first via provided in the first overlap area. Coupling, the orthographic projection of the first conductive connection portion on the substrate has a third overlap area with the orthographic projection of the transfer pattern on the substrate, and the first conductive connection portion is disposed on the The third via hole in the third overlapping area is coupled to the transfer pattern;
  • each of the first conductive connection portions to which each of the adapter portions are correspondingly coupled there is a target conductive connection portion, and the orthographic projection of the target conductive connection portion on the substrate and the first auxiliary signal line
  • the orthographic projection of the layer on the substrate forms a second overlapping area, and the target conductive connection portion is coupled to the first auxiliary signal line layer through a second via provided in the second overlapping area.
  • each of the initialization signal line patterns includes a first sub-pattern and a second sub-pattern, which are located in adjacent sub-pixel regions in the same row along the first direction, and the second sub-pattern in the previous sub-pixel region Forming an integral structure with the first sub-pattern in the latter sub-pixel area;
  • the orthographic projection of the second sub-pattern on the substrate and the orthographic projection of the first conductive connection portion on the substrate have the first overlap area, and A conductive connection portion is coupled to the second sub-pattern through a first via hole provided in the first overlap area.
  • the display panel further includes:
  • a power signal line layer includes a power signal line pattern disposed in each of the sub-pixel regions, at least a part of the power signal line pattern extends along a second direction, and the second direction is connected to the Intersect in the first direction;
  • the display panel further includes:
  • a light-emitting control signal line layer includes a light-emission control signal line pattern located in each of the sub-pixel regions, and at least a part of the light-emission control signal line pattern extends along the first direction;
  • a reset signal line layer including a reset signal line pattern located in each of the sub-pixel regions, the reset signal line pattern extending along the first direction;
  • the orthographic projection of the third auxiliary signal line pattern on the substrate is formed into a wave-shaped structure.
  • the display panel further includes:
  • a gate line layer includes a gate line pattern located in each of the sub-pixel regions, and at least a part of the gate line pattern extends along a first direction;
  • a data line layer includes a data line pattern located in each of the sub-pixel regions, at least part of the data line pattern extends along a second direction, and the first direction intersects the second direction,
  • the orthographic projection of the data line pattern on the substrate overlaps the orthographic projection of the grid line pattern on the substrate;
  • a conductive connection portion layer including a third conductive connection portion and a fourth conductive connection portion located in each of the sub-pixel regions;
  • each of the sub-pixel drive circuits includes a drive transistor, a storage capacitor, a first transistor, and a second transistor; the gate of the drive transistor is multiplexed The first plate of the storage capacitor, the gate of the drive transistor is coupled to the second electrode of the second transistor through the fourth conductive connection portion in the corresponding sub-pixel area, and the second electrode of the storage capacitor The plate is coupled to the second electrode of the first transistor through the third conductive connection portion in the corresponding sub-pixel area; the gate of the first transistor and the gate of the second transistor are respectively connected to the corresponding sub-pixel
  • the grid pattern in the region is coupled; the orthographic projection of the grid pattern on the substrate and the orthographic projection of the third conductive connection portion on the substrate do not overlap, and/or the grid pattern The orthographic projection on the substrate and the orthographic projection of the fourth conductive connecting portion on the substrate do not overlap.
  • the conductive connection portion layer further includes a second conductive connection portion located in each of the sub-pixel regions, and the anode pattern corresponding to the second conductive connection portion and the sub-pixel region in which it is located is positive on the substrate.
  • the projection overlaps, and the second conductive connection portion is coupled to the anode pattern at the overlap;
  • Each of the sub-pixel driving circuits further includes a fifth transistor, an eighth transistor, and a ninth transistor;
  • the gate of the fifth transistor is coupled to the corresponding reset signal line pattern, the first electrode of the fifth transistor is coupled to the corresponding initialization signal line pattern, and the second electrode of the fifth transistor is coupled to the corresponding reset signal line pattern.
  • the third conductive connection portion is coupled through a fourth via;
  • the gate of the eighth transistor is coupled to the corresponding reset signal line pattern, the first pole of the eighth transistor is coupled to the corresponding initialization signal line pattern, and the second pole of the eighth transistor is coupled to the reset signal line pattern.
  • the second conductive connection portion is coupled through a fifth via;
  • the gate of the ninth transistor is coupled to the corresponding light-emitting control signal line pattern, the first electrode of the ninth transistor and the fourth conductive connection portion are coupled through a sixth via, and the The second pole is floating;
  • the third auxiliary signal line pattern includes a first auxiliary part, a second auxiliary part, and a third auxiliary part that are sequentially coupled; in one sub-pixel area, the orthographic projection of the first auxiliary part on the substrate, Located between the orthographic projection of the fifth via on the substrate and the orthographic projection of the sixth via on the substrate, the orthographic projection of the second auxiliary part on the substrate is located at the Between the orthographic projection of the fifth via on the substrate and the orthographic projection of the fourth via on the substrate; the orthographic projection of the third auxiliary part on the substrate is located on the first Between the orthographic projection of the six vias on the substrate and the orthographic projection of the fourth via on the substrate.
  • the display panel further includes:
  • a data line layer includes a data line pattern located in each of the sub-pixel regions, at least a part of the data line pattern extends along a second direction;
  • the third auxiliary signal line patterns adjacent to each other in the same row of sub-pixel regions along the first direction form a shielding portion at the coupling position, the shielding portion extends in the second direction, and the shielding portion is located on the substrate
  • the orthographic projection on the upper and the orthographic projection of the data line pattern on the substrate overlap, and in a direction perpendicular to the second direction, the width of the shielding portion is greater than the width of the data line pattern.
  • the display panel further includes:
  • a data line layer includes a data line pattern located in each of the sub-pixel regions, at least part of the data line pattern extends along a second direction, the first direction intersects the second direction;
  • a power signal line layer includes a power signal line pattern located in each of the sub-pixel regions, at least a part of the power signal line pattern extends along the second direction;
  • the orthographic projection of the power signal line pattern on the substrate In the same sub-pixel area, the orthographic projection of the gate of the driving transistor on the substrate and the data line pattern on the substrate Between the orthographic projections.
  • the power signal line pattern includes a first power supply portion and a second power supply portion that are coupled to each other, the first power supply portion extends along the second direction, and the second power supply portion extends away from where it is located.
  • the direction of the data line pattern in the pixel area protrudes from the first power supply part; in the direction perpendicular to the second direction and parallel to the substrate, the width of the first power supply part is greater than that of the second power supply part.
  • the width of the power supply is
  • the orthographic projection of the first electrode of the driving transistor on the substrate overlaps the orthographic projection of the first power supply part in the corresponding sub-pixel area on the substrate, and the first electrode of the driving transistor It is coupled with the first power supply part at the overlap.
  • the display panel further includes:
  • a first shielding layer includes a first shielding pattern located in each of the sub-pixel regions, the orthographic projection of the first shielding pattern on the substrate and the first power supply part are in the The orthographic projections on the substrate overlap, where the first shielding pattern is coupled to the first power supply part; at least part of the first shielding pattern extends along the second direction, and the first The orthographic projection of the shielding pattern on the substrate overlaps the orthographic projection of the data line pattern on the substrate.
  • the display panel further includes:
  • a gate line layer includes a gate line pattern located in each of the sub-pixel regions, and at least a part of the gate line pattern extends along a first direction;
  • a reset signal line layer includes a reset signal line pattern located in each of the sub-pixel areas, and the gate line pattern in the current sub-pixel area is similar to the one in the next sub-pixel area adjacent in the second direction.
  • the reset signal line pattern is formed as an integral structure.
  • the display panel further includes: a power signal line pattern, a data line pattern, a reset signal line pattern, a light-emission control signal line pattern, and a gate line pattern located in each of the sub-pixel regions;
  • One-to-one corresponding sub-pixel drive circuits in the pixel area, each of the sub-pixel drive circuits includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, The eighth transistor, the ninth transistor and the storage capacitor;
  • the gate of the first transistor is coupled to the gate line pattern, the first electrode of the first transistor is coupled to the data line pattern, and the second electrode of the first transistor is connected to the storage capacitor
  • the second plate is coupled, and the first plate of the storage capacitor is coupled to the gate of the third transistor
  • the gate of the second transistor is coupled to the gate line pattern, the first electrode of the second transistor is coupled to the second electrode of the third transistor, and the second electrode of the second transistor is coupled to the second electrode of the third transistor.
  • the gate of the third transistor is coupled;
  • the first electrode of the third transistor is coupled to the power signal line pattern
  • the gate of the fourth transistor is coupled to the reset signal line pattern, the first electrode of the fourth transistor is coupled to the initialization signal line pattern, and the second electrode of the fourth transistor is coupled to the first The gates of the three transistors are coupled;
  • the gate of the fifth transistor is coupled to the reset signal line pattern, the first electrode of the fifth transistor is coupled to the initialization signal line pattern, and the second electrode of the fifth transistor is coupled to the memory
  • the second plate of the capacitor is coupled;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the initialization signal line pattern, and the second electrode of the sixth transistor is coupled to the storage capacitor ⁇ second plate coupling;
  • the gate of the seventh transistor is coupled to the light emission control signal line pattern, the first electrode of the seventh transistor is coupled to the second electrode of the third transistor, and the second electrode of the seventh transistor corresponds to ⁇ anodic pattern coupling;
  • the gate of the eighth transistor is coupled to the reset signal line pattern, the first electrode of the eighth transistor is coupled to the initialization signal line pattern, and the second electrode of the eighth transistor is coupled to the corresponding anode Graphics coupling
  • the gate of the ninth transistor is coupled to the corresponding light emission control signal line pattern, the first electrode of the ninth transistor is coupled to the gate of the third transistor, and the second electrode of the ninth transistor is Extremely floating.
  • a second aspect of the present disclosure provides a display device, which includes the above-mentioned display panel.
  • a third aspect of the present disclosure provides a method for manufacturing a display panel.
  • the display panel includes a plurality of sub-pixel regions distributed in an array, and the sub-pixel regions located in the same row along the first direction are divided into A plurality of mutually independent sub-pixel area groups, each sub-pixel area group includes at least two adjacent sub-pixel areas; the manufacturing method includes:
  • the initialization signal line layer includes initialization signal line patterns arranged in each of the sub-pixel regions;
  • the transfer layer includes a transfer pattern disposed in each of the sub-pixel regions, at least a part of the transfer pattern extends along the first direction, and the transfer pattern and the initialization signal in the sub-pixel region where it is located Line pattern coupling; each of the transfer patterns located in the same sub-pixel area group is sequentially coupled along the first direction to form a transfer portion;
  • the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel regions one-to-one, the plurality of anode patterns are arranged at intervals, and an anode spacer region is formed between the adjacent anode patterns;
  • the first auxiliary signal line layer has a grid-like structure, and at least a part of the first auxiliary signal line layer is located in the anode spacer area and insulated from the anode pattern.
  • the transition in each sub-pixel area group The connection parts are respectively coupled with the first auxiliary signal line layer.
  • FIG. 1 is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 2 is a working timing diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 3 is a schematic layout diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic cross-sectional view along the direction B1B2 in FIG. 3;
  • FIG. 5 is a schematic diagram of a first layout of a first auxiliary signal line layer provided by an embodiment of the disclosure
  • FIG. 6 is a schematic diagram of a second layout of a first auxiliary signal line layer provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of the active film layer layout in FIG. 3;
  • FIG. 8 is a schematic diagram of the layout of the first gate metal layer in FIG. 3;
  • FIG. 9 is a schematic diagram of the layout of the second gate metal layer in FIG. 3;
  • FIG. 10 is a schematic diagram of the layout of the first source and drain metal layer in FIG. 3.
  • an embodiment of the present disclosure provides a display panel, including: a substrate, and an initialization signal line layer and a transfer layer sequentially stacked on the substrate in a direction away from the substrate And the anode layer; further comprising a plurality of sub-pixel areas distributed in an array, the sub-pixel areas in the same row along the first direction are divided into a plurality of independent sub-pixel area groups, each sub-pixel area group includes at least two adjacent sub-pixel areas Pixel area
  • the initialization signal line layer includes initialization signal line patterns 904 arranged in each of the sub-pixel regions;
  • the transfer layer includes a transfer pattern 8061 disposed in each of the sub-pixel regions, at least a part of the transfer pattern 8061 extends along the first direction, and the transfer pattern 8061 extends along the first direction.
  • the connecting pattern 8061 is coupled to the initialization signal line pattern 904 in the sub-pixel area where it is located; the connecting patterns 8061 in the same sub-pixel area group are sequentially coupled along the first direction to form a connecting portion 806;
  • the anode layer includes a plurality of anode patterns 906 corresponding to the plurality of sub-pixel regions one to one.
  • the plurality of anode patterns 906 are arranged at intervals and are formed between adjacent anode patterns 906.
  • the display panel further includes: a first auxiliary signal line layer 801, the first auxiliary signal line layer 801 has a grid structure, and at least part of the first auxiliary signal line layer 801 is located in the anode spacer region 9061, It is insulated from the anode pattern 906, and the transfer portion 806 in each sub-pixel area group is respectively coupled to the first auxiliary signal line layer 801.
  • the plurality of sub-pixel regions arranged in an array can be divided into multiple rows of sub-pixel regions sequentially arranged along the second direction, and multiple columns of sub-pixel regions sequentially arranged along the first direction.
  • Each row of sub-pixel regions includes a plurality of sub-pixel regions spaced along the first direction
  • each column of sub-pixel regions includes a plurality of sub-pixel regions spaced along the second direction.
  • the first direction intersects the second direction.
  • the first direction includes the X direction
  • the second direction includes the Y direction.
  • the sub-pixel areas located in the same row along the first direction can be divided into a plurality of independent sub-pixel area groups, and each sub-pixel area group includes at least two adjacent sub-pixel areas; it is worth noting that, Each sub-pixel area may belong to only one sub-pixel area group.
  • the initialization signal line layer includes a plurality of initialization signal line patterns 904, the plurality of initialization signal line patterns 904 correspond to the plurality of sub-pixel areas one-to-one, and the initialization signal line patterns 904 are located in corresponding sub-pixel areas, It is used to provide an initialization signal for the sub-pixel driving circuit corresponding to the sub-pixel area.
  • the transfer layer includes a plurality of transfer patterns 8061 one-to-one corresponding to the plurality of sub-pixel regions, and the transfer patterns 8061 are located in the corresponding sub-pixel regions.
  • the transfer patterns 8061 can be coupled to the initialization signal line pattern 904 in a variety of ways; for example, the transfer pattern 8061 is located on the side of the initialization signal line pattern 904 facing away from the substrate, and can be connected to the A via hole is formed between the connection pattern 8061 and the initialization signal line pattern 904, so that the transfer pattern 8061 and the initialization signal line pattern 904 are directly coupled through the via hole.
  • the transfer pattern 8061 there are various specific structures of the transfer pattern 8061.
  • at least a part of the transfer pattern 8061 extends along the first direction, and each of the transfer patterns 8061 in the same sub-pixel area group can They are sequentially coupled along the first direction to form a transfer portion 806; for example, each of the transfer patterns 8061 included in the transfer portion 806 is formed as an integral structure.
  • the transfer pattern 8061 can be made by using the second gate metal layer in the display panel, but it is not limited to this.
  • the anode layer is located on the side of the adapter portion 806 facing away from the substrate.
  • the anode layer includes a plurality of anode patterns 906, and the plurality of anode patterns 906 are spaced apart from each other.
  • An anode spacer 9061 is formed therebetween.
  • the anode pattern 906 has a one-to-one correspondence with the sub-pixel driving circuit in the display panel, and the anode pattern 906 is coupled to the corresponding sub-pixel driving circuit and can receive driving signals provided by the corresponding sub-pixel driving circuit.
  • the side of the anode layer facing away from the substrate is further provided with a light-emitting functional layer and a cathode layer.
  • the light-emitting functional layer is located between the anode layer and the cathode layer and can be located between the anode layer and the cathode Under the action of the electric field formed between the layers, light of the corresponding color is emitted.
  • the light-emitting functional layer may specifically include a layered hole injection layer, a hole transport layer, an organic light emitting material layer, an electron transport layer, and an electron injection layer, but it is not limited thereto.
  • FIG. 6 the figure shows a red light-emitting element R, a green light-emitting element G, and a blue light-emitting element B.
  • the light-emitting elements of different colors correspond to the organic light-emitting material layers of different colors.
  • the display panel further includes a first auxiliary signal line layer 801, at least part of the first auxiliary signal line layer 801 is arranged in the anode spacer region 9061 and insulated from the anode pattern 906.
  • the anode spacer region 9061 is formed as a grid-like area, so that the first auxiliary signal line layer 801 arranged on the anode spacer region 9061 is formed as a grid-like structure.
  • the first auxiliary signal line layer 801 may be laid out in all the anode spacer regions 9061 in the display panel.
  • the display panel further includes a flat layer PLN.
  • the anode layer (including the anode pattern 906) is generally formed on the surface of the flat layer PLN facing away from the substrate 50, and the The first auxiliary signal line layer 801 is laid out in the anode spacer 9061, so that the first auxiliary signal line layer 801 is also laid out on the surface of the flat layer PLN facing away from the substrate 50.
  • This layout makes the first An auxiliary signal line layer 801 is provided in the same layer as the anode layer to avoid the increase in the thickness of the display panel due to the introduction of the first auxiliary signal line layer 801.
  • the first auxiliary signal line layer 801 is laid out in the anode spacer region 9061, so that the first auxiliary signal line layer 801 is located on the side of the transfer portion 806 facing away from the substrate 50, for example, A corresponding via structure can be provided between the first auxiliary signal line layer 801 and each of the transfer portions 806, so that the first auxiliary signal line layer 801 can pass through the corresponding via structure respectively. It is coupled with each of the adapter portions 806.
  • the sub-pixel areas located in the same row along the first direction are divided into a plurality of independent sub-pixel area groups, and each sub-pixel area group includes phases.
  • At least two adjacent sub-pixel areas are provided with a transfer portion 806 corresponding to the sub-pixel area group one to one at the same time, and the initialization signal line pattern in each sub-pixel area in the corresponding sub-pixel area group is changed by the transfer portion 806 904 are coupled together, and the transfer portions 806 in each of the sub-pixel area groups are respectively coupled to the first auxiliary signal line layer 801; this arrangement makes the first auxiliary signal line layer 801
  • the initialization signal line patterns 904 in each sub-pixel area are all coupled together, so that the first auxiliary signal line layer 801 can provide initialization signals for the initialization signal line patterns 904 in each sub-pixel area; therefore, the present disclosure
  • the initialization signal line pattern 904 in each sub-pixel area is respectively coupled to the first auxiliary signal line layer 801 arranged in the anode spacer area 9061, which solves the problem of the limited layout space of the display panel. There is a problem that the initialization signal line patterns 904 in the same row are not easily connected together.
  • the first auxiliary signal line layer 801 can be laid out in all the anode spacer regions 9061 in the display area, and the initialization signal line pattern 904 in each sub-pixel region and the second An auxiliary signal line layer 801 is coupled to better ensure the stability of the initialization signal transmitted on the initialization signal line pattern 904 in each sub-pixel area.
  • the first auxiliary signal line layer 801 and the anode layer can be arranged in the same layer, which is more conducive to the thinning of the display panel.
  • each initialization pattern in the sub-pixel area group is coupled to the first auxiliary signal line pattern.
  • the initializing signal line pattern 904 in the at least two sub-pixel regions coupled by the transfer portion 806 is coupled to the first auxiliary signal line layer 801. Therefore, in the display panel provided by the embodiment of the present disclosure, While realizing the coupling of each of the initialization signal line patterns 904 with the first auxiliary signal line patterns, the number of via structures penetrating the planar layer PLN is effectively reduced.
  • initialization signal line pattern 904 is used to provide an initialization signal (Vinit) for the corresponding sub-pixel driving circuit, and can also be used to provide a reference signal (Vref) for the corresponding sub-pixel driving circuit.
  • the initialization signal line pattern 904 and the active layer in the transistor structure of the display panel are provided with the same layer and the same material.
  • the above-mentioned setting the initialization signal line pattern 904 and the active layer in the transistor structure in the same layer and the same material not only enables the initialization signal line pattern 904 and the active layer to be in the same patterning process
  • the first electrode (or the second electrode) of the transistor structure coupled to the initialization signal line pattern 904 in the display panel is also made of the active layer, so that the first electrode (or The second pole) can be coupled with the initialization signal line pattern 904 to form an integrated structure, thereby further saving the layout space occupied by the transistor structure and the initialization signal line pattern 904, which is more conducive to improving the display panel Resolution.
  • the first auxiliary signal line layer 801 and the anode layer are made of the same layer and the same material.
  • the first auxiliary signal line layer 801 and the anode layer are arranged in the same layer and the same material, so that the first auxiliary signal line layer 801 and the anode layer can be formed in the same patterning process without requiring An additional patterning process dedicated to the production of the first auxiliary cathode layer is added, thereby effectively simplifying the production process and saving production costs.
  • first auxiliary signal line layer 801 and the anode layer are arranged in the same layer and the same material, a certain distance needs to be reserved between the first auxiliary signal line layer 801 and the anode layer to avoid The first auxiliary signal line layer 801 and the anode layer are short-circuited, which affects the yield of the display panel.
  • the display panel further includes:
  • the conductive connection portion layer includes a first conductive connection portion 9091 located in each of the sub-pixel areas. In the same sub-pixel area, the first conductive connection portion 9091 is located on the substrate 50 An orthographic projection, and the orthographic projection of the initialization signal line pattern 904 on the substrate 50 has a first overlap area, and the first conductive connection portion 9091 passes through a first via hole disposed in the first overlap area Coupled to the initialization signal line pattern 904, the orthographic projection of the first conductive connection portion 9091 on the substrate 50 has a third overlap with the orthographic projection of the transfer pattern 8061 on the substrate 50 Area, the first conductive connection portion 9091 is coupled to the transfer pattern 8061 through a third via provided in the third overlap area;
  • each of the first conductive connection portions 9091 to which each of the adapter portions 806 are coupled there is a target conductive connection portion 9091', and the orthographic projection of the target conductive connection portion 9091' on the substrate 50 is the same as
  • the orthographic projection of the first auxiliary signal line layer 801 on the substrate 50 forms a second overlapping area, and the target conductive connection portion 9091' passes through the second via hole disposed in the second overlapping area and the The first auxiliary signal line layer 801 is coupled.
  • the conductive connection portion layer is located between the transfer layer and the first auxiliary signal line layer 801, and the conductive connection portion layer may be made of the first source/drain metal layer in the display panel.
  • the conductive connection portion layer includes a plurality of first conductive connection portions 9091 one-to-one corresponding to the plurality of pixel regions, and the first conductive connection portions 9091 are located in the corresponding sub-pixel regions.
  • the specific structure of the first conductive connection portion 9091 included in the conductive connection portion layer can be set according to actual needs, but it should satisfy that in the same sub-pixel area, the first conductive connection portion
  • the orthographic projection of 9091 see the target conductive connecting portion 9091' in FIG.
  • the substrate 50 has a first overlap area with the orthographic projection of the initialization signal line pattern 904 on the substrate 50, and
  • the orthographic projection of the first conductive connecting portion 9091 on the substrate 50 and the orthographic projection of the transfer pattern 8061 on the substrate 50 have a third overlapping area; in this way, the first conductive connecting portion 9091 is arranged
  • the first via 61 in the first overlap area can be coupled to the initialization signal line pattern 904, and the first conductive connection portion 9091 passes through the third via provided in the third overlap area.
  • 63 can be coupled to the transfer pattern 8061 (see the transfer portion 806 in FIG. 4), thereby realizing that the initialization signal line pattern 904 is coupled to the transfer pattern 8061 through the first conductive connection portion 9091 catch.
  • first conductive connection portion 9091 In the first conductive connection portion 9091 to which each switch pattern 8061 in each switch portion 806 is correspondingly coupled, there is a target conductive connection portion 9091', and the target conductive connection portion 9091' is on the substrate 50
  • the orthographic projection of the first auxiliary signal line layer 801 and the orthographic projection of the first auxiliary signal line layer 801 on the substrate 50 can form a second overlapping area.
  • the two via holes 62 are coupled to the first auxiliary signal line layer 801.
  • FIG. 4 also shows a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, and a flat layer PLN.
  • the first conductive connection portion 9091 is located on the side of the initialization signal line pattern 904 facing away from the substrate 50, between the first conductive connection portion 9091 and the initialization signal line pattern 904 It includes a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD; at the same time, the first conductive connection portion 9091 is located on the side of the transfer pattern 8061 facing away from the substrate 50.
  • An interlayer insulating layer ILD is included between the first conductive connecting portion 9091 and the transfer pattern 8061; in this way, after the interlayer insulating layer ILD is formed, a via etching process (via mask) can be used to form The first via 61 penetrating through a gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD, and the third via 63 penetrating the interlayer insulating layer ILD, form the first conductive connection After the portion 9091, the first conductive connection portion 9091 can be coupled to the initialization signal line pattern 904 through the first via 61, and can be coupled to the transfer pattern 8061 through the third via 63 In this way, the number of via masks is effectively reduced, the manufacturing process of the display panel is simplified, and the manufacturing cost is saved.
  • the transfer pattern 8061 and the first auxiliary signal line layer 801 are coupled to the target conductive connection portion 9091' to be coupled to the first auxiliary signal line layer 801.
  • Layer 801 is coupled to avoid making too deep vias between the transfer pattern 8061 and the first auxiliary signal line layer 801, which improves the transfer pattern 8061 and the first auxiliary signal line layer 801.
  • the reliability of the coupling between the signal line layers 801, and this arrangement allows the transfer pattern 8061 and the first auxiliary signal line layer 801 to have more layout modes, which better reduces the display panel Difficulty of layout and production process.
  • each sub-pixel area group including two sub-pixel areas when the transfer portion 806 is not provided in the display panel, the initialization signal line pattern 904 in each sub-pixel area is coupled to the conductive connection portion
  • the conductive connecting portion is to be coupled to the first auxiliary signal line layer 801 through the PLN hole (that is, the second via 62) penetrating the flat layer PLN, so that each sub-pixel area includes one for coupling to the first The PLN hole of the auxiliary signal line layer 801.
  • each sub-pixel area group two sub-pixel areas are provided to be coupled to the first auxiliary signal line layer 801 through the corresponding transfer portion 806 and a PLN hole penetrating the planarization layer PLN. Therefore, the number of PLN holes that need to be provided in the display panel is reduced by half, which is more beneficial to increase the layout space of the anode layer and the first auxiliary signal line layer 801.
  • the dotted frame in FIG. 5 shows that in two adjacent sub-pixel regions, two second vias 62 are provided, and each dotted frame in FIG. 6 shows In the two adjacent sub-pixel regions, only one second via 62 is provided.
  • each initialization signal line pattern 904 includes a first sub-pattern 9041 and a second sub-pattern 9042, which are located in the same row along the first direction.
  • the second sub-pattern 9042 in the previous sub-pixel area and the first sub-pattern 9041 in the next sub-pixel area form an integral structure; in each sub-pixel area, the second sub-pattern 9042
  • the orthographic projection on the substrate 50 and the orthographic projection of the first conductive connecting portion 9091 on the substrate 50 have the first overlapping area, and the first conductive connecting portion 9091 is disposed on the The first via 61 in the first overlapping area is coupled to the second sub-pattern 9042.
  • each initialization signal line pattern includes a first sub-pattern 9041 and a second sub-pattern 9042. In the same sub-pixel area, so The first sub-graphics 9041 and the second sub-graphics 9042 are arranged along the first direction.
  • the initialization signal line pattern adopts this structure, in adjacent sub-pixel areas, the second sub-pattern 9042 in the previous sub-pixel area and the first sub-pattern 9041 in the subsequent sub-pixel area are Adjacent.
  • the above arrangement is located in adjacent sub-pixel areas in the same row along the first direction.
  • the second sub-pattern 9042 in the previous sub-pixel area and the first sub-pattern 9041 in the latter sub-pixel area form an integrated structure, which is not only conducive to improvement.
  • the initialization signal transmitted on the initialization signal line pattern is stable, and can effectively reduce the difficulty of making the initialization signal line pattern.
  • the first sub-pattern 9041 and the second sub-pattern 9042 may be set.
  • this connection mode can better ensure the connection performance of the initialization signal line pattern and the first auxiliary signal line layer, and can more effectively improve the initialization signal line pattern transmission
  • the second sub-pattern 9042 is set to be coupled to the first conductive connection portion 9091, that is, as shown in FIG.
  • the first conductive connection portion 9091 and the second sub-pattern 9042 are coupled through a first via 61 located in the first overlapping area, and the first conductive connection portion 9091 is connected to the first auxiliary signal line layer 801 is coupled through a second via 62 located in the second overlapping area.
  • the display panel further includes:
  • a power signal line layer includes a power signal line pattern 901 arranged in each of the sub-pixel regions, at least a part of the power signal line pattern 901 extends along a second direction, and the second direction is The first direction intersects;
  • the power signal line layer is located between the initialization signal line layer and the anode layer, the power signal line layer includes a power signal line pattern 901 arranged in each of the sub-pixel regions, and the power source
  • the signal line pattern 901 has a one-to-one correspondence with the sub-pixel area, and the power signal line pattern 901 is located in the corresponding sub-pixel area.
  • At least part of the power signal line pattern 901 extends along the second direction, and the power signal line patterns 901 arranged in each column of sub-pixel regions are sequentially coupled along the second direction, and can be formed as an integral structure.
  • the third auxiliary signal line pattern 805 corresponds to the sub-pixel area one-to-one, the third auxiliary signal line pattern 805 is located in the corresponding sub-pixel area, and at least part of the third auxiliary signal line pattern 805 is along the first pixel area. Extending in one direction, the third auxiliary signal line patterns 805 located in the same row of sub-pixel regions along the first direction are sequentially coupled. For example, each third auxiliary signal line pattern 805 located in the same row of sub-pixel regions along the first direction is coupled in sequence.
  • the signal line pattern 805 is formed as an integral structure.
  • At least part of the power signal line pattern 901 extends along a second direction, and the second direction intersects the first direction. Therefore, in the same sub-pixel area, the third auxiliary signal line pattern 805 is located on the substrate.
  • the orthographic projection of the power signal line pattern 901 and the orthographic projection of the power signal line pattern 901 on the substrate form a fourth overlapping area, and the third auxiliary signal line pattern 805 can pass through the seventh overlapped area.
  • the via 67 is coupled to the power signal line pattern 901.
  • the power signal line patterns 901 located in the same column of sub-pixel areas along the second direction are sequentially coupled, and the third auxiliary signal line patterns 805 located in the same row of sub-pixel areas along the first direction are arranged.
  • the third auxiliary signal line pattern 805 is coupled to the power signal line pattern 901, so that the power signal line layer and the third auxiliary signal line layer together form a mesh
  • This arrangement effectively improves the stability of the power signal line layer, and the power signal transmitted on the power signal line layer is used to provide the source of the driving transistor in the sub-pixel driving circuit, and the sub-pixel driving
  • the display panel further includes a transistor structure and a storage capacitor Cst, and the storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2 arranged oppositely, so The first electrode plate Cst1 is located between the substrate and the second electrode plate Cst2, and the first electrode plate Cst1 and the gate electrode in the transistor structure are arranged in the same layer and the same material; the third auxiliary signal line The layer and the second electrode plate Cst2 are made of the same layer and the same material.
  • each film layer corresponding to the sub-pixel driving circuit is as follows: the active film layer, the first gate insulating layer, the first gate metal layer, and the second gate insulating layer are stacked in sequence in the direction away from the substrate. , The second gate metal layer, the interlayer insulating layer, the first source and drain metal layer and the flat layer.
  • the sub-pixel driving circuit includes a storage capacitor Cst and a plurality of transistor structures, the active film layer is used to form active patterns in the plurality of transistor structures, and the first gate metal layer is used to form the multiple transistor structures.
  • the gate of the transistor structure and the first plate Cst1 of the storage capacitor Cst, and the second gate metal layer is used to form the second plate Cst2 of the storage capacitor Cst.
  • the first electrode plate Cst1 and the gate electrode in the transistor structure are arranged in the same layer and the same material, so that the first electrode plate Cst1 and the gate electrode in the transistor structure can be formed simultaneously in the same patterning process , So as to better simplify the production process of the display panel and save the production cost.
  • arranging the third auxiliary signal line layer and the second electrode plate Cst2 in the same layer and the same material can achieve the same patterning process of the third auxiliary signal line layer and the second electrode plate Cst2. It is formed at the same time, so as to better simplify the production process of the display panel and save the production cost.
  • the above-mentioned “same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate through a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • the display panel further includes:
  • a light-emitting control signal line layer includes a light-emission control signal line pattern 903 located in each of the sub-pixel regions, and at least a part of the light-emission control signal line pattern 903 extends along the first direction;
  • a reset signal line layer includes a reset signal line pattern 905 located in each of the sub-pixel regions, and the reset signal line pattern 905 extends along the first direction;
  • the orthographic projection of the third auxiliary signal line pattern 805 on the substrate is formed in a wave-shaped structure.
  • the light-emission control signal line layer includes light-emission control signal line patterns 903 corresponding to the sub-pixel areas one-to-one, the light-emission control signal line patterns 903 are located in the corresponding sub-pixel areas, and the light-emission control signal lines At least part of the pattern 903 extends along the first direction, and the light-emitting control signal line patterns 903 located in the same row of sub-pixel regions are electrically connected in sequence to form an integrated structure.
  • the reset signal line layer includes a reset signal line pattern 905 corresponding to the sub-pixel area one-to-one, the reset signal line pattern 905 is located in the corresponding sub-pixel area, and the reset signal line pattern 905 extends along a first direction .
  • the orthographic projection of the third auxiliary signal line pattern 805 on the substrate is positioned on the substrate with the light emission control signal line pattern 903 Between the orthographic projection of the reset signal line pattern 905 and the orthographic projection of the reset signal line pattern 905 on the substrate, and the third auxiliary signal line pattern 805 is formed into a wave-shaped structure; Each third auxiliary signal line pattern 805 in the area is sequentially coupled.
  • the third auxiliary signal line pattern 805 needs to occupy a larger horizontal layout space, and the third auxiliary signal line pattern 805 will not be connected to the light-emitting control signal line.
  • the patterns 903 overlap too much, thereby avoiding increasing the RC (resistance-capacitance) loading of the light-emitting control signal line pattern 903 and increasing the power consumption of the gate driving circuit in the display panel.
  • both the third auxiliary signal line pattern 805 and the second electrode plate Cst2 of the storage capacitor Cst are made of a second gate metal layer, the above arrangement does not need to reduce the second electrode of the storage capacitor Cst.
  • the area of the electrode plate Cst2 satisfies the layout space requirement of the third auxiliary signal line pattern 805, so that the area of the second electrode plate Cst2 of the storage capacitor Cst is large enough, which is more conducive to the gate of the driving transistor in the sub-pixel driving circuit.
  • the third auxiliary signal line pattern 805 is formed into a wave-shaped structure, more specifically, for example, a W-shaped structure, so that the third auxiliary signal line pattern 805 can make good use of the light emission control.
  • the layout space between the signal line pattern 903 and the reset signal line pattern 905 solves the problem of dynamic crosstalk and is more conducive to the development of the display panel in the direction of high resolution.
  • the display panel further includes:
  • a gate line layer includes a gate line pattern 902 located in each of the sub-pixel regions, and at least a part of the gate line pattern 902 extends along a first direction;
  • a data line layer includes a data line pattern 908 located in each of the sub-pixel regions, at least part of the data line pattern 908 extends along a second direction, the first direction and the second direction Intersect, the orthographic projection of the data line pattern 908 on the substrate overlaps the orthographic projection of the gate line pattern 902 on the substrate;
  • the conductive connection portion layer includes a third conductive connection portion 9093 and a fourth conductive connection portion 9094 located in each of the sub-pixel regions;
  • each of the sub-pixel driving circuits includes: a driving transistor (that is, a third transistor T3), a storage capacitor Cst, a first transistor T1 and a second transistor T2;
  • the gate of the driving transistor is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the gate of the driving transistor is connected to the second transistor T2 through the fourth conductive connection portion 9094 in the corresponding sub-pixel area.
  • the second electrode D2 of the storage capacitor Cst is coupled to the second electrode D1 of the first transistor T1 through the third conductive connection portion 9093 in the corresponding sub-pixel area;
  • the gate 201g of the first transistor T1 and the gate 202g of the second transistor T2 are respectively coupled to the gate line pattern 902 in the corresponding sub-pixel area;
  • the orthographic projection of the gate line pattern 902 on the substrate is the same as
  • the orthographic projection of the third conductive connecting portion 9093 on the substrate does not overlap, and/or the orthographic projection of the grid line pattern 902 on the substrate and the fourth conductive connecting portion 9094 on the substrate
  • the orthographic projections on do not overlap.
  • the gate line layer includes a plurality of gate line patterns 902, and the gate line patterns 902 correspond to the plurality of sub-pixel regions in a one-to-one manner.
  • the gate line patterns 902 are located in the corresponding sub-pixel regions and are used for
  • the sub-pixel driving circuit corresponding to the sub-pixel area provides scanning signals. At least part of each of the gate line patterns 902 extends along the first direction, and the gate line patterns 902 in the sub-pixel regions located in the same row along the first direction are electrically connected in sequence to form an integral structure.
  • the data line layer includes a plurality of data line patterns 908, the data line patterns 908 correspond to the plurality of sub-pixel areas one-to-one, and the data line patterns 908 are located in the corresponding sub-pixel areas and are used for the sub-pixels.
  • the sub-pixel driving circuit corresponding to the area provides data signals. At least a part of each of the data line patterns 908 extends along the second direction, and the data line patterns 908 in the sub-pixel regions in the same column along the second direction are electrically connected in sequence to form an integral structure.
  • the conductive connection portion layer may be made of the first source/drain metal layer in the display panel, and the specific structure of the third conductive connection portion 9093 and the fourth conductive connection portion 9094 included in the conductive connection portion layer may be based on actual conditions. It needs to be provided. Illustratively, at least part of the third conductive connecting portion 9093 extends along the second direction, and at least part of the fourth conductive connecting portion 9094 extends along the second direction.
  • the sub-pixel driving circuits correspond to the sub-pixel regions one to one, and each of the sub-pixel driving circuits includes a driving transistor, a storage capacitor Cst, a first transistor T1, and a second transistor T2; the driving transistor can generate For driving signals for driving the light-emitting element to emit light, the gate of the driving transistor is coupled to the first plate Cst1 of the storage capacitor Cst. For example, the gate of the driving transistor can be multiplexed as the storage capacitor The first plate Cst1 of Cst.
  • the gate of the driving transistor can also be coupled to the second electrode D2 of the second transistor T2 through the fourth conductive connection portion 9094 in the corresponding sub-pixel area, and the first electrode S2 of the second transistor T2 is connected to the The second electrode of the driving transistor is coupled, and the gate 202g of the second transistor T2 is coupled to the gate line pattern 902 in the corresponding sub-pixel area.
  • the second electrode plate Cst2 of the storage capacitor Cst is coupled to the second electrode D1 of the first transistor T1 through the third conductive connection portion 9093 in the corresponding sub-pixel area, and the first electrode of the first transistor T1 is S1 is coupled to the data line pattern 908 in the corresponding sub-pixel area, and the gate 201g of the first transistor T1 is coupled to the gate line pattern 902 in the corresponding sub-pixel area.
  • the gate of the driving transistor can be coupled to the second stage D2 of the second transistor T2 through the fourth conductive connection portion 9094, and can pass through the storage capacitor Cst, and the third conductive connection portion 9093 and the first transistor T1 The diode D1 is coupled. Therefore, the signals on the third conductive connecting portion 9093 and the fourth conductive connecting portion 9094 can affect the gate signal of the driving transistor.
  • the orthographic projection of the third conductive connecting portion 9093 on the substrate does not overlap, and/or the orthographic projection of the grid line pattern 902 on the substrate and the fourth conductive connecting portion 9094 on the substrate
  • the orthographic projections on the above do not overlap; so that in the same sub-pixel area, in the direction perpendicular to the substrate, the gate line pattern 902 can only overlap with the data line pattern 908, but not with the
  • the third conductive connection portion 9093 and/or the fourth conductive connection portion 9094 overlap, thereby preventing the data line pattern 908 from being connected to the third conductive connection portion 9093 and/or the fourth conductive connection portion 9093 and/or the fourth conductive connection portion through the gate line pattern 902
  • the portion 9094 forms a series of parasitic electricity, which effectively improves the crosstalk problem of the gate voltage change of the driving transistor caused by the jump of the data signal transmitted on the data line pattern 908.
  • the display panel provided by the above embodiment, when the display panel is in the light-emitting state, even if the voltage of the data signal transmitted on the data line pattern 908 jumps, the gate voltage of the driving transistor will not be driven by the parasitic capacitance. Therefore, the stability of the gate voltage of the driving transistor is well ensured, the static crosstalk phenomenon is avoided, and the display quality of the display panel is effectively improved.
  • the conductive connection portion layer further includes a second conductive connection portion 9092 located in each of the sub-pixel areas, and the second conductive connection portion 9092 and the anode pattern 906 corresponding to the sub-pixel area where it is located The orthographic projections on the substrate overlap, and the second conductive connecting portion 9092 is coupled to the anode pattern 906 at the overlap;
  • Each of the sub-pixel driving circuits further includes a fifth transistor T5, an eighth transistor T8, and a ninth transistor T9;
  • the gate 205g of the fifth transistor T5 is coupled to the corresponding reset signal line pattern 905, the first pole S5 of the fifth transistor T5 is coupled to the corresponding initialization signal line pattern 904, and the fifth transistor
  • the second pole D5 of T5 is coupled to the third conductive connecting portion 9093 through a fourth via 64;
  • the gate 208g of the eighth transistor T8 is coupled to the corresponding reset signal line pattern 905, the first electrode S8 of the eighth transistor T8 is coupled to the corresponding initialization signal line pattern 904, and the eighth transistor
  • the second pole D8 of T8 is coupled to the second conductive connecting portion 9092 through a fifth via 65;
  • the gate 209g of the ninth transistor T9 is coupled to the corresponding light-emitting control signal line pattern 903, and the first electrode S9 of the ninth transistor T9 is coupled to the fourth conductive connection portion 9094 through a sixth via 66 , The second electrode D9 of the ninth transistor T9 is floating;
  • the third auxiliary signal line pattern 805 includes a first auxiliary part, a second auxiliary part, and a third auxiliary part that are sequentially coupled; in a sub-pixel area, the orthographic projection of the first auxiliary part on the substrate , Located between the orthographic projection of the fifth via 65 on the substrate and the orthographic projection of the sixth via 66 on the substrate, the orthographic projection of the second auxiliary part on the substrate , Located between the orthographic projection of the fifth via 65 on the substrate and the orthographic projection of the fourth via 64 on the substrate; the orthographic projection of the third auxiliary part on the substrate , Located between the orthographic projection of the sixth via 66 on the substrate and the orthographic projection of the fourth via 64 on the substrate.
  • the conductive connecting portion layer includes a plurality of second conductive connecting portions 9092, and the second conductive connecting portions 9092 are located in the plurality of sub-pixel regions in a one-to-one correspondence, and the second conductive connecting portions 9092 and its sub-pixel regions are located in a one-to-one correspondence.
  • the orthographic projection of the anode pattern 906 corresponding to the pixel area on the substrate overlaps, and the second conductive connection portion 9092 is coupled to the anode pattern 906 at the overlap.
  • the eighth transistor T8 can be turned on or off under the control of the reset signal transmitted by the reset signal line pattern 905 to which it is correspondingly coupled, for the anode pattern 906 coupled to the second conductive connection portion 9092. Perform a reset.
  • the fifth transistor T5 can be turned on or off under the control of the reset signal transmitted by the reset signal line pattern 905 to which it is coupled, and is used to perform the second plate Cst2 of the storage capacitor Cst coupled to it. Reset.
  • the fifth via 65 and the fourth via 64 are arranged along a first direction, and the sixth via 66 is closer to the light emitting control signal line pattern than the fourth via 64 903, the orthographic projection of the fourth via 64 on the substrate, the orthographic projection of the fifth via 65 on the substrate, and the orthographic projection of the sixth via 66 on the substrate
  • the connection between them can form a triangle-like structure.
  • the fourth via 64 hole, the fifth via hole 65 and the sixth via hole 66 are all via holes penetrating the interlayer insulating layer (ILD layer).
  • the above arrangement of the third auxiliary signal line pattern 805 includes the first auxiliary part, the second auxiliary part, and the third auxiliary part that are sequentially coupled, so that the third auxiliary signal line pattern 805 can be used reasonably
  • the space between the fourth via hole 64, the fifth via hole 65 and the sixth via hole 66 makes the third auxiliary signal line pattern 805 formed into a W-shaped structure, so that the third The auxiliary signal line pattern 805 can make good use of the layout space between the light-emitting control signal line pattern 903 and the reset signal line pattern 905. While solving the problem of dynamic crosstalk, it is more conducive to the orientation of the display panel. The direction of high resolution development. It is worth noting that the above layout can support display panels with a pixel resolution of 480PPI.
  • the display panel further includes:
  • a data line layer includes a data line pattern 908 located in each of the sub-pixel regions, at least part of the data line pattern 908 extends along the second direction;
  • the adjacent third auxiliary signal line patterns 805 in the same row of sub-pixel regions along the first direction form a shielding portion 8051 at the coupling position, the shielding portion 8051 extends along the second direction, and the shielding portion 8051
  • the orthographic projection on the substrate overlaps the orthographic projection of the data line pattern 908 on the substrate, and in the direction perpendicular to the second direction, the width of the shielding portion 8051 is larger than that of the data line The width of the graphic 908.
  • the shielding portion 8051 may be formed in a rectangular-like structure extending along the second direction, and by setting the orthographic projection of the shielding portion 8051 on the substrate and the data line pattern 908 in the The orthogonal projections on the substrate overlap, so that the shielding portion 8051 can shield the data line pattern 908, thereby improving the static crosstalk phenomenon caused by the jump of the data signal transmitted on the data line pattern 908.
  • the width of the shielding portion 8051 is greater than the width of the data line pattern 908, so that the overlapping area of the shielding portion 8051 and the data line pattern 908 is greater. Larger, it is more conducive to improving the static crosstalk phenomenon caused by the jump of the data signal transmitted on the data line pattern 908.
  • the shielding portion 8051 and the adjacent third auxiliary signal line pattern 805 may form an integral structure, but it is not limited to this.
  • the display panel further includes:
  • a data line layer includes a data line pattern 908 located in each of the sub-pixel regions, at least part of the data line pattern 908 extends along a second direction, the first direction and the second direction intersect;
  • a power signal line layer includes a power signal line pattern 901 located in each of the sub-pixel regions, at least part of the power signal line pattern 901 extends along the second direction;
  • the orthographic projection of the power signal line pattern 901 on the substrate is located at the gate of the driving transistor (that is, the gate 203g of the third transistor T3) on the substrate Between the orthographic projection and the orthographic projection of the data line pattern 908 on the substrate.
  • the power signal line pattern 901 extends along the second direction
  • at least part of the data line pattern 908 extends along the second direction.
  • the orthographic projection of the power signal line pattern 901 on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the data line pattern 908 on the substrate.
  • the distance between the data line pattern 908 and the gate of the driving transistor is made longer, and the power signal line pattern 901 can be formed between the data line pattern 908 and the gate of the driving transistor.
  • Good barrier thereby reducing the lateral parasitic capacitance formed between the data line pattern 908 and the gate of the driving transistor in the same sub-pixel area, effectively improving the stability of the gate potential of the driving transistor sex.
  • the power signal line pattern 901 includes a first power source part 9011 and a second power source part 9012 that are coupled to each other, and the first power source part 9011 extends along the first power source part 9011. Extending in two directions, the second power supply portion 9012 protrudes from the first power supply portion 9011 in a direction away from the data line pattern 908 in the sub-pixel area where it is located; perpendicular to the second direction and parallel to the In the direction of the substrate, the width L1 of the first power supply portion 9011 is greater than the width L2 of the second power supply portion 9012;
  • the orthographic projection of the first pole of the driving transistor (that is, the first pole S3 of the third transistor T3) on the substrate is the same as that of the first power supply portion 9011 in the corresponding sub-pixel area on the substrate.
  • the orthographic projections overlap, and the first pole of the driving transistor and the first power supply portion 9011 are coupled at the overlap.
  • the specific structure of the power signal line pattern 901 is various.
  • the power signal line pattern 901 includes a first power source portion 9011 and a second power source portion 9012 that are coupled to each other.
  • the first power source The portion 9011 extends along the second direction, and a first spacer area is formed between the first power portion 9011 and the data line pattern 908 in the sub-pixel area where it is located; the second power portion 9012 is away from the sub-pixel area where it is located.
  • the direction of the data line pattern 908 protrudes from the first power supply portion 9011, and a second spacer is formed between the second power supply portion 9012 and the data line pattern 908, along a direction perpendicular to the second direction Above, the maximum width L3 of the second spacer is greater than the maximum width of the first spacer L4.
  • the first power source 9011 in the corresponding sub-pixel area is on the substrate.
  • the orthographic projections on the above overlap, so that the first pole of the driving transistor and the first power supply portion 9011 can be coupled through the connection hole 69 provided at the overlap.
  • the above arrangement is in a direction perpendicular to the second direction and parallel to the substrate, the width of the first power supply portion 9011 is greater than the width of the second power supply portion 9012, and the first pole of the driving transistor
  • the orthographic projection on the substrate overlaps the orthographic projection of the first power supply portion 9011 on the substrate in the corresponding sub-pixel area, and the first pole of the driving transistor and the first power supply portion are overlapped.
  • the display panel further includes:
  • a first shielding layer the first shielding layer includes a first shielding pattern 804 located in each of the sub-pixel regions, and the orthographic projection of the first shielding pattern 804 on the substrate and the first power supply part 9011
  • the orthographic projections on the substrate overlap, where the first shielding pattern 804 is coupled to the first power supply portion 9011; at least part of the first shielding pattern 804 is along the second direction Extending, the orthographic projection of the first shielding pattern 804 on the substrate overlaps the orthographic projection of the data line pattern 908 on the substrate.
  • the first shielding layer includes a plurality of first shielding patterns 804, the first shielding patterns 804 have a one-to-one correspondence with the sub-pixel regions, and the first shielding patterns 804 are located in the corresponding sub-pixel regions.
  • at least part of the first shielding pattern 804 extends along the second direction
  • at least part of the data line pattern 908 extends along the second direction.
  • the first The orthographic projection of the shielding pattern 804 on the substrate overlaps the orthographic projection of the data line pattern 908 on the substrate; this arrangement enables the first shielding pattern 804 to be formed with the data line pattern 908
  • the larger overlapping area makes the shielding effect of the first shielding pattern 804 on the data line pattern 908 more significant.
  • the first shielding layer is made of the second gate metal layer in the display panel, that is, the first shielding layer can be in the same position as the second plate Cst2 of the storage capacitor Cst. Formed in the sub-patterning process.
  • the first shielding layer transmits a signal with a fixed potential.
  • the first shielding pattern 804 is coupled to the power signal line pattern 901 in the display panel, and has a power signal transmitted on the power signal line. The same stable potential.
  • the 804 is coupled to the first power supply part; since the first power supply part has a larger width in a direction perpendicular to the second direction, this arrangement is beneficial to the first shielding pattern 804 and the A larger overlap area is formed between the first power supply parts, which is more conducive to forming a connection hole with a larger aperture at the overlap point, and ensures that the first shielding pattern 804 and the first power supply part are better. Coupling performance.
  • the parasitic formed between the data line pattern 908 and the gate of the adjacent driving transistor is well shielded. Capacitance, thereby effectively improving the crosstalk phenomenon caused by the change of the data signal in the display panel to the gate of the driving transistor.
  • the first electrode S1 of the first transistor T1 extends along the first direction, and the first electrode S1 of the first transistor T1 is on the substrate.
  • the orthographic projection of the corresponding sub-pixel area overlaps the orthographic projection of the data line pattern 908 on the substrate.
  • the first electrode S1 of the first transistor T1 and the data line pattern 908 in the corresponding sub-pixel area overlap The overlap is coupled by a first connecting hole 68; the orthographic projection of the first connecting hole 68 on the substrate and the orthographic projection of the second power supply portion 9092 on the substrate are aligned with the second The direction is perpendicular to the arrangement.
  • the specific structure of the first electrode S1 of the first transistor T1 is various.
  • the first electrode S1 of the first transistor T1 extends along the first direction.
  • the orthographic projection of the first connecting hole 68 on the substrate and the orthographic projection of the second power supply portion 9012 on the substrate are arranged in a direction perpendicular to the second direction, so that the first A connecting hole 68 can be formed in the vicinity of the second spacer area, and since the distance between the second power supply portion 9012 and the data line pattern 908 in the second spacer area is longer, it is more conducive to increase the
  • the aperture of the first connecting hole 68 effectively improves the coupling performance between the first electrode S1 of the first transistor T1 and the data line pattern 908.
  • the display panel further includes:
  • a gate line layer includes a gate line pattern 902 located in each of the sub-pixel regions, and at least a part of the gate line pattern 902 extends along a first direction;
  • a reset signal line layer includes a reset signal line pattern 905 located in each of the sub-pixel regions, and the gate line pattern 902 in the current sub-pixel region is adjacent to the next sub-pixel region along the second direction
  • the reset signal line pattern 905 in is formed as an integral structure.
  • each of the gate line patterns 902 extends along the first direction, and the gate line patterns 902 in the sub-pixel regions in the same row along the first direction are electrically connected in sequence to form an integrated structure
  • Each of the reset signal line pattern 905 extends along the first direction, the gate line pattern 902 in the current sub-pixel area and the reset signal line pattern 905 in the next sub-pixel area adjacent to the second direction, It may be formed as an integral structure by a connecting portion extending in the second direction.
  • the gate line pattern 902, the reset signal line pattern 905, and the light emission control signal line pattern 903 included in the display panel may all be made of a first gate metal layer, so that the gate line pattern 902, the reset signal The line pattern 905 and the light-emitting control signal line pattern 903 can be formed in the same patterning process, thereby effectively simplifying the manufacturing process and saving production costs.
  • the gate line pattern 902 in the current sub-pixel area and the reset signal line pattern 905 in the next sub-pixel area adjacent to the second direction are formed as an integral structure, so that the gate line pattern 902 in the sub-pixel area of the previous row is transmitted
  • the scan signal can be used as the reset signal transmitted on the reset signal line pattern 905 in the next row of sub-pixels, thereby avoiding the introduction of a special signal transmission path by providing a reset signal for the reset signal line pattern 905, and effectively reducing the resetting.
  • the layout space occupied by the signal line pattern 905 is more conducive to improving the resolution of the display panel.
  • the above layout method can support a display panel with a pixel resolution of 400PPI.
  • the display panel further includes: a power signal line pattern, a data line pattern, a reset signal line pattern, a light emission control signal line pattern, and a gate line located in each of the sub-pixel regions.
  • Graphics also includes a sub-pixel drive circuit corresponding to the sub-pixel area one-to-one, each of the sub-pixel drive circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, The sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the storage capacitor;
  • the gate of the first transistor is coupled to the gate line pattern, the first electrode of the first transistor is coupled to the data line pattern, and the second electrode of the first transistor is connected to the storage capacitor
  • the second plate is coupled, and the first plate of the storage capacitor is coupled to the gate of the third transistor
  • the gate of the second transistor is coupled to the gate line pattern, the first electrode of the second transistor is coupled to the second electrode of the third transistor, and the second electrode of the second transistor is coupled to the second electrode of the third transistor.
  • the gate of the third transistor is coupled;
  • the first electrode of the third transistor is coupled to the power signal line pattern
  • the gate of the fourth transistor is coupled to the reset signal line pattern, the first electrode of the fourth transistor is coupled to the initialization signal line pattern, and the second electrode of the fourth transistor is coupled to the first The gates of the three transistors are coupled;
  • the gate of the fifth transistor is coupled to the reset signal line pattern, the first electrode of the fifth transistor is coupled to the initialization signal line pattern, and the second electrode of the fifth transistor is coupled to the memory
  • the second plate of the capacitor is coupled;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the initialization signal line pattern, and the second electrode of the sixth transistor is coupled to the storage capacitor ⁇ second plate coupling;
  • the gate of the seventh transistor is coupled to the light emission control signal line pattern, the first electrode of the seventh transistor is coupled to the second electrode of the third transistor, and the second electrode of the seventh transistor corresponds to ⁇ anodic pattern coupling;
  • the gate of the eighth transistor is coupled to the reset signal line pattern, the first electrode of the eighth transistor is coupled to the initialization signal line pattern, and the second electrode of the eighth transistor is coupled to the corresponding anode Graphics coupling
  • the gate of the ninth transistor is coupled to the corresponding light emission control signal line pattern, the first electrode of the ninth transistor is coupled to the gate of the third transistor, and the second electrode of the ninth transistor is Extremely floating.
  • the gate 201g of the first transistor T1 is coupled to the gate line pattern 902, and the first electrode S1 of the first transistor T1 is coupled to the data line pattern 908 Coupled, the second electrode D1 of the first transistor T1 is coupled to the second electrode Cst2 of the storage capacitor Cst, and the first electrode Cst1 of the storage capacitor Cst and the third transistor T3 (that is, the The gate 203g of the driving transistor) is coupled;
  • the gate 202g of the second transistor T2 is coupled to the gate line pattern 902, the first electrode S2 of the second transistor T2 is coupled to the second electrode D3 of the third transistor T3, and the second The second electrode D2 of the transistor T2 is coupled to the gate 203g of the third transistor T3;
  • the first electrode S3 of the third transistor T3 is coupled to the power signal line pattern 901;
  • the gate 204g of the fourth transistor T4 is coupled to the reset signal line pattern 905, the first pole S4 of the fourth transistor T4 is coupled to the initialization signal line pattern 904, and the The second electrode D4 is coupled to the gate 203g of the third transistor T3;
  • the gate 205g of the fifth transistor T5 is coupled to the reset signal line pattern 905, the first pole S5 of the fifth transistor T5 is coupled to the initialization signal line pattern 904, and the The second electrode D5 is coupled to the second electrode plate Cst2 of the storage capacitor Cst;
  • the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903, the first electrode S6 of the sixth transistor T6 is coupled to the initialization signal line pattern 904, and the first electrode S6 of the sixth transistor T6 is coupled to the initialization signal line pattern 904.
  • the diode D6 is coupled to the second plate Cst2 of the storage capacitor Cst;
  • the gate 207g of the seventh transistor T7 is coupled to the light emission control signal line pattern 903, the first electrode S7 of the seventh transistor T7 is coupled to the second electrode D3 of the third transistor T3, and the seventh transistor T7 is coupled to the second electrode D3 of the third transistor T3.
  • the second electrode D7 of the transistor T7 is coupled to the anode pattern 906 of the corresponding light-emitting element EL, and the cathode of the light-emitting element EL is coupled to the negative power signal line VSS;
  • the gate 208g of the eighth transistor T8 is coupled to the reset signal line pattern 905, the first pole S8 of the eighth transistor T8 is coupled to the initialization signal line pattern 904, and the The second electrode D8 is coupled to the anode pattern 906 of the corresponding light emitting element EL.
  • At least part of the power signal line pattern 901 and the data line pattern 908 extend along the second direction; at least part of the gate line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 905 are all Extending in a first direction, the first direction intersects the second direction.
  • the first direction includes the X direction
  • the second direction includes the Y direction.
  • the multiple sub-pixel areas can be divided into multiple rows of sub-pixel areas sequentially arranged along the second direction, and multiple columns of sub-pixel areas sequentially arranged along the first direction.
  • Each of the sub-pixel areas located in the same row The gate line patterns 902 are electrically connected in sequence to form an integrated structure; the light-emitting control signal line patterns 903 located in the same row of sub-pixel areas are electrically connected in sequence to form an integrated structure; the data line patterns located in the same column of sub-pixel areas 908 are electrically connected in sequence to form an integrated structure; the power signal line patterns 901 located in the sub-pixel area of the same column are electrically connected in sequence to form an integrated structure.
  • each film layer in the display panel is as follows: a buffer layer, a sub-pixel driving circuit film layer, an anode layer, a pixel defining layer, and a spacer layer 70 are sequentially stacked on the substrate in a direction away from the substrate.
  • the layout of each film layer corresponding to the sub-pixel driving circuit is as follows: an active film layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, The second gate metal layer, the interlayer insulating layer, the first source and drain metal layer and the flat layer.
  • the active film layer is used to form the channel region (such as 101g ⁇ 109g), the first pole (such as S1 ⁇ S9) and the second pole (such as : D1 ⁇ D9), due to the doping effect of the active film layer corresponding to the first pole and the second pole, the conductivity will be better than that of the active film layer corresponding to the channel region;
  • the active film layer can be amorphous silicon or polysilicon , Oxide semiconductor materials, etc.
  • the first electrode and the second electrode may be doped with n-type impurities or p-type impurities.
  • the active film layer corresponding to the first electrode and the second electrode can be directly used as the source or drain of the corresponding transistor, or a metal material can also be used to make the source in contact with the first electrode. , Using a metal material to make the drain electrode in contact with the second electrode.
  • the active film layer is also used to form the initialization signal line pattern 904, and the part of the active film layer used to form the initialization signal line pattern 904 can have good conductivity due to the doping effect.
  • the first gate metal layer is used to form the gates of the transistors in the sub-pixel driving circuit (such as 201g to 209g), and the gate line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 905 included in the display panel.
  • the gate 203g of the third transistor T3 in each sub-pixel driving circuit is multiplexed as the first plate Cst1 of the storage capacitor Cst in the sub-pixel driving circuit.
  • the second gate metal layer is used to form the second plate Cst2 of the storage capacitor Cst, and the first shielding pattern 804 and the third auxiliary signal line layer included in the display panel.
  • the first source-drain metal layer is used to form the data line pattern 908, the power signal line pattern 901 and some conductive connections.
  • each work cycle includes a reset period P1, a write compensation period P2, and a light emitting period P3.
  • E1 represents the emission control signal transmitted on the emission control signal line pattern 903 in the current sub-pixel area
  • R1 represents the reset signal transmitted on the reset signal line pattern 905 in the current sub-pixel area
  • G1 represents the current sub-pixel area.
  • the gate scan signal is transmitted on the gate line pattern 902 in the.
  • the reset signal input by the reset signal line pattern 905 is at an active level
  • the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned on, and the signal transmitted by the initialization signal line pattern 904
  • the initialization signal is input to the gate 203g of the third transistor T3, the anode pattern 906 and the second plate of the storage capacitor, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared, and the third transistor T3
  • the gate 203g of T3 is reset, and the anode pattern 906 and the second plate of the storage capacitor are reset at the same time.
  • the reset signal input from the reset signal line pattern 905 is at an inactive level
  • the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are all turned off
  • the scan signal input from the gate line pattern 902 is at Effective level
  • the first transistor T1 and the second transistor T2 are controlled to be turned on
  • the data line pattern 908 writes a data signal, and is transmitted to the node N1 through the first transistor T1, and is coupled to the gate of the third transistor T3 through the storage capacitor.
  • the first transistor T1 and the second transistor T2 are turned on, so that the third transistor T3 is formed into a diode structure.
  • the first transistor T1, the third transistor T3, and the second transistor T2 work together to achieve the third The threshold voltage compensation of the transistor T3, when the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled to finally reach Vth+VDD, where VDD is the power signal voltage value, and Vth represents the threshold voltage of the third transistor T3.
  • the light emission control signal written in the light emission control signal line pattern 903 is at an effective level, and the sixth transistor T6 and the seventh transistor T7 are controlled to be turned on, and the power signal transmitted by the power signal line pattern 901 is input to the third transistor
  • the gate 203g of the third transistor T3 becomes Vint-Vdata+Vth+VDD, where Vdata represents the voltage value of the data signal, and Vint represents the voltage value of the initial signal, so that the third transistor T3 When turned on, the gate-source voltage corresponding to the third transistor T3 is Vdata-Vint+Vth, and the leakage current generated based on the gate-source voltage flows to the anode pattern 906 of the corresponding light-emitting element EL to drive the corresponding light-emitting element EL to emit light.
  • the sub-pixel driving circuit further includes a ninth transistor T9, the gate 209g of the ninth transistor T9 is coupled to the light emission control signal line pattern 903, and the first The pole S9 is coupled to the gate 203g of the third transistor T3, and the second pole D9 of the ninth transistor T9 is floating.
  • the light emission control signal written in the light emission control signal line pattern 903 is at an inactive level, and the ninth transistor T9 is controlled to be in an off state.
  • the light-emission control signal written in the light-emission control signal line pattern 903 is at an effective level, and the ninth transistor T9 is controlled to be in a conductive state.
  • the aforementioned sub-pixel driving circuit further includes the ninth transistor T9, so that during the light-emitting period, by turning on the ninth transistor T9, the excess charge accumulated in the gate 203g of the third transistor T3 can be discharged to ensure the first The potential of the gate 203g of the three transistor T3 is stable.
  • the embodiments of the present disclosure also provide a display device, including the display panel provided in the above-mentioned embodiments.
  • the sub-pixel areas located in the same row along the first direction are divided into a plurality of independent sub-pixel area groups, and each sub-pixel area group includes at least two adjacent sub-pixel areas.
  • the patterns 904 are all coupled together to realize that the first auxiliary signal line layer 801 can provide the initialization signal for the initialization signal line pattern 904 in each sub-pixel area; therefore, in the display panel provided by the above embodiment, each The initialization signal line pattern 904 in the sub-pixel area is separately coupled to the first auxiliary signal line layer 801 laid out in the anode spacer
  • the first auxiliary signal line layer 801 can be laid out in all the anode spacer regions 9061 in the display area, and the initialization signal line pattern 904 in each sub-pixel region can be combined with the first
  • the auxiliary signal line layer 801 is coupled to better ensure the stability of the initialization signal transmitted on the initialization signal line pattern 904 in each sub-pixel area.
  • the first auxiliary signal line layer 801 and the anode layer can be arranged in the same layer, which is more conducive to the thinning of the display panel.
  • each initialization pattern in the sub-pixel area group is coupled to the first auxiliary signal line pattern, Therefore, only one via structure needs to be provided between each transfer portion 806 and the first auxiliary signal line layer 801 to realize the coupling between the transfer portion 806 and the first auxiliary signal line layer 801.
  • the initialization signal line pattern 904 in the at least two sub-pixel regions coupled by the transfer portion 806 is coupled to the first auxiliary signal line layer 801. Therefore, in the display panel provided by the embodiment of the present disclosure, While realizing that each of the initialization signal line patterns 904 are coupled to the first auxiliary signal line patterns, the number of via structures penetrating the planarization layer PLN is effectively reduced.
  • the display device provided by the embodiment of the present disclosure includes the display panel provided by the above-mentioned embodiment, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and so on.
  • the embodiment of the present disclosure also provides a method for manufacturing a display panel, the display panel includes a plurality of sub-pixel areas distributed in an array, and the sub-pixel areas located in the same row along the first direction are divided into a plurality of independent sub-pixel area groups Each sub-pixel area group includes at least two adjacent sub-pixel areas; the manufacturing method includes:
  • the initialization signal line layer includes initialization signal line patterns arranged in each of the sub-pixel regions;
  • the transfer layer includes a transfer pattern disposed in each of the sub-pixel regions, at least a part of the transfer pattern extends along the first direction, and the transfer pattern and the initialization signal in the sub-pixel region where it is located Line pattern coupling; each of the transfer patterns located in the same sub-pixel area group is sequentially coupled along the first direction to form a transfer portion;
  • the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel regions one-to-one, the plurality of anode patterns are arranged at intervals, and an anode spacer region is formed between the adjacent anode patterns;
  • the first auxiliary signal line layer has a grid-like structure, and at least a part of the first auxiliary signal line layer is located in the anode spacer area and insulated from the anode pattern.
  • the transition in each sub-pixel area group The connection parts are respectively coupled with the first auxiliary signal line layer.
  • the sub-pixel areas located in the same row along the first direction are divided into a plurality of independent sub-pixel area groups, and each sub-pixel area group includes at least two adjacent sub-pixel area groups.
  • Sub-pixel areas and at the same time, a transfer portion 806 corresponding to the sub-pixel area group is provided, and the initialization signal line pattern 904 in each sub-pixel area in its corresponding sub-pixel area group is coupled to Together, and the transfer portion 806 in each sub-pixel area group is respectively coupled to the first auxiliary signal line layer 801; this arrangement makes the first auxiliary signal line layer 801 connect each sub-pixel area
  • the initializing signal line patterns 904 in the sub-pixel area are all coupled together, so that the first auxiliary signal line layer 801 can provide an initializing signal for the initializing signal line pattern 904 in each sub-pixel area; therefore, the embodiment of the present disclosure provides In the display panel manufactured by the manufacturing method, the initialization signal line pattern 904 in each sub-pixel area and the first auxiliary signal line layer 801 laid out in the anode spacer area 9061 are respectively coupled, which solves the problem of the limited layout space of the display panel. This makes it difficult to connect the initialization signal line patterns 904 in the same row.
  • the first auxiliary signal line layer 801 can be laid out in all the anode spacer regions 9061 in the display area, and the initialization signal line pattern in each sub-pixel region
  • the 904 is coupled to the first auxiliary signal line layer 801 to better ensure the stability of the initialization signal transmitted on the initialization signal line pattern 904 in each sub-pixel area.
  • the first auxiliary signal line layer 801 and the anode layer can be arranged in the same layer, which is more conducive to the thinning of the display panel.
  • the sub-pixel area group is divided and the transfer portion 806 is introduced to connect each initialization pattern in the sub-pixel area group to the first auxiliary
  • the signal line pattern is coupled, so that only one via structure needs to be provided between each transfer portion 806 and the first auxiliary signal line layer 801 to realize the transfer portion 806 and the first auxiliary signal line
  • the coupling between the layers 801 further realizes that the initialization signal line pattern 904 in the at least two sub-pixel regions coupled by the transfer portion 806 is coupled to the first auxiliary signal line layer 801. Therefore, the embodiment of the present disclosure provides In the display panel of, while realizing the coupling of each of the initialization signal line patterns 904 and the first auxiliary signal line patterns, the number of via structures penetrating the planarization layer PLN is effectively reduced.

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Abstract

本公开提供一种显示面板及其制作方法、显示装置。所述显示面板中多个子像素区沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区；转接层包括设置于各子像素区中的转接图形，转接图形与其所在子像素区中的初始化信号线图形耦接；位于同一子像素区组中的各转接图形沿第一方向依次耦接，形成转接部；第一辅助信号线层的至少部分位于阳极间隔区，且与阳极图形绝缘，各子像素区组中的转接部分别与第一辅助信号线层耦接。

Description

一种显示面板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2020年05月09日在中国提交的中国专利申请号No.202010388571.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
有源矩阵有机发光二极管(英文：Active-matrix organic light-emitting diode，简称：AMOLED)显示面板，以其自发光、低功耗、响应速度快等优点，被广泛的应用在各个领域。AMOLED显示面板包括子像素驱动电路和发光单元，通过子像素驱动电路驱动对应的发光单元发光，以实现显示面板的显示功能。
但是随着显示面板的分辨率越来越高，显示面板中的布局空间越来越小，在布局用于为子像素驱动电路提供初始化信号的初始化信号线图形时，位于同一行的初始化信号线图形不容易连接在一起，导致显示面板的生产成本增加。
发明内容
本公开的目的在于提供一种显示面板及其制作方法、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示面板，包括：基底，以及沿远离所述基底的方向依次层叠设置在所述基底上的初始化信号线层、转接层和阳极层；还包括呈阵列分布的多个子像素区，沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区；
所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形；
所述转接层包括设置于各所述子像素区中的转接图形，所述转接图形的至少部分沿所述第一方向延伸，所述转接图形与其所在子像素区中的初始化信号线图形耦接；位于同一子像素区组中的各所述转接图形沿所述第一方向依次耦接，形成转接部；
所述阳极层包括与所述多个子像素区一一对应的多个阳极图形，所述多个阳极图形间隔设置，在相邻的所述阳极图形之间形成阳极间隔区；
所述显示面板还包括：第一辅助信号线层，所述第一辅助信号线层为网格状结构，所述第一辅助信号线层的至少部分位于所述阳极间隔区，且与所述阳极图形绝缘，各所述子像素区组中的转接部分别与所述第一辅助信号线层耦接。
可选的，所述显示面板还包括：
导电连接部层，所述导电连接部层包括位于各所述子像素区中的第一导电连接部，在同一子像素区中，所述第一导电连接部在所述基底上的正投影，与
所述初始化信号线图形在所述基底上的正投影具有第一交叠区域，所述第一导电连接部通过设置在所述第一交叠区域的第一过孔与所述初始化信号线图形耦接，所述第一导电连接部在所述基底上的正投影，与所述转接图形在所述基底上的正投影具有第三交叠区域，所述第一导电连接部通过设置在所述第三交叠区域的第三过孔与所述转接图形耦接；
每个所述转接部对应耦接的各所述第一导电连接部中，存在一个目标导电连接部，所述目标导电连接部在所述基底上的正投影与所述第一辅助信号线层在所述基底上的正投影形成第二交叠区域，所述目标导电连接部通过设置在所述第二交叠区域的第二过孔与所述第一辅助信号线层耦接。
可选的，每个所述初始化信号线图形均包括第一子图形和第二子图形，沿第一方向位于同一行的相邻子像素区中，前一个子像素区中的第二子图形与后一个子像素区中的第一子图形形成为一体结构；
在每个子像素区中，所述第二子图形在所述基底上的正投影，与所述第 一导电连接部在所述基底上的正投影具有所述第一交叠区域，所述第一导电连接部通过设置在所述第一交叠区域的第一过孔与所述第二子图形耦接。
可选的，所述显示面板还包括：
电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
位于所述初始化信号线层与所述电源信号线层之间的第三辅助信号线层，所述第三辅助信号线层包括位于各所述子像素区中的第三辅助信号线图形，所述第三辅助信号线图形的至少部分沿第一方向延伸；在同一子像素区中，所述第三辅助信号线图形在所述基底上的正投影与所述电源信号线图形在所述基底上的正投影形成第四交叠区域，所述第三辅助信号线图形在所述第四交叠区域与所述电源信号线图形耦接；沿所述第一方向位于同一行子像素区中各第三辅助信号线图形依次耦接。
可选的，所述显示面板还包括：
发光控制信号线层，所述发光控制信号线层包括位于各所述子像素区中的发光控制信号线图形，所述发光控制信号线图形的至少部分沿所述第一方向延伸；
复位信号线层，所述复位信号线层包括位于各所述子像素区中的复位信号线图形，所述复位信号线图形沿所述第一方向延伸；
在同一子像素区中，所述第三辅助信号线图形在所述基底上的正投影，位于所述发光控制信号线图形在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影之间，所述第三辅助信号线图形形成为波浪形结构。
可选的，所述显示面板还包括：
栅线层，所述栅线层包括位于各所述子像素区中的栅线图形，所述栅线图形的至少部分沿第一方向延伸；
数据线层，所述数据线层包括位于各所述子像素区中的数据线图形，所述数据线图形的至少部分沿第二方向延伸，所述第一方向与所述第二方向相交，所述数据线图形在所述基底上的正投影与所述栅线图形在所述基底上的正投影交叠；
导电连接部层，所述导电连接部层包括位于各所述子像素区中的第三导电连接部和第四导电连接部；
与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管、存储电容、第一晶体管和第二晶体管；所述驱动晶体管的栅极复用为所述存储电容的第一极板，所述驱动晶体管的栅极通过对应的子像素区中的第四导电连接部与所述第二晶体管的第二极耦接，所述存储电容的第二极板通过对应的子像素区中的第三导电连接部与所述第一晶体管的第二极耦接；所述第一晶体管的栅极和所述第二晶体管的栅极分别与对应的子像素区中的栅线图形耦接；所述栅线图形在所述基底上的正投影与所述第三导电连接部在所述基底上的正投影不交叠，和/或所述栅线图形在所述基底上的正投影与所述第四导电连接部在所述基底上的正投影不交叠。
可选的，所述导电连接部层还包括位于各所述子像素区中的第二导电连接部，所述第二导电连接部与其所在子像素区对应的阳极图形在所述基底上的正投影交叠，所述第二导电连接部在该交叠处与该阳极图形耦接；
每个所述子像素驱动电路还包括第五晶体管、第八晶体管和第九晶体管；
所述第五晶体管的栅极与对应的复位信号线图形耦接，所述第五晶体管的第一极与对应的所述初始化信号线图形耦接，所述第五晶体管的第二极与所述第三导电连接部通过第四过孔耦接；
所述第八晶体管的栅极与对应的复位信号线图形耦接，所述第八晶体管的第一极与对应的所述初始化信号线图形耦接，所述第八晶体管的第二极与所述第二导电连接部通过第五过孔耦接；
所述第九晶体管的栅极与对应的发光控制信号线图形耦接，所述第九晶体管的第一极与所述第四导电连接部通过第六过孔耦接，所述第九晶体管的第二极浮接；
所述第三辅助信号线图形包括依次耦接的第一辅助部分、第二辅助部分和第三辅助部分；在一个子像素区中，所述第一辅助部分在所述基底上的正投影，位于所述第五过孔在所述基底上的正投影与所述第六过孔在所述基底上的正投影之间，所述第二辅助部分在所述基底上的正投影，位于所述第五过孔在所述基底上的正投影与所述第四过孔在所述基底上的正投影之间；所 述第三辅助部分在所述基底上的正投影，位于所述第六过孔在所述基底上的正投影与所述第四过孔在所述基底上的正投影之间。
可选的，所述显示面板还包括：
数据线层，所述数据线层包括位于各所述子像素区中的数据线图形，所述数据线图形的至少部分沿第二方向延伸；
沿所述第一方向位于同一行子像素区中相邻的第三辅助信号线图形在耦接处形成屏蔽部，所述屏蔽部沿所述第二方向延伸，所述屏蔽部在所述基底上的正投影与所述数据线图形在所述基底上的正投影交叠，沿垂直于所述第二方向的方向上，所述屏蔽部的宽度大于所述数据线图形的宽度。
可选的，所述显示面板还包括：
与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管；
数据线层，所述数据线层包括位于各所述子像素区中的数据线图形，所述数据线图形的至少部分沿第二方向延伸，所述第一方向与所述第二方向相交；
电源信号线层，所述电源信号线层包括位于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿所述第二方向延伸；
在同一所述子像素区中，所述电源信号线图形在所述基底上的正投影，位于所述驱动晶体管的栅极在所述基底上的正投影与所述数据线图形在所述基底上的正投影之间。
可选的，所述电源信号线图形包括相耦接的第一电源部和第二电源部，所述第一电源部沿所述第二方向延伸，所述第二电源部向远离其所在子像素区中的数据线图形的方向突出于所述第一电源部；在垂直于所述第二方向、且平行于所述基底的方向上，所述第一电源部的宽度大于所述第二电源部的宽度；
所述驱动晶体管的第一极在所述基底上的正投影，与对应的子像素区中的所述第一电源部在所述基底上的正投影交叠，所述驱动晶体管的第一极与所述第一电源部在该交叠处耦接。
可选的，所述显示面板还包括：
第一屏蔽层，所述第一屏蔽层包括位于各所述子像素区中的第一屏蔽图形，所述第一屏蔽图形在所述基底上的正投影与所述第一电源部在所述基底上的正投影交叠，在该交叠处所述第一屏蔽图形与所述第一电源部耦接；所述第一屏蔽图形的至少部分沿所述第二方向延伸，所述第一屏蔽图形在所述基底上的正投影与所述数据线图形在所述基底上的正投影交叠。
可选的，所述显示面板还包括：
栅线层，所述栅线层包括位于各所述子像素区中的栅线图形，所述栅线图形的至少部分沿第一方向延伸；
复位信号线层，所述复位信号线层包括位于各所述子像素区中的复位信号线图形，当前子像素区中的栅线图形与沿第二方向相邻的下一个子像素区中的复位信号线图形形成为一体结构。
可选的，所述显示面板还包括：位于各所述子像素区中的电源信号线图形、数据线图形、复位信号线图形和发光控制信号线图形和栅线图形；还包括与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和存储电容；
所述第一晶体管的栅极与所述栅线图形耦接，所述第一晶体管的第一极与所述数据线图形耦接，所述第一晶体管的第二极与所述存储电容的第二极板耦接，所述存储电容的第一极板与所述第三晶体管的栅极耦接；
所述第二晶体管的栅极与所述栅线图形耦接，所述第二晶体管的第一极与所述第三晶体管的第二极耦接，所述第二晶体管的第二极与所述第三晶体管的栅极耦接；
所述第三晶体管的第一极与所述电源信号线图形耦接；
所述第四晶体管的栅极与所述复位信号线图形耦接，所述第四晶体管的第一极与所述初始化信号线图形耦接，所述第四晶体管的第二极与所述第三晶体管的栅极耦接；
所述第五晶体管的栅极与所述复位信号线图形耦接，所述第五晶体管的第一极与所述初始化信号线图形耦接，所述第五晶体管的第二极与所述存储电容的第二极板耦接；
第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述初始化信号线图形耦接，所述第六晶体管的第二极与所述存储电容的第二极板耦接；
第七晶体管的栅极与所述发光控制信号线图形耦接，所述第七晶体管的第一极与所述第三晶体管的第二极耦接，所述第七晶体管的第二极与对应的阳极图形耦接；
所述第八晶体管的栅极与所述复位信号线图形耦接，所述第八晶体管的第一极与所述初始化信号线图形耦接，所述第八晶体管的第二极与对应的阳极图形耦接；
所述第九晶体管的栅极与对应的所述发光控制信号线图形耦接，所述第九晶体管的第一极与所述第三晶体管的栅极耦接，所述第九晶体管的第二极浮接。
基于上述显示面板的技术方案，本公开的第二方面提供一种显示装置，其中，包括上述显示面板。
基于上述显示面板的技术方案，本公开的第三方面提供一种显示面板的制作方法，所述显示面板包括呈阵列分布的多个子像素区，沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区；所述制作方法包括：
在基底上制作初始化信号线层、转接层、阳极层和第一辅助信号线层；
所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形；
所述转接层包括设置于各所述子像素区中的转接图形，所述转接图形的至少部分沿所述第一方向延伸，所述转接图形与其所在子像素区中的初始化信号线图形耦接；位于同一子像素区组中的各所述转接图形沿所述第一方向依次耦接，形成转接部；
所述阳极层包括与所述多个子像素区一一对应的多个阳极图形，所述多个阳极图形间隔设置，在相邻的所述阳极图形之间形成阳极间隔区；
所述第一辅助信号线层为网格状结构，所述第一辅助信号线层的至少部分位于所述阳极间隔区，且与所述阳极图形绝缘，各所述子像素区组中的转 接部分别与所述第一辅助信号线层耦接。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的子像素驱动电路的电路图；
图2为本公开实施例提供的子像素驱动电路的工作时序图；
图3为本公开实施例提供的子像素驱动电路的布局示意图；
图4为图3中沿B1B2方向的截面示意图；
图5为本公开实施例提供的第一辅助信号线层的第一布局示意图；
图6为本公开实施例提供的第一辅助信号线层的第二布局示意图；
图7为图3中有源膜层布局示意图；
图8为图3中第一栅金属层布局示意图；
图9为图3中第二栅金属层布局示意图；
图10为图3中第一源漏金属层布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示面板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
请参阅图3～图6所示，本公开实施例提供了一种显示面板，包括：基底，以及沿远离所述基底的方向依次层叠设置在所述基底上的初始化信号线层、转接层和阳极层；还包括呈阵列分布的多个子像素区，沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区；
如图3和图7所示，所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形904；
如图3和图9所示，所述转接层包括设置于各所述子像素区中的转接图形8061，所述转接图形8061的至少部分沿所述第一方向延伸，所述转接图形8061与其所在子像素区中的初始化信号线图形904耦接；位于同一子像素区组中的各所述转接图形8061沿所述第一方向依次耦接，形成转接部806；
如图6所示，所述阳极层包括与所述多个子像素区一一对应的多个阳极图形906，所述多个阳极图形906间隔设置，在相邻的所述阳极图形906之间形成阳极间隔区9061；
所述显示面板还包括：第一辅助信号线层801，所述第一辅助信号线层801为网格状结构，所述第一辅助信号线层801的至少部分位于所述阳极间隔区9061，且与所述阳极图形906绝缘，各所述子像素区组中的转接部806分别与所述第一辅助信号线层801耦接。
具体地，阵列排布的多个子像素区能够划分为沿第二方向依次排列的多行子像素区，和沿第一方向依次排列的多列子像素区。每行子像素区均包括沿第一方向间隔设置的多个子像素区，每列子像素区均包括沿所述第二方向间隔设置的多个子像素区。所述第一方向与所述第二方向相交，示例性的，所述第一方向包括X方向，所述第二方向包括Y方向。
所述多个子像素区中，沿第一方向位于同一行的子像素区能够划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区；值得注意，每个子像素区可以仅属于一个子像素区组。
所述初始化信号线层包括多个初始化信号线图形904，所述多个初始化信号线图形904与所述多个子像素区一一对应，所述初始化信号线图形904位于对应的子像素区中，用于为该子像素区对应的子像素驱动电路提供初始化信号。
所述转接层包括与所述多个子像素区一一对应的多个转接图形8061，所述转接图形8061位于对应的子像素区中，在同一个子像素区中，所述转接图形8061能够通过多种方式与所述初始化信号线图形904耦接；示例性的，所述转接图形8061位于所述初始化信号线图形904背向所述基底的一侧，可以通过在所述转接图形8061与所述初始化信号线图形904之间形成一个过孔，使得所述转接图形8061与所述初始化信号线图形904通过该过孔直接耦接。
所述转接图形8061的具体结构多种多样，示例性的，所述转接图形8061的至少部分沿所述第一方向延伸，位于同一子像素区组中的各所述转接图形8061能够沿所述第一方向依次耦接，形成转接部806；示例性的，所述转接部806中包括的各所述转接图形8061形成为一体结构。所述转接图形8061可以采用所述显示面板中的第二栅金属层制作，但不仅限于此。
所述阳极层位于转接部806背向所述基底的一侧，所述阳极层包括多个阳极图形906，所述多个阳极图形906彼此间隔设置，在相邻的所述阳极图形906之间形成阳极间隔区9061。所述阳极图形906与所述显示面板中的子像素驱动电路一一对应，所述阳极图形906与对应的子像素驱动电路耦接，能够接收对应的子像素驱动电路提供的驱动信号。所述阳极层背向所述基底的一侧还设置有发光功能层和阴极层，所述发光功能层位于所述阳极层与所述阴极层之间，能够在所述阳极层和所述阴极层之间形成的电场的作用下，发出对应颜色的光。值得注意，所述发光功能层可具体包括层叠设置的空穴注入层、空穴传输层，有机发光材料层、电子传输层和电子注入层，但不仅限于此。如图6所示，图中示出了红色发光元件R、绿色发光元件G和蓝色发光元件B，不同颜色的发光元件对应不同颜色的有机发光材料层。
如图6所示，所述显示面板还包括第一辅助信号线层801，所述第一辅助信号线层801的至少部分布局在所述阳极间隔区9061，且与所述阳极图形906绝缘。所述阳极间隔区9061形成为网格状区域，使得布局在所述阳极间隔区9061的第一辅助信号线层801形成为网格状结构。示例性的，所述第一辅助信号线层801可以在显示面板中的全部阳极间隔区9061中布局。
值得注意，如图4所示，所述显示面板中还包括平坦层PLN，所述阳极层(包括阳极图形906)一般形成于所述平坦层PLN背向所述基底50的表面，将所述第一辅助信号线层801布局在阳极间隔区9061中，使得所述第一辅助信号线层801也布局在所述平坦层PLN背向所述基底50的表面，这种布局方式使得所述第一辅助信号线层801与所述阳极层同层设置，避免由于引入所述第一辅助信号线层801而增加显示面板的厚度。
将所述第一辅助信号线层801布局在所述阳极间隔区9061，使得所述第一辅助信号线层801位于所述转接部806背向所述基底50的一侧，示例性的， 可通过在所述第一辅助信号线层801与每一个所述转接部806之间均设置一个对应的过孔结构，使得所述第一辅助信号线层801能够通过对应的过孔结构分别与各所述转接部806实现耦接。
根据上述显示面板的具体结构可知，本公开实施例提供的显示面板中，将沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区，同时设置与所述子像素区组一一对应的转接部806，通过转接部806将其对应的子像素区组中各子像素区内的初始化信号线图形904耦接在一起，并将各所述子像素区组中的转接部806分别与所述第一辅助信号线层801耦接；这种设置方式使得所述第一辅助信号线层801将各子像素区中的初始化信号线图形904全部耦接在一起，实现了通过所述第一辅助信号线层801能够为各子像素区中的初始化信号线图形904提供初始化信号；因此，本公开实施例提供的显示面板中，将各子像素区中的初始化信号线图形904与布局在阳极间隔区9061的第一辅助信号线层801分别耦接，解决了由于显示面板的布局空间有限，使得位于同一行的初始化信号线图形904不容易连接在一起的问题。
而且，本公开实施例提供的显示面板中，可以将所述第一辅助信号线层801布局在显示区域中全部阳极间隔区9061，将各子像素区中的初始化信号线图形904与所述第一辅助信号线层801耦接，更好的保证了各子像素区中的初始化信号线图形904上传输的初始化信号的稳定性。另外，将所述第一辅助阴极层布局在阳极间隔区9061，可以使所述第一辅助信号线层801与所述阳极层同层设置，从而更有利于所述显示面板的薄型化。
此外，本公开实施例提供的显示面板中，通过划分所述子像素区组，以及引入所述转接部806将子像素区组中的各初始化图形与所述第一辅助信号线图形耦接，使得在每个转接部806与所述第一辅助信号线层801之间仅需要设置一个过孔结构即可实现所述转接部806与所述第一辅助信号线层801之间的耦接，进而实现该转接部806耦接的至少两个子像素区中的初始化信号线图形904与所述第一辅助信号线层801耦接，因此，本公开实施例提供的显示面板中，在实现将各所述初始化信号线图形904均与所述第一辅助信号线图形耦接的同时，有效减少了贯穿平坦层PLN的过孔结构的数量。
需要说明，上述实施例提供的初始化信号线图形904除了用于为对应的子像素驱动电路提供初始化信号(Vinit)，也可以用于为对应的子像素驱动电路提供基准信号(Vref)。
在一些实施例中，所述初始化信号线图形904与所述显示面板中晶体管结构中的有源层同层同材料设置。
具体地，上述将所述初始化信号线图形904与所述晶体管结构中的有源层同层同材料设置，不仅使得所述初始化信号线图形904与所述有源层能够在同一次构图工艺中形成，而且，由于所述显示面板中与所述初始化信号线图形904耦接的晶体管结构的第一极(或第二极)也是采用所述有源层制作，从而使得该第一极(或第二极)能够与其耦接的初始化信号线图形904形成为一体结构，从而进一步节省了所述晶体管结构与所述初始化信号线图形904占用的布局空间，从而更有利于提升所述显示面板的分辨率。
在一些实施例中，所述第一辅助信号线层801与所述阳极层同层同材料设置。
具体地，将所述第一辅助信号线层801与所述阳极层同层同材料设置，使得所述第一辅助信号线层801与所述阳极层能够在同一次构图工艺中形成，不需要增加额外的专门用于制作所述第一辅助阴极层的构图工艺，从而有效简化了制作流程，节约了生产成本。
值得注意，在将所述第一辅助信号线层801与所述阳极层同层同材料设置时，需要在所述第一辅助信号线层801与所述阳极层之间保留一定间距，以避免所述第一辅助信号线层801与所述阳极层发生短路，影响所述显示面板的良率。
如图3和图4所示，在一些实施例中，所述显示面板还包括：
导电连接部层，所述导电连接部层包括位于各所述子像素区中的第一导电连接部9091，在同一子像素区中，所述第一导电连接部9091在所述基底50上的正投影，与所述初始化信号线图形904在所述基底50上的正投影具有第一交叠区域，所述第一导电连接部9091通过设置在所述第一交叠区域的第一过孔与所述初始化信号线图形904耦接，所述第一导电连接部9091在所述基底50上的正投影，与所述转接图形8061在所述基底50上的正投影具有 第三交叠区域，所述第一导电连接部9091通过设置在所述第三交叠区域的第三过孔与所述转接图形8061耦接；
每个所述转接部806对应耦接的各所述第一导电连接部9091中，存在一个目标导电连接部9091’，所述目标导电连接部9091’在所述基底50上的正投影与所述第一辅助信号线层801在所述基底50上的正投影形成第二交叠区域，所述目标导电连接部9091’通过设置在所述第二交叠区域的第二过孔与所述第一辅助信号线层801耦接。
具体地，所述导电连接部层位于所述转接层与所述第一辅助信号线层801之间，所述导电连接部层可以采用所述显示面板中的第一源漏金属层制作。所述导电连接部层包括与所述多个像素区一一对应的多个第一导电连接部9091，所述第一导电连接部9091位于对应的子像素区中。
如图3和图4所示，所述导电连接部层中包括的第一导电连接部9091的具体结构可根据实际需要设置，但要满足在同一子像素区中，所述第一导电连接部9091(见图4中的目标导电连接部9091’)在所述基底50上的正投影，与所述初始化信号线图形904在所述基底50上的正投影具有第一交叠区域，所述第一导电连接部9091在所述基底50上的正投影，与所述转接图形8061在所述基底50上的正投影具有第三交叠区域；这样所述第一导电连接部9091通过设置在所述第一交叠区域的第一过孔61能够与所述初始化信号线图形904耦接，同时所述第一导电连接部9091通过设置在所述第三交叠区域的第三过孔63能够与所述转接图形8061(见图4中的转接部806)耦接，从而实现了所述初始化信号线图形904通过所述第一导电连接部9091与所述转接图形8061耦接。
每个所述转接部806中各转接图形8061对应耦接的所述第一导电连接部9091中，存在一个目标导电连接部9091’，该目标导电连接部9091’在所述基底50上的正投影能够与所述第一辅助信号线层801在所述基底50上的正投影形成第二交叠区域，该目标导电连接部9091’能够通过设置在所述第二交叠区域的第二过孔62与所述第一辅助信号线层801耦接。
需要说明，图4中还示出了第一栅极绝缘层GI1，第二栅极绝缘层GI2，层间绝缘层ILD和平坦层PLN。
上述实施例提供的显示面板中，第一导电连接部9091位于所述初始化信号线图形904背向所述基底50的一侧，在第一导电连接部9091与所述初始化信号线图形904之间包括第一栅极绝缘层GI1，第二栅极绝缘层GI2和层间绝缘层ILD；同时第一导电连接部9091位于所述转接图形8061背向所述基底50的一侧，在所述第一导电连接部9091与所述转接图形8061之间包括层间绝缘层ILD；这样在形成所述层间绝缘层ILD之后，就可以通过一次过孔刻蚀工艺(过孔mask)，形成贯穿一栅极绝缘层GI1，第二栅极绝缘层GI2和层间绝缘层ILD的第一过孔61，以及贯穿层间绝缘层ILD的第三过孔63，在形成所述第一导电连接部9091后，该第一导电连接部9091能够通过所述第一过孔61与所述初始化信号线图形904耦接，并能够通过所述第三过孔63与所述转接图形8061耦接，这种方式有效减少了过孔mask数量，简化了显示面板的制作工艺流程，节约了制作成本。
另外，上述实施例提供的显示面板中，通过设置所述目标导电连接部9091’与所述第一辅助信号线层801耦接，来实现所述转接图形8061与所述第一辅助信号线层801耦接，避免了在所述转接图形8061与所述第一辅助信号线层801之间制作过深的过孔，很好的提升了所述转接图形8061与所述第一辅助信号线层801之间耦接的信赖性，而且，这种设置方式使得所述转接图形8061与所述第一辅助信号线层801存在更多的布局方式，更好的降低了显示面板的布局难度和制作工艺难度。
更详细地说，以每个子像素区组包括两个子像素区为例，在显示面板中未设置转接部806时，每个子像素区中的初始化信号线图形904与所述导电连接部耦接，所述导电连接部要通过贯穿平坦层PLN的PLN孔(即第二过孔62)与第一辅助信号线层801耦接，这样每个子像素区中，均包括一个用于耦接第一辅助信号线层801的PLN孔。而上述实施例提供的显示面板中，在每个子像素区组中，设置两个子像素区通过对应的转接部806，以及贯穿平坦层PLN的一个PLN孔与第一辅助信号线层801耦接，将显示面板中需要设置的PLN孔的数量缩小了一半，从而更有利于增加所述阳极层和所述第一辅助信号线层801的布局空间。
更详细地说，参见图5和图6，图5的虚线框中示出了相邻的两个子像 素区中，设置了两个第二过孔62，图6中的各虚线框中示出了相邻的两个子像素区中，仅设置了一个第二过孔62。
如图3、图4和图7所示，在一些实施例中，每个所述初始化信号线图形904均包括第一子图形9041和第二子图形9042，沿第一方向位于同一行的相邻子像素区中，前一个子像素区中的第二子图形9042与后一个子像素区中的第一子图形9041形成为一体结构；在每个子像素区中，所述第二子图形9042在所述基底50上的正投影，与所述第一导电连接部9091在所述基底50上的正投影具有所述第一交叠区域，所述第一导电连接部9091通过设置在所述第一交叠区域的第一过孔61与所述第二子图形9042耦接。
具体地，所述初始化信号线图形的具体结构多种多样，示例性的，每个所述初始化信号线图形均包括第一子图形9041和第二子图形9042，在同一个子像素区中，所述第一子图形9041与所述第二子图形9042沿所述第一方向排列。当所述初始化信号线图形采用这种结构时，相邻的子像素区中，前一个子像素区中的所述第二子图形9042与后一个子像素区中的所述第一子图形9041相邻。
上述设置沿第一方向位于同一行的相邻子像素区中，前一个子像素区中的第二子图形9042与后一个子像素区中的第一子图形9041形成为一体结构，不仅利于提升所述初始化信号线图形上传输的初始化信号的稳定性，而且能够有效降低所述初始化信号线图形的制作难度。
值得注意，当设置所述初始化信号线图形包括所述第一子图形9041和所述第二子图形9042时，示例性的，可设置所述第一子图形9041和所述第二子图形9042分别与所述第一导电连接部耦接，这种连接方式能够更好的保证所述初始化信号线图形与所述第一辅助信号线层的连接性能，能够更有效的提升初始化信号线图形传输的初始化信号的稳定性；或者，如图4所示，在每个子像素区中，设置所述第二子图形9042与所述第一导电连接部9091耦接，即如图4所示，所述第一导电连接部9091与所述第二子图形9042通过位于所述第一交叠区域的第一过孔61耦接，所述第一导电连接部9091与所述第一辅助信号线层801通过位于所述第二交叠区域的第二过孔62耦接。
如图5和图9所示，在一些实施例中，所述显示面板还包括：
电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
位于所述初始化信号线层与所述电源信号线层之间的第三辅助信号线层，所述第三辅助信号线层包括位于各所述子像素区中的第三辅助信号线图形805，所述第三辅助信号线图形805的至少部分沿第一方向延伸；在同一子像素区中，所述第三辅助信号线图形805在所述基底上的正投影与所述电源信号线图形901在所述基底上的正投影形成第四交叠区域，所述第三辅助信号线图形805在所述第四交叠区域与所述电源信号线图形901耦接；沿所述第一方向位于同一行子像素区中各第三辅助信号线图形805依次耦接。
具体地，所述电源信号线层位于所述初始化信号线层与所述阳极层之间，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形901，所述电源信号线图形901与所述子像素区一一对应，所述电源信号线图形901位于对应的所述子像素区中。所述电源信号线图形901的至少部分沿第二方向延伸，每一列子像素区中设置的各所述电源信号线图形901沿所述第二方向依次耦接，且能够形成为一体结构。
所述第三辅助信号线图形805与所述子像素区一一对应，所述第三辅助信号线图形805位于对应的子像素区中，所述第三辅助信号线图形805的至少部分沿第一方向延伸，沿所述第一方向位于同一行子像素区中各第三辅助信号线图形805依次耦接，示例性的，沿所述第一方向位于同一行子像素区中各第三辅助信号线图形805形成为一体结构。
所述电源信号线图形901的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交，因此在同一子像素区中，所述第三辅助信号线图形805在所述基底上的正投影与所述电源信号线图形901在所述基底上的正投影形成第四交叠区域，所述第三辅助信号线图形805能够通过设置在所述第四交叠区域的第七过孔67与所述电源信号线图形901实现耦接。
上述实施例提供的显示面板中，通过设置沿第二方向位于同一列子像素区中的电源信号线图形901依次耦接，沿第一方向位于同一行子像素区中各第三辅助信号线图形805依次耦接，以及在同一子像素中所述第三辅助信号 线图形805与所述电源信号线图形901耦接，使得所述电源信号线层与所述第三辅助信号线层共同形成为网状交叉布线结构，这种设置方式有效提升了电源信号线层的稳定性，而电源信号线层上传输的电源信号用于提供给子像素驱动电路中的驱动晶体管的源极，而子像素驱动电路产生的发光电流I oled＝k[(Vgs-Vth)] 2，Vgs＝Vg-Vs，Vg为驱动晶体管的栅极电压，Vs为驱动晶体管的源极电压，Vth为驱动晶体管的阈值电压，因此，电源信号作为Vs，会对发光电流I oled的大小产生影响，因此，上述设置方式在提升电源信号线层的稳定性的同时，更好的保证了发光电流I oled的稳定性，有效避免了动态串扰现象的发生。
如图3和图9所示，在一些实施例中，所述显示面板还包括晶体管结构和存储电容Cst，所述存储电容Cst包括相对设置的第一极板Cst1和第二极板Cst2，所述第一极板Cst1位于所述基底与所述第二极板Cst2之间，所述第一极板Cst1与所述晶体管结构中的栅极同层同材料设置；所述第三辅助信号线层与所述第二极板Cst2同层同材料设置。
具体地，子像素驱动电路对应的各膜层的布局如下：沿远离基底的方向上依次层叠设置的有源膜层、第一栅极绝缘层、第一栅金属层、第二栅极绝缘层、第二栅金属层、层间绝缘层、第一源漏金属层和平坦层。
所述子像素驱动电路包括存储电容Cst和多个晶体管结构，所述有源膜层用于形成所述多个晶体管结构中的有源图形，所述第一栅金属层用于形成所述多个晶体管结构的栅极和所述存储电容Cst的第一极板Cst1，所述第二栅金属层用于形成所述存储电容Cst的第二极板Cst2。
上述将所述第一极板Cst1与所述晶体管结构中的栅极同层同材料设置，使得所述第一极板Cst1与所述晶体管结构中的栅极能够在同一次构图工艺中同时形成，从而更好的简化显示面板的制作流程，节约了生产成本。同样的，将所述第三辅助信号线层与所述第二极板Cst2同层同材料设置，能够实现将所述第三辅助信号线层和所述第二极板Cst2在同一次构图工艺中同时形成，从而更好的简化显示面板的制作流程，节约了生产成本。
需要说明，上述“同层”指的是采用同一成膜工艺制作用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图 形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
如图3和图9所示，在一些实施例中，所述显示面板还包括：
发光控制信号线层，所述发光控制信号线层包括位于各所述子像素区中的发光控制信号线图形903，所述发光控制信号线图形903的至少部分沿所述第一方向延伸；
复位信号线层，所述复位信号线层包括位于各所述子像素区中的复位信号线图形905，所述复位信号线图形905沿所述第一方向延伸；
在同一子像素区中，所述第三辅助信号线图形805在所述基底上的正投影，位于所述发光控制信号线图形903在所述基底上的正投影与所述复位信号线图形905在所述基底上的正投影之间，所述第三辅助信号线图形805形成为波浪形结构。
具体地，所述发光控制信号线层包括与所述子像素区一一对应的发光控制信号线图形903，所述发光控制信号线图形903位于对应的子像素区中，所述发光控制信号线图形903的至少部分沿所述第一方向延伸，位于同一行子像素区中的所述发光控制信号线图形903依次电连接，形成为一体结构。
所述复位信号线层包括与所述子像素区一一对应的复位信号线图形905，所述复位信号线图形905位于对应的子像素区中，所述复位信号线图形905沿第一方向延伸。
上述实施例提供的显示面板中，通过设置在同一子像素区中，所述第三辅助信号线图形805在所述基底上的正投影，位于所述发光控制信号线图形903在所述基底上的正投影与所述复位信号线图形905在所述基底上的正投影之间，并将所述第三辅助信号线图形805形成为波浪形结构；使得即使沿第一方向位于同一行子像素区中的各第三辅助信号线图形805依次耦接，所述第三辅助信号线图形805需要占用较大的横向布局空间，所述第三辅助信号线图形805也不会与发光控制信号线图形903有过多交叠，从而避免了增大该发光控制信号线图形903的RC(阻容)loading(负载)，以及增加显示面板中栅极驱动电路的功耗。
而且，在将所述第三辅助信号线图形805与所述存储电容Cst的第二极板Cst2均采用第二栅金属层制作时，上述设置方式，不需要通过减小存储电容Cst的第二极板Cst2的面积，来满足第三辅助信号线图形805对布局空间的需要，使得存储电容Cst的第二极板Cst2的面积足够大，从而更有利于子像素驱动电路中，驱动晶体管的栅极信号的保持，以及该驱动晶体管的尺寸和布局设计。
另外，上述将所述第三辅助信号线图形805形成为波浪形结构，更具体地说，例如：类似W形结构，使得所述第三辅助信号线图形805能够很好的利用所述发光控制信号线图形903与所述复位信号线图形905之间的布局空间，在解决了动态串扰的问题的同时，更有利于所述显示面板向高分辨率方向发展。
如图3、图8和图10所示，在一些实施例中，所述显示面板还包括：
栅线层，所述栅线层包括位于各所述子像素区中的栅线图形902，所述栅线图形902的至少部分沿第一方向延伸；
数据线层，所述数据线层包括位于各所述子像素区中的数据线图形908，所述数据线图形908的至少部分沿第二方向延伸，所述第一方向与所述第二方向相交，所述数据线图形908在所述基底上的正投影与所述栅线图形902在所述基底上的正投影交叠；
所述导电连接部层包括位于各所述子像素区中的第三导电连接部9093和第四导电连接部9094；
与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括：驱动晶体管(即第三晶体管T3)、存储电容Cst、第一晶体管T1和第二晶体管T2；所述驱动晶体管的栅极复用为所述存储电容Cst的第一极板Cst1，所述驱动晶体管的栅极通过对应的子像素区中的第四导电连接部9094与所述第二晶体管T2的第二极D2耦接，所述存储电容Cst的第二极板Cst2通过对应的子像素区中的第三导电连接部9093与所述第一晶体管T1的第二极D1耦接；所述第一晶体管T1的栅极201g和所述第二晶体管T2的栅极202g分别与对应的子像素区中的栅线图形902耦接；所述栅线图形902在所述基底上的正投影与所述第三导电连接部9093在所述基底上的正投影不交叠，和 /或所述栅线图形902在所述基底上的正投影与所述第四导电连接部9094在所述基底上的正投影不交叠。
具体地，所述栅线层包括多个栅线图形902，所述栅线图形902与所述多个子像素区一一对应，所述栅线图形902位于对应的子像素区中，用于为该子像素区对应的子像素驱动电路提供扫描信号。每个所述栅线图形902的至少部分沿所述第一方向延伸，沿所述第一方向位于同一行的子像素区中的各栅线图形902依次电连接，形成为一体结构。
所述数据线层包括多个数据线图形908，所述数据线图形908与所述多个子像素区一一对应，所述数据线图形908位于对应的子像素区中，用于为该子像素区对应的子像素驱动电路提供数据信号。每个所述数据线图形908的至少部分沿所述第二方向延伸，沿所述第二方向位于同一列的子像素区中的各数据线图形908依次电连接，形成为一体结构。
所述导电连接部层可以采用所述显示面板中的第一源漏金属层制作，所述导电连接部层中包括的第三导电连接部9093和第四导电连接部9094的具体结构可根据实际需要设置，示例性的，所述第三导电连接部9093的至少部分沿所述第二方向延伸，所述第四导电连接部9094的至少部分沿所述第二方向延伸。
所述子像素驱动电路与所述子像素区一一对应，每个所述子像素驱动电路均包括驱动晶体管、存储电容Cst、第一晶体管T1和第二晶体管T2；所述驱动晶体管能够产生用于驱动发光元件发光的驱动信号，所述驱动晶体管的栅极与所述存储电容Cst的第一极板Cst1耦接，示例性的，所述驱动晶体管的栅极能够复用为所述存储电容Cst的第一极板Cst1。
所述驱动晶体管的栅极还能够通过对应的子像素区中的第四导电连接部9094与所述第二晶体管T2的第二极D2耦接，所述第二晶体管T2的第一极S2与所述驱动晶体管的第二极耦接，所述第二晶体管T2的栅极202g与对应的子像素区中的栅线图形902耦接。所述存储电容Cst的第二极板Cst2通过对应的子像素区中的第三导电连接部9093与所述第一晶体管T1的第二极D1耦接，所述第一晶体管T1的第一极S1与对应的子像素区中的数据线图形908耦接，所述第一晶体管T1的栅极201g与对应的子像素区中的栅线图形902 耦接。
由于所述驱动晶体管的栅极能够通过第四导电连接部9094与第二晶体管T2的第二级D2耦接，并能够通过存储电容Cst，以及第三导电连接部9093与第一晶体管T1的第二极D1耦接，因此，所述第三导电连接部9093和所述第四导电连接部9094上的信号均能够对所述驱动晶体管的栅极信号产生影响。
上述设置所述数据线图形908在所述基底上的正投影与所述栅线图形902在所述基底上的正投影交叠，以及所述栅线图形902在所述基底上的正投影与所述第三导电连接部9093在所述基底上的正投影不交叠，和/或所述栅线图形902在所述基底上的正投影与所述第四导电连接部9094在所述基底上的正投影不交叠；使得在同一子像素区中，在垂直于所述基底的方向上，所述栅线图形902仅能够与所述数据线图形908交叠，而不会与所述第三导电连接部9093和/或第四导电连接部9094交叠，从而避免了所述数据线图形908通过栅线图形902与所述第三导电连接部9093和/或所述第四导电连接部9094形成串联的寄生电，有效改善了由于数据线图形908上传输的数据信号跳变导致的驱动晶体管的栅极电压变化的串扰问题。
因此，上述实施例提供的显示面板中，当显示面板处于发光状态时，即使数据线图形908上传输的数据信号的电压发生跳变，与也不会通过寄生电容带动驱动晶体管的栅极电压产生变化，从而很好的保证了驱动晶体管的栅极电压的稳定性，避免了静态串扰现象，有效提升了显示面板的显示质量。
在一些实施例中，所述导电连接部层还包括位于各所述子像素区中的第二导电连接部9092，所述第二导电连接部9092与其所在子像素区对应的阳极图形906在所述基底上的正投影交叠，所述第二导电连接部9092在该交叠处与该阳极图形906耦接；
每个所述子像素驱动电路还包括第五晶体管T5、第八晶体管T8和第九晶体管T9；
所述第五晶体管T5的栅极205g与对应的复位信号线图形905耦接，所述第五晶体管T5的第一极S5与对应的所述初始化信号线图形904耦接，所述第五晶体管T5的第二极D5与所述第三导电连接部9093通过第四过孔64 耦接；
所述第八晶体管T8的栅极208g与对应的复位信号线图形905耦接，所述第八晶体管T8的第一极S8与对应的所述初始化信号线图形904耦接，所述第八晶体管T8的第二极D8与所述第二导电连接部9092通过第五过孔65耦接；
所述第九晶体管T9的栅极209g与对应的发光控制信号线图形903耦接，所述第九晶体管T9的第一极S9与所述第四导电连接部9094通过第六过孔66耦接，所述第九晶体管T9的第二极D9浮接；
所述第三辅助信号线图形805包括依次耦接的第一辅助部分、第二辅助部分和第三辅助部分；在一个子像素区中，所述第一辅助部分在所述基底上的正投影，位于所述第五过孔65在所述基底上的正投影与所述第六过孔66在所述基底上的正投影之间，所述第二辅助部分在所述基底上的正投影，位于所述第五过孔65在所述基底上的正投影与所述第四过孔64在所述基底上的正投影之间；所述第三辅助部分在所述基底上的正投影，位于所述第六过孔66在所述基底上的正投影与所述第四过孔64在所述基底上的正投影之间。
具体地，所述导电连接部层包括多个第二导电连接部9092，所述第二导电连接部9092一一对应位于所述多个子像素区中，所述第二导电连接部9092与其所在子像素区对应的阳极图形906在所述基底上的正投影交叠，所述第二导电连接部9092在该交叠处与该阳极图形906耦接。
所述第八晶体管T8能够在其对应耦接的复位信号线图形905传输的复位信号的控制下，实现导通或断开，用于对其通过第二导电连接部9092耦接的阳极图形906进行复位。
所述第五晶体管T5能够在其对应耦接的复位信号线图形905传输的复位信号的控制下，实现导通或断开，用于对其耦接的存储电容Cst的第二极板Cst2进行复位。
示例性的，所述第五过孔65与所述第四过孔64沿第一方向排列，所述第六过孔66相对于所述第四过孔64更靠近所述发光控制信号线图形903，所述第四过孔64在所述基底上的正投影，所述第五过孔65在所述基底上的正投影，以及所述第六过孔66在所述基底上的正投影之间的连线，能够形成 类似三角形的结构。
需要说明，所述第四过64孔、所述第五过孔65和所述第六过孔66均为贯穿层间绝缘层(ILD层)的过孔。
上述设置所述第三辅助信号线图形805包括依次耦接的所述第一辅助部分、所述第二辅助部分和所述第三辅助部分，使得所述第三辅助信号线图形805能够合理利用所述第四过孔64、所述第五过孔65和所述第六过孔66之间的空间，使得所述第三辅助信号线图形805形成为类似W形结构，使得所述第三辅助信号线图形805能够很好的利用所述发光控制信号线图形903与所述复位信号线图形905之间的布局空间，在解决了动态串扰的问题的同时，更有利于所述显示面板向高分辨率方向发展。值得注意，上述布局方式能够支持像素分辨率在480PPI的显示面板。
如图3和图9所示，在一些实施例中，所述显示面板还包括：
数据线层，所述数据线层包括位于各所述子像素区中的数据线图形908，所述数据线图形908的至少部分沿第二方向延伸；
沿所述第一方向位于同一行子像素区中相邻的第三辅助信号线图形805在耦接处形成屏蔽部8051，所述屏蔽部8051沿所述第二方向延伸，所述屏蔽部8051在所述基底上的正投影与所述数据线图形908在所述基底上的正投影交叠，沿垂直于所述第二方向的方向上，所述屏蔽部8051的宽度大于所述数据线图形908的宽度。
具体地，所述屏蔽部8051可形成为沿所述第二方向延伸的，类似矩形的结构，通过设置所述屏蔽部8051在所述基底上的正投影与所述数据线图形908在所述基底上的正投影交叠，使得所述屏蔽部8051能够对所述数据线图形908起到屏蔽的作用，从而改善所述数据线图形908上传输的数据信号跳变导致的静态串扰现象。
另外，设置沿垂直于所述第二方向的方向上，所述屏蔽部8051的宽度大于所述数据线图形908的宽度，使得所述屏蔽部8051与所述数据线图形908的交叠面积更大，更有利于改善所述数据线图形908上传输的数据信号跳变导致的静态串扰现象。
值得注意，所述屏蔽部8051与所述相邻的第三辅助信号线图形805可形 成为一体结构，但不仅限于此。
如图3图10所示，在一些实施例中，所述显示面板还包括：
与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管；
数据线层，所述数据线层包括位于各所述子像素区中的数据线图形908，所述数据线图形908的至少部分沿第二方向延伸，所述第一方向与所述第二方向相交；
电源信号线层，所述电源信号线层包括位于各所述子像素区中的电源信号线图形901，所述电源信号线图形901的至少部分沿所述第二方向延伸；
在同一所述子像素区中，所述电源信号线图形901在所述基底上的正投影，位于所述驱动晶体管的栅极(即第三晶体管T3的栅极203g)在所述基底上的正投影与所述数据线图形908在所述基底上的正投影之间。
具体地，所述电源信号线图形901的至少部分沿所述第二方向延伸，所述数据线图形908的至少部分沿所述第二方向延伸，通过设置在同一所述子像素区中，所述电源信号线图形901在所述基底上的正投影，位于所述驱动晶体管的栅极在所述基底上的正投影与所述数据线图形908在所述基底上的正投影之间，不仅使得所述数据线图形908与所述驱动晶体管的栅极之间的距离更远，还使得所述电源信号线图形901在所述数据线图形908和所述驱动晶体管的栅极之间能够形成很好的阻隔，从而减小了在同一子像素区中，所述数据线图形908与所述驱动晶体管的栅极之间形成的侧向寄生电容，有效提升了驱动晶体管的栅极电位的稳定性。
如图3和图10所示，在一些实施例中，所述电源信号线图形901包括相耦接的第一电源部9011和第二电源部9012，所述第一电源部9011沿所述第二方向延伸，所述第二电源部9012向远离其所在子像素区中的数据线图形908的方向突出于所述第一电源部9011；在垂直于所述第二方向、且平行于所述基底的方向上，所述第一电源部9011的宽度L1大于所述第二电源部9012的宽度L2；
所述驱动晶体管的第一极(即第三晶体管T3的第一极S3)在所述基底上的正投影，与对应的子像素区中的所述第一电源部9011在所述基底上的正 投影交叠，所述驱动晶体管的第一极与所述第一电源部9011在该交叠处耦接。
具体地，所述电源信号线图形901的具体结构多种多样，示例性的，所述电源信号线图形901包括相耦接的第一电源部9011和第二电源部9012，所述第一电源部9011沿所述第二方向延伸，所述第一电源部9011与其所在子像素区中的数据线图形908之间形成第一间隔区；所述第二电源部9012向远离其所在子像素区中的数据线图形908的方向突出于所述第一电源部9011，在所述第二电源部9012与该数据线图形908之间形成第二间隔区，沿垂直于所述第二方向的方向上，所述第二间隔区的最大宽度L3大于所述第一间隔区L4的最大宽度。
通过设置所述驱动晶体管的第一极(即第三晶体管T3的第一极S3)在所述基底上的正投影，与对应的子像素区中的所述第一电源部9011在所述基底上的正投影交叠，使得所述驱动晶体管的第一极与所述第一电源部9011能够通过设置在该交叠处的连接孔69实现耦接。
上述设置在垂直于所述第二方向、且平行于所述基底的方向上，所述第一电源部9011的宽度大于所述第二电源部9012的宽度，以及所述驱动晶体管的第一极在所述基底上的正投影，与对应的子像素区中的所述第一电源部9011在所述基底上的正投影交叠，所述驱动晶体管的第一极与所述第一电源部9011在该交叠处耦接，使得所述驱动晶体管的第一极在所述基底上的正投影，与对应的子像素区中的所述第一电源部9011在所述基底上的正投影之间能够形成更大的交叠面积，这样就能够在交叠处形成较大孔径的连接孔69，从而更有利于在交叠处，所述驱动晶体管的第一极与所述电源信号线图形901的耦接性能。
如图3、图9和图10所示，在一些实施例中，所述显示面板还包括：
第一屏蔽层，所述第一屏蔽层包括位于各所述子像素区中的第一屏蔽图形804，所述第一屏蔽图形804在所述基底上的正投影与所述第一电源部9011在所述基底上的正投影交叠，在该交叠处所述第一屏蔽图形804与所述第一电源部9011耦接；所述第一屏蔽图形804的至少部分沿所述第二方向延伸，所述第一屏蔽图形804在所述基底上的正投影与所述数据线图形908在所述 基底上的正投影交叠。
具体地，所述第一屏蔽层包括多个第一屏蔽图形804，所述第一屏蔽图形804与所述子像素区一一对应，所述第一屏蔽图形804位于对应的子像素区中。示例性的，所述第一屏蔽图形804的至少部分沿所述第二方向延伸，所述数据线图形908的至少部分沿所述第二方向延伸，在同一子像素区中，所述第一屏蔽图形804在所述基底上的正投影与所述数据线图形908在所述基底上的正投影交叠；这种设置方式使得所述第一屏蔽图形804能够与所述数据线图形908形成较大的交叠面积，使得所述第一屏蔽图形804对所述数据线图形908的屏蔽效果更加显著。
如图8所示，示例性的，所述第一屏蔽层采用显示面板中的第二栅金属层制作，即所述第一屏蔽层能够与所述存储电容Cst的第二极板Cst2在同一次构图工艺中形成。
所述第一屏蔽层上传输具有固定电位的信号，示例性的，所述第一屏蔽图形804与所述显示面板中的电源信号线图形901耦接，具有与电源信号线上传输的电源信号相同的稳定电位。示例性的，可设置所述第一屏蔽图形804在所述基底上的正投影与所述第一电源部在所述基底上的正投影交叠，在该交叠处所述第一屏蔽图形804与所述第一电源部耦接；由于所述第一电源部在垂直于所述第二方向的方向上具有更大的宽度，这种设置方式有利于所述第一屏蔽图形804与所述第一电源部之间形成更大的交叠面积，从而更有利于在交叠处形成具有更大孔径的连接孔，保证所述第一屏蔽图形804与所述第一电源部更好的耦接性能。
上述实施例提供的显示面板中，通过设置具有稳定电位的第一屏蔽层与数据线图形908交叠，很好的屏蔽了数据线图形908与相邻的驱动晶体管的栅极之间形成的寄生电容，从而有效改善了显示面板中数据信号变化对驱动晶体管的栅极产生的串扰现象。
如图3和图10所示，在一些实施例中，所述第一晶体管T1的第一极S1沿所述第一方向延伸，所述第一晶体管T1的第一极S1在所述基底上的正投影与对应的子像素区中的数据线图形908在所述基底上的正投影交叠，所述第一晶体管T1的第一极S1与对应的子像素区中的数据线图形908在该交叠 处通过第一连接孔68耦接；所述第一连接孔68在所述基底上的正投影与所述第二电源部9092在所述基底上的正投影沿与所述第二方向垂直的方向排列。
具体地，所述第一晶体管T1的第一极S1的具体结构多种多样，示例性的，所述第一晶体管T1的第一极S1沿所述第一方向延伸。
上述通过设置所述第一连接孔68在所述基底上的正投影与所述第二电源部9012在所述基底上的正投影沿与所述第二方向垂直的方向排列，使得所述第一连接孔68能够形成在所述第二间隔区附近，而由于在所述第二间隔区所述第二电源部9012与所述数据线图形908之间距离较远，更有利于增加所述第一连接孔68的孔径，从而有效提升所述第一晶体管T1的第一极S1与所述数据线图形908之间的耦接性能。
如图3和图8所示，在一些实施例中，所述显示面板还包括：
栅线层，所述栅线层包括位于各所述子像素区中的栅线图形902，所述栅线图形902的至少部分沿第一方向延伸；
复位信号线层，所述复位信号线层包括位于各所述子像素区中的复位信号线图形905，当前子像素区中的栅线图形902与沿第二方向相邻的下一个子像素区中的复位信号线图形905形成为一体结构。
具体地，每个所述栅线图形902的至少部分沿所述第一方向延伸，沿所述第一方向位于同一行的子像素区中的各栅线图形902依次电连接，形成为一体结构；每个所述复位信号线图形905均沿所述第一方向延伸，当前子像素区中的栅线图形902与沿第二方向相邻的下一个子像素区中的复位信号线图形905，可以通过沿所述第二方向延伸的连接部形成为一体结构。
所述栅线图形902、所述复位信号线图形905和所述显示面板中包括的发光控制信号线图形903均可以采用第一栅金属层制作，使得所述栅线图形902、所述复位信号线图形905和所述发光控制信号线图形903能够在同一次构图工艺中形成，从而有效简化了制作流程，节约了生产成本。
上述设置当前子像素区中的栅线图形902与沿第二方向相邻的下一个子像素区中的复位信号线图形905形成为一体结构，使得上一行子像素区中栅线图形902传输的扫描信号能够作为相邻下一行子像素中复位信号线图形 905上传输的复位信号，从而避免为所述复位信号线图形905提供复位信号而引入专门的信号传输路径，有效减小了所述复位信号线图形905占用的布局空间，从而更有利于提升所述显示面板的分辨率。上述布局方式能够支持像素分辨率在400PPI的显示面板。
如图3所示，在一些实施例中，所述显示面板还包括：位于各所述子像素区中的电源信号线图形、数据线图形、复位信号线图形和发光控制信号线图形和栅线图形；还包括与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和存储电容；
所述第一晶体管的栅极与所述栅线图形耦接，所述第一晶体管的第一极与所述数据线图形耦接，所述第一晶体管的第二极与所述存储电容的第二极板耦接，所述存储电容的第一极板与所述第三晶体管的栅极耦接；
所述第二晶体管的栅极与所述栅线图形耦接，所述第二晶体管的第一极与所述第三晶体管的第二极耦接，所述第二晶体管的第二极与所述第三晶体管的栅极耦接；
所述第三晶体管的第一极与所述电源信号线图形耦接；
所述第四晶体管的栅极与所述复位信号线图形耦接，所述第四晶体管的第一极与所述初始化信号线图形耦接，所述第四晶体管的第二极与所述第三晶体管的栅极耦接；
所述第五晶体管的栅极与所述复位信号线图形耦接，所述第五晶体管的第一极与所述初始化信号线图形耦接，所述第五晶体管的第二极与所述存储电容的第二极板耦接；
第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述初始化信号线图形耦接，所述第六晶体管的第二极与所述存储电容的第二极板耦接；
第七晶体管的栅极与所述发光控制信号线图形耦接，所述第七晶体管的第一极与所述第三晶体管的第二极耦接，所述第七晶体管的第二极与对应的阳极图形耦接；
所述第八晶体管的栅极与所述复位信号线图形耦接，所述第八晶体管的第一极与所述初始化信号线图形耦接，所述第八晶体管的第二极与对应的阳极图形耦接；
所述第九晶体管的栅极与对应的所述发光控制信号线图形耦接，所述第九晶体管的第一极与所述第三晶体管的栅极耦接，所述第九晶体管的第二极浮接。
具体地，如图1和图3所示，所述第一晶体管T1的栅极201g与所述栅线图形902耦接，所述第一晶体管T1的第一极S1与所述数据线图形908耦接，所述第一晶体管T1的第二极D1与所述存储电容Cst的第二极板Cst2耦接，所述存储电容Cst的第一极板Cst1与所述第三晶体管T3(即所述驱动晶体管)的栅极203g耦接；
所述第二晶体管T2的栅极202g与所述栅线图形902耦接，所述第二晶体管T2的第一极S2与所述第三晶体管T3的第二极D3耦接，所述第二晶体管T2的第二极D2与所述第三晶体管T3的栅极203g耦接；
所述第三晶体管T3的第一极S3与所述电源信号线图形901耦接；
所述第四晶体管T4的栅极204g与所述复位信号线图形905耦接，所述第四晶体管T4的第一极S4与所述初始化信号线图形904耦接，所述第四晶体管T4的第二极D4与所述第三晶体管T3的栅极203g耦接；
所述第五晶体管T5的栅极205g与所述复位信号线图形905耦接，所述第五晶体管T5的第一极S5与所述初始化信号线图形904耦接，所述第五晶体管T5的第二极D5与所述存储电容Cst的第二极板Cst2耦接；
第六晶体管T6的栅极206g与所述发光控制信号线图形903耦接，所述第六晶体管T6的第一极S6与所述初始化信号线图形904耦接，所述第六晶体管T6的第二极D6与所述存储电容Cst的第二极板Cst2耦接；
第七晶体管T7的栅极207g与所述发光控制信号线图形903耦接，所述第七晶体管T7的第一极S7与所述第三晶体管T3的第二极D3耦接，所述第七晶体管T7的第二极D7与对应的发光元件EL的阳极图形906耦接，发光元件EL的阴极与负电源信号线VSS耦接；
所述第八晶体管T8的栅极208g与所述复位信号线图形905耦接，所述 第八晶体管T8的第一极S8与所述初始化信号线图形904耦接，所述第八晶体管T8的第二极D8与对应的发光元件EL的阳极图形906耦接。
所述电源信号线图形901的至少部分和所述数据线图形908沿第二方向延伸；所述栅线图形902的至少部分、所述发光控制信号线图形903、所述复位信号线图形905均沿第一方向延伸，所述第一方向与所述第二方向相交。示例性的，所述第一方向包括X方向，所述第二方向包括Y方向。
所述多个子像素区能够划分为沿所述第二方向依次排列的多行子像素区，以及沿所述第一方向依次排列的多列子像素区，位于同一行子像素区中的各所述栅线图形902依次电连接，形成为一体结构；位于同一行子像素区中的所述发光控制信号线图形903依次电连接，形成为一体结构；位于同一列子像素区中的所述数据线图形908依次电连接，形成为一体结构；位于同一列子像素区中的所述电源信号线图形901依次电连接，形成为一体结构。
所述显示面板中各膜层布局如下：沿远离基底的方向依次层叠设置在所述基底上的缓冲层，子像素驱动电路膜层，阳极层，像素界定层和隔垫物层70。所述子像素驱动电路对应的各膜层的布局如下：沿远离基底的方向上依次层叠设置的有源膜层、第一栅极绝缘层、第一栅金属层、第二栅极绝缘层、第二栅金属层、层间绝缘层、第一源漏金属层和平坦层。
如图7所示，所述有源膜层用于形成子像素驱动电路中各晶体管的沟道区(如：101g～109g)，第一极(如：S1～S9)和第二极(如：D1～D9)，第一极和第二极对应的有源膜层由于掺杂作用，导电性能会优于沟道区对应的有源膜层；有源膜层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述第一极和第二极可为掺杂有n型杂质或p型杂质。另外，值得注意，所述第一极和第二极对应的有源膜层可直接作为对应晶体管的源极或漏极，或者，也可以采用金属材料制作与所述第一极接触的源极，采用金属材料制作与所述第二极接触的漏极。
所述有源膜层还用于形成初始化信号线图形904，所述有源膜层用于形成初始化信号线图形904的部分由于掺杂作用，能够具有良好的导电性能。
第一栅金属层用于形成子像素驱动电路中各晶体管的栅极(如：201g～209g)，以及显示面板包括的栅线图形902、发光控制信号线图形903、 复位信号线图形905等结构，每个子像素驱动电路中的第三晶体管T3的栅极203g均复用为该子像素驱动电路中的存储电容Cst的第一极板Cst1。
第二栅金属层用于形成存储电容Cst的第二极板Cst2，以及显示面板包括的第一屏蔽图形804和第三辅助信号线层。
所述第一源漏金属层用于形成数据线图形908、电源信号线图形901和一些导电连接部。
如图1和图2所示，上述结构的子像素驱动电路在工作时，每个工作周期均包括复位时段P1、写入补偿时段P2和发光时段P3。图3中，E1代表当前子像素区中的发光控制信号线图形903上传输的发光控制信号，R1代表当前子像素区中的复位信号线图形905上传输的复位信号，G1代表当前子像素区中的栅线图形902上传输的栅极扫描信号。
在所述复位时段P1，所述复位信号线图形905输入的复位信号处于有效电平，第四晶体管T4、第五晶体管T5和第八晶体管T8导通，将由所述初始化信号线图形904传输的初始化信号输入至第三晶体管T3的栅极203g，阳极图形906和存储电容的第二极板，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位，同时对阳极图形906和存储电容的第二极板进行复位。
在写入补偿时段P2，所述复位信号线图形905输入的复位信号处于非有效电平，第四晶体管T4、第五晶体管T5和第八晶体管T8均截止，栅线图形902输入的扫描信号处于有效电平，控制第一晶体管T1和第二晶体管T2导通，数据线图形908写入数据信号，并经所述第一晶体管T1传输至N1节点，经存储电容耦合至第三晶体管T3的栅极203g，同时，第一晶体管T1和第二晶体管T2导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和第二晶体管T2配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vth+VDD，VDD为电源信号电压值，Vth代表第三晶体管T3的阈值电压。
在发光时段P3，发光控制信号线图形903写入的发光控制信号处于有效电平，控制第六晶体管T6和第七晶体管T7导通，由电源信号线图形901传 输的电源信号输入至第三晶体管T3的源极，同时由于存储电容的耦合作用，第三晶体管T3的栅极203g变为Vint-Vdata+Vth+VDD，Vdata代表数据信号电压值，Vint代表初始信号电压值，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata-Vint+Vth，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极图形906，驱动对应的发光元件EL发光。
在一些实施例中，所述子像素驱动电路还包括第九晶体管T9，所述第九晶体管T9的栅极209g与所述发光控制信号线图形903耦接，所述第九晶体管T9的第一极S9与所述第三晶体管T3的栅极203g耦接，所述第九晶体管T9的第二极D9浮接。
具体地，在复位时段P1和在写入补偿时段P2，发光控制信号线图形903写入的发光控制信号处于非有效电平，控制所述第九晶体管T9处于截止状态。在发光时段P3，发光控制信号线图形903写入的发光控制信号处于有效电平，控制所述第九晶体管T9处于导通状态。
上述设置子像素驱动电路还包括所述第九晶体管T9，使得在发光时段，通过导通所述第九晶体管T9，能够将第三晶体管T3的栅极203g累计的多余电荷释放掉，以保证第三晶体管T3的栅极203g的电位稳定。
需要说明，由写入补偿时段P2进入发光时段P3时，栅线图形902输入的扫描信号的电位升高，从而对第三晶体管T3的栅极203g电位产生拉动，使得在第三晶体管T3的栅极203g聚集多余电荷。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示面板。
由于上述实施例提供的显示面板中，将沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区，同时设置与所述子像素区组一一对应的转接部806，通过转接部806将其对应的子像素区组中各子像素区内的初始化信号线图形904耦接在一起，并将各所述子像素区组中的转接部806分别与所述第一辅助信号线层801耦接；这种设置方式使得所述第一辅助信号线层801将各子像素区中的初始化信号线图形904全部耦接在一起，实现了通过所述第一辅助信号线层801能够为各子像素区中的初始化信号线图形904提供初始化信号；因此，上述实施例提供的显示面板中，将各子像素区中的初始化信号线图形904与 布局在阳极间隔区9061的第一辅助信号线层801分别耦接，解决了由于显示面板的布局空间有限，使得位于同一行的初始化信号线图形904不容易连接在一起的问题。
而且，上述实施例提供的显示面板中，可以将所述第一辅助信号线层801布局在显示区域中全部阳极间隔区9061，将各子像素区中的初始化信号线图形904与所述第一辅助信号线层801耦接，更好的保证了各子像素区中的初始化信号线图形904上传输的初始化信号的稳定性。另外，将所述第一辅助阴极层布局在阳极间隔区9061，可以使所述第一辅助信号线层801与所述阳极层同层设置，从而更有利于所述显示面板的薄型化。
此外，上述实施例提供的显示面板中，通过划分所述子像素区组，以及引入所述转接部806将子像素区组中的各初始化图形与所述第一辅助信号线图形耦接，使得在每个转接部806与所述第一辅助信号线层801之间仅需要设置一个过孔结构即可实现所述转接部806与所述第一辅助信号线层801之间的耦接，进而实现该转接部806耦接的至少两个子像素区中的初始化信号线图形904与所述第一辅助信号线层801耦接，因此，本公开实施例提供的显示面板中，在实现将各所述初始化信号线图形904均与所述第一辅助信号线图形耦接的同时，有效减少了贯穿平坦层PLN的过孔结构的数量。
因此，本公开实施例提供的显示装置在包括上述实施例提供的显示面板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示面板的制作方法，所述显示面板包括呈阵列分布的多个子像素区，沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区；所述制作方法包括：
在基底上制作初始化信号线层、转接层、阳极层和第一辅助信号线层；
所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形；
所述转接层包括设置于各所述子像素区中的转接图形，所述转接图形的 至少部分沿所述第一方向延伸，所述转接图形与其所在子像素区中的初始化信号线图形耦接；位于同一子像素区组中的各所述转接图形沿所述第一方向依次耦接，形成转接部；
所述阳极层包括与所述多个子像素区一一对应的多个阳极图形，所述多个阳极图形间隔设置，在相邻的所述阳极图形之间形成阳极间隔区；
所述第一辅助信号线层为网格状结构，所述第一辅助信号线层的至少部分位于所述阳极间隔区，且与所述阳极图形绝缘，各所述子像素区组中的转接部分别与所述第一辅助信号线层耦接。
采用本公开实施例提供的制作方法制作的显示面板中，将沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区，同时设置与所述子像素区组一一对应的转接部806，通过转接部806将其对应的子像素区组中各子像素区内的初始化信号线图形904耦接在一起，并将各所述子像素区组中的转接部806分别与所述第一辅助信号线层801耦接；这种设置方式使得所述第一辅助信号线层801将各子像素区中的初始化信号线图形904全部耦接在一起，实现了通过所述第一辅助信号线层801能够为各子像素区中的初始化信号线图形904提供初始化信号；因此，采用本公开实施例提供的制作方法制作的显示面板中，将各子像素区中的初始化信号线图形904与布局在阳极间隔区9061的第一辅助信号线层801分别耦接，解决了由于显示面板的布局空间有限，使得位于同一行的初始化信号线图形904不容易连接在一起的问题。
而且，采用本公开实施例提供的制作方法制作的显示面板中，可以将所述第一辅助信号线层801布局在显示区域中全部阳极间隔区9061，将各子像素区中的初始化信号线图形904与所述第一辅助信号线层801耦接，更好的保证了各子像素区中的初始化信号线图形904上传输的初始化信号的稳定性。另外，将所述第一辅助阴极层布局在阳极间隔区9061，可以使所述第一辅助信号线层801与所述阳极层同层设置，从而更有利于所述显示面板的薄型化。
此外，采用本公开实施例提供的制作方法制作的显示面板中，通过划分所述子像素区组，以及引入所述转接部806将子像素区组中的各初始化图形 与所述第一辅助信号线图形耦接，使得在每个转接部806与所述第一辅助信号线层801之间仅需要设置一个过孔结构即可实现所述转接部806与所述第一辅助信号线层801之间的耦接，进而实现该转接部806耦接的至少两个子像素区中的初始化信号线图形904与所述第一辅助信号线层801耦接，因此，本公开实施例提供的显示面板中，在实现将各所述初始化信号线图形904均与所述第一辅助信号线图形耦接的同时，有效减少了贯穿平坦层PLN的过孔结构的数量。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种显示面板，包括：基底，以及沿远离所述基底的方向依次层叠设置在所述基底上的初始化信号线层、转接层和阳极层；还包括呈阵列分布的多个子像素区，沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区；
    所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形；
    所述转接层包括设置于各所述子像素区中的转接图形，所述转接图形的至少部分沿所述第一方向延伸，所述转接图形与其所在子像素区中的初始化信号线图形耦接；位于同一子像素区组中的各所述转接图形沿所述第一方向依次耦接，形成转接部；
    所述阳极层包括与所述多个子像素区一一对应的多个阳极图形，所述多个阳极图形间隔设置，在相邻的所述阳极图形之间形成阳极间隔区；
    所述显示面板还包括：第一辅助信号线层，所述第一辅助信号线层为网格状结构，所述第一辅助信号线层的至少部分位于所述阳极间隔区，且与所述阳极图形绝缘，各所述子像素区组中的转接部分别与所述第一辅助信号线层耦接。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    导电连接部层，所述导电连接部层包括位于各所述子像素区中的第一导电连接部，在同一子像素区中，所述第一导电连接部在所述基底上的正投影，与
    所述初始化信号线图形在所述基底上的正投影具有第一交叠区域，所述第一导电连接部通过设置在所述第一交叠区域的第一过孔与所述初始化信号线图形耦接，所述第一导电连接部在所述基底上的正投影，与所述转接图形在所述基底上的正投影具有第三交叠区域，所述第一导电连接部通过设置在所述第三交叠区域的第三过孔与所述转接图形耦接；
    每个所述转接部对应耦接的各所述第一导电连接部中，存在一个目标导电连接部，所述目标导电连接部在所述基底上的正投影与所述第一辅助信号 线层在所述基底上的正投影形成第二交叠区域，所述目标导电连接部通过设置在所述第二交叠区域的第二过孔与所述第一辅助信号线层耦接。
  3. 根据权利要求2所述的显示面板，其中，每个所述初始化信号线图形均包括第一子图形和第二子图形，沿第一方向位于同一行的相邻子像素区中，前一个子像素区中的第二子图形与后一个子像素区中的第一子图形形成为一体结构；
    在每个子像素区中，所述第二子图形在所述基底上的正投影，与所述第一导电连接部在所述基底上的正投影具有所述第一交叠区域，所述第一导电连接部通过设置在所述第一交叠区域的第一过孔与所述第二子图形耦接。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
    位于所述初始化信号线层与所述电源信号线层之间的第三辅助信号线层，所述第三辅助信号线层包括位于各所述子像素区中的第三辅助信号线图形，所述第三辅助信号线图形的至少部分沿第一方向延伸；在同一子像素区中，所述第三辅助信号线图形在所述基底上的正投影与所述电源信号线图形在所述基底上的正投影形成第四交叠区域，所述第三辅助信号线图形在所述第四交叠区域与所述电源信号线图形耦接；沿所述第一方向位于同一行子像素区中各第三辅助信号线图形依次耦接。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    发光控制信号线层，所述发光控制信号线层包括位于各所述子像素区中的发光控制信号线图形，所述发光控制信号线图形的至少部分沿所述第一方向延伸；
    复位信号线层，所述复位信号线层包括位于各所述子像素区中的复位信号线图形，所述复位信号线图形沿所述第一方向延伸；
    在同一子像素区中，所述第三辅助信号线图形在所述基底上的正投影，位于所述发光控制信号线图形在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影之间，所述第三辅助信号线图形形成为波浪形结构。
  6. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    栅线层，所述栅线层包括位于各所述子像素区中的栅线图形，所述栅线图形的至少部分沿第一方向延伸；
    数据线层，所述数据线层包括位于各所述子像素区中的数据线图形，所述数据线图形的至少部分沿第二方向延伸，所述第一方向与所述第二方向相交，所述数据线图形在所述基底上的正投影与所述栅线图形在所述基底上的正投影交叠；
    导电连接部层，所述导电连接部层包括位于各所述子像素区中的第三导电连接部和第四导电连接部；
    与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管、存储电容、第一晶体管和第二晶体管；所述驱动晶体管的栅极复用为所述存储电容的第一极板，所述驱动晶体管的栅极通过对应的子像素区中的第四导电连接部与所述第二晶体管的第二极耦接，所述存储电容的第二极板通过对应的子像素区中的第三导电连接部与所述第一晶体管的第二极耦接；所述第一晶体管的栅极和所述第二晶体管的栅极分别与对应的子像素区中的栅线图形耦接；所述栅线图形在所述基底上的正投影与所述第三导电连接部在所述基底上的正投影不交叠，和/或所述栅线图形在所述基底上的正投影与所述第四导电连接部在所述基底上的正投影不交叠。
  7. 根据权利要求6所述的显示面板，其中，所述导电连接部层还包括位于各所述子像素区中的第二导电连接部，所述第二导电连接部与其所在子像素区对应的阳极图形在所述基底上的正投影交叠，所述第二导电连接部在该交叠处与该阳极图形耦接；
    每个所述子像素驱动电路还包括第五晶体管、第八晶体管和第九晶体管；
    所述第五晶体管的栅极与对应的复位信号线图形耦接，所述第五晶体管的第一极与对应的所述初始化信号线图形耦接，所述第五晶体管的第二极与所述第三导电连接部通过第四过孔耦接；
    所述第八晶体管的栅极与对应的复位信号线图形耦接，所述第八晶体管的第一极与对应的所述初始化信号线图形耦接，所述第八晶体管的第二极与所述第二导电连接部通过第五过孔耦接；
    所述第九晶体管的栅极与对应的发光控制信号线图形耦接，所述第九晶体管的第一极与所述第四导电连接部通过第六过孔耦接，所述第九晶体管的第二极浮接；
    所述第三辅助信号线图形包括依次耦接的第一辅助部分、第二辅助部分和第三辅助部分；在一个子像素区中，所述第一辅助部分在所述基底上的正投影，位于所述第五过孔在所述基底上的正投影与所述第六过孔在所述基底上的正投影之间，所述第二辅助部分在所述基底上的正投影，位于所述第五过孔在所述基底上的正投影与所述第四过孔在所述基底上的正投影之间；所述第三辅助部分在所述基底上的正投影，位于所述第六过孔在所述基底上的正投影与所述第四过孔在所述基底上的正投影之间。
  8. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：
    数据线层，所述数据线层包括位于各所述子像素区中的数据线图形，所述数据线图形的至少部分沿第二方向延伸；
    沿所述第一方向位于同一行子像素区中相邻的第三辅助信号线图形在耦接处形成屏蔽部，所述屏蔽部沿所述第二方向延伸，所述屏蔽部在所述基底上的正投影与所述数据线图形在所述基底上的正投影交叠，沿垂直于所述第二方向的方向上，所述屏蔽部的宽度大于所述数据线图形的宽度。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管；
    数据线层，所述数据线层包括位于各所述子像素区中的数据线图形，所述数据线图形的至少部分沿第二方向延伸，所述第一方向与所述第二方向相交；
    电源信号线层，所述电源信号线层包括位于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿所述第二方向延伸；
    在同一所述子像素区中，所述电源信号线图形在所述基底上的正投影，位于所述驱动晶体管的栅极在所述基底上的正投影与所述数据线图形在所述基底上的正投影之间。
  10. 根据权利要求9所述的显示面板，其中，所述电源信号线图形包括 相耦接的第一电源部和第二电源部，所述第一电源部沿所述第二方向延伸，所述第二电源部向远离其所在子像素区中的数据线图形的方向突出于所述第一电源部；在垂直于所述第二方向、且平行于所述基底的方向上，所述第一电源部的宽度大于所述第二电源部的宽度；
    所述驱动晶体管的第一极在所述基底上的正投影，与对应的子像素区中的所述第一电源部在所述基底上的正投影交叠，所述驱动晶体管的第一极与所述第一电源部在该交叠处耦接。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    第一屏蔽层，所述第一屏蔽层包括位于各所述子像素区中的第一屏蔽图形，所述第一屏蔽图形在所述基底上的正投影与所述第一电源部在所述基底上的正投影交叠，在该交叠处所述第一屏蔽图形与所述第一电源部耦接；所述第一屏蔽图形的至少部分沿所述第二方向延伸，所述第一屏蔽图形在所述基底上的正投影与所述数据线图形在所述基底上的正投影交叠。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    栅线层，所述栅线层包括位于各所述子像素区中的栅线图形，所述栅线图形的至少部分沿第一方向延伸；
    复位信号线层，所述复位信号线层包括位于各所述子像素区中的复位信号线图形，当前子像素区中的栅线图形与沿第二方向相邻的下一个子像素区中的复位信号线图形形成为一体结构。
  13. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：位于各所述子像素区中的电源信号线图形、数据线图形、复位信号线图形和发光控制信号线图形和栅线图形；还包括与所述子像素区一一对应的子像素驱动电路，每个所述子像素驱动电路均包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和存储电容；
    所述第一晶体管的栅极与所述栅线图形耦接，所述第一晶体管的第一极与所述数据线图形耦接，所述第一晶体管的第二极与所述存储电容的第二极板耦接，所述存储电容的第一极板与所述第三晶体管的栅极耦接；
    所述第二晶体管的栅极与所述栅线图形耦接，所述第二晶体管的第一极 与所述第三晶体管的第二极耦接，所述第二晶体管的第二极与所述第三晶体管的栅极耦接；
    所述第三晶体管的第一极与所述电源信号线图形耦接；
    所述第四晶体管的栅极与所述复位信号线图形耦接，所述第四晶体管的第一极与所述初始化信号线图形耦接，所述第四晶体管的第二极与所述第三晶体管的栅极耦接；
    所述第五晶体管的栅极与所述复位信号线图形耦接，所述第五晶体管的第一极与所述初始化信号线图形耦接，所述第五晶体管的第二极与所述存储电容的第二极板耦接；
    第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述初始化信号线图形耦接，所述第六晶体管的第二极与所述存储电容的第二极板耦接；
    第七晶体管的栅极与所述发光控制信号线图形耦接，所述第七晶体管的第一极与所述第三晶体管的第二极耦接，所述第七晶体管的第二极与对应的阳极图形耦接；
    所述第八晶体管的栅极与所述复位信号线图形耦接，所述第八晶体管的第一极与所述初始化信号线图形耦接，所述第八晶体管的第二极与对应的阳极图形耦接；
    所述第九晶体管的栅极与对应的所述发光控制信号线图形耦接，所述第九晶体管的第一极与所述第三晶体管的栅极耦接，所述第九晶体管的第二极浮接。
  14. 一种显示装置，包括如权利要求1～13中任一项所述的显示面板。
  15. 一种显示面板的制作方法，所述显示面板包括呈阵列分布的多个子像素区，沿第一方向位于同一行的子像素区划分为相互独立的多个子像素区组，每个子像素区组中包括相邻的至少两个子像素区；所述制作方法包括：
    在基底上制作初始化信号线层、转接层、阳极层和第一辅助信号线层；
    所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形；
    所述转接层包括设置于各所述子像素区中的转接图形，所述转接图形的 至少部分沿所述第一方向延伸，所述转接图形与其所在子像素区中的初始化信号线图形耦接；位于同一子像素区组中的各所述转接图形沿所述第一方向依次耦接，形成转接部；
    所述阳极层包括与所述多个子像素区一一对应的多个阳极图形，所述多个阳极图形间隔设置，在相邻的所述阳极图形之间形成阳极间隔区；
    所述第一辅助信号线层为网格状结构，所述第一辅助信号线层的至少部分位于所述阳极间隔区，且与所述阳极图形绝缘，各所述子像素区组中的转接部分别与所述第一辅助信号线层耦接。
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