WO2022061546A1 - 一种阵列基板及其制作方法、显示面板、显示装置 - Google Patents

一种阵列基板及其制作方法、显示面板、显示装置 Download PDF

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Publication number
WO2022061546A1
WO2022061546A1 PCT/CN2020/116915 CN2020116915W WO2022061546A1 WO 2022061546 A1 WO2022061546 A1 WO 2022061546A1 CN 2020116915 W CN2020116915 W CN 2020116915W WO 2022061546 A1 WO2022061546 A1 WO 2022061546A1
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Prior art keywords
metal layer
signal line
electrically connected
transistor
shielding structure
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PCT/CN2020/116915
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English (en)
French (fr)
Inventor
王刚
张锴
王仓鸿
宋二龙
蔡兴瑞
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN202080002062.XA priority Critical patent/CN114788007A/zh
Priority to PCT/CN2020/116915 priority patent/WO2022061546A1/zh
Priority to US17/419,389 priority patent/US20220320221A1/en
Publication of WO2022061546A1 publication Critical patent/WO2022061546A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a manufacturing method thereof, a display panel, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Display
  • OLED display has the advantages of low energy consumption, low production cost, self-illumination and wide viewing angle. and fast response.
  • OLED displays have begun to replace traditional LCD displays in display fields such as mobile phones, tablet computers, and digital cameras.
  • a first metal layer located on the base substrate, and the first metal layer includes a light-emitting control signal line;
  • a second metal layer located on the side of the first metal layer away from the base substrate, the second metal layer includes an anode overlapping electrode, and the anode overlapping electrode and the light-emitting control signal line have a first intersection. overlapping area;
  • a shielding structure located between the first metal layer and the second metal layer, the shielding structure is insulated from the first metal layer and the second metal layer, and the shielding structure is located on the substrate
  • the orthographic projection on the substrate and the orthographic projection of the first overlapping region on the base substrate at least partially cover, and the shielding structure is coupled to a fixed potential.
  • an orthographic projection area of the shielding structure on the base substrate is larger than an orthographic projection area of the first overlapping region on the base substrate 50%.
  • a third metal layer is further included between the first metal layer and the second metal layer, and the shielding structure is located on the third metal layer layer and the second metal layer, the shielding structure and the third metal layer are insulated from each other.
  • a third metal layer is further included between the first metal layer and the second metal layer, and the shielding structure is located on the third metal layer layer and the first metal layer, the shielding structure and the third metal layer are insulated from each other.
  • a third metal layer is further included between the first metal layer and the second metal layer, and the shielding structure is located on the third metal layer Floor.
  • the second metal layer further includes a driving voltage signal line
  • the third metal layer includes a capacitor plate electrically connected to the driving voltage signal line
  • the shielding structure and the capacitor electrode plate are integral structures.
  • the second metal layer further includes a data signal line arranged in parallel with the driving voltage signal line, and the capacitor plate and the data signal line have In the second overlapping region, along the extending direction of the data signal line, the width of the second overlapping region is smaller than the width of the non-overlapping portion of the capacitor plate and the data signal line.
  • the third metal layer includes an initialization signal line, and the shielding structure and the initialization signal line are integral structures.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure, it further includes: an insulating layer located on a side of the second metal layer away from the base substrate, and an insulating layer located on the side of the insulating layer away from the base substrate An anode on one side; the anode is electrically connected to the anode lap electrode through a via hole penetrating the insulating layer.
  • the anode and the anode overlap electrode have a third overlapping area, and the third overlapping area is a chamfered structure.
  • the second metal layer further includes a driving voltage signal line
  • the third metal layer includes an initialization signal line and a signal line that is electrically connected to the driving voltage signal line.
  • capacitor plate the extension directions of the initialization signal line and the light-emitting control signal line are the same, and the extension directions of the driving voltage signal line and the light-emitting control signal line cross each other;
  • the array substrate has a plurality of sub-pixel regions, and each of the sub-pixel regions includes: a first light-emitting control transistor and a second light-emitting control transistor that are electrically connected to the light-emitting control signal line, and a second light-emitting control transistor that is electrically connected to the initialization signal line. a first initialization transistor and a second initialization transistor;
  • Both the second light emission control transistor and the second initialization transistor are electrically connected to the anode bonding electrode.
  • each of the sub-pixel regions further includes: a first data writing transistor, a second data writing transistor, a driving transistor and a storage capacitor; wherein,
  • the gate of the first data writing transistor and the gate of the second data writing transistor are both electrically connected to the first scan line, and the first electrode of the first data writing transistor is electrically connected to the data signal line , the second pole of the first data writing transistor is electrically connected to the first pole of the driving transistor;
  • the first pole of the second data writing transistor is electrically connected to the gate of the driving transistor, and the second pole of the second data writing transistor is electrically connected to the second pole of the driving transistor;
  • the first pole of the storage capacitor is the capacitor plate, and the second pole of the storage capacitor is electrically connected to the gate of the driving transistor;
  • the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line, the first electrode of the first light-emitting control transistor is electrically connected to the driving voltage signal line, and the first electrode of the first light-emitting control transistor is electrically connected to the driving voltage signal line.
  • the diode is electrically connected to the first electrode of the driving transistor;
  • the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line
  • the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor
  • the second light-emitting control transistor The second pole is electrically connected to the anode lap electrode
  • the gate of the first initialization transistor is electrically connected to the second scan line, the first electrode of the first initialization transistor is electrically connected to the initialization signal line, and the second electrode of the first initialization transistor is electrically connected to the drive The gate of the transistor is electrically connected;
  • the gate of the second initialization transistor is electrically connected to the second scan line
  • the first electrode of the second initialization transistor is electrically connected to the initialization signal line
  • the second electrode of the second initialization transistor is electrically connected to the initialization signal line.
  • the anode is electrically connected to the lapped electrode.
  • an embodiment of the present disclosure further provides a display panel including the above-mentioned array substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display panel provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a method for fabricating an array substrate, including:
  • a first metal layer is formed on the base substrate; wherein, the first metal layer includes a light-emitting control signal line;
  • a second metal layer is formed on the base substrate on which the shielding structure is formed; wherein the shielding structure and the second metal layer are insulated from each other, and the second metal layer includes an anode overlapping electrode, and the anode overlapping
  • the connecting electrode and the light emitting control signal line have a first overlapping area, and the orthographic projection of the shielding structure on the base substrate at least covers the orthographic projection of the first overlapping area on the base substrate.
  • the method further includes: forming a driving voltage signal line on the second metal layer;
  • the method further includes: forming a third metal layer on the side of the first metal layer away from the base substrate, the third metal layer including being electrically connected to the driving voltage signal line the capacitor plate;
  • the capacitor electrode plate and the shielding structure are formed by one patterning process.
  • the method before forming the second metal layer, further includes: forming a third metal layer on a side of the first metal layer away from the base substrate, the third metal layer includes an initialization signal line;
  • the initialization signal line and the shielding structure are formed through one patterning process.
  • FIG. 1 is a schematic cross-sectional structure diagram of an array substrate provided in the related art
  • Fig. 2 is the top-view structure schematic diagram corresponding to Fig. 1;
  • FIG. 3 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of still another array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic cross-sectional structure diagram of still another array substrate according to an embodiment of the present disclosure.
  • Fig. 6 is a kind of top-view structure schematic diagram corresponding to Fig. 5;
  • Fig. 7 is another top-view structure schematic diagram corresponding to Fig. 5;
  • FIG. 8 is a schematic top-view structure diagram of a sub-pixel region in an array substrate according to an embodiment of the present disclosure.
  • FIG. 9A-9H are respectively schematic top-view structural views of each film layer corresponding to FIG. 8;
  • FIG. 10 is a schematic diagram of an equivalent circuit of the pixel driving circuit corresponding to FIG. 8;
  • FIG. 11 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 12A-FIG. 12F are schematic top-view structural views of fabricating the array substrate shown in FIG. 8 after each step is performed;
  • FIG. 13 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • AMOLED Active-matrix organic light emitting diode
  • AMOLED Active-matrix organic light emitting diode
  • its bright and rich color display is more and more popular with more and more people, and the uniformity of color display appears very important.
  • AMOLED is a current-driven light-emitting device, when displaying low gray scale, the current itself is very small.
  • the parasitic capacitance and leakage paths existing between the pixels make its color display distorted, and the color coordinate shifts, etc. It affects its display quality and the sensory experience of consumers.
  • FIG. 1 is a schematic diagram of part of the layout design of the 7T1C pixel driving circuit
  • FIG. 2 is a schematic cross-sectional structure diagram along the MM' direction in FIG. 1 .
  • the second The signal of the metal layer 9 is the signal of the anode 11. Therefore, when the EM signal changes (when the EM is switched from on to off), the voltage of the second metal layer 9 will rise through the parasitic capacitance (ie, the voltage of the anode 11 will rise), This in turn causes the pixel to emit light. For example, at a low gray scale, lighting a single-color screen will cause other color pixels to emit light, causing color coordinate shifts, and so on. Especially when the EM needs to switch more times, it will seriously aggravate this problem, so it is more and more important to improve this parasitic capacitance.
  • an array substrate provided by an embodiment of the present disclosure includes:
  • the first metal layer 5 is located on the base substrate 1, and the first metal layer 5 includes the light-emitting control signal line EM;
  • the second metal layer 9 is located on the side of the first metal layer 5 away from the base substrate 1.
  • the second metal layer 9 includes an anode overlapping electrode 91, and the anode overlapping electrode 91 and the light-emitting control signal line EM have a first overlapping area DD ;
  • the shielding structure 13 is located between the first metal layer 5 and the second metal layer 9.
  • the shielding structure 13 is insulated from the first metal layer 5 and the second metal layer 9.
  • the orthographic projection of the shielding structure 13 on the base substrate 1 is At least partially covering the orthographic projection of the first overlapping region DD on the base substrate 1 , the shielding structure 13 is coupled to a fixed potential.
  • a shielding structure 13 which is mutually insulated from the first metal layer 5 and the second metal layer 9 is provided between the first metal layer 5 and the second metal layer 9, and the shielding structure 13 is coupled to Connected to a fixed potential, so that the shielding structure 13 can reduce or eliminate the parasitic capacitance between the light-emitting control signal line EM and the anode bonding electrode 91, and can prevent the anode voltage electrically connected to the anode bonding electrode 91 from changing, thereby improving the display chromaticity. uniformity.
  • the parasitic capacitance between the light emission control signal line EM and the anode bonding electrode 91 generally includes the overlap capacitance and the lateral capacitance between the light emission control signal line EM and the anode bonding electrode 91, and the shielding structure 13 can shield the the overlap capacitance and side capacitance.
  • the orthographic projection area on the DD is greater than 50% of the orthographic projection area of the first overlapping region DD on the base substrate 1 .
  • the orthographic projection area of the shielding structure 13 on the base substrate 1 is larger than the orthographic projection area of the first overlapping region DD on the base substrate 1, so that the shielding structure 13 can
  • the entire first overlapping area DD is shielded, and the parasitic capacitance between the light-emitting control signal line EM and the anode bonding electrode 91 will not affect the anode voltage electrically connected to the anode bonding electrode 91, further improving the uniformity of display chromaticity.
  • the area of the shielding structure 13 should not be too large, and is set according to actual needs.
  • the above-mentioned array substrate provided in the embodiment of the present disclosure further includes a third metal layer 7 located between the first metal layer 5 and the second metal layer 9 , and the shielding structure 13 is located at Between the third metal layer 7 and the second metal layer 9 , the shielding structure 13 and the third metal layer 7 are insulated from each other. That is, by disposing the shielding structure 13 between the third metal layer 7 and the second metal layer 9 in the embodiment of the present disclosure, the parasitic capacitance between the light emission control signal line EM and the anode bonding electrode 91 can be shielded.
  • the above-mentioned array substrate provided in the embodiment of the present disclosure further includes a third metal layer 7 located between the first metal layer 5 and the second metal layer 9 , and the shielding structure 13 is located in Between the third metal layer 7 and the first metal layer 5 , the shielding structure 13 and the third metal layer 7 are insulated from each other. That is, by disposing the shielding structure 13 between the third metal layer 7 and the first metal layer 5 in the embodiment of the present disclosure, the parasitic capacitance between the light emission control signal line EM and the anode bonding electrode 91 can also be shielded.
  • the shielding structure 13 when the shielding structure 13 adopts the structure shown in FIG. 3 or FIG. 4 , the shielding structure 13 may be grounded.
  • the shielding structure 13 shown in FIGS. 3 and 4 is a metal layer separately added to the array substrate provided by the embodiment of the present disclosure, which is not conducive to the requirement of light and thin display devices.
  • the shielding structure 13 is located on the third metal layer 7 .
  • the first metal layer 5 is generally used to fabricate gates, scan lines and other structures
  • the third metal layer 7 is generally used to fabricate the storage capacitor structure of the pixel circuit in the array substrate. In this way, it only needs to be changed when the third metal layer 7 is formed.
  • the pattern of the shielding structure 13 and the third metal layer 7 can be formed by one patterning process without adding a separate process for preparing the shielding structure 13 , which can simplify the manufacturing process, save production costs, and improve production efficiency.
  • FIG. 6 is a schematic top-view structure diagram of some film layers in the array substrate provided by the embodiment of the present disclosure
  • FIG. 5 is a diagram 6 is a schematic cross-sectional structure extending along the NN' direction
  • the second metal layer 9 further includes a driving voltage signal line VDD
  • the third metal layer 7 includes a capacitor plate 71 electrically connected to the driving voltage signal line VDD;
  • the shielding structure 13 and the capacitor plate 71 are integrally formed. In this way, it is only necessary to change the original patterning pattern when forming the capacitor electrode plate 71, and the pattern of the shielding structure 13 and the capacitor electrode plate 71 can be formed by one patterning process without adding a separate process for preparing the shielding structure 13, which can simplify the manufacturing process. process, saving production costs and improving production efficiency.
  • the area of the capacitor plate 71 is equivalent to increase, and the capacitance of the driving voltage signal line VDD can be increased, and the VDD power supply signal can be greatly affected. stability is beneficial.
  • the second metal layer 9 further includes the data signal line Data arranged in parallel with the driving voltage signal line VDD, the capacitor plate 71 and the data signal line VDD.
  • the signal line Data has a second overlapping area (the portion of the oval dotted line in FIG. 8 ), and along the extension direction of the data signal line, the width D1 of the second overlapping area is smaller than the non-overlapping portion of the capacitor plate 71 and the data signal line Data The width D2.
  • the capacitor plate 71 is electrically connected to the driving voltage signal line VDD, that is, the signal on the capacitor plate 71 is the VDD signal, while the signal on the data signal line Data changes, the change of the Data signal will affect the VDD signal.
  • the signal interferes, causing signal crosstalk between pixels; therefore, it is better that the capacitor plate 71 does not overlap with the data signal line Data, but in order to ensure the stability of the VDD signal, it is necessary to increase the capacitance of the electrical connection of the VDD signal, so in order to balance the pixels
  • the capacitor plate 71 only partially overlaps with the data signal line Data.
  • FIG. 7 is a schematic top-view structure diagram of some film layers in the array substrate provided by the embodiment of the present disclosure
  • FIG. 5 is a diagram 7 is a schematic diagram of a cross-sectional structure extending along the NN' direction
  • the third metal layer 7 includes an initialization signal line Init
  • the shielding structure 13 and the initialization signal line Init are integrated into a structure.
  • the pattern of the shielding structure 13 and the initialization signal line Init can be formed by one patterning process, without adding a separate process for preparing the shielding structure 13, which can simplify the manufacturing process. process, saving production costs and improving production efficiency.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG. 5 , FIG. 6 and FIG. 7 , it further includes: a fourth insulating layer 10 located on the side of the source-drain metal 9 away from the base substrate 1 . , and the anode 11 located on the side of the fourth insulating layer 10 away from the base substrate 1 ; Since the voltage on the anode bonding electrode 91 is the same as the voltage on the anode 11, the shielding structure 13 shields the parasitic capacitance between the light-emitting control signal line EM and the anode bonding electrode 91, that is, the influence of the parasitic capacitance on the voltage of the anode 11 is shielded. Improve the uniformity of display chromaticity.
  • the above-mentioned array substrate provided in the embodiment of the present disclosure further includes: a buffer layer 2 and an active layer 3 that are stacked between the base substrate 1 and the first metal layer 5 . and the first insulating layer 4, the second insulating layer 6 between the first metal layer 5 and the third metal layer 7, the third insulating layer 8 between the third metal layer 7 and the second metal layer 9, and
  • the pixel definition layer 12 is located on the side of the anode 11 away from the base substrate 1 .
  • the array substrate provided by the embodiments of the present disclosure also includes other functional film layers known to those skilled in the art, which are not listed here.
  • the first insulating layer 4 and the second insulating layer 6 may be gate insulating layers
  • the third insulating layer 8 may be an interlayer insulating layer
  • the fourth insulating layer 10 may be a flat layer.
  • FIG. 6 and FIG. 7 are only schematic top-view structural schematic diagrams of a sub-pixel region when the shielding structure 13 is located in the third metal layer 7 .
  • FIG. 8 is a detailed top-view structural schematic diagram of a sub-pixel region in the array substrate provided by the embodiment of the present disclosure, and FIG. 8 uses a shielding Structure and capacitor plate as one structure
  • the second metal layer 9 also includes a drive voltage signal line VDD
  • the third metal layer 7 includes an initialization signal line Init and a capacitor plate 71 electrically connected to the drive voltage signal line VDD;
  • the extension directions of the initialization signal line Init and the light emission control signal line EM are the same, and the extension directions of the driving voltage signal line VDD and the light emission control signal line EM cross each other.
  • a sub-pixel area includes a 7T1C pixel circuit as an example.
  • a 7T1C pixel circuit it is necessary to fabricate the active layer 3 , the first metal layer 5 , the first metal layer 5 , the The three metal layers 7, the third insulating layer 8, the second metal layer 9, the fourth insulating layer 10, the anode 11, the pixel defining layer 12, etc., the schematic top-view structures of the layers are shown in Figs. 9A-9H, respectively. .
  • FIG. 9D illustrates the via area of the third insulating layer 8
  • FIG. 9F illustrates the via area of the fourth insulating layer 10
  • FIG. 9H illustrates the opening area of the pixel defining layer 12 .
  • FIGS. 9A-9H only show schematic top views of the main film layers in the sub-pixel area.
  • each sub-pixel area also includes buffer layer 2, first insulating layer 4, second insulating layer 6 and other films. layer structure.
  • the anode overlapping portion 91 and the gate of the driving transistor T3 do not overlap.
  • the anode 11 and the anode overlapping electrode 91 have a third overlapping area (The portion of the dashed line in FIG. 9G ), the third overlapping area is a chamfered structure, which prevents the third overlapping area from being formed into sharp corners, which is beneficial to reduce electrostatic damage during mask manufacturing.
  • the active layer 3 has a “U”-shaped area
  • the capacitor plate 71 covers the “U”-shaped area and the active area on the left side of the “U”-shaped area.
  • Layer 3 the structure of the capacitor plate 71 is set in this way to shield the interference of the data line Data line to the source of the driving transistor T3, so as to prevent the source of the driving transistor T3 from being unstable due to the influence of the high-frequency Data signal, resulting in poor display. question.
  • the capacitor plate 71 may partially cover the active layer on the right side of the "U"-shaped region, and the coverage area is less than 50% of the area of the active layer on the right side of the "U”-shaped region.
  • the diodes at least partially overlap, in order to reduce the formation of a coupling capacitance between the second electrode of the driving transistor T3 and VDD, thereby reducing the risk that the anode voltage is pulled up to cause the black screen to become brighter.
  • the second electrode of the driving transistor T3 may be the drain electrode.
  • the shape of the "U"-shaped region of the active layer 3 in FIG. 9A can also be an S-shaped or H-shaped shape, which can be designed according to actual needs, and the specific shape is not limited in the present disclosure.
  • the driving voltage signal line VDD is set to a structure with a narrow top and a wide bottom to ensure the layout uniformity of the array substrate, that is, the metal of the same layer should try to ensure that the distance between the lines is the same as possible. .
  • FIG. 10 is a schematic diagram of an equivalent circuit structure of the pixel circuit corresponding to FIG. 8
  • the array substrate has a plurality of sub-pixel regions (this disclosure only illustrates one sub-pixel region), each The sub-pixel area includes: a first light-emitting control transistor T4 and a second light-emitting control transistor T7 electrically connected to the light-emitting control signal line EM, and a first initialization transistor T1 and a second initialization transistor T6 electrically connected to the initialization signal line Init;
  • Both the second light emission control transistor T7 and the second initialization transistor T6 are electrically connected to the anode bonding electrode 91 .
  • each sub-pixel region further includes: a first data writing transistor T5, a second data writing transistor T2, drive transistor T3 and storage capacitor Cst; wherein,
  • the gate of the first data writing transistor T5 and the gate of the second data writing transistor T2 are both electrically connected to the first scan line Sn, and the first pole of the first data writing transistor T5 is electrically connected to the data signal line Data, The second pole of the first data writing transistor T5 is electrically connected to the first pole of the driving transistor T3;
  • the first pole of the second data writing transistor T2 is electrically connected to the gate of the driving transistor T3, and the second pole of the second data writing transistor T2 is electrically connected to the second pole of the driving transistor T3;
  • the first pole of the storage capacitor Cst is the capacitor plate 91, and the second pole of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3; specifically, as shown in FIG. 8, the capacitor plate 91 of the storage capacitor Cst is connected to the shielding structure 13 integrated structure;
  • the gate of the first light-emitting control transistor T4 is electrically connected to the light-emitting control signal line EM, the first electrode of the first light-emitting control transistor T4 is electrically connected to the driving voltage signal line VDD, and the second electrode of the first light-emitting control transistor T4 is electrically connected to the driving transistor
  • the first pole of T3 is electrically connected;
  • the gate of the second light-emitting control transistor T7 is electrically connected to the light-emitting control signal line EM, the first electrode of the second light-emitting control transistor T7 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the second light-emitting control transistor T7 is electrically connected to the second electrode of the driving transistor T3.
  • the anode lap electrode 91 is electrically connected;
  • the gate of the first initialization transistor T1 is electrically connected to the second scan line Sn-1, the first electrode of the first initialization transistor T1 is electrically connected to the initialization signal line Init, and the second electrode of the first initialization transistor T1 is electrically connected to the drive transistor T3. grid electrical connection;
  • the gate of the second initialization transistor T6 is electrically connected to the second scan line Sn-1, the first electrode of the second initialization transistor T6 is electrically connected to the initialization signal line Init, and the second electrode of the second initialization transistor T6 is connected to the anode electrode 91 Electrical connections.
  • the thin film transistor included in each sub-pixel region is generally an oxide transistor (Oxide TFT).
  • the light shielding layer of the object TFT is not limited in the present disclosure.
  • each sub-pixel region further includes a light-emitting device L electrically connected to the anode overlap electrode 91 .
  • the 7T1C pixel drive circuit is used to drive the light-emitting device L to emit light.
  • the driving transistor since the driving transistor is used to output a stable current to drive the light-emitting device to emit light, the gate voltage stability of the driving transistor is very important, so it is necessary to reduce the leakage current between the gate of the driving transistor and the storage capacitor , so in order to reduce the leakage current between the gate of the driving transistor and the storage capacitor, in the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG. 8 and FIG. 10 , the first initialization transistor T1 and the second data write The transistors T2 are all double-gate transistors.
  • the first initialization transistor T1 includes a first initialization sub-transistor T1 1 and a second initialization sub-transistor T1 2 connected in series
  • the second data writing transistor T2 includes a first data writing sub-transistor T2 1 and a second data writing sub-transistor T2 1 connected in series Write sub-transistor T2 2 .
  • the principle of driving the light-emitting device L to emit light by the pixel driving circuit shown in FIG. 8 and FIG. 10 is the same as that of the prior art, and the difference from the prior art is that the capacitor plate 71 of the storage capacitor Cst and the shielding structure 13 are fabricated It is equivalent to changing the patterning process when making the capacitor electrode plate 71, increasing the pattern of the capacitor electrode plate 71, so that the enlarged part covers the first overlap of the anode lap electrode 91 and the light-emitting control signal line EM In the area DD, the enlarged portion is the shielding structure 13, so as to realize the function of shielding the parasitic capacitance formed by the anode lap electrode 91 and the light-emitting control signal line EM, and improve the uniformity of display chromaticity.
  • the array substrate generally includes a plurality of sub-pixel regions of different colors, such as red sub-pixels, green sub-pixels, and blue sub-pixels.
  • the shape of the shielding structure corresponding to the sub-pixel regions of different colors may be The same or different, or sub-pixels of some colors may not be provided with a shielding structure.
  • the setting position of the shielding structure can be set according to actual needs.
  • an embodiment of the present disclosure also provides a method for fabricating an array substrate, as shown in FIG. 11 , including:
  • the shielding structure and the second metal layer are insulated from each other, and the second metal layer includes an anode overlapping electrode, and the anode overlapping electrode and the light-emitting control signal line have In the first overlapping area, the orthographic projection of the shielding structure on the base substrate at least covers the orthographic projection of the first overlapping area on the base substrate.
  • a shielding structure that is mutually insulated from the first metal layer and the second metal layer is provided between the first metal layer and the second metal layer, and the shielding structure is coupled to a fixed potential
  • the shielding structure can reduce or eliminate the parasitic capacitance between the light-emitting control signal line and the anode overlapping electrode, and can prevent the anode voltage electrically connected to the anode overlapping electrode from changing, thereby improving the uniformity of display chromaticity.
  • the method further includes: forming a driving voltage signal line on the second metal layer;
  • the method further includes: forming a third metal layer on the side of the first metal layer away from the base substrate, and the third metal layer includes a capacitor electrode plate electrically connected to the driving voltage signal line;
  • the capacitor plate and the shielding structure are formed by one patterning process. In this way, it is only necessary to change the original patterning pattern when forming the capacitor electrode plate, and then the pattern of the shielding structure and the capacitor electrode plate can be formed by one patterning process, without adding a separate process for preparing the shielding structure, which can simplify the manufacturing process flow and save production. cost and improve production efficiency.
  • the method before forming the second metal layer, the method further includes: forming a third metal layer on the side of the first metal layer away from the base substrate, and the third metal layer includes Initialize the signal line;
  • the initialization signal lines and the shielding structure are formed by one patterning process. In this way, it is only necessary to change the original patterning pattern when forming the initialization signal line, and the pattern of the shielding structure and the initialization signal line can be formed by one patterning process, without adding a separate process for preparing the shielding structure, which can simplify the manufacturing process flow and save production. cost and improve production efficiency.
  • the pattern of the active layer 3 is formed on the base substrate, and the pattern of at least the first metal layer 5 is formed on the active layer 3 , as shown in FIG. 12A .
  • the pattern of the third metal layer 7 is formed on the first metal layer 5, and the pattern of the shielding structure 13 and the capacitor electrode plate 71 is formed through a patterning process, as shown in FIG. 12B.
  • a pattern of the third insulating layer 8 is formed on the third metal layer 7, as shown in FIG. 12C.
  • a pattern of the second metal layer 9 is formed on the third insulating layer 8, as shown in FIG. 12D.
  • a pattern of the fourth insulating layer 10 is formed on the second metal layer 9, as shown in FIG. 12E.
  • a pattern of the anode 11 is formed on the fourth insulating layer 10, as shown in FIG. 12F.
  • a pattern of the pixel definition layer 12 is formed on the anode 11, as shown in FIG. 8 .
  • steps (1)-(7) only show schematic diagrams of the fabrication of the main film layers, and of course also include fabrication of other film layer structures such as the buffer layer 2 , the first insulating layer 4 , and the second insulating layer 6 .
  • each film layer may be fabricated by a patterning process.
  • the patterning process may only include a photolithography process, or may include a photolithography process and
  • the etching step can also include printing, inkjet and other processes for forming a predetermined pattern;
  • the lithography process refers to the use of photoresist, mask, exposure machine, etc. to form processes including film formation, exposure, development and other processes.
  • Graphic craft During specific implementation, a corresponding patterning process can be selected according to the structure formed in the present invention.
  • an embodiment of the present disclosure further provides a display panel including the above-mentioned array substrate provided by an embodiment of the present disclosure.
  • the problem-solving principle of the display panel is similar to that of the aforementioned array substrate. Therefore, the implementation of the display panel can refer to the aforementioned implementation of the array substrate, and repeated details will not be repeated here.
  • the display panel provided by the embodiments of the present disclosure is an organic light-emitting display panel.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure.
  • the principle of solving the problem of the display device is similar to that of the aforementioned array substrate. Therefore, the implementation of the display device can refer to the aforementioned implementation of the array substrate, and the repetition will not be repeated here.
  • the above-mentioned display device provided by the embodiments of the present disclosure may be a full-screen display device, or may also be a flexible display device, etc., which is not limited herein.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be a mobile phone with a full screen as shown in FIG. 13 .
  • the above-mentioned display device provided by the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.
  • a shielding structure that is mutually insulated from the first metal layer and the second metal layer is provided between the first metal layer and the second metal layer, and The shielding structure is coupled to a fixed potential, so that the shielding structure can reduce or eliminate the parasitic capacitance between the light-emitting control signal line and the anode overlapping electrode, and can prevent the anode voltage electrically connected to the anode overlapping electrode from changing, thereby improving the display chromaticity. uniformity.

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Abstract

一种阵列基板及其制作方法、显示面板、显示装置，阵列基板包括：衬底基板（1）；第一金属层（5），位于衬底基板（1）上，第一金属层（5）包括发光控制信号线（EM）；第二金属层（9），位于第一金属层（5）背离衬底基板（1）一侧，第二金属层（9）包括阳极搭接电极（91），阳极搭接电极（91）和发光控制信号线（EM）具有第一交叠区域（DD）；屏蔽结构（13），位于第一金属层（5）和第二金属层（9）之间，屏蔽结构（13）与第一金属层（5）、第二金属层（9）相互绝缘，屏蔽结构（13）在衬底基板（1）上的正投影与第一交叠区域（DD）在衬底基板（1）上的正投影至少部分覆盖，屏蔽结构（13）耦接固定电位。

Description

一种阵列基板及其制作方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及其制作方法、显示面板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)是当今平板显示器研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。目前，在手机、平板电脑、数码相机等显示领域，OLED显示器已经开始取代传统的LCD显示器。
发明内容
本公开实施例提供的一种阵列基板，包括：
衬底基板；
第一金属层，位于所述衬底基板上，所述第一金属层包括发光控制信号线；
第二金属层，位于所述第一金属层背离所述衬底基板一侧，所述第二金属层包括阳极搭接电极，所述阳极搭接电极和所述发光控制信号线具有第一交叠区域；
屏蔽结构，位于所述第一金属层和所述第二金属层之间，所述屏蔽结构与所述第一金属层、所述第二金属层相互绝缘，所述屏蔽结构在所述衬底基板上的正投影与所述第一交叠区域在所述衬底基板上的正投影至少部分覆盖，所述屏蔽结构耦接固定电位。
可选地，在本公开实施例提供的上述阵列基板中，所述屏蔽结构在所述衬底基板上的正投影面积大于所述第一交叠区域在所述衬底基板上的正投影 面积的50％。
可选地，在本公开实施例提供的上述阵列基板中，还包括位于所述第一金属层和所述第二金属层之间的第三金属层，所述屏蔽结构位于所述第三金属层和所述第二金属层之间，所述屏蔽结构与所述第三金属层相互绝缘。
可选地，在本公开实施例提供的上述阵列基板中，还包括位于所述第一金属层和所述第二金属层之间的第三金属层，所述屏蔽结构位于所述第三金属层和所述第一金属层之间，所述屏蔽结构与所述第三金属层相互绝缘。
可选地，在本公开实施例提供的上述阵列基板中，还包括位于所述第一金属层和所述第二金属层之间的第三金属层，所述屏蔽结构位于所述第三金属层。
可选地，在本公开实施例提供的上述阵列基板中，所述第二金属层还包括驱动电压信号线，所述第三金属层包括与所述驱动电压信号线电连接的电容极板；
所述屏蔽结构与所述电容极板为一体结构。
可选地，在本公开实施例提供的上述阵列基板中，所述第二金属层还包括与所述驱动电压信号线平行设置的数据信号线，所述电容极板和所述数据信号线具有第二交叠区域，沿所述数据信号线的延伸方向，所述第二交叠区域的宽度小于所述电容极板和所述数据信号线未交叠部分的宽度。
可选地，在本公开实施例提供的上述阵列基板中，所述第三金属层包括初始化信号线，所述屏蔽结构与所述初始化信号线为一体结构。
可选地，在本公开实施例提供的上述阵列基板中，还包括：位于所述第二金属层背离所述衬底基板一侧的绝缘层，以及位于所述绝缘层背离所述衬底基板一侧的阳极；所述阳极通过贯穿所述绝缘层的过孔与所述阳极搭接电极电连接。
可选地，在本公开实施例提供的上述阵列基板中，所述阳极与所述阳极搭接电极具有第三交叠区域，所述第三交叠区域为倒角结构。
可选地，在本公开实施例提供的上述阵列基板中，所述第二金属层还包 括驱动电压信号线，所述第三金属层包括初始化信号线以及与所述驱动电压信号线电连接的电容极板；所述初始化信号线和所述发光控制信号线的延伸方向相同，所述驱动电压信号线和所述发光控制信号线的延伸方向相互交叉；
所述阵列基板具有多个子像素区域，每一所述子像素区域包括：与所述发光控制信号线电连接的第一发光控制晶体管和第二发光控制晶体管，与所述初始化信号线电连接的第一初始化晶体管和第二初始化晶体管；
所述第二发光控制晶体管和所述第二初始化晶体管均与所述阳极搭接电极电连接。
可选地，在本公开实施例提供的上述阵列基板中，每一所述子像素区域还包括：第一数据写入晶体管，第二数据写入晶体管，驱动晶体管和存储电容；其中，
所述第一数据写入晶体管的栅极和所述第二数据写入晶体管的栅极均与第一扫描线电连接，所述第一数据写入晶体管的第一极与数据信号线电连接，所述第一数据写入晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第二数据写入晶体管的第一极与所述驱动晶体管的栅极电连接，所述第二数据写入晶体管的第二极与所述驱动晶体管的第二极电连接；
所述存储电容的第一极为所述电容极板，所述存储电容的第二极与所述驱动晶体管的栅极电连接；
所述第一发光控制晶体管的栅极与所述发光控制信号线电连接，所述第一发光控制晶体管的第一极与所述驱动电压信号线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第二发光控制晶体管的栅极与所述发光控制信号线电连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述阳极搭接电极电连接；
所述第一初始化晶体管的栅极与第二扫描线电连接，所述第一初始化晶体管的第一极与所述初始化信号线电连接，所述第一初始化晶体管的第二极与所述驱动晶体管的栅极电连接；
所述第二初始化晶体管的栅极与所述第二扫描线电连接，所述第二初始化晶体管的第一极与所述初始化信号线电连接，所述第二初始化晶体管的第二极与所述阳极搭接电极电连接。
相应地，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述阵列基板。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。
相应地，本公开实施例还提供了一种阵列基板的制作方法，包括：
在衬底基板上形成第一金属层；其中，所述第一金属层包括发光控制信号线；
在形成有所述第一金属层的衬底基板上形成屏蔽结构；其中，所述屏蔽结构与所述第一金属层相互绝缘，且所述屏蔽结构耦接固定电位；
在形成有所述屏蔽结构的衬底基板上形成第二金属层；其中，所述屏蔽结构与所述第二金属层相互绝缘，所述第二金属层包括阳极搭接电极，所述阳极搭接电极和所述发光控制信号线具有第一交叠区域，所述屏蔽结构在所述衬底基板上的正投影至少覆盖所述第一交叠区域在所述衬底基板上的正投影。
可选地，在本公开实施例提供的上述制作方法中，还包括：在所述第二金属层形成驱动电压信号线；
在形成所述第二金属层之前，还包括：在所述第一金属层背离所述衬底基板一侧形成第三金属层，所述第三金属层包括与所述驱动电压信号线电连接的电容极板；
通过一次构图工艺形成所述电容极板和所述屏蔽结构。
可选地，在本公开实施例提供的上述制作方法中，在形成所述第二金属层之前，还包括：在所述第一金属层背离所述衬底基板一侧形成第三金属层，所述第三金属层包括初始化信号线；
通过一次构图工艺形成所述初始化信号线和所述屏蔽结构。
附图说明
图1为相关技术中提供的一种阵列基板的截面结构示意图；
图2为图1对应的俯视结构示意图；
图3为本公开实施例提供的一种阵列基板的截面结构示意图；
图4为本公开实施例提供的又一种阵列基板的截面结构示意图；
图5为本公开实施例提供的又一种阵列基板的截面结构示意图；
图6为图5对应的一种俯视结构示意图；
图7为图5对应的又一种俯视结构示意图；
图8为本公开实施例提供的一种阵列基板中一个子像素区域的俯视结构示意图；
图9A-图9H分别为图8对应的每一膜层的俯视结构示意图；
图10为图8对应的像素驱动电路的等效电路示意图；
图11为本公开实施例提供的一种阵列基板的制作方法流程示意图；
图12A-图12F分别为制作图8所示的阵列基板在执行每一步骤之后的俯视结构示意图；
图13为本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面 列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
有源发光矩阵二极管(Active-matrix organic light emitting diode，AMOLED)在显示领域的应用越来越广泛，其鲜艳丰富的色彩显示更受到越来越多的人喜欢，色彩显示的均一性就显得十分重要了。但是由于AMOLED是电流驱动发光的器件，在显示低灰阶的时候，本身电流就很小，再加上像素之间存在的寄生电容和漏电路径使得其颜色显示失真，色坐标偏移等，严重影响了其显示品质和消费者的感官体验。
相关技术中，在7T1C像素驱动电路的版图设计方面，如图1和图2所示，图1为7T1C像素驱动电路的部分版图设计示意图，图2为图1中沿MM’方向的截面结构示意图，包括：衬底基板1，位于衬底基板1上依次层叠设置的缓冲层2、有源层3、第一绝缘层4、第一金属层5、第二绝缘层6、第三金属层7、第三绝缘层8、第二金属层9、第四绝缘层10、阳极11和像素定义层12等膜层，阳极11通过贯穿第四绝缘层10的过孔与第二金属层9搭接，第一金属层5一般设置有发光控制线EM，发光控制线EM与阳极11下方的第二金属层9直接交叠形成寄生电容(图1和图2中的虚线框所示)，第二金属层9的信号即为阳极11的信号，因此EM信号变化(当EM从开到关)时，会通过此寄生电容引起第二金属层9电压升高(即引起阳极11电压升高)，进而导致像素发光。例如在低灰阶时，点亮某一单色画面时，会引起其他颜色像素发光，引起色坐标偏移等。尤其当EM需要开关次数较多时，会严重加重此问题，因此改善此寄生电容也显得越来越重要。
有鉴于此，本公开实施例提供的一种阵列基板，如图3-图5所示，包括：
衬底基板1；
第一金属层5，位于衬底基板1上，第一金属层5包括发光控制信号线EM；
第二金属层9，位于第一金属层5背离衬底基板1一侧，第二金属层9包括阳极搭接电极91，阳极搭接电极91和发光控制信号线EM具有第一交叠区域DD；
屏蔽结构13，位于第一金属层5和第二金属层9之间，屏蔽结构13与第一金属层5、第二金属层9相互绝缘，屏蔽结构13在衬底基板1上的正投影至与第一交叠区域DD在衬底基板1上的正投影至少部分覆盖，屏蔽结构13耦接固定电位。
本发明实施例提供的上述阵列基板，通过在第一金属层5和第二金属层9之间设置与第一金属层5和第二金属层9相互绝缘的屏蔽结构13，且屏蔽结构13耦接固定电位，这样屏蔽结构13能够降低或消除发光控制信号线EM和阳极搭接电极91之间的寄生电容，可以避免与阳极搭接电极91电连接的阳极电压发生变化，从而提高显示色度的均一性。
具体地，发光控制信号线EM和阳极搭接电极91之间的寄生电容一般包括发光控制信号线EM和阳极搭接电极91之间的交叠电容和侧向电容，屏蔽结构13的设置可以屏蔽该交叠电容和侧向电容。
在具体实施时，为了能够有效降低发光控制信号线和阳极搭接电极之间的寄生电容，在本公开实施例提供的上述阵列基板中，如图3所示，屏蔽结构13在衬底基板1上的正投影面积大于第一交叠区域DD在衬底基板1上的正投影面积的50％。本公开实施例附图是以屏蔽结构13在衬底基板1上的正投影面积大于第一交叠区域DD在衬底基板1上的正投影面积为例进行示意的，这样屏蔽结构13可以将整个第一交叠区域DD屏蔽，发光控制信号线EM和阳极搭接电极91之间的寄生电容完全不会影响阳极搭接电极91电连接的阳极电压，进一步提高显示色度的均一性。当然，在具体实施时，屏蔽结构13的面积不宜过大，根据实际需要进行设置。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图3所示，还包括位于第一金属层5和第二金属层9之间的第三金属层7，屏蔽结构13位于第三金属层7和第二金属层9之间，屏蔽结构13与第三金属层7相互绝缘。即本公开实施例通过在第三金属层7和第二金属层9之间设置屏蔽结构13，可以起到屏蔽发光控制信号线EM和阳极搭接电极91之间的寄生电容的作用。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图4所示，还包括位于第一金属层5和第二金属层9之间的第三金属层7，屏蔽结构13位于第三金属层7和第一金属层5之间，屏蔽结构13与第三金属层7相互绝缘。即本公开实施例通过在第三金属层7和第一金属层5之间设置屏蔽结构13，也可以起到屏蔽发光控制信号线EM和阳极搭接电极91之间的寄生电容的作用。
在具体实施时，在屏蔽结构13采用图3或图4所示的结构时，屏蔽结构13可以接地设置。
在具体实施时，图3和图4所示的屏蔽结构13是在本公开实施例提供的阵列基板中单独增加设置的一层金属层，这样不利于显示装置轻薄化的要求，因此，为了在实现显示装置轻薄化的基础上屏蔽发光控制信号线EM和阳极搭接电极91之间的寄生电容，在本公开实施例提供的上述阵列基板中，如图5所示，还包括位于第一金属层5和第二金属层9之间的第三金属层7，屏蔽结构13位于第三金属层7。具体地，第一金属层5一般是制作栅极、扫描线等结构，第三金属层7一般是制作阵列基板中像素电路的存储电容结构，这样，只需要在形成第三金属层7时改变原有的构图图形，即可通过一次构图工艺形成屏蔽结构13与第三金属层7的图形，不用增加单独制备屏蔽结构13的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图5和图6所示，图6为本公开实施例提供的阵列基板中部分膜层的俯视结构示意图，图5为图6中沿NN’方向延伸的截面结构示意图，第二金属层9还包括驱动电压信号线VDD，第三金属层7包括与驱动电压信号线VDD电连接的电容极板71；
屏蔽结构13与电容极板71为一体结构。这样，只需要在形成电容极板71 时改变原有的构图图形，即可通过一次构图工艺形成屏蔽结构13与电容极板71的图形，不用增加单独制备屏蔽结构13的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
并且，如图5所示，在采用屏蔽结构13与电容极板71为一体结构时，相当于增大了电容极板71的面积，则可以增大驱动电压信号线VDD电容，对VDD电源信号的稳定性起到有利的作用。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图8所示，第二金属层9还包括与驱动电压信号线VDD平行设置的数据信号线Data，电容极板71和数据信号线Data具有第二交叠区域(图8中椭圆形虚线框部分)，沿数据信号线的延伸方向，第二交叠区域的宽度D1小于电容极板71和数据信号线Data未交叠部分的宽度D2。具体地，由于电容极板71是与驱动电压信号线VDD电连接的，即电容极板71上的信号是VDD信号，而数据信号线Data上的信号是变化的，Data信号的变化会对VDD信号产生干扰，引起像素之间信号串扰(crosstalk)；因此电容极板71与数据信号线Data不交叠较佳，但是为了保证VDD信号稳定，需要增加VDD信号电连接的电容，因此为了平衡像素串扰和保证VDD信号稳定的问题，在沿数据信号线Data的延伸方向上，电容极板71仅部分与数据信号线Data交叠。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图5和图7所示，图7为本公开实施例提供的阵列基板中部分膜层的俯视结构示意图，图5为图7中沿NN’方向延伸的截面结构示意图，第三金属层7包括初始化信号线Init，屏蔽结构13与初始化信号线Init为一体结构。这样，只需要在形成初始化信号线Init时改变原有的构图图形，即可通过一次构图工艺形成屏蔽结构13与初始化信号线Init的图形，不用增加单独制备屏蔽结构13的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图5、图6和图7所示，还包括：位于源漏金属9背离衬底基板1一侧的第四绝缘层10，以及位于第四绝缘层10背离衬底基板1一侧的阳极11；阳极11通过贯穿第四绝缘层 10的过孔与阳极搭接电极91电连接。由于阳极搭接电极91上的电压与阳极11电压相同，因此屏蔽结构13屏蔽了发光控制信号线EM和阳极搭接电极91之间的寄生电容，即屏蔽了寄生电容对阳极11电压的影响，提高显示色度的均一性。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图5所示，还包括：位于衬底基板1和第一金属层5之间层叠设置的缓冲层2、有源层3和第一绝缘层4，位于第一金属层5和第三金属层7之间的第二绝缘层6，位于第三金属层7和第二金属层9之间的第三绝缘层8，以及位于阳极11背离衬底基板1一侧的像素定义层12。当然，本公开实施例提供的阵列基板还包括本领域技术人员熟知的其它功能性膜层，在此不做一一列举。
具体地，第一绝缘层4和第二绝缘层6可以为栅绝缘层，第三绝缘层8可以为层间绝缘层，第四绝缘层10可以为平坦层。
需要说明的是，图6和图7仅是为了示意屏蔽结构13位于第三金属层7时一个子像素区域的局部俯视结构示意图。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图8所示，图8为本公开实施例提供的阵列基板中一个子像素区域的详细俯视结构示意图，并且图8以屏蔽结构和电容极板为一体结构为了进行说明，第二金属层9还包括驱动电压信号线VDD，第三金属层7包括初始化信号线Init以及与驱动电压信号线VDD电连接的电容极板71；初始化信号线Init和发光控制信号线EM的延伸方向相同，驱动电压信号线VDD和发光控制信号线EM的延伸方向相互交叉。
具体地，如图8所示，图8以一个子像素区域包括7T1C像素电路为例，在制作7T1C像素电路时，需要在衬底基板1依次制作有源层3、第一金属层5、第三金属层7、第三绝缘层8、第二金属层9、第四绝缘层10、阳极11、像素界定层12等图形，该各膜层的俯视结构示意图分别如图9A-图9H所示。
需要说明的是，图9D示意的是第三绝缘层8的过孔区域，图9F示意的是第四绝缘层10的过孔区域，图9H示意的是像素界定层12的开口区域。
需要说明的是，图9A-图9H仅示意出子像素区域中主要膜层的俯视示意图，当然每一子像素区域还包括缓冲层2、第一绝缘层4、第二绝缘层6等其它膜层结构。
在具体实施时，如图8所示，阳极搭接部91和驱动晶体管T3的栅极不交叠，如图8和图9G所示，阳极11与阳极搭接电极91具有第三交叠区域(图9G中虚线框部分)，第三交叠区域为倒角结，构这样避免第三交叠区域设置成尖角，有利于掩膜版(mask)工艺制作时减少静电击伤。
在具体实施时，如图8、图9A和图10所示，有源层3具有一“U”型区，电容极板71覆盖“U”型区以及“U”型区左侧的有源层3，这样设置电容极板71的结构是为了屏蔽数据线Data线对驱动晶体管T3的源极的干扰，以免驱动晶体管T3的源极受到高频Data信号的影响而不稳定，发生显示不良的问题。另外，电容极板71可以部分覆盖“U”型区右侧有源层，并且覆盖面积为小于“U”型区右侧有源层面积的50％，电容极板71与驱动晶体管T3的第二极至少部分交叠，这是为了减小驱动晶体管T3的第二极和VDD形成耦合电容，进而减小阳极电压被拉高引起黑画面偏亮的风险。具体地，驱动晶体管T3的第二极可以为漏极。
在具体实施时，图9A中有源层3的“U”型区的形状还可以为S型或H型等形状，可以根据实际需要进行设计，本公开对具体形状不做限定。
需要说明的是，上述所说的“左侧”、“右侧”，只是对于本公开实施例的附图而言，当然也可能随着版图(layout)的变化以及信号传输方向变化，“左侧”、“右侧”可能有变化。
在具体实施时，如图8所示，驱动电压信号线VDD设置成上窄下宽的结构，是为了保证阵列基板的版图均一性，即同层的金属尽量保证线与线之间的距离一致。
具体地，如图8和图10所示，图10为图8对应的像素电路的等效电路结构示意图，该阵列基板具有多个子像素区域(本公开仅示意出一个子像素区域)，每一子像素区域包括：与发光控制信号线EM电连接的第一发光控制晶体管T4 和第二发光控制晶体管T7，与初始化信号线Init电连接的第一初始化晶体管T1和第二初始化晶体管T6；
第二发光控制晶体管T7和第二初始化晶体管T6均与阳极搭接电极91电连接。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图8和图10所示，每一子像素区域还包括：第一数据写入晶体管T5，第二数据写入晶体管T2，驱动晶体管T3和存储电容Cst；其中，
第一数据写入晶体管T5的栅极和第二数据写入晶体管T2的栅极均与第一扫描线Sn电连接，第一数据写入晶体管T5的第一极与数据信号线Data电连接，第一数据写入晶体管T5的第二极与驱动晶体管T3的第一极电连接；
第二数据写入晶体管T2的第一极与驱动晶体管T3的栅极电连接，第二数据写入晶体管T2的第二极与驱动晶体管T3的第二极电连接；
存储电容Cst的第一极为电容极板91，存储电容Cst的第二极与驱动晶体管T3的栅极电连接；具体地，如图8所示，存储电容Cst的电容极板91与屏蔽结构13为一体结构；
第一发光控制晶体管T4的栅极与发光控制信号线EM电连接，第一发光控制晶体管T4的第一极与驱动电压信号线VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T3的第一极电连接；
第二发光控制晶体管T7的栅极与发光控制信号线EM电连接，第二发光控制晶体管T7的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T7的第二极与阳极搭接电极91电连接；
第一初始化晶体管T1的栅极与第二扫描线Sn-1电连接，第一初始化晶体管T1的第一极与初始化信号线Init电连接，第一初始化晶体管T1的第二极与驱动晶体管T3的栅极电连接；
第二初始化晶体管T6的栅极与第二扫描线Sn-1电连接，第二初始化晶体管T6的第一极与初始化信号线Init电连接，第二初始化晶体管T6的第二极与阳极搭接电极91电连接。
具体地，每一子像素区域包括的薄膜晶体管一般为氧化物晶体管(Oxide TFT)，本公开实施例提供的屏蔽结构所在的膜层可以作为Oxide TFT的栅极或源漏极，也可作为氧化物TFT的遮光层，本公开对此不作限定。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图10所示，每一子像素区域还包括与阳极搭接电极91电连接的发光器件L，上述由T1-T7组成的7T1C像素驱动电路用于驱动发光器件L发光。
在具体实施时，由于驱动晶体管用于输出稳定的电流以驱动发光器件发光，因此驱动晶体管的栅极电压稳定性至关重要，这样就需要降低驱动晶体管的栅极和存储电容之间的漏电流，因此为了降低驱动晶体管的栅极和存储电容之间的漏电流，在本公开实施例提供的上述阵列基板中，如图8和图10所示，第一初始化晶体管T1和第二数据写入晶体管T2均为双栅晶体管。具体地，第一初始化晶体管T1包括串联的第一初始化子晶体管T1 1和第二初始化子晶体管T1 2，第二数据写入晶体管T2包括串联的第一数据写入子晶体管T2 1和第二数据写入子晶体管T2 2。
需要说明的是，图8和图10所示的像素驱动电路驱动发光器件L发光的原理与现有技术相同，与现有技术的区别在于将存储电容Cst的电容极板71与屏蔽结构13制作成一体结构，即相当于在制作电容极板71时，改变构图工艺，增大电容极板71的图案，使增大的部分覆盖阳极搭接电极91和发光控制信号线EM的第一交叠区域DD，增大的部分即为屏蔽结构13，从而实现屏蔽阳极搭接电极91和发光控制信号线EM形成的寄生电容的作用，提高显示色度的均一性。
在具体实施时，阵列基板一般包括不同颜色的多个子像素区域，例如红色子像素、绿色子像素和蓝色子像素，在设置屏蔽结构时，不同颜色的子像素区域对应设置的屏蔽结构形状可以相同，也可以不同，或者有些颜色的子像素可以不设置屏蔽结构。具体地，屏蔽结构的设置位置可以根据实际需要进行设置。
基于同一发明构思，本公开实施例还提供了一种阵列基板的制作方法， 如图11所示，包括：
S1101、在衬底基板上形成第一金属层；其中，第一金属层包括发光控制信号线；
S1102、在形成有第一金属层的衬底基板上形成屏蔽结构；其中，屏蔽结构与第一金属层相互绝缘，且屏蔽结构耦接固定电位；
S1103、在形成有屏蔽结构的衬底基板上形成第二金属层；其中，屏蔽结构与第二金属层相互绝缘，第二金属层包括阳极搭接电极，阳极搭接电极和发光控制信号线具有第一交叠区域，屏蔽结构在衬底基板上的正投影至少覆盖第一交叠区域在衬底基板上的正投影。
本发明实施例提供的阵列基板的其制作方法，通过在第一金属层和第二金属层之间设置与第一金属层和第二金属层相互绝缘的屏蔽结构，且屏蔽结构耦接固定电位，这样屏蔽结构能够降低或消除发光控制信号线和阳极搭接电极之间的寄生电容，可以避免与阳极搭接电极电连接的阳极电压发生变化，从而提高显示色度的均一性。
在具体实施时，在本公开实施例提供的上述制作方法中，还包括：在第二金属层形成驱动电压信号线；
在形成第二金属层之前，还包括：在第一金属层背离衬底基板一侧形成第三金属层，第三金属层包括与驱动电压信号线电连接的电容极板；
通过一次构图工艺形成电容极板和屏蔽结构。这样，只需要在形成电容极板时改变原有的构图图形，即可通过一次构图工艺形成屏蔽结构与电容极板的图形，不用增加单独制备屏蔽结构的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
在具体实施时，在本公开实施例提供的上述制作方法中，在形成第二金属层之前，还包括：在第一金属层背离衬底基板一侧形成第三金属层，第三金属层包括初始化信号线；
通过一次构图工艺形成初始化信号线和屏蔽结构。这样，只需要在形成初始化信号线时改变原有的构图图形，即可通过一次构图工艺形成屏蔽结构 与初始化信号线的图形，不用增加单独制备屏蔽结构的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
具体地，本公开实施例提供的阵列基板的制作方法中屏蔽结构的实施原理参见前述阵列基板中的屏蔽结构的实施原理，在此不做赘述。
下面对本公开实施例提供的图8所示的阵列基板的制作方法进行说明，具体包括如下步骤：
(1)在衬底基板上制作有源层3的图形，在有源层3至少制作第一金属层5的图形，如图12A所示。
(2)在第一金属层5上制作第三金属层7的图形，并且通过一次构图工艺形成屏蔽结构13和电容极板71的图形，如图12B所示。
(3)在第三金属层7上制作第三绝缘层8的图形，如图12C所示。
(4)在第三绝缘层8上制作第二金属层9的图形，如图12D所示。
(5)在第二金属层9上制作第四绝缘层10的图形，如图12E所示。
(6)在第四绝缘层10上制作阳极11的图形，如图12F所示。
(7)在阳极11上制作像素定义层12的图形，如图8所示。
通过上述步骤(1)-(7)即可制得本公开实施例提供的图8所示的阵列基板。
需要说明的是，上述步骤(1)-(7)仅示意出主要膜层的制作示意图，当然还包括制作缓冲层2、第一绝缘层4、第二绝缘层6等其它膜层结构。
需要说明的是，在本公开实施例提供的上述阵列基板的制作方法中，可以采用构图工艺制作各膜层，具体地，该构图工艺可只包括光刻工艺，或，可以包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。在具体实施时，可根据本发明中所形成的结构选择相应的构图工艺。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述阵列基板。该显示面板解决问题的原理与前述阵列基板相 似，因此该显示面板的实施可以参见前述阵列基板的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的显示面板为有机发光显示面板。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述阵列基板相似，因此该显示装置的实施可以参见前述阵列基板的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为全面屏显示装置，或者也可以为柔性显示装置等，在此不作限定。
在具体实施时，本公开实施例提供的上述显示装置可以为如图13所示的全面屏的手机。当然，本公开实施例提供的上述显示装置也可以为平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本发明实施例提供的阵列基板及其制作方法、显示面板、显示装置，通过在第一金属层和第二金属层之间设置与第一金属层和第二金属层相互绝缘的屏蔽结构，且屏蔽结构耦接固定电位，这样屏蔽结构能够降低或消除发光控制信号线和阳极搭接电极之间的寄生电容，可以避免与阳极搭接电极电连接的阳极电压发生变化，从而提高显示色度的均一性。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    第一金属层，位于所述衬底基板上，所述第一金属层包括发光控制信号线；
    第二金属层，位于所述第一金属层背离所述衬底基板一侧，所述第二金属层包括阳极搭接电极，所述阳极搭接电极和所述发光控制信号线具有第一交叠区域；
    屏蔽结构，位于所述第一金属层和所述第二金属层之间，所述屏蔽结构与所述第一金属层、所述第二金属层相互绝缘，所述屏蔽结构在所述衬底基板上的正投影与所述第一交叠区域在所述衬底基板上的正投影至少部分覆盖，所述屏蔽结构耦接固定电位。
  2. 如权利要求1所述的阵列基板，其中，所述屏蔽结构在所述衬底基板上的正投影面积大于所述第一交叠区域在所述衬底基板上的正投影面积的50％。
  3. 如权利要求1所述的阵列基板，其中，还包括位于所述第一金属层和所述第二金属层之间的第三金属层，所述屏蔽结构位于所述第三金属层和所述第二金属层之间，所述屏蔽结构与所述第三金属层相互绝缘。
  4. 如权利要求1所述的阵列基板，其中，还包括位于所述第一金属层和所述第二金属层之间的第三金属层，所述屏蔽结构位于所述第三金属层和所述第一金属层之间，所述屏蔽结构与所述第三金属层相互绝缘。
  5. 如权利要求1所述的阵列基板，其中，还包括位于所述第一金属层和所述第二金属层之间的第三金属层，所述屏蔽结构位于所述第三金属层。
  6. 如权利要求5所述的阵列基板，其中，所述第二金属层还包括驱动电压信号线，所述第三金属层包括与所述驱动电压信号线电连接的电容极板；
    所述屏蔽结构与所述电容极板为一体结构。
  7. 如权利要求6所述的阵列基板，其中，所述第二金属层还包括与所述驱动电压信号线平行设置的数据信号线，所述电容极板和所述数据信号线具有第二交叠区域，沿所述数据信号线的延伸方向，所述第二交叠区域的宽度小于所述电容极板和所述数据信号线未交叠部分的宽度。
  8. 如权利要求5所述的阵列基板，其中，所述第三金属层包括初始化信号线，所述屏蔽结构与所述初始化信号线为一体结构。
  9. 如权利要求1所述的阵列基板，其中，还包括：位于所述第二金属层背离所述衬底基板一侧的绝缘层，以及位于所述绝缘层背离所述衬底基板一侧的阳极；所述阳极通过贯穿所述绝缘层的过孔与所述阳极搭接电极电连接。
  10. 如权利要求9所述的阵列基板，其中，所述阳极与所述阳极搭接电极具有第三交叠区域，所述第三交叠区域为倒角结构。
  11. 如权利要求5所述的阵列基板，其中，所述第二金属层还包括驱动电压信号线，所述第三金属层包括初始化信号线以及与所述驱动电压信号线电连接的电容极板；所述初始化信号线和所述发光控制信号线的延伸方向相同，所述驱动电压信号线和所述发光控制信号线的延伸方向相互交叉；
    所述阵列基板具有多个子像素区域，每一所述子像素区域包括：与所述发光控制信号线电连接的第一发光控制晶体管和第二发光控制晶体管，与所述初始化信号线电连接的第一初始化晶体管和第二初始化晶体管；
    所述第二发光控制晶体管和所述第二初始化晶体管均与所述阳极搭接电极电连接。
  12. 如权利要求11所述的阵列基板，其中，每一所述子像素区域还包括：第一数据写入晶体管，第二数据写入晶体管，驱动晶体管和存储电容；其中，
    所述第一数据写入晶体管的栅极和所述第二数据写入晶体管的栅极均与第一扫描线电连接，所述第一数据写入晶体管的第一极与数据信号线电连接，所述第一数据写入晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述第二数据写入晶体管的第一极与所述驱动晶体管的栅极电连接，所述第二数据写入晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述存储电容的第一极为所述电容极板，所述存储电容的第二极与所述驱动晶体管的栅极电连接；
    所述第一发光控制晶体管的栅极与所述发光控制信号线电连接，所述第一发光控制晶体管的第一极与所述驱动电压信号线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述第二发光控制晶体管的栅极与所述发光控制信号线电连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述阳极搭接电极电连接；
    所述第一初始化晶体管的栅极与第二扫描线电连接，所述第一初始化晶体管的第一极与所述初始化信号线电连接，所述第一初始化晶体管的第二极与所述驱动晶体管的栅极电连接；
    所述第二初始化晶体管的栅极与所述第二扫描线电连接，所述第二初始化晶体管的第一极与所述初始化信号线电连接，所述第二初始化晶体管的第二极与所述阳极搭接电极电连接。
  13. 一种显示面板，其中，包括如权利要求1-12任一项所述的阵列基板。
  14. 一种显示装置，其中，包括如权利要求13所述的显示面板。
  15. 一种阵列基板的制作方法，其中，包括：
    在衬底基板上形成第一金属层；其中，所述第一金属层包括发光控制信号线；
    在形成有所述第一金属层的衬底基板上形成屏蔽结构；其中，所述屏蔽结构与所述第一金属层相互绝缘，且所述屏蔽结构耦接固定电位；
    在形成有所述屏蔽结构的衬底基板上形成第二金属层；其中，所述屏蔽结构与所述第二金属层相互绝缘，所述第二金属层包括阳极搭接电极，所述阳极搭接电极和所述发光控制信号线具有第一交叠区域，所述屏蔽结构在所述衬底基板上的正投影至少覆盖所述第一交叠区域在所述衬底基板上的正投影。
  16. 如权利要求15所述的制作方法，其中，还包括：在所述第二金属层 形成驱动电压信号线；
    在形成所述第二金属层之前，还包括：在所述第一金属层背离所述衬底基板一侧形成第三金属层，所述第三金属层包括与所述驱动电压信号线电连接的电容极板；
    通过一次构图工艺形成所述电容极板和所述屏蔽结构。
  17. 如权利要求15所述的制作方法，其中，在形成所述第二金属层之前，还包括：在所述第一金属层背离所述衬底基板一侧形成第三金属层，所述第三金属层包括初始化信号线；
    通过一次构图工艺形成所述初始化信号线和所述屏蔽结构。
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