WO2019024565A1 - 布线结构及其制备方法、oled阵列基板以及显示装置 - Google Patents

布线结构及其制备方法、oled阵列基板以及显示装置 Download PDF

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Publication number
WO2019024565A1
WO2019024565A1 PCT/CN2018/086460 CN2018086460W WO2019024565A1 WO 2019024565 A1 WO2019024565 A1 WO 2019024565A1 CN 2018086460 W CN2018086460 W CN 2018086460W WO 2019024565 A1 WO2019024565 A1 WO 2019024565A1
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Prior art keywords
conductive pattern
pattern
sub
substrate
wiring structure
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PCT/CN2018/086460
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English (en)
French (fr)
Inventor
肖丽
玄明花
杨盛际
陈小川
王磊
付杰
卢鹏程
刘冬妮
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京东方科技集团股份有限公司
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Priority to US16/303,825 priority Critical patent/US10868103B2/en
Priority to EP18800457.6A priority patent/EP3664138A4/en
Priority to JP2018561612A priority patent/JP7156952B2/ja
Publication of WO2019024565A1 publication Critical patent/WO2019024565A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Definitions

  • Embodiments of the present disclosure relate to a wiring structure and a method of fabricating the same, an organic light emitting diode (OLED) array substrate, and a display device.
  • OLED organic light emitting diode
  • OLED Organic Light-Emitting Diode
  • PDAs personal digital assistants
  • the organic light emitting diode (OLED) array substrate includes a plurality of pixel units, and each of the pixel units may include a switching transistor, a driving transistor, and an OLED display device.
  • An OLED is a current-type light-emitting device that mainly includes an anode, a cathode, and a functional layer of an organic material.
  • the main working principle of OLED is that the organic material functional layer emits light by carrier injection and recombination driven by an electric field formed by the anode and the cathode.
  • a driving transistor electrically connected to an anode or a cathode of the OLED functions as a current limiting.
  • the resistivity of the electrode material of the driving transistor is too large or the resistance of the power supply trace is too large, a large voltage drop or voltage rise occurs. Moreover, the influence on the pixel units at different positions is different, thereby adversely affecting the uniformity of display.
  • At least one embodiment of the present disclosure provides a wiring structure including: a substrate including a first surface and a second surface opposite to each other; and the first disposed on the substrate a first conductive pattern on the surface and a second conductive pattern disposed on the second surface of the base substrate; wherein the first conductive pattern and the second conductive pattern pass through the base substrate The through hole pattern is connected.
  • the second conductive pattern includes a plurality of second sub-conductive patterns spaced apart from each other, the through-hole pattern includes a plurality of via holes, and the first conductive pattern And each of the second sub-conductive patterns is respectively connected through the through hole.
  • adjacent through holes are equally spaced.
  • the second sub-conductive pattern has a grid-like structure.
  • At least one embodiment of the present disclosure also provides an organic light emitting diode (OLED) array substrate including the wiring structure of any of the above.
  • OLED organic light emitting diode
  • the first conductive pattern and the second conductive pattern are configured as power supply traces of the OLED array substrate.
  • the array substrate includes an array of pixel structures, each of which is connected to the first conductive pattern.
  • At least one embodiment of the present disclosure further provides a display device comprising the organic light emitting diode (OLED) array substrate of any of the above.
  • OLED organic light emitting diode
  • the display device provided by at least one embodiment of the present disclosure further includes a driving circuit, the first conductive pattern is connected to the driving circuit, and the plurality of second sub-conductive patterns are respectively connected to the driving circuit.
  • At least one embodiment of the present disclosure further provides a method of fabricating a wiring structure, the method comprising: providing a substrate; forming a via pattern penetrating the substrate; forming a first surface on the substrate a conductive pattern; forming a second conductive pattern on the second surface of the base substrate; wherein the first conductive pattern and the second conductive pattern are connected by the via pattern.
  • the via pattern is formed by a laser irradiation method.
  • the preparation method provided by at least one embodiment of the present disclosure includes first forming the via pattern through the substrate, and then forming the first conductive pattern on the first surface of the substrate.
  • a preparation method provided by at least one embodiment of the present disclosure includes first forming the first conductive pattern on a first surface of the base substrate, and then forming the via pattern through the base substrate.
  • forming the via pattern includes forming a plurality of via holes.
  • the second conductive pattern includes a plurality of second sub-conductive patterns spaced apart from each other, and the first conductive pattern and each of the second sub-conductive patterns respectively pass The through holes are connected.
  • adjacent through holes are equally spaced.
  • the second sub-conductive pattern has a grid-like structure.
  • FIG. 1A-1B are schematic cross-sectional views of a wiring structure according to an embodiment of the present disclosure
  • FIG. 2 is a partial structural diagram of a wiring structure including a first surface according to an embodiment of the present disclosure
  • FIG. 3 is a partial structural diagram of a wiring structure including a first surface according to still another embodiment of the present disclosure
  • FIG. 4 is a partial structural diagram of a wiring structure including a second surface according to an embodiment of the present disclosure
  • FIG. 5 is a partial structural diagram of a wiring structure including a second surface according to still another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram showing a planar structure of an organic light emitting diode (OLED) array substrate according to an embodiment of the present disclosure
  • FIGS. 7A-7B are schematic diagrams of a 2T1C pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for fabricating a wiring structure according to an embodiment of the present disclosure.
  • 100-wiring structure 101, 201-substrate substrate; 102-first surface; 103-second surface; 104-first conductive pattern; 105-second conductive pattern; 1051, 1051a, 1051b, 1051c, 1051d- Two-substrate conductive pattern; 106-via pattern; 1061-via; 110-drive circuit layer; 202-power trace; 203-gate line; 204-data line; 205-pixel structure; 206-switch transistor; Driving transistor; 208-OLED device; 210-first via structure.
  • the wiring structure and the size of each pattern in the OLED array substrate of the embodiments of the present disclosure are generally on the order of micrometers or less in actual products, and for the sake of clarity, the dimensions of the structures in the drawings of the embodiments of the present disclosure are It is magnified and does not represent actual size and proportion unless explicitly stated otherwise.
  • the inventors have found that in the current structure of the OLED array substrate, the VDD trace or the VSS trace itself has a resistance, and when there is a current through the VDD trace or the VSS trace, the voltage drop on the VDD trace or the VSS trace The voltage rise on the LED will affect the illuminating current, which will cause a certain difference in the amplitude of the VDD signal or the VSS signal.
  • the voltage drop on the VDD trace or the voltage rise on the VSS trace affects Vds, so OLEDs in different positions
  • the current output by the sub-pixel will change due to the change of VDD voltage or VSS voltage, resulting in uneven display. Therefore, the VDD trace and the resistance of the VSS trace should be reduced as much as possible to reduce the voltage drop on the VDD trace.
  • the voltage on the VSS trace rises.
  • At least one embodiment of the present disclosure provides a wiring structure including: a substrate including a first surface and a second surface opposite to each other; and a first surface disposed on the first surface of the substrate And a conductive pattern and a second conductive pattern disposed on the second surface of the base substrate, the first conductive pattern and the second conductive pattern being connected by a through hole pattern penetrating the base substrate.
  • the first conductive pattern is a pattern of a VDD trace or a VSS trace, since the first conductive pattern and the second conductive pattern are connected by a via pattern penetrating through the substrate, such that The resistance of the VDD trace or the VSS trace can be reduced, so that the voltage drop on the VDD trace and the voltage rise on the VSS trace can be reduced, thereby improving display uniformity.
  • FIGS. 1A and 1B are schematic cross-sectional views of a wiring structure according to an embodiment of the present disclosure.
  • the wiring structure 100 includes: a base substrate 101 including first and second surfaces 102 and 103 facing each other; a first conductive pattern 104 disposed on the first surface 102 of the base substrate 101 and disposed on the substrate The second conductive pattern 105 on the second surface 103 of the 101, the first conductive pattern 104 and the second conductive pattern 105 are connected by a via pattern 106 penetrating the base substrate 101.
  • the base substrate 101 is an insulating substrate, and the material thereof may be glass, quartz, a resin material having a certain hardness, or other suitable material.
  • the material of the first conductive pattern 104 and the second conductive pattern 105 may be a copper-based metal, for example, copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum-titanium.
  • Alloy Cu/Mo/Ti
  • copper-molybdenum-tungsten alloy Cu/Mo/W
  • copper-molybdenum-niobium alloy Cu/Mo/Nb
  • chromium-based metal for example, chromium-molybdenum alloy (Cr/Mo ), chrome-titanium alloy (Cr/Ti), chromium-molybdenum-titanium alloy (Cr/Mo/Ti), etc. or other suitable conductive metal materials.
  • the resistance of the first conductive pattern 104 is greatly reduced as compared with the first conductive pattern 104 of the single-layer structure.
  • the first conductive pattern 104 is a mesh-like structure formed of metal wires (strips) that intersect each other, thereby forming a plurality of meshes, which can further reduce resistance.
  • the first conductive pattern 104 is a planar structure formed by a metal mesh (rather than a single strip or line), and when the planar first conductive pattern is applied to the display panel, the first can be reduced.
  • the voltage drop (IR drop) or voltage rise (IR rising) of the conductive pattern can reduce the energy consumption of the display panel.
  • the conductive pattern of the planar structure is to guide the electrical pattern to have a certain size and extension range in the width and length directions.
  • the second conductive pattern 105 includes a plurality of second sub-conductive patterns 1051 spaced apart from each other, and the via pattern 106 includes a plurality of vias 1061, and the first conductive patterns 104 and the respective second sub-conductors The patterns 1051 are respectively connected through the through holes 1061.
  • the via pattern 106 can be formed by a punching technique such as laser irradiation.
  • the energy of the laser irradiation is 700 to 900 mJ and the time is 6 to 10 seconds.
  • the energy of the laser irradiation is 800 mJ and the time is 10 seconds; in another example, the energy of the laser irradiation is 850 mJ, the time is 9 seconds.
  • a wiring structure as shown in FIG. 1B is used for a display substrate of a display device, such as a display substrate for an OLED display device, and a driving circuit layer 110 for driving an OLED pixel array is formed on one side of the second conductive pattern 105.
  • the first conductive pattern 104 and the second conductive pattern 105 may be configured as a cathode (for example, a common cathode) of the pixel array, an anode (for example, a common anode), one of power lines, and the like.
  • FIG. 2 is a partial structural schematic view of a wiring structure including a first surface according to an embodiment of the present disclosure.
  • the first conductive pattern 104 has a rectangular grid-like structure, and has an input end on each side of the rectangular grid-like structure, and the input ends are respectively connected to an IC or an FPC.
  • the via pattern 106 on the base substrate corresponds to a metal material of a rectangular grid-like structure rather than a mesh.
  • the via pattern 106 includes four through holes 1061 corresponding to the intersections of the horizontally intersecting metal lines (strips) on the first surface of the wiring structure, which ensures The first conductive pattern 104 and the subsequently formed second conductive pattern are in electrical communication.
  • the adjacent two through holes 1061 are equally spaced in the lateral direction and the longitudinal direction, and the equally spaced through holes can eliminate the problem that the input electrical signal difference caused by the inconsistency of the line length is large.
  • the electric signals input to the respective second sub-conducting patterns 1051 are more precisely controlled.
  • FIG. 3 is a schematic structural view of a further wiring structure including a first surface according to an embodiment of the present disclosure.
  • the number of the through holes 1061 included in the through hole pattern is eight. It should be noted that the number of the through holes 1061 is not limited to four in FIG. 2 and eight in FIG. It can also be 2, 3 or 5, etc. Of course, when the number of the via holes 1061 is one, the effect of reducing the electric resistance of the first conductive pattern can be achieved, but the effect of improving the uniformity of display is not remarkable.
  • eight through holes 1061 are formed to form eight connection channels, which can further reduce the electric resistance of the first conductive pattern.
  • the through holes 1061 may be non-equally spaced, and the through holes may be disposed only at positions corresponding to the metal wires (strips) in the lateral direction, or only at the metal wires corresponding to the longitudinal direction (strips) ) at the location.
  • the mesh structure is not limited to a rectangle, and may be a circle, a regular polygon, a trapezoid or an irregular polygon.
  • a grid-shaped first conductive pattern may be correspondingly arranged for each column of pixel structures (sub-pixels), so that a plurality of grid-shaped first conductive patterns may continue to be connected to form an integrated structure.
  • the area of the first conductive pattern can be made larger, thereby further reducing the voltage drop (IR drop) or the voltage rise (IR rising) of the first conductive pattern, and the uniformity of display can be improved when the wiring structure is used for a display panel. At the same time, reduce the power consumption of the display panel.
  • a plurality of pixel structures may be correspondingly disposed with a planar first conductive pattern, that is, the first conductive pattern corresponds to an area of the entire pixel structure.
  • FIG. 4 is a partial structural schematic view of a wiring structure including a second surface according to an embodiment of the present disclosure.
  • the structure of the second surface of the wiring structure in FIG. 4 may be combined with the structure of the first surface of the wiring structure in FIG. 2 to form a wiring structure.
  • the four second sub-conductive patterns 1051 (including 1051a, 1051b, 1051c, 1051d) are spaced apart from each other, that is, the four second sub-conductive patterns 1051 are not in electrical communication on the second surface of the wiring structure.
  • FIG. 4 is a partial structural schematic view of a wiring structure including a second surface according to an embodiment of the present disclosure.
  • the structure of the second surface of the wiring structure in FIG. 4 may be combined with the structure of the first surface of the wiring structure in FIG. 2 to form a wiring structure.
  • the four second sub-conductive patterns 1051 are spaced apart from each other, that is, the four second sub-conductive patterns 1051 are not in electrical communication on the second surface of the wiring structure.
  • each of the second sub-conductive patterns 1051 corresponds to at least one through hole 1061 penetrating through the substrate, such that each of the second sub-conductive patterns 1051 can pass through the through hole 1061 and the first conductive pattern respectively (not shown). ) Electrical connection.
  • FIG. 5 is a partial structural diagram of a wiring structure including a second surface according to an embodiment of the present disclosure.
  • the structure of the second surface of the wiring structure in FIG. 5 may be combined with the structure of the first surface of the wiring structure in FIG. 3 to form a wiring structure.
  • Each of the second sub-conductive patterns 1051 may correspond to the plurality of through holes 1061 at different positions. As shown in FIG. 5 , each of the second sub-conductive patterns 1051 corresponds to two through holes 1061 , and each of the second sub-conductive patterns 1051 The first conductive pattern is electrically connected at two different locations, which can further reduce the resistance of the first conductive pattern 104.
  • the second sub-conductive pattern 1051 has a grid-like structure, and the shapes of the second sub-conductive patterns 1051 may be the same or different.
  • the shape of the second sub-conductive pattern 1051 is not limited to a rectangle, and may also be a circular shape. Polygons, trapezoids, or irregular polygons.
  • the first conductive pattern 104 in FIG. 3 and the second sub-conductive patterns 1051 spaced apart from each other are respectively connected through the via hole 1061, so that the input voltage of one second sub-conductive pattern 1051 can be individually controlled to adjust the small area.
  • the voltage at which the conductive pattern 104 is connected to the second sub-conductive pattern 1051 is such that the voltage rise or voltage drop in the first conductive pattern 104 is substantially close to zero by separately controlling the voltage input in the small region.
  • the uniformity of display can be improved when the wiring structure is applied to a display panel.
  • an embodiment of the present disclosure provides a wiring structure connected to the driving circuit.
  • the first conductive pattern may be connected to the driving circuit through an input end, and each of the second sub-conductive patterns is respectively connected through a respective input end.
  • a wiring structure composed of a first conductive pattern of the first surface shown in FIG. 2 and a second sub-conductive pattern of the second surface shown in FIG. 4 is taken as an example, and is assumed to be input into the first conductive pattern 104.
  • the voltage value is V0, and the voltage at the junction of the first conductive pattern 104 and the second sub-conductive pattern 1051a is detected as V1'.
  • V0 is equal to or substantially equal to V1'
  • no voltage is applied to the second sub-conductive pattern 1051a
  • V0 If the difference from V1' is large, a voltage is applied to the second sub-conductive pattern 1051a such that V0 is equal to or substantially equal to V1', and a voltage is applied to the second sub-conductive pattern 1051a, for example, V1.
  • the voltages at the junctions of the first conductive pattern and the second sub-conductive pattern 1051b, the second sub-conductive pattern 1051c, and the second sub-conductive pattern 1051d are respectively detected as V2.
  • V0 is equal or substantially equal to V2', V3' or V4', no voltage is applied to the second sub-conducting pattern 1051b, the second sub-conducting pattern 1051c or the second sub-conducting pattern 1051d; If V0 differs greatly from V2', V3', and/or V4', it is necessary to apply a voltage to the second sub-conductive pattern 1051b, the second sub-conductive pattern 1051c, and/or the second sub-conductive pattern 1051d so that V0 and V2 ', V3' and/or V4' are equal or substantially equal, and voltages applied to the second sub-conductive pattern 1051b, the second sub-conductive pattern 1051c, and/or the second sub-conductive pattern 1051d may be, for example, V2, V3, and V4, respectively.
  • the second conductive pattern 105 having a grid-like structure formed on the second surface of the base substrate 101 may function as an electrostatic shield, thereby avoiding external
  • the static electricity interferes with the electrical signal of the first conductive pattern 104 disposed on the first surface 102 of the base substrate 101, and the occurrence of electrostatic breakdown can also be avoided.
  • the wiring structure can be applied to a machine light emitting diode (OLED) array substrate.
  • a thin film transistor liquid crystal display uses a stable voltage to control display brightness.
  • an OLED array substrate is driven by current, when the resistance of a power supply voltage trace (for example, VDD or VSS) is large. A large voltage drop will occur at VDD, or a large voltage rise will occur at VSS, which will result in uneven current and uneven display.
  • the connection structure formed by the first conductive pattern and the second conductive pattern in the present disclosure may be configured as a power supply trace in the OLED array substrate.
  • FIG. 6 is a schematic plan view of an organic light emitting diode (OLED) array substrate according to an embodiment of the present disclosure, as shown in FIG.
  • the organic light emitting diode (OLED) array substrate includes a substrate substrate 201, power traces 202, gate lines 203, and data lines 204 disposed on the first and second surfaces of the base substrate 201, and is disposed on the gate lines 203.
  • the pixel structure 205 in the area defined by the intersection of the data line 204, for example, the power supply line 202 is a connection structure formed by the first conductive pattern 104 and the second conductive pattern 105 in any one of the wiring structures in the first embodiment.
  • the first conductive pattern is a pattern formed by power traces connected to the power supply terminal in the organic light emitting diode (OLED) array substrate.
  • the first conductive pattern is configured as a power supply trace of the OLED array substrate, and the array substrate includes an array of pixel structures, each of which is connected to the first conductive pattern.
  • the pixel structure 205 includes a switching transistor 206, a driving transistor 207, and an OLED device 208, and the switching transistor 206 is connected to the gate line 203 and the data line 204.
  • the driving transistor 207 is connected to the switching transistor 206, the power supply line 202, and the OLED device 208;
  • the first conductive pattern 104 in the trace 202 is disposed under the pixel structure 205 and at least partially overlaps the pixel structure 205; an insulating layer is disposed between the first conductive pattern 104 and the pixel structure 205 in the power trace 202 (Fig.
  • a first via structure 210 is disposed in the insulating layer, and the first conductive pattern 104 in the power trace 202 is connected to the driving transistor 207 through the first via structure 210.
  • the positions of the switching transistor 206 and the driving transistor 207 are referred to the corresponding dashed box.
  • the second conductive pattern in the power trace 202 is connected to the first conductive pattern through a through hole penetrating through the base substrate 201.
  • pixel structure included in the array substrate of the embodiment of the present disclosure is not limited to the four shown, but may include more.
  • a storage capacitor is further included in each of the pixel structures, and the storage capacitor includes a first electrode and a second electrode disposed opposite to each other with a dielectric layer formed of an insulating material disposed therebetween.
  • the first electrode is connected to the gate of the driving transistor 207, and the second electrode is connected to the first conductive pattern 104.
  • the OLED array substrate includes a display area and a peripheral area other than the display area, wherein the display area is also referred to as an AA (Active Area) area, and is generally used to implement display, and the peripheral area can be used to set a driving circuit for packaging of the display panel, etc. .
  • AA Active Area
  • the above pixel structure, gate lines and data lines are all located in the display area.
  • the OLED array substrate may further include a detection compensation line connecting the pixel unit and the detection integrated circuit, and the detection compensation line may also be located in the display area.
  • the power supply line can be set to a wider area and the area where the driving transistor is located, and the area where the storage capacitor is located is perpendicular to the OLED array substrate. overlap.
  • a region of the power supply line (the connection structure formed by the first conductive pattern and the second conductive pattern) corresponding to the pixel structure, the gate line, and the data line may be provided with a hollow structure.
  • the size of the hollow structure corresponds to the size of the pixel structure, the gate line and the data line, and the size of the hollow structure is larger than the size of the mesh in the metal mesh.
  • the area corresponding to the power line and the pixel structure is set to a hollow structure mainly to prevent the use of a metal power line to affect the transmittance of the light, that is, a hollow structure in the corresponding area of the pixel structure can increase the transmittance of the light, and the incident.
  • the light is fully utilized; the area corresponding to the power line and the gate line and the data line is set to a hollow structure, mainly to prevent capacitance between the power line and the gate line and the data line.
  • the hollow structure may include a plurality of non-continuous sub-hollow structures (ie, a plurality of sub-hollow structures are spaced apart from each other), which is equivalent to dividing the power line into a plurality of connected regions, and the voltage drop of the power line can be greatly reduced. .
  • a color film layer may be disposed for the sub-pixel defining region, for example, for the red sub-pixel, the blue sub-pixel, and the green sub-pixel, by combining the white OLED device and the corresponding red color film layer, Blue color film layer and green color film layer are obtained.
  • the color film layer may be a filter or a light conversion layer (for example, a fluorescent layer).
  • a flat layer may be provided on the color film layer.
  • Figures 7A-7B are schematic diagrams of a 2T1C pixel circuit provided by an embodiment of the present disclosure.
  • the 2T1C pixel circuit includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cs.
  • the gate of the switching transistor T1 is connected to a gate line (scanning line) to receive a scan signal (Scan), for example, the source is connected to the data line to receive the data signal (Vdata), and the drain is connected to the gate of the driving transistor T2;
  • the source of the driving transistor T2 is connected to the first power terminal (Vdd, high voltage terminal), and the drain is connected to the positive terminal of the OLED;
  • one end of the storage capacitor Cs is connected to the drain of the switching transistor T1 and the gate of the driving transistor T2, and One end is connected to the source of the driving transistor T2 and the first power terminal;
  • the cathode of the OLED is connected to the second power terminal (Vss, low voltage terminal), for example, grounded.
  • the 2T1C pixel circuit is driven by controlling the brightness and darkness (gray scale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the scan signal Scan is applied through the gate line to turn on the switching transistor T1
  • the data voltage (Vdata) fed through the data line by the data driving circuit charges the storage capacitor Cs via the switching transistor T1, thereby storing the data voltage in the storage capacitor Cs.
  • the stored data voltage controls the degree of conduction of the driving transistor T2, thereby controlling the magnitude of the current flowing through the driving transistor to drive the OLED to emit light, that is, the current determines the gray level of the pixel illumination.
  • the switching transistor T1 is an N-type transistor and the driving transistor T2 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cs, but the connection mode thereof is slightly changed, and the driving transistor T2 is an N-type transistor.
  • the variation of the pixel circuit of FIG. 7B with respect to FIG. 7A includes that the positive terminal of the OLED is connected to the first power terminal (Vdd, high voltage terminal) and the negative terminal is connected to the drain of the driving transistor T2, the driving transistor The source of T2 is connected to the second power supply terminal (Vss, low voltage terminal), such as ground.
  • One end of the storage capacitor Cs is connected to the drain of the switching transistor T1 and the gate of the driving transistor T2, and the other end is connected to the source of the driving transistor T2 and the second power supply terminal.
  • the switching transistor T1 is not limited to an N-type transistor, and may be a P-type transistor, thereby controlling the polarity of a scan signal (Scan) that is turned on or off accordingly. Change it.
  • the first conductive pattern is a pattern formed by a signal line connected to the first power terminal in the organic light emitting diode (OLED) array substrate or the first conductive pattern is an organic light emitting diode (OLED) array substrate and a second A pattern formed by signal lines connected to the power supply terminal.
  • the pixel circuit may be 3T1C, 4T2C, etc., and may include a compensation transistor, a reset transistor, and the like in addition to the above-described switching transistor and the driving transistor, which are not limited herein.
  • At least one embodiment of the present disclosure further provides a display device including any of the above organic light emitting diode (OLED) array substrates, and further includes a gate driving circuit, a data driving circuit, a power source, and the like, and the gate lines are connected to the gate driving circuit.
  • the data line is connected to the data driving circuit, and the power wiring is connected to the power source.
  • the display device can be any product or component having an display function such as an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the organic light emitting diode (OLED) array substrate included in the display device provided by the embodiment of the present disclosure has the same structure as any of the above organic light emitting diode (OLED) array substrates, and the technical effects thereof are the same as the implementation principle, and details are not described herein again. It should be noted that, if necessary, it is not limited to the layer structure of the above-described organic light emitting diode (OLED) array substrate, and may include other layer structures.
  • the display device further includes a driving circuit, wherein the first conductive pattern is connected to the driving circuit, and the plurality of second sub-conductive patterns are respectively connected to the driving circuit.
  • the display device may adopt a bottom emission or a top emission mode, and may also adopt a two-sided emission mode.
  • FIG. 8 is a flowchart of a method for fabricating a wiring structure according to an embodiment of the present disclosure. As shown in FIG. 8, the method includes the following steps:
  • Step 101 Providing a substrate.
  • the base substrate is an insulating substrate, and the material thereof may be glass, quartz, a resin material having a certain hardness, or other suitable material.
  • Step 102 forming a via pattern extending through the substrate.
  • the through hole pattern is formed by a laser irradiation method
  • the laser irradiation energy is 700 to 900 mJ
  • the time is 6 to 10 seconds.
  • the laser irradiation energy is 800 mJ
  • the time is 7 seconds.
  • the laser is illuminated at 850 mJ for 9 seconds.
  • Step 103 Form a first conductive pattern on the first surface of the base substrate.
  • the first conductive pattern can be formed by a process of coating a photoresist, exposing, developing, etching, etc. by depositing a metal thin film. It can be understood that the first conductive pattern can enter the region of the via hole and adhere to The side wall of the through hole.
  • Step 104 forming a second conductive pattern on the second surface of the base substrate, wherein the first conductive pattern and the second conductive pattern are connected by the through hole pattern. It can be understood that the second conductive pattern can enter the area where the through hole is located. And adhered to the side wall of the through hole.
  • the first conductive pattern is formed by a process step of applying photoresist, exposure, development, etching, or the like.
  • the materials of the first conductive pattern and the second conductive pattern can be referred to the related description in the above embodiments, and details are not described herein again.
  • the order of the above steps 102 and 103 is not limited, and includes two modes.
  • the first way first forming a through-hole pattern through the substrate, and then forming a first conductive pattern on the first surface of the substrate, so as to ensure the integrity of the first conductive pattern and the reliability of the electrical connection;
  • the via pattern includes a via hole corresponding to the intersection of the horizontally intersecting metal lines (strips) on the first surface of the wiring structure, so that the first conductive pattern and the second conductive pattern can be ensured.
  • the adjacent through holes are equally spaced in the lateral direction and the longitudinal direction, and the equally spaced through holes can eliminate the problem of large difference in input electrical signals caused by inconsistent line lengths, and more precise control input to each second. The electrical signal of the sub-conductive pattern.
  • the number of the through holes included in the through hole pattern may be one, two, three, four, eight or more, which is not limited herein.
  • the through holes may be non-equally spaced, and the through holes may be provided only at positions corresponding to the metal wires (strips) in the lateral direction, or only at positions corresponding to the metal wires (strips) in the longitudinal direction.
  • the plurality of second sub-conductive patterns are spaced apart from each other, that is, the plurality of second sub-conductive patterns are not in electrical communication on the second surface of the wiring structure.
  • Each of the second sub-conductive patterns corresponds to at least one through hole penetrating through the substrate, such that each of the second sub-conductive patterns can be electrically connected to the first conductive pattern through the through holes, respectively.
  • each of the second sub-conductive patterns may correspond to a plurality of through holes at different positions, and each of the second sub-conductive patterns is electrically connected to the first conductive patterns at different positions, respectively, which may further reduce the first conductive The resistance of the pattern.
  • the second sub-conductive pattern has a grid-like structure, and the shapes of the second sub-conductive patterns may be the same or different.
  • the shape of the second sub-conductive pattern is not limited to a rectangle, and may also be a circular shape, a regular polygon, or a trapezoidal shape. Or irregular polygons, etc.
  • Embodiments of the present disclosure provide a wiring structure and a method of fabricating the same, an organic light emitting diode (OLED) array substrate, and a display device having at least one of the following beneficial effects:
  • the first conductive pattern and the second conductive pattern may be electrically connected to each other through the via pattern of the substrate substrate to reduce the resistance of the first conductive pattern, thereby reducing the The voltage drop across a conductive pattern.
  • the first conductive pattern and the second sub-conductive patterns spaced apart from each other are respectively connected through the via holes, so that the input voltage of one second sub-conductive pattern can be individually controlled. Adjust the voltage in a small area.
  • the second conductive pattern having the grid structure can function as an electrostatic shield, so that the external static electricity pair can be prevented from being disposed on the first surface of the base substrate.
  • the electrical signal of the first conductive pattern interferes, and the occurrence of electrostatic breakdown can also be avoided.
  • the value of the voltage rise or the voltage drop in the first conductive pattern is substantially close to zero by individually controlling the input voltage in the small region, thereby ensuring display. Uniformity.

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Abstract

一种布线结构及其制备方法、有机发光二极管(OLED)阵列基板以及显示装置，该布线结构(100)包括：衬底基板(101,201)，该衬底基板(101,201)包括彼此相对的第一表面(102)和第二表面(103)；设置在所述衬底基板(101,201)的所述第一表面(102)上的第一导电图案(104)和设置在所述衬底基板(101,201)的所述第二表面(103)上的第二导电图案(105)；其中，所述第一导电图案(104)和所述第二导电图案(105)通过贯穿所述衬底基板(101,201)的通孔图案(106)连接。第一导电图案(104)和第二导电图案(105)通过贯穿衬底基板(101,201)的通孔图案(106)连接可以减小第一导电图案(104)的电阻，将该布线结构(100)应用于有机发光二极管(OLED)阵列基板中时，可以改善显示的均一性。

Description

布线结构及其制备方法、OLED阵列基板以及显示装置
本申请要求于2017年8月2日递交的中国专利申请第201710650543.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种布线结构及其制备方法、有机发光二极管(OLED)阵列基板以及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)是一种采用电激发荧光体或磷光体有机化合物实现发光的器件。有机发光二极管(OLED)因其具有自发光、全固态、宽视角、响应快等诸多优点而被认为在显示领域中有着巨大的应用前景。有机发光二极管已被广泛地应用于手机、数码摄像机、个人数字助理(PDA)以及笔记本电脑中。
有机发光二极管(OLED)阵列基板包括多个像素单元，每个像素单元可以包括开关晶体管、驱动晶体管和OLED显示器件。OLED是电流型发光器件，其主要包括阳极、阴极以及有机材料功能层。OLED主要的工作原理是：有机材料功能层在阳极和阴极形成的电场的驱动下，通过载流子注入和复合而发光。与OLED的阳极或者阴极电连接的驱动晶体管起着限流的作用，如果驱动晶体管的电极材料的电阻率太大或者电源走线的电阻太大，则会出现很大的电压降或者电压升，而且对于不同位置处的像素单元的影响不同，从而对显示的均一性产生不利影响。
发明内容
本公开至少一实施例提供一种布线结构，该布线结构包括：衬底基板，所述衬底基板包括彼此相对的第一表面和第二表面；设置在所述衬底基板的所述第一表面上的第一导电图案和设置在所述衬底基板的所述第二表面上的第二导电图案；其中，所述第一导电图案和所述第二导电图案通过贯 穿所述衬底基板的通孔图案连接。
例如，在本公开至少一实施例提供的布线结构中，所述第二导电图案包括相互间隔的多个第二子导电图案，所述通孔图案包括多个通孔，所述第一导电图案与各个所述第二子导电图案分别通过所述通孔连接。
例如，在本公开至少一实施例提供的布线结构中，相邻的所述通孔等间距排列。
例如，在本公开至少一实施例提供的布线结构中，所述第二子导电图案具有网格状结构。
本公开至少一实施例还提供一种有机发光二极管(OLED)阵列基板，其包括上述任一所述的布线结构。
例如，在本公开至少一实施例提供的OLED阵列基板中，所述第一导电图案和所述第二导电图案被配置为所述OLED阵列基板的电源走线。
例如，在本公开至少一实施例提供的OLED阵列基板中，所述阵列基板包括阵列设置的像素结构，每个所述像素结构均与所述第一导电图案连接。
本公开至少一实施例还提供一种显示装置，包括上述任一所述的有机发光二极管(OLED)阵列基板。
例如，本公开至少一实施例提供的显示装置，还包括驱动电路，所述第一导电图案连接至所述驱动电路，所述多个第二子导电图案分别连接至所述驱动电路。
本公开至少一实施例还提供一种布线结构的制备方法，该制备方法包括：提供衬底基板；形成贯穿所述衬底基板的通孔图案；在所述衬底基板的第一表面形成第一导电图案；在所述衬底基板的第二表面形成第二导电图案；其中，所述第一导电图案和所述第二导电图案通过所述通孔图案连接。
例如，在本公开至少一实施例提供的制备方法中，通过激光照射的方法形成所述通孔图案。
例如，本公开至少一实施例提供的制备方法包括：先形成贯穿所述衬底基板的所述通孔图案，然后在所述衬底基板的第一表面上形成所述第一导电图案。
例如，本公开至少一实施例提供的制备方法包括：先在所述衬底基板 的第一表面上形成所述第一导电图案，然后形成贯穿所述衬底基板的所述通孔图案。
例如，在本公开至少一实施例提供的制备方法中，形成所述通孔图案包括形成多个通孔。
例如，在本公开至少一实施例提供的制备方法中，所述第二导电图案包括相互间隔的多个第二子导电图案，所述第一导电图案与各个所述第二子导电图案分别通过所述通孔连接。
例如，在本公开至少一实施例提供的制备方法中，相邻的所述通孔等间距排列。
例如，在本公开至少一实施例提供的制备方法中，所述第二子导电图案具有网格状结构。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A-1B为本公开一实施例提供的一种布线结构的截面结构示意图；
图2为本公开一实施例提供的一种布线结构的包括第一表面的部分结构示意图；
图3为本公开再一实施例提供的一种布线结构的包括第一表面的部分结构示意图；
图4为本公开一实施例提供的一种布线结构的包括第二表面的部分结构示意图；
图5为本公开再一实施例提供的一种布线结构的包括第二表面的部分结构示意图；
图6为本公开一实施例提供的一种有机发光二极管(OLED)阵列基板的平面结构示意图；
图7A-7B为本公开一实施例提供的2T1C像素电路的示意图；以及
图8为本公开一实施例提供的一种布线结构的制备方法的流程图。
附图标记：
100-布线结构；101，201-衬底基板；102-第一表面；103-第二表面； 104-第一导电图案；105-第二导电图案；1051，1051a,1051b，1051c,1051d-第二子导电图案；106-通孔图案；1061-通孔；110-驱动电路层；202-电源走线；203-栅线；204-数据线；205-像素结构；206-开关晶体管；207-驱动晶体管；208-OLED器件；210-第一过孔结构。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的实施例所涉及的布线结构以及OLED阵列基板中各图案的尺寸在实际产品中通常为微米或更小量级，为了清楚起见，本公开的实施例的附图中各结构的尺寸均被放大，除非另有明确说明，不代表实际尺寸与比例。
发明人研究发现，在目前的OLED阵列基板的结构中，VDD走线或者VSS走线自身具有电阻，当有电流通过VDD走线或者VSS走线时，VDD走线上的电压降或者VSS走线上的电压升会对发光电流产生影响，这样会导致VDD信号或者VSS信号的幅值有一定的差异。考虑到薄膜晶体管(TFT)的特性并非理想(饱和区电流不仅和Vgs有关，还和Vds有关)，VDD走线上的电压降或者VSS走线上的电压升会影响Vds，因此不同位置的OLED子像素输出的电流会因为VDD电压或者VSS电压的变化而变 化，从而造成显示不均匀，所以要尽量地减小VDD走线以及VSS走线的电阻，进而减小VDD走线上的电压降以及VSS走线上的电压升。
本公开至少一实施例提供一种布线结构，该布线结构包括：衬底基板，该衬底基板包括彼此相对的第一表面和第二表面；设置在衬底基板的第一表面上的第一导电图案和设置在衬底基板的第二表面上的第二导电图案，该第一导电图案和第二导电图案通过贯穿衬底基板的通孔图案连接。
将该布线结构应用于OLED阵列基板中时，第一导电图案即为VDD走线或者VSS走线的图案，由于第一导电图案和第二导电图案通过贯穿衬底基板的通孔图案连接，这样可以减小VDD走线或者VSS走线的电阻，从而可以减小VDD走线上的电压降以及VSS走线上的电压升，进而可以改善显示的均一性。
本公开至少一实施例提供一种布线结构，例如，图1A和1B为本公开的一个实施例提供的一种布线结构的截面结构示意图，如图1A和1B所示，该布线结构100包括：衬底基板101，该衬底基板101包括彼此相对的第一表面102和第二表面103；设置在该衬底基板101的第一表面102上的第一导电图案104和设置在该衬底基板101的第二表面103上的第二导电图案105，该第一导电图案104和该第二导电图案105通过贯穿衬底基板101的通孔图案106连接。
例如，该衬底基板101是绝缘基板，其材料可以是玻璃、石英、具有一定硬度的树脂材料或其他适合的材料。
例如，该第一导电图案104和第二导电图案105的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等或者其他适合的导电金属材料。
例如，相较于单层结构的第一导电图案104，第一导电图案104和第二导电图案105连接形成双层结构后，第一导电图案104的电阻会大大地减小。
例如，第一导电图案104为由相互交叉的金属线(条)形成的网格状结构，由此形成多个网孔，该网格状结构可以进一步地减小电阻。
例如，该第一导电图案104为由金属网格形成的面状结构(而非单个 条状或线状)，将该面状的第一导电图案应用于显示面板中时，可以减小第一导电图案的电压降(IR drop)或者电压升(IR rising)，从而可以降低显示面板的能耗。需要说明的是，面状结构的导电图案是指导电图案在宽度和长度方向上均有一定的尺寸和延伸范围。
例如，如图1A和1B所示，第二导电图案105包括相互间隔的多个第二子导电图案1051，通孔图案106包括多个通孔1061，第一导电图案104与各个第二子导电图案1051分别通过通孔1061连接。
例如，可以通过激光照射等打孔技术形成通孔图案106。例如，激光照射的能量为700～900mJ，时间为6～10秒，在一个示例中，激光照射的能量为800mJ，时间为10秒；在另一个示例中，激光照射的能量为850mJ，时间为9秒。
例如，如图1B所示的布线结构用于显示装置的显示基板，例如用于OLED显示装置的显示基板，在第二导电图案105一侧形成用于驱动OLED像素阵列的驱动电路层110。此时，第一导电图案104和第二导电图案105可以被配置为像素阵列的阴极(例如公共阴极)、阳极(例如公共阳极)、电源线中的一种等。
例如，图2为本公开的实施例提供的一种布线结构的包括第一表面的部分结构示意图。如图2所示，该第一导电图案104为矩形的网格状结构，在该矩形的网格状结构的两侧分别有一个输入端，该输入端分别与IC或FPC相连。衬底基板上的通孔图案106与矩形的网格状结构的金属材料而非网孔相对应。如图2所示，该通孔图案106包括4个通孔1061，该4个通孔1061分别对应于布线结构的第一表面上横纵交叉的金属线(条)的交汇处，这样可以确保第一导电图案104和后续形成的第二导电图案电连通。例如，如图2所示，相邻的两个通孔1061在横向和纵向上的间距相等，等间距设置的通孔可以排除线路长短不一致带来的输入的电信号差异较大的问题，以更精确的控制输入至各个第二子导电图案1051上的电信号。
例如，图3为本公开的实施例提供的再一种布线结构的包括第一表面的结构示意图。如图3所示，该通孔图案包括的通孔1061的个数为8个，需要说明的是，该通孔1061的个数不限于图2中的4个和图3中的8个，还可以是2个、3个或者5个等。当然，通孔1061的个数为1个时也可以达到减小第一导电图案的电阻的效果，但在提高显示的均一性上效果不明 显。
例如，在图3所示的结构中，形成有8个通孔1061从而形成8个连接通道，这样可以进一步地减小第一导电图案的电阻。例如，如图3所示，通孔1061可以是非等间距分布的，通孔还可以仅设置在对应于横向的金属线(条)的位置处，或者仅设置在对应于纵向的金属线(条)的位置处。
需要说明的是，该网状结构不限于矩形，还可以是圆形、正多边形、梯形或者不规则多边形等。
例如，在一个示例中，可以为每一列像素结构(亚像素)对应设置一个网格状的第一导电图案，这样可以继续将多个网格状的第一导电图案相连以形成一体的结构，可以使得第一导电图案的面积更大，进而使得第一导电图案的电压降(IR drop)或者电压升(IR rising)进一步降低，将该布线结构用于显示面板时，可以提高显示的均一性，同时减少显示面板的功耗。
例如，在另一个示例中，还可以为多个像素结构(亚像素)对应设置一个面状的第一导电图案，即第一导电图案对应整个像素结构的区域。
例如，图4为本公开的实施例提供的一种布线结构的包括第二表面的部分结构示意图。图4中布线结构的第二表面的结构可以与图2中布线结构的第一表面的结构相结合以形成布线结构。如图4所示，4个第二子导电图案1051(包括1051a,1051b，1051c，1051d)相互间隔，即4个第二子导电图案1051在布线结构的第二表面上没有电连通。如图4所示，每个第二子导电图案1051都对应至少一个贯穿衬底基板的通孔1061，这样各个第二子导电图案1051可以分别通过通孔1061与第一导电图案(未示出)电连接。
例如，图5为本公开的实施例提供的一种布线结构的包括第二表面的部分结构示意图。图5中布线结构的第二表面的结构可以与图3中布线结构的第一表面的结构相结合以形成布线结构。各个第二子导电图案1051可以在不同的位置处对应多个通孔1061，如图5所示，每个第二子导电图案1051对应于两个通孔1061，每个第二子导电图案1051在两个不同的位置处与第一导电图案电连接，这样可以进一步地减小第一导电图案104的电阻。
例如，第二子导电图案1051具有网格状结构，各个第二子导电图案 1051的形状可以相同或者不同，例如，该第二子导电图案1051的形状不限于矩形，还可以是圆形、正多边形、梯形或者不规则多边形等。
例如，将图3中的第一导电图案104与相互间隔的各个第二子导电图案1051分别通过通孔1061连接，这样可以通过单独控制一个第二子导电图案1051的输入电压来调整小区域内第一导电图案104与一个第二子导电图案1051连接处的电压，这样通过单独控制小区域内输入的电压即可实现第一导电图案104中的电压升或者电压降的值基本接近于零。这样，将该布线结构应用于显示面板中时可以提高显示的均匀性。
在使用时，本公开一实施例提供的一种布线结构连接至驱动电路，例如，可以是第一导电图案通过输入端连接至驱动电路，每个第二子导电图案分别通过各自的输入端连接至驱动电路。以图2中所示的第一表面的第一导电图案和图4所示的第二表面的第二子导电图案相结合构成的布线结构为例加以说明，假定输入第一导电图案104中的电压值为V0，检测第一导电图案104和第二子导电图案1051a连接处的电压为V1’，如果V0与V1’相等或者基本相等，则不用对第二子导电图案1051a施加电压；如果V0与V1’相差较大，则需要对第二子导电图案1051a施加电压，以使V0与V1’相等或者基本相等，对第二子导电图案1051a施加电压例如为V1。
类似地，假定输入第一导电图案104中的电压值为V0，检测第一导电图案和第二子导电图案1051b、第二子导电图案1051c以及第二子导电图案1051d连接处的电压分别为V2’、V3’以及V4’，如果V0与V2’、V3’或者V4’相等或者基本相等，则不用对第二子导电图案1051b、第二子导电图案1051c或第二子导电图案1051d施加电压；如果V0与V2’、V3’和/或V4’相差较大，则需要对第二子导电图案1051b、第二子导电图案1051c和/或第二子导电图案1051d施加电压，以使V0与V2’、V3’和/或V4’相等或者基本相等，对第二子导电图案1051b、第二子导电图案1051c和/或第二子导电图案1051d施加电压例如可以分别为V2、V3以及V4。
除此之外，在布线结构的周边可能存在大量的静电，在衬底基板101的第二表面形成的具有网格状结构第二导电图案105可以起到静电屏蔽的作用，这样可以避免外界的静电对设置在衬底基板101的第一表面102上的第一导电图案104的电信号产生干扰，同时也可以避免静电击穿的发生。
例如，该布线结构可以应用于机发光二极管(OLED)阵列基板中。薄膜晶体管液晶显示器(TFT-LCD)利用稳定的电压来控制显示亮度，与TFT-LCD不同的是，OLED阵列基板属于电流驱动，当电源电压走线(例如，VDD或者VSS)的电阻较大时，会在VDD上产生较大的电压降，或者，在VSS上产生较大的电压升，这样会使得电流不均匀而导致显示不均匀。本公开中第一导电图案和第二导电图案形成的连接结构可以被配置为OLED阵列基板中的电源走线。
本公开至少一实施例还提供一有种机发光二极管(OLED)阵列基板，图6为本公开的实施例提供的一种有机发光二极管(OLED)阵列基板的平面结构示意图，如图6所示，该有机发光二极管(OLED)阵列基板包括衬底基板201、设置在衬底基板201的第一表面和第二表面上的电源走线202、栅线203和数据线204，设置在栅线203和数据线204交叉限定的区域内的像素结构205，例如，该电源走线202为实施例一中任意一种布线结构中的第一导电图案104和第二导电图案105形成的连接结构。第一导电图案为有机发光二极管(OLED)阵列基板中与电源端连接的电源走线构成的图案。
例如，第一导电图案被配置为OLED阵列基板的电源走线，阵列基板包括阵列设置的像素结构，每个像素结构均与第一导电图案连接。
该像素结构205包括开关晶体管206、驱动晶体管207和OLED器件208，且开关晶体管206连接到栅线203和数据线204，驱动晶体管207连接到开关晶体管206、电源走线202和OLED器件208；电源走线202中的第一导电图案104设置在像素结构205的下方且与像素结构205至少部分重叠；在电源走线202中的第一导电图案104与像素结构205之间设置有绝缘层(图1A和1B中未示出)，该绝缘层中设置有第一过孔结构210，电源走线202中的第一导电图案104通过第一过孔结构210与驱动晶体管207连接。开关晶体管206和驱动晶体管207的位置参见相应的虚线框。电源走线202中的第二导电图案通过贯穿衬底基板201的通孔与第一导电图案连接。
例如，图6中虽然仅示出了四个彼此并列的像素结构，且分别用于发出白光(W)、红光(R)、绿光(G)和蓝光(B)，但是本领的普通技术人员应该理解，本公开实施例的阵列基板所包括的像素结构不限于所示出 的四个，而是可以包括更多。
每个像素结构中还包括存储电容，该存储电容包括彼此相对设置的第一电极和第二电极，且二者之间设置有由绝缘材料形成的介电层。例如，第一电极与驱动晶体管207的栅极连接，而第二电极与第一导电图案104连接。
例如，该OLED阵列基板包括显示区域和显示区域之外的外围区域，其中显示区域又称为AA(Active Area)区，一般用于实现显示，外围区域可用于设置驱动电路进行显示面板的封装等。上述像素结构、栅线和数据线均位于显示区域。例如，在该OLED阵列基板中除了栅线、数据线等导线外，还可以包括连接像素单元与检测集成电路的检测补偿线，该检测补偿线也可以位于显示区域。
例如，考虑到栅线所在区域和驱动晶体管、存储电容的区域相距很近，可以将电源走线设置成更宽的区域与驱动晶体管所在区域、存储电容所在区域在垂直于OLED阵列基板的方向上交叠。
例如，在一个示例中，电源线(第一导电图案和第二导电图案形成的连接结构)的与像素结构、栅线和数据线对应的区域可以设置有镂空结构。需要说明的是，该镂空结构的尺寸与像素结构、栅线和数据线的尺寸相对应，该镂空结构的尺寸大于上述金属网格中网孔的尺寸。电源线与像素结构对应的区域设置成镂空结构主要是为了防止采用金属材质的电源线影响光线的透过率，即在像素结构对应的区域设置镂空结构可以增大光线的透过率，对入射光线进行充分的利用；电源线与栅线、数据线对应的区域设置成镂空结构，主要是为了防止电源线与栅线、数据线之间形成电容。镂空结构可以包括多个非连续的子镂空结构(即多个子镂空结构彼此间间隔开)，这样相当于把电源线分割成多个连接的区域，同样可以大幅度的减小电源线的电压降。
例如，在OLED阵列基板中，对于亚像素限定区还可以设置彩膜层，例如，对于红色亚像素、蓝色亚像素以及绿色亚像素，可以通过组合白光OLED器件以及相应的红色彩膜层、蓝色彩膜层以及绿色彩膜层得到。该彩膜层可以为滤光片或者光转换层(例如荧光层)。又例如，在彩膜层上还可以设置平坦层。
例如，图7A-7B为本公开的实施例提供的2T1C像素电路的示意图。 结合图6和图7A可以看出，该2T1C像素电路包括开关晶体管T1、驱动晶体管T2以及存储电容Cs。例如，该开关晶体管T1的栅极连接栅线(扫描线)以接收扫描信号(Scan)，例如源极连接到数据线以接收数据信号(Vdata)，漏极连接到驱动晶体管T2的栅极；驱动晶体管T2的源极连接到第一电源端(Vdd，高压端)，漏极连接到OLED的正极端；存储电容Cs的一端连接到开关晶体管T1的漏极以及驱动晶体管T2的栅极，另一端连接到驱动晶体管T2的源极以及第一电源端；OLED的负极连接到第二电源端(Vss，低压端)，例如接地。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过栅线施加扫描信号Scan以开启开关晶体管T1时，数据驱动电路通过数据线送入的数据电压(Vdata)将经由开关晶体管T1对存储电容Cs充电，由此将数据电压存储在存储电容Cs中，且此存储的数据电压控制驱动晶体管T2的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图7A所示的2T1C像素电路中，开关晶体管T1为N型晶体管而驱动晶体管T2为P型晶体管。
如图7B所示，又一种2T1C像素电路也包括开关晶体管T1、驱动晶体管T2以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管T2为N型晶体管。更具体而言，图7B的像素电路相对于图7A的变化之处包括：OLED的正极端连接到第一电源端(Vdd，高压端)而负极端连接到驱动晶体管T2的漏极，驱动晶体管T2的源极连接到第二电源端(Vss，低压端)，例如接地。存储电容Cs的一端连接到开关晶体管T1的漏极以及驱动晶体管T2的栅极，另一端连接到驱动晶体管T2的源极以及第二电源端。
此外，对于图7A和图7B所示的像素电路，开关晶体管T1不限于N型晶体管，也可以为P型晶体管，由此控制其导通或截止的扫描信号(Scan)的极性进行相应地改变即可。
可以理解的是，第一导电图案为有机发光二极管(OLED)阵列基板中与第一电源端连接的信号线构成的图案或者，第一导电图案为有机发光二极管(OLED)阵列基板中与第二电源端连接的信号线构成的图案。
例如，在本公开的实施例中，像素电路还可以为3T1C、4T2C等，除上述开关晶体管和驱动晶体管之外，还可以包括补偿晶体管、复位晶体管 等，在此不做限制。
本公开至少一实施例还提供一种显示装置，包括上述任一有机发光二极管(OLED)阵列基板，并且还可以包括栅极驱动电路、数据驱动电路以及电源等，栅线与栅极驱动电路连接，数据线与数据驱动电路连接，电源布线与电源连接。该显示装置可以为OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置所包括的有机发光二极管(OLED)阵列基板与上述任一有机发光二极管(OLED)阵列基板的结构相同，其技术效果与实现原理相同，在此不再赘述。需要说明的是，根据需要，不限于上述有机发光二极管(OLED)阵列基板的层结构，也可以包括其他的层结构。
该显示装置还包括驱动电路，其中，第一导电图案连接至驱动电路，多个第二子导电图案分别连接至驱动电路。
另外，该显示装置可以采用底发射或者顶发射模式，还可以采用两面发射模式。
本公开至少一实施例还提供一种布线结构的制备方法，图8为本公开的实施例提供的布线结构的制备方法的流程图，如图8所示，该制备方法包括如下步骤：
步骤101、提供衬底基板。
例如，该衬底基板是绝缘基板，其材料可以是玻璃、石英、具有一定硬度的树脂材料或其他适合的材料。
步骤102、形成贯穿该衬底基板的通孔图案。
例如，通过激光照射的方法形成所述通孔图案，该激光照射的能量为700～900mJ，时间为6～10秒，在一个示例中，激光照射的能量为800mJ，时间为7秒，在另一个示例中，激光照射的能量为850mJ，时间为9秒。
步骤103、在该衬底基板的第一表面形成第一导电图案。
例如，可以通过沉积金属薄膜，在通过涂覆光刻胶、曝光、显影、刻蚀等工艺步骤形成第一导电图案，可以理解的是，第一导电图案能够进入通孔所在区域并粘附在通孔的侧壁。
步骤104、在该衬底基板的第二表面形成第二导电图案，该第一导电 图案和第二导电图案通过该通孔图案连接，可以理解的是，第二导电图案能够进入通孔所在区域并粘附在通孔的侧壁。
例如，通过涂覆光刻胶、曝光、显影、刻蚀等工艺步骤形成第一导电图案。
例如，第一导电图案和第二导电图案的材料可以参见上述实施例中的相关描述，在此不再赘述。
例如，上述步骤102和步骤103的先后顺序不限，包含两种方式。第一种方式：先形成贯穿衬底基板的通孔图案，然后在衬底基板的第一表面上形成第一导电图案，这样可以保证第一导电图案的完整性以及电连接的可靠性；第二种方式：先在衬底基板的第一表面上形成第一导电图案，再形成只贯穿衬底基板的通孔图案，这样可以确保形成的通孔图案是位于第一导电图案上的，可以确保激光打孔的定位精准。
例如，该通孔图案包括个通孔，多个通孔分别对应于布线结构的第一表面上横纵交叉的金属线(条)的交汇处，这样可以确保第一导电图案和第二导电图案连通。例如，相邻的通孔在横向和纵向上的间距相等，等间距设置的通孔可以排除线路长短不一致带来的输入的电信号差异较大的问题，以更精确的控制输入至各个第二子导电图案的电信号。
例如，该通孔图案包括的通孔的个数可以为1个、2个、3个、4个、8个或更多个，在此不作限定。
例如，通孔的个数越多形成的连接的通道越多，这样可以进一步地减小第一导电图案的电阻。例如，通孔可以是非等间距分布的，通孔可以仅设置在对应于横向的金属线(条)的位置处，或者仅设置在对应于纵向的金属线(条)的位置处。
例如，多个第二子导电图案相互间隔，即多个第二子导电图案在布线结构的第二表面上没有电连通。每个第二子导电图案都对应至少一个贯穿衬底基板的通孔，这样各个第二子导电图案可以分别通过通孔与第一导电图案电连接。例如，各个第二子导电图案可以在不同的位置处对应多个通孔，每个第二子导电图案在不同的位置处分别与第一导电图案电连接，这样可以进一步地减小第一导电图案的电阻。
例如，第二子导电图案具有网格状结构，各个第二子导电图案的形状可以相同或者不同，例如，该第二子导电图案的形状不限于矩形，还可以 是圆形、正多边形、梯形或者不规则多边形等。
本公开的实施例提供一种布线结构及其制备方法、有机发光二极管(OLED)阵列基板以及显示装置具有以下至少一项有益效果：
(1)在本公开至少一实施例提供的布线结构中，第一导电图案和第二导电图通过贯穿衬底基板的通孔图案电连接可以减小第一导电图案的电阻，从而减小第一导电图案上的电压降。
(2)在本公开至少一实施例提供的布线结构中，第一导电图案与相互间隔的各个第二子导电图案分别通过通孔连接，这样可以单独控制一个第二子导电图案的输入电压来调整小区域内的电压。
(3)在本公开至少一实施例提供的布线结构中，具有网格状结构第二导电图案可以起到静电屏蔽的作用，这样可以避免外界的静电对设置在衬底基板的第一表面上的第一导电图案的电信号进行干扰，同时也可以避免静电击穿的发生。
(4)在本公开至少一实施例提供的OLED阵列基板中，通过单独控制小区域中的输入电压即可实现第一导电图案中的电压升或者电压降的值基本接近于零，从而保证显示的均一性。
有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开的实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种有机发光二极管(OLED)阵列基板，包括：
    衬底基板，包括彼此相对的第一表面和第二表面；
    设置在所述衬底基板的所述第一表面上的第一导电图案和设置在所述衬底基板的所述第二表面上的第二导电图案；
    其中，所述第一导电图案和所述第二导电图案通过贯穿所述衬底基板的通孔图案连接；
    所述第一导电图案和所述第二导电图案被配置为所述OLED阵列基板的电源走线。
  2. 根据权利要求1所述的有机发光二极管(OLED)阵列基板，其中，所述OLED阵列基板包括阵列设置的像素结构，每个所述像素结构均与所述第一导电图案连接。
  3. 根据权利要求1或2任一项所述的有机发光二极管(OLED)阵列基板，其中，所述第二导电图案包括相互间隔的多个第二子导电图案，所述通孔图案包括多个通孔，所述第一导电图案与各个所述第二子导电图案分别通过所述通孔连接。
  4. 根据权利要求3所述的布线结构，其中，相邻的所述通孔等间距排列。
  5. 根据权利要求3或4任一项所述的布线结构，其中，所述第二子导电图案具有网格状结构。
  6. 一种显示装置，包括权利要求1-5中任一项所述的有机发光二极管(OLED)阵列基板。
  7. 根据权利要求6所述的显示装置，还包括驱动电路，其中，所述第一导电图案连接至所述驱动电路，所述多个第二子导电图案分别连接至所述驱动电路。
  8. 一种布线结构，包括：
    衬底基板，包括彼此相对的第一表面和第二表面；
    设置在所述衬底基板的所述第一表面上的第一导电图案和设置在所述衬底基板的所述第二表面上的第二导电图案；
    其中，所述第一导电图案和所述第二导电图案通过贯穿所述衬底基板 的通孔图案连接。
  9. 根据权利要求8所述的布线结构，其中，所述第二导电图案包括相互间隔的多个第二子导电图案，所述通孔图案包括多个通孔，所述第一导电图案与各个所述第二子导电图案分别通过所述通孔连接。
  10. 根据权利要求9所述的布线结构，其中，相邻的所述通孔等间距排列。
  11. 根据权利要求9或10所述的布线结构，其中，所述第二子导电图案具有网格状结构。
  12. 一种布线结构的制备方法，包括：
    提供衬底基板；
    形成贯穿所述衬底基板的通孔图案；
    在所述衬底基板的第一表面形成第一导电图案；
    在所述衬底基板的第二表面形成第二导电图案；其中，
    所述第一导电图案和所述第二导电图案通过所述通孔图案连接。
  13. 根据权利要求12所述的制备方法，其中，通过激光照射的方法形成所述通孔图案。
  14. 根据权利要求12或13所述的制备方法，包括：先形成贯穿所述衬底基板的所述通孔图案，然后在所述衬底基板的第一表面上形成所述第一导电图案。
  15. 根据权利要求12或13所述的制备方法，包括：先在所述衬底基板的第一表面上形成所述第一导电图案，然后形成贯穿所述衬底基板的所述通孔图案。
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