WO2019227943A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2019227943A1
WO2019227943A1 PCT/CN2019/071409 CN2019071409W WO2019227943A1 WO 2019227943 A1 WO2019227943 A1 WO 2019227943A1 CN 2019071409 W CN2019071409 W CN 2019071409W WO 2019227943 A1 WO2019227943 A1 WO 2019227943A1
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WIPO (PCT)
Prior art keywords
line
signal line
conductive
display panel
transistor
Prior art date
Application number
PCT/CN2019/071409
Other languages
English (en)
French (fr)
Inventor
许晨
郝学光
先建波
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2019570479A priority Critical patent/JP7359701B2/ja
Priority to EP19739193.1A priority patent/EP3806082A4/en
Priority to US16/480,493 priority patent/US11545088B2/en
Publication of WO2019227943A1 publication Critical patent/WO2019227943A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present disclosure relate to a display panel and a display device.
  • OLED Organic Light-Emitting Diode
  • Embodiments of the present disclosure provide a display panel and a display device.
  • the display panel can simultaneously improve display uniformity and resolution, thereby improving display quality of the display panel.
  • a substrate including a display area and a peripheral area located on at least one side of the display area
  • each pixel unit including a light emitting unit and a pixel circuit structure for providing a driving current to the light emitting unit, the light emitting unit being an electroluminescent element;
  • a functional signal line connected to the pixel circuit structure of each pixel unit and providing a common voltage signal for the pixel circuit structure
  • the first conductive structure is parallel to the functional signal line and is located on a different layer from the functional signal line.
  • the plurality of pixel units extend in a row direction and a column direction to form a plurality of rows of pixel units and a plurality of columns of pixel units
  • the functional signal line includes a first signal line extending in a first direction.
  • a signal line extends along a row of pixel units or a column of pixel units.
  • the functional signal line includes a second signal line extending in a second direction.
  • the second signal line is located in the peripheral area.
  • the second signal line is connected to the first signal line.
  • the second direction intersects the first direction.
  • the second signal line is connected to a signal input circuit.
  • the first conductive structure includes a first conductive line extending along a first direction, and the first conductive line extends along a row of pixel units or a column of pixel units.
  • the first conductive structure includes a second conductive line extending along a second direction, the second conductive line is located in the peripheral region, and the second conductive line is connected to the first conductive line.
  • the second conductive line and the first conductive line are located in different layers.
  • the display panel further includes an insulating layer located between the first conductive structure and the functional signal line, wherein the first conductive structure and the functional signal line pass between the first conductive structure and the functional signal line.
  • the vias of the insulation layer are connected.
  • the via includes at least one of a display area via located in the display area and a peripheral area via located in the peripheral area.
  • the first signal line and the first conductive line in a direction perpendicular to the substrate, have a first overlapping area, and the display area via is located in the first overlapping area.
  • the first signal line and the first conductive line are connected through the display area via.
  • the second signal line and the second conductive line in a direction perpendicular to the substrate, have a second overlapping area, and the peripheral area via is located in the second overlapping area.
  • the second signal line and the second conductive line are connected through the peripheral region via.
  • the number of vias in the display area is multiple, and at least one via in the display area is provided for each pixel unit.
  • the number of vias in the peripheral region is plural, and each of the vias in the peripheral region corresponds to a row of pixel units or a column of pixel units.
  • the first conductive line is connected to the first signal line through a transfer pattern, and the first conductive line and the transfer pattern are connected through a via hole passing through an insulating layer therebetween.
  • the transfer pattern and the first signal line are connected through a via hole penetrating through an insulating layer located therebetween.
  • each light-emitting unit includes a first electrode, the first electrodes of different light-emitting units are insulated from each other, the first conductive structure is on the same layer as the first electrode, and the first conductive line is in an adjacent row of pixels The cell or the adjacent first pixel electrodes extend in a gap.
  • the display panel further includes a gate line, a data line, a first power line, and a second power line.
  • the pixel circuit structure includes a storage capacitor, a driving transistor, a data writing transistor, and a threshold compensation transistor.
  • the storage capacitor The first pole of the capacitor is electrically connected to the first power line, and the second pole of the storage capacitor is electrically connected to the second pole of the threshold compensation transistor through a first connection electrode;
  • the gate line is electrically connected, and a first pole and a second pole of the data writing transistor are electrically connected to the data line and the first pole of the driving transistor, respectively;
  • the gate of the threshold compensation transistor and the The gate line is electrically connected, and the first pole and the second pole of the threshold compensation transistor are electrically connected to the second pole and the gate of the driving transistor, respectively;
  • the second electrode of the light-emitting element is electrically connected to the second power line connection.
  • the first conductive line includes a first portion having a first width and a second portion having a second width, and the first width is smaller than the second width in a direction perpendicular to the substrate.
  • the second portion overlaps at least one of a channel region of the driving transistor, a channel region of the data writing transistor, and a channel region of the threshold compensation transistor.
  • the display panel further includes an initialization signal line, a light emission control signal line, and a reset control signal line
  • the pixel circuit structure further includes a first light emission control transistor, a second light emission control transistor, a first reset transistor, and a first Two reset transistors; a gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line, and a first pole and a second pole of the first light-emitting control transistor are respectively connected to the first power supply line and the The first electrode of the driving transistor is electrically connected; the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line, and the first and second electrodes of the second light-emitting control transistor are respectively connected to the driving transistor.
  • the second electrode of the light-emitting element is electrically connected; the gate of the first reset transistor is electrically connected to the reset control signal line, and the first and second electrodes of the first reset transistor are respectively Electrically connected to the initialization signal line and the gate of the driving transistor; the gate of the second reset transistor is electrically connected to the reset control signal line A first electrode of the second transistor and a second electrode respectively connected to a reset to the initialization signal line, and a first electrode of the light emitting element.
  • the pixel circuit structure further includes a first stabilization capacitor disposed between the data line and the first power supply line, the first stabilization capacitor includes a first capacitance electrode; the gate line, The gate of the driving transistor and the second pole of the storage capacitor are disposed on the same layer; the first capacitor electrode, the initialization signal line, and the first pole of the storage capacitor are disposed on the same layer; the data line, The first power supply line and the first connection electrode are disposed on the same layer; the first capacitor electrode and the data line overlap each other in a direction perpendicular to the substrate.
  • the function signal line includes at least one of an initialization signal line, a first power line, and a second power line.
  • the gate line, the light emission control signal line, and the reset control signal line are located on a first conductive pattern layer; the first signal line is located on a second conductive pattern layer; the data line, the The first power line and the second signal line are located in a third conductive pattern layer; the first electrode, the first conductive line, and the second conductive line are located in a fourth conductive pattern layer; the first signal line And the second signal line constitute the initialization signal line, and the first conductive line and the second conductive line constitute the first conductive structure.
  • the threshold compensation transistor and the first reset transistor are metal oxide semiconductor thin film transistors.
  • the display panel further includes a second conductive structure
  • the functional signal line is the initialization signal line
  • the second conductive structure is parallel to the first power supply line
  • the second conductive structure is located in the Between the third conductive pattern layer and the fourth conductive pattern layer.
  • the pixel circuit structure further includes at least one of a second stabilizing capacitor and a third stabilizing capacitor.
  • the second stabilizing capacitor is provided between the data line and the first pole of the driving transistor.
  • the third stabilizing capacitor is provided between the first power line and the first pole of the driving transistor.
  • An embodiment of the present disclosure further provides a display device including a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 1A is a schematic top view of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 1B is a schematic diagram of a pixel unit in a display panel provided by at least one embodiment of the present disclosure
  • 1C is a schematic diagram of a signal line for providing a signal to each pixel unit in a display panel provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic top view of a display panel provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view at M-N in FIG. 2;
  • 4A-4D are schematic top views of each of the four conductive pattern layers in FIG. 2;
  • FIG. 5 is a schematic diagram of connecting a functional signal line and a signal input circuit in a display panel according to an embodiment of the present disclosure
  • FIG. 6A is a schematic top view of a display panel according to another embodiment of the present disclosure.
  • 6B is a schematic sectional view at X-Y in FIG. 6A;
  • FIG. 7 is a schematic diagram of a fourth conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a first conductive line in a display panel according to an embodiment of the present disclosure
  • FIG. 9 is a schematic top plan view of a first signal line and a channel region of a thin film transistor in a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic plan view of a display panel according to an embodiment of the present disclosure.
  • FIG. 13 is a timing signal diagram of a pixel unit in a display panel according to an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 15 is a schematic plan view of a display panel according to an embodiment of the present disclosure.
  • FIG. 16 is a cross-sectional view of the display panel taken along a section line I-I 'in FIG. 15;
  • FIG. 17 is a cross-sectional view of the display panel in FIG. 15 along a section line II-II '.
  • the cause of uneven display is as follows:
  • the voltage input end of the wire has a more obvious IR drop effect than the voltage input start end, which easily causes signal delay problems and causes uneven display of the display panel.
  • increasing the wire size is a simple way to improve the display uniformity, but increasing the wire size is not conducive to the improvement of resolution.
  • the way to improve the resolution is to reduce the size of the circuit structure, such as reducing the line width, but reducing the line width will aggravate the display unevenness, and reducing the line width will also reduce the process yield.
  • the circuit structure of the OLED is more complicated than that of a liquid crystal display (LCD), and the space for improving the resolution is limited. Therefore, it is necessary to provide a new design to meet the requirements of high resolution and display uniformity.
  • a display panel provided by at least one embodiment of the present disclosure can simultaneously improve the display uniformity of the display panel and the resolution of the display panel.
  • FIG. 1A is a schematic top view of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel includes a substrate 200 and a plurality of pixel units 101.
  • the substrate 200 includes a display area 201 and a peripheral area 202 located on at least one side of the display area 201.
  • a plurality of pixel units 101 are located in the display area 201. It is shown in FIG. 1A that the peripheral area 202 is provided around the display area 201, but is not limited thereto.
  • the number and arrangement of the pixel units 101 are not limited to those shown in the figure.
  • FIG. 1B is a schematic diagram of a pixel unit in a display panel provided by at least one embodiment of the present disclosure.
  • each pixel unit 101 includes a light-emitting unit 20 and a pixel circuit structure 10 for providing a driving current to the light-emitting unit 20.
  • the light-emitting unit 20 may be an electroluminescent element, for example, an organic electroluminescent element, such as Organic light emitting diode (OLED).
  • OLED Organic light emitting diode
  • the driving principle of electroluminescence elements is as follows: electroluminescence elements are driven by current, and the magnitude of the current determines the display gray level. Therefore, under the control of the same driving signal between different pixels, the voltage drop of the functional signal lines of pixels at different positions is controlled. Different can cause current differences, and current differences can cause uneven display.
  • FIG. 1C is a schematic diagram of a signal line for providing a signal to each pixel unit in a display panel provided by at least one embodiment of the present disclosure.
  • a gate line 11, a data line 12, a first power line 13, a second power line 14, and an initialization signal line 16 are shown in FIG. 1C.
  • the gate line 11 is configured to provide a scanning signal Scan to the pixel circuit structure 10
  • the data line 12 is configured to provide a data signal Data to the pixel circuit structure 10
  • the first power line 13 is configured to provide a constant
  • the first voltage signal ELVDD and the second power line 14 are configured to provide the pixel circuit structure 10 with a constant second voltage signal ELVSS, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS.
  • the initialization signal line 16 is configured to provide an initialization signal Vint to the pixel circuit structure 10.
  • the initialization signal Vint is a constant voltage signal, and its magnitude may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto.
  • the initialization signal Vint may be less than or equal to the second voltage signal ELVSS.
  • signal lines such as the first power supply line 13, the second power supply line 14, and the initialization signal line 16 may have the aforementioned signal delay problem.
  • FIG. 2 is a schematic top view of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel also includes a function signal line 01.
  • the function signal line 01 is connected to the pixel circuit structure 10 of each pixel unit 101 and provides a common voltage signal to the pixel circuit structure 10.
  • the common voltage signal may be a constant voltage signal.
  • the display panel further includes a first conductive structure 02.
  • the first conductive structure 02 is connected in parallel with the functional signal line 01 and is located on a different layer from the functional signal line 01.
  • the arrangement of different layers of the first conductive structure 02 and the functional signal line may facilitate the two in parallel via a hole.
  • the first conductive structure 02 is connected in parallel with the functional signal line 01, which can reduce the resistance of the functional signal line, so that the signal delay problem caused by the resistance problem of the functional signal line is reduced.
  • the display panel provided in the embodiments of the present disclosure can help to improve both display uniformity and resolution, thereby improving display quality.
  • the plurality of pixel units 101 extend in the row direction and the column direction to form a plurality of row pixel units and a plurality of column pixel units.
  • Three rows and three columns of pixel units are shown in FIG. 2, and an embodiment of the present disclosure is described using this as an example.
  • the row direction is horizontal and the column direction is vertical.
  • the functional signal line 01 includes a first signal line 011 extending along a first direction D1, and the first signal line 011 extends along a row of pixel units.
  • the first signal line 011 is located in the display area 201.
  • the functional signal line 01 further includes a second signal line 012 extending along the second direction D2.
  • the second signal line 012 is located in the peripheral area 202.
  • the second signal line 012 and the first The signal line 011 is connected, and the second direction D2 crosses the first direction D1.
  • the second direction D2 is perpendicular to the first direction D1.
  • the first signal line 011 and the second signal line 012 are disposed in different layers, and are electrically connected through vias penetrating the insulating layer.
  • the first signal line 011 and the second signal line 012 may also be disposed on the same layer.
  • the first conductive structure 02 includes a first conductive line 021 extending along a first direction D1, and the first conductive line 021 extends along a row of pixel units.
  • the first conductive line 021 is located in the display area.
  • the first conductive structure 02 further includes a second conductive line 022 extending along the second direction D2.
  • the second conductive line 022 is located in the peripheral region 202.
  • a conductive wire 021 is connected.
  • the first conductive line 021 and the second conductive line 022 are disposed on the same layer.
  • the first conductive lines 021 and the second conductive lines 022 may also be disposed in different layers and electrically connected through vias penetrating the insulating layer.
  • An insulating layer may be provided between different conductive pattern layers.
  • the display panel further includes an insulating layer (not shown in the figure, refer to FIG. 3).
  • the insulating layer is located between the first conductive structure 02 and the functional signal line 01, and the first conductive structure 02 and the functional signal. Lines 01 are connected through vias V through the insulating layer.
  • the via hole V includes at least one of a display area via hole V1 located in a display area and a peripheral area via hole V2 located in a peripheral area.
  • the first signal line 011 and the first conductive line 021 have a first overlapping area OL1, and the display area via V1 is located in the first overlapping area OL1.
  • the line 011 and the first conductive line 021 are connected through the display area via V1.
  • the top view of the display panel can also be regarded as a direction perpendicular to the substrate 200.
  • a direction perpendicular to the substrate 200 may be in a thickness direction of the substrate 200 or a direction perpendicular to a main surface of the substrate 200.
  • the top view of the display panel is a view obtained by orthographic projection from above the display panel.
  • the number of via holes V1 in the display area is plural, and at least one display area via hole V1 is provided for each pixel unit 101.
  • the number of display area vias V1 may be at least the same as the number of pixel units.
  • the number of display area vias V1 may be at least twice (eg, twice) the number of pixel units.
  • the second signal line 012 and the second conductive line 022 have a second overlapping area OL2, and the peripheral region via V2 is located in the second overlapping area OL2.
  • the line 012 and the second conductive line 022 are connected through the peripheral region via V2.
  • the number of vias V2 in the peripheral region is multiple.
  • each of the plurality of peripheral region vias V2 corresponds to a row of pixel units.
  • the first conductive structure 02 and the functional signal line 01 are connected in parallel through the display area via V1 and the peripheral area via V2 as an example for description. It should be noted that the first conductive structure 02 and the functional signal line 01 may be connected in parallel only through the display area via V1, or the first conductive structure 02 and the functional signal line 01 may be connected in parallel only through the peripheral area via V2. In addition, the arrangement of the display area vias V1 and the peripheral area vias V2 is not limited to that shown in FIG. 2.
  • the first conductive line 021 may be connected through the transfer pattern 271 and the first signal line 011, and the first signal line 011 and the transfer pattern 271
  • the via pattern V11 is connected through the insulating layer therebetween, and the transfer pattern 271 and the first conductive line 021 are connected via the via hole V12 through the insulating layer therebetween (see also FIG. 3).
  • the transfer pattern 271 may not be provided, which is not limited in the embodiment of the present disclosure.
  • Fig. 3 is a schematic sectional view at M-N in Fig. 2.
  • the functional signal line 01 includes a first signal line 011 and a second signal line 012.
  • the first signal line 011 and the second signal line 012 are electrically connected through a via V0 passing through the interlayer insulating layer 26.
  • the second conductive line 022 and the second signal line 012 are electrically connected through a via V2 passing through the insulating layer 30 between the second conductive line 022 and the second signal line 012 (functional signal line 01).
  • the transition pattern 271 and the first signal line 011 are electrically connected through a via V11 located between the first signal line 011 and the transition pattern 271 through the interlayer insulation layer 26, and the second conductive line 021 and the transition
  • the pattern 271 is electrically connected through a via hole V12 passing through the insulating layer 30 between the second conductive line 021 and the transfer pattern 271.
  • FIG. 3 also shows the base substrate 200 and the buffer layer 28 thereon.
  • FIG. 3 also shows a first overlapping region OL1 and a second overlapping region OL2.
  • the display panel includes a first conductive pattern layer 23, a second conductive pattern layer 25, a third conductive pattern layer 27, and a fourth conductive pattern layer 29.
  • the first conductive pattern layer 23 includes a gate line 11, a light emission control signal line 15, and a reset control signal line 17.
  • the second conductive pattern layer 25 includes a first signal line 011.
  • the first signal line 011 and the gate line 11 extend in the same direction.
  • the plurality of first signal lines 011 are spaced from each other.
  • each first signal line 011 may correspond to a row of pixel units.
  • the third conductive pattern layer 27 includes a second signal line 012, a data line 12, a first power line 13, and a transfer pattern 271.
  • the second signal line 012 and the data line 12 extend in the same direction.
  • the data line 12 may correspond to a column of pixel units
  • the first power line 13 may correspond to a column of pixel units.
  • the fourth conductive pattern layer 29 includes a first conductive structure 02
  • the first conductive structure 02 includes a first conductive line 021 and a second conductive line 022 that are electrically connected.
  • the first conductive line 021 and the second conductive line 022 may be formed in the same layer.
  • the first conductive line 021 and the second conductive line 022 may also be electrically connected through vias penetrating through the insulating layer in different layers.
  • the first conductive line 021 is in the same layer as the first electrode 2001 (see FIG. 7)
  • the second conductive line 022 is in the same layer as the initialization signal line 16 in a peripheral region.
  • the functional signal line 01 in FIG. 2 may be the initialization signal line 16 in the pixel circuit structure.
  • the function signal line 01 may also be the first power line 13, which will be described in detail in FIG. 6A.
  • the initialization signal line 16 may include a portion located in the display area (which may correspond to the first signal line 011) and a portion located in the peripheral region (which may correspond to the second signal line 012).
  • FIG. 5 is a schematic diagram of connection of a functional signal line and a signal input circuit in a display panel according to an embodiment of the present disclosure.
  • the second signal line 012 is connected to the signal input circuit 80.
  • the second signal line 012 and the first signal line 011 are located on different layers and are connected through a via V2.
  • a portion of the function signal line 01 close to the signal input circuit 80 may be a voltage input end, and a portion of the function signal line 01 away from the signal input circuit 80 may be a voltage input end.
  • a conductive structure 02 is connected in parallel with the functional signal line 01, which can reduce the signal delay problem caused by the voltage drop effect between the voltage input end and the voltage input start end. At the same time, because the problem of signal delay can be reduced, it is not necessary to use a signal line with a larger width, which is conducive to improving the resolution of the display panel and thus improving the display quality.
  • FIG. 6A is a schematic top view of a display panel according to an embodiment of the present disclosure.
  • the first signal line 011 extends along a column of pixel units
  • the first conductive line 021 extends along a column of pixel units
  • each of the plurality of peripheral region vias V2 corresponds to a column of pixel units.
  • the second signal line 012 extends along a row of pixel units
  • the second conductive line 022 extends along a row of pixel units.
  • Fig. 6B is a schematic cross-sectional view at X-Y in Fig. 6A.
  • the first signal line 011 and the second signal line 012 are electrically connected through a via V0 passing through the interlayer insulating layer 26 therebetween to form a functional signal line 01.
  • the first conductive line 021 and the first signal line 011 are electrically connected through the display area via V1 of the insulating layer 30 penetrating therebetween.
  • the transfer pattern 272 and the second signal line 012 are electrically connected through a via hole V21 (peripheral region via hole V2) penetrating the interlayer insulating layer 26 therebetween.
  • the second conductive line 022 and the transfer pattern 272 are electrically connected through a via hole V22 (peripheral region via hole V2) penetrating the insulating layer 30 therebetween.
  • FIG. 7 is a schematic diagram of a fourth conductive pattern layer in a display panel according to an embodiment of the present disclosure.
  • each light-emitting unit for example, an organic electroluminescent diode
  • each light-emitting unit includes a first electrode 2001
  • the first electrodes 2001 of different light-emitting units are insulated from each other
  • the first conductive structure 02 is on the same layer as the first electrode 2001 .
  • the first conductive structure 02 includes first conductive lines 021 and second conductive lines 022 in the same layer and electrically connected.
  • FIG. 8 is a schematic diagram of a first conductive line in a display panel according to an embodiment of the present disclosure.
  • the first conductive line 021 extends in a gap between the first electrodes 2001 of the adjacent pixel units 101.
  • the first conductive line 021 may also extend in the gap between the first electrodes 2001 of the adjacent pixel units 101.
  • the first conductive line 021 and the second conductive line 022 are in different layers.
  • one of the first conductive line 021 and the second conductive line 022 may be disposed on the same layer as the first electrode 2001 and the other disposed on the same layer as the other conductive structures, but is not limited thereto.
  • FIG. 9 is a schematic top view of a first signal line and a channel region of a thin film transistor in a display panel according to an embodiment of the present disclosure.
  • the first conductive line 021 includes a first portion 0211 having a first width and a second portion 0212 having a second width.
  • the first width d1 is smaller than the second width d2.
  • the second portion 0212 may be At least one of the channel region T1a of the driving transistor, the channel region T2a of the data writing transistor, and the channel region T3a of the threshold compensation transistor overlap.
  • the driving transistor, the data writing transistor, and the threshold compensation transistor here can refer to the driving transistor T1, the data writing transistor T2, and the threshold compensation transistor T3 described below (for example, as shown in FIG. 11).
  • the channel region T1a of the driving transistor, the channel region T2a of the data writing transistor, and the channel region T3a of the threshold compensation transistor can also be referred to FIG. 15.
  • Using the second part of the first conductive line to shield the channel region of the thin film transistor can further improve the stability of the thin film transistor and reduce the leakage current.
  • the second portion 0212 overlaps with the channel region T1a of the driving transistor, the channel region T2a of the data writing transistor, and the channel region T3a of the threshold compensation transistor as an example.
  • the second portion 0212 may also overlap one or two of the channel region T1a of the driving transistor, the channel region T2a of the data writing transistor, and the channel region T3a of the threshold compensation transistor.
  • FIG. 10 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.
  • the display panel further includes a fifth conductive pattern layer 290.
  • the fifth conductive pattern layer 290 may be located between the third conductive pattern layer 27 and the fourth conductive pattern layer 29.
  • the fifth conductive pattern layer 290 may include a second conductive structure 03.
  • the functional signal line 01 is an initialization signal line 16, and the second conductive structure 03 and the first power line 13 are connected in parallel.
  • the second conductive structure 03 may be in a grid shape.
  • the fifth conductive pattern layer 290 may further include transfer patterns 2901 and 2902 to facilitate compatibility with the patterning process and reduce the difficulty of manufacturing vias.
  • An insulating layer 31 between the fifth conductive pattern layer 290 and the fourth conductive pattern layer 29 is also shown in FIG. 10.
  • the function signal line may be at least one of an initialization signal line, a first power line, and a second power line.
  • the above embodiments are described by using the function signal line as the initialization signal line and / or the first power line as an example. It should be noted that the embodiments of the present disclosure are not limited thereto, as long as the signal lines that provide a common voltage signal to the pixel circuit structure may be functional signal lines.
  • FIG. 11 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 12 is a schematic planar structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 100 includes a plurality of pixel units 101 arranged in a matrix.
  • Each pixel unit 101 includes a pixel circuit structure 10, a light emitting element 20, a gate line 11, a data line 12, and a voltage signal. line.
  • the light-emitting element 20 is an organic light-emitting element OLED, and the light-emitting element 20 emits red light, green light, blue light, or white light under the driving of the corresponding pixel circuit structure 10.
  • the voltage signal line may include one or a plurality of voltage signal lines.
  • the voltage signal line includes at least one of a first power line 13, a second power line 14, a light emission control signal line 15, an initialization signal line 16, a reset control signal line 17, and the like.
  • the first power line 13 is configured to provide the pixel circuit structure 10 with a constant first voltage signal ELVDD
  • the second power line 14 is configured to provide the pixel circuit structure 10 with a constant second voltage signal ELVSS
  • the first voltage signal ELVDD Greater than the second voltage signal ELVSS.
  • the light emission control signal line 15 is configured to provide a light emission control signal EM to the pixel circuit structure 10.
  • the initialization signal line 16 and the reset control signal line 17 are respectively configured to provide an initialization signal Vint and a reset control signal Reset to the pixel circuit structure 10, wherein the initialization signal Vint is a constant voltage signal, and its size can be, for example, between the first voltage signal ELVDD And the second voltage signal ELVSS, but is not limited thereto, for example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS.
  • the pixel circuit structure 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset The transistor T7 and the storage capacitor Cst.
  • the driving transistor T1 is electrically connected to the light emitting element 20 and outputs a driving current to control the light emitting element 20 to emit light under the control of the scanning signal Scan, the data signal Data, the first voltage signal ELVDD, and the second voltage signal ELVSS.
  • a driving transistor is connected to the organic light emitting element, and a driving current is output to the organic light emitting element under the control of signals such as data signals and scanning signals, thereby driving the organic light emitting element to emit light. Since the magnitude of the gate voltage of the driving transistor is directly related to the magnitude of the driving current in the organic light emitting element, the stability of the gate signal is an important factor for achieving the light emitting stability of the organic light emitting element and the display stability of the display panel.
  • the inventors found that when a data signal is transmitted on a data line, the fluctuation of the data signal is likely to cause interference with the gate signal of the driving transistor, such as a parasitic capacitance formed between the data signal and the gate of the driving transistor through the data line Causes interference to the gate signal, which affects the stability of the gate signal.
  • the pixel circuit structure 10 further includes a first stabilization capacitor C1 disposed between the data line 12 and the first power supply line 13.
  • the first stabilizing capacitor C1 can reduce the interference of the parasitic capacitance between the data line 12 and the gate of the driving transistor T1 on the gate signal of the driving transistor T1.
  • the capacitance value of the first stabilizing capacitor C1 can be designed to be more than 10 times larger than the parasitic capacitance between the data line 12 and the gate of the driving transistor T1.
  • the capacitance value of the parasitic capacitor is neglected compared with the first stable capacitor C1, the influence of the data signal Data on the gate signal through the parasitic capacitor can also be ignored.
  • the first stabilizing capacitor C1 can be set in various ways.
  • the first stable capacitor may include a first capacitor electrode and a second capacitor electrode.
  • the first capacitor electrode is electrically connected to the first power line 13 and the second capacitor electrode is electrically connected to the data line 12.
  • the first capacitor electrode may be a part of the first power source line 13 or an electrode which is separately provided and electrically connected to the first power source line 13. Both cases are included in the above-mentioned "first capacitor electrode and the first power source.” Wire electrical connection ".
  • the second capacitor electrode may be a part of the data line 12 or an electrode that is separately provided and electrically connected to the data line 12, both of which are included in the above-mentioned range of "the second capacitor electrode is electrically connected to the data line”.
  • a pixel circuit structure is prepared on a substrate of the display panel 100 through a semiconductor process, which includes a stacked circuit layer, an insulating layer, and the like.
  • the first capacitor electrode and the second capacitor electrode may overlap each other in a direction perpendicular to the substrate of the display panel 100 and are separated by an insulating layer (dielectric layer) therebetween, thereby constituting a capacitor.
  • the first stable capacitor C1 can be adjusted by designing the distance between the first capacitor electrode and the second capacitor electrode, the material of the insulating layer (that is, the dielectric constant) therebetween, and the overlap area between the two. Capacitance.
  • the first pole of the storage capacitor Cst is electrically connected to the first power line 13 and the second pole of the storage capacitor Cst is electrically connected to the second pole of the threshold compensation transistor T3.
  • the gate of the data writing transistor T2 is electrically connected to the gate line 11, and the first and second electrodes of the data writing transistor T2 are electrically connected to the data line 12 and the first electrode of the driving transistor T1, respectively.
  • the gate of the threshold compensation transistor T3 is electrically connected to the gate line 11, and the first and second electrodes of the threshold compensation transistor T3 are electrically connected to the second and gate of the driving transistor T1, respectively.
  • the gate of the first light-emitting control transistor T4 is electrically connected to the light-emitting control signal line 15, and the first and second electrodes of the first light-emitting control transistor T4 are respectively connected to the first power line 13 and the driving transistor T1.
  • the first pole is electrically connected.
  • the gate of the second light-emission control transistor T5 is electrically connected to the light-emission control signal line 15, and the first and second electrodes of the second light-emission control transistor T5 are electrically connected to the second electrode of the drive transistor T1 and the first electrode of the light-emitting element 20, respectively. connection.
  • the gate of the first reset transistor T6 is electrically connected to the reset control signal line 17, and the first and second electrodes of the first reset transistor T6 are electrically connected to the initialization signal line 16 and the gate of the drive transistor T1, respectively.
  • the gate of the second reset transistor T7 is electrically connected to the reset control signal line 17, and the first and second electrodes of the second reset transistor T7 are respectively connected to the initialization signal line 16 and the first electrode of the light emitting element 20 (may be an OLED pixel)
  • An electrode, such as an anode is electrically connected.
  • the second electrode (which may be a common electrode of the OLED, such as a cathode) of the light-emitting element 20 is electrically connected to the second power line 14.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the first poles of the transistors in the embodiments of the present disclosure are described. It is interchangeable with the second pole as required.
  • the first electrode of the transistor according to the embodiment of the present disclosure may be a source and the second electrode may be a drain; or, the first electrode of the transistor is a drain and the second electrode is a source.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • the embodiments of the present disclosure are described by using a P-type transistor as an example of the transistors. Based on the description and teaching of this implementation in the present disclosure, a person of ordinary skill in the art can easily think of using at least part of the transistors in the pixel circuit structure of the embodiments of the present disclosure as N-type transistors without creative work, that is, using N Implementations of N-type transistors or N-type transistors and P-type transistors, and therefore, these implementations are also within the scope of the present disclosure.
  • the active layer of the transistor used in the embodiments of the present disclosure may be single crystal silicon, polysilicon (such as low temperature polysilicon), or metal oxide semiconductor materials (such as IGZO, AZO, etc.).
  • the transistors are all P-type LTPS (low temperature polysilicon) thin film transistors.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (such as IGZO, AZO Etc.), the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.
  • the transistors used in the embodiments of the present disclosure may include various structures, such as a top-gate type, a bottom-gate type, or a double-gate structure.
  • the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are double-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.
  • the display panel 100 provided by the embodiment of the present disclosure further includes a data driver 102, a scan driver 103, and a controller 104.
  • the data driver 102 is configured to provide a data signal Data to the pixel unit 101 according to an instruction of the controller 104;
  • the scan driver 103 is configured to provide the pixel unit 101 with a light emission control signal EM, a scan signal Scan, and a reset control signal according to an instruction of the controller 104 Reset, etc.
  • the scan driver 103 is a GOA (Gate On Array) structure mounted on the display panel, or a driver chip (IC) structure that is bonded to the display panel.
  • GOA Gate On Array
  • the display panel 100 further includes a power source (not shown in the figure) to provide the above-mentioned voltage signal, which may be a voltage source or a current source as required.
  • the power source is configured to pass through the first power line 13 and the second power line 14 respectively.
  • the initialization signal line 16 provides the pixel unit 101 with a first power supply voltage ELVDD, a second power supply voltage ELVSS, an initialization signal Vint, and the like.
  • FIG. 13 is a timing signal diagram of a pixel unit in a display panel according to an embodiment of the present disclosure.
  • a driving method of one pixel unit in a display panel provided by an embodiment of the present disclosure will be described with reference to FIG. 13.
  • the driving method of the pixel unit includes a reset phase t1, a data writing and threshold compensation phase t2, and a light emitting phase t3.
  • the lighting control signal EM is set to the off voltage
  • the reset control signal Reset is set to the on voltage
  • the scan signal Scan is set to the off voltage.
  • the light emission control signal EM is set to the off voltage
  • the reset control signal Reset is set to the off voltage
  • the scan signal Scan is set to the on voltage.
  • the light-emitting control signal EM is set to the on voltage
  • the reset control signal Reset is set to the off voltage
  • the scan signal Scan is set to the off voltage.
  • the turn-on voltage in the embodiment of the present disclosure refers to a voltage that can turn on the first pole and the second stage of the corresponding transistor
  • the turn-off voltage refers to a voltage that can turn off the first pole and the second stage of the corresponding transistor.
  • the turn-on voltage is a low voltage (for example, 0V) and the turn-off voltage is a high voltage (for example, 5V);
  • the transistor is an N-type transistor, the turn-on voltage is a high voltage (for example, 5V), and it is turned off.
  • the voltage is a low voltage (for example, 0V).
  • the driving waveforms shown in FIG. 13 are all described by taking a P-type transistor as an example, that is, the turn-on voltage is a low voltage (for example, 0V), and the turn-off voltage is a high voltage (for example, 5V).
  • the light emission control signal EM is an off voltage
  • the reset control signal Reset is an on voltage
  • the scan signal Scan is an off voltage.
  • the first reset transistor T6 and the second reset transistor T7 are in an on state
  • the data write transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, and the second light emission control transistor T5 are in an off state.
  • the first reset transistor T6 transmits an initialization signal (initialization voltage) Vint to the gate of the driving transistor T1 and is stored by the storage capacitor Cst, resets the driving transistor T1 and erases data stored at the previous (previous frame) light emission, and the second The reset transistor T7 transmits an initialization signal Vint to the first electrode of the light emitting element 20 to reset the light emitting element 20.
  • the light emission control signal EM is an off voltage
  • the reset control signal Reset is an off voltage
  • the scan signal Scan is an on voltage.
  • the data writing transistor T2 and the threshold compensation transistor T3 are in an on state
  • the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7 are in an off state.
  • the data writing transistor T2 transmits the data signal voltage Vdata to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scanning signal Scan and the data signal Data and sends the scanning signal Scan to the first of the driving transistor T1 according to the scanning signal Scan.
  • the pole writes a data signal Data.
  • the threshold compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, so that the gate of the driving transistor T1 can be charged.
  • the gate voltage of the driving transistor T1 is Vdata + Vth, where Vdata is the data signal voltage and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scanning signal Scan and drives the driving signal according to the scanning signal Scan.
  • the gate voltage of the transistor T1 is subjected to threshold voltage compensation. At this stage, the voltage difference across the storage capacitor Cst is ELVDD-Vdata-Vth.
  • the light-emission control signal EM is the on-voltage
  • the reset control signal Reset is the off-voltage
  • the scan signal Scan is the off-voltage.
  • the first light emission control transistor T4 and the second light emission control transistor T5 are in an on state
  • the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are in an off state.
  • the first power signal ELVDD is transmitted to the first pole of the driving transistor T1 through the first light-emitting control transistor T4, the gate voltage of the driving transistor T1 is maintained at Vdata + Vth, and the light-emitting current I passes through the first light-emitting control transistor T4, the driving transistor T1, and
  • the second light emission control transistor T5 flows into the light emitting element 20, and the light emitting element 20 emits light. That is, the first light emission control transistor T4 and the second light emission control transistor T5 receive the light emission control signal EM, and control the light emitting element 20 to emit light in accordance with the light emission control signal EM.
  • the light-emitting current I satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the drive transistor
  • Cox is the channel capacitance per unit area of the drive transistor T1
  • W and L are the channel width and channel length of the drive transistor T1
  • Vgs is the gate and source of the drive transistor T1 The voltage difference between the electrodes (that is, the first electrode of the driving transistor T1 in this embodiment).
  • the current flowing through the light-emitting element 20 has nothing to do with the threshold voltage of the driving transistor T1. Therefore, the pixel circuit structure is very well compensated for the threshold voltage of the driving transistor T1.
  • the reset control signal line 17 may be set as a scan line of the pixel unit of the previous row, that is, the reset control signal is performed by the scan signal Scan (n-1) of the pixel unit of the previous row This reduces the number of wiring and signals.
  • the proportion of the duration of the light-emitting phase t3 in the display period of one frame may be adjusted.
  • the brightness of the light emission can be controlled by adjusting the proportion of the duration of the light emission phase t3 to the display period of one frame.
  • controlling the scan driver 103 or an additional driver provided in the display panel to adjust the proportion of the duration of the light-emitting phase t3 to the display period of one frame.
  • the first stabilization capacitor C1 may also be disposed between the data line 12 and other signal lines that provide a constant voltage signal.
  • the first stabilization capacitor C1 is disposed between the data line 12 and the second power supply line 14, or the first stabilization capacitor C1 is disposed between the data line 12 and the initialization signal line 16.
  • the first light-emitting control transistor T4 or the second light-emitting control transistor T5 may not be provided, or the first reset transistor T6 or the second reset transistor T7 may not be provided, that is, the embodiment of the present disclosure is not limited to that shown in FIG. 11.
  • the specific pixel circuit shown other pixel circuits capable of compensating the driving transistor can be used. Based on the description and teaching of this implementation manner in the present disclosure, other setting manners that can be easily conceived by a person of ordinary skill in the art without making creative work fall within the protection scope of the present disclosure.
  • FIG. 14 is a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel provided in this embodiment is different from the display panel in FIG. 11 in that the display panel 100 further includes a second stabilization capacitor C2 and / or a third stabilization capacitor C3, and the second capacitor C2 is disposed on the data line.
  • a third stabilizing capacitor C3 is disposed between the first power line 13 and the first pole of the driving transistor T1. Due to the existence of the second stabilizing capacitor C2, the interference of the parasitic capacitance between the data line 12 and the gate of the driving transistor T1 on the gate signal of the driving transistor T1 is further reduced. Due to the existence of the third stabilizing capacitor C3, the interference of the parasitic capacitance between the first power line 13 and the gate of the driving transistor T1 on the gate signal of the driving transistor T1 is reduced.
  • FIG. 15 is an exemplary plan structural diagram (exemplary layout) of the display panel 100 in FIG. 11.
  • the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the storage capacitor Cst, and the first stabilizing capacitor C1 are shown in the figure.
  • the structures of other transistors are not shown.
  • FIG. 16 is a cross-sectional view of the display panel taken along the section line I-I 'in FIG. 15, and
  • FIG. 17 is a cross-sectional view of the display panel taken along the section line II-II' in FIG.
  • the display panel 100 provided by the embodiment of the present disclosure will be exemplarily described below with reference to FIGS. 15 to 17.
  • “same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate through one patterning process.
  • the same patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the layer structure formed may be continuous or discontinuous.
  • These specific patterns may also be at different heights Or have different thicknesses.
  • a plurality of element / component graphics can be provided on the same layer, which can not increase the number of film layers, which is beneficial to reducing the thickness of the display panel and simplifying the manufacturing process.
  • T1g, T1s, T1d, and T1a are used to indicate the gate, first, second, and channel regions of the driving transistor T1 in the figure and the following descriptions, respectively.
  • the first pole and the second pole of the storage capacitor Cst are represented by Csa and Csb, respectively.
  • the display panel 100 includes a substrate 200 and a semiconductor pattern layer 21, a first insulating layer 22, a first conductive pattern layer 23, a second insulating layer 24, and a second conductive pattern layer 25 stacked in this order on the substrate 200. , An interlayer insulating layer 26, and a third conductive pattern layer 27.
  • the semiconductor pattern layer 21 includes an active layer T1a of the driving transistor T1, an active layer T2a of the data writing transistor T2, and an active layer T3a of the threshold compensation transistor T3.
  • the first conductive pattern layer 23 includes a gate line 11, a second electrode Csb of the storage capacitor Cst, a gate T1g of the driving transistor T1, a gate T2g of the data writing transistor, and a gate T3g of the threshold compensation transistor.
  • the second conductive pattern layer 25 includes a first electrode Csa of the storage capacitor Cst.
  • the first electrode Csa of the storage capacitor Cst and the gate T1g of the driving transistor T1 overlap each other in a direction perpendicular to the substrate 200.
  • the third conductive pattern layer 27 includes a data line 12 and a first power line 13.
  • the gate line 11 extends in the first direction D1
  • the data line 12 and the first power supply line 13 extend in the second direction D2 and are disposed on the same layer.
  • the first direction D1 and the second direction D2 are substantially perpendicular.
  • the first stable capacitor C1 includes a first capacitor electrode 18 that is separately provided and electrically connected to the first power line 13, and the second capacitor electrode of the first stable capacitor C1 is part of the data line 12 itself.
  • the second capacitor electrode may be separately provided as an electrode connected to the data line 12.
  • the first capacitor electrode 18 is disposed on a side of the data line 12 near the substrate 200 and is disposed on the same layer as the first electrode Csa of the storage capacitor Cst.
  • the first capacitor electrode 18 is electrically connected to the first power line 13 through a first via 260 passing through the interlayer insulating layer 26.
  • the first capacitor electrode 18 and the data line 12 overlap each other in a direction perpendicular to the substrate 200, thereby forming a first stable capacitor C1.
  • the semiconductor pattern layer 21 is subjected to a conductive process by using the self-alignment process and the first conductive pattern layer 23 as a mask.
  • the semiconductor pattern layer 21 is re-doped by ion implantation. So that the portion of the semiconductor pattern layer 21 that is not covered by the first conductive pattern layer 23 is made conductive, forming a source region (first electrode T1s) and a drain region (second electrode T1d) of the driving transistor T1, data writing The source region (first electrode T2s) and drain region (second electrode T2d) of the input transistor T2 and the source region (first electrode T3s) and drain region (second electrode T3d) of the threshold compensation transistor T3.
  • a portion of the semiconductor pattern layer 21 covered by the first conductive pattern layer 23 retains semiconductor characteristics, and forms channel regions T1a, T2a, and T3a of each transistor.
  • the display panel 200 further includes a first connection electrode 19 configured to connect the drain region of the threshold compensation transistor T3 and the gate T1g of the driving transistor T1, thereby compensating the threshold.
  • the second electrode T3d of the transistor T3 is electrically connected to the gate T1g of the driving transistor T1.
  • the first connection electrode 19 is disposed on the same layer as the data line 12 and has the same extension direction as the data line 12.
  • a parasitic capacitance exists between the data line 12 and the first connection electrode 19, or between the data line 12 and the second electrode T3d of the threshold compensation transistor T3, 18 is disposed on a side of the data line 12 near the substrate 200.
  • the first capacitor electrode 18 can play a role of raising the data line, and can increase the data line 12 and the first connection electrode 19 and the second value of the threshold compensation transistor T3.
  • the distance between the sides of the pole T3d can reduce this parasitic capacitance. For example, since the second pole T3d of the threshold compensation transistor T3 is directly connected to the gate of the driving transistor T1, reducing the parasitic capacitance helps reduce the interference of the data line on the gate signal of the driving transistor T1.
  • the orthographic projection of the first connection electrode 19 on the layer where the first capacitor electrode 18 is located ie, the second conductive pattern layer 23
  • the first capacitor electrode 18 in a direction perpendicular to the direction in which the data line 12 extends that is, The directions D1 overlap each other.
  • the orthographic projection of the first connection electrode 19 on the layer where the first capacitor electrode 18 is located ie, the second conductive pattern layer 23
  • the direction of the first capacitor electrode 18 perpendicular to the extending direction of the data line 12 overlap each other.
  • the first electrode Csa of the storage capacitor Cst is provided with an opening 250 through which the first connection electrode 19 passes and the second via hole 240 penetrating the second insulating layer 24 and the interlayer insulating layer 26 and the gate of the driving transistor T1.
  • T1g that is, the second pole Csb of the storage capacitor Cst
  • the first connection electrode 19 is electrically connected to the second electrode T3d of the threshold compensation transistor T3 through a third via hole 220 penetrating the first insulating layer 22, the second insulating layer 24, and the interlayer insulating layer 26.
  • the first power supply line 13 is electrically connected to the first electrode Csa of the storage capacitor Cst through a fourth via 261 penetrating the interlayer insulating layer 26.
  • the first pole Csa of the storage capacitor Cst and the data line 13 overlap each other in a direction perpendicular to the substrate, thereby forming a fourth stable capacitor C4. Since the first pole Csa of the storage capacitor Cst is electrically connected to the first power line 13, the fourth stabilizing capacitor C4 is also formed between the first power line and the data line, further reducing the data line 12 and the gate of the driving transistor T1. Interference of parasitic capacitance between the electrodes on the gate signal of the driving transistor T1.
  • the materials of the first insulating layer 22, the second insulating layer 24, and the interlayer insulating layer 26 may include an inorganic insulating material, such as silicon nitride, silicon oxynitride, or the like, or aluminum oxide, titanium nitride, or the like.
  • the insulating material may also include organic insulating materials such as acrylic and polymethyl methacrylate (PMMA).
  • PMMA polymethyl methacrylate
  • the insulating layer may have a single-layer structure or a multilayer structure.
  • the materials of the first conductive pattern layer 23, the second conductive pattern layer 25, the third conductive pattern layer 27, the fourth conductive pattern layer 29, the functional signal line, the first conductive structure, and the second conductive structure include gold (Au). , Silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloys of these metals; or conductive metal oxide materials, such as indium oxide Tin (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the display panel 100 may further include a buffer layer 28 provided between the substrate 200 and the semiconductor pattern layer 21.
  • the substrate 200 is a glass substrate
  • the buffer layer 28 is silicon dioxide, which is used to prevent impurities (metal ions) in the substrate 200 from diffusing into the pixel circuit structure.
  • the function signal line may include at least one of an initialization signal line 16, a light emission control signal line 15, a reset control signal line 17, a first power line 13, and a second power line 14.
  • the array substrate includes, in order, a substrate, a polysilicon layer, a first gate insulating layer, a first conductive pattern layer (including a gate line, a gate, and a second electrode of a storage capacitor), and a second gate insulation.
  • the passivation layer, the planarization layer, the fourth conductive pattern layer (including the first electrode, the first conductive structure, the first electrode may be the anode of the OLED), the light-emitting layer, and the second electrode (the cathode of the OLED).
  • the functional signal line is a first power line
  • the first conductive structure is disposed on the same layer as the first electrode, and the first conductive structure is parallel to the first power line.
  • the first conductive structure 02 may also be provided separately.
  • the array substrate includes a substrate, a polysilicon layer, a first gate insulating layer, a first conductive pattern layer (including a gate line, a gate, and a second electrode of a storage capacitor), a second gate insulating layer, and a second conductive pattern layer.
  • a fourth conductive pattern layer (including the first conductive structure), a second planarization layer, an anode layer of the OLED, a light emitting layer, and a cathode layer of the OLED.
  • the functional signal line is a first power line
  • the first conductive structure is connected in parallel with the first power line.
  • the pixel circuit structure in the display panel provided by the embodiment of the present disclosure is not limited to that shown in FIG. 11, and pixel structure of other structures may also be adopted.
  • the first stabilizing capacitor C1 the first light-emitting control transistor T4
  • the display panel provided in the embodiment of the present disclosure can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display panel is an organic light emitting diode display panel.
  • an embodiment of the present disclosure further provides a display device including the above display panel.
  • the display device may be an electronic device such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., to which the display panel is applied.
  • the display device is an organic light emitting diode display device.

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Abstract

一种显示面板及显示装置。显示面板包括：基板(200)、多个像素单元(101)、功能信号线(01)和第一导电结构(02)。基板(200)包括显示区(201)和位于显示区(201)至少一侧的周边区(202)。多个像素单元(101)位于显示区(201)，每个像素单元(101)包括发光单元(20)和为发光单元(20)提供驱动电流的像素电路结构(10)，发光单元(20)为电致发光元件。功能信号线(01)与每个像素单元(101)的像素电路结构(10)连接并为像素电路结构(10)提供公共电压信号。第一导电结构(02)与功能信号线(01)并联，且与功能信号线(01)位于不同的层。显示面板可提高显示均匀性以及分辨率，从而提高显示面板的显示品质。

Description

显示面板及显示装置
相关申请的交叉引用
本专利申请要求于2018年5月29日递交的中国专利申请第201820812831.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示面板及显示装置。
背景技术
在显示领域，有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
发明内容
本公开实施例提供一种显示面板和显示装置，该显示面板可兼顾提高显示均匀性以及分辨率，从而提高显示面板的显示品质。
本公开至少一实施例提供一种显示面板，包括：
基板，包括显示区和位于所述显示区至少一侧的周边区，
多个像素单元，位于所述显示区，每个像素单元包括发光单元和为所述发光单元提供驱动电流的像素电路结构，所述发光单元为电致发光元件；
功能信号线，与每个像素单元的像素电路结构连接并为所述像素电路结构提供公共电压信号；
第一导电结构，与所述功能信号线并联，且与所述功能信号线位于不同的层。
一些实施例中，所述多个像素单元沿行方向和列方向延伸以形成多行像素单元和多列像素单元，所述功能信号线包括沿第一方向延伸的第一信号线，所述第一信号线沿一行像素单元或一列像素单元延伸。
一些实施例中，所述功能信号线包括沿第二方向延伸的第二信号线，所 述第二信号线位于所述周边区，所述第二信号线与所述第一信号线相连，所述第二方向与所述第一方向交叉。
一些实施例中，所述第二信号线与信号输入电路相连。
一些实施例中，所述第一导电结构包括沿第一方向延伸的第一导电线，所述第一导电线沿一行像素单元或一列像素单元延伸。
一些实施例中，所述第一导电结构包括沿第二方向延伸的第二导电线，所述第二导电线位于所述周边区，所述第二导电线与所述第一导电线连接。
一些实施例中，所述第二导电线和所述第一导电线位于不同的层。
一些实施例中，显示面板还包括位于所述第一导电结构和所述功能信号线之间的绝缘层，其中，所述第一导电结构和所述功能信号线通过贯穿位于两者之间的所述绝缘层的过孔相连。
一些实施例中，所述过孔包括位于所述显示区的显示区过孔和位于所述周边区的周边区过孔至少之一。
一些实施例中，在垂直于所述基板的方向上，所述第一信号线和所述第一导电线具有第一交叠区域，所述显示区过孔位于所述第一交叠区域，所述第一信号线和所述第一导电线通过所述显示区过孔连接。
一些实施例中，在垂直于所述基板的方向上，所述第二信号线和所述第二导电线具有第二交叠区域，所述周边区过孔位于所述第二交叠区域，所述第二信号线和所述第二导电线通过所述周边区过孔连接。
一些实施例中，所述显示区过孔的数量为多个，为每个像素单元设置至少一个显示区过孔。
一些实施例中，所述周边区过孔的数量为多个，所述多个周边区过孔中的每个对应一行像素单元或对应一列像素单元。
一些实施例中，所述第一导电线通过转接图案和所述第一信号线连接，所述第一导电线和所述转接图案通过贯穿位于两者之间的绝缘层的过孔连接，所述转接图案和所述第一信号线通过贯穿位于两者之间的绝缘层的过孔连接。
一些实施例中，每个发光单元包括第一电极，不同发光单元的第一电极彼此绝缘，所述第一导电结构与所述第一电极同层，所述第一导电线在相邻行像素单元或相邻列像素单元的第一电极的间隙中延伸。
一些实施例中，显示面板还包括栅线、数据线、第一电源线以及第二电源线，所述像素电路结构包括存储电容、驱动晶体管、数据写入晶体管和阈值补偿晶体管，所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极通过第一连接电极与所述阈值补偿晶体管的第二极电连接；所述数据写入晶体管的栅极与所述栅线电连接，所述数据写入晶体管的第一极与第二极分别与所述数据线、所述驱动晶体管的第一极电连接；所述阈值补偿晶体管的栅极与所述栅线电连接，所述阈值补偿晶体管的第一极和第二极分别与所述驱动晶体管的第二极和栅极电连接；所述发光元件的第二电极与所述第二电源线电连接。
一些实施例中，所述第一导电线包括具有第一宽度的第一部分和具有第二宽度的第二部分，所述第一宽度小于所述第二宽度，在垂直于所述基板的方向上，所述第二部分与所述驱动晶体管的沟道区、所述数据写入晶体管的沟道区和所述阈值补偿晶体管的沟道区至少之一重叠。
一些实施例中，显示面板还包括初始化信号线、发光控制信号线和复位控制信号线，其中，所述像素电路结构还包括第一发光控制晶体管、第二发光控制晶体管、第一复位晶体管以及第二复位晶体管；所述第一发光控制晶体管的栅极与所述发光控制信号线电连接，所述第一发光控制晶体管的第一极与第二极分别与所述第一电源线和所述驱动晶体管的第一极电连接；所述第二发光控制晶体管的栅极与所述发光控制信号线电连接，所述第二发光控制晶体管的第一极与第二极分别与所述驱动晶体管的第二极、所述发光元件的第一电极电连接；所述第一复位晶体管的栅极与所述复位控制信号线电连接，所述第一复位晶体管的第一极和第二极分别与所述初始化信号线以及所述驱动晶体管的栅极电连接；所述第二复位晶体管的栅极与所述复位控制信号线电连接，所述第二复位晶体管的第一极和第二极分别与所述初始化信号线以及所述发光元件的第一电极电连接。
一些实施例中，所述像素电路结构还包括设置于所述数据线和所述第一电源线之间的第一稳定电容，所述第一稳定电容包括第一电容电极；所述栅线、所述驱动晶体管的栅极和所述存储电容的第二极同层设置；所述第一电容电极、所述初始化信号线、所述存储电容的第一极同层设置；所述数据线、所述第一电源线以及所述第一连接电极同层设置；所述第一电容电极与所述 数据线在垂直于所述基板的方向上彼此重叠。
一些实施例中，所述功能信号线包括初始化信号线、第一电源线、第二电源线至少之一。
一些实施例中，所述栅线、所述发光控制信号线和所述复位控制信号线位于第一导电图案层；所述第一信号线位于第二导电图案层；所述数据线、所述第一电源线和所述第二信号线位于第三导电图案层；所述第一电极、所述第一导电线和所述第二导电线位于第四导电图案层；所述第一信号线和所述第二信号线构成所述初始化信号线，所述第一导电线和所述第二导电线构成所述第一导电结构。
一些实施例中，所述阈值补偿晶体管和所述第一复位晶体管为金属氧化物半导体薄膜晶体管。
一些实施例中，显示面板还包括第二导电结构，所述功能信号线为所述初始化信号线，所述第二导电结构和所述第一电源线并联，所述第二导电结构位于所述第三导电图案层和所述第四导电图案层之间。
一些实施例中，所述像素电路结构还包括第二稳定电容和第三稳定电容至少之一，所述第二稳定电容提供于所述数据线和所述驱动晶体管的第一极之间，所述第三稳定电容提供与所述第一电源线和所述驱动晶体管的第一极之间。
本公开实施例还提供一种显示装置，包括本公开至少一实施例提供的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1A为本公开至少一实施例提供的一种显示面板的俯视示意图；
图1B为本公开至少一实施例提供的一种显示面板中一个像素单元的示意图；
图1C为本公开至少一实施例提供的一种显示面板中为每个像素单元提供信号的信号线的示意图；
图2为本公开至少一实施例提供的一种显示面板的俯视示意图；
图3为图2中M-N处的剖视示意图；
图4A-4D分别为图2中四个导电图案层的每个的俯视示意图；
图5为本公开一实施例提供的显示面板中功能信号线与信号输入电路连接的示意图；
图6A为本公开另一实施例提供的显示面板的俯视示意图；
图6B为图6A中X-Y处的剖视示意图；
图7为本公开一实施例提供的显示面板中的第四导电图案层的示意图；
图8为本公开一实施例提供的显示面板中的第一导电线的示意图；
图9为本公开一实施例提供的显示面板中的第一信号线与薄膜晶体管的沟道区的俯视示意图；
图10为本公开一实施例提供的显示面板的剖视示意图；
图11为本公开一实施例提供一种显示面板的结构示意图；
图12为本公开一实施例提供的一种显示面板的平面示意图；
图13为本公开一实施例提供的显示面板中一个像素单元的时序信号图；
图14为本公开另一实施例提供的一种显示面板的结构示意图；
图15为本公开一实施例提供的一种显示面板的平面示意图；
图16为图15中显示面板沿剖面线I-I’的剖视图；以及
图17为图15中显示面板沿剖面线II-II’的剖视图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、 “第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
随着显示产品的应用越来越广泛，消费者对显示品质例如显示均匀性以及分辨率的要求越来越高。例如，造成显示不均匀的原因如下：导线的电压输入末端与电压输入起始端相比，有较明显的压降(IR drop)效应，容易造成信号延迟问题，造成显示面板的显示不均匀。例如，增大导线尺寸为一种简单提升显示均匀性的做法，但增大导线尺寸对分辨率提升不利。提升分辨率的做法是减小电路结构尺寸，如降低线宽，但降低线宽会加剧显示不均匀，同时降低线宽同样导致工艺良率降低。目前OLED的电路结构比液晶显示器(liquid crystal display，LCD)的电路结构复杂，提升分辨率空间有限。因此，需要提供一种新型设计以满足高分辨率以及显示均匀性要求。
本公开至少一实施例提供的一种显示面板可兼顾提高显示面板的显示均匀性以及提高显示面板的分辨率。
图1A为本公开至少一实施例提供的一种显示面板的俯视示意图。该显示面板包括：基板200和多个像素单元101。基板200包括显示区201和位于显示区201至少一侧的周边区202，多个像素单元101位于显示区201。图1A中示出了周边区202围绕显示区201设置，但不限于此。像素单元101的个数和排布方式不限于图中所示。
图1B为本公开至少一实施例提供的一种显示面板中一个像素单元的示意图。如图1B所示，每个像素单元101包括发光单元20和为发光单元20提供驱动电流的像素电路结构10，发光单元20可为电致发光元件，例如，有机电致发光元件，例如可为有机发光二极管(OLED)。例如，电致发光元件的驱动原理如下：电致发光元件采用电流驱动，电流大小决定显示灰阶， 因此不同像素间在相同的驱动信号控制下，不同位置处的像素的功能信号线的压降不同可造成电流差异，电流差异可造成显示不均匀。
图1C为本公开至少一实施例提供的一种显示面板中为每个像素单元提供信号的信号线的示意图。图1C中示出了栅线11、数据线12、第一电源线13、第二电源线14和初始化信号线16。例如，栅线11被配置为向像素电路结构10提供扫描信号Scan，数据线12被配置为向像素电路结构10提供数据信号Data，第一电源线13被配置为向像素电路结构10提供恒定的第一电压信号ELVDD，第二电源线14被配置为向像素电路结构10提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。初始化信号线16被配置为向像素电路结构10提供初始化信号Vint。初始化信号Vint为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vint可小于或等于第二电压信号ELVSS。例如，第一电源线13、第二电源线14和初始化信号线16等信号线可存在上述信号延迟问题。
图2为本公开至少一实施例提供的一种显示面板的俯视示意图。该显示面板还包括功能信号线01。功能信号线01与每个像素单元101的像素电路结构10连接并为像素电路结构10提供公共电压信号。例如，公共电压信号可为恒定的电压信号。
如图2所示，该显示面板还包括第一导电结构02。第一导电结构02与功能信号线01并联，且与功能信号线01位于不同的层。例如，第一导电结构02和功能信号线的不同层的设置可利于两者通过孔方式并联。
本公开的实施例中提供的显示面板，第一导电结构02与功能信号线01并联，可降低功能信号线的电阻，使得由功能信号线的电阻问题造成的信号延迟问题得到减弱。同时，因第一导电结构02与功能信号线01并联可减弱信号延迟问题，可不必使用较大宽度的功能信号线，可利于提高分辨率。从而，本公开的实施例中提供的显示面板，可利于兼顾提高显示均匀性以及提高分辨率，进而可提高显示品质。
例如，如图2所示，多个像素单元101沿行方向和列方向延伸以形成多行像素单元和多列像素单元。图2中示出了三行和三列像素单元，本公开的实施例以此为例进行说明。例如，行方向为横向，列方向为纵向。功能信号 线01包括沿第一方向D1延伸的第一信号线011，第一信号线011沿一行像素单元延伸。例如，第一信号线011位于显示区201。
例如，如图2所示，为进一步降低电阻，功能信号线01还包括沿第二方向D2延伸的第二信号线012，第二信号线012位于周边区202，第二信号线012与第一信号线011相连，第二方向D2与第一方向D1交叉。进一步例如，第二方向D2垂直于第一方向D1。如图2所示，第一信号线011和第二信号线012异层设置，通过贯穿绝缘层的过孔电连接。当然，第一信号线011和第二信号线012也可同层设置。
例如，如图2所示，第一导电结构02包括沿第一方向D1延伸的第一导电线021，第一导电线021沿一行像素单元延伸。例如，第一导电线021位于显示区。
例如，如图2所示，为进一步降低电阻，第一导电结构02还包括沿第二方向D2延伸的第二导电线022，第二导电线022位于周边区202，第二导电线022与第一导电线021连接。如图2所示，第一导电线021和第二导电线022同层设置。当然，第一导电线021和第二导电线022也可以异层设置，通过贯穿绝缘层的过孔电连接。
不同的导电图案层之间可设置绝缘层。例如，如图2所示，显示面板还包括绝缘层(图中未显示，可参照图3)，绝缘层位于第一导电结构02和功能信号线01之间，第一导电结构02和功能信号线01通过贯穿绝缘层的过孔V相连。
例如，如图2所示，过孔V包括位于显示区的显示区过孔V1和位于周边区的周边区过孔V2至少之一。
例如，如图2所示，在显示面板的俯视图中，第一信号线011和第一导电线021具有第一交叠区域OL1，显示区过孔V1位于第一交叠区域OL1，第一信号线011和第一导电线021通过显示区过孔V1连接。需要说明的是，本公开的实施例中，在显示面板的俯视图中也可以看作在垂直于基板200的方向上。
例如，本公开的实施例中，垂直于基板200的方向上可为在基板200的厚度方向上或者垂直于基板200的主表面的方向上。例如，显示面板的俯视图为由显示面板上方向下做正投影得到的视图。
例如，如图2所示，为利于进一步降低功能信号线的电阻，显示区过孔V1的数量为多个，为每个像素单元101至少设置一个显示区过孔V1。例如，显示区过孔V1的数量可以至少与像素单元的数量相同。例如，显示区过孔V1的数量可以为像素单元的数量的至少一倍(例如两倍)。
例如，如图2所示，在显示面板的俯视图中，第二信号线012和第二导电线022具有第二交叠区域OL2，周边区过孔V2位于第二交叠区域OL2，第二信号线012和第二导电线022通过周边区过孔V2连接。
例如，如图2所示，为利于进一步降低功能信号线的电阻，周边区过孔V2的数量为多个。例如，多个周边区过孔V2中的每两个对应一行像素单元。
图2中，以第一导电结构02和功能信号线01通过显示区过孔V1和周边区过孔V2并联连接为例进行说明。需要说明的是，第一导电结构02和功能信号线01可仅通过显示区过孔V1并联连接，或者，第一导电结构02和功能信号线01可仅通过周边区过孔V2并联连接。并且，显示区过孔V1和周边区过孔V2的设置并不限于图2所示。
例如，如图2所示，为了与构图工艺兼容且降低过孔的制作难度，第一导电线021可通过转接图案271和第一信号线011连接，第一信号线011和转接图案271通过贯穿位于两者之间的绝缘层的过孔V11连接，转接图案271和第一导电线021通过贯穿位于两者之间的绝缘层的过孔V12连接(也可参见图3)。当然，也可不设置转接图案271，本公开的实施例对此不作限定。
图3为图2中M-N处的剖视示意图。如图3所示，功能信号线01包括第一信号线011和第二信号线012，第一信号线011和第二信号线012通过贯穿层间绝缘层26的过孔V0电连接。在周边区，第二导电线022和第二信号线012通过贯穿位于第二导电线022和第二信号线012(功能信号线01)之间的绝缘层30的过孔V2电连接。在显示区，转接图案271和第一信号线011通过位于贯穿第一信号线011和转接图案271之间的层间绝缘层26的过孔V11电连接，第二导电线021和转接图案271通过贯穿位于第二导电线021和转接图案271之间的绝缘层30之间的过孔V12电连接。图3还示出了衬底基板200以及其上的缓冲层28。图3还示出了第一交叠区域OL1和第二交叠区域OL2。
图4A-4D为图2中四个导电图案层的每个的俯视示意图。请结合图2、 图4A-4D，显示面板包括第一导电图案层23、第二导电图案层25、第三导电图案层27和第四导电图案层29。
如图4A所示，第一导电图案层23包括栅线11、发光控制信号线15和复位控制信号线17。
如图4B所示，第二导电图案层25包括第一信号线011。如图4A和4B所示，第一信号线011与栅线11的延伸方向相同。多个第一信号线011相互间隔。例如，每个第一信号线011可与一行像素单元相对应。
如图4C所示，第三导电图案层27包括第二信号线012、数据线12、第一电源线13和转接图案271。例如，第二信号线012与数据线12的延伸方向相同。例如，数据线12可对应一列像素单元，第一电源线13可对应一列像素单元。
如图4D所示，第四导电图案层29包括第一导电结构02，第一导电结构02包括电连接的第一导电线021和第二导电线022。例如，第一导电线021和第二导电线022可同层形成，当然，也可以不同层，通过贯穿绝缘层的过孔电连接。例如，一个实施例中，第一导电线021与第一电极2001(可参见图7)同层，第二导电线022与初始化信号线16位于周边区的部分同层。
例如，图2中的功能信号线01可为像素电路结构中的初始化信号线16。当然，功能信号线01还可以为第一电源线13，将在图6A中进行详细描述。初始化信号线16可包括位于显示区的部分(可对应于第一信号线011)和位于周边区的部分(可对应于第二信号线012)。
图5为本公开一实施例提供的显示面板中功能信号线与信号输入电路连接的示意图。如图5所示，第二信号线012与信号输入电路80相连。例如，如图5所示，第二信号线012与第一信号线011位于不同的层，通过过孔V2相连。
如图5所示，功能信号线01靠近信号输入电路80的部分可为电压输入起始端，功能信号线01远离信号输入电路80的部分可为电压输入末端，因本公开的实施例中，第一导电结构02与功能信号线01并联，可减小电压输入末端和电压输入起始端之间的压降效应导致的信号延迟问题。同时，因可减小信号延迟问题，从而不必使用较大宽度的信号线，进而利于提高显示面板的分辨率，从而利于提高显示品质。
图6A为本公开一实施例提供的显示面板的俯视示意图。如图6A所示，第一信号线011沿一列像素单元延伸，第一导电线021沿一列像素单元延伸，多个周边区过孔V2中的每四个对应一列像素单元。如图6A所示，第二信号线012沿一行像素单元延伸，第二导电线022沿一行像素单元延伸。
图6B为图6A中X-Y处的剖视示意图。如图6A和图6B所示。第一信号线011和第二信号线012通过贯穿两者之间的层间绝缘层26的过孔V0电连接构成功能信号线01。第一导电线021和第一信号线011通过贯穿两者之间的绝缘层30的显示区过孔V1电连接。转接图案272和第二信号线012通过贯穿位于两者之间的层间绝缘层26的过孔V21(周边区过孔V2)电连接。第二导电线022和转接图案272通过贯穿位于两者之间的绝缘层30的过孔V22(周边区过孔V2)电连接。
图7为本公开一实施例提供的显示面板中的第四导电图案层的示意图。例如，如图7所示，每个发光单元(例如，有机电致发光二极管)包括第一电极2001，不同发光单元的第一电极2001彼此绝缘，第一导电结构02与第一电极2001同层。第一导电结构02包括同层且电连接的第一导电线021和第二导电线022。
图8为本公开一实施例提供的显示面板中的第一导电线的示意图。如图8所示，第一导电线021在相邻行像素单元101的第一电极2001的间隙中延伸。当然，类似的，第一导电线021也可在相邻列像素单元101的第一电极2001的间隙中延伸。如图8所示，第一导电线021和第二导电线022不同层。例如，可第一导电线021和第二导电线022之一与第一电极2001同层，另一个与其他导电结构同层设置，但不限于此。
图9为本公开一实施例提供的显示面板中的第一信号线与薄膜晶体管的沟道区的俯视示意图。
例如，第一导电线021包括具有第一宽度的第一部分0211和具有第二宽度的第二部分0212，第一宽度d1小于第二宽度d2，在显示面板的俯视图中，第二部分0212可与驱动晶体管的沟道区T1a、数据写入晶体管的沟道区T2a和阈值补偿晶体管的沟道区T3a至少之一重叠。此处的驱动晶体管、数据写入晶体管和阈值补偿晶体管可参照如下所述的驱动晶体管T1、数据写入晶体管T2和阈值补偿晶体管T3(例如，如图11所示)。驱动晶体管的沟道区T1a、 数据写入晶体管的沟道区T2a和阈值补偿晶体管的沟道区T3a也可参照图15。用第一导电线的第二部分对薄膜晶体管的沟道区进行遮挡，可进一步提升薄膜晶体管的稳定性，降低漏电流。图9中以在显示面板的俯视图中，第二部分0212与驱动晶体管的沟道区T1a、数据写入晶体管的沟道区T2a和阈值补偿晶体管的沟道区T3a重叠为例进行说明。本公开的实施例中，第二部分0212也可以与驱动晶体管的沟道区T1a、数据写入晶体管的沟道区T2a和阈值补偿晶体管的沟道区T3a中的一个或两个重叠。
图10为本公开一实施例提供的显示面板的剖视示意图。与图3所示的显示面板相比，显示面板还包括第五导电图案层290。第五导电图案层290可位于第三导电图案层27和第四导电图案层29之间。第五导电图案层290可包括第二导电结构03，在该实施例中，功能信号线01为初始化信号线16，第二导电结构03和第一电源线13并联。例如，在显示面板的俯视图中，第二导电结构03可为网格状。
如图10所示，第五导电图案层290还可包括转接图案2901和2902以利于与构图工艺兼容且降低过孔的制作难度。图10中还示出了第五导电图案层290和第四导电图案层29之间的绝缘层31。
以下根据对像素电路结构进行具体描述。例如，功能信号线可为初始化信号线、第一电源线、第二电源线至少之一。以上实施例以功能信号线为初始化信号线和/或第一电源线为例进行说明。需要说明的是，本公开的实施例不限于此，只要是向像素电路结构提供公共电压信号的信号线均可为功能信号线。
图11为本公开的实施例提供一种显示面板的结构示意图，图12为本公开实施例提供的一种显示面板的平面结构示意图。请一并参阅图11和图12，显示面板100包括呈矩阵排布的多个像素单元101，每个像素单元101包括像素电路结构10、发光元件20以及栅线11、数据线12及电压信号线。发光元件20为有机发光元件OLED，发光元件20在其对应的像素电路结构10的驱动下发出红光、绿光、蓝光，或者白光等。该电压信号线可以是一条也可以包括多条。例如，如图所示，该电压信号线包括第一电源线13、第二电源线14、发光控制信号线15、初始化信号线16和复位控制信号线17等中的至少之一。
例如，第一电源线13配置为向像素电路结构10提供恒定的第一电压信号ELVDD，第二电源线14配置为向像素电路结构10提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。发光控制信号线15配置为向像素电路结构10提供发光控制信号EM。初始化信号线16和复位控制信号线17分别配置为向像素电路结构10提供初始化信号Vint和复位控制信号Reset，其中，初始化信号Vint为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vint可小于或等于第二电压信号ELVSS。
如图11所示，该像素电路结构10包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容Cst。驱动晶体管T1与发光元件20电连接，并在扫描信号Scan、数据信号Data、第一电压信号ELVDD、第二电压信号ELVSS等信号的控制下输出驱动电流以驱动发光元件20发光。
在有机发光二极管显示面板的像素单元中，驱动晶体管与有机发光元件连接，在数据信号、扫描信号等信号的控制下向有机发光元件输出驱动电流，从而驱动有机发光元件发光。由于驱动晶体管的栅极电压的大小直接与有机发光元件中的驱动电流大小相关，栅极信号的稳定对于实现有机发光元件的发光稳定以及显示面板的显示稳定是一个重要因素。
在研究中，发明人发现，数据信号在数据线上传输时，数据信号的波动容易对驱动晶体管的栅极信号造成干扰，例如数据信号通过数据线与驱动晶体管的栅极之间形成的寄生电容对栅极信号造成干扰，从而影响栅极信号的稳定性。
如图11所示，像素电路结构10还包括设置于数据线12与第一电源线13之间的第一稳定电容C1。当数据线12上的数据信号Data发生变化时，第一稳定电容C1可以降低数据线12与驱动晶体管T1栅极之间寄生电容对驱动晶体管T1栅极信号的干扰。
在实际情况中，例如可以设计使得第一稳定电容C1的电容值大于数据线12与驱动晶体管T1栅极之间寄生电容的10倍以上。当该寄生电容的电容值相较于第一稳定电容C1忽略不计时，则该数据信号Data通过该寄生电 容对栅极信号的影响也可以忽略不计。
第一稳定电容C1可以有多种设置方式。例如，第一稳定电容可以包括第一电容电极和第二电容电极，第一电容电极与第一电源线13电连接，第二电容电极与数据线12电连接。需要说明的是，第一电容电极可以是第一电源线13的一部分或者单独设置的与第一电源线13电连接的电极，这两种情形都包括在上述“第一电容电极与第一电源线电连接”的范围内。同样，第二电容电极可以是数据线12的一部分或者单独设置的与数据线12电连接的电极，这两种情形都包括在上述“第二电容电极与数据线电连接”的范围内。
例如，在制备过程中，在显示面板100的基板上通过半导体工艺制备像素电路结构，其包括层叠的电路层、绝缘层等。第一电容电极与第二电容电极可以在垂直于显示面板100的基板的方向上彼此重叠，且二者之间由绝缘层(介电层)间隔开，由此构成电容器。在实际设计中，可以通过设计第一电容电极与第二电容电极之间的距离、其间的绝缘层的材料(即介电常数)以及二者之间的重叠面积来调节第一稳定电容C1的电容值。
如图11所示，存储电容Cst的第一极与第一电源线13电连接，存储电容Cst的第二极与阈值补偿晶体管T3的第二极电连接。数据写入晶体管T2的栅极与栅线11电连接，数据写入晶体管T2的第一极与第二极分别与数据线12、驱动晶体管T1的第一极电连接。阈值补偿晶体管T3的栅极与栅线11电连接，阈值补偿晶体管T3的第一极和第二极分别与驱动晶体管T1的第二极和栅极电连接。
如图11所示，第一发光控制晶体管T4的栅极与发光控制信号线15电连接，第一发光控制晶体管T4的第一极与第二极分别与第一电源线13和驱动晶体管T1的第一极电连接。第二发光控制晶体管T5的栅极与发光控制信号线15电连接，第二发光控制晶体管T5的第一极与第二极分别与驱动晶体管T1的第二极、发光元件20的第一电极电连接。第一复位晶体管T6的栅极与复位控制信号线17电连接，第一复位晶体管T6的第一极和第二极分别与初始化信号线16以及驱动晶体管T1的栅极电连接。第二复位晶体管T7的栅极与复位控制信号线17电连接，第二复位晶体管T7的第一极和第二极分别与初始化信号线16以及发光元件20的第一电极(可为OLED的像素电极，例如阳极)电连接。发光元件20的第二电极(可为OLED的公共电极， 例如阴极)与第二电源线14电连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本公开实施例的像素电路结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
例如，本公开实施例采用的晶体管的有源层可以为单晶硅、多晶硅(例如低温多晶硅)或金属氧化物半导体材料(如IGZO、AZO等)。在一个示例中，该晶体管均为P型LTPS(低温多晶硅)薄膜晶体管。在另一个示例中，与驱动晶体管T1栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为金属氧化物半导体薄膜晶体管，即晶体管的沟道材料为金属氧化物半导体材料(如IGZO、AZO等)，金属氧化物半导体薄膜晶体管具有较低的漏电流，可以有助于降低驱动晶体管T1的栅极漏电流。
例如，本公开实施例采用的晶体管可以包括多种结构，如顶栅型、底栅型或者双栅结构。在一个示例中，与驱动晶体管T1栅极直接连接的阈值补偿晶体管T3和第一复位晶体管T6为双栅型薄膜晶体管，可以有助于降低驱动晶体管T1的栅极漏电流。
例如，如图12所示，本公开实施例提供的显示面板100还包括：数据驱动器102、扫描驱动器103和控制器104。数据驱动器102被配置为根据控制器104的指令向像素单元101提供数据信号Data；扫描驱动器103被配置为根据控制器104的指令向像素单元101提供发光控制信号EM、扫描信号Scan 以及复位控制信号Reset等。例如，扫描驱动器103为安装于该显示面板上的GOA(Gate On Array)结构，或者为与该显示面板进行绑定(Bonding)的驱动芯片(IC)结构。例如，还可以采用不同的驱动器分别提供发光控制信号EM和扫描信号Scan。例如，显示面板100还包括电源(图中未示出)以提供上述电压信号，根据需要可以为电压源或电流源，所述电源被配置为分别通过第一电源线13、第二电源线14、以及初始化信号线16向像素单元101提供第一电源电压ELVDD、第二电源电压ELVSS、以及初始化信号Vint等。
图13为本公开实施例提供的显示面板中一个像素单元的时序信号图。以下将结合图13对本公开实施例提供的显示面板中一个像素单元的驱动方法进行说明。
如图13所示，在一帧显示时间段内，像素单元的驱动方法包括复位阶段t1、数据写入及阈值补偿阶段t2和发光阶段t3。
在复位阶段t1，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为开启电压，设置扫描信号Scan为关闭电压。
在数据写入及阈值补偿阶段t2，设置发光控制信号EM为关闭电压，设置复位控制信号Reset为关闭电压，设置扫描信号Scan为开启电压。
在发光阶段t3，设置发光控制信号EM为开启电压，设置复位控制信号Reset为关闭电压，设置扫描信号Scan为关闭电压。
例如，本公开实施例中的开启电压是指能使相应晶体管第一极和第二级导通的电压，关闭电压是指能使相应晶体管的第一极和第二级断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图13所示的驱动波形均以P型晶体管为例进行说明，即开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)。
请一并参阅图11和图13，在复位阶段t1，发光控制信号EM为关闭电压，复位控制信号Reset为开启电压，扫描信号Scan为关闭电压。此时，第一复位晶体管T6和第二复位晶体管T7处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4和第二发光控制晶体管T5 处于关闭状态。第一复位晶体管T6将初始化信号(初始化电压)Vint传输到驱动晶体管T1的栅极并被存储电容Cst存储，将驱动晶体管T1复位并消除上一次(上一帧)发光时存储的数据，第二复位晶体管T7将初始化信号Vint传输到发光元件20的第一电极，以将发光元件20复位。
在数据写入及阈值补偿阶段t2，发光控制信号EM为关闭电压，复位控制信号Reset为关闭电压，扫描信号Scan为开启电压。此时，数据写入晶体管T2和阈值补偿晶体管T3处于导通状态，而第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。此时，数据写入晶体管T2将数据信号电压Vdata传输到驱动晶体管T1的第一极，即，数据写入晶体管T2接收扫描信号Scan和数据信号Data并根据扫描信号Scan向驱动晶体管T1的第一极写入数据信号Data。阈值补偿晶体管T3导通将驱动晶体管T1连接成二极管结构，由此可对于驱动晶体管T1的栅极进行充电。充电完成之后，驱动晶体管T1的栅极电压为Vdata+Vth，其中，Vdata为数据信号电压，Vth为驱动晶体管T1的阈值电压，即，阈值补偿晶体管T3接收扫描信号Scan并根据扫描信号Scan对驱动晶体管T1的栅极电压进行阈值电压补偿。在此阶段，存储电容Cst两端的电压差为ELVDD-Vdata-Vth。
在发光阶段t3，发光控制信号EM为开启电压，复位控制信号Reset为关闭电压，扫描信号Scan为关闭电压。第一发光控制晶体管T4和第二发光控制晶体管T5处于导通状态，而数据写入晶体管T2、阈值补偿晶体管T3、第一复位晶体管T6和第二复位晶体管T7处于关闭状态。第一电源信号ELVDD通过第一发光控制晶体管T4传输到驱动晶体管T1的第一极，驱动晶体管T1的栅极电压保持为Vdata+Vth，发光电流I通过第一发光控制晶体管T4、驱动晶体管T1和第二发光控制晶体管T5流入发光元件20，发光元件20发光。即，第一发光控制晶体管T4和第二发光控制晶体管T5接收发光控制信号EM，并根据发光控制信号EM控制发光元件20发光。发光电流I满足如下饱和电流公式：
K(Vgs-Vth) 2＝K(Vdata+Vth-ELVDD-Vth) 2＝K(Vdata-ELVDD) 2
其中，
Figure PCTCN2019071409-appb-000001
μ n为驱动晶体管的沟道迁移率，Cox为驱动晶体 管T1单位面积的沟道电容，W和L分别为驱动晶体管T1的沟道宽度和沟道长度，Vgs为驱动晶体管T1的栅极与源极(也即本实施例中驱动晶体管T1的第一极)之间的电压差。
由上式中可以看到流经发光元件20的电流与驱动晶体管T1的阈值电压无关。因此，本像素电路结构非常好的补偿了驱动晶体管T1的阈值电压。
例如，在显示面板的像素阵列中，为了方便布线，复位控制信号线17可以设置为上一行像素单元的扫描线，也即复位控制信号由上一行像素单元的扫描信号Scan(n-1)充当，从而减少了布线以及信号数量。
例如，发光阶段t3的时长占一帧显示时间段的比例可被调节。这样，可以通过调节发光阶段t3的时长占一帧显示时间段的比例控制发光亮度。例如，通过控制显示面板中的扫描驱动器103或者额外设置的驱动器实现调节发光阶段t3的时长占一帧显示时间段的比例。
例如，在其他示例中，第一稳定电容C1还可以设置于数据线12和其它提供恒定电压信号的信号线之间。例如，第一稳定电容C1设置于数据线12与第二电源线14之间，或者第一稳定电容C1设置于数据线12与初始化信号线16之间。在其他示例中，可以不提供第一发光控制晶体管T4或第二发光控制晶体管T5，或者可以不提供第一复位晶体管T6或第二复位晶体管T7等，也即本公开实施例不限于图11所示出的具体像素电路，可以采用其他能实现对于驱动晶体管补偿的像素电路。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到的其它设置方式，都属于本公开的保护范围之内。
图14为本公开另一实施例提供的显示面板的示意图。如图所示，本实施例提供的显示面板与图11中的显示面板的区别在于，显示面板100还包括第二稳定电容C2和/或第三稳定电容C3，第二电容C2设置于数据线12和驱动晶体管T1的第一极之间，第三稳定电容C3设置于第一电源线13和驱动晶体管T1的第一极之间。由于第二稳定电容C2的存在，数据线12与驱动晶体管T1的栅极之间的寄生电容对驱动晶体管T1的栅极信号的干扰得以进一步减小。由于第三稳定电容C3的存在，第一电源线13与驱动晶体管T1的栅极之间的寄生电容对驱动晶体管T1的栅极信号的干扰得以减小。
图15为图11中显示面板100的一种示例性平面结构示意图(示例性布 图)。为了清楚起见，图中仅示出了驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、存储电容Cst以及第一稳定电容C1的结构，其它晶体管的结构并未示出。图16为图15中显示面板沿剖面线I-I’的剖视图，图17为图15中显示面板沿剖面线II-II’的剖视图。以下将结合图15-图17对本公开实施例提供的显示面板100进行示范性说明。
这里应该理解的是，在本公开中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，同一构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。例如，本公开的实施例中，可通过同层设置多个元件/部件的图形，可不增加膜层制作数量，利于减小显示面板的厚度，简化制作工艺。
还需要说明的是，本公开所称的A与B电连接包括A是B的一部分以及B是A的一部分的情形。
为了方便说明，在图中以及以下的说明中用T1g、T1s、T1d、T1a分别表示驱动晶体管T1的栅极、第一极、第二极和沟道区，用T2g、T2s、T2d、T2a分别表示数据写入晶体管T2的栅极、第一极、第二极和沟道区，用T3g、T3s、T3d、T3a分别表示阈值补偿晶体管T3的栅极、第一极、第二极和沟道区，用Csa和Csb分别表示存储电容Cst的第一极和第二极。
如图所示，显示面板100包括基板200以及依次层叠设置于基板200上的半导体图案层21、第一绝缘层22、第一导电图案层23、第二绝缘层24、第二导电图案层25、层间绝缘层26、第三导电图案层27。
例如，半导体图案层21包括驱动晶体管T1的有源层T1a、数据写入晶体管T2的有源层T2a及阈值补偿晶体管T3的有源层T3a。
例如，第一导电图案层23包括栅线11、存储电容Cst的第二极Csb、驱动晶体管T1的栅极T1g、数据写入晶体管的栅极T2g和阈值补偿晶体管的栅极T3g。
例如，第二导电图案层25包括存储电容Cst的第一极Csa。
例如，存储电容Cst的第一极Csa与驱动晶体管T1的栅极T1g在垂直于基板200的方向上彼此重叠。
例如，第三导电图案层27包括数据线12和第一电源线13。
如图15所示，栅线11沿第一方向D1延伸，数据线12和第一电源线13沿第二方向D2延伸并且同层设置。例如，第一方向D1和第二方向D2基本垂直。
在本实施例中，第一稳定电容C1包括单独设置的与第一电源线13电连接的第一电容电极18，第一稳定电容C1的第二电容电极由数据线12本身的一部分充当。在其它实施例中，第二电容电极也可以单独设置为与数据线12连接的电极。
例如，如图15和16所示，第一电容电极18设置于数据线12靠近基板200的一侧，并与存储电容Cst的第一极Csa同层设置。第一电容电极18通过穿过层间绝缘层26的第一过孔260与第一电源线13电连接。第一电容电极18和数据线12在垂直于基板200的方向上彼此重叠，从而形成第一稳定电容C1。
例如，在显示面板200的制作过程中，采用自对准工艺，以第一导电图案层23为掩模对半导体图案层21进行导体化处理，例如，采用离子注入对半导体图案层21进行重掺杂，从而使得半导体图案层21未被第一导电图案层23覆盖的部分被导体化，形成驱动晶体管T1的源极区(第一极T1s)和漏极区(第二极T1d)、数据写入晶体管T2的源极区(第一极T2s)和漏极区(第二极T2d)以及阈值补偿晶体管T3的源极区(第一极T3s)和漏极区(第二极T3d)。半导体图案层21被第一导电图案层23覆盖的部分保留半导体特性，形成各晶体管的沟道区T1a、T2a和T3a。
例如，如图15和17所示，显示面板200还包括第一连接电极19，第一连接电极19配置为连接阈值补偿晶体管T3的漏极区和驱动晶体管T1的栅极T1g，从而将阈值补偿晶体管T3的第二极T3d与驱动晶体管T1的栅极T1g电连接。
例如，第一连接电极19与数据线12同层设置，且与数据线12的延伸方向相同。
请一并参阅图15和图16，由于数据线12和第一连接电极19之间，或者或数据线12与阈值补偿晶体管T3的第二极T3d之间存在寄生电容，通过将第一电容电极18设置于数据线12靠近基板200的一侧，该第一电容电极 18可以起到垫高该数据线的作用，可以增大数据线12与第一连接电极19以及阈值补偿晶体管T3的第二极T3d的侧面之间的距离，从而可以降低该寄生电容。例如，由于阈值补偿晶体管T3的第二极T3d与驱动晶体管T1的栅极直接连接，降低该寄生电容有助于降低该数据线对驱动晶体管T1的栅极信号的干扰。
例如，第一连接电极19在第一电容电极18所在层(也即第二导电图案层23)上的正投影与第一电容电极18在垂直于数据线12延伸方向的方向(也即第一方向D1)上彼此重叠。
例如，请参阅图16，第一连接电极19在第一电容电极18所在层(也即第二导电图案层23)上的正投影与第一电容电极18在垂直于数据线12延伸方向的方向(也即第一方向D1)上彼此重叠。
例如，存储电容Cst的第一极Csa上设置有开口250，第一连接电极19通过该开口以及贯穿第二绝缘层24和层间绝缘层26的第二过孔240与驱动晶体管T1的栅极T1g(也即存储电容Cst的第二极Csb)电连接。
例如，第一连接电极19通过贯穿第一绝缘层22、第二绝缘层24及层间绝缘层26的第三过孔220与阈值补偿晶体管T3的第二极T3d电连接。
例如，第一电源线13通过贯穿层间绝缘层26的第四过孔261与存储电容Cst的第一极Csa电连接。
例如，请一并参考图15，存储电容Cst的第一极Csa与数据线13在垂直于基板的方向上彼此重叠，从而构成第四稳定电容C4。由于存储电容Cst的第一极Csa与第一电源线13电连接，该第四稳定电容C4也形成于该第一电源线与该数据线之间，进一步降低了数据线12与驱动晶体管T1栅极之间寄生电容对驱动晶体管T1栅极信号的干扰。例如，第一绝缘层22、第二绝缘层24和层间绝缘层26的材料可以包括无机绝缘材料，例如氮化硅、氮氧化硅等，或者氧化铝、氮化钛等。例如，该绝缘材料还可以包括丙烯酸、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，该绝缘层可以是单层结构也可以是多层结构。
例如，第一导电图案层23、第二导电图案层25、第三导电图案层27、第四导电图案层29、功能信号线、第一导电结构以及第二导电结构的材料包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W) 以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，显示面板100还可以包括设置于基板200与半导体图案层21之间的缓冲层28。例如，基板200为玻璃基板，缓冲层28为二氧化硅，用于防止基板200中杂质(金属离子)扩散到像素电路结构之中。
本公开的实施例中，功能信号线可包括初始化信号线16、发光控制信号线15、复位控制信号线17、第一电源线13、第二电源线14至少之一。
例如，一个实施例中，阵列基板依次包括：基板，多晶硅层，第一栅极绝缘层，第一导电图案层(包括栅线、栅极、存储电容的第二极)，第二栅极绝缘层，第二导电图案层(包括初始化信号线，存储电容的第一极，第一连接电极)，层间绝缘层，第三导电图案层(包括数据线、显示区的第一电源线)，钝化层，平坦化层，第四导电图案层(包括第一电极，第一导电结构，第一电极可为OLED的阳极)，发光层，第二电极(可为OLED的阴极)。功能信号线为第一电源线，第一导电结构与第一电极同层设置，第一导电结构与第一电源线并联。
本公开的实施例中，第一导电结构02也可单独设置。例如，阵列基板包括基板，多晶硅层，第一栅极绝缘层，第一导电图案层(包括栅线、栅极、存储电容的第二极)，第二栅极绝缘层，第二导电图案层(包括初始化信号线，存储电容的第一极，第一连接电极)，层间绝缘层，第三导电图案层(包括数据线、显示区的第一电源线)、有机绝缘层、钝化层、第四导电图案层(包括第一导电结构)、第二平坦化层，OLED的阳极层、发光层、OLED的阴极层。第四导电图案层和第三导电图案层之间间隔有机绝缘层和钝化层，且钝化层直接位于第四导电图案层之下，可以保证第一导电结构所在的层刻蚀完全，并且有机绝缘层能提供尽量的平坦化。该实施例中，功能信号线为第一电源线，第一导电结构与第一电源线并联。
本公开实施例提供的显示面板中的像素电路结构不限于图11中所示，还可以采用其他结构的像素电路结构，例如，还可以不设置第一稳定电容C1、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7至少之一。
例如，本公开实施例提供的显示面板可以应用于手机、平板电脑、电视 机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。例如，该显示面板为有机发光二极管显示面板。
本公开实施例还提供一种显示装置，包括上述显示面板。例如，该显示装置可以为应用该显示面板的手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等电子装置。例如，该显示装置为有机发光二极管显示装置。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种显示面板，包括：
    基板，包括显示区和位于所述显示区至少一侧的周边区，
    多个像素单元，位于所述显示区，每个像素单元包括发光单元和为所述发光单元提供驱动电流的像素电路结构，所述发光单元为电致发光元件；
    功能信号线，与每个像素单元的像素电路结构连接并为所述像素电路结构提供公共电压信号；
    第一导电结构，与所述功能信号线并联，且与所述功能信号线位于不同的层。
  2. 根据权利要求1所述的显示面板，其中，所述多个像素单元沿行方向和列方向延伸以形成多行像素单元和多列像素单元，所述功能信号线包括沿第一方向延伸的第一信号线，所述第一信号线沿一行像素单元或一列像素单元延伸。
  3. 根据权利要求2所述的显示面板，其中，所述功能信号线包括沿第二方向延伸的第二信号线，所述第二信号线位于所述周边区，所述第二信号线与所述第一信号线相连，所述第二方向与所述第一方向交叉。
  4. 根据权利要求3所述的显示面板，其中，所述第二信号线与信号输入电路相连。
  5. 根据权利要求3所述的显示面板，其中，所述第一导电结构包括沿第一方向延伸的第一导电线，所述第一导电线沿一行像素单元或一列像素单元延伸。
  6. 根据权利要求5所述的显示面板，其中，所述第一导电结构包括沿第二方向延伸的第二导电线，所述第二导电线位于所述周边区，所述第二导电线与所述第一导电线连接。
  7. 根据权利要求6所述的显示面板，其中，所述第二导电线和所述第一导电线位于不同的层。
  8. 根据权利要求6所述的显示面板，还包括位于所述第一导电结构和所述功能信号线之间的绝缘层，其中，所述第一导电结构和所述功能信号线通过贯穿位于两者之间的所述绝缘层的过孔相连。
  9. 根据权利要求8所述的显示面板，其中，所述过孔包括位于所述显示 区的显示区过孔和位于所述周边区的周边区过孔至少之一。
  10. 根据权利要求9所述的显示面板，其中，在垂直于所述基板的方向上，所述第一信号线和所述第一导电线具有第一交叠区域，所述显示区过孔位于所述第一交叠区域，所述第一信号线和所述第一导电线通过所述显示区过孔连接。
  11. 根据权利要求9所述的显示面板，其中，在垂直于所述基板的方向上，所述第二信号线和所述第二导电线具有第二交叠区域，所述周边区过孔位于所述第二交叠区域，所述第二信号线和所述第二导电线通过所述周边区过孔连接。
  12. 根据权利要求9所述的显示面板，其中，所述显示区过孔的数量为多个，为每个像素单元设置至少一个显示区过孔。
  13. 根据权利要求9所述的显示面板，其中，所述周边区过孔的数量为多个，所述多个周边区过孔中的每个对应一行像素单元或对应一列像素单元。
  14. 根据权利要求5-13任一项所述的显示面板，其中，所述第一导电线通过转接图案和所述第一信号线连接，所述第一导电线和所述转接图案通过贯穿位于两者之间的绝缘层的过孔连接，所述转接图案和所述第一信号线通过贯穿位于两者之间的绝缘层的过孔连接。
  15. 根据权利要求5-13任一项所述的显示面板，其中，每个发光单元包括第一电极，不同发光单元的第一电极彼此绝缘，所述第一导电结构与所述第一电极同层，所述第一导电线在相邻行像素单元或相邻列像素单元的第一电极的间隙中延伸。
  16. 根据权利要求5-13任一项所述的显示面板，还包括栅线、数据线、第一电源线以及第二电源线，其中，所述像素电路结构包括存储电容、驱动晶体管、数据写入晶体管和阈值补偿晶体管，
    所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极通过第一连接电极与所述阈值补偿晶体管的第二极电连接；
    所述数据写入晶体管的栅极与所述栅线电连接，所述数据写入晶体管的第一极与第二极分别与所述数据线、所述驱动晶体管的第一极电连接；
    所述阈值补偿晶体管的栅极与所述栅线电连接，所述阈值补偿晶体管的第一极和第二极分别与所述驱动晶体管的第二极和栅极电连接；
    所述发光元件的第二电极与所述第二电源线电连接。
  17. 根据权利要求16所述的显示面板，其中，所述第一导电线包括具有第一宽度的第一部分和具有第二宽度的第二部分，所述第一宽度小于所述第二宽度，在垂直于所述基板的方向上，所述第二部分与所述驱动晶体管的沟道区、所述数据写入晶体管的沟道区和所述阈值补偿晶体管的沟道区至少之一重叠。
  18. 根据权利要求16所述的显示面板，还包括初始化信号线、发光控制信号线和复位控制信号线，其中，所述像素电路结构还包括第一发光控制晶体管、第二发光控制晶体管、第一复位晶体管以及第二复位晶体管；
    所述第一发光控制晶体管的栅极与所述发光控制信号线电连接，所述第一发光控制晶体管的第一极与第二极分别与所述第一电源线和所述驱动晶体管的第一极电连接；
    所述第二发光控制晶体管的栅极与所述发光控制信号线电连接，所述第二发光控制晶体管的第一极与第二极分别与所述驱动晶体管的第二极、所述发光元件的第一电极电连接；
    所述第一复位晶体管的栅极与所述复位控制信号线电连接，所述第一复位晶体管的第一极和第二极分别与所述初始化信号线以及所述驱动晶体管的栅极电连接；
    所述第二复位晶体管的栅极与所述复位控制信号线电连接，所述第二复位晶体管的第一极和第二极分别与所述初始化信号线以及所述发光元件的第一电极电连接。
  19. 根据权利要求18所述的显示面板，其中，所述像素电路结构还包括设置于所述数据线和所述第一电源线之间的第一稳定电容，所述第一稳定电容包括第一电容电极；
    所述栅线、所述驱动晶体管的栅极和所述存储电容的第二极同层设置；
    所述第一电容电极、所述初始化信号线、所述存储电容的第一极同层设置；
    所述数据线、所述第一电源线以及所述第一连接电极同层设置；
    所述第一电容电极与所述数据线在垂直于所述基板的方向上彼此重叠。
  20. 根据权利要求18或19所述的显示面板，其中，所述功能信号线包 括初始化信号线、第一电源线、第二电源线至少之一。
  21. 根据权利要求18或19所述的显示面板，其中，
    所述栅线、所述发光控制信号线和所述复位控制信号线位于第一导电图案层；
    所述第一信号线位于第二导电图案层；
    所述数据线、所述第一电源线和所述第二信号线位于第三导电图案层；
    所述第一电极、所述第一导电线和所述第二导电线位于第四导电图案层；
    所述第一信号线和所述第二信号线构成所述初始化信号线，所述第一导电线和所述第二导电线构成所述第一导电结构。
  22. 根据权利要求18或19所述的显示面板，其中，所述阈值补偿晶体管和所述第一复位晶体管为金属氧化物半导体薄膜晶体管。
  23. 根据权利要求21所述的显示面板，还包括第二导电结构，其中，所述功能信号线为所述初始化信号线，所述第二导电结构和所述第一电源线并联，所述第二导电结构位于所述第三导电图案层和所述第四导电图案层之间。
  24. 根据权利要求16所述的显示面板，其中，所述像素电路结构还包括第二稳定电容和第三稳定电容至少之一，其中，
    所述第二稳定电容提供于所述数据线和所述驱动晶体管的第一极之间，
    所述第三稳定电容提供与所述第一电源线和所述驱动晶体管的第一极之间。
  25. 一种显示装置，包括如权利要求1-24任一项所述的显示面板。
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CN111816691A (zh) * 2020-08-28 2020-10-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
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