WO2021168728A1 - 显示面板及其制造方法和显示装置 - Google Patents

显示面板及其制造方法和显示装置 Download PDF

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Publication number
WO2021168728A1
WO2021168728A1 PCT/CN2020/076935 CN2020076935W WO2021168728A1 WO 2021168728 A1 WO2021168728 A1 WO 2021168728A1 CN 2020076935 W CN2020076935 W CN 2020076935W WO 2021168728 A1 WO2021168728 A1 WO 2021168728A1
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Prior art keywords
projection
area
electrode
active layer
region
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PCT/CN2020/076935
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English (en)
French (fr)
Inventor
郭永林
张锴
曹丹
李瀚�
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/076935 priority Critical patent/WO2021168728A1/zh
Priority to US17/419,325 priority patent/US11910668B2/en
Priority to CN202080000189.8A priority patent/CN113826209B/zh
Publication of WO2021168728A1 publication Critical patent/WO2021168728A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • organic light emitting diodes organic light emitting diodes, OLED
  • OLED organic light emitting diodes
  • a display panel including: a substrate and a plurality of sub-pixels on the substrate. At least one sub-pixel includes: a light-emitting element including an anode and a cathode; a first transistor including a first active layer and a first gate connected to a scan line; the first active layer includes a first electrode region, a second An electrode area, and a first channel area located between the first electrode area and the second electrode area, the first electrode area is connected to a data line, and the second electrode area is connected to a power line; a capacitor , Including a first electrode plate and a second electrode plate connected to the power line; a second transistor, including a second active layer and a second gate connected to the first electrode plate, the second active
  • the layer includes a third electrode region, a fourth electrode region, and a second channel region located between the third electrode region and the fourth electrode region, and the third electrode region is connected to the second electrode region , The fourth electrode region is connected to the
  • the third projection includes a first portion and a second portion that are spaced apart, the first portion being located within the first projection, and the second portion being located outside the first projection.
  • the area of the second region is greater than the area of the third region.
  • the shapes of the first area, the second area, and the third area are all rectangles.
  • the display panel further includes a shielding layer, wherein: the orthographic projection of the first electrode region of the first active layer on the substrate is a fifth projection; the third active layer The orthographic projection of the fifth electrode area of the layer on the substrate is a sixth projection; the orthographic projection of the shielding layer on the substrate is a seventh projection, and the seventh projection is at least partially located on the first Between the fifth projection and the sixth projection.
  • At least one of the fifth projection and the sixth projection at least partially overlaps the seventh projection.
  • At least one of the fifth projection and the sixth projection is within the seventh projection.
  • the first active layer and the third active layer are located on the same layer, and the shielding layer is located between the same layer and the substrate.
  • the shielding layer includes a metal layer.
  • the metal layer includes a first metal layer, a second metal layer, and a third metal layer located between the first metal layer and the second metal layer.
  • the first metal layer and the second metal layer are made of the same material and different from the third metal layer.
  • the material of the first metal layer and the second metal layer includes Ti, and the material of the third metal layer includes Al.
  • the at least one sub-pixel further includes at least one of the following: a fourth transistor including a fourth active layer and a fourth gate connected to the scan line, the fourth active layer Comprising a seventh electrode area, an eighth electrode area, and a fourth channel area located between the seventh electrode area and the eighth electrode area, the seventh electrode area is connected to the second gate, The eighth electrode region is connected to the fourth electrode region;
  • the fifth transistor includes a fifth active layer and a fifth gate connected to a control line, and the fifth active layer includes a ninth electrode region, a Ten electrode area, and a fifth channel area located between the ninth electrode area and the tenth electrode area, the ninth electrode area is connected to the power line, and the tenth electrode area is connected to the The second electrode area;
  • the first active layer, the second active layer, the third active layer, the fourth active layer, the fifth active layer, the sixth active layer, and the seventh active layer are located at The same layer.
  • the second electrode plate and the initialization voltage line are located on the same layer.
  • the scan line, the first electrode plate and the reset line are located on the same layer.
  • the data line and the power line are located on the same layer.
  • two of at least one of the following three groups are integrated: the scan line and the first grid; the first electrode plate and the second grid; the reset Line and the third gate.
  • a display device including: the display panel described in any one of the above embodiments.
  • a method of manufacturing a display panel including: providing a substrate; and forming a plurality of sub-pixels on the substrate. At least one sub-pixel includes: a light-emitting element including an anode and a cathode; a first transistor including a first active layer and a first gate connected to a scan line; the first active layer includes a first electrode region, a second An electrode area, and a first channel area located between the first electrode area and the second electrode area, the first electrode area is connected to a data line, and the second electrode area is connected to a power line; a capacitor , Including a first electrode plate and a second electrode plate connected to the power line; a second transistor, including a second active layer and a second gate connected to the first electrode plate, the second active
  • the layer includes a third electrode region, a fourth electrode region, and a second channel region located between the third electrode region and the fourth electrode region, and the third electrode region is connected to the second electrode
  • FIG. 1 is a schematic diagram showing the structure of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing the structure of a sub-pixel according to an embodiment of the present disclosure
  • 3 to 6 are schematic diagrams respectively showing the layout of a certain layer in the sub-pixels according to some embodiments of the present disclosure
  • FIG. 7A is a schematic diagram showing the layout of the layer overlay shown in FIG. 3, FIG. 5, and FIG. 6 in sub-pixels according to an embodiment of the present disclosure
  • FIG. 7B is a schematic diagram showing the layout of the layer overlay shown in FIG. 3 to FIG. 6 in sub-pixels according to an embodiment of the present disclosure
  • FIG. 8A is a schematic diagram showing projections of partial layers of multiple layers in a sub-pixel on a substrate according to an embodiment of the present disclosure
  • FIG. 8B is an enlarged schematic diagram showing the first area A1, the second area A2, and the third area A3 shown in FIG. 8A;
  • Fig. 8C is a schematic cross-sectional view taken along C-C' shown in Fig. 7B;
  • FIG. 9A is a schematic diagram showing the structure of a display panel according to another embodiment of the present disclosure.
  • FIG. 9B is a schematic diagram showing the projection of partial layers of multiple layers in a sub-pixel on a substrate according to another embodiment of the present disclosure.
  • a specific component when it is described that a specific component is located between the first component and the second component, there may or may not be an intermediate component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is connected to another component, the specific component may be directly connected to the other component without an intervening component, or may not be directly connected to the other component but with an intervening component.
  • FIG. 1 is a schematic diagram showing the structure of a display panel according to an embodiment of the present disclosure.
  • the display panel includes a substrate 11 and a plurality of sub-pixels 12 on the substrate 11. At least one sub-pixel 12 among the plurality of sub-pixels 12 in the display panel may include a structure as shown in FIG. 2.
  • FIG. 2 is a schematic diagram showing the structure of a sub-pixel according to an embodiment of the present disclosure.
  • 3 to 6 are schematic diagrams respectively showing the layout of a certain layer in the sub-pixels according to some embodiments of the present disclosure.
  • FIG. 7A is a schematic diagram showing the layout of the layer overlay shown in FIG. 3, FIG. 5, and FIG. 6 in sub-pixels according to an embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram showing the layout of the layer overlay shown in FIG. 3 to FIG. 6 in the sub-pixel according to an embodiment of the present disclosure.
  • the sub-pixel 12 may include a light-emitting element D, a first transistor T1, a capacitor C, a second transistor T2, and a third transistor T3.
  • the light emitting element D includes an anode D1 and a cathode D2.
  • the light-emitting element D may be an OLED.
  • the first transistor T1 may also be referred to as a switching transistor
  • the second transistor T2 may also be referred to as a driving transistor
  • the third transistor T3 may also be referred to as a reset transistor.
  • the first transistor T1 is configured to transmit the data signal from the data line Data to the second transistor T2 in response to the scan signal of the gate line Gate when turned on.
  • the second transistor T2 is configured to transmit the driving current Id to the light-emitting element D when turned on to drive the light-emitting element D to emit light.
  • the third transistor T3 is configured to reset the voltage of the gate G2 of the second transistor T2 to the voltage of the initialization voltage line Vinit when turned on in response to the reset signal of the reset line Reset.
  • the sub-pixel 12 may further include one or more of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.
  • the fourth transistor T4 may also be referred to as a compensation transistor
  • the fifth transistor T5 may also be referred to as a drive control transistor
  • the sixth transistor T6 may also be referred to as an emission control transistor
  • the seventh transistor T7 may also be referred to as a bypass transistor.
  • the fourth transistor T4 is configured to respond to the scan signal of the scan line Gate and make the second transistor T2 in a diode connection state when turned on.
  • the fifth transistor T5 and the sixth transistor T6 are configured to make the emission current Id flow to the light emitting element D in response to the control signal of the control line EM when turned on.
  • the seventh transistor T7 is configured to respond to the reset signal of the reset line Reset, and when turned on, causes a part of the driving current Id to flow as the bypass current Ibp.
  • the third gate G3 of the third transistor T3 and the seventh gate G7 of the seventh transistor T7 shown in FIG. 2 are both connected to the same reset line Reset.
  • the seventh gate G7 of the seventh transistor T7 may be connected to another reset line different from the reset line Reset.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-channel thin film transistors. In other embodiments, one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be N Channel thin film transistor.
  • the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be as shown in FIG. 3 .
  • the material of the active layer may include, for example, polysilicon, such as low-temperature polysilicon.
  • the active layer of each transistor includes two electrode regions and a channel region located between the two electrode regions.
  • one of the two electrode regions is a source region, and the other is a drain region.
  • the doping concentration in the two electrode regions is greater than the doping concentration in the channel region.
  • each of the two electrode regions is a conductor region, and the channel region is a semiconductor region.
  • the first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to the scan line Gate.
  • the scan line Gate and the first gate G1 may be integrally provided.
  • the first active layer ACT1 includes a first electrode area ACT11, a second electrode area ACT12, and a first channel area ACT13 located between the first electrode area and the second electrode area.
  • the first electrode area ACT11 is connected to the data line Data
  • the second electrode area ACT12 is connected to the power supply line VDD.
  • the first electrode area ACT11 may be connected to the data line Data via the via V1 shown in FIG. 7B.
  • the second electrode region ACT12 may be connected to the power supply line VDD via the fifth active layer ACT5 of the fifth transistor T5.
  • the fifth active layer ACT5 may be connected to the power supply line VDD via the via V2 shown in FIG. 7B.
  • the data line Data and the power supply line VDD may be located in the same layer.
  • the capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to the power supply line VDD.
  • the second electrode plate C2 may be connected to the power supply line VDD via the via V3 shown in FIG. 7B.
  • the second transistor T2 includes a second active layer ACT2 and a second gate G2 connected to the first electrode plate C1.
  • the first electrode plate C1 and the second grid G2 may be integrally provided.
  • the second active layer ACT2 includes a third electrode area ACT21, a fourth electrode area ACT22, and a second channel area ACT23 located between the third electrode area ACT21 and the fourth electrode area ACT22.
  • the third electrode area ACT21 is connected to the second electrode area ACT12
  • the fourth electrode area ACT22 is connected to the anode D1.
  • the third electrode area ACT21 and the second electrode area ACT12 may be integrally provided.
  • the third electrode region ACT21 may be connected to the power supply line VDD via the fifth active layer ACT5 of the fifth transistor T5.
  • the third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to the reset line Reset.
  • the reset line Reset and the third gate G3 may be integrally provided.
  • the third active layer ACT3 includes a fifth electrode area ACT31, a sixth electrode area ACT32, and a third channel area ACT33 located between the fifth electrode area ACT31 and the sixth electrode area ACT32.
  • the fifth electrode area ACT31 is connected to the first electrode plate C1, and the sixth electrode area ACT32 is connected to the initialization voltage line Vinit.
  • the fifth electrode area ACT31 may be connected to the first connector CT1 via the via hole V4 shown in FIG.
  • the first electrode plate C1 may be connected to the first connector CT1 via the via hole V5 shown in FIG. 7B.
  • the sixth electrode area ACT32 may be connected to the second connector CT2 via the via hole V6 shown in FIG. 7B, and the initialization voltage line Vinit may be connected to the second connector CT2 via the via hole V7 shown in FIG. 7B.
  • the first connector CT1, the second connector CT2, the data line Data, and the power line VDD may be located on the same layer.
  • the scan line Gate, the first electrode plate C1, and the reset line Reset may be located in the same layer.
  • the second electrode plate C2 and the initialization voltage line Vinit may be located on the same layer.
  • the first channel region ACT13 may be an area where the first active layer ACT1 overlaps the scan line Gate
  • the second channel region ACT23 may be an area where the second active layer ACT2 overlaps the first electrode plate C1
  • the third channel region ACT33 may be a region where the third active layer ACT3 overlaps the reset line Reset
  • the fourth channel region ACT43 may be a region where the fourth active layer ACT4 overlaps the scan line Gate.
  • FIG. 8A is a schematic diagram showing the projection of partial layers of multiple layers in a sub-pixel on a substrate according to an embodiment of the present disclosure. It should be noted that in order to clearly show the positional relationship between the power line VDD, the reset line Reset, the data line Data and the third active layer ACT3, FIG. 8A omits other components in some layers.
  • the orthographic projection of the power line VDD on the substrate 11 is the first projection VDD'
  • the orthographic projection of the reset line Reset on the substrate 11 is the second projection Reset'
  • the orthographic projection of ACT33 on the substrate 11 is the third projection ACT33'
  • the orthographic projection of the data line Data on the substrate 11 is the fourth projection Data'.
  • the third projection ACT33' may include a first part ACT331' and a second part ACT332' that are spaced apart. The first part ACT331' is located within the first projection VDD', and the second part ACT332' is located outside the first projection VDD'.
  • the third gate G3 of the third transistor T3 includes two gates, of which the orthographic projection of one gate on the substrate 11 completely overlaps the first portion ACT331', and the orthographic projection of the other gate on the substrate 11 is The second part ACT332' completely overlaps.
  • the area where the first projection VDD', the second projection Reset' and the third projection ACT33' overlap each other is the first area A1, and the first projection VDD' overlaps the second projection Reset' and is different from the third projection ACT33'.
  • the overlapping area includes a second area A2 and a third area A3 that are both adjacent to the first area A1.
  • the second area A2 is located on the side of the first area A1 close to the fourth projection Data'
  • the third area A3 is located on the side of the first area A1 away from the fourth projection Data'.
  • the shapes of the first area A1, the second area A2, and the third area A3 may all be rectangular. It should be understood that the rectangle here refers to a rectangle within the process deviation range, that is, roughly a rectangle. It should also be understood that the present disclosure is not limited to this.
  • FIG. 8B is an enlarged schematic diagram showing the first area A1, the second area A2, and the third area A3 shown in FIG. 8A.
  • the area of the second area A2 is not smaller than the area of the third area A3.
  • the area of the second area A2 is equal to the area of the third area A3.
  • the area of the second area A2 is larger than the area of the third area A3.
  • the area of the second area A2 is not less than the area of the third area A3
  • the first electrode area ACT11 of the first active layer ACT1 and the fifth electrode area ACT31 of the third active layer ACT3 are enlarged. Therefore, the capacitance between the first electrode area ACT11 and the fifth electrode area ACT31 is reduced, and the crosstalk of the display panel is reduced.
  • the distance between the first electrode area ACT11 and the fifth electrode area ACT31 can be expressed as a.
  • the crosstalk corresponding to different distances a can be obtained.
  • the following table shows the correspondence between several typical values of a and crosstalk.
  • the following table also shows c1 and c2 corresponding to different a.
  • c1 represents the capacitance between the first electrode area ACT11 and the fifth electrode area ACT31 in the same sub-pixel
  • c2 represents the difference between the first electrode area ACT11 in one sub-pixel 12 and the fifth electrode area ACT31 in another sub-pixel 12 Between the capacitance.
  • a may be 2.5 microns to 5 microns, for example, 2.74 microns, 3.26 microns, 3.58 microns, 3.83 microns, and so on.
  • a in order to balance the resolution of the display panel and the crosstalk of the display panel, a may be 3.26 microns.
  • the width of the data line Data may be, for example, 2 micrometers to 3 micrometers, for example about 2.5 micrometers.
  • the ratio value in the above table can reflect the magnitude of crosstalk.
  • crosstalk can be measured by the size of Ib/Ia.
  • Ia is the current flowing through the light-emitting element in a certain sub-pixel when the display panel displays a white screen.
  • Ib is the current flowing through the light-emitting element in the sub-pixel when a black screen is displayed in a partial area (for example, a certain rectangular area) adjacent to the sub-pixel of the display panel, and a white screen is displayed in other areas.
  • different parameters may be used to reflect the crosstalk of the display panel.
  • Fig. 8C is a schematic cross-sectional view taken along C-C' shown in Fig. 7B.
  • a buffer layer 21 may be provided on the substrate 11, such as an inorganic layer such as silicon oxide and silicon nitride.
  • the first active layer ACT1 and the third active layer ACT3 are spaced apart on the buffer layer 21.
  • the first insulating layer GI1 covers the first active layer ACT1 and the third active layer ACT3.
  • the second insulating layer GI1 is located on the first insulating layer GI1.
  • the interlayer insulating layer ILD is disposed on the second insulating layer GI1.
  • the data line Data and the power supply line VDD are spaced apart on the interlayer insulating layer ILD.
  • the material of the first insulating layer GI1 and the second insulating layer GI1 may include silicon oxide or the like.
  • the positions of the first active layer ACT1 and the third active layer ACT3 can be adjusted to reduce the first electrode region ACT11 and the third active layer in the first active layer ACT1.
  • the display panel in order to further reduce the crosstalk of the display panel, may further include a shielding layer.
  • FIG. 9A is a schematic diagram showing the structure of a display panel according to another embodiment of the present disclosure.
  • FIG. 9A only shows the first active layer ACT1 and the third active layer ACT3 in one sub-pixel 12 in a simplified manner, and does not show other active layers.
  • the display panel further includes a shielding layer 13.
  • the first active layer ACT1 of the first transistor T1 and the third active layer ACT3 of the third transistor T3 are located in the same layer.
  • FIG. 9A schematically shows the shielding layer 13 as being located between the same layer where the first active layer ACT1 and the third active layer ACT3 are located and the substrate 11. It should be understood that in other implementation manners, the shielding layer 13 may also be located on the side of the same layer where the first active layer ACT1 and the third active layer ACT3 are located away from the substrate 11, that is, the upper side.
  • FIG. 9B is a schematic diagram showing the projection of partial layers of multiple layers in a sub-pixel on a substrate according to another embodiment of the present disclosure. The positional relationship between the shielding layer 13 and other layers will be introduced below in conjunction with FIG. 9B.
  • FIG. 9B only shows the first active layer ACT1, the third active layer ACT1 and the third active layer ACT3.
  • the orthographic projection of the first active layer ACT1 on the substrate 11 is the projection ACT1'
  • the orthographic projection of the first electrode area ACT11 of the first active layer ACT1 on the substrate 11 is the projection ACT11'
  • the first active layer ACT1 The orthographic projection of the second electrode region ACT12 on the substrate 11 is the projection ACT12'
  • the orthographic projection of the first channel region ACT13 of the first active layer ACT1 on the substrate 11 is the projection ACT13'.
  • the orthographic projection of the third active layer ACT3 on the substrate 11 is the projection ACT3'
  • the orthographic projection of the fifth electrode area ACT31 of the third active layer ACT3 on the substrate 11 is the projection ACT31'
  • the third active layer ACT3 is the projection ACT3'.
  • the orthographic projection of the six-electrode region ACT32 on the substrate 11 is the projection ACT32'
  • the orthographic projection of the third channel region ACT33 of the third active layer ACT3 on the substrate 11 is the projection ACT33'.
  • the orthographic projection of the first electrode area ACT11 on the substrate 11 is called the fifth projection ACT11'
  • the orthographic projection of the fifth electrode area ACT31 on the substrate 11 is called the sixth projection ACT31'
  • the shielding layer 13 is on the substrate.
  • the orthographic projection on 11 is called the seventh projection 13'.
  • the seventh projection 13' is at least partially located between the fifth projection ACT11' and the sixth projection ACT31'.
  • the seventh projection 13' may be partially located between the fifth projection ACT11' and the sixth projection ACT31'.
  • the seventh projection 13' may be entirely located between the fifth projection ACT11' and the sixth projection ACT31'.
  • the presence of the shielding layer 13 can further reduce the capacitance between the first electrode area ACT31 and the fifth electrode area ACT32, thereby further reducing the crosstalk of the display panel.
  • the shielding layer 13 includes a metal layer.
  • the material of the metal layer may include Mo.
  • the metal layer may include a first metal layer 131, a second metal layer 132, and The third metal layer 133 between the first metal layer 131 and the second metal layer.
  • the materials of the first metal layer 131 and the second metal layer 132 are the same, and the materials of the first metal layer 131 and the third metal layer 133 are different.
  • the material of the first metal layer 1311 and the second metal layer 32 may include Ti, and the material of the third metal layer 133 may include Al.
  • At least one of the fifth projection ACT11' and the sixth projection ACT31' may at least partially overlap with the seventh projection 13'.
  • the fifth projection ACT11' partially overlaps the seventh projection 13'
  • the sixth projection ACT31' does not overlap the seventh projection 13'.
  • the fifth projection ACT11' partially overlaps the seventh projection 13'
  • the sixth projection ACT31' partially overlaps the seventh projection 13'.
  • At least one of the fifth projection ACT1' and the sixth projection ACT3' It can be within the seventh projection 13'.
  • one of the fifth projection ACT1' and the sixth projection ACT3' is within the seventh projection 13', and the other is not within the seventh projection 13'.
  • both the fifth projection ACT1' and the sixth projection ACT3' are within the seventh projection 13'.
  • At least one sub-pixel 12 may further include one or one of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. Multiple.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 will be introduced below in conjunction with FIG. 2 and FIG. 3.
  • the fourth transistor T4 includes a fourth active layer ACT4 and a fourth gate G4 connected to the scan line Gate.
  • the scan line Gate and the fourth gate G4 may be integrally provided.
  • the fourth active layer ACT4 includes a seventh electrode area ACT41, an eighth electrode area ACT42, and a fourth channel area ACT43 located between the seventh electrode area ACT41 and the eighth electrode area ACT42.
  • the seventh electrode area ACT41 is connected to the second gate G2, and the eighth electrode area ACT42 is connected to the fourth electrode area ACT22.
  • the seventh electrode region ACT41 may be connected to the first connector CT1 through the via hole V4 shown in FIG.
  • the second gate G2 may be connected to the first connector CT1 through the via hole V5 shown in FIG. 7B.
  • the seventh electrode area ACT41 and the fifth electrode area ACT31 may be integrally provided.
  • the eighth electrode area ACT42 and the fourth electrode area ACT22 may be integrally provided.
  • the fourth channel region ACT43 may include two spaced apart portions, that is, the fourth gate G4 may include two gates.
  • the fifth transistor T5 includes a fifth active layer ACT5 and a fifth gate G5 connected to the control line EM.
  • the fifth active layer ACT5 includes a ninth electrode area ACT51, a tenth electrode area ACT52, and a fifth channel area ACT53 located between the ninth electrode area ACT51 and the tenth electrode area ACT52.
  • the ninth electrode area ACT51 is connected to the power supply line VDD
  • the tenth electrode area ACT52 is connected to the second electrode area ACT12.
  • the ninth electrode area ACT51 may be connected to the power supply line VDD via the via V2 shown in FIG. 7B.
  • the tenth electrode area ACT52 may be connected to the second electrode area ACT12 via the third electrode area ACT21.
  • the control line EM, the scan line Gate, the first electrode plate C1, and the reset line Reset may be located in the same layer.
  • the sixth transistor T6 includes a sixth active layer ACT6 and a sixth gate G6 connected to the control line EM.
  • the sixth active layer ACT6 includes an eleventh electrode area ACT61, a twelfth electrode area ACT62, and a sixth channel area located between the eleventh electrode area ACT61 and the twelfth electrode area ACT62.
  • ACT63 The eleventh electrode area ACT61 is connected to the fourth electrode area ACT22, and the twelfth electrode area ACT62 is connected to the anode D1.
  • the eleventh electrode area ACT61 and the fourth electrode area ACT22 may be integrally provided.
  • the twelfth electrode region ACT62 may be connected to the conductive layer M (for example, a metal layer) via the via hole V8 shown in FIG. 7B, and the conductive layer M may be connected to the anode D1 via other via holes.
  • the conductive layer M, the first connection member CT1, the second connection member CT2, the data line Data, and the power supply line VDD may be located in the same layer.
  • the seventh transistor T7 includes a seventh active layer ACT7 and a seventh gate G7 connected to the reset line Reset.
  • the reset line Reset and the seventh gate G7 may be integrally provided.
  • the seventh active layer ACT7 includes a thirteenth electrode area ACT71, a fourteenth electrode area ACT72, and a seventh channel area located between the thirteenth electrode area ACT71 and the fourteenth electrode area ACT72.
  • ACT73 The thirteenth electrode area ACT71 is connected to the twelfth electrode area ACT62, and the fourteenth electrode area ACT72 is connected to the initialization voltage line Vinit.
  • the fourteenth electrode area ACT72 may be connected to the second connector CT2 via the via hole V6 shown in FIG. 7B, and the initialization voltage line Vinit may be connected to the second connector CT2 via the via hole V7 shown in FIG. 7B.
  • the fourteenth electrode area ACT72 and the sixth electrode area ACT32 may be integrally provided.
  • the fifth channel region ACT53 may be a region where the fifth active layer ACT5 overlaps the control line EM
  • the sixth channel region ACT63 may be a region where the sixth active layer ACT6 overlaps the control line EM
  • the seventh channel region ACT73 may be a region where the seventh active layer ACT7 overlaps the reset line.
  • the first active layer ACT1, the second active layer ACT2, the third active layer ACT3, the fourth active layer ACT4, the fifth active layer ACT5, and the sixth active layer ACT6 and the seventh active layer ACT7 may be located in the same layer.
  • sub-pixels include T1, T2, T3, T4, T5, T6, and T7, and the transistors T1, T2, T3, T4, T5, T6, and T7 are all P-type grooves. Road transistor.
  • the third transistor T3 is turned on in response to the reset signal of the reset line Reset, and the second gate G2 of the second transistor T2 is connected to the initialization voltage line Vinit via the third transistor T3. In this way, the voltage of the second gate G2 of the driving transistor T1 is reset to the voltage of the initialization voltage line Vinit.
  • the first transistor T1 and the fourth transistor T4 are turned on in response to the scan signal of the scan line Gate.
  • the second transistor T2 is in a diode connection state and is forward biased.
  • the voltage of the second gate G2 of the second transistor T2 is the sum of the voltage Vdata of the data signal from the data line Data and the threshold voltage Vth (negative number) of the second transistor T2, that is, Vdata+Vth.
  • the voltage of the first electrode plate C1 of the capacitor Cst is Vdata+Vth
  • the voltage of the second electrode plate C2 of the capacitor Cst is the voltage ELVDD of the power supply line VDD.
  • the capacitor Cst is charged with electric charge corresponding to the voltage difference between the first electrode plate C1 and the second electrode plate C2.
  • the fifth transistor T5 and the sixth transistor T6 are turned on in response to the control signal of the control line EM.
  • the driving current Id is generated in response to the voltage difference between the voltage of the second gate G2 of the second transistor T2 and the voltage of the power supply line VDD, and the driving current Id is supplied to the light emitting element D through the sixth transistor T6.
  • the gate-source voltage Vgs of the second transistor T2 is maintained at (Vdata+Vth)-ELVDD.
  • the drive current Id is proportional to (Vdata-ELVDD) 2 . Therefore, the driving current Id is independent of the threshold voltage Vth of the first transistor T1.
  • the seventh transistor T7 is turned on in response to the reset signal of the reset line Reset.
  • the seventh transistor T7 may be turned on simultaneously with the first transistor T1 and the fourth transistor T4.
  • a part of the driving current Id can be used as a bypass current Ibp to flow out through the seventh transistor T7.
  • the present disclosure also provides a display device, which may include the display panel of any one of the above embodiments.
  • the display device may be, for example, any product or component with a display function, such as a mobile terminal, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and electronic paper.
  • the embodiments of the present disclosure also provide a method for manufacturing a display panel.
  • the manufacturing method of the display panel includes: providing a substrate; and forming a plurality of sub-pixels on the substrate.
  • the structure of at least one sub-pixel includes a light-emitting element D, a first transistor T1, a capacitor C, a second transistor T2, and a third transistor T3.
  • the light-emitting element D includes an anode D1 and a cathode D2.
  • the first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to the scan line Gate.
  • the first active layer ACT1 includes a first electrode area ACT11, a second electrode area ACT12, and a In the first channel region ACT13 between the second electrode regions, the first electrode region ACT11 is connected to the data line Data, and the second electrode region ACT12 is connected to the power line VDD.
  • the capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to the power supply line VDD.
  • the second transistor T2 includes a second active layer ACT2 and a second gate G2 connected to the first electrode plate C1.
  • the second active layer ACT2 includes a third electrode area ACT21, a fourth electrode area ACT22, and a third electrode
  • the second channel area ACT23 between the area ACT21 and the fourth electrode area ACT22, the third electrode area ACT21 is connected to the second electrode area ACT12, and the fourth electrode area ACT22 is connected to the anode D1.
  • the third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to the reset line Reset.
  • the third active layer ACT3 includes a fifth electrode area ACT31, a sixth electrode area ACT32, and a fifth electrode area ACT31. Between the third channel region ACT33 and the sixth electrode region ACT32, the fifth electrode region ACT31 is connected to the first electrode plate C1, and the sixth electrode region ACT32 is connected to the initialization voltage line Vinit.
  • the orthographic projection of the power line VDD on the substrate 11 is the first projection VDD'
  • the orthographic projection of the reset line Reset on the substrate 11 is the second projection Reset'
  • the orthographic projection of ACT33 on the substrate 11 is the third projection ACT33'
  • the orthographic projection of the data line Data on the substrate 11 is the fourth projection Data'.
  • the area where the first projection VDD', the second projection Reset' and the third projection ACT33' overlap each other is the first area A1, and the first projection VDD' overlaps the second projection Reset' and is different from the third projection ACT33'.
  • the overlapping area includes a second area A2 and a third area A3 that are both adjacent to the first area A1.
  • the second area A2 is located on the side of the first area A1 close to the fourth projection Data'
  • the third area A3 is located on the side of the first area A1 away from the fourth projection Data'.
  • the area of the second area A2 is not less than the area of the third area A3.
  • the first electrode area ACT11 of the first active layer ACT1 and the second area of the third active layer ACT3 are enlarged.
  • the distance between the five electrode areas ACT31 reduces the capacitance between the first electrode area ACT11 and the fifth electrode area ACT31, and reduces the crosstalk of the display panel.

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Abstract

一种显示面板及其制造方法和显示装置。显示面板中至少一个子像素（12）包括：包括阳极（D1）的发光元件（D）；第一晶体管（T1），包括第一有源层（ACT1），包括连接至数据线（Data）的第一电极区（ACT11）、连接至电源线（VDD）的第二电极区（ACT12）及第一沟道区（ACT13）；电容器（C），包括第一电极板（C1）和第二电极板（C2）；第二晶体管（T2），包括第二有源层（ACT2），包括第三电极区（ACT21）、第四电极区（ACT22）及第二沟道区（ACT23）；第三晶体管（T3），包括第三有源层（ACT3）和连接至复位线（Reset）的第三栅极（G3），第三有源层（ACT3）包括第五电极区（ACT31）、第六电极区（ACT32）及第三沟道区（ACT33）。电源线（VDD）、复位线（Reset）、第三沟道区（ACT33）和数据线（Data）在基板（11）上正投影分别为第一投影（VDD'）、第二投影（Reset'）、第三投影（ACT33'）和第四投影（Data'）。第一投影（VDD'）、第二投影（Reset'）和第三投影（ACT33'）彼此交叠的区域为第一区域（A1），第一投影（VDD'）与第二投影（Reset'）交叠且与第三投影（ACT33'）不交叠的区域包括第三区域（A3）和面积不小于第三区域（A3）的第二区域（A2）。

Description

显示面板及其制造方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制造方法和显示装置。
背景技术
近年来，由于具有自发光、广视角、短反应时间、高发光效率、广色域、低工作电压、可大尺寸制作、可柔性化、制程简单等特性，有机发光二极管(organic light emitting diode,OLED)显示面板被广泛应用。
发明内容
根据本公开实施例的一方面，提供一种显示面板，包括：基板和位于所述基板上的多个子像素。至少一个子像素包括：发光元件，包括阳极和阴极；第一晶体管，包括第一有源层和连接至扫描线的第一栅极，所述第一有源层包括第一电极区、第二电极区、以及位于所述第一电极区和所述第二电极区之间的第一沟道区，所述第一电极区连接至数据线，所述第二电极区连接至电源线；电容器，包括第一电极板和连接至所述电源线的第二电极板；第二晶体管，包括第二有源层和连接至所述第一电极板的第二栅极，所述第二有源层包括第三电极区、第四电极区、以及位于所述第三电极区和所述第四电极区之间的第二沟道区，所述第三电极区连接至所述第二电极区，所述第四电极区连接至所述阳极；和第三晶体管，包括第三有源层和连接至复位线的第三栅极，所述第三有源层包括第五电极区、第六电极区、以及位于所述第五电极区和所述第六电极区之间的第三沟道区，所述第五电极区连接至所述第一电极板，所述第六电极区连接至初始化电压线；其中：所述电源线在所述基板上的正投影为第一投影，所述复位线在所述基板上的正投影为第二投影，所述第三沟道区在所述基板上的正投影为第三投影，所述数据线在所述基板上的正投影为第四投影；所述第一投影、所述第二投影和所述第三投影彼此交叠的区域为第一区域，所述第一投影与所述第二投影交叠、且与所述第三投影不交叠的区域包括与所述第一区域均邻接的第二区域和第三区域，所述第二区域位于所述第一区域靠近所述第四投影的一侧，所述第三区域位于所述第一区域远离所述第四投影的一侧，所述第二区域的面积不小于所述第三区域的面积。
在一些实施例中，所述第三投影包括间隔开的第一部分和第二部分，所述第一部分位于所述第一投影之内，所述第二部分位于所述第一投影之外。
在一些实施例中，所述第二区域的面积大于所述第三区域的面积。
在一些实施例中，所述第一区域、所述第二区域和所述第三区域的形状均为矩形。
在一些实施例中，所述显示面板还包括屏蔽层，其中：所述第一有源层的所述第一电极区在所述基板上的正投影为第五投影；所述第三有源层的所述第五电极区在所述基板上的正投影为第六投影；所述屏蔽层在所述基板上的正投影为第七投影，所述第七投影至少部分地位于所述第五投影和所述第六投影之间。
在一些实施例中，所述第五投影和所述第六投影中的至少一个与所述第七投影至少部分地交叠。
在一些实施例中，所述第五投影和所述第六投影中的至少一个在所述第七投影之内。
在一些实施例中，所述第一有源层和所述第三有源层位于同一层，所述屏蔽层位于所述同一层与所述基板之间。
在一些实施例中，所述屏蔽层包括金属层。
在一些实施例中，所述金属层包括第一金属层、第二金属层、以及位于所述第一金属层和所述第二金属层之间的第三金属层。
在一些实施例中，所述第一金属层和所述第二金属层的材料相同，并且和所述第三金属层的材料不同。
在一些实施例中，所述第一金属层和所述第二金属层的材料包括Ti，所述第三金属层的材料包括Al。
在一些实施例中，所述至少一个子像素还包括下列中的至少一个：第四晶体管，包括第四有源层和连接至所述扫描线的第四栅极，所述第四有源层包括第七电极区、第八电极区、以及位于所述第七电极区和所述第八电极区之间的第四沟道区，所述第七电极区连接至所述第二栅极，所述第八电极区连接至所述第四电极区；第五晶体管，包括第五有源层和连接至控制线的第五栅极，所述第五有源层包括第九电极区、第十电极区、以及位于所述第九电极区和所述第十电极区之间的第五沟道区，所述第九电极区连接至所述电源线，所述第十电极区连接至所述第二电极区；第六晶体管，包括第六有源层和连接至控制线的第六栅极，所述第六有源层包括第十一电极区、第十二电极区、以及位于所述第十一电极区和所述第十二电极区之间的第六沟道区，所述第 十一电极区连接至所述第四电极区，所述第十二电极区连接至所述阳极；第七晶体管，包括第七有源层和连接至所述复位线的第七栅极，所述第七有源层包括第十三电极区、第十四电极区、以及位于所述第十三电极区和所述第十四电极区之间的第七沟道区，所述第十三电极区连接至所述第十二电极区，所述第十四电极区连接至所述初始化电压线。
在一些实施例中，所述第一有源层、第二有源层、第三有源层、第四有源层、第五有源层、第六有源层和第七有源层位于同一层。
在一些实施例中，所述第二电极板和所述初始化电压线位于同一层。
在一些实施例中，所述扫描线、所述第一电极板和所述复位线位于同一层。
在一些实施例中，所述数据线和所述电源线位于同一层。
在一些实施例中，下列三组中的至少一组中的两个一体设置：所述扫描线与所述第一栅极；所述第一电极板与所述第二栅极；所述复位线与所述第三栅极。
根据本公开实施例的另一方面，提供一种显示装置，包括：上述任意一个实施例所述的显示面板。
根据本公开实施例的又一方面，提供一种显示面板的制造方法，包括：提供基板；和在所述基板上形成多个子像素。至少一个子像素包括：发光元件，包括阳极和阴极；第一晶体管，包括第一有源层和连接至扫描线的第一栅极，所述第一有源层包括第一电极区、第二电极区、以及位于所述第一电极区和所述第二电极区之间的第一沟道区，所述第一电极区连接至数据线，所述第二电极区连接至电源线；电容器，包括第一电极板和连接至所述电源线的第二电极板；第二晶体管，包括第二有源层和连接至所述第一电极板的第二栅极，所述第二有源层包括第三电极区、第四电极区、以及位于所述第三电极区和所述第四电极区之间的第二沟道区，所述第三电极区连接至所述第二电极区，所述第四电极区连接至所述阳极；和第三晶体管，包括第三有源层和连接至复位线的第三栅极，所述第三有源层包括第五电极区、第六电极区、以及位于所述第五电极区和所述第六电极区之间的第三沟道区，所述第五电极区连接至所述第一电极板，所述第六电极区连接至初始化电压线；其中：所述电源线在所述基板上的正投影为第一投影，所述复位线在所述基板上的正投影为第二投影，所述第三沟道区在所述基板上的正投影为第三投影，所述数据线在所述基板上的正投影为第四投影；所述第一投影、所述第二投影和所述第三投影彼此交叠的区域为第一区域，所述第一投影与所述第二投影交叠、且与所述第三投影不交叠的区域包括与所述第一区域均邻接的第 二区域和第三区域，所述第二区域位于所述第一区域靠近所述第四投影的一侧，所述第三区域位于所述第一区域远离所述第四投影的一侧，所述第二区域的面积不小于所述第三区域的面积。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是示出根据本公开一个实施例的显示面板的结构示意图；
图2是示出根据本公开一个实施例的子像素的结构示意图；
图3-图6是分别示出根据本公开一些实施例的子像素中的某一层的布局示意图；
图7A是示出根据本公开一个实施例的子像素中图3、图5和图6所示的层叠加的布局示意图；
图7B是示出根据本公开一个实施例的子像素中图3至图6所示的层叠加的布局示意图；
图8A是示出根据本公开一个实施例的子像素中的多层的部分层在基板上的投影的示意图；
图8B是示出图8A所示的第一区域A1、第二区域A2和第三区域A3的放大示意图；
图8C是沿着图7B所示的C-C’截取的截面示意图；
图9A是示出根据本公开另一个实施例的显示面板的结构示意图；
图9B是示出根据本公开另一个实施例的子像素中的多层的部分层在基板上的投影的示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且 完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
发明人注意到，OLED显示面板的串扰会导致OLED显示面板的显示质量下降。针对这一问题，发明人研究后发现：通过增大连接至数据线的开关晶体管的有源层与连接至驱动晶体管的栅极的初始化晶体管的有源层之间的距离，可以减小显示面板的串扰。
据此，本公开实施例提出了如下技术方案。
图1是示出根据本公开一个实施例的显示面板的结构示意图。
如图1所示，显示面板包括基板11和位于基板11上的多个子像素12。显示面板中的多个子像素12中的至少一个子像素12可以包括如图2所示的结构。
图2是示出根据本公开一个实施例的子像素的结构示意图。图3-图6是分别示出根据本公开一些实施例的子像素中的某一层的布局示意图。图7A是示出根据本公开一个实施例的子像素中图3、图5和图6所示的层叠加的布局示意图。图7B是示出根据本公开一个实施例的子像素中图3至图6所示的层叠加的布局示意图。
如图2所示，子像素12可以包括发光元件D、第一晶体管T1、电容器C、第二晶体管T2和第三晶体管T3。发光元件D包括阳极D1和阴极D2。在一些实现方式中，发光元件D可以是OLED。这里，第一晶体管T1也可以称为开关晶体管，第二晶体管T2也可以称为驱动晶体管，第三晶体管T3也可以称为复位晶体管。
第一晶体管T1被配置为响应于栅极线Gate的扫描信号，在导通的情况下将来自数据线Data的数据信号传输至第二晶体管T2。第二晶体管T2被配置为在导通的情况下将驱动电流Id传输至发光元件D，以驱动发光元件D发光。第三晶体管T3被配置为响应于复位线Reset的复位信号，在导通的情况下将第二晶体管T2的栅极G2的电压复位至初始化电压线Vinit的电压。
在不同的实施例中，如图2所示，子像素12还可以包括第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的一个或多个。这里，第四晶体管T4也可以称为补偿晶体管，第五晶体管T5也可以称为驱动控制晶体管，第六晶体管T6也可以称为发射控制晶体管，第七晶体管T7也可以称为旁路晶体管。例如，第四晶体管T4被配置为响应于扫描线Gate的扫描信号，在导通的情况下使得第二晶体管T2处于二极管连接状态。例如，第五晶体管T5和第六晶体管T6被配置为响应于控制线EM的控制信号，在导通的情况下使得发射电流Id流向发光元件D。例如，第七晶体管T7被配置为响应于复位线Reset的复位信号，在导通的情况下使得驱动电流Id的一部分作为旁路电流Ibp流过。需要说明的是，虽然图2示出的第三晶体管T3的第三栅极G3和第七晶体管T7的第七栅极G7均连接至同一复位线Reset。但是，这并非是限制性的。例如，在某些实施例中，第七晶体管T7的第七栅极G7可以连接至与复位线Reset不同的另一复位线。
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P沟道薄膜晶体管。在另一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的一个或多个可以为N沟道薄膜晶体管。
例如，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的每一个的有源层可以如图3所示。有源层的材料例如可以包括多晶硅，例如低温多晶硅等。每个晶体管的有源层包括两个电极区和位于两个电极区之间的沟道区。这里，两个电极区中的一个为源极区，另 一个为漏极区。应理解，两个电极区中的掺杂浓度大于沟道区中的掺杂浓度。换言之，两个电极区中的每一个为导体区，而沟道区为半导体区。
参见图2和图3，第一晶体管T1包括第一有源层ACT1和连接至扫描线Gate的第一栅极G1。在一些实施例中，扫描线Gate和第一栅极G1可以一体设置。如图3所示，第一有源层ACT1包括第一电极区ACT11、第二电极区ACT12、以及位于第一电极区和第二电极区之间的第一沟道区ACT13。这里，第一电极区ACT11连接至数据线Data，第二电极区ACT12连接至电源线VDD。例如，第一电极区ACT11可以经由图7B所示的过孔V1连接至数据线Data。在一些实施例中，第二电极区ACT12可以经由第五晶体管T5的第五有源层ACT5连接至电源线VDD。例如，第五有源层ACT5可以经由图7B所示的过孔V2连接至电源线VDD。在一些实施例中，参见图4，数据线Data和电源线VDD可以位于同一层。
需要说明的是，在本文中，两个部件位于同一层是指这两个部件是通过同一图案化工艺形成的，即，通过对同一材料层进行一次图案化形成的；或者，这两个部件位于同一膜层之上，并且与该膜层直接接触。
电容器C包括第一电极板C1和连接至电源线VDD的第二电极板C2。例如，第二电极板C2可以经由图7B所示的过孔V3连接至电源线VDD。
第二晶体管T2包括第二有源层ACT2和连接至第一电极板C1的第二栅极G2。在一些实施例中，第一电极板C1和第二栅极G2可以一体设置。如图3所示，第二有源层ACT2包括第三电极区ACT21、第四电极区ACT22、以及位于第三电极区ACT21和第四电极区ACT22之间的第二沟道区ACT23。第三电极区ACT21连接至第二电极区ACT12，第四电极区ACT22连接至阳极D1。在一些实施例中，第三电极区ACT21和第二电极区ACT12可以一体设置。在一些实施例中，第三电极区ACT21可以经由第五晶体管T5的第五有源层ACT5连接至电源线VDD。
第三晶体管T3包括第三有源层ACT3和连接至复位线Reset的第三栅极G3。在一些实施例中，复位线Reset和第三栅极G3可以一体设置。如图3所示，第三有源层ACT3包括第五电极区ACT31、第六电极区ACT32、以及位于第五电极区ACT31和第六电极区ACT32之间的第三沟道区ACT33。第五电极区ACT31连接至第一电极板C1，第六电极区ACT32连接至初始化电压线Vinit。例如，第五电极区ACT31可以经由图7B所示的过孔V4连接至第一连接件CT1，第一电极板C1可以经由图7B所示的过孔V5连接至第一连接件CT1。例如，第六电极区ACT32可以经由图7B所 示的过孔V6连接至第二连接件CT2，初始化电压线Vinit可以经由图7B所示的过孔V7连接至第二连接件CT2。在一些实施例中，参见图4，第一连接件CT1、第二连接件CT2、数据线Data和电源线VDD可以位于同一层。在一些实施例中，参见图5，扫描线Gate、第一电极板C1和复位线Reset可以位于同一层。在一些实施例中，参见图6，第二电极板C2和初始化电压线Vinit可以位于同一层。
参见图3和图7A，第一沟道区ACT13可以是第一有源层ACT1与扫描线Gate重叠的区域，第二沟道区ACT23可以是第二有源层ACT2与第一电极板C1重叠的区域，第三沟道区ACT33可以是第三有源层ACT3与复位线Reset重叠的区域，第四沟道区ACT43可以是第四有源层ACT4与扫描线Gate重叠的区域。
图8A是示出根据本公开一个实施例的子像素中的多层的部分层在基板上的投影的示意图。需要说明的是，为了清晰地示出电源线VDD、复位线Reset、数据线Data和第三有源层ACT3之间的位置关系，图8A省略了某些层中的其他部件。
如图8A所示，电源线VDD在基板11上的正投影为第一投影VDD’，复位线Reset在基板11上的正投影为第二投影Reset’，第三晶体管T3的第三沟道区ACT33在基板11上的正投影为第三投影ACT33’，数据线Data在基板11上的正投影为第四投影Data’。在一些实施例中，第三投影ACT33’可以包括间隔开的第一部分ACT331’和第二部分ACT332’。第一部分ACT331’位于第一投影VDD’之内，第二部分ACT332’位于第一投影VDD’之外。换言之，第三晶体管T3的第三栅极G3包括两个栅极，其中一个栅极在基板11上的正投影与第一部分ACT331’完全地重叠，另一个栅极在基板11上的正投影与第二部分ACT332’完全地重叠。
第一投影VDD’、第二投影Reset’和第三投影ACT33’彼此交叠的区域为第一区域A1，第一投影VDD’与第二投影Reset’交叠、且与第三投影ACT33’不交叠的区域包括与第一区域A1均邻接的第二区域A2和第三区域A3。第二区域A2位于第一区域A1靠近第四投影Data’的一侧，第三区域A3位于第一区域A1远离第四投影Data’的一侧。作为一些实现方式，第一区域A1、第二区域A2和第三区域A3的形状可以均为矩形。应理解，这里的矩形是指在工艺偏差范围内的矩形，即大致是矩形。还应理解，本公开并不限于此。
图8B是示出图8A所示的第一区域A1、第二区域A2和第三区域A3的放大示意图。
在图8A和图8B中，第二区域A2的面积不小于第三区域A3的面积。例如，第 二区域A2的面积等于第三区域A3的面积。又例如，第二区域A2的面积大于第三区域A3的面积。
上述实施例中，由于第二区域A2的面积不小于第三区域A3的面积，故增大了第一有源层ACT1的第一电极区ACT11和第三有源层ACT3的第五电极区ACT31之间的距离，从而降低了第一电极区ACT11和第五电极区ACT31之间的电容，减小了显示面板的串扰。
如图3所示，第一电极区ACT11与第五电极区ACT31之间的距离可以表示为a。通过仿真实验，可以得到不同距离a对应的串扰。
下表示出了几个a的典型值与串扰的对应关系。另外，下表还示出了不同的a对应的c1和c2。c1表示同一子像素内的第一电极区ACT11与第五电极区ACT31之间的电容，c2表示一个子像素12内的第一电极区ACT11与另一个子像素12内的第五电极区ACT31之间的电容。
a/微米 2.74 3.26 3.83
c1/Ff 0.0793 0.0713 0.0561
c2/fF 0.0281 0.0287 0.0279
串扰 0.808％ 0.762％ 0.665％
从上表可以看出，随着a的增大，c1逐渐减小，串扰也逐渐减小。在一些实施例中，a的范围可以是2.5微米至5微米，例如，2.74微米、3.26微米、3.58微米、3.83微米等。在一些实施例中，为了兼顾显示面板的分辨率和显示面板的串扰，a可以是3.26微米。数据线Data的宽度例如可以是2微米至3微米，例如2.5微米左右。
应理解，上表中的比例值可以反应串扰的大小。例如，串扰可以用Ib/Ia的大小来衡量。Ia是在显示面板显示白色画面时流经某个子像素中的发光元件的电流。Ib是在显示面板与该子像素邻近的部分区域(例如某个矩形区域)显示黑色画面、其他区域显示白色画面的情况下，流经该子像素中的发光元件的电流。需要说明的是，在不同的实施例中，可以采用不同的参数来反应显示面板的串扰。
图8C是沿着图7B所示的C-C’截取的截面示意图。
如图8C所示，基板上11可以设置有缓冲层21，例如硅的氧化物、硅的氮化物等无机层。第一有源层ACT1和第三有源层ACT3间隔开地设置在缓冲层21上。第一绝缘层GI1覆盖第一有源层ACT1和第三有源层ACT3。第二绝缘层GI1位于第一绝缘层GI1上。层间绝缘层ILD上设置在第二绝缘层GI1上。数据线Data和电源线 VDD间隔开地设置在层间绝缘层ILD上。第一绝缘层GI1和第二绝缘层GI1的材料可以包括硅的氧化物等。
在形成子像素12的过程中，可以通过调整第一有源层ACT1和第三有源层ACT3的位置，来减小第一有源层ACT1中的第一电极区ACT11和第三有源层ACT3中的第五电极区ACT31之间的距离，从而减小显示面板的串扰。
在一些实施例中，为了进一步降低显示面板的串扰，显示面板还可以包括屏蔽层。
图9A是示出根据本公开另一个实施例的显示面板的结构示意图。
需要说明的是，图9A仅简化地示出了一个子像素12中的第一有源层ACT1和第三有源层ACT3，并未示出其他有源层。
如图9A所示，显示面板还包括屏蔽层13。该实施例中，第一晶体管T1的第一有源层ACT1和第三晶体管T3的第三有源层ACT3位于同一层。图9A示意性地将屏蔽层13示出为位于第一有源层ACT1和第三有源层ACT3所在的同一层与基板11之间。应理解，在其他的实现方式中，屏蔽层13也可以位于第一有源层ACT1和第三有源层ACT3所在的同一层远离基板11的一侧，即上侧。
图9B是示出根据本公开另一个实施例的子像素中的多层的部分层在基板上的投影的示意图。下面结合图9B对屏蔽层13和其他层之间的位置关系进行介绍。
可以理解的是，为了清楚地示出第一有源层ACT1、第三有源层ACT3和屏蔽层13之间的位置关系，图9B仅示出了第一有源层ACT1、第三有源层ACT3和屏蔽层13在基板11上的正投影的标记。
第一有源层ACT1在基板11上的正投影为投影ACT1’,第一有源层ACT1的第一电极区ACT11在基板11上的正投影为投影ACT11’,第一有源层ACT1的第二电极区ACT12在基板11上的正投影为投影ACT12’,第一有源层ACT1的第一沟道区ACT13在基板11上的正投影为投影ACT13’。
第三有源层ACT3在基板11上的正投影为投影ACT3’,第三有源层ACT3的第五电极区ACT31在基板11上的正投影为投影ACT31’,第三有源层ACT3的第六电极区ACT32在基板11上的正投影为投影ACT32’,第三有源层ACT3的第三沟道区ACT33在基板11上的正投影为投影ACT33’。
为了区分，这里将第一电极区ACT11在基板11上的正投影称为第五投影ACT11’，第五电极区ACT31在基板11上的正投影称为第六投影ACT31’，屏蔽层13在基板11上的正投影称为第七投影13’。
第七投影13’至少部分地位于第五投影ACT11’和第六投影ACT31’之间。例如，如图9B所示，第七投影13’可以部分地位于第五投影ACT11’和第六投影ACT31’之间。又例如，第七投影13’可以全部地位于第五投影ACT11’和第六投影ACT31’之间。
上述实施例中，屏蔽层13的存在可以进一步降低第一电极区ACT31和第五电极区ACT32之间的电容，从而进一步降低显示面板的串扰。
在一些实施例中，屏蔽层13包括金属层。作为一些实现方式，金属层的材料可以包括Mo。
作为另一些实现方式，为了更有效性地降低第一电极区ACT31和第五电极区ACT32之间的电容，参见图9A，金属层可以包括第一金属层131、第二金属层132、以及位于第一金属层131和第二金属层之间的第三金属层133。例如，第一金属层131和第二金属层132的材料相同，并且，第一金属层131和第三金属层133的材料不同。作为一些示例，第一金属层1311和第二金属层32的材料可以包括Ti，第三金属层133的材料可以包括Al。
在一些实施例中，为了更进一步降低第一电极区ACT31和第五电极区42之间的电容，从而更进一步降低显示面板的串扰，第五投影ACT11’和第六投影ACT31’中的至少一个可以与第七投影13’至少部分地交叠。例如，第五投影ACT11’与第七投影13’部分交叠，第六投影ACT31’与第七投影13’不交叠。又例如，第五投影ACT11’与第七投影13’部分地交叠，第六投影ACT31’与第七投影13’部分地交叠。
在一些实施例中，为了更进一步降低第一电极区ACT31和第五电极区42之间的电容，从而更进一步降低显示面板的串扰，第五投影ACT1’和第六投影ACT3’中的至少一个可以在第七投影13’之内。例如，第五投影ACT1’和第六投影ACT3’中的一个在第七投影13’之内，另一个不在第七投影13’之内。又例如，第五投影ACT1’和第六投影ACT3’均在第七投影13’之内。
如上所述，在本公开各实施例的显示面板的多个子像素中，至少一个子像素12还可以包括第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的一个或多个。
下面结合图2和图3对第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7进行介绍。
第四晶体管T4包括第四有源层ACT4和连接至扫描线Gate的第四栅极G4。在一些实施例中，扫描线Gate和第四栅极G4可以一体设置。如图3所示，第四有源层 ACT4包括第七电极区ACT41、第八电极区ACT42、以及位于第七电极区ACT41和第八电极区ACT42之间的第四沟道区ACT43。第七电极区ACT41连接至第二栅极G2，第八电极区ACT42连接至第四电极区ACT22。例如，第七电极区ACT41可以经由图7B所示的过孔V4连接至第一连接件CT1，第二栅极G2可以经由图7B所示的过孔V5连接至第一连接件CT1。在一些实施例中，第七电极区ACT41和第五电极区ACT31可以一体设置。在一些实施例中，第八电极区ACT42和第四电极区ACT22可以一体设置。在某些实施例中，第四沟道区ACT43可以包括间隔开的两部分，即，第四栅极G4可以包括两个栅极。
第五晶体管T5包括第五有源层ACT5和连接至控制线EM的第五栅极G5。如图3所示，第五有源层ACT5包括第九电极区ACT51、第十电极区ACT52、以及位于第九电极区ACT51和第十电极区ACT52之间的第五沟道区ACT53。第九电极区ACT51连接至电源线VDD，第十电极区ACT52连接至第二电极区ACT12。例如，第九电极区ACT51可以经由图7B所示的过孔V2连接至电源线VDD。例如，第十电极区ACT52可以经由第三电极区ACT21连接至第二电极区ACT12。在一些实施例中，参见图5，控制线EM、扫描线Gate、第一电极板C1和复位线Reset可以位于同一层。
第六晶体管T6包括第六有源层ACT6和连接至控制线EM的第六栅极G6。如图3所示，第六有源层ACT6包括第十一电极区ACT61、第十二电极区ACT62、以及位于第十一电极区ACT61和第十二电极区ACT62之间的第六沟道区ACT63。第十一电极区ACT61连接至第四电极区ACT22，第十二电极区ACT62连接至阳极D1。在一些实施例中，第十一电极区ACT61和第四电极区ACT22可以一体设置。在一些实施例中，第十二电极区ACT62可以经由图7B所示的过孔V8连接至导电层M(例如金属层)，导电层M可以经由其他过孔连接至阳极D1。在一些实施例中，参见图4，导电层M、第一连接件CT1、第二连接件CT2、数据线Data和电源线VDD可以位于同一层。
第七晶体管T7包括第七有源层ACT7和连接至复位线Reset的第七栅极G7。在一些实施例中，复位线Reset和第七栅极G7可以一体设置。如图3所示，第七有源层ACT7包括第十三电极区ACT71、第十四电极区ACT72、以及位于第十三电极区ACT71和第十四电极区ACT72之间的第七沟道区ACT73。第十三电极区ACT71连接至第十二电极区ACT62，第十四电极区ACT72连接至初始化电压线Vinit。例如，例如，第十四电极区ACT72可以经由图7B所示的过孔V6连接至第二连接件CT2， 初始化电压线Vinit可以经由图7B所示的过孔V7连接至第二连接件CT2。在一些实施例中，第十四电极区ACT72和第六电极区ACT32可以一体设置。
参见图3和图7A，第五沟道区ACT53可以是第五有源层ACT5与控制线EM重叠的区域，第六沟道区ACT63可以是第六有源层ACT6与控制线EM重叠的区域，第七沟道区ACT73可以是第七有源层ACT7与复位线重叠的区域。
在一些实施例中，参见图3，第一有源层ACT1、第二有源层ACT2、第三有源层ACT3、第四有源层ACT4、第五有源层ACT5、第六有源层ACT6和第七有源层ACT7可以位于同一层。
下面介绍根据本公开一些实施例的子像素的驱动方法。需要说明的是，在下面的描述中，假设子像素包括T1、T2、T3、T4、T5、T6和T7，并且，晶体管T1、T2、T3、T4、T5、T6和T7均为P型沟道晶体管。
在复位阶段，第三晶体管T3响应于复位线Reset的复位信号而导通，第二晶体管T2的第二栅极G2经由第三晶体管T3连接到初始化电压线Vinit。如此，驱动晶体管T1的第二栅极G2的电压被复位至初始化电压线Vinit的电压。
在补偿阶段，第一晶体管T1和第四晶体管T4响应于扫描线Gate的扫描信号而导通。这种情况下，第二晶体管T2处于二极管连接状态，并且处于正向偏置。第二晶体管T2的第二栅极G2的电压为来自数据线Data的数据信号的电压Vdata与第二晶体管T2的阈值电压Vth(负数)之和，即，Vdata+Vth。此时，电容器Cst的第一电极板C1的电压为Vdata+Vth，电容器Cst的第二电极板C2的电压为电源线VDD的电压ELVDD。电容器Cst被充入与第一电极板C1和第二电极板C2之间的电压差对应的电荷。
在发光阶段，第五晶体管T5和第六晶体管T6响应于控制线EM的控制信号而导通。响应于第二晶体管T2的第二栅极G2的电压与电源线VDD的电压之间的电压差而产生驱动电流Id，驱动电流Id通过第六晶体管T6被供应至发光元件D。在发光阶段，第二晶体管T2的栅源电压Vgs保持为(Vdata+Vth)-ELVDD。驱动电流Id与(Vdata-ELVDD) 2成比例。因此，驱动电流Id与第一晶体管T1的阈值电压Vth无关。
另外，在复位阶段，第七晶体管T7响应于复位线Reset的复位信号而导通。另外，第七晶体管T7可以与第一晶体管T1和第四晶体管T4同时导通。为了避免在第二晶体管T2截止的情况下的驱动电流Id驱动发光元件D发光，驱动电流Id的一部 分可以作为旁路电流Ibp通过第七晶体管T7流出。
本公开还提供了一种显示装置，显示装置可以包括上述任意一个实施例的显示面板。在一些实施例中，显示装置例如可以是移动终端、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
本公开实施例的还提供了一种显示面板的制造方法。显示面板的制造方法包括：提供基板；和在基板上形成多个子像素。参见图2，至少一个子像素的结构包括发光元件D、第一晶体管T1、电容器C、第二晶体管T2和第三晶体管T3。
参见图2和图3，发光元件D包括阳极D1和阴极D2。第一晶体管T1包括第一有源层ACT1和连接至扫描线Gate的第一栅极G1，第一有源层ACT1包括第一电极区ACT11、第二电极区ACT12、以及位于第一电极区和第二电极区之间的第一沟道区ACT13，第一电极区ACT11连接至数据线Data，第二电极区ACT12连接至电源线VDD。
电容器C包括第一电极板C1和连接至电源线VDD的第二电极板C2。第二晶体管T2包括第二有源层ACT2和连接至第一电极板C1的第二栅极G2，第二有源层ACT2包括第三电极区ACT21、第四电极区ACT22、以及位于第三电极区ACT21和第四电极区ACT22之间的第二沟道区ACT23，第三电极区ACT21连接至第二电极区ACT12，第四电极区ACT22连接至阳极D1。
第三晶体管T3包括第三有源层ACT3和连接至复位线Reset的第三栅极G3，第三有源层ACT3包括第五电极区ACT31、第六电极区ACT32、以及位于第五电极区ACT31和第六电极区ACT32之间的第三沟道区ACT33，第五电极区ACT31连接至第一电极板C1，第六电极区ACT32连接至初始化电压线Vinit。
如图8A所示，电源线VDD在基板11上的正投影为第一投影VDD’，复位线Reset在基板11上的正投影为第二投影Reset’，第三晶体管T3的第三沟道区ACT33在基板11上的正投影为第三投影ACT33’，数据线Data在基板11上的正投影为第四投影Data’。第一投影VDD’、第二投影Reset’和第三投影ACT33’彼此交叠的区域为第一区域A1，第一投影VDD’与第二投影Reset’交叠、且与第三投影ACT33’不交叠的区域包括与第一区域A1均邻接的第二区域A2和第三区域A3。第二区域A2位于第一区域A1靠近第四投影Data’的一侧，第三区域A3位于第一区域A1远离第四投影Data’的一侧。第二区域A2的面积不小于第三区域A3的面积。
上述实施例形成的显示面板中，由于第二区域A2的面积不小于第三区域A3的面 积，故增大了第一有源层ACT1的第一电极区ACT11和第三有源层ACT3的第五电极区ACT31之间的距离，从而降低了第一电极区ACT11和第五电极区ACT31之间的电容，减小了显示面板的串扰。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种显示面板，包括：基板和位于所述基板上的多个子像素，至少一个子像素包括：
    发光元件，包括阳极和阴极；
    第一晶体管，包括第一有源层和连接至扫描线的第一栅极，所述第一有源层包括第一电极区、第二电极区、以及位于所述第一电极区和所述第二电极区之间的第一沟道区，所述第一电极区连接至数据线，所述第二电极区连接至电源线；
    电容器，包括第一电极板和连接至所述电源线的第二电极板；
    第二晶体管，包括第二有源层和连接至所述第一电极板的第二栅极，所述第二有源层包括第三电极区、第四电极区、以及位于所述第三电极区和所述第四电极区之间的第二沟道区，所述第三电极区连接至所述第二电极区，所述第四电极区连接至所述阳极；和
    第三晶体管，包括第三有源层和连接至复位线的第三栅极，所述第三有源层包括第五电极区、第六电极区、以及位于所述第五电极区和所述第六电极区之间的第三沟道区，所述第五电极区连接至所述第一电极板，所述第六电极区连接至初始化电压线；
    其中：
    所述电源线在所述基板上的正投影为第一投影，所述复位线在所述基板上的正投影为第二投影，所述第三沟道区在所述基板上的正投影为第三投影，所述数据线在所述基板上的正投影为第四投影；
    所述第一投影、所述第二投影和所述第三投影彼此交叠的区域为第一区域，所述第一投影与所述第二投影交叠、且与所述第三投影不交叠的区域包括与所述第一区域均邻接的第二区域和第三区域，所述第二区域位于所述第一区域靠近所述第四投影的一侧，所述第三区域位于所述第一区域远离所述第四投影的一侧，所述第二区域的面积不小于所述第三区域的面积。
  2. 根据权利要求1所述的显示面板，其中，所述第三投影包括间隔开的第一部分和第二部分，所述第一部分位于所述第一投影之内，所述第二部分位于所述第一投影之外。
  3. 根据权利要求1所述的显示面板，其中，所述第二区域的面积大于所述第三区域的面积。
  4. 根据权利要求1所述的显示面板，其中，所述第一区域、所述第二区域和所述第三区域的形状均为矩形。
  5. 根据权利要求1所述的显示面板，还包括屏蔽层，其中：
    所述第一有源层的所述第一电极区在所述基板上的正投影为第五投影；
    所述第三有源层的所述第五电极区在所述基板上的正投影为第六投影；
    所述屏蔽层在所述基板上的正投影为第七投影，所述第七投影至少部分地位于所述第五投影和所述第六投影之间。
  6. 根据权利要求5所述的显示面板，其中，所述第五投影和所述第六投影中的至少一个与所述第七投影至少部分地交叠。
  7. 根据权利要求6所述的显示面板，其中，所述第五投影和所述第六投影中的至少一个在所述第七投影之内。
  8. 根据权利要求5所述的显示面板，其中，所述第一有源层和所述第三有源层位于同一层，所述屏蔽层位于所述同一层与所述基板之间。
  9. 根据权利要求5所述的显示面板，其中，所述屏蔽层包括金属层。
  10. 根据权利要求9所述的显示面板，其中，所述金属层包括第一金属层、第二金属层、以及位于所述第一金属层和所述第二金属层之间的第三金属层。
  11. 根据权利要求10所述的显示面板，其中，所述第一金属层和所述第二金属层的材料相同，并且和所述第三金属层的材料不同。
  12. 根据权利要求11所述的显示面板，其中，所述第一金属层和所述第二金属 层的材料包括Ti，所述第三金属层的材料包括Al。
  13. 根据权利要求1-12任意一项所述的显示面板，其中，所述至少一个子像素还包括下列中的至少一个：
    第四晶体管，包括第四有源层和连接至所述扫描线的第四栅极，所述第四有源层包括第七电极区、第八电极区、以及位于所述第七电极区和所述第八电极区之间的第四沟道区，所述第七电极区连接至所述第二栅极，所述第八电极区连接至所述第四电极区；
    第五晶体管，包括第五有源层和连接至控制线的第五栅极，所述第五有源层包括第九电极区、第十电极区、以及位于所述第九电极区和所述第十电极区之间的第五沟道区，所述第九电极区连接至所述电源线，所述第十电极区连接至所述第二电极区；
    第六晶体管，包括第六有源层和连接至控制线的第六栅极，所述第六有源层包括第十一电极区、第十二电极区、以及位于所述第十一电极区和所述第十二电极区之间的第六沟道区，所述第十一电极区连接至所述第四电极区，所述第十二电极区连接至所述阳极；
    第七晶体管，包括第七有源层和连接至所述复位线的第七栅极，所述第七有源层包括第十三电极区、第十四电极区、以及位于所述第十三电极区和所述第十四电极区之间的第七沟道区，所述第十三电极区连接至所述第十二电极区，所述第十四电极区连接至所述初始化电压线。
  14. 根据权利要求13所述的显示面板，其中，所述第一有源层、第二有源层、第三有源层、第四有源层、第五有源层、第六有源层和第七有源层位于同一层。
  15. 根据权利要求1-12任意一项所述的显示面板，其中，所述第二电极板和所述初始化电压线位于同一层。
  16. 根据权利要求1-12任意一项所述的显示面板，其中，所述扫描线、所述第一电极板和所述复位线位于同一层。
  17. 根据权利要求1-12任意一项所述的显示面板，其中，所述数据线和所述电源 线位于同一层。
  18. 根据权利要求1-12任意一项所述的显示面板，其中，下列三组中的至少一组中的两个一体设置：
    所述扫描线与所述第一栅极；
    所述第一电极板与所述第二栅极；
    所述复位线与所述第三栅极。
  19. 一种显示装置，包括：如权利要求1-18任意一项所述的显示面板。
  20. 一种显示面板的制造方法，包括：提供基板；和在所述基板上形成多个子像素，至少一个子像素包括：
    发光元件，包括阳极和阴极；
    第一晶体管，包括第一有源层和连接至扫描线的第一栅极，所述第一有源层包括第一电极区、第二电极区、以及位于所述第一电极区和所述第二电极区之间的第一沟道区，所述第一电极区连接至数据线，所述第二电极区连接至电源线；
    电容器，包括第一电极板和连接至所述电源线的第二电极板；
    第二晶体管，包括第二有源层和连接至所述第一电极板的第二栅极，所述第二有源层包括第三电极区、第四电极区、以及位于所述第三电极区和所述第四电极区之间的第二沟道区，所述第三电极区连接至所述第二电极区，所述第四电极区连接至所述阳极；和
    第三晶体管，包括第三有源层和连接至复位线的第三栅极，所述第三有源层包括第五电极区、第六电极区、以及位于所述第五电极区和所述第六电极区之间的第三沟道区，所述第五电极区连接至所述第一电极板，所述第六电极区连接至初始化电压线；
    其中：
    所述电源线在所述基板上的正投影为第一投影，所述复位线在所述基板上的正投影为第二投影，所述第三沟道区在所述基板上的正投影为第三投影，所述数据线在所述基板上的正投影为第四投影；
    所述第一投影、所述第二投影和所述第三投影彼此交叠的区域为第一区域，所述第一投影与所述第二投影交叠、且与所述第三投影不交叠的区域包括与所述第一区域 均邻接的第二区域和第三区域，所述第二区域位于所述第一区域靠近所述第四投影的一侧，所述第三区域位于所述第一区域远离所述第四投影的一侧，所述第二区域的面积不小于所述第三区域的面积。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745253A (zh) * 2021-09-06 2021-12-03 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102697120B1 (ko) * 2020-11-06 2024-08-22 삼성디스플레이 주식회사 유기 발광 표시 장치

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007316511A (ja) * 2006-05-29 2007-12-06 Toshiba Matsushita Display Technology Co Ltd アクティブマトリクス型表示装置
CN208173203U (zh) * 2018-05-29 2018-11-30 北京京东方技术开发有限公司 显示面板及显示装置
CN110299103A (zh) * 2019-06-28 2019-10-01 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN110689848A (zh) * 2019-12-10 2020-01-14 京东方科技集团股份有限公司 显示装置和驱动方法
CN110752248A (zh) * 2019-11-20 2020-02-04 京东方科技集团股份有限公司 显示基板及其制作方法、和显示装置
CN110767665A (zh) * 2019-11-29 2020-02-07 京东方科技集团股份有限公司 一种显示面板、其制备方法及显示装置
CN110808265A (zh) * 2018-08-06 2020-02-18 三星显示有限公司 有机发光显示设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371652A (en) * 1993-11-15 1994-12-06 Thermalloy, Inc. Spring clamp assembly with electrically insulating shoe
KR101982074B1 (ko) * 2012-10-08 2019-08-29 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102211966B1 (ko) * 2013-10-14 2021-02-15 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이를 포함하는 유기 발광 표시 장치
KR102675913B1 (ko) * 2016-04-29 2024-06-17 엘지디스플레이 주식회사 백플레인 기판 및 이를 이용한 유기 발광 표시 장치
KR20180040185A (ko) * 2016-10-11 2018-04-20 삼성디스플레이 주식회사 표시 장치
KR102349279B1 (ko) * 2017-09-08 2022-01-11 삼성디스플레이 주식회사 디스플레이 장치
CN209232793U (zh) * 2018-12-13 2019-08-09 昆山国显光电有限公司 一种显示面板及显示装置
CN110728267B (zh) * 2019-11-15 2024-08-09 京东方科技集团股份有限公司 显示基板及其制作方法、显示面板和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007316511A (ja) * 2006-05-29 2007-12-06 Toshiba Matsushita Display Technology Co Ltd アクティブマトリクス型表示装置
CN208173203U (zh) * 2018-05-29 2018-11-30 北京京东方技术开发有限公司 显示面板及显示装置
CN110808265A (zh) * 2018-08-06 2020-02-18 三星显示有限公司 有机发光显示设备
CN110299103A (zh) * 2019-06-28 2019-10-01 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN110752248A (zh) * 2019-11-20 2020-02-04 京东方科技集团股份有限公司 显示基板及其制作方法、和显示装置
CN110767665A (zh) * 2019-11-29 2020-02-07 京东方科技集团股份有限公司 一种显示面板、其制备方法及显示装置
CN110689848A (zh) * 2019-12-10 2020-01-14 京东方科技集团股份有限公司 显示装置和驱动方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113745253A (zh) * 2021-09-06 2021-12-03 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
US12101975B2 (en) 2021-09-06 2024-09-24 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and display device

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