WO2022160797A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

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Publication number
WO2022160797A1
WO2022160797A1 PCT/CN2021/125465 CN2021125465W WO2022160797A1 WO 2022160797 A1 WO2022160797 A1 WO 2022160797A1 CN 2021125465 W CN2021125465 W CN 2021125465W WO 2022160797 A1 WO2022160797 A1 WO 2022160797A1
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Prior art keywords
electrode region
electrode
transistor
active layer
region
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PCT/CN2021/125465
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English (en)
French (fr)
Inventor
王旭
李子华
蔡璐
郭强
金文强
李春波
王强
王旭东
张瑞卿
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US17/996,829 priority Critical patent/US20230209932A1/en
Publication of WO2022160797A1 publication Critical patent/WO2022160797A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • the sub-pixels of the display panel include more transistors and signal lines. Also, there are more and more connections between transistors and signal lines.
  • a display panel including: a base substrate and a plurality of sub-pixels located on the base substrate, at least one sub-pixel of the plurality of sub-pixels includes: a light-emitting element including an anode and a cathode; a first transistor including a first active layer and a first gate connected to a gate line, the first active layer including a first electrode region, a second electrode region, and a a first channel region between the electrode region and the second electrode region, the first electrode region is connected to a data line, and the second electrode region is connected to a power supply line; a capacitor includes a first electrode plate and is connected to a a second electrode plate of the power supply line; a second transistor including a second active layer and a second gate connected to the first electrode plate, the second active layer including a third electrode region, a fourth an electrode region, and a second channel region between the third electrode region and the fourth electrode region, the third electrode region being connected to the second
  • the orthographic projection of the via on the base substrate is within the orthographic projection of the initialization line on the base substrate.
  • the orthographic projection of the via hole on the base substrate is located within the orthographic projection of the sixth electrode region on the base substrate.
  • the fifth electrode region includes a first portion, a second portion, and a third portion connected between the first portion and the second portion;
  • the third active layer further includes another a sixth electrode region, and another third channel region between the second portion and the other sixth electrode region; and
  • the third gate includes two gates, the two One of the gates is located between the first portion and the sixth electrode region, and the other of the two gates is located between the second portion and the other sixth electrode region.
  • the sixth electrode region includes: a fourth portion; and a fifth portion connected to the fourth portion on a side of the fourth portion away from the third channel region, and is located on the side of the fourth part away from the other sixth electrode region, wherein: the orthographic projection of the via hole on the base substrate is located on the positive side of the fifth part on the base substrate projection, and the orthographic projection of the fifth portion on the base substrate is within the orthographic projection of the initialization line on the base substrate.
  • the extending direction of the fifth portion is perpendicular to the extending direction of the fourth portion.
  • the orthographic projection of the end of the fifth portion away from the fourth portion on the base substrate has an arc.
  • the orthographic projection of the third portion on the base substrate is within the orthographic projection of the power supply line on the base substrate.
  • the at least one subpixel further includes: a fourth transistor including a fourth active layer and a fourth gate connected to the gate line, the fourth active layer including a seventh electrode region, an eighth electrode region, and a fourth channel region between the seventh electrode region and the eighth electrode region, the seventh electrode region being connected to the second gate, the eighth electrode region An electrode region is connected to the fourth electrode region.
  • the at least one sub-pixel further includes: a fifth transistor including a fifth active layer and a fifth gate connected to the control line, the fifth active layer including a ninth electrode region, a fifth a tenth electrode region, and a fifth channel region between the ninth electrode region and the tenth electrode region, the ninth electrode region is connected to the power supply line, and the tenth electrode region is connected to the the second electrode region; and a sixth transistor including a sixth active layer and a sixth gate connected to the control line, the sixth active layer including an eleventh electrode region, a twelfth electrode region, and a A sixth channel region between the eleventh electrode region and the twelfth electrode region, the eleventh electrode region is connected to the fourth electrode region, and the twelfth electrode region is connected to the the anode.
  • the at least one subpixel further includes: a seventh transistor including a seventh active layer and a seventh gate connected to another reset line, the seventh active layer including a thirteenth electrode region, a fourteenth electrode region, and a seventh channel region between the thirteenth electrode region and the fourteenth electrode region, the thirteenth electrode region being connected to the twelfth electrode region , the fourteenth electrode region is connected to another initialization line.
  • a seventh transistor including a seventh active layer and a seventh gate connected to another reset line
  • the seventh active layer including a thirteenth electrode region, a fourteenth electrode region, and a seventh channel region between the thirteenth electrode region and the fourteenth electrode region, the thirteenth electrode region being connected to the twelfth electrode region , the fourteenth electrode region is connected to another initialization line.
  • each sub-pixel of the plurality of sub-pixels includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the first transistor six transistors and the seventh transistor.
  • the first active layer, the second active layer, the third active layer, the fourth active layer, the fifth active layer, the sixth active layer, and the seventh active layer are located at same layer.
  • each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor One is a P-type transistor.
  • the second electrode plate and the initialization line are located on the same layer.
  • the gate line, the first electrode plate and the reset line are located on the same layer.
  • the data lines and the power lines are located on the same layer.
  • the gate line is integrated with the first gate; the first electrode plate is integrated with the second gate; the reset line is integrated with the third gate .
  • a display device comprising: the display panel according to any one of the above embodiments.
  • a method for manufacturing a display panel including: providing a base substrate; and forming a plurality of sub-pixels on the base substrate, at least one sub-pixel of the plurality of sub-pixels It includes: a light-emitting element, including an anode and a cathode; a first transistor, including a first active layer and a first gate connected to the gate line, the first active layer including a first electrode region, a second electrode region, and a first channel region located between the first electrode region and the second electrode region, the first electrode region is connected to a data line, and the second electrode region is connected to a power supply line; a capacitor, including a first an electrode plate and a second electrode plate connected to the power supply line; a second transistor including a second active layer and a second gate connected to the first electrode plate, the second active layer including a second active layer A three-electrode region, a fourth electrode region, and a second channel region between the third
  • FIG. 1 is a schematic structural diagram illustrating a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram illustrating a sub-pixel according to an embodiment of the present disclosure
  • 3 to 6 are schematic layout diagrams respectively illustrating a certain layer in a sub-pixel according to some embodiments of the present disclosure
  • FIG. 7A is a schematic layout diagram illustrating the superposition of the layers shown in FIGS. 3 to 5 in a sub-pixel according to an embodiment of the present disclosure
  • FIG. 7B is a schematic layout diagram illustrating the superposition of the layers shown in FIGS. 3 to 6 in a sub-pixel according to an embodiment of the present disclosure
  • FIG. 8 is a schematic cross-sectional view of a sixth electrode region of a third transistor connected to an initialization line according to an embodiment of the present disclosure
  • FIG. 9 is a partial enlarged schematic view of FIG. 7B according to an embodiment of the present disclosure.
  • first,” “second,” and similar words do not denote any order, quantity, or importance, but are merely used to distinguish the different parts.
  • “Comprising” or “comprising” and similar words mean that the element preceding the word covers the elements listed after the word, and does not exclude the possibility that other elements are also covered.
  • “Up”, “Down”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • a specific component when a specific component is described as being between a first component and a second component, there may or may not be an intervening component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without intervening components, or may not be directly connected to the other components but have intervening components.
  • the extra connectors will interfere with other signal lines, which will affect the display effect of the display panel; on the other hand, in the process of manufacturing the additional connectors, the residues will also affect the display effect of the display panel. Negative Effects.
  • FIG. 1 is a schematic structural diagram illustrating a display panel according to an embodiment of the present disclosure.
  • the display panel includes a base substrate 11 and a plurality of sub-pixels 12 located on the base substrate 11 . At least one sub-pixel 12 of the plurality of sub-pixels 12 in the display panel may include the structure shown in FIG. 2 .
  • FIG. 2 is a schematic structural diagram illustrating a sub-pixel according to an embodiment of the present disclosure.
  • 3 to 6 are schematic layout diagrams respectively illustrating a certain layer in a sub-pixel according to some embodiments of the present disclosure.
  • FIG. 7A is a schematic layout diagram illustrating the superposition of the layers shown in FIGS. 3 to 5 in a sub-pixel according to an embodiment of the present disclosure.
  • FIG. 7B is a schematic layout diagram illustrating the superposition of the layers shown in FIGS. 3 to 6 in a sub-pixel according to an embodiment of the present disclosure.
  • each layer shown in different layout schematic diagrams can also be understood as the orthographic projection of each layer on the base substrate 11 .
  • the sub-pixel 12 may include a light emitting element D, a first transistor T1, a capacitor C, a second transistor T2 and a third transistor T3.
  • the light-emitting element D includes an anode D1 and a cathode D2.
  • the light emitting element D may be an organic light emitting diode (OLED).
  • the first transistor T1 can also be called a switching transistor
  • the second transistor T2 can also be called a driving transistor
  • the third transistor T3 can also be called a reset transistor.
  • the first transistor T1 is configured to transmit the data signal from the data line Data to the second transistor T2 in the case of being turned on in response to the scan signal of the gate line Gate.
  • the second transistor T2 is configured to transmit the driving current Id to the light-emitting element D to drive the light-emitting element D to emit light while being turned on.
  • the third transistor T3 is configured to reset the voltage of the gate G2 of the second transistor T2 to the voltage of the initialization line Vinit in the case of being turned on in response to the reset signal of the reset line Reset.
  • the sub-pixel 12 may further include one or more of a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 .
  • the fourth transistor T4 can also be called a compensation transistor
  • the fifth transistor T5 can also be called a driving control transistor
  • the sixth transistor T6 can also be called a light emission control transistor
  • the seventh transistor T7 can also be called a bypass transistor.
  • the fourth transistor T4 is configured to make the second transistor T2 in a diode-connected state in the case of being turned on in response to the scan signal of the gate line Gate.
  • the fifth transistor T5 and the sixth transistor T6 are configured to cause the emission current Id to flow to the light emitting element D in the case of being turned on in response to the control signal of the control line EM.
  • the seventh transistor T7 is configured to allow a part of the driving current Id to flow as the bypass current Ibp in the case of being turned on in response to the reset signal of the other reset line Reset'.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors. In other embodiments, one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be N type thin film transistor.
  • the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be as shown in FIG. 3 .
  • the material of the active layer may include polysilicon, such as low temperature polysilicon, for example.
  • the active layer of each transistor includes two electrode regions and a channel region located between the two electrode regions. It should be understood that one of the two electrode regions is a source region and the other is a drain region. It should also be understood that the doping concentration of the two electrode regions is greater than the doping concentration of the channel region. In other words, each of the two electrode regions is a conductor region, and the channel region is a semiconductor region.
  • the first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to the gate line Gate.
  • the gate line Gate and the first gate G1 may be integrally disposed.
  • the first active layer ACT1 includes a first electrode region ACT11 , a second electrode region ACT12 , and a first channel region ACT13 located between the first electrode region and the second electrode region.
  • the first channel region ACT13 may be a region where the first active layer ACT1 overlaps with the gate line Gate.
  • the first electrode area ACT11 is connected to the data line Data
  • the second electrode area ACT12 is connected to the power line VDD.
  • the first electrode region ACT11 may be connected to the data line Data via the via hole V1 shown in FIG. 7B .
  • the second electrode region ACT12 may be connected to the power line VDD via the fifth active layer ACT5 of the fifth transistor T5.
  • the fifth active layer ACT5 may be connected to the power supply line VDD via the via hole V2 shown in FIG. 7B .
  • the data line Data and the power line VDD may be located on the same layer.
  • two components are located on the same layer means that the two components are formed by patterning the same material layer.
  • the capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to the power supply line VDD.
  • the second electrode plate C2 may be connected to the power supply line VDD via the via hole V3 shown in FIG. 7B .
  • the second transistor T2 includes a second active layer ACT2 and a second gate G2 connected to the first electrode plate C1.
  • the first electrode plate C1 and the second grid G2 may be integrally provided.
  • the second active layer ACT2 includes a third electrode region ACT21 , a fourth electrode region ACT22 , and a second channel region ACT23 located between the third electrode region ACT21 and the fourth electrode region ACT22 .
  • the second channel region ACT23 may be a region where the second active layer ACT2 overlaps with the first electrode plate C1.
  • the third electrode area ACT21 is connected to the second electrode area ACT12, and the fourth electrode area ACT22 is connected to the anode D1.
  • the third electrode area ACT21 and the second electrode area ACT12 may be integrally provided.
  • the third electrode region ACT21 may be connected to the power line VDD via the fifth active layer ACT5 of the fifth transistor T5.
  • the third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to the reset line Reset.
  • the reset line Reset and the third gate G3 may be integrally provided.
  • the third active layer ACT3 includes a fifth electrode region ACT31 , a sixth electrode region ACT32 , and a third channel region ACT33 located between the fifth electrode region ACT31 and the sixth electrode region ACT32 .
  • the third channel region ACT33 may be a region where the third active layer ACT3 overlaps with the reset line Reset.
  • the fifth electrode region ACT31 is connected to the first electrode plate C1.
  • the fifth electrode region ACT31 may be connected to the connection member CT via the via hole V4 shown in FIG. 7B
  • the first electrode plate C1 may be connected to the connection member CT via the via hole V5 shown in FIG. 7B
  • the sixth electrode region ACT32 is directly connected to the initialization line Vinit through the via hole V6.
  • the gate line Gate, the first electrode plate C1 and the reset line Reset may be located on the same layer.
  • the second electrode plate C2 and the initialization line Vinit may be located on the same layer.
  • the connector CT, the data line Data and the power line VDD may be located on the same layer.
  • the orthographic projection of the initialization line Vinit on the base substrate 11 is located between the orthographic projection of the reset line Reset on the base substrate and the orthographic projection of the gate line Gate on the base substrate 11 .
  • the initialization line Vinit is located between the reset line Reset and the gate line Gate, and the sixth electrode region ACT32 of the third transistor T3 is directly connected to the initialization line Vinit through the via hole V6.
  • the sixth electrode region ACT32 is connected to the initialization line Vinit without an additional connector, which reduces the parasitic capacitance caused by the additional connector and improves the display effect of the display panel.
  • FIG. 8 is a schematic cross-sectional view of a sixth electrode region of a third transistor connected to an initialization line according to an embodiment of the present disclosure.
  • the first insulating layer GI1 is located on the side of the third active layer ACT3 away from the base substrate 11
  • the third gate G3 is located at the side of the first insulating layer GI1 away from the base substrate 11 .
  • the second insulating layer GI2 is located on the side of the third gate G3 and the first insulating layer GI1 away from the base substrate 11 .
  • the initialization line Vinit is located on the side of the second insulating layer GI2 away from the base substrate 11 , and is directly connected to the sixth electrode region ACT32 of the third transistor T3 via the via V6 penetrating the second insulating layer GI2 and the first insulating layer GI1 .
  • the interlayer insulating layer ILD is located on the side of the initialization line Vinit and the second insulating layer GI2 away from the base substrate 11 . It can be understood that one of the source and the drain of the third transistor T3 may be connected to one of the fifth electrode region ACT31 and the sixth electrode region ACT32 via a via hole penetrating the interlayer insulating layer ILD, and the third transistor T3 The other one of the source and drain electrodes of T3 may be connected to the other one of the fifth electrode region ACT31 and the sixth electrode region ACT32 via another via hole penetrating the interlayer insulating layer ILD.
  • the orthographic projection of the via hole V6 on the base substrate 1 and the orthographic projection of the initialization line Vinit on the base substrate 11 are at least Partially overlapping.
  • the orthographic projection of the via hole V6 on the base substrate 1 is located within the orthographic projection of the initialization line Vinit on the base substrate 11 . In this way, it can be ensured that the initialization line Vinit can be connected to the sixth electrode area ACT32 through the via hole V6.
  • the orthographic projection of the via hole V6 on the base substrate 1 is located within the orthographic projection of the sixth electrode region ACT32 on the base substrate 11 . In this way, it can be ensured that the sixth electrode region ACT32 can be connected to the initialization line Vinit through the via hole V6.
  • FIG. 9 is a partial enlarged schematic view of FIG. 7A according to an embodiment of the present disclosure. It should be noted that, for the sake of clarity, FIG. 9 only shows some layers of sub-pixels, and some layers are omitted.
  • the fifth electrode region ACT1 of the third transistor T3 includes a first part P1, a second part P2, and a third part P3 connected between the first part P1 and the second part P2.
  • the extending direction of the third portion P3 is different from the extending direction of the first portion P1 and is different from the extending direction of the second portion P2.
  • the third active layer ACT3 further includes another sixth electrode region ACT32', and another third channel region ACT33' between the second portion P2 and the other sixth electrode region ACT32'.
  • the third gate G3 includes two gates G31 and G32, one gate G31 of the two gates is located between the first part P1 and the sixth electrode region ACT32, and the other gate G32 of the two gates is located at the first part P1 and the sixth electrode region ACT32. between the two parts P2 and another sixth electrode region ACT32'.
  • the sixth electrode region ACT32 includes a fourth portion P4 and a fifth portion P5 connected to the fourth portion P4.
  • the fifth portion P5 is located on a side of the fourth portion P4 away from the third channel region ACT33, and is located at a side of the fourth portion P4 away from the other sixth electrode region ACT32'.
  • the orthographic projection of the via hole V6 on the base substrate 11 is located within the orthographic projection of the fifth portion P5 on the base substrate 11 .
  • the orthographic projection of the fifth portion P5 on the base substrate 11 is located within the orthographic projection of the initialization line Vinit on the base substrate 11 .
  • the extending direction of the fifth portion P5 is perpendicular to the extending direction of the fourth portion P4.
  • the extending direction of the fifth portion P5 is the same as that of the initialization line Vinit
  • the extending direction of the fourth portion P4 is the same as that of the power supply line VDD. In this way, it is beneficial to reduce the length of the third active layer and reduce the mutual influence between the third active layer and other active layers.
  • the orthographic projection of the end of the fifth portion P5 away from the fourth portion P4 on the base substrate 11 has an arc. In this way, the contact edge can be enlarged, so that the via hole V6 can be connected with the fifth part P5 more reliably.
  • the orthographic projection of the third portion P3 on the base substrate 11 is located within the orthographic projection of the power supply line VDD on the base substrate 11 .
  • a capacitor is formed between the third part P3 and the power supply line VDD, which is beneficial to reduce the mutual influence between the third part P3 and other signal lines, thereby reducing the crosstalk of the display panel.
  • the display panel may further include a metal layer connected to the power line VDD.
  • the metal layer is on the same layer as the initialization line Vinit.
  • the orthographic projection of the metal layer on the base substrate 11 overlaps with the orthographic projection of the first electrode region ACT11 on the base substrate 11 , and overlaps with the orthographic projection of the fifth electrode region ACT11 on the base substrate 11 . In this way, the mutual interference between the first electrode area ACT11 and the fifth electrode area ACT11 can be reduced, the crosstalk of the display panel can be further reduced, and the display effect can be improved.
  • At least one sub-pixel 12 may further include one of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 or multiple.
  • the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 and the seventh transistor T7 will be described below with reference to FIGS. 2 and 3 .
  • the fourth transistor T4 includes a fourth active layer ACT4 and a fourth gate G4 connected to the gate line Gate.
  • the gate line Gate and the fourth gate G4 may be integrally disposed.
  • the fourth active layer ACT4 includes a seventh electrode region ACT41 , an eighth electrode region ACT42 , and a fourth channel region ACT43 located between the seventh electrode region ACT41 and the eighth electrode region ACT42 .
  • the seventh electrode area ACT41 is connected to the second gate G2, and the eighth electrode area ACT42 is connected to the fourth electrode area ACT22.
  • the seventh electrode region ACT41 may be connected to the connection member CT1 via the via hole V4 shown in FIG.
  • the second gate G2 may be connected to the connection member CT1 via the via hole V5 shown in FIG. 7B .
  • the seventh electrode area ACT41 and the fifth electrode area ACT31 may be integrally provided.
  • the eighth electrode area ACT42 and the fourth electrode area ACT22 may be integrally provided.
  • the fourth channel region ACT43 may include two spaced apart portions, that is, the fourth gate G4 may include two gates.
  • the fifth transistor T5 includes a fifth active layer ACT5 and a fifth gate G5 connected to the control line EM.
  • the fifth active layer ACT5 includes a ninth electrode region ACT51 , a tenth electrode region ACT52 , and a fifth channel region ACT53 located between the ninth electrode region ACT51 and the tenth electrode region ACT52 .
  • the ninth electrode area ACT51 is connected to the power supply line VDD
  • the tenth electrode area ACT52 is connected to the second electrode area ACT12.
  • the ninth electrode region ACT51 may be connected to the power supply line VDD via the via hole V2 shown in FIG. 7B .
  • the tenth electrode area ACT52 may be connected to the second electrode area ACT12 via the third electrode area ACT21.
  • the control line EM, the gate line Gate, the first electrode plate C1 and the reset line Reset may be located at the same layer.
  • the sixth transistor T6 includes a sixth active layer ACT6 and a sixth gate G6 connected to the control line EM.
  • the sixth active layer ACT6 includes an eleventh electrode region ACT61, a twelfth electrode region ACT62, and a sixth channel region located between the eleventh electrode region ACT61 and the twelfth electrode region ACT62 ACT63.
  • the eleventh electrode area ACT61 is connected to the fourth electrode area ACT22, and the twelfth electrode area ACT62 is connected to the anode D1.
  • the eleventh electrode area ACT61 and the fourth electrode area ACT22 may be integrally provided.
  • the twelfth electrode region ACT62 may be connected to the conductive layer M (eg, a metal layer) via the via V7 shown in FIG. 7B , and the conductive layer M may be connected to the anode D1 via other vias.
  • the conductive layer M, the connector CT, the data line Data and the power line VDD may be located on the same layer.
  • the seventh transistor T7 includes a seventh active layer ACT7 and a seventh gate G7 connected to the reset line Reset.
  • the reset line Reset and the seventh gate G7 may be integrally provided.
  • the seventh active layer ACT7 includes a thirteenth electrode region ACT71, a fourteenth electrode region ACT72, and a seventh channel region located between the thirteenth electrode region ACT71 and the fourteenth electrode region ACT72 ACT73.
  • the thirteenth electrode area ACT71 is connected to the twelfth electrode area ACT62, and the fourteenth electrode area ACT72 is connected to another initialization line Vinit'.
  • the fourteenth electrode region ACT72 may be directly connected to another initialization line Vinit' via a via hole V6 similar to that shown in FIG. 7B .
  • the fourteenth electrode area ACT72 and the sixth electrode area ACT32 may be integrally provided.
  • the seventh active layer ACT7 shown in FIG. 3 is the seventh active layer ACT7 of the seventh transistor T7 of another sub-pixel.
  • the fifth channel region ACT53 may be a region where the fifth active layer ACT5 overlaps with the control line EM
  • the sixth channel region ACT63 may be a region where the sixth active layer ACT6 overlaps with the control line EM
  • the seventh channel region ACT73 may be a region where the seventh active layer ACT7 overlaps with the reset line.
  • the first active layer ACT1 , the second active layer ACT2 , the third active layer ACT3 , the fourth active layer ACT4 , the fifth active layer ACT5 , the sixth active layer ACT6 and the seventh active layer ACT7 may be located at the same layer.
  • the following describes the driving methods of sub-pixels according to some embodiments of the present disclosure. It should be noted that, in the following description, it is assumed that the sub-pixels include T1, T2, T3, T4, T5, T6 and T7, and the transistors T1, T2, T3, T4, T5, T6 and T7 are all P-type transistors .
  • the third transistor T3 is turned on in response to the reset signal of the reset line Reset, and the second gate G2 of the second transistor T2 is connected to the initialization line Vinit via the third transistor T3. In this way, the voltage of the second gate G2 of the second transistor T2 is reset to the voltage of the initialization line Vinit.
  • the first transistor T1 and the fourth transistor T4 are turned on in response to the scan signal of the gate line Gate.
  • the second transistor T2 is diode-connected and forward-biased.
  • the voltage of the second gate G2 of the second transistor T2 is the sum of the voltage Vdata of the data signal from the data line Data and the threshold voltage Vth (negative number) of the second transistor T2, ie, Vdata+Vth.
  • the voltage of the first electrode plate C1 of the capacitor C is Vdata+Vth
  • the voltage of the second electrode plate C2 of the capacitor C is the voltage ELVDD of the power supply line VDD.
  • the capacitor C is charged with a charge corresponding to the voltage difference between the first electrode plate C1 and the second electrode plate C2.
  • the fifth transistor T5 and the sixth transistor T6 are turned on in response to the control signal of the control line EM.
  • the driving current Id is generated in response to the voltage difference between the voltage of the second gate G2 of the second transistor T2 and the voltage of the power supply line VDD, and the driving current Id is supplied to the light emitting element D through the sixth transistor T6.
  • the gate-source voltage Vgs of the second transistor T2 is maintained at (Vdata+Vth)-ELVDD.
  • the drive current Id is proportional to (Vdata-ELVDD) 2 . Therefore, the driving current Id is independent of the threshold voltage Vth of the first transistor T1.
  • the seventh transistor T7 is turned on in response to the reset signal of the reset line Reset.
  • the seventh transistor T7 may be turned on simultaneously with the first transistor T1 and the fourth transistor T4. In order to prevent the driving current Id from driving the light-emitting element D to emit light when the second transistor T2 is turned off, a part of the driving current Id may flow out through the seventh transistor T7 as the bypass current Ibp.
  • An embodiment of the present disclosure further provides a display device, and the display device may include the display panel of any one of the foregoing embodiments.
  • the display device may be, for example, a mobile terminal, a television, a monitor, a notebook computer, a digital photo frame, a navigator, an electronic paper, or any other product or component with a display function.
  • Embodiments of the present disclosure also provide a method for manufacturing a display panel.
  • a manufacturing method of a display panel includes: providing a substrate; and forming a plurality of sub-pixels on the substrate.
  • the structure of at least one sub-pixel includes a light-emitting element, a first transistor, a capacitor, a second transistor, and a third transistor.
  • the light-emitting element includes an anode and a cathode.
  • the first transistor includes a first active layer and a first gate connected to the gate line.
  • the first active layer includes a first electrode region, a second electrode region, and a first channel region between the first electrode region and the second electrode region.
  • the first electrode area is connected to the data line, and the second electrode area is connected to the power line.
  • the capacitor includes a first electrode plate and a second electrode plate connected to the power line.
  • the second transistor includes a second active layer and a second gate connected to the first electrode plate.
  • the second active layer includes a third electrode region, a fourth electrode region, and a second channel region between the third electrode region and the fourth electrode region.
  • the third electrode region is connected to the second electrode region, and the fourth electrode region is connected to the anode.
  • the third transistor includes a third active layer and a third gate connected to the reset line.
  • the third active layer includes a fifth electrode region, a sixth electrode region, and a third channel region between the fifth electrode region and the sixth electrode region.
  • the fifth electrode region is connected to the first electrode plate, and the sixth electrode region is directly connected to the initialization line through the via hole.
  • the orthographic projection of the initialization line on the base substrate is located between the orthographic projection of the reset line on the base substrate and the orthographic projection of the gate line on the base substrate.
  • a via hole connected to the sixth electrode region is formed using a mask.
  • the via may penetrate through multiple insulating layers, as described above.
  • the initialization line is located between the reset line and the gate line, and the sixth electrode region of the third transistor is directly connected to the initialization line through the via hole.
  • the sixth electrode region does not need an additional connection member to be connected to the initialization line, thereby reducing the parasitic capacitance caused by the additional connection member and improving the display effect of the display panel.

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Abstract

本公开提供了一种显示面板及其制造方法、显示装置。显示面板包括衬底基板和多个子像素。至少一个子像素包括：发光元件；第一晶体管，包括第一有源层和连接至栅极线的第一栅极，第一有源层包括连接至数据线的第一电极区、连接至电源线的第二电极区、第一沟道区；电容器，包括第一电极板和第二电极板；第二晶体管，包括第二有源层和连接至第一电极板的第二栅极，第二有源层包括第三电极区、第四电极区、第二沟道区；第三晶体管，包括第三有源层和连接至复位线的第三栅极，第三有源层包括第五电极区、经由过孔直接连接至初始化线的第六电极区、第三沟道区。初始化线在衬底基板上的正投影位于复位线与栅极线在衬底基板上的正投影之间。

Description

显示面板及其制造方法、显示装置
相关申请的交叉引用
本公开以中国申请号为202110128211.3，申请日为2021年1月29日的申请为基础，并主张其优先权，该中国申请的公开内容在此作为整体引入本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制造方法、显示装置。
背景技术
随着显示技术的发展，显示面板的子像素包括更多的晶体管和信号线。并且，晶体管和信号线之间的连接件也越来越多。
发明内容
根据本公开实施例的一方面，提供一种显示面板，包括：衬底基板和位于所述衬底基板上的多个子像素，所述多个子像素中的至少一个子像素包括：发光元件，包括阳极和阴极；第一晶体管，包括第一有源层和连接至栅极线的第一栅极，所述第一有源层包括第一电极区、第二电极区、以及位于所述第一电极区和所述第二电极区之间的第一沟道区，所述第一电极区连接至数据线，所述第二电极区连接至电源线；电容器，包括第一电极板和连接至所述电源线的第二电极板；第二晶体管，包括第二有源层和连接至所述第一电极板的第二栅极，所述第二有源层包括第三电极区、第四电极区、以及位于所述第三电极区和所述第四电极区之间的第二沟道区，所述第三电极区连接至所述第二电极区，所述第四电极区连接至所述阳极；和第三晶体管，包括第三有源层和连接至复位线的第三栅极，所述第三有源层包括第五电极区、第六电极区、以及位于所述第五电极区和所述第六电极区之间的第三沟道区，所述第五电极区连接至所述第一电极板，所述第六电极区经由过孔直接连接至初始化线，其中，所述初始化线在所述衬底基板上的正投影位于所述复位线在所述衬底基板上的正投影与所述栅极线在所述衬底基板上的正投影之间。
在一些实施例中，所述过孔在所述衬底基板上的正投影位于所述初始化线在所述衬底基板上的正投影之内。
在一些实施例中，所述过孔在所述衬底基板上的正投影位于所述第六电极区在所述衬底基板上的正投影之内。
在一些实施例中，所述第五电极区包括第一部分、第二部分、以及连接在所述第一部分和所述第二部分之间的第三部分；所述第三有源层还包括另一第六电极区、以及位于所述第二部分和所述另一第六电极区之间的另一第三沟道区；并且所述第三栅极包括两个栅极，所述两个栅极中的一个位于所述第一部分和所述第六电极区之间，所述两个栅极中的另一个位于所述第二部分和所述另一第六电极区之间。
在一些实施例中，所述第六电极区包括：第四部分；和连接至所述第四部分的第五部分，位于所述第四部分远离所述第三沟道区的一侧，并且位于所述第四部分远离所述另一第六电极区的一侧，其中：所述过孔在所述衬底基板上的正投影位于所述第五部分在所述衬底基板上的正投影之内，并且所述第五部分在所述衬底基板上的正投影位于所述初始化线在所述衬底基板上的正投影之内。
在一些实施例中，所述第五部分的延伸方向与所述第四部分的延伸方向垂直。
在一些实施例中，所述第五部分远离所述第四部分的端部在所述衬底基板上的正投影具有弧度。
在一些实施例中，所述第三部分在所述衬底基板上的正投影位于所述电源线在所述衬底基板上的正投影之内。
在一些实施例中，所述至少一个子像素还包括：第四晶体管，包括第四有源层和连接至所述栅极线的第四栅极，所述第四有源层包括第七电极区、第八电极区、以及位于所述第七电极区和所述第八电极区之间的第四沟道区，所述第七电极区连接至所述第二栅极，所述第八电极区连接至所述第四电极区。
在一些实施例中，所述至少一个子像素还包括：第五晶体管，包括第五有源层和连接至控制线的第五栅极，所述第五有源层包括第九电极区、第十电极区、以及位于所述第九电极区和所述第十电极区之间的第五沟道区，所述第九电极区连接至所述电源线，所述第十电极区连接至所述第二电极区；和第六晶体管，包括第六有源层和连接至控制线的第六栅极，所述第六有源层包括第十一电极区、第十二电极区、以及位于所述第十一电极区和所述第十二电极区之间的第六沟道区，所述第十一电极区连接至所述第四电极区，所述第十二电极区连接至所述阳极。
在一些实施例中，所述至少一个子像素还包括：第七晶体管，包括第七有源层和连接至另一复位线的第七栅极，所述第七有源层包括第十三电极区、第十四电极区、以及 位于所述第十三电极区和所述第十四电极区之间的第七沟道区，所述第十三电极区连接至所述第十二电极区，所述第十四电极区连接至另一初始化线。
在一些实施例中，所述多个子像素中的每个子像素包括所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管。
在一些实施例中，所述第一有源层、第二有源层、第三有源层、第四有源层、第五有源层、第六有源层和第七有源层位于同一层。
在一些实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管中的每一个为P型晶体管。
在一些实施例中，所述第二电极板和所述初始化线位于同一层。
在一些实施例中，所述栅极线、所述第一电极板和所述复位线位于同一层。
在一些实施例中，所述数据线和所述电源线位于同一层。
在一些实施例中，所述栅极线与所述第一栅极一体设置；所述第一电极板与所述第二栅极一体设置；所述复位线与所述第三栅极一体设置。
根据本公开实施例的另一方面，提供一种显示装置，包括：上述任意一个实施例所述的显示面板。
根据本公开实施例的又一方面，提供一种显示面板的制造方法，包括：提供衬底基板；和在所述衬底基板上形成多个子像素，所述多个子像素中的至少一个子像素包括：发光元件，包括阳极和阴极；第一晶体管，包括第一有源层和连接至栅极线的第一栅极，所述第一有源层包括第一电极区、第二电极区、以及位于所述第一电极区和所述第二电极区之间的第一沟道区，所述第一电极区连接至数据线，所述第二电极区连接至电源线；电容器，包括第一电极板和连接至所述电源线的第二电极板；第二晶体管，包括第二有源层和连接至所述第一电极板的第二栅极，所述第二有源层包括第三电极区、第四电极区、以及位于所述第三电极区和所述第四电极区之间的第二沟道区，所述第三电极区连接至所述第二电极区，所述第四电极区连接至所述阳极；和第三晶体管，包括第三有源层和连接至复位线的第三栅极，所述第三有源层包括第五电极区、第六电极区、以及位于所述第五电极区和所述第六电极区之间的第三沟道区，所述第五电极区连接至所述第一电极板，所述第六电极区经由过孔直接连接至初始化线，其中，所述初始化线在所述衬底基板上的正投影位于所述复位线在所述衬底基板上的正投影与所述栅极线在所述衬底基板上的正投影之间。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本公开的示例性实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，在附图中：
图1是示出根据本公开一个实施例的显示面板的结构示意图；
图2是示出根据本公开一个实施例的子像素的结构示意图；
图3至图6是分别示出根据本公开一些实施例的子像素中的某一层的布局示意图；
图7A是示出根据本公开一个实施例的子像素中图3至图5所示的层叠加的布局示意图；
图7B是示出根据本公开一个实施例的子像素中图3至图6所示的层叠加的布局示意图；
图8是根据本公开一个实施例的第三晶体管的第六电极区与初始化线连接的截面示意图；
图9是根据本公开一个实施例的图7B的局部放大示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅 用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
发明人注意到，相关技术中，在显示面板的子像素中，与初始化线连接的晶体管需要通过额外的连接件与初始化线连接。一方面，额外的连接件会与其他信号线之间存在相互干扰，影响显示面板的显示效果；另一方面，在制造额外的连接件的过程中，残余物也会对显示面板的显示效果造成不利影响。
有鉴于此，本公开实施例提出了如下技术方案。
图1是示出根据本公开一个实施例的显示面板的结构示意图。
如图1所示，显示面板包括衬底基板11和位于衬底基板11上的多个子像素12。显示面板中的多个子像素12中的至少一个子像素12可以包括如图2所示的结构。
图2是示出根据本公开一个实施例的子像素的结构示意图。图3至图6是分别示出根据本公开一些实施例的子像素中的某一层的布局示意图。图7A是示出根据本公开一个实施例的子像素中图3至图5所示的层叠加的布局示意图。图7B是示出根据本公开一个实施例的子像素中图3至图6所示的层叠加的布局示意图。
需要说明的是，在本文中，不同布局示意图示出的各层也可以理解为各层在衬底基板11上的正投影。
如图2所示，子像素12可以包括发光元件D、第一晶体管T1、电容器C、第二晶体管T2和第三晶体管T3。发光元件D包括阳极D1和阴极D2。在一些实现方式中，发光元件D可以是有机发光二极管(OLED)。这里，第一晶体管T1也可以称为开关晶体管，第二晶体管T2也可以称为驱动晶体管，第三晶体管T3也可以称 为复位晶体管。
第一晶体管T1被配置为响应于栅极线Gate的扫描信号，在导通的情况下将来自数据线Data的数据信号传输至第二晶体管T2。第二晶体管T2被配置为在导通的情况下将驱动电流Id传输至发光元件D，以驱动发光元件D发光。第三晶体管T3被配置为响应于复位线Reset的复位信号，在导通的情况下将第二晶体管T2的栅极G2的电压复位至初始化线Vinit的电压。
在一个或多个实施例中，参见图2，子像素12还可以包括第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的一个或多个。这里，第四晶体管T4也可以称为补偿晶体管，第五晶体管T5也可以称为驱动控制晶体管，第六晶体管T6也可以称为发光控制晶体管，第七晶体管T7也可以称为旁路晶体管。例如，第四晶体管T4被配置为响应于栅极线Gate的扫描信号，在导通的情况下使得第二晶体管T2处于二极管连接状态。例如，第五晶体管T5和第六晶体管T6被配置为响应于控制线EM的控制信号，在导通的情况下使得发射电流Id流向发光元件D。例如，第七晶体管T7被配置为响应于另一复位线Reset’的复位信号，在导通的情况下使得驱动电流Id的一部分作为旁路电流Ibp流过。
在一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型晶体管。在另一些实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的一个或多个可以为N型薄膜晶体管。
例如，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的每一个的有源层可以如图3所示。有源层的材料例如可以包括多晶硅，例如低温多晶硅等。每个晶体管的有源层包括两个电极区和位于两个电极区之间的沟道区。应理解，两个电极区中的一个为源极区，另一个为漏极区。还应理解，两个电极区的掺杂浓度大于沟道区的掺杂浓度。换而言之，两个电极区中的每一个为导体区，而沟道区为半导体区。
参见图2和图3，第一晶体管T1包括第一有源层ACT1和连接至栅极线Gate的第一栅极G1。在一些实施例中，栅极线Gate和第一栅极G1可以一体设置。如图3所示，第一有源层ACT1包括第一电极区ACT11、第二电极区ACT12、以及位于第一电极区和第二电极区之间的第一沟道区ACT13。第一沟道区ACT13可以是第一 有源层ACT1与栅极线Gate重叠的区域。这里，第一电极区ACT11连接至数据线Data，第二电极区ACT12连接至电源线VDD。例如，第一电极区ACT11可以经由图7B所示的过孔V1连接至数据线Data。在一些实施例中，第二电极区ACT12可以经由第五晶体管T5的第五有源层ACT5连接至电源线VDD。例如，第五有源层ACT5可以经由图7B所示的过孔V2连接至电源线VDD。在一些实施例中，参见图6，数据线Data和电源线VDD可以位于同一层。
需要说明的是，在本文中，两个部件位于同一层是指这两个部件是通过对同一材料层进行图案化而形成的。
电容器C包括第一电极板C1和连接至电源线VDD的第二电极板C2。例如，第二电极板C2可以经由图7B所示的过孔V3连接至电源线VDD。
第二晶体管T2包括第二有源层ACT2和连接至第一电极板C1的第二栅极G2。在一些实施例中，第一电极板C1和第二栅极G2可以一体设置。如图3所示，第二有源层ACT2包括第三电极区ACT21、第四电极区ACT22、以及位于第三电极区ACT21和第四电极区ACT22之间的第二沟道区ACT23。参见图3和图7A，第二沟道区ACT23可以是第二有源层ACT2与第一电极板C1重叠的区域。第三电极区ACT21连接至第二电极区ACT12，第四电极区ACT22连接至阳极D1。在一些实施例中，第三电极区ACT21和第二电极区ACT12可以一体设置。在一些实施例中，第三电极区ACT21可以经由第五晶体管T5的第五有源层ACT5连接至电源线VDD。
第三晶体管T3包括第三有源层ACT3和连接至复位线Reset的第三栅极G3。在一些实施例中，复位线Reset和第三栅极G3可以一体设置。如图3所示，第三有源层ACT3包括第五电极区ACT31、第六电极区ACT32、以及位于第五电极区ACT31和第六电极区ACT32之间的第三沟道区ACT33。参见图3和图7A，第三沟道区ACT33可以是第三有源层ACT3与复位线Reset重叠的区域。
第五电极区ACT31连接至第一电极板C1。例如，第五电极区ACT31可以经由图7B所示的过孔V4连接至连接件CT，第一电极板C1可以经由图7B所示的过孔V5连接至连接件CT。第六电极区ACT32经由过孔V6直接连接至初始化线Vinit。在一些实施例中，参见图4，栅极线Gate、第一电极板C1和复位线Reset可以位于同一层。在一些实施例中，参见图5，第二电极板C2和初始化线Vinit可以位于同一层。在一些实施例中，参见图6，连接件CT、数据线Data和电源线VDD可以位于同一层。
参见图7B，初始化线Vinit在衬底基板11上的正投影位于复位线Reset在衬底基板上的正投影与栅极线Gate在衬底基板11上的正投影之间。
上述实施例中，初始化线Vinit位于复位线Reset与栅极线Gate之间，并且第三晶体管T3的第六电极区ACT32经由过孔V6直接连接至初始化线Vinit。这样的显示面板中，第六电极区ACT32无需额外的连接件连接至初始化线Vinit，减小了额外的连接件带来的寄生电容，提高了显示面板的显示效果。
另外，由于无需额外的连接件，可以避免额外的连接件在制造过程中残留物对显示面板的显示效果造成的不利影响。
图8是根据本公开一个实施例的第三晶体管的第六电极区与初始化线连接的截面示意图。
在一些实施例中，如图8所示，第一绝缘层GI1位于第三有源层ACT3远离衬底基板11的一侧，第三栅极G3位于第一绝缘层GI1远离衬底基板11的一侧，第二绝缘层GI2位于第三栅极G3和第一绝缘层GI1远离衬底基板11的一侧。
初始化线Vinit位于第二绝缘层GI2远离衬底基板11的一侧，并且经由贯穿第二绝缘层GI2和第一绝缘层GI1的过孔V6直接连接至第三晶体管T3的第六电极区ACT32。
层间绝缘层ILD位于初始化线Vinit和第二绝缘层GI2远离衬底基板11的一侧。可以理解的是，第三晶体管T3的源极和漏极中的一个可以经由贯穿层间绝缘层ILD的一个过孔连接至第五电极区ACT31和第六电极区ACT32中的一个，第三晶体管T3的源极和漏极中的另一个可以经由贯穿层间绝缘层ILD的另一个过孔连接至第五电极区ACT31和第六电极区ACT32中的另一个。
在第六电极区ACT32经由过孔V6直接连接至初始化线Vinit的情况下，参见图7B，过孔V6在衬底基板1上的正投影与初始化线Vinit在衬底基板11上的正投影至少部分交叠。
在一些实施例中，参见图7B和图8，过孔V6在衬底基板1上的正投影位于初始化线Vinit在衬底基板11上的正投影之内。这样的方式下，可以确保初始化线Vinit能够经由过孔V6连接至第六电极区ACT32。
在一些实施例中，参见图7B和图8，过孔V6在衬底基板1上的正投影位于第六电极区ACT32在衬底基板11上的正投影之内。这样的方式下，可以确保第六电极区ACT32能够经由过孔V6连接至初始化线Vinit。
图9是根据本公开一个实施例的图7A的局部放大示意图。需要说明的是，为了更清楚，图9仅示出了子像素的部分层，省略了某些层。
在一些实施例中，第三晶体管T3的第五电极区ACT1包括第一部分P1、第二部分P2、以及连接在第一部分P1和第二部分P2之间的第三部分P3。例如，第三部分P3的延伸方向与第一部分P1的延伸方向不同，并且与第二部分P2的延伸方向不同。
第三有源层ACT3还包括另一第六电极区ACT32’、以及位于第二部分P2和另一第六电极区ACT32’之间的另一第三沟道区ACT33’。第三栅极G3包括两个栅极G31和G32，两个栅极中的一个栅极G31位于第一部分P1和第六电极区ACT32之间，两个栅极中的另一个栅极G32位于第二部分P2和另一第六电极区ACT32’之间。
在一些实施例中，第六电极区ACT32包括第四部分P4和连接至第四部分P4的第五部分P5。第五部分P5位于第四部分P4远离第三沟道区ACT33的一侧，并且位于第四部分P4远离另一第六电极区ACT32’的一侧。过孔V6在衬底基板11上的正投影位于第五部分P5在衬底基板11上的正投影之内。第五部分P5在衬底基板11上的正投影位于初始化线Vinit在衬底基板11上的正投影之内。
在一些实施例中，第五部分P5的延伸方向与第四部分P4的延伸方向垂直。例如，第五部分P5的延伸方向与初始化线Vinit的延伸方向相同，第四部分P4的延伸方向与电源线VDD的延伸方向相同。这样的方式下，有利于减小第三有源层的长度，减小第三有源层与其他有源层之间的相互影响。
在一些实施例中，第五部分P5远离第四部分P4的端部在衬底基板11上的正投影具有弧度。这样的方式下，可以增大接触边缘，从而更可靠地使得过孔V6与第五部分P5连接。
在一些实施例中，第三部分P3在衬底基板11上的正投影位于电源线VDD在衬底基板11上的正投影之内。这样的方式下，第三部分P3和电源线VDD之间形成电容，有利于减小第三部分P3与其他信号线之间的相互影响，从而降低显示面板的串扰。
在一些实施例中，显示面板还可以包括与电源线VDD连接的金属层。例如，金属层与初始化线Vinit位于同一层。金属层在衬底基板11上的正投影与第一电极区ACT11在衬底基板11上的正投影交叠，并且与第五电极区ACT11在衬底基板11上的正投影交叠。如此，可以减小第一电极区ACT11和第五电极区ACT11的相互干扰，进一步降低显示面板的串扰，提高显示效果。
如上所述，在本公开各实施例的显示面板的多个子像素中，至少一个子像素12还可 以包括第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7中的一个或多个。
下面结合图2和图3对第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7进行介绍。
第四晶体管T4包括第四有源层ACT4和连接至栅极线Gate的第四栅极G4。在一些实施例中，栅极线Gate和第四栅极G4可以一体设置。如图3所示，第四有源层ACT4包括第七电极区ACT41、第八电极区ACT42、以及位于第七电极区ACT41和第八电极区ACT42之间的第四沟道区ACT43。第七电极区ACT41连接至第二栅极G2，第八电极区ACT42连接至第四电极区ACT22。例如，第七电极区ACT41可以经由图7B所示的过孔V4连接至连接件CT1，第二栅极G2可以经由图7B所示的过孔V5连接至连接件CT1。在一些实施例中，第七电极区ACT41和第五电极区ACT31可以一体设置。在一些实施例中，第八电极区ACT42和第四电极区ACT22可以一体设置。在某些实施例中，第四沟道区ACT43可以包括间隔开的两部分，即，第四栅极G4可以包括两个栅极。
第五晶体管T5包括第五有源层ACT5和连接至控制线EM的第五栅极G5。如图3所示，第五有源层ACT5包括第九电极区ACT51、第十电极区ACT52、以及位于第九电极区ACT51和第十电极区ACT52之间的第五沟道区ACT53。第九电极区ACT51连接至电源线VDD，第十电极区ACT52连接至第二电极区ACT12。例如，第九电极区ACT51可以经由图7B所示的过孔V2连接至电源线VDD。例如，第十电极区ACT52可以经由第三电极区ACT21连接至第二电极区ACT12。在一些实施例中，参见图4，控制线EM、栅极线Gate、第一电极板C1和复位线Reset可以位于同一层。
第六晶体管T6包括第六有源层ACT6和连接至控制线EM的第六栅极G6。如图3所示，第六有源层ACT6包括第十一电极区ACT61、第十二电极区ACT62、以及位于第十一电极区ACT61和第十二电极区ACT62之间的第六沟道区ACT63。第十一电极区ACT61连接至第四电极区ACT22，第十二电极区ACT62连接至阳极D1。在一些实施例中，第十一电极区ACT61和第四电极区ACT22可以一体设置。在一些实施例中，第十二电极区ACT62可以经由图7B所示的过孔V7连接至导电层M(例如金属层)，导电层M可以经由其他过孔连接至阳极D1。在一些实施例中，参见图6，导电层M、连接件CT、数据线Data和电源线VDD可以位于同一层。
第七晶体管T7包括第七有源层ACT7和连接至复位线Reset的第七栅极G7。在一些实施例中，复位线Reset和第七栅极G7可以一体设置。如图3所示，第七有源层ACT7 包括第十三电极区ACT71、第十四电极区ACT72、以及位于第十三电极区ACT71和第十四电极区ACT72之间的第七沟道区ACT73。第十三电极区ACT71连接至第十二电极区ACT62，第十四电极区ACT72连接至另一初始化线Vinit’。例如，第十四电极区ACT72可以经由类似于图7B所示的过孔V6直接连接至另一初始化线Vinit’。在一些实施例中，第十四电极区ACT72和第六电极区ACT32可以一体设置。
可以理解的是，图3所示的第七有源层ACT7为另一子像素的第七晶体管T7的第七有源层ACT7。
参见图3和图7A，第五沟道区ACT53可以是第五有源层ACT5与控制线EM重叠的区域，第六沟道区ACT63可以是第六有源层ACT6与控制线EM重叠的区域，第七沟道区ACT73可以是第七有源层ACT7与复位线重叠的区域。
在一些实施例中，参见图3，第一有源层ACT1、第二有源层ACT2、第三有源层ACT3、第四有源层ACT4、第五有源层ACT5、第六有源层ACT6和第七有源层ACT7可以位于同一层。
下面介绍根据本公开一些实施例的子像素的驱动方法。需要说明的是，在下面的描述中，假设子像素包括T1、T2、T3、T4、T5、T6和T7，并且，晶体管T1、T2、T3、T4、T5、T6和T7均为P型晶体管。
在复位阶段，第三晶体管T3响应于复位线Reset的复位信号而导通，第二晶体管T2的第二栅极G2经由第三晶体管T3连接到初始化线Vinit。如此，第二晶体管T2的第二栅极G2的电压被复位至初始化线Vinit的电压。
在补偿阶段，第一晶体管T1和第四晶体管T4响应于栅极线Gate的扫描信号而导通。这种情况下，第二晶体管T2处于二极管连接状态，并且处于正向偏置。第二晶体管T2的第二栅极G2的电压为来自数据线Data的数据信号的电压Vdata与第二晶体管T2的阈值电压Vth(负数)之和，即，Vdata+Vth。此时，电容器C的第一电极板C1的电压为Vdata+Vth，电容器C的第二电极板C2的电压为电源线VDD的电压ELVDD。电容器C被充入与第一电极板C1和第二电极板C2之间的电压差对应的电荷。
在发光阶段，第五晶体管T5和第六晶体管T6响应于控制线EM的控制信号而导通。响应于第二晶体管T2的第二栅极G2的电压与电源线VDD的电压之间的电压差而产生驱动电流Id，驱动电流Id通过第六晶体管T6被供应至发光元件D。在发光阶段，第二晶体管T2的栅源电压Vgs保持为(Vdata+Vth)-ELVDD。驱动电流Id与(Vdata-ELVDD) 2成比例。因此，驱动电流Id与第一晶体管T1的阈值电压Vth无关。
另外，在复位阶段，第七晶体管T7响应于复位线Reset的复位信号而导通。另外，第七晶体管T7可以与第一晶体管T1和第四晶体管T4同时导通。为了避免在第二晶体管T2截止的情况下的驱动电流Id驱动发光元件D发光，驱动电流Id的一部分可以作为旁路电流Ibp通过第七晶体管T7流出。
本公开实施例还提供了一种显示装置，显示装置可以包括上述任意一个实施例的显示面板。在一个实施例中，显示装置例如可以是移动终端、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
本公开实施例的还提供了一种显示面板的制造方法。显示面板的制造方法包括：提供基板；和在基板上形成多个子像素。至少一个子像素的结构包括发光元件、第一晶体管、电容器、第二晶体管和第三晶体管。
发光元件包括阳极和阴极。
第一晶体管包括第一有源层和连接至栅极线的第一栅极。第一有源层包括第一电极区、第二电极区、以及位于第一电极区和第二电极区之间的第一沟道区。第一电极区连接至数据线，第二电极区连接至电源线。
电容器包括第一电极板和连接至电源线的第二电极板。
第二晶体管包括第二有源层和连接至第一电极板的第二栅极。第二有源层包括第三电极区、第四电极区、以及位于第三电极区和第四电极区之间的第二沟道区。第三电极区连接至第二电极区，第四电极区连接至阳极。
第三晶体管包括第三有源层和连接至复位线的第三栅极。第三有源层包括第五电极区、第六电极区、以及位于第五电极区和第六电极区之间的第三沟道区。第五电极区连接至第一电极板，第六电极区经由过孔直接连接至初始化线。
初始化线在衬底基板上的正投影位于复位线在衬底基板上的正投影与栅极线在衬底基板上的正投影之间。
例如，在形成初始化线之前，利用掩模形成连接至第六电极区的过孔。例如，该过孔可以贯穿多层绝缘层，如上所述。
上述实施例中，初始化线位于复位线与栅极线之间，并且第三晶体管的第六电极区经由过孔直接连接至初始化线。这样的显示面板中，第六电极区无需额外的连接件连接至初始化线，减小了额外的连接件带来的寄生电容，提高了显示面板的显示效果。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实 施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种显示面板，包括：衬底基板和位于所述衬底基板上的多个子像素，所述多个子像素中的至少一个子像素包括：
    发光元件，包括阳极和阴极；
    第一晶体管，包括第一有源层和连接至栅极线的第一栅极，所述第一有源层包括第一电极区、第二电极区、以及位于所述第一电极区和所述第二电极区之间的第一沟道区，所述第一电极区连接至数据线，所述第二电极区连接至电源线；
    电容器，包括第一电极板和连接至所述电源线的第二电极板；
    第二晶体管，包括第二有源层和连接至所述第一电极板的第二栅极，所述第二有源层包括第三电极区、第四电极区、以及位于所述第三电极区和所述第四电极区之间的第二沟道区，所述第三电极区连接至所述第二电极区，所述第四电极区连接至所述阳极；和
    第三晶体管，包括第三有源层和连接至复位线的第三栅极，所述第三有源层包括第五电极区、第六电极区、以及位于所述第五电极区和所述第六电极区之间的第三沟道区，所述第五电极区连接至所述第一电极板，所述第六电极区经由过孔直接连接至初始化线，
    其中，所述初始化线在所述衬底基板上的正投影位于所述复位线在所述衬底基板上的正投影与所述栅极线在所述衬底基板上的正投影之间。
  2. 根据权利要求1所述的显示面板，其中，所述过孔在所述衬底基板上的正投影位于所述初始化线在所述衬底基板上的正投影之内。
  3. 根据权利要求1所述的显示面板，其中，所述过孔在所述衬底基板上的正投影位于所述第六电极区在所述衬底基板上的正投影之内。
  4. 根据权利要求1所述的显示面板，其中：
    所述第五电极区包括第一部分、第二部分、以及连接在所述第一部分和所述第二部分之间的第三部分；
    所述第三有源层还包括另一第六电极区、以及位于所述第二部分和所述另一第六电极区之间的另一第三沟道区；并且
    所述第三栅极包括两个栅极，所述两个栅极中的一个位于所述第一部分和所述第六电极区之间，所述两个栅极中的另一个位于所述第二部分和所述另一第六电极区之间。
  5. 根据权利要求4所述的显示面板，其中，所述第六电极区包括：
    第四部分；和
    连接至所述第四部分的第五部分，位于所述第四部分远离所述第三沟道区的一侧，并且位于所述第四部分远离所述另一第六电极区的一侧，其中：
    所述过孔在所述衬底基板上的正投影位于所述第五部分在所述衬底基板上的正投影之内，并且
    所述第五部分在所述衬底基板上的正投影位于所述初始化线在所述衬底基板上的正投影之内。
  6. 根据权利要求5所述的显示面板，其中，所述第五部分的延伸方向与所述第四部分的延伸方向垂直。
  7. 根据权利要求5所述的显示面板，其中，所述第五部分远离所述第四部分的端部在所述衬底基板上的正投影具有弧度。
  8. 根据权利要求4-7任意一项所述的显示面板，其中，所述第三部分在所述衬底基板上的正投影位于所述电源线在所述衬底基板上的正投影之内。
  9. 根据权利要求1-8任意一项所述的显示面板，其中，所述至少一个子像素还包括：
    第四晶体管，包括第四有源层和连接至所述栅极线的第四栅极，所述第四有源层包括第七电极区、第八电极区、以及位于所述第七电极区和所述第八电极区之间的第四沟道区，所述第七电极区连接至所述第二栅极，所述第八电极区连接至所述第四电极区。
  10. 根据权利要求9所述的显示面板，其中，所述至少一个子像素还包括：
    第五晶体管，包括第五有源层和连接至控制线的第五栅极，所述第五有源层包括第九电极区、第十电极区、以及位于所述第九电极区和所述第十电极区之间的第五沟道区，所述第九电极区连接至所述电源线，所述第十电极区连接至所述第二电极区；和
    第六晶体管，包括第六有源层和连接至控制线的第六栅极，所述第六有源层包括第十一电极区、第十二电极区、以及位于所述第十一电极区和所述第十二电极区之间的第六沟道区，所述第十一电极区连接至所述第四电极区，所述第十二电极区连接至所述阳极。
  11. 根据权利要求10所述的显示面板，其中，所述至少一个子像素还包括：
    第七晶体管，包括第七有源层和连接至另一复位线的第七栅极，所述第七有源层包括第十三电极区、第十四电极区、以及位于所述第十三电极区和所述第十四电极区之间的第七沟道区，所述第十三电极区连接至所述第十二电极区，所述第十四电极区连接至另一初始化线。
  12. 根据权利要求11所述的显示面板，其中：
    所述多个子像素中的每个子像素包括所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管。
  13. 根据权利要求11所述的显示面板，其中，所述第一有源层、第二有源层、第三有源层、第四有源层、第五有源层、第六有源层和第七有源层位于同一层。
  14. 根据权利要求11所述的显示面板，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管中的每一个为P型晶体管。
  15. 根据权利要求1-14任意一项所述的显示面板，其中，所述第二电极板和所述初始化线位于同一层。
  16. 根据权利要求1-14任意一项所述的显示面板，其中，所述栅极线、所述第一电极板和所述复位线位于同一层。
  17. 根据权利要求1-14任意一项所述的显示面板，其中，所述数据线和所述电源线位于同一层。
  18. 根据权利要求1-14任意一项所述的显示面板，其中：
    所述栅极线与所述第一栅极一体设置；
    所述第一电极板与所述第二栅极一体设置；
    所述复位线与所述第三栅极一体设置。
  19. 一种显示装置，包括：如权利要求1-18任意一项所述的显示面板。
  20. 一种显示面板的制造方法，包括：提供衬底基板；和在所述衬底基板上形成多个子像素，所述多个子像素中的至少一个子像素包括：
    发光元件，包括阳极和阴极；
    第一晶体管，包括第一有源层和连接至栅极线的第一栅极，所述第一有源层包括第一电极区、第二电极区、以及位于所述第一电极区和所述第二电极区之间的第一沟道区，所述第一电极区连接至数据线，所述第二电极区连接至电源线；
    电容器，包括第一电极板和连接至所述电源线的第二电极板；
    第二晶体管，包括第二有源层和连接至所述第一电极板的第二栅极，所述第二有源层包括第三电极区、第四电极区、以及位于所述第三电极区和所述第四电极区之间的第二沟道区，所述第三电极区连接至所述第二电极区，所述第四电极区连接至所述阳极；和
    第三晶体管，包括第三有源层和连接至复位线的第三栅极，所述第三有源层包括第五电极区、第六电极区、以及位于所述第五电极区和所述第六电极区之间的第三沟道区，所述第五电极区连接至所述第一电极板，所述第六电极区经由过孔直接连接至初始化线，
    其中，所述初始化线在所述衬底基板上的正投影位于所述复位线在所述衬底基板上的正投影与所述栅极线在所述衬底基板上的正投影之间。
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