WO2021017840A1 - 像素电路及其驱动方法、显示基板和显示面板 - Google Patents

像素电路及其驱动方法、显示基板和显示面板 Download PDF

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Publication number
WO2021017840A1
WO2021017840A1 PCT/CN2020/102235 CN2020102235W WO2021017840A1 WO 2021017840 A1 WO2021017840 A1 WO 2021017840A1 CN 2020102235 W CN2020102235 W CN 2020102235W WO 2021017840 A1 WO2021017840 A1 WO 2021017840A1
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Prior art keywords
sub
light
circuit
pixel
transistor
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PCT/CN2020/102235
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English (en)
French (fr)
Inventor
杨慧娟
刘庭良
张波
李依然
刘练彬
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/273,614 priority Critical patent/US11514856B2/en
Publication of WO2021017840A1 publication Critical patent/WO2021017840A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G2300/04—Structural and physical details of display devices
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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Definitions

  • the embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, a display substrate and a display panel.
  • AMOLED active-matrix organic light-emitting diode
  • At least one embodiment of the present disclosure provides a pixel circuit including: a driving sub-circuit, a light emission control sub-circuit, a data writing sub-circuit, a storage sub-circuit, and a first compensation sub-circuit, wherein the data writing sub-circuit is configured To write the data voltage into the storage sub-circuit under the control of the scan signal; the storage sub-circuit is configured to store the data voltage; the driving sub-circuit is electrically connected to the first node, and the light emitting element is electrically connected to the Two nodes, the driving sub-circuit is configured to drive the light-emitting element to emit light based on the data voltage; the light-emitting control sub-circuit is electrically connected to the first node and the second node, and the light-emitting control sub The circuit is configured to enable or disconnect the connection between the driving sub-circuit and the light-emitting element; the first compensation sub-circuit is electrically connected to the first node and the second node, and is It is configured to
  • the first compensation sub-circuit includes a first capacitor, a first end of the first capacitor is electrically connected to the first node, and the first capacitor The second end of is electrically connected to the second node.
  • the light emission control sub-circuit includes a light emission control transistor, the first electrode of the light emission control transistor is electrically connected to the first node, and the light emission control transistor The second electrode is electrically connected to the second node, and the gate of the light emission control transistor is configured to receive a light emission control signal.
  • the driving sub-circuit includes a driving transistor, a first electrode of the driving transistor is electrically connected to a first power terminal, and a second electrode of the driving transistor is electrically connected to the first power terminal.
  • the first node is electrically connected, and the gate of the driving transistor is electrically connected to the third node.
  • the data writing sub-circuit includes a data writing transistor
  • the storage sub-circuit includes a second capacitor
  • the first pole of the data writing transistor is configured In order to receive the data voltage, the second electrode of the data writing transistor is electrically connected to the first end of the second capacitor, the gate of the data writing transistor is configured to receive the scan signal, the The second end of the second capacitor is electrically connected to the third node.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a second compensation sub-circuit configured to receive a threshold compensation control signal and write to the third node according to the threshold compensation control signal Input threshold compensation voltage.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a reference voltage writing sub-circuit, and the reference voltage writing sub-circuit is configured to receive a reference voltage control signal and send a reference voltage control signal to the second The first end of the capacitor is written with a reference voltage.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a first reset sub-circuit, and the first reset sub-circuit is configured to receive a first reset control signal and send a signal to the third reset control signal according to the first reset control signal.
  • the node writes the first reset voltage.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a second reset sub-circuit configured to receive a second reset control signal and send the second reset control signal to the second reset control signal according to the second reset control signal.
  • the first terminal of the capacitor is written with a second reset voltage.
  • the pixel circuit provided by at least one embodiment of the present disclosure further includes a second compensation sub-circuit, a reference voltage writing sub-circuit, a first reset sub-circuit, and a second reset sub-circuit.
  • the first compensation sub-circuit includes a first capacitor.
  • the light emission control sub-circuit includes a light emission control transistor
  • the drive sub-circuit includes a drive transistor
  • the data writing sub-circuit includes a data writing transistor
  • the storage sub-circuit includes a second capacitor
  • the second compensator The circuit includes a threshold compensation transistor
  • the reference voltage writing sub-circuit includes a reference voltage writing transistor
  • the first reset sub-circuit includes a first reset transistor
  • the second reset sub-circuit includes a second reset transistor
  • the first reset sub-circuit includes a second reset transistor.
  • the first terminal of a capacitor is electrically connected to the first node, the second terminal of the first capacitor is electrically connected to the second node, and the first electrode of the light-emitting control transistor is electrically connected to the first node ,
  • the second pole of the light emission control transistor is electrically connected to the second node, the gate of the light emission control transistor is configured to receive a light emission control signal;
  • the first electrode of the drive transistor is electrically connected to the first power terminal ,
  • the second electrode of the driving transistor is electrically connected to the first node, the gate of the driving transistor is electrically connected to the third node;
  • the first light-emitting voltage applying electrode of the light-emitting element is electrically connected to the second Node, the second light-emitting voltage applying electrode of the light-emitting element is electrically connected to the second power supply terminal;
  • the first electrode of the data writing transistor is configured to receive the data voltage, and the second electrode of the data writing transistor Is electrically connected to the first terminal of the second capacitor, the
  • At least one embodiment of the present disclosure further provides a display substrate, including a base substrate, the pixel circuit according to any one of the above, and the light-emitting element, the light-emitting element and the pixel circuit are arranged on the base substrate on.
  • the first compensation sub-circuit when the first compensation sub-circuit includes a first capacitor, the first capacitor includes a first electrode and a second electrode, and the light-emitting element includes A first light-emitting voltage applying electrode, a second light-emitting voltage applying electrode, and a light-emitting layer provided between the first light-emitting voltage applying electrode and the second light-emitting voltage applying electrode, and the first electrode of the first capacitor is electrically connected To the first node, the second electrode of the first capacitor is electrically connected to the second node, and the second electrode of the first capacitor and the first light-emitting voltage applying electrode are integrally arranged, and are perpendicular to the In the direction of the base substrate, the first electrode of the first capacitor is located between the first light-emitting voltage application electrode and the base substrate, and the first light-emitting voltage application electrode is located at the end of the first capacitor. Between the first electrode and the light-emitting layer.
  • the orthographic projection of the first electrode of the first capacitor on the base substrate and the first light-emitting voltage application electrode are on the base substrate
  • the orthographic projections overlap at least partially.
  • At least one embodiment of the present disclosure further provides a method for driving the pixel circuit according to any one of the above, including: in a data writing stage, writing the data voltage to the driving sub-circuit, and based on the first The level of one node compensates the level of the second node; in the light-emitting phase, the driving sub-circuit drives the light-emitting element to emit light based on the data voltage.
  • At least one embodiment of the present disclosure further provides a display panel, including a base substrate and a plurality of repeating units located on the base substrate, each repeating unit of the plurality of repeating units includes a first sub-pixel and a second Two sub-pixels, the first sub-pixel includes a first light-emitting element and a first pixel circuit, the first pixel circuit is the pixel circuit according to any one of the above, and the first light-emitting element is formed by the first pixel circuit.
  • the light-emitting element driven by a pixel circuit.
  • the second sub-pixel includes a second light-emitting element and a second pixel circuit
  • the second pixel circuit is configured to drive the second light-emitting element to emit light
  • the driving sub-circuit in the first pixel circuit is located between the base substrate and the first light-emitting element
  • the driving sub-circuit in the second pixel circuit Located between the base substrate and the second light-emitting element, the orthographic projection of the driver sub-circuit in the first pixel circuit on the base substrate and the first light-emitting element on the base substrate
  • the orthographic projections on the second pixel circuit at least partially overlap, and the orthographic projection of the driving sub-circuit in the second pixel circuit on the base substrate and the orthographic projection of the second light-emitting element on the base substrate do not overlap.
  • the orthographic projection of the driving sub-circuit in the first pixel circuit on the base substrate is located on the first light-emitting element on the base substrate Within the orthographic projection.
  • each repeating unit further includes a third sub-pixel and a fourth sub-pixel, and the first sub-pixel and the second sub-pixel are both green sub-pixels. Pixels, the third sub-pixel is a red sub-pixel, and the fourth sub-pixel is a blue sub-pixel.
  • each repeating unit further includes a third subpixel and a fourth subpixel.
  • the first subpixel and the The second sub-pixels are arranged along a first direction
  • the third sub-pixels and the fourth sub-pixels are arranged along a second direction
  • the first direction and the second direction are respectively perpendicular to each other in the same plane Two directions.
  • the plurality of repeating units are arranged along the second direction to form a plurality of repeating unit groups, and the plurality of repeating unit groups are arranged along the first direction .
  • the first pixel circuit in the case where the first pixel circuit includes a first capacitor, a threshold compensation transistor, and a light emission control transistor, in the first direction, the first pixel circuit
  • the orthographic projection of the first electrode of the capacitor on the base substrate is located on the orthographic projection of the gate of the threshold compensation transistor on the base substrate and the orthographic projection of the gate of the light-emitting control transistor on the base substrate. Between projections.
  • FIG. 1 is a schematic diagram of a structure of a pixel repeating unit in a pixel arrangement structure
  • FIG. 2 is a schematic diagram of detection results of the anode voltage of the first green sub-pixel and the anode voltage of the second green sub-pixel in the pixel repeating unit shown in FIG. 1;
  • FIG. 3 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel circuit provided by some embodiments of the disclosure.
  • FIG. 5 is a schematic block diagram of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view of a first node in the pixel circuit shown in FIG. 4;
  • FIG. 7 is a schematic flowchart of a method for driving a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 8 is an exemplary timing chart of the driving method of the pixel circuit shown in FIG. 4;
  • FIG. 9 is a schematic diagram of a partial structure of a display panel provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a second pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 11 is a schematic cross-sectional view of a first node in the second pixel circuit shown in FIG. 10;
  • FIG. 12 is a schematic diagram of the detection results of the anode voltage of the first sub-pixel and the anode voltage of the second sub-pixel in the repeating unit shown in FIG. 9;
  • FIG. 13 is a schematic diagram of a repeating unit on a display panel provided by some embodiments of the present disclosure.
  • FIG. 14 is a plan partial schematic diagram of another display panel provided by some embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a pixel repeating unit in a pixel arrangement structure
  • FIG. 2 is a detection result of the anode voltage of the first green sub-pixel and the anode voltage of the second green sub-pixel in the pixel repeating unit shown in FIG. 1 Schematic.
  • a pixel arrangement structure includes a plurality of pixel repeating units 400 arranged on a base substrate (not shown), and the plurality of pixel repeating units 400 are arranged in an array along the A1 direction and the A2 direction.
  • Each pixel repeating unit 400 includes a red sub-pixel 401, a blue sub-pixel 402, a first green sub-pixel 403, and a second green sub-pixel 404.
  • the red sub-pixel 401 and the blue sub-pixel 402 are arranged along the A1 direction
  • the first green sub-pixel 403 and the second green sub-pixel 404 are arranged along the A2 direction
  • the first green sub-pixel 403 and the second green sub-pixel 404 are located between the red sub-pixel 401 and the blue sub-pixel 402.
  • the brightness of the first green sub-pixel 403 and the second green sub-pixel 404 are inconsistent, leading to the problem of missed detection of bright spots, that is, some The green sub-pixel cannot be detected.
  • the brightness of the first green sub-pixel 403 is higher than the brightness of the second green sub-pixel 404, so that the first green sub-pixel 403 is bright and the second green sub-pixel 404 is dark.
  • the orthographic projection of the gate of the driving transistor in the pixel circuit for driving the first green sub-pixel 403 on the base substrate is similar to that of the first green sub-pixel 403.
  • the orthographic projection of the anode of the light-emitting element on the base substrate does not overlap each other, and the orthographic projection of the gate of the driving transistor in the pixel circuit for driving the second green sub-pixel 404 on the base substrate and the second green
  • the orthographic projections of the anodes of the light-emitting elements of the sub-pixels 404 on the base substrate overlap each other.
  • the anode voltage of the first green sub-pixel 403 is 0.8682 volts (V)
  • the second green sub-pixel The anode voltage of 404 is 0.7597V, that is, the anode voltage of the first green sub-pixel 403 is greater than the anode voltage of the second green sub-pixel 404, resulting in that the brightness of the first green sub-pixel 403 is higher than that of the second green sub-pixel 404.
  • the display effect
  • At least some embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display substrate and a display panel.
  • the pixel circuit includes a driving subcircuit, a light emission control subcircuit, a data writing subcircuit, a storage subcircuit, and a first compensation subcircuit .
  • the data writing sub-circuit is configured to write the data voltage into the storage sub-circuit under the control of the scan signal; the storage sub-circuit is configured to store the data voltage; the driving sub-circuit is electrically connected to the first node, and the light emitting element is electrically connected to the second Node, the driving sub-circuit is configured to drive the light-emitting element to emit light; the light-emitting control sub-circuit is electrically connected to the first node and the second node, and the light-emitting control sub-circuit is configured to realize the connection between the driving sub-circuit and the light-emitting element. Disconnected; the first compensation sub-circuit is electrically connected to the first node and the second node, and is configured to compensate the level of the second node based on the level of the first node.
  • a first compensation sub-circuit is provided between the first node and the second node to compensate for the level of the second node, solve the problem of the difference in pixel brightness of the display panel, and make different pixels
  • the pixel brightness is consistent, thereby improving display uniformity and display effect.
  • the pixel circuit has a simple structure, is easy to design and manufacture, and has low cost.
  • FIG. 3 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure
  • FIG. 4 is a schematic structural diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • the pixel circuit 100 provided by the embodiment of the present disclosure includes a driving sub-circuit 11, a light emission control sub-circuit 12, a data writing sub-circuit 13, a storage sub-circuit 14 and a first compensation sub-circuit 15.
  • the data writing sub-circuit 13 is configured to write the data voltage into the storage sub-circuit 14 under the control of the scan signal; the storage sub-circuit 14 is configured to store the data voltage; the driving sub-circuit 11 is electrically connected to the first node N1, the light emitting element EL is electrically connected to the second node N2, and the driving sub-circuit 11 is configured to drive the light-emitting element EL to emit light based on the data voltage; the light-emitting control sub-circuit 12 is electrically connected to the first node N1 and the second node N2, and the light-emitting control sub-circuit 12 is It is configured to realize that the connection between the driving sub-circuit 11 and the light-emitting element EL is turned on or off; the first compensation sub-circuit 15 is electrically connected to the first node N1 and the second node N2, and is configured to be based on the first node N1 The level of the second node N2 compensates.
  • the pixel circuit 100 may be applied to a display panel, such as an active matrix organic light emitting diode (AMOLED) display panel, etc.
  • the pixel arrangement structure in the AMOLED display panel can be an RGBG pixel arrangement structure to increase the PPI (pixel per inch) of the display panel, thereby increasing the visual resolution of the display panel under the same display resolution. rate.
  • the pixel circuit 100 is applied to the AMOLED display panel, the problem of the difference in pixel brightness of the display panel can be solved, and the display uniformity and display effect can be improved.
  • the pixel circuit 100 and the light emitting element EL may be provided on a base substrate.
  • the first compensation sub-circuit 15 includes a first capacitor C1.
  • the first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the second node N2.
  • the first compensation sub-circuit 15 may include a parasitic capacitance between the first node N1 and the second node N2 (that is, the first capacitor C1 is a parasitic capacitance).
  • the first compensation sub-circuit The circuit 15 can control the level of the second node N2 based on the level of the first node N1 to compensate for the difference between the orthographic projection of the driving sub-circuit 11 of the pixel circuit on the base substrate and the anode of the light emitting element EL on the base substrate.
  • the influence of factors such as the overlap of orthographic projections on the level of the second node N2 improves the level control of the second node N2, thereby improving the display uniformity and the display effect.
  • the pixel circuit provided by the embodiment of the present disclosure can use the first capacitor C1, for example, to increase the level of the second node N2 to increase the brightness of the light emitting element EL.
  • the capacitance value of the first capacitor C1 may range from 1 fF to 8 fF.
  • the light emission control sub-circuit 12 may include a light emission control transistor M2.
  • the first pole of the emission control transistor M2 is electrically connected to the first node N1
  • the second pole of the emission control transistor M2 is electrically connected to the second node N2
  • the gate of the emission control transistor M2 is configured to be electrically connected to the emission control line EM to receive Lighting control signal VEM.
  • the driving sub-circuit 11 includes a driving transistor M1.
  • the first electrode of the driving transistor M1 is electrically connected to the first power supply terminal VDD
  • the second electrode of the driving transistor M1 is electrically connected to the first node N1
  • the gate of the driving transistor M1 is electrically connected to the third node N3. That is, the first terminal of the first capacitor C1 is electrically connected to the second terminal of the driving transistor M1.
  • the driving transistor M1 may be a P-type transistor.
  • the first electrode of the driving transistor M1 may be a source, and the second electrode of the driving transistor M1 may be a drain, which is described below as an example.
  • the driving transistor M1 is electrically connected to the light emitting element EL through the light emitting control transistor M2.
  • the light emission control transistor M2 When the light emission control transistor M2 is turned on, the connection between the driving transistor M1 and the light emitting element EL is turned on; when the light emission control transistor M2 is turned off, the connection between the driving transistor M1 and the light emitting element EL is disconnected.
  • the light emitting control transistor M2 can be turned off, so that the light emitting control transistor M2 can disconnect the connection between the driving transistor M1 and the light emitting element EL to ensure that the light emitting element EL does not emit light.
  • the light-emission control line EM can provide the light-emission control transistor M2 with a light-emission control signal VEM to turn on the light-emission control transistor M2, and the light-emission current can be transmitted to the light-emission via the turned-on driving transistor M1 and the light-emission control transistor M2 in turn.
  • the element EL drives it to emit light.
  • the first light-emitting voltage applying electrode of the light-emitting element EL (the anode of the light-emitting element EL in this embodiment) is electrically connected to the second node N2, and the second light-emitting voltage applying electrode (the In the embodiment, the cathode of the light emitting element EL) is electrically connected to the second power terminal VSS. That is, the second end of the first capacitor C1 is electrically connected to the first light-emitting voltage application electrode of the light-emitting element EL.
  • the light-emitting element EL is configured to receive a light-emitting signal (for example, a current signal) during operation, and emit light of an intensity corresponding to the light-emitting signal.
  • the light emitting element EL may be a light emitting diode, and the light emitting diode may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), etc., but the embodiments of the present disclosure are not limited thereto.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage.
  • the second power terminal VSS may also be grounded.
  • the data writing sub-circuit 13 includes a data writing transistor M3.
  • the first pole of the data writing transistor M3 is configured to receive the data voltage Vdata
  • the second pole of the data writing transistor M3 is electrically connected to the fourth node N4
  • the gate of the data writing transistor M3 is configured to receive the scan signal Vg1.
  • the first electrode of the data writing transistor M3 is electrically connected to the data line D to receive the data voltage Vdata
  • the gate of the data writing transistor M3 is electrically connected to the gate line G1 to receive the scan signal Vg1 .
  • the storage sub-circuit 14 includes a second capacitor C2.
  • the first end of the second capacitor C2 is electrically connected to the fourth node N4, that is, the second electrode of the data writing transistor M3 is electrically connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is electrically connected to
  • the third node N3 is electrically connected, that is, the second end of the second capacitor C2 is electrically connected to the gate of the driving transistor M1.
  • the capacitance value of the second capacitor C2 may range from 40 fF to 100 fF.
  • the pixel circuit 100 further includes a second compensation sub-circuit 16.
  • the second compensation sub-circuit 16 is configured to receive the threshold compensation control signal and write a threshold compensation voltage to the third node N3, that is, the gate of the driving transistor M1, according to the threshold compensation control signal.
  • the second compensation sub-circuit 16 may include a threshold compensation transistor M4.
  • the first pole of the threshold compensation transistor M4 is electrically connected to the first node N1, that is, the first pole of the threshold compensation transistor M4 is electrically connected to the second pole of the driving transistor M1, and the second pole of the threshold compensation transistor M4 is electrically connected to the third node.
  • the gate of the threshold compensation transistor M4 is electrically connected to the threshold compensation control line G2 to receive the threshold compensation control signal Vg2.
  • the threshold compensation control signal Vg2 and the scan signal Vg1 are the same.
  • the gate of the data writing transistor M3 and the gate of the threshold compensation transistor M4 may be electrically connected to the same signal line, such as the gate line G1, to receive the same signal (for example, the scan signal Vg1).
  • the The display panel of the pixel circuit 100 may not be provided with the threshold compensation control line G2 to reduce the number of signal lines.
  • the gate of the data writing transistor M3 and the gate of the threshold compensation transistor M4 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor M3 is electrically connected to the gate line G1, and the threshold compensation transistor M4
  • the gate of G1 is electrically connected to the threshold compensation control line G2, and the gate line G1 and the threshold compensation control line G2 transmit the same signal.
  • threshold compensation control signal Vg2 and the scan signal Vg1 are also different, so that the data writing transistor M3 and the threshold compensation transistor M4 can be controlled separately, which increases the flexibility of controlling the pixel circuit.
  • the pixel circuit 100 further includes a reference voltage writing sub-circuit 17.
  • the reference voltage writing sub-circuit 17 is configured to receive the reference voltage control signal VCR and write the reference voltage to the first end of the second capacitor C2 (ie the fourth node N4) according to the reference voltage control signal VCR.
  • the reference voltage writing sub-circuit 17 may include a reference voltage writing transistor M5.
  • the first pole of the reference voltage writing transistor M5 is configured to receive the reference voltage Vref
  • the second pole of the reference voltage writing transistor M5 is electrically connected to the first end of the second capacitor C2
  • the reference voltage writing transistor M5 has the gate It is configured to receive the reference voltage control signal VCR.
  • the first pole of the reference voltage writing transistor M5 may be electrically connected to the reference power terminal REF to receive the reference voltage Vref
  • the gate of the reference voltage writing transistor M5 may be electrically connected to the reference voltage control line CR to receive the reference voltage control Signal VCR.
  • the reference voltage control line CR may provide the reference voltage control signal VCR to the gate of the reference voltage writing transistor M5 to turn on the reference voltage writing transistor M5.
  • the reference power terminal REF can provide a reference voltage V ref to the first pole of the reference voltage writing transistor M5, so that the reference voltage V ref charges the first terminal of the second capacitor C2 through the reference voltage writing transistor M5, thereby the second capacitor
  • the voltage at the first terminal of C2 may be the reference voltage V ref .
  • the reference voltage control signal VCR and the light emission control signal VEM may be the same.
  • the gate of the emission control transistor M2 and the gate of the reference voltage writing transistor M5 may be electrically connected to the same signal line, such as the emission control line EM, to receive the same signal (for example, the emission control signal VEM).
  • the display panel including the pixel circuit 100 may not be provided with the reference voltage control line CR, which reduces the number of signal lines.
  • reference voltage control signal VCR and the light emission control signal VEM may also be different, which is not limited in the embodiment of the present disclosure.
  • the pixel circuit 100 further includes a first reset sub-circuit 18.
  • the first reset sub-circuit 18 is configured to receive a first reset control signal and write a first reset voltage to the third node N3 (ie, the gate of the driving transistor M1) according to the first reset control signal.
  • the first reset sub-circuit 18 includes a first reset transistor M6.
  • the first electrode of the first reset transistor M6 is configured to receive the first reset voltage
  • the second electrode of the first reset transistor M6 is electrically connected to the third node N3, that is, the second electrode of the first reset transistor M6 is electrically connected to the driving transistor
  • the gate of M1 and the gate of the first reset transistor M6 are configured to receive the first reset control signal Vrt1.
  • the first electrode of the first reset transistor M6 is electrically connected to the first reset power terminal VINT to receive the first reset voltage Vint1
  • the gate of the first reset transistor M6 is electrically connected to the first reset control signal line Rst1 to receive the first reset voltage. Reset control signal Vrt1.
  • the first reset power terminal VINT is a DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal VINT may be a high-voltage terminal or a low-voltage terminal, as long as it can provide the first reset voltage Vint1 to reset the third node N3, which is not limited in the present disclosure.
  • the pixel circuit 100 further includes a second reset sub-circuit 19.
  • the second reset sub-circuit 19 is configured to receive a second reset control signal and write a second reset voltage to the first end of the second capacitor C2 (ie, the fourth node N3) according to the second reset control signal.
  • the second reset sub-circuit 19 includes a second reset transistor M7.
  • the first voltage output by the first power terminal VDD can be used as the second reset voltage Vint2, so that the first electrode of the second reset transistor M7 is electrically connected to the first power terminal VDD.
  • the second terminal of the second reset transistor M7 is electrically connected to the first terminal of the second capacitor C2.
  • the gate of the second reset transistor M7 is configured to receive the second reset control signal Vrt2, for example, the gate of the second reset transistor M7 is electrically connected to the second reset control signal line Rst2 to receive the second reset control signal Vrt2.
  • the embodiment of the present disclosure is not limited to this, and the first pole of the second reset transistor M7 may also be electrically connected to a separately provided second reset power terminal to receive the second reset voltage Vint2.
  • the first reset control signal Vrt1 and the second reset control signal Vrt2 may be the same, so that the gate of the first reset transistor M6 and the gate of the second reset transistor M7 may be electrically connected to the same signal line (for example, the first reset The signal line Rst1) is controlled to receive the same reset control signal (for example, the first reset control signal Vrt1). It should be noted that the first reset control signal Vrt2 and the second reset control signal Vrt2 may also be different.
  • the first reset voltage Vint1 and the second reset voltage Vint2 may be the same.
  • the storage sub-circuit is only illustrative, the second compensation sub-circuit, the reference voltage writing sub-circuit, the first reset sub-circuit, the second reset sub-circuit, the light emission control sub-circuit, the data writing sub-circuit, the storage sub-circuit and other circuits
  • the specific structure of can be set according to actual application requirements, which is not specifically limited in the embodiments of the present disclosure.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to explain in detail the description of the present disclosure.
  • the transistors of the embodiments of the present disclosure are not limited to P-type transistors.
  • N-type transistors for example, N-type MOS transistors
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors. .
  • the source and drain of the transistor can be symmetric in structure, so the source and drain can be indistinguishable in physical structure.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, in the embodiments of the present disclosure, all or part of the transistors have the first pole.
  • the first pole and the second pole are interchangeable as needed.
  • FIG. 5 is a schematic block diagram of a display substrate provided by some embodiments of the present disclosure
  • FIG. 6 is a schematic cross-sectional view of a first node in the pixel circuit shown in FIG. 4.
  • the display substrate 200 may include a base substrate 110 and the pixel circuit 100 and the light emitting element EL according to any embodiment of the present disclosure. Both the light emitting element EL and the pixel circuit 100 are provided on the base substrate 110.
  • the display substrate 200 may be applied to an organic light emitting diode display panel or the like.
  • the display substrate 200 may be an array substrate.
  • the base substrate 110 may be a suitable substrate such as a glass substrate or a quartz substrate.
  • the first capacitor C1 when the first compensation sub-circuit in the pixel circuit 100 includes the first capacitor, for example, taking the embodiment shown in FIG. 4 as an example, as shown in FIG. 6, the first capacitor C1 includes The first electrode 321 and the second electrode, the first electrode 321 of the first capacitor C1 is the first terminal of the first capacitor C1, and the second electrode of the first capacitor C1 is the second terminal of the first capacitor C1, that is, the first capacitor
  • the first electrode 321 of C1 is electrically connected to the first node N1, that is, the first electrode 321 of the first capacitor C1 is electrically connected to the second electrode (for example, the drain) of the driving transistor M1, and the second electrode of the first capacitor C1 is electrically connected. It is connected to the second node N2, that is, the second electrode of the first capacitor C1 is electrically connected to the first light-emitting voltage application electrode of the light-emitting element EL.
  • the first intermediate layer 331 may include a gate insulating layer (GI layer), a gate layer (GATE layer), an interlayer dielectric layer (ILD), etc. of transistors (e.g., light emission control transistors, driving transistors, etc.) in the pixel circuit
  • the second intermediate layer 332 may include an active semiconductor layer or the like of a transistor (for example, a light emission control transistor, a driving transistor, etc.) in a pixel circuit.
  • the gate insulating layer and the interlayer dielectric layer are inorganic layers, and the gate layer and the like are metal layers.
  • the light emitting element EL includes a first light emitting voltage applying electrode 301, a second light emitting voltage applying electrode 302, and a light emitting layer provided between the first light emitting voltage applying electrode 301 and the second light emitting voltage applying electrode 302. 303.
  • the material of the light-emitting layer 303 can be selected according to the color of light emitted by the light-emitting element EL.
  • the material of the light-emitting layer 303 includes a fluorescent light-emitting material or a phosphorescent light-emitting material.
  • the first light-emitting voltage applying electrode 301 is an anode
  • the second light-emitting voltage applying electrode 302 is a cathode
  • both the first light-emitting voltage applying electrode 301 and the second light-emitting voltage applying electrode 302 are made of conductive materials.
  • a first organic layer 311 is provided between the first light-emitting voltage application electrode 301 and the light-emitting layer 303, and a second organic layer 312 is provided between the second light-emitting voltage application electrode 302 and the light-emitting layer 303.
  • the first organic layer 311 and the second organic layer 312 are used for leveling and may be omitted.
  • the light-emitting layer of each light-emitting element may include the electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, for example, hole injection layer, hole transport Layer, electron injection layer, electron transport layer, etc., but in the drawings of the present disclosure, only the electroluminescent layer in the light-emitting layer is shown, and other common layers are not shown.
  • the orthographic projection of the first light-emitting voltage application electrode 301 on the base substrate 110, the orthographic projection of the light-emitting layer 303 on the base substrate 110, and the orthographic projection of the second light-emitting voltage application electrode 302 on the base substrate 110 are at least partially overlap.
  • the orthographic projection of the first light-emitting voltage application electrode 301 on the base substrate 110 is located within the orthographic projection of the second light-emitting voltage application electrode 302 on the base substrate 110, and the orthographic projection of the light-emitting layer 303 on the base substrate 110 is located
  • the second light-emitting voltage application electrode 302 is in an orthographic projection on the base substrate 110.
  • the orthographic projection of the first light-emitting voltage application electrode 301 on the base substrate 110 In the area where the orthographic projection of the light-emitting layer 303 on the base substrate 110 and the orthographic projection of the second light-emitting voltage application electrode 302 on the base substrate 110 overlap, the portion corresponding to the opening of the pixel defining layer is used for light emission.
  • the first electrode 321 of the first capacitor C1 is located between the first light-emitting voltage application electrode 301 and the base substrate 110, and the first light-emitting voltage application electrode 301 is located in the first capacitor C1. Between the first electrode 321 and the light-emitting layer 303.
  • the second electrode of the first capacitor C1 and the first light-emitting voltage applying electrode 301 are integrated, that is, the second electrode of the first capacitor C1 and the first light-emitting voltage applying electrode 301 are the same electrode, and the first light-emitting voltage
  • the applying electrode 301 is multiplexed as the second electrode of the first capacitor C1. Therefore, in the pixel circuit provided by the embodiment of the present disclosure, the first electrode 321 of the first capacitor C1 is formed only by adding a metal layer between the first light-emitting voltage applying electrode 301 and the first intermediate layer 331.
  • the first electrode 321 of C1 and the first light-emitting voltage application electrode 301 can form the first capacitor C1, thereby realizing compensation for the level of the second node, solving the problem of pixel brightness differences of the display panel, and improving display uniformity and display effect.
  • the second electrode of the first capacitor C1 and the first light-emitting voltage application electrode 301 may also be two separate electrodes, but the second electrode of the first capacitor C1 and the first light-emitting voltage application electrode 301 are electrically connected to each other.
  • the orthographic projection of the first electrode 321 (ie, the added metal layer) of the first capacitor C1 on the base substrate 110 and the orthographic projection of the first light-emitting voltage applying electrode 301 on the base substrate 110 at least partially overlap.
  • the orthographic projection of the first electrode 321 of the first capacitor C1 on the base substrate 110 is within the orthographic projection of the first light-emitting voltage application electrode 301 on the base substrate 110, that is, the first light-emitting voltage application
  • the orthographic projection of the electrode 301 on the base substrate 110 completely covers the orthographic projection of the first electrode 321 of the first capacitor C1 on the base substrate 110.
  • a dielectric layer 341 is further provided between the first light-emitting voltage application electrode 301 and the first electrode 321, and the first light-emitting voltage application electrode 301 and the first electrode 321 are not directly electrically connected.
  • FIG. 7 is a schematic flowchart of a method for driving a pixel circuit according to some embodiments of the present disclosure. As shown in FIG. 7, the driving method of the pixel circuit includes the following steps:
  • the driving sub-circuit drives the light-emitting element to emit light based on the data voltage.
  • the driving method of the pixel circuit further includes: , Use the first reset sub-circuit to reset the third node, and use the second reset sub-circuit to reset the fourth node.
  • timing diagram of the pixel circuit can be set according to actual requirements, which is not specifically limited in the embodiments of the present disclosure.
  • FIG. 8 is an exemplary timing chart of the driving method of the pixel circuit shown in FIG. 4.
  • the operation flow of a driving method of a pixel circuit provided by an embodiment of the present disclosure will be described in detail below with reference to FIGS. 4 and 8.
  • the first reset control signal Vrt1 and the second reset control signal Vrt2 are the same
  • the threshold compensation control signal Vg2 is the same as the scan signal Vg1
  • the reference voltage control signal VCR and the light emission control signal VEM are the same. All transistors in the pixel circuit are P-type transistors.
  • the first reset control signal Vrt1 and the second reset control signal Vrt2 are both low-level signals (ie, turn-on signals, such as -6V), and the scan signal Vg1 and the threshold
  • the compensation control signal Vg2, the reference voltage control signal VCR, and the light emission control signal VEM are all high-level signals (ie cut-off signals, such as 6V), so that the first reset transistor M6 and the second reset transistor M7 are both turned on, and the light emission control transistor M2 ,
  • the data writing transistor M3, the threshold compensation transistor M4, and the reference voltage writing transistor M5 are all turned off.
  • the first reset voltage Vint1 output from the first reset power supply terminal VINT is written into the third node N3 (that is, the gate of the driving transistor M1 and the second end of the second capacitor C2) via the first reset transistor M6 to provide a negative effect on the third node N3.
  • the second reset voltage Vint2 output from the first power supply terminal VDD is written into the fourth node N4 (ie, the first end of the second capacitor C2) via the second reset transistor M7 to reset the fourth node N4.
  • the voltage on the third node N3 is the first reset voltage Vint1
  • the voltage on the fourth node N4 is the second reset voltage Vint2
  • the first reset voltage Vint1 and the second reset voltage Vint2 are the same, Therefore, the voltage on the third node N3 and the voltage on the fourth node N4 are the same.
  • the first reset control signal Vrt1 and the second reset control signal Vrt2 become high-level signals, and the scan signal Vg1 and the threshold compensation control signal Vg2 become low.
  • the level signal, the reference voltage control signal VCR and the light emission control signal VEM are maintained as high level signals.
  • the data writing transistor M3 and the threshold compensation transistor M4 are all turned on, and the first reset transistor M6, the second reset transistor M7, the light emission control transistor M2, and the reference voltage writing transistor M5 are all turned off.
  • the data writing transistor M3 Since the data writing transistor M3 is turned on, the data voltage Vdata (for example, the range of the data voltage Vdata is 2.1V to 4.5V) is written to the fourth node N4 via the data writing transistor M3, so that the voltage on the fourth node N4 changes Is the data voltage Vdata. Due to the bootstrap effect of the second capacitor C2, the voltage on the third node N3 also becomes the data voltage Vdata.
  • the threshold compensation transistor M4 is turned on, and the driving transistor M1 forms a diode connection to control the driving transistor M1 Is also turned on, the threshold compensation transistor M4 is also turned on, and the first voltage V1 output by the first power supply terminal VDD can charge the third node N3 via the driving transistor M1 and the threshold compensation transistor M4.
  • Vth is the threshold voltage of the driving transistor M1
  • the voltage difference between the first electrode of the driving transistor M1 (the voltage of the first electrode of the driving transistor M1 is the first voltage V1) and the gate is the same as the threshold voltage of the driving transistor M1
  • the threshold compensation voltage may be V1+Vth.
  • the threshold compensation transistor M4 since the threshold compensation transistor M4 is turned on, the voltage of the first node N1 and the voltage of the third node N3 are the same, so the voltage of the first node N1 changes with the voltage of the third node N3.
  • the change process is the same. Due to the bootstrap effect of the first capacitor C1, when the voltage of the first node N1 changes, the voltage of the second node N2 can be controlled to change accordingly, thereby realizing compensation for the second node N2. For example, if the voltage of the first node N1 gradually increases, the voltage of the second node N2 also gradually increases.
  • the first reset control signal Vrt1 and the second reset control signal Vrt2 remain high-level signals, and the scan signal Vg1 and the threshold compensation control signal Vg2 become high-level signals.
  • the reference voltage control signal VCR and the light emission control signal VEM become low level signals.
  • the light emission control transistor M2 and the reference voltage writing transistor M5 are both turned on, and the data writing transistor M3, the threshold compensation transistor M4, the first reset transistor M6 and the second reset transistor M7 are all turned off.
  • the reference voltage writing transistor M5 Since the reference voltage writing transistor M5 is turned on, the reference voltage V ref is written to the fourth node N4 via the reference voltage writing transistor M5, so that the voltage on the fourth node N4 becomes the reference voltage V ref , that is, on the fourth node N4 The voltage of the data voltage Vdata becomes the reference voltage V ref . Due to the bootstrap effect of the second capacitor C2, the voltage on the third node N3 becomes V ref -Vdata+V1+Vth, that is, the voltage on the gate of the driving transistor M1 The voltage is V ref -Vdata+V1+Vth, and the voltage on the first pole of the driving transistor M1 is the first voltage V1.
  • step S12 “the driving sub-circuit drives the light-emitting element to emit light based on the data voltage” means that the driving sub-circuit is turned on under the control of the voltage V ref ⁇ Vdata+V1+Vth to drive the light-emitting element to emit light.
  • the driving transistor M1 is in saturation.
  • the saturation current formula of the driving transistor M1 the light-emitting current IEL flowing through the driving transistor M1 can be expressed as:
  • the light-emitting current I EL is not affected by the threshold voltage Vth of the driving transistor M1 and the first voltage output by the first power supply terminal VDD, but only with the reference voltage V ref output by the reference power supply terminal REF and The data voltage Vdata is related.
  • the data voltage Vdata is directly transmitted by the data line and has nothing to do with the threshold voltage Vth of the driving transistor M1, so that the problem of the threshold voltage drift of the driving transistor M1 due to the process and long-term operation can be solved.
  • the reference voltage V ref is provided by the reference power terminal REF, which has nothing to do with the power supply voltage drop (IR drop) of the first power terminal VDD, so that the IR drop problem of the display panel can be solved.
  • the pixel circuit can ensure the accuracy of the light-emitting current IEL, eliminate the influence of the threshold voltage of the driving transistor M1 and IR drop on the light-emitting current IEL, and ensure the normal operation of the light-emitting element EL.
  • this pixel circuit by adding a first capacitor C1 between the first node N1 and the second node N2, the level of the second node N2 is compensated based on the level of the first node N1, thereby solving The problem of the difference in pixel brightness of the display panel improves the uniformity of the display picture and improves the display effect.
  • K is a constant, and K can be expressed as:
  • ⁇ n is the electron mobility of the driving transistor M1
  • C ox is the gate of the driving transistor M1 unit capacitance
  • W is the channel width of the driving transistor M1
  • L is a channel length of the driving transistor M1.
  • the setting modes of the reset phase, the data writing phase, and the light-emitting phase can be set according to actual application requirements, which are not specifically limited in the embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of a partial structure of a display panel provided by some embodiments of the present disclosure.
  • a display panel 500 provided by an embodiment of the present disclosure includes a base substrate 501 and a plurality of repeating units 502 located on the base substrate 501.
  • Each repeating unit 502 includes a first sub-pixel 5021, a second sub-pixel 5022, a third sub-pixel 5023, and a fourth sub-pixel 5024.
  • the first sub-pixel 5021 includes a first light-emitting element and a first pixel circuit.
  • the first pixel circuit is the pixel circuit according to any one of the above embodiments.
  • the first light-emitting element is a light-emitting element driven by the first pixel circuit, that is, In other words, the first pixel circuit may be the pixel circuit 100 shown in FIG. 4, and the first light-emitting element may be the light-emitting element EL shown in FIG.
  • the orthographic projection of the gate of the driving transistor in the first pixel circuit of the first sub-pixel 5021 on the base substrate is in line with the anode of the first light-emitting element of the first sub-pixel 5021
  • the orthographic projections on the base substrate at least partially overlap each other, and the orthographic projection of the gate of the driving transistor in the second pixel circuit of the second sub-pixel 5022 on the base substrate and the second light-emitting element of the second sub-pixel 5022
  • the orthographic projections of the anodes on the base substrate do not overlap each other.
  • only the shape of the anode of each sub-pixel is shown in FIG. 9.
  • FIG. 10 is a schematic structural diagram of a second pixel circuit provided by some embodiments of the present disclosure.
  • the second sub-pixel 5022 includes a second light-emitting element EL′ and a second pixel circuit, and the second pixel circuit is configured to drive the second light-emitting element EL′ to emit light.
  • the second pixel circuit does not include the first capacitor provided between the first node N1 and the second node N2.
  • the remaining components in the second pixel circuit and the first pixel circuit The rest of the components are the same, that is, as shown in FIG.
  • the second pixel circuit may include a driving sub-circuit 11', a light-emitting control sub-circuit 12', a data writing sub-circuit 13', a storage sub-circuit 14', and a second compensation circuit.
  • the sub-circuit 16', the reference voltage writing sub-circuit 17', the first reset sub-circuit 18', the second reset sub-circuit 19', etc., and the connection mode of each sub-circuit is the same as that of the corresponding sub-circuit in the first pixel circuit
  • the connection method is the same.
  • FIG. 11 is a schematic cross-sectional view of the first node in the second pixel circuit shown in FIG. 10.
  • the second light-emitting element EL' includes a first light-emitting voltage applying electrode 301', a second light-emitting voltage applying electrode 302', and a first light-emitting voltage applying electrode 301' and a second light-emitting voltage applying electrode 302'.
  • a first organic layer 311' is provided between the first light-emitting voltage application electrode 301' and the light-emitting layer 303'
  • a second organic layer 312' is provided between the second light-emitting voltage application electrode 302' and the light-emitting layer 303'.
  • a first intermediate layer 331' and a second intermediate layer 332' are also provided between the first light-emitting voltage applying electrode 301' and the base substrate 501.
  • no metal layer is provided at the first node of the second pixel circuit, that is, no capacitor is provided between the first node and the second node.
  • the driving sub-circuit in the first pixel circuit is located between the base substrate 501 and the first light-emitting element
  • the driving sub-circuit in the second pixel circuit is located between the base substrate 501 and the base substrate 501. Between the second light-emitting elements.
  • the orthographic projection of the driver sub-circuit in the first pixel circuit on the base substrate 501 and the orthographic projection of the first light-emitting element on the base substrate 501 at least partially overlap, for example, the driver sub-circuit in the first pixel circuit is on the substrate
  • the orthographic projection on the substrate 501 is located within the orthographic projection of the first light-emitting element on the base substrate 501, for example, the orthographic projection of the driver sub-circuit in the first pixel circuit on the base substrate 501 and the orthographic projection of the first light-emitting element on the substrate 501
  • the orthographic projections on the substrate 501 completely overlap.
  • the orthographic projection of the driver sub-circuit in the second pixel circuit on the base substrate 501 and the orthographic projection of the second light-emitting element on the base substrate 501 are at least partially non-overlapping.
  • the driver sub-circuit in the second pixel circuit is on the base substrate 501.
  • the orthographic projection on the base substrate 501 and the orthographic projection of the second light-emitting element on the base substrate 501 do not overlap at all.
  • the orthographic projection of the gate of the driving transistor in the first sub-pixel 5021 on the base substrate 501 overlaps the orthographic projection of the anode of the first light-emitting element on the base substrate 501, while the orthographic projection of the gate of the second sub-pixel 5022
  • the orthographic projection of the gate of the driving transistor on the base substrate 501 and the orthographic projection of the anode of the second light-emitting element on the base substrate 501 do not overlap.
  • the driver in the first sub-pixel 5021 The orthographic projection of the circuit on the base substrate 501 overlaps with the orthographic projection of the anode of the first light-emitting element on the base substrate 501, and the orthographic projection of the driving sub-circuit in the second sub-pixel 5022 on the base substrate 501 overlaps
  • the orthographic projection of the anode of the second light-emitting element on the base substrate 501 does not overlap, and the voltage at the gate of the driving transistor in the second pixel circuit of the second sub-pixel 5022 is higher than that of the first sub-pixel 5021.
  • the voltage at the gate of the driving transistor in the pixel circuit is small, so that the light-emitting current flowing through the driving transistor in the second pixel circuit of the second sub-pixel 5022 is greater than that flowing through the first sub-pixel circuit in the first sub-pixel 5021
  • the brightness of the second light-emitting element is higher than that of the first light-emitting element, which causes the brightness of the first sub-pixel and the second sub-pixel to be inconsistent.
  • FIG. 12 is a schematic diagram of the detection results of the anode voltage of the first sub-pixel and the anode voltage of the second sub-pixel in the repeating unit shown in FIG. 9.
  • the first compensation sub-circuit in the first pixel circuit can affect the second node Is compensated to increase the brightness of the first light-emitting element, so that the brightness of the first light-emitting element is consistent with the brightness of the second light-emitting element.
  • the capacitance value of the first capacitor C1 in the first pixel circuit may range from 1fF to 8fF, but the present disclosure is not limited to this, as long as the first capacitor C1 can enable the first pixel circuit in the first sub-pixel
  • the voltage of the second node and the second node in the second pixel circuit of the second sub-pixel may be equivalent.
  • the voltage of the second node in the first pixel circuit and the voltage of the second node in the second pixel circuit may be approximately Just equal.
  • FIG. 12 a simulation analysis of the first sub-pixel 5021 and the second sub-pixel 5022 in a repeating unit shown in FIG.
  • the anode voltage of the first sub-pixel 5021 is 0.8682 volts (V )
  • the anode voltage of the second sub-pixel 5022 is 0.8682V, that is, the anode voltage of the first sub-pixel 5021 is equal to the anode voltage of the second sub-pixel 5022
  • the brightness of the first sub-pixel 5021 is the same as that of the second sub-pixel 5022 , Thereby improving the brightness uniformity of the display panel.
  • the third sub-pixel 5023 may include a third light-emitting element and a third pixel circuit, and the third pixel circuit is configured to drive the third light-emitting element to emit light.
  • the fourth sub-pixel 5024 may include a fourth light-emitting element and a fourth pixel circuit, and the fourth pixel circuit is configured to drive the fourth light-emitting element to emit light. Both the third pixel circuit and the fourth pixel circuit may be the same as the second pixel circuit shown in FIG. 10.
  • the first sub-pixel 5021 and the second sub-pixel 5022 are both green sub-pixels
  • the third sub-pixel 5023 is a red sub-pixel
  • the fourth sub-pixel 5024 is a blue sub-pixel. That is, the first light emitting element and the second light emitting element are both configured to emit green light, the third light emitting element is configured to emit red light, and the fourth light emitting element is configured to emit blue light.
  • the orthographic projection of the light-emitting layer of the light-emitting element (ie, the first light-emitting element) of the first sub-pixel 5021 on the base substrate 110 is in line with the light-emitting layer of the light-emitting element (ie, the second light-emitting element) of the second sub-pixel 5022.
  • the orthographic projection on the base substrate 110 is continuous, that is, the light-emitting layer of the light-emitting element of the first sub-pixel and the light-emitting layer of the light-emitting element of the second sub-pixel can be made of one of the high-definition metal mask (FMM) plates. Hole making can effectively reduce the process difficulty of FMM.
  • FMM high-definition metal mask
  • the light-emitting layer of the light-emitting element of the first sub-pixel 5021 and the light-emitting layer of the light-emitting element of the second sub-pixel 5022 are integrated, that is, the light-emitting layer of the light-emitting element of the first sub-pixel 5021 and the light-emitting element of the second sub-pixel 5022
  • the light-emitting layer is integrated.
  • the part where the integrated light-emitting layer overlaps the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel 5021 can be expressed as the light-emitting element of the first sub-pixel 5021
  • the light-emitting layer, the part where the integrated light-emitting layer overlaps the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel 5022 may be referred to as the light-emitting layer of the light-emitting element of the second sub-pixel 5022.
  • the display panel 500 further includes a pixel defining layer (not shown).
  • the first light-emitting voltage application electrode of the light-emitting element of each sub-pixel is located on a side away from the base substrate 110 and includes a first opening that exposes the first At least a part of the first light-emitting voltage applying electrode of the light-emitting element of the sub-pixel 5021 and the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel 5022, the light-emitting layer of the light-emitting element of the first sub-pixel 5021 and the second sub-pixel 5022 At least part of the light-emitting layer of the light-emitting element is located in the first opening and covers the exposed portion of the first light-emitting voltage applying electrode of the first sub-pixel 5021 and the exposed portion of the first light-emitting voltage applying electrode of the second sub-pixel 5022 Part, the area where the first opening and the first light-emitting voltage applying electrode of the first sub-pixel 5021
  • the pixel defining layer further includes a second opening that exposes a part of the first light-emitting voltage application electrode of the light-emitting element of the third sub-pixel 5023, and at least part of the light-emitting layer of the light-emitting element of the third sub-pixel 5023 is located in the second
  • the exposed portion of the first light-emitting voltage application electrode of the third sub-pixel 5023 is covered in the opening, and the part of the area where the second opening overlaps the first light-emitting voltage application electrode of the third sub-pixel 5023 is the area of the third sub-pixel 5023. Effective light-emitting area.
  • the pixel defining layer further includes a third opening that exposes a part of the first light-emitting voltage applying electrode of the light-emitting element of the fourth sub-pixel 5024, and at least part of the light-emitting layer of the light-emitting element of the fourth sub-pixel 5024 is located in the third opening And cover the exposed part of the first light-emitting voltage applying electrode of the fourth sub-pixel 5024, and the part of the area where the third opening overlaps the first light-emitting voltage applying electrode of the fourth sub-pixel 5024 is the effective light emission of the fourth sub-pixel 5024. Area.
  • the second light-emitting voltage application electrodes of the light-emitting elements of all sub-pixels on the display panel are integrated, that is, the entire second light-emitting voltage application electrode covers the entire base substrate 110, that is,
  • the second light-emitting voltage application electrode may be a planar electrode.
  • the portion where the planar second light-emitting voltage application electrode overlaps the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel 5021 can be denoted as the first sub-pixel 5021
  • the second light-emitting voltage applying electrode of the light-emitting element of the pixel 5021, and the area where the planar second light-emitting voltage applying electrode overlaps the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel 5022 can be denoted as the second sub-pixel 5022
  • the second light-emitting voltage application electrode of the light-emitting element That is, the second light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel 5021 and the second light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel 5022 are integrally provided.
  • the first sub-pixel 5021 and the second sub-pixel 5022 are arranged along the first direction X
  • the third sub-pixel 5023 and the fourth sub-pixel 5024 are arranged along the second direction Y.
  • the first direction X and the second direction Y are two directions perpendicular to each other in the same plane (for example, a plane parallel to the surface of the base substrate 501).
  • the line connecting the center of the first sub-pixel 5021 and the center of the second sub-pixel 5022 is the first center line
  • the center of the third sub-pixel 5023 and the center of the fourth sub-pixel 5024 are The connection is the second center line.
  • the length of the first centerline is shorter than the length of the second centerline.
  • the first center line and the second center line are perpendicular to each other and bisect, and the first center line is parallel to the first direction X, and the second center line is parallel to the second direction Y.
  • a plurality of repeating units 502 are arranged along the second direction Y to form a plurality of repeating unit groups
  • FIG. 9 shows two repeating unit groups, and the two repeating unit groups are respectively the Pth repeating unit.
  • the unit group and the P+1th repeating unit group, the Pth repeating unit group and the P+1th repeating unit group are two adjacent repeating unit groups, for example, P is a positive integer greater than or equal to 1.
  • the multiple repeating unit groups are arranged along the first direction X. That is, the multiple repeating units 502 are arranged in an array along the first direction X and the second direction Y.
  • the extension line of the connecting line between the center of the first sub-pixel and the second sub-pixel of the repeating unit in the P-th repeating unit group and the first sub-pixel and the first sub-pixel and the second sub-pixel of the repeating unit in the P+1th repeating unit group does not overlap.
  • the extension line of the line connecting the center of the first sub-pixel and the second sub-pixel of the repeating unit in the P-th repeating unit group passes through the gap between two adjacent repeating units in the P+1-th repeating unit group.
  • the center of the interval similarly, the extension line of the line connecting the center of the first sub-pixel and the second sub-pixel of the repeating unit in the P+1th repeating unit group passes through two adjacent ones in the Pth repeating unit group The center of the interval between repeating units.
  • FIG. 13 is a schematic diagram of a repeating unit on a display panel provided by some embodiments of the present disclosure.
  • the first light-emitting voltage application electrode of the first light-emitting element of the first sub-pixel 5021 includes a first drive electrode block De1 and a first connection electrode block Ce1, and a first drive electrode block De1 and a first connection The electrode block Ce1 is electrically connected.
  • the first connecting electrode block Ce1 is located on the side of the first driving electrode block De1 away from the second light-emitting element of the second sub-pixel 5022.
  • the first connecting electrode block Ce1 is used to connect the first driving electrode block De1 and the first pixel circuit of the first sub-pixel 5021.
  • the first connecting electrode block Ce1 and the first driving electrode block De1 are integrally provided. It should be noted that in other examples, the first connecting electrode block Ce1 and the first driving electrode block De1 can also be separately provided, as long as the first connecting electrode block Ce1 and the first driving electrode block De1 can be electrically connected to each other. .
  • the first light-emitting voltage application electrode of the second light-emitting element of the second sub-pixel 5022 includes a second drive electrode block De2 and a second connection electrode block Ce2, and a second drive electrode block De2 and a second connection
  • the electrode block Ce2 is electrically connected.
  • the second connecting electrode block Ce2 is located on the side of the second driving electrode block De2 away from the first light-emitting element of the first sub-pixel 5021.
  • the second connecting electrode block Ce2 is used to connect the second driving electrode block De2 and the second pixel circuit of the second sub-pixel 5022.
  • the second connecting electrode block Ce2 and the second driving electrode block De2 are integrally provided. It should be noted that in other examples, the second connecting electrode block Ce2 and the second driving electrode block De2 can also be separately provided, as long as the second connecting electrode block Ce2 and the second driving electrode block De2 can be electrically connected to each other. .
  • the first drive electrode block De1 is located between the first connection electrode block Ce1 and the second drive electrode block De2, and the second drive electrode block De2 is located between the second connection electrode block Ce2 and the first drive electrode. Between blocks De1.
  • the line between the center of the first driving electrode block De1 and the center of the second driving electrode block De2 is parallel to the first direction X.
  • the shape of the first drive electrode block De1 and the shape of the second drive electrode block De2 may be the same, and the area of the orthographic projection of the first drive electrode block De1 on the base substrate 110 is the same as that of the second drive electrode block De2 on the base substrate.
  • the area of the orthographic projection on 110 is the same.
  • the shape of the first connection electrode block Ce1 and the shape of the second connection electrode block Ce2 may also be the same.
  • the orthographic projection area of the first connection electrode block Ce1 on the base substrate 110 is the same as that of the second connection electrode block Ce2 on the base substrate 110.
  • the area of the orthographic projection is the same.
  • the shape of the first driving electrode block De1 and the shape of the second driving electrode block De2 may both be rectangular, pentagonal, or rhombus.
  • the shape of the first connection electrode block Ce1 and the shape of the second connection electrode block Ce2 may be regular shapes, for example, a rectangle, a rhombus, etc.; the shape of the first connection electrode block Ce1 and the shape of the second connection electrode block Ce2 may also be different. Regular shape.
  • the shape of the first driving electrode block De1 and the shape of the second driving electrode block De2 may also be rectangular or rhombic.
  • the shape of the first driving electrode block De1 and the shape of the second driving electrode block De2 may also be different, which is not limited in the present disclosure.
  • the width of the first connection electrode block Ce1 is smaller than the maximum width of the first drive electrode block De1
  • the width of the second connection electrode block Ce2 is smaller than the maximum width of the second drive electrode block De2.
  • the first light-emitting voltage application electrode of the third light-emitting element of the third sub-pixel 5023 includes a third drive electrode block De3 and a third connection electrode block Ce3, and a third drive electrode block De3 and a third connection
  • the electrode block Ce3 is electrically connected.
  • the third connection electrode Ce3 is located on the side of the third driving electrode block De3 away from the second connection electrode block Ce2 of the second sub-pixel 5022, in the second direction Y
  • the third connection electrode Ce3 is located on the side of the third drive electrode block De3 close to the fourth drive electrode block De4, that is, in the example shown in FIG.
  • the third connection electrode block Ce3 is located on the third drive electrode block De4.
  • the lower left side of the block De3, that is, the shape of the first light-emitting voltage application electrode of the third light-emitting element of the third sub-pixel 5023 may be similar to a Q-shape.
  • the third connecting electrode block Ce3 is used to connect the third driving electrode block De3 and the third pixel circuit of the third sub-pixel 5023.
  • the third driving electrode block De3 and the third connecting electrode block Ce3 are integrally provided. It should be noted that in other examples, the third driving electrode block De3 and the third connecting electrode block Ce3 can also be separately provided, as long as the third driving electrode block De3 and the third connecting electrode block Ce3 can be electrically connected to each other. .
  • the first light-emitting voltage application electrode of the fourth light-emitting element of the fourth sub-pixel 5024 includes a fourth drive electrode block De4 and a fourth connection electrode block Ce4, and a fourth drive electrode block De4 and a fourth connection
  • the electrode block Ce4 is electrically connected.
  • the fourth connection electrode Ce4 in each repeating unit 502, in the first direction X, is located on the fourth driving electrode block De4 away from the second connection electrode block Ce2 of the second sub-pixel 5022.
  • the fourth connection electrode Ce4 is located on the side of the fourth drive electrode block De4 close to the third drive electrode block De3, that is, in the example shown in FIG.
  • the fourth connection The electrode block Ce4 is located on the lower right side of the fourth driving electrode block De4, that is, the shape of the first light-emitting voltage application electrode of the fourth light-emitting element of the fourth sub-pixel 5024 may be similar to the Q-shaped mirror-symmetric shape.
  • the fourth connecting electrode block Ce4 is used to connect the fourth driving electrode block De4 and the fourth pixel circuit of the fourth sub-pixel 5024.
  • the fourth connecting electrode block Ce4 and the fourth driving electrode block De4 are integrally provided. It should be noted that in other examples, the fourth connecting electrode block Ce4 and the fourth driving electrode block De4 may also be separately provided, as long as the fourth connecting electrode block Ce4 and the fourth driving electrode block De4 can be electrically connected to each other. .
  • the line between the center of the third driving electrode block De3 and the center of the fourth driving electrode block De4 is parallel to the second direction Y.
  • the shape of the third drive electrode block De3 and the shape of the fourth drive electrode block De4 may be the same, and the orthographic projection area of the third drive electrode block De3 on the base substrate 110 and the fourth drive electrode block De4 on the substrate The area of the orthographic projection on the substrate 110 is different.
  • the shape of the third driving electrode block De3 and the shape of the fourth driving electrode block De4 are both rectangular, hexagonal, or oblong.
  • the area of the third driving electrode block De3 is smaller than the area of the fourth driving electrode block De4.
  • the shape and area of the third connection electrode block Ce3 and the shape and area of the fourth connection electrode block Ce4 may be different.
  • the shape of the third connection electrode block Ce3 and the shape of the fourth connection electrode block Ce4 may be regular shapes, such as rectangles, diamonds, etc.; the shape of the third connection electrode block Ce3 and the shape of the fourth connection electrode block Ce4 may also be It is an irregular shape.
  • the shape of the third connection electrode block Ce3 and the shape of the fourth connection electrode block Ce4 are irregular hexagons.
  • the first connection electrode block Ce1, the second connection electrode block Ce2, the third connection electrode block Ce3, and the fourth connection electrode block Ce4 are located between two adjacent repeating unit groups.
  • the first connecting electrode block Ce1, the third connecting electrode block Ce3, and the fourth connecting electrode block Ce4 are located in the P+1th repeating unit group.
  • the second connecting electrode block Ce2 is located between the Pth repeating unit group and the P+1th repeating unit group.
  • the orthographic projection of the first driving electrode block De1 on the base substrate 501 and the orthographic projection of the gate of the driving transistor of the first pixel circuit on the base substrate 501 at least partially overlap.
  • the orthographic projection of the second driving electrode block De2 on the base substrate 501 and the orthographic projection of the gate of the driving transistor of the second pixel circuit on the base substrate 501 do not overlap at all.
  • the orthographic projection of the third driving electrode block De3 on the base substrate 501 and the orthographic projection of the gate of the driving transistor of the third pixel circuit on the base substrate 501 at least partially overlap.
  • the orthographic projection of the fourth driving electrode block De4 on the base substrate 501 and the orthographic projection of the gate of the driving transistor of the fourth pixel circuit on the base substrate 501 at least partially overlap.
  • the pixel circuit of each sub-pixel is located between the intermediate layer and the base substrate 501, and the light-emitting element of each sub-pixel is located on the side of the intermediate layer away from the base substrate 501 That is, the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are all located between the intermediate layer and the base substrate 501, and the first light emitting element, the second light emitting element, and the third light emitting element Both the fourth light-emitting element and the fourth light-emitting element are located on the side of the intermediate layer away from the base substrate 501.
  • the intermediate layer can be a flat insulating layer.
  • the first light-emitting voltage application electrode of the first light-emitting element of the first sub-pixel 5021 is disposed on the light-emitting layer of the first light-emitting element of the first sub-pixel 5021 near the middle layer.
  • the second light-emitting voltage application electrode of the first light-emitting element of the first sub-pixel 5021 is provided on the side of the light-emitting layer of the first light-emitting element of the first sub-pixel 5021 away from the intermediate layer.
  • the layer structure of the second light-emitting element in the second sub-pixel 5022, the third light-emitting element in the third sub-pixel 5023, and the fourth light-emitting element in the fourth sub-pixel 5024 is similar to that of the first light-emitting element, and will not be repeated here. .
  • the intermediate layer includes a first via h1, a second via h2, a third via h3, a fourth via h4, and the like.
  • each pixel circuit may include an active semiconductor layer, a gate metal layer, and a source and drain metal layer.
  • the active semiconductor layer is located between the base substrate 501 and the gate metal layer.
  • the gate metal layer is located between the active semiconductor layer and the source and drain metal layers.
  • the respective transistors in the pixel circuit of each sub-pixel (for example, the driving transistor M1, the light emission control transistor M2, the data writing transistor M3, the threshold compensation transistor M4, the reference voltage writing transistor M5, the first reset The active layer of the transistor M6, the second reset transistor M7, etc.) is located in the active semiconductor layer, the gate of each transistor in the pixel circuit of each sub-pixel is located in the gate metal layer, and the gate of each transistor in the pixel circuit
  • the source and drain are both located in the source and drain metal layer.
  • Each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the active layer of each transistor is integrated.
  • the first connection electrode block Ce1 extends to the first via hole h1 and is electrically connected to the first pixel circuit of the first sub-pixel 5021 through the first via hole h1.
  • the first connection electrode block Ce1 passes through the first via hole.
  • h1 is electrically connected to the second electrode of the light-emitting control transistor of the first pixel circuit of the first sub-pixel 5021.
  • the first connection electrode block Ce1 extends to the source and drain metal layer through the first via hole h1 to be electrically connected to the second electrode of the light emission control transistor of the first pixel circuit located in the source and drain metal layer.
  • the second connecting electrode block Ce2 extends to the second via hole h2 and is electrically connected to the second pixel circuit of the second sub-pixel 5022 through the second via hole h2.
  • the second connecting electrode block Ce2 passes through the second via hole.
  • h2 is electrically connected to the second pole of the light emission control transistor of the second pixel circuit of the second sub-pixel 5022.
  • the second connecting electrode block Ce2 extends to the source and drain metal layer through the second via hole h2 to be electrically connected to the second electrode of the light-emitting control transistor of the second pixel circuit located in the source and drain metal layer.
  • the third connecting electrode block Ce3 extends to the third via hole h3 and is electrically connected to the third pixel circuit of the third sub-pixel 5023 through the third via hole h3.
  • the third connection electrode block Ce3 is electrically connected to the second electrode of the light emission control transistor of the third pixel circuit of the third sub-pixel 5023 through the third via hole h3.
  • the third connection electrode block Ce3 extends to the source and drain metal layer through the third via hole h3 to be electrically connected to the second electrode of the light emission control transistor of the third pixel circuit located in the source and drain metal layer.
  • the fourth connection electrode block Ce4 extends to the fourth via hole h4 and is electrically connected to the fourth pixel circuit of the fourth sub-pixel 5024 through the fourth via hole h4.
  • the fourth connection electrode block Ce4 is electrically connected to the second electrode of the light emission control transistor of the fourth pixel circuit of the fourth sub-pixel 5024 through the fourth via hole h4.
  • the fourth connection electrode block Ce4 extends to the source and drain metal layer through the fourth via hole h4 to be electrically connected to the second electrode of the light emission control transistor of the fourth pixel circuit located in the source and drain metal layer.
  • connection electrode block of each sub-pixel may cover and fill the corresponding via hole.
  • first connection electrode block Ce1 covers and fills the first via hole h1
  • second connection electrode block Ce2 covers and fills the second via hole.
  • Hole h2 covers and fills the third via hole h3
  • the fourth connection electrode block Ce4 covers and fills the fourth via hole h4.
  • FIG. 13 Each via hole of is located above the corresponding connecting electrode block.
  • the gate of the drive transistor of the pixel circuit of the first sub-pixel 5021 ie, the first pixel circuit
  • the gate of the drive transistor of the pixel circuit of the second sub-pixel 5022 are along the first direction X Arrangement.
  • the second driving electrode block De2 is located on the side of the gate of the driving transistor of the pixel circuit of the second sub-pixel close to the gate of the driving transistor of the pixel circuit of the first sub-pixel.
  • the second driving electrode block De2 is located between the gate of the driving transistor of the pixel circuit of the first sub-pixel and the gate of the driving transistor of the pixel circuit of the second sub-pixel.
  • the second connecting electrode block Ce2 is located on the side of the second driving electrode block De2 away from the gate of the driving transistor of the pixel circuit of the first sub-pixel 5021.
  • the second connection electrode block Ce2 is located between the gate of the driving transistor of the pixel circuit of the first sub-pixel and the gate of the driving transistor of the pixel circuit of the second sub-pixel.
  • the first connection electrode block Ce1 is located on the side of the gate of the driving transistor of the pixel circuit of the first sub-pixel 5021 away from the gate of the driving transistor of the pixel circuit of the second sub-pixel 5022.
  • the distance between the center of the gate of the driving transistor of the pixel circuit of the first sub-pixel 5021 and the center of the first driving electrode block De1 is smaller than the center of the gate of the driving transistor of the pixel circuit of the second sub-pixel 5022 and the first The distance between the centers of the two driving electrode blocks De2.
  • center may refer to the geometric center of the physical shape of the element.
  • elements such as the gate of the driving transistor and the anode of the light-emitting element are generally designed in regular shapes, such as rectangles, hexagons, pentagons, trapezoids or other shapes.
  • the center of the element for example, the gate of the driving transistor or the anode of the light-emitting element, etc.
  • the shapes of the gates of the driving transistors and the anodes of the light-emitting elements formed will generally deviate from the regular shapes designed above.
  • the corners of the aforementioned regular shape may become rounded corners. Therefore, the shape of the gate of the driving transistor and the anode of the light-emitting element may be rounded corners.
  • the shapes of the gates of the drive transistors and the anodes of the light-emitting elements that are actually manufactured may have other changes from the designed shapes. For example, the shape of a sub-pixel designed as a hexagon may become approximately elliptical in actual manufacturing. Therefore, the center of elements such as the gate of the driving transistor and the anode of the light-emitting element may not be the exact geometric center of the irregular shape of the formed element.
  • the center of the element may have a certain offset from the geometric center of the shape of the element.
  • the "center" may also indicate the center of gravity of the element.
  • the reference power terminal REF is connected to the reference power line
  • the first reset power terminal VINT is connected to the first reset power line.
  • the gate line G1 and the threshold compensation control line G2 may be the same signal line
  • the first reset control signal line Rst1 and the second reset control signal line Rst2 may be the same signal line
  • the voltage control line CR can be the same signal line.
  • the gate line G1, the threshold compensation control line G2, the reference voltage control line CR, the first reset control signal line Rst1, the second reset control signal line Rst2, the light emission control line EM, the reference power line, the first A reset power line is arranged along the first direction X and all extend along the second direction Y.
  • the gate line G1, the threshold compensation control line G2, the reference voltage control line CR, the first reset control signal line Rst1, the second reset control signal line Rst2, the light emission control line EM, the reference power line, and the first reset power line are approximately parallel .
  • the first power terminal VDD is connected to the first power line, and the first power line and the data line D are substantially parallel to each other.
  • the first power line and the data line D are arranged along the second direction Y, and both extend along the first direction X.
  • each signal line (for example, the first gate signal line, the second gate signal line, the reference control signal line, the light emission control signal line, the first reset signal line , The second reset signal line, the initialization signal line, and the reference voltage signal line) are generally routed directions, each signal line may not be a straight line microscopically, but extend in the second direction Y in a wave shape.
  • FIG. 14 is a plan partial schematic diagram of another display panel provided by some embodiments of the present disclosure.
  • 201 to 206 may be areas where the pixel circuits of each sub-pixel on the base substrate 110 are located.
  • the first pixel circuit of the first sub-pixel 5021 is located in the area 202
  • the second pixel circuit of the second sub-pixel 5022 is located in the area 205.
  • the third pixel circuit of the third sub-pixel 5023 is located in the area 201
  • the fourth pixel circuit of the fourth sub-pixel 5024 is located in the area 203.
  • the active semiconductor layer 28 is disposed on the base substrate 501, and the shape of the active semiconductor 28 in the region where the pixel circuit of each sub-pixel is located is the same. That is, for example, the shape of the first portion of the active semiconductor 28 in the region 202 and the shape of the second portion of the active semiconductor 28 in the region 205 are the same.
  • the signal line 25 and the signal line 26 electrically connected to the first pixel circuit located in the area 202 extend in the second direction Y, and in the direction perpendicular to the base substrate 501, the signal line The signal line 25 and the signal line 26 at least partially overlap the first pixel circuit in the area 202.
  • the signal line 24 and the signal line 27 that are electrically connected to the second pixel circuit located in the area 205 extend along the second direction Y, and in the direction perpendicular to the base substrate 501, the signal line 24 and the signal line 27 and the area 205
  • the second pixel circuits in at least partially overlap.
  • the signal line 24, the signal line 25, the signal line 26, and the signal line 27 are substantially parallel to each other.
  • the signal line 24, the signal line 25, the signal line 26, and the signal line 27 are arranged along the first direction X.
  • the gate line G1 and the compensation control line G2 electrically connected to the first pixel circuit are the same signal line 25, and the reference voltage control line CR electrically connected to the first pixel circuit It is the same signal line 26 as the emission control line EM, that is, the signal line 25 shown in FIG. 14 serves as a gate line G1 electrically connected to the first pixel circuit, and is also multiplexed as a compensation control line electrically connected to the first pixel circuit G2, the signal line 26 shown in FIG. 14 serves not only as a reference voltage control line CR electrically connected to the first pixel circuit, but also multiplexed as an emission control line EM electrically connected to the first pixel circuit.
  • the gate line G1 and the compensation control line G2 electrically connected to the second pixel circuit are the same signal line 24, and the reference voltage control line CR and the light emission control line EM electrically connected to the second pixel circuit are the same signal line 27. That is, the signal line 24 shown in FIG. 14 serves as the gate line G1 electrically connected to the second pixel circuit and is also multiplexed as the compensation control line G2 electrically connected to the second pixel circuit.
  • the signal line 27 shown in FIG. 14 serves as both The reference voltage control line CR electrically connected to the second pixel circuit is multiplexed as a light emitting control line EM electrically connected to the second pixel circuit.
  • the first pixel circuit includes a first capacitor C1.
  • the first electrode 321 of the first capacitor C1 is located between the signal line 25 and the signal line 26.
  • the orthographic projection of the first electrode 321 of the first capacitor C1 on the base substrate 501 and the orthographic projection of the first light-emitting voltage application electrode 301 on the base substrate 501 at least partially overlap, for example, the first electrode of the first capacitor C1
  • the orthographic projection of 321 on the base substrate 501 is located within the orthographic projection of the first light-emitting voltage application electrode 301 on the base substrate 501. For example, as shown in FIGS.
  • the first pixel circuit further includes a driving transistor M1, a light emission control transistor M2, a data writing transistor M3, and a threshold compensation transistor M4, and the second electrode (eg, drain) of the driving transistor M1
  • a driving transistor M1 a light emission control transistor M2, a data writing transistor M3, and a threshold compensation transistor M4, and the second electrode (eg, drain) of the driving transistor M1
  • the orthographic projections on the base substrate 501 at least partially overlap each other.
  • the areas shown by the rectangular dashed circles respectively indicate the area corresponding to the gate of the driving transistor M1, the area corresponding to the gate of the light emission control transistor M2, and the data writing transistor M3 on the base substrate 501.
  • the region corresponding to the gate of the threshold compensation transistor M4 corresponds to the region.
  • the orthographic projection of the gate of the driving transistor M1 on the base substrate 501 and the anode of the light-emitting element of the first sub-pixel 5021 are on the base substrate 501.
  • the orthographic projection on the substrate at least partially overlaps, the orthographic projection of the gate of the emission control transistor M2 on the substrate 501 and the orthographic projection of the signal line 26 on the substrate 501 at least partially overlap, and the gate of the threshold compensation transistor M4 is on the substrate.
  • the orthographic projection on the base substrate 501 and the orthographic projection of the signal line 25 on the base substrate 501 at least partially overlap.
  • the portion of the signal line 26 that overlaps the active semiconductor layer 28 includes the emission control transistor M2
  • the gate of the signal line 25 that overlaps the active semiconductor layer 28 includes the gate of the threshold compensation transistor M4.
  • the gate (electrode block 29 shown in FIG. 14) of the driving transistor M1 is located on the same layer as the signal line 25 and the signal line 26.
  • the first capacitor C1 The orthographic projection of the first electrode 321 on the base substrate 501 is located between the orthographic projection of the gate of the threshold compensation transistor M4 on the base substrate 501 and the orthographic projection of the gate of the light emission control transistor M2 on the base substrate 501.
  • the orthographic projection of the first electrode 321 of the first capacitor C1 on the base substrate 501 and the active layer of the threshold compensation transistor M4 and the active layer of the light emission control transistor M2 are active.
  • the orthographic projection of the semiconductor layer 28 on the base substrate 501 at least partially overlaps.
  • the second pole of the driving transistor M1, the first pole of the light emission control transistor M2, and the first pole of the threshold compensation transistor M4 may be integrated.
  • the orthographic projection of the first electrode 321 of the first capacitor C1 on the base substrate 501 and the orthographic projection of the second electrode of the driving transistor M1 on the base substrate 501 at least partially overlap.
  • the orthographic projection of the second electrode of the driving transistor M1 on the base substrate 501 is within the orthographic projection of the first electrode 321 of the first capacitor C1 on the base substrate 501.
  • the shape of the first electrode 321 of the first capacitor C1 may be a rectangle, and the long side of the rectangle may be substantially parallel to the first direction X, for example.
  • the first electrode 321 of the first capacitor C1, the second electrode of the driving transistor M1, the first electrode of the light emission control transistor M2, and the first electrode of the threshold compensation transistor M4 are all electrically connected.
  • the metal layer used to form the first electrode 321 of the first capacitor C1 is directly formed on the second electrode of the driving transistor M1, so as to electrically connect the first electrode 321 of the first capacitor C1 to the driving transistor.
  • the second pole of M1 is electrically connected.
  • the data writing sub-circuit of the pixel circuit of the first sub-pixel 5021, the data writing sub-circuit of the pixel circuit of the third sub-pixel 5023, and the data writing of the pixel circuit of the fourth sub-pixel 5024 are electrically connected to, for example, the gate line of the Nth row to receive the scan signal, and the pixel circuit of the second sub-pixel 5022 is electrically connected to the gate line of the N-1th row to receive the scan signal.
  • the gate line in the N-1th row is the upper gate line adjacent to the gate line in the Nth row.
  • N is a positive integer greater than 1. For example, as shown in FIG.
  • the signal line 24 can represent the N-1th row of gate lines
  • the signal line 25 can represent the Nth row of gate lines.
  • the N-1th row of gate lines ie, the signal line 24
  • the orthographic projection of the gate line of the Nth row ie the signal line 25
  • the orthographic projection of the gate line (ie the signal line 24) of the N-1th row on the base substrate 501 and the area 204, the area 205, and the area 206 at least partially overlap.
  • the signal line 26 may represent the reference voltage control line/lighting control line of the Nth row
  • the signal line 27 may represent the reference voltage control line/lighting control line of the N-1th row
  • the reference voltage control line/lighting control line of the Nth row (Ie the signal line 26) the orthographic projection on the base substrate 501 and the area 201, the area 202, and the area 203 at least partially overlap, the reference voltage control line/light emitting control line (ie the signal line 27) in the N-1th row
  • the orthographic projection on the base substrate 501 at least partially overlaps the area 204, the area 205, and the area 206.
  • the display panel 500 may be an organic light emitting diode (OLED) display panel or the like.
  • OLED organic light emitting diode
  • the display panel 500 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 500 may not only be a flat panel, but also a curved panel or even a spherical panel.
  • the display panel 500 may also have a touch function, that is, the display panel 500 may be a touch display panel.
  • the display panel 500 can be applied to any products or components with display functions such as mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.

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Abstract

一种像素电路及其驱动方法、显示基板和显示面板。像素电路包括驱动子电路、发光控制子电路、数据写入子电路、存储子电路和第一补偿子电路。数据写入子电路被配置为在扫描信号的控制下将数据电压写入存储子电路；存储子电路被配置为存储数据电压；驱动子电路电连接至第一节点，发光元件电连接至第二节点，驱动子电路被配置为基于数据电压驱动发光元件发光；发光控制子电路分别电连接至第一节点和第二节点，发光控制子电路被配置为实现驱动子电路和发光元件之间的连接导通或断开；第一补偿子电路分别电连接至第一节点和第二节点，且被配置为基于第一节点的电平对第二节点的电平进行补偿。

Description

像素电路及其驱动方法、显示基板和显示面板
本申请要求于2019年07月31日递交的中国专利申请第201910702440.4号的优先权，在此出于所有目标全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示基板和显示面板。
背景技术
随着有源矩阵有机发光二极管(Active-matrix organic light-emitting diode，AMOLED)在显示领域的迅猛发展，人们对显示效果的要求越来越高。由于具有显示质量高等优点，高分辨率显示装置的应用范围也越来越广。通常，可通过减小像素的尺寸和减小像素间的间距来提高显示装置的分辨率。
发明内容
本公开至少一实施例提供一种像素电路，包括：驱动子电路、发光控制子电路、数据写入子电路、存储子电路和第一补偿子电路，其中，所述数据写入子电路被配置为在扫描信号的控制下将数据电压写入所述存储子电路；所述存储子电路被配置为存储所述数据电压；所述驱动子电路电连接至第一节点，发光元件电连接至第二节点，所述驱动子电路被配置为基于所述数据电压驱动所述发光元件发光；所述发光控制子电路分别电连接至所述第一节点和所述第二节点，所述发光控制子电路被配置为实现所述驱动子电路和所述发光元件之间的连接导通或断开；所述第一补偿子电路分别电连接至所述第一节点和所述第二节点，且被配置为基于所述第一节点的电平对所述第二节点的电平进行补偿。
例如，在本公开至少一实施例提供的像素电路中，所述第一补偿子电路包括第一电容，所述第一电容的第一端电连接至所述第一节点，所述第一电容的第二端电连接至所述第二节点。
例如，在本公开至少一实施例提供的像素电路中，所述发光控制子电路包括发光控制晶体管，所述发光控制晶体管的第一极与所述第一节点电连接，所述发光控制晶体管的第二极与所述第二节点电连接，所述发光控制晶体管的栅极被配置为接收发光控制信号。
例如，在本公开至少一实施例提供的像素电路中，所述驱动子电路包括驱动晶体管，所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述第一节点电连接，所述驱动晶体管的栅极与第三节点电连接。
例如，在本公开至少一实施例提供的像素电路中，所述数据写入子电路包括数据写入晶体管，所述存储子电路包括第二电容，所述数据写入晶体管的第一极被配置为接收所述数据电压，所述数据写入晶体管的第二极与所述第二电容的第一端电连接，所述数据写入晶体管的栅极被配置为接收所述扫描信号，所述第二电容的第二端与所述第三节点电连接。
例如，本公开至少一实施例提供的像素电路还包括第二补偿子电路，所述第二补偿子电路被配置为接收阈值补偿控制信号并根据所述阈值补偿控制信号向所述第三节点写入阈值补偿电压。
例如，本公开至少一实施例提供的像素电路还包括参考电压写入子电路，所述参考电压写入子电路被配置为接收参考电压控制信号并根据所述参考电压控制信号向所述第二电容的第一端写入参考电压。
例如，本公开至少一实施例提供的像素电路还包括第一复位子电路，所述第一复位子电路被配置为接收第一复位控制信号并根据所述第一复位控制信号向所述第三节点写入第一复位电压。
例如，本公开至少一实施例提供的像素电路还包括第二复位子电路，所述第二复位子电路被配置为接收第二复位控制信号并根据所述第二复位控制信号向所述第二电容的第一端写入第二复位电压。
例如，本公开至少一实施例提供的像素电路还包括第二补偿子电路、参考电压写入子电路、第一复位子电路和第二复位子电路，所述第一补偿子电路包括第一电容，所述发光控制子电路包括发光控制晶体管，所述驱动子电路包括驱动晶体管，所述数据写入子电路包括数据写入晶体管，所述存储子电路包括第二电容，所述第二补偿子电路包括阈值补偿晶体管，所述参考电压写入子电路包括参考电压写入晶体管，所述第一复位子电路包括第一复位晶体管，所述第二复位子电路包括第二复位晶体管，所述第一电容的第一端电连接至所述第一节点，所述第一电容的第二端电连接至所述第二节点，所述发光控制晶体管的第一极与所述第一节点电连接，所述发光控制晶体管的第二极与所述第二节点电连接，所述发光控制晶体管的栅极被配置为接收发光控制信号；所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述第一节点电连接，所述驱动晶体管的栅极与第三节点电连接；所述发光元件的第一发光电压施加电极电连接至所述第二节点，所述发光元件的第二发光电压施加电极电连接至第二电源端；所述数据写入晶体管的第一极被配置为接收所述数据电压，所述数据写入晶体管的第二极与所述第二电容的第一端电连接，所述数据写入晶体管的栅极被配置为接收所述扫描信号；所述第二电容的第二端与所述第三节点电连接；所述阈值补偿晶体管的第一极电连接至所述第一节点，所述阈值补偿晶体管的第二极电连接至所述第三节点，所述阈值补偿晶体管的栅 极被配置为接收阈值补偿控制信号；所述参考电压写入晶体管的第一极被配置为接收参考电压，所述参考电压写入晶体管的第二极电连接至所述第二电容的第一端，所述参考电压写入晶体管的栅极被配置为接收参考电压控制信号；所述第一复位晶体管的第一极被配置为接收第一复位电压，所述第一复位晶体管的第二极电连接至所述第三节点，所述第一复位晶体管的栅极被配置为接收第一复位控制信号；所述第二复位晶体管的第一极电连接至所述第一电源端，所述第二复位晶体管的第二极电连接至所述第二电容的第一端，所述第二复位晶体管的栅极被配置为接收第二复位控制信号。
本公开至少一实施例还提供一种显示基板，包括衬底基板和根据上述任一项所述的像素电路和所述发光元件，所述发光元件和所述像素电路设置在所述衬底基板上。
例如，在本公开至少一实施例提供的显示基板中，在所述第一补偿子电路包括第一电容的情况下，所述第一电容包括第一电极和第二电极，所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，所述第一电容的第一电极电连接至所述第一节点，所述第一电容的第二电极电连接至所述第二节点，所述第一电容的第二电极和所述第一发光电压施加电极一体设置，在垂直于所述衬底基板的方向上，所述第一电容的第一电极位于所述第一发光电压施加电极和所述衬底基板之间，所述第一发光电压施加电极位于所述第一电容的第一电极和所述发光层之间。
例如，在本公开至少一实施例提供的显示基板中，所述第一电容的第一电极在所述衬底基板上的正投影与所述第一发光电压施加电极在所述衬底基板上的正投影至少部分重叠。
本公开至少一实施例还提供一种根据上述任一项所述的像素电路的驱动方法，包括：在数据写入阶段，向所述驱动子电路写入所述数据电压，并且基于所述第一节点的电平对所述第二节点的电平进行补偿；在发光阶段，所述驱动子电路基于所述数据电压驱动所述发光元件发光。
本公开至少一实施例还提供一种显示面板，包括衬底基板和位于所述衬底基板上的多个重复单元，所述多个重复单元中的每个重复单元包括第一子像素和第二子像素，所述第一子像素包括第一发光元件和第一像素电路，所述第一像素电路为根据上述任一项所述的像素电路，所述第一发光元件是由所述第一像素电路驱动的所述发光元件。
例如，在本公开至少一实施例提供的显示面板中，所述第二子像素包括第二发光元件和第二像素电路，所述第二像素电路被配置为驱动所述第二发光元件发光，在垂直于所述衬底基板的方向上，所述第一像素电路中的驱动子电路 位于所述衬底基板和所述第一发光元件之间，所述第二像素电路中的驱动子电路位于所述衬底基板和所述第二发光元件之间，所述第一像素电路中的驱动子电路在所述衬底基板上的正投影和所述第一发光元件在所述衬底基板上的正投影至少部分重叠，所述第二像素电路中的驱动子电路在所述衬底基板上的正投影和所述第二发光元件在所述衬底基板上的正投影不重叠。
例如，在本公开至少一实施例提供的显示面板中，所述第一像素电路中的驱动子电路在所述衬底基板上的正投影位于所述第一发光元件在所述衬底基板上的正投影内。
例如，在本公开至少一实施例提供的显示面板中，所述每个重复单元还包括第三子像素和第四子像素，所述第一子像素和所述第二子像素均为绿色子像素，所述第三子像素为红色子像素，所述第四子像素为蓝色子像素。
例如，在本公开至少一实施例提供的显示面板中，所述每个重复单元还包括第三子像素和第四子像素，在所述每个重复单元中，所述第一子像素和所述第二子像素沿第一方向排列，所述第三子像素和所述第四子像素沿第二方向排列，所述第一方向和所述第二方向分别为在同一平面内相互垂直的两个方向。
例如，在本公开至少一实施例提供的显示面板中，所述多个重复单元沿所述第二方向排列以形成多个重复单元组，所述多个重复单元组沿所述第一方向排列。
例如，在本公开至少一实施例提供的显示面板中，在所述第一像素电路包括第一电容、阈值补偿晶体管和发光控制晶体管的情况下，在所述第一方向上，所述第一电容的第一电极在所述衬底基板上的正投影位于所述阈值补偿晶体管的栅极在衬底基板上的正投影和所述发光控制晶体管的栅极在所述衬底基板上的正投影之间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种像素排列结构中的像素重复单元的结构示意图；
图2为图1所示的像素重复单元中的第一绿色子像素的阳极电压和第二绿色子像素的阳极电压的检测结果示意图；
图3为本公开一些实施例提供的一种像素电路的示意性框图；
图4为本公开一些实施例提供的一种像素电路的结构示意图；
图5为本公开一些实施例提供的一种显示基板的示意性框图；
图6为图4所示的像素电路中的第一节点的截面示意图；
图7为本公开一些实施例提供的一种像素电路的驱动方法的示意性流程图；
图8是图4所示的像素电路的驱动方法的示例性时序图；
图9为本公开一些实施例提供的一种显示面板的局部结构示意图；
图10为本公开一些实施例提供的一种第二像素电路的结构示意图；
图11为图10所示的第二像素电路中的第一节点的截面示意图；
图12为图9所示的重复单元中的第一子像素的阳极电压和第二子像素的阳极电压的检测结果示意图；
图13为本公开一些实施例提供的一种显示面板上的重复单元的示意图；
图14为本公开一些实施例提供的另一种显示面板的平面局部示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
图1为一种像素排列结构中的像素重复单元的结构示意图，图2为图1所示的像素重复单元中的第一绿色子像素的阳极电压和第二绿色子像素的阳极电压的检测结果示意图。如图1所示，一种像素排列结构包括设置在衬底基板(未示出)上的多个像素重复单元400，多个像素重复单元400沿A1方向和A2方向阵列排布。每个像素重复单元400包括红色子像素401、蓝色子像素402、第一绿色子像素403和第二绿色子像素404。如图1所示，红色子像素401和蓝色子像素402沿A1方向排列，第一绿色子像素403和第二绿色子像素404沿A2方向排列，且在A1方向上，第一绿色子像素403和第二绿色子 像素404位于红色子像素401和蓝色子像素402之间。
在对图1所示的像素排列结构中的各个子像素进行点灯检测的过程中，由于第一绿色子像素403和第二绿色子像素404的亮度不一致，从而导致亮点漏检的问题，即部分绿色子像素无法被检测到。根据实验结果可知，第一绿色子像素403的亮度比第二绿色子像素404的亮度高，从而出现第一绿色子像素403发亮，而第二绿色子像素404发暗的现象。
通过对像素排列结构进行分析可知，在该像素排列结构中，用于驱动第一绿色子像素403的像素电路中的驱动晶体管的栅极在衬底基板上的正投影与第一绿色子像素403的发光元件的阳极在衬底基板上的正投影彼此不交叠，而用于驱动第二绿色子像素404的像素电路中的驱动晶体管的栅极在衬底基板上的正投影和第二绿色子像素404的发光元件的阳极在衬底基板上的正投影彼此交叠。通过对第一绿色子像素403和第二绿色子像素404进行提取3D电容的操作，发现第一绿色子像素403的寄生电容和第二绿色子像素404的寄生电容存在较大的差异，从而导致第一绿色子像素403和第二绿色子像素404的亮度差异。如图2所示，通过对第一绿色子像素403和第二绿色子像素404进行模拟分析，可以看到，第一绿色子像素403的阳极电压为0.8682伏特(V)，第二绿色子像素404的阳极电压为0.7597V，即第一绿色子像素403的阳极电压大于第二绿色子像素404的阳极电压，从而导致第一绿色子像素403的亮度比第二绿色子像素404的亮度高，严重影响显示效果。
本公开至少一些实施例提供一种像素电路及其驱动方法、显示基板和显示面板，该像素电路包括驱动子电路、发光控制子电路、数据写入子电路、存储子电路和第一补偿子电路。数据写入子电路被配置为在扫描信号的控制下将数据电压写入存储子电路；存储子电路被配置为存储数据电压；驱动子电路电连接至第一节点，发光元件电连接至第二节点，驱动子电路被配置为驱动发光元件发光；发光控制子电路分别电连接至第一节点和第二节点，发光控制子电路被配置为实现驱动子电路和发光元件之间的连接导通或断开；第一补偿子电路分别电连接至第一节点和第二节点，且被配置为基于第一节点的电平对第二节点的电平进行补偿。
在该像素电路中，通过在第一节点和第二节点之间设置第一补偿子电路，以实现对第二节点的电平进行补偿，解决显示面板的像素亮度差异的问题，使不同像素的像素亮度达到一致，从而提高显示均匀性和显示效果。另外，该像素电路结构简单，易于设计制造，成本较低。
下面结合附图对本公开的几个实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图3为本公开一些实施例提供的一种像素电路的示意性框图，图4为本公 开一些实施例提供的一种像素电路的结构示意图。
例如，如图3所示，本公开实施例提供的像素电路100包括驱动子电路11、发光控制子电路12、数据写入子电路13、存储子电路14和第一补偿子电路15。数据写入子电路13被配置为在扫描信号的控制下将数据电压写入存储子电路14；存储子电路14被配置为存储数据电压；驱动子电路11电连接至第一节点N1，发光元件EL电连接至第二节点N2，驱动子电路11被配置为基于数据电压驱动发光元件EL发光；发光控制子电路12分别电连接至第一节点N1和第二节点N2，发光控制子电路12被配置为实现驱动子电路11和发光元件EL之间的连接导通或断开；第一补偿子电路15分别电连接至第一节点N1和第二节点N2，且被配置为基于第一节点N1的电平对第二节点N2的电平进行补偿。
例如，像素电路100可应用于显示面板，例如有源矩阵有机发光二极管(AMOLED)显示面板等。AMOLED显示面板中的像素排列结构可以为RGBG像素排列结构，以增加显示面板的PPI(pixel per inch，每英寸的像素数)，从而在显示分辨率相同的情况下，增大显示面板的视觉分辨率。当像素电路100应用于该AMOLED显示面板中，可以解决显示面板的像素亮度差异的问题，提高显示均匀性和显示效果。
例如，像素电路100和发光元件EL可以设置在一衬底基板上。
例如，如图4所示，在一些实施例中，第一补偿子电路15包括第一电容C1。第一电容C1的第一端电连接至第一节点N1，第一电容C1的第二端电连接至第二节点N2。也就是说，第一补偿子电路15可以包括在第一节点N1和第二节点N2之间的寄生电容(即第一电容C1为寄生电容)，由于电容的自举效应，该第一补偿子电路15可以基于第一节点N1的电平控制第二节点N2的电平，以补偿由于像素电路的驱动子电路11在衬底基板上的正投影与发光元件EL的阳极在衬底基板上的正投影彼此交叠等因素对于第二节点N2的电平的影响，提高对于第二节点N2的电平控制，从而提高显示均匀性和显示效果。例如，相较于没有设置第一电容的像素电路，本公开实施例提供的像素电路可以利用第一电容C1例如提高第二节点N2的电平，以提高发光元件EL的发光亮度。
例如，第一电容C1的电容值的范围可以为1fF至8fF。
例如，如图4所示，发光控制子电路12可以包括发光控制晶体管M2。发光控制晶体管M2的第一极与第一节点N1电连接，发光控制晶体管M2的第二极与第二节点N2电连接，发光控制晶体管M2的栅极被配置为电连接发光控制线EM以接收发光控制信号VEM。
例如，如图4所示，驱动子电路11包括驱动晶体管M1。驱动晶体管M1的第一极与第一电源端VDD电连接，驱动晶体管M1的第二极与第一节点N1 电连接，驱动晶体管M1的栅极与第三节点N3电连接。也就是说，第一电容C1的第一端与驱动晶体管M1的第二极电连接。
例如，驱动晶体管M1可以为P型晶体管。驱动晶体管M1的第一极可以为源极，驱动晶体管M1的第二极可以为漏极，下面以此为例进行说明。
例如，驱动晶体管M1通过发光控制晶体管M2与发光元件EL电连接。当发光控制晶体管M2导通时，驱动晶体管M1和发光元件EL之间的连接导通；当发光控制晶体管M2断开时，驱动晶体管M1和发光元件EL之间的连接断开。例如，在数据写入阶段，发光控制晶体管M2可以断开，从而发光控制晶体管M2可以将驱动晶体管M1和发光元件EL之间的连接断开，以保证发光元件EL不发光。而在发光阶段，发光控制线EM可以向发光控制晶体管M2提供发光控制信号VEM，以使发光控制晶体管M2导通，发光电流可以依次经由导通的驱动晶体管M1和发光控制晶体管M2被传输至发光元件EL以驱动其发光。
例如，如图4所示，发光元件EL的第一发光电压施加电极(该实施例中为发光元件EL的阳极)电连接至第二节点N2，发光元件EL的第二发光电压施加电极(该实施例中为发光元件EL的阴极)电连接至第二电源端VSS。也就是说，第一电容C1的第二端与发光元件EL的第一发光电压施加电极电连接。
例如，发光元件EL被配置为在工作时接收发光信号(例如，可以为电流信号)，并发出与该发光信号相对应强度的光。发光元件EL可以为发光二极管，发光二极管例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等，但本公开的实施例不限于此。
例如，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图4所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压。例如，在一些示例中，第二电源端VSS也可以接地。
例如，如图4所示，数据写入子电路13包括数据写入晶体管M3。数据写入晶体管M3的第一极被配置为接收数据电压Vdata，数据写入晶体管M3的第二极与第四节点N4电连接，数据写入晶体管M3的栅极被配置接收扫描信号Vg1。例如，在一些实施例中，数据写入晶体管M3的第一极电连接至数据线D，以接收数据电压Vdata；数据写入晶体管M3的栅极电连接至栅线G1，以接收扫描信号Vg1。
例如，如图4所示，存储子电路14包括第二电容C2。第二电容C2的第一端与第四节点N4电连接，也就是说，数据写入晶体管M3的第二极与第二 电容C2的第一端电连接，第二电容C2的第二端与第三节点N3电连接，也就是说，第二电容C2的第二端与驱动晶体管M1的栅极电连接。
例如，第二电容C2的电容值的范围可以为40fF至100fF。
例如，如图4所示，像素电路100还包括可以第二补偿子电路16。第二补偿子电路16被配置为接收阈值补偿控制信号并根据阈值补偿控制信号向第三节点N3，即驱动晶体管M1的栅极，写入阈值补偿电压。
例如，第二补偿子电路16可以包括阈值补偿晶体管M4。阈值补偿晶体管M4的第一极电连接到第一节点N1，即阈值补偿晶体管M4的第一极电连接到驱动晶体管M1的第二极，阈值补偿晶体管M4的第二极电连接到第三节点N3，即阈值补偿晶体管M4的第二极电连接到驱动晶体管M1的栅极，阈值补偿晶体管M4的栅极被配置为接收阈值补偿控制信号Vg2。例如，如图4所示，阈值补偿晶体管M4的栅极电连接至阈值补偿控制线G2，以接收阈值补偿控制信号Vg2。
例如，阈值补偿控制信号Vg2和扫描信号Vg1相同。例如，数据写入晶体管M3的栅极和阈值补偿晶体管M4的栅极可以电连接到同一条信号线，例如栅线G1，以接收相同的信号(例如，扫描信号Vg1)，此时，包含该像素电路100的显示面板可以不设置阈值补偿控制线G2，以减少信号线的数量。又例如，数据写入晶体管M3的栅极和阈值补偿晶体管M4的栅极也可以分别电连接至不同的信号线，即数据写入晶体管M3的栅极电连接到栅线G1，阈值补偿晶体管M4的栅极电连接到阈值补偿控制线G2，而栅线G1和阈值补偿控制线G2传输的信号相同。
需要说明的是，阈值补偿控制信号Vg2和扫描信号Vg1也不相同，从而使得数据写入晶体管M3和阈值补偿晶体管M4可以被分开单独控制，增加控制像素电路的灵活性。
例如，如图4所示，像素电路100还包括参考电压写入子电路17。参考电压写入子电路17被配置为接收参考电压控制信号VCR并根据参考电压控制信号VCR向第二电容C2的第一端(即第四节点N4)写入参考电压。
例如，参考电压写入子电路17可以包括参考电压写入晶体管M5。参考电压写入晶体管M5的第一极被配置为接收参考电压V ref，参考电压写入晶体管M5的第二极电连接至第二电容C2的第一端，参考电压写入晶体管M5的栅极被配置为接收参考电压控制信号VCR。例如，参考电压写入晶体管M5的第一极可以电连接至参考电源端REF以接收参考电压V ref，参考电压写入晶体管M5的栅极可以电连接至参考电压控制线CR以接收参考电压控制信号VCR。
例如，在数据写入阶段，参考电压控制线CR可以向参考电压写入晶体管M5的栅极提供参考电压控制信号VCR，以使参考电压写入晶体管M5导通。 参考电源端REF可以向参考电压写入晶体管M5的第一极提供参考电压V ref，从而参考电压V ref经由参考电压写入晶体管M5对第二电容C2的第一端充电，由此第二电容C2的第一端的电压可以为参考电压V ref。
例如，参考电压控制信号VCR和发光控制信号VEM可以相同。例如，发光控制晶体管M2的栅极和参考电压写入晶体管M5的栅极可以电连接到同一条信号线，例如发光控制线EM，以接收相同的信号(例如，发光控制信号VEM)，此时，包含该像素电路100的显示面板可以不设置参考电压控制线CR，减少信号线的数量。
需要说明的是，参考电压控制信号VCR和发光控制信号VEM也可以不相同，本公开的实施例对此不作限制。
例如，如图4所示，像素电路100还包括第一复位子电路18。第一复位子电路18被配置为接收第一复位控制信号并根据第一复位控制信号向第三节点N3(即驱动晶体管M1的栅极)写入第一复位电压。
例如，第一复位子电路18包括第一复位晶体管M6。第一复位晶体管M6的第一极被配置为接收第一复位电压，第一复位晶体管M6的第二极电连接至第三节点N3，即第一复位晶体管M6的第二极电连接至驱动晶体管M1的栅极，第一复位晶体管M6的栅极被配置为接收第一复位控制信号Vrt1。例如，第一复位晶体管M6的第一极电连接至第一复位电源端VINT以接收第一复位电压Vint1，第一复位晶体管M6的栅极电连接至第一复位控制信号线Rst1以接收第一复位控制信号Vrt1。
例如，第一复位电源端VINT为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端VINT可以为高压端，也可以为低压端，只要其能够提供第一复位电压Vint1以对第三节点N3进行复位即可，本公开对此不作限制。
例如，如图4所示，像素电路100还包括第二复位子电路19。第二复位子电路19被配置为接收第二复位控制信号并根据第二复位控制信号向第二电容C2的第一端(即第四节点N3)写入第二复位电压。
例如，第二复位子电路19包括第二复位晶体管M7。在图4所示的实施例中，第一电源端VDD输出的第一电压可以作为第二复位电压Vint2，从而第二复位晶体管M7的第一极电连接至第一电源端VDD。第二复位晶体管M7的第二极电连接至第二电容C2的第一端。第二复位晶体管M7的栅极被配置为接收第二复位控制信号Vrt2，例如，第二复位晶体管M7的栅极电连接至第二复位控制信号线Rst2以接收第二复位控制信号Vrt2。然而，本公开的实施例不限于此，第二复位晶体管M7的第一极也可以电连接至单独设置的第二复位电源端，以接收第二复位电压Vint2。
例如，第一复位控制信号Vrt1和第二复位控制信号Vrt2可以相同，从而 第一复位晶体管M6的栅极和第二复位晶体管M7的栅极可以电连接至同一条信号线(例如，第一复位控制信号线Rst1)以接收相同的复位控制信号(例如第一复位控制信号Vrt1)。需要说明的是，第一复位控制信号Vrt2和第二复位控制信号Vrt2也可以不相同。
例如，在一些实施例中，第一复位电压Vint1和第二复位电压Vint2可以相同。
需要说明的是，图4所示的像素电路中的第二补偿子电路、参考电压写入子电路、第一复位子电路、第二复位子电路、发光控制子电路、数据写入子电路、存储子电路仅为示意性的，第二补偿子电路、参考电压写入子电路、第一复位子电路、第二复位子电路、发光控制子电路、数据写入子电路、存储子电路等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
本公开一实施例还提供一种显示基板。图5为本公开一些实施例提供的一种显示基板的示意性框图，图6为图4所示的像素电路中的第一节点的截面示意图。
例如，如图5所示，显示基板200可以包括衬底基板110和根据本公开任一实施例所述的像素电路100和发光元件EL。发光元件EL和像素电路100均设置在衬底基板110上。
例如，显示基板200可以应用于有机发光二极管显示面板等。显示基板200可以为阵列基板。
例如，衬底基板110可以为玻璃基板、石英基板等合适的基板。
例如，在一些实施例中，在像素电路100中的第一补偿子电路包括第一电容的情况下，例如以图4所示的实施例为例，如图6所示，第一电容C1包括 第一电极321和第二电极，第一电容C1的第一电极321为第一电容C1的第一端，第一电容C1的第二电极为第一电容C1的第二端，即第一电容C1的第一电极321电连接至第一节点N1，即第一电容C1的第一电极321电连接至驱动晶体管M1的第二极(例如，漏极)，第一电容C1的第二电极电连接至第二节点N2，即第一电容C1的第二电极电连接发光元件EL的第一发光电压施加电极。
例如，如图6所示，在第一电容C1和衬底基板110之间还具有第一中间层331和第二中间层332。第一中间层331可以包括像素电路中的晶体管(例如，发光控制晶体管、驱动晶体管等)的栅极绝缘层(GI层)、栅极层(GATE层)、层间介质层(ILD)等，第二中间层332可以包括像素电路中的晶体管(例如，发光控制晶体管、驱动晶体管等)的有源半导体层等。例如，栅极绝缘层和层间介质层为无机层，栅极层等为金属层。
例如，如图6所示，发光元件EL包括第一发光电压施加电极301、第二发光电压施加电极302和设置在第一发光电压施加电极301和第二发光电压施加电极302之间的发光层303。
例如，发光层303的材料可以根据发光元件EL发射光的颜色的不同进行选择。发光层303的材料包括荧光发光材料或磷光发光材料等。例如，第一发光电压施加电极301为阳极，第二发光电压施加电极302为阴极，第一发光电压施加电极301和第二发光电压施加电极302均采用导电材料制备。
例如，如图6所示，第一发光电压施加电极301和发光层303之间设置有第一有机层311，第二发光电压施加电极302和发光层303之间设置有第二有机层312。第一有机层311和第二有机层312用于起平坦作用，可以被省略。需要说明的是，在本公开的实施例中，每个发光元件的发光层可以包括电致发光层本身以及位于电致发光层两侧的其他公共层，例如，空穴注入层、空穴传输层、电子注入层以及电子传输层等等，但是在本公开的附图中，仅示出了发光层中的电致发光层，而没有示出其他公共层。
例如，第一发光电压施加电极301在衬底基板110上的正投影、发光层303在衬底基板110上的正投影和第二发光电压施加电极302在衬底基板110上的正投影至少部分交叠。例如，第一发光电压施加电极301在衬底基板110上的正投影位于第二发光电压施加电极302在衬底基板110上的正投影内，发光层303在衬底基板110上的正投影位于第二发光电压施加电极302在衬底基板110上的正投影内。
需要说明的是，对于每个子像素(例如第一子像素、第二子像素、第三子像素或第四子像素)，在第一发光电压施加电极301在衬底基板110上的正投影、发光层303在衬底基板110上的正投影和第二发光电压施加电极302在衬 底基板110上的正投影的投影重叠的区域内，对应于像素界定层的开口的部分用于发光。
例如，在垂直于衬底基板110的方向上，第一电容C1的第一电极321位于第一发光电压施加电极301和衬底基板110之间，第一发光电压施加电极301位于第一电容C1的第一电极321和发光层303之间。
例如，第一电容C1的第二电极和第一发光电压施加电极301一体设置，也就是说，第一电容C1的第二电极和第一发光电压施加电极301为同一个电极，第一发光电压施加电极301复用为第一电容C1的第二电极。从而，本公开实施例提供的像素电路中仅通过在第一发光电压施加电极301和第一中间层331之间增加一层金属层以形成第一电容C1的第一电极321，该第一电容C1的第一电极321和第一发光电压施加电极301即可形成第一电容C1，从而实现对第二节点的电平进行补偿，解决显示面板的像素亮度差异的问题，提高显示均匀性和显示效果。例如，第一电容C1的第二电极和第一发光电压施加电极301也可以分别为两个单独的电极，但第一电容C1的第二电极和第一发光电压施加电极301彼此电连接。
例如，第一电容C1的第一电极321(即增加的金属层)在衬底基板110上的正投影与第一发光电压施加电极301在衬底基板110上的正投影至少部分重叠。例如，在一些示例中，第一电容C1的第一电极321在衬底基板110上的正投影位于第一发光电压施加电极301在衬底基板110上的正投影内，即第一发光电压施加电极301在衬底基板110上的正投影完全覆盖第一电容C1的第一电极321在衬底基板110上的正投影。
需要说明的是，如图6所示，第一发光电压施加电极301和第一电极321之间还设置有电介质层341，第一发光电压施加电极301和第一电极321不直接电连接。
值得注意的是，对于显示基板200的其它组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开一实施例还提供一种像素电路的驱动方法，该驱动方法可以应用于上述任一项所述的像素电路。图7为本公开一些实施例提供的一种像素电路的驱动方法的示意性流程图。如图7所示，像素电路的驱动方法包括以下步骤：
S10：在数据写入阶段，向驱动子电路写入数据电压，并且基于第一节点的电平对第二节点的电平进行补偿；
S20：在发光阶段，驱动子电路基于数据电压驱动发光元件发光。
例如，在一些实施例中，在像素电路还包括第一复位子电路和第二复位子电路的情况下，例如在图4所示的实施例中，像素电路的驱动方法还包括：在复位阶段，利用第一复位子电路对第三节点进行复位，利用第二复位子电路对 第四节点进行复位。
例如，像素电路的时序图可以根据实际需求进行设定，本公开的实施例对此不作具体限定。
例如，在一些示例中，图8是图4所示的像素电路的驱动方法的示例性时序图。下面结合图4和图8详细说明本公开实施例提供的一种像素电路的驱动方法的操作流程。需要说明的是，在下面的描述中，第一复位控制信号Vrt1和第二复位控制信号Vrt2相同，阈值补偿控制信号Vg2和扫描信号Vg1相同，参考电压控制信号VCR和发光控制信号VEM相同。像素电路中的所有晶体管均为P型晶体管。
例如，如图4和图8所示，在复位阶段T1，第一复位控制信号Vrt1和第二复位控制信号Vrt2均为低电平信号(即开启信号，例如-6V)，扫描信号Vg1、阈值补偿控制信号Vg2、参考电压控制信号VCR和发光控制信号VEM均为高电平信号(即截止信号，例如6V)，从而第一复位晶体管M6和第二复位晶体管M7均导通，发光控制晶体管M2、数据写入晶体管M3、阈值补偿晶体管M4、参考电压写入晶体管M5均截止。第一复位电源端VINT输出的第一复位电压Vint1经由第一复位晶体管M6被写入第三节点N3(即驱动晶体管M1的栅极和第二电容C2的第二端)以对第三节点N3进行复位，第一电源端VDD输出的第二复位电压Vint2经由第二复位晶体管M7被写入第四节点N4(即第二电容C2的第一端)以对第四节点N4进行复位。由此，在前一帧中，保持在驱动晶体管M1的栅极上的电压和第二电容C2的第一端上的电压被清除，驱动晶体管M1的栅极和第二电容C2的第一端均被复位，例如，此时，第三节点N3上的电压为第一复位电压Vint1，第四节点N4上的电压为第二复位电压Vint2，第一复位电压Vint1和第二复位电压Vint2相同，从而第三节点N3上的电压和第四节点N4上的电压相同。
例如，如图4和图8所示，在数据写入阶段T2，第一复位控制信号Vrt1和第二复位控制信号Vrt2变为高电平信号，扫描信号Vg1、阈值补偿控制信号Vg2变为低电平信号，参考电压控制信号VCR和发光控制信号VEM保持为高电平信号。由此，数据写入晶体管M3和阈值补偿晶体管M4均导通，第一复位晶体管M6、第二复位晶体管M7、发光控制晶体管M2和参考电压写入晶体管M5均截止。由于数据写入晶体管M3导通，数据电压Vdata(例如，数据电压Vdata的范围为2.1V至4.5V)经由数据写入晶体管M3被写入第四节点N4，从而第四节点N4上的电压变为数据电压Vdata，由于第二电容C2的自举效应，第三节点N3上的电压也变为数据电压Vdata，此外，阈值补偿晶体管M4导通，驱动晶体管M1形成二极管连接方式，控制驱动晶体管M1也导通，阈值补偿晶体管M4也导通，第一电源端VDD输出的第一电压V1可以经由驱 动晶体管M1和阈值补偿晶体管M4对第三节点N3充电，当第三节点N3的电压为V1+Vth时，Vth为驱动晶体管M1的阈值电压，驱动晶体管M1的第一极(驱动晶体管M1的第一极的电压为第一电压V1)和栅极之间的电压差VGS与驱动晶体管M1的阈值电压Vth相等，即VGS＝Vth，此时，驱动晶体管M1截止，阈值补偿结束。
需要说明的是，阈值补偿电压可以为V1+Vth。
例如，在数据写入阶段T2，由于阈值补偿晶体管M4导通，第一节点N1的电压和第三节点N3的电压相同，从而第一节点N1的电压的变化过程与第三节点N3的电压的变化过程相同，由于第一电容C1的自举效应，当第一节点N1的电压变化时，可以控制第二节点N2的电压发生相应的变化，从而实现对第二节点N2进行补偿。例如，若第一节点N1的电压逐渐升高，则第二节点N2的电压也逐渐升高。
例如，如图4和图8所示，在发光阶段T3，第一复位控制信号Vrt1和第二复位控制信号Vrt2保持为高电平信号，扫描信号Vg1、阈值补偿控制信号Vg2变为高电平信号，参考电压控制信号VCR和发光控制信号VEM变为低电平信号。由此，发光控制晶体管M2和参考电压写入晶体管M5均导通，数据写入晶体管M3、阈值补偿晶体管M4、第一复位晶体管M6和第二复位晶体管M7均截止。由于参考电压写入晶体管M5导通，参考电压V ref经由参考电压写入晶体管M5被写入第四节点N4，从而第四节点N4上的电压变为参考电压V ref，即第四节点N4上的电压由数据电压Vdata变为参考电压V ref，由于第二电容C2的自举效应，第三节点N3上的电压变为V ref－Vdata+V1+Vth，即驱动晶体管M1的栅极上的电压为V ref－Vdata+V1+Vth，驱动晶体管M1的第一极上的电压为第一电压V1。需要说明的是，在步骤S12中，“驱动子电路基于数据电压驱动发光元件发光”表示驱动子电路在电压V ref－Vdata+V1+Vth的控制下导通，从而驱动发光元件发光。
例如，在发光阶段T3，驱动晶体管M1处于饱和状态，根据驱动晶体管M1的饱和电流公式，流经驱动晶体管M1的发光电流IEL可以表示为：
I EL＝K*(VGS-Vth) 2
＝K*[(V ref-Vdata+V1+Vth-V1)-Vth] 2
＝K*(V ref-Vdata) 2
由上述公式中可以看到，发光电流I EL已经不受驱动晶体管M1的阈值电压Vth和第一电源端VDD输出的第一电压的影响，而只与参考电源端REF输出的参考电压V ref和数据电压Vdata有关。数据电压Vdata由数据线直接传输，其与驱动晶体管M1的阈值电压Vth无关，从而可以解决驱动晶体管M1由于工艺制程及长时间的操作造成阈值电压漂移的问题。参考电压V ref由参考电源 端REF提供，其与第一电源端VDD的电源电压降(IR drop)无关，从而可以解决显示面板的IR drop的问题。综上所述，像素电路可以保证发光电流IEL的准确性，消除驱动晶体管M1的阈值电压和IR drop对发光电流IEL的影响，保证发光元件EL正常工作。此外，在该像素电路中，通过在第一节点N1和第二节点N2之间增加第一电容C1，以基于第一节点N1的电平对第二节点N2的电平进行补偿，从而可以解决显示面板的像素亮度差异的问题，提高显示画面的均匀性，提升显示效果。
例如，上述公式中K为常数，且K可以表示为：
K＝0.5*μ n*C ox*(W/L)
其中，μ n为驱动晶体管M1的电子迁移率，C ox为驱动晶体管M1的栅极单位电容量，W为驱动晶体管M1的沟道宽，L为驱动晶体管M1的沟道长。
需要说明的是，复位阶段、数据写入阶段和发光阶段的设置方式可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
本公开实施例还提供一种显示面板。图9为本公开一些实施例提供的一种显示面板的局部结构示意图。
例如，如图9所示，本公开实施例提供的显示面板500包括衬底基板501和位于衬底基板501上的多个重复单元502。每个重复单元502包括第一子像素5021、第二子像素5022、第三子像素5023和第四子像素5024。第一子像素5021包括第一发光元件和第一像素电路，第一像素电路为根据上述任一实施例所述的像素电路，第一发光元件是由第一像素电路驱动的发光元件，也就是说，第一像素电路可以为图4所示的像素电路100，第一发光元件可以为图4所示的发光元件EL。
需要说明的是，图9所示的第一子像素5021和第二子像素5022的位置关系仅是示意性的，本公开对第一子像素5021和第二子像素5022的相对位置关系不作限定，但是在本公开的实施例中，第一子像素5021的第一像素电路中的驱动晶体管的栅极在衬底基板上的正投影与第一子像素5021的第一发光元件的阳极在衬底基板上的正投影彼此至少部分交叠，而第二子像素5022的第二像素电路中的驱动晶体管的栅极在衬底基板上的正投影和第二子像素5022的第二发光元件的阳极在衬底基板上的正投影彼此不交叠。此外，图9中仅示出了各个子像素的例如阳极的形状。
图10为本公开一些实施例提供的一种第二像素电路的结构示意图。例如，如图10所示，第二子像素5022包括第二发光元件EL'和第二像素电路，第二像素电路被配置为驱动第二发光元件EL'发光。相较于第一像素电路，第二像素电路不包括设置在第一节点N1和第二节点N2之间的第一电容，除此之外，第二像素电路中的其余组件和第一像素电路中的其余组件均相同，即如图10 所示，第二像素电路可以包括驱动子电路11'、发光控制子电路12'、数据写入子电路13'、存储子电路14'、第二补偿子电路16'、参考电压写入子电路17'、第一复位子电路18'和第二复位子电路19'等，且各子电路的连接方式与第一像素电路中的相应的各个子电路的连接方式相同。
图11为图10所示的第二像素电路中的第一节点的截面示意图。如图11所示，第二发光元件EL'包括第一发光电压施加电极301'、第二发光电压施加电极302'和设置在第一发光电压施加电极301'和第二发光电压施加电极302'之间的发光层303'。第一发光电压施加电极301'和发光层303'之间设置有第一有机层311'，第二发光电压施加电极302'和发光层303'之间设置有第二有机层312'。在第一发光电压施加电极301'和衬底基板501之间还具有第一中间层331'和第二中间层332'。相较于第一像素电路，在第二像素电路的第一节点处，没有设置一层金属层，即在第一节点和第二节点之间未设置电容。
例如，在垂直于衬底基板501的方向上，第一像素电路中的驱动子电路位于衬底基板501和第一发光元件之间，第二像素电路中的驱动子电路位于衬底基板501和第二发光元件之间。第一像素电路中的驱动子电路在衬底基板501上的正投影和第一发光元件在衬底基板501上的正投影至少部分重叠，例如，第一像素电路中的驱动子电路在衬底基板501上的正投影位于第一发光元件在衬底基板501上的正投影内，例如，第一像素电路中的驱动子电路在衬底基板501上的正投影和第一发光元件在衬底基板501上的正投影完全重叠。第二像素电路中的驱动子电路在衬底基板501上的正投影和第二发光元件在衬底基板501上的正投影至少部分不重叠，例如，第二像素电路中的驱动子电路在衬底基板501上的正投影和第二发光元件在衬底基板501上的正投影完全不重叠。例如，第一子像素5021中的驱动晶体管的栅极在衬底基板501上的正投影与第一发光元件的阳极在衬底基板501上的正投影交叠，而第二子像素5022中的驱动晶体管的栅极在衬底基板501上的正投影与第二发光元件的阳极在衬底基板501上的正投影不交叠。
若采用现有的像素电路驱动第一发光元件和第二发光元件时，即第一像素电路和第二像素电路均为图10所示的像素电路时，由于第一子像素5021中的驱动子电路在衬底基板501上的正投影与第一发光元件的阳极在衬底基板501上的正投影交叠，而第二子像素5022中的驱动子电路在衬底基板501上的正投影与第二发光元件的阳极在衬底基板501上的正投影不交叠，则第二子像素5022的第二像素电路中的驱动晶体管的栅极处的电压比第一子像素5021的第一子像素电路中的驱动晶体管的栅极处的电压小，从而流过第二子像素5022的第二像素电路中的驱动晶体管的发光电流大于流过第一子像素5021的第一子像素电路中的驱动晶体管的发光电流，第二发光元件的亮度比第一发光元件 的亮度高，造成第一子像素和第二子像素的亮度不一致。
图12为图9所示的重复单元中的第一子像素的阳极电压和第二子像素的阳极电压的检测结果示意图。
若采用本公开实施例提供的像素电路作为第一子像素中的第一像素电路，第一像素电路中的第一补偿子电路(即图4所示的第一电容C1)可以对第二节点的电平进行补偿，以提高第一发光元件的亮度，使第一发光元件的亮度和第二发光元件的亮度一致。例如，第一像素电路中的第一电容C1的电容值的范围可以为1fF至8fF，但本公开不限于此，只要该第一电容C1能使第一子像素的第一像素电路中的第二节点和第二子像素的第二像素电路中的第二节点的电压相当即可，例如，使第一像素电路中的第二节点的电压和第二像素电路中的第二节点的电压大致相等即可。如图12所示，对图9所示的一个重复单元中的第一子像素5021和第二子像素5022进行模拟分析，根据模拟结果可知，第一子像素5021的阳极电压为0.8682伏特(V)，第二子像素5022的阳极电压为0.8682V，即第一子像素5021的阳极电压与第二子像素5022的阳极电压相等，第一子像素5021的亮度和第二子像素5022的亮度相同，从而提高了显示面板的亮度均匀性。
例如，第三子像素5023可以包括第三发光元件和第三像素电路，第三像素电路被配置为驱动第三发光元件发光。第四子像素5024可以包括第四发光元件和第四像素电路，第四像素电路被配置为驱动第四发光元件发光。第三像素电路和第四像素电路均可以与图10所示的第二像素电路相同。
例如，第一子像素5021和第二子像素5022均为绿色子像素，第三子像素5023为红色子像素，第四子像素5024为蓝色子像素。即第一发光元件和第二发光元件均被配置为发出绿光，第三发光元件被配置为发出红光，第四发光元件被配置为发出蓝光。
例如，第一子像素5021的发光元件(即第一发光元件)的发光层在衬底基板110上的正投影与第二子像素5022的发光元件(即第二发光元件)的发光层在衬底基板110上的正投影是连续的，也就是说，第一子像素的发光元件的发光层和第二子像素的发光元件的发光层可以由高精细金属掩模(FMM)板中的一个开孔制作，可以有效降低FMM的工艺难度。例如，第一子像素5021的发光元件的发光层和第二子像素5022的发光元件的发光层为一个整体，即第一子像素5021的发光元件的发光层和第二子像素5022的发光元件的发光层一体设置。对于第一子像素5021和第二子像素5022，一体设置的发光层与第一子像素5021的发光元件的第一发光电压施加电极交叠的部分可以表示为第一子像素5021的发光元件的发光层，一体设置的发光层与第二子像素5022的发光元件的第一发光电压施加电极交叠的部分可以表示为第二子像素5022的 发光元件的发光层。
例如，显示面板500还包括像素界定层(未示出)，位于各个子像素的发光元件的第一发光电压施加电极远离衬底基板110的一侧且包括第一开口，第一开口暴露第一子像素5021的发光元件的第一发光电压施加电极和第二子像素5022的发光元件的第一发光电压施加电极的至少一部分，第一子像素5021的发光元件的发光层和第二子像素5022的发光元件的发光层的至少部分位于第一开口内并覆盖第一子像素5021的第一发光电压施加电极的被暴露的部分和第二子像素5022的第一发光电压施加电极的被暴露的部分，第一开口与第一子像素5021的第一发光电压施加电极交叠的部分区域为第一子像素5021的有效发光区，第一开口与第二子像素5022的第一发光电压施加电极交叠的部分区域为第二子像素5022的有效发光区。例如，像素界定层还包括第二开口，第二开口暴露第三子像素5023的发光元件的第一发光电压施加电极的一部分，第三子像素5023的发光元件的发光层的至少部分位于第二开口内并覆盖第三子像素5023的第一发光电压施加电极的被暴露的部分，第二开口与第三子像素5023的第一发光电压施加电极交叠的部分区域为第三子像素5023的有效发光区。像素界定层还包括第三开口，第三开口暴露第四子像素5024的发光元件的第一发光电压施加电极的一部分，第四子像素5024的发光元件的发光层的至少部分位于第三开口内并覆盖第四子像素5024的第一发光电压施加电极的被暴露的部分，第三开口与第四子像素5024的第一发光电压施加电极交叠的部分区域为第四子像素5024的有效发光区。
例如，在一些实施例中，显示面板上所有子像素的发光元件的第二发光电压施加电极均一体设置，也就是说，第二发光电压施加电极整层覆盖在整个衬底基板110上，即第二发光电压施加电极可以为一个面状电极。例如，对于第一子像素5021和第二子像素5022，面状的第二发光电压施加电极与第一子像素5021的发光元件的第一发光电压施加电极交叠的部分可以表示为第一子像素5021的发光元件的第二发光电压施加电极，面状的第二发光电压施加电极与第二子像素5022的发光元件的第一发光电压施加电极交叠的部分可以表示为第二子像素5022的发光元件的第二发光电压施加电极。即第一子像素5021的发光元件的第二发光电压施加电极和第二子像素5022的发光元件的第二发光电压施加电极一体设置。
例如，如图9所示，在每个重复单元502中，第一子像素5021和第二子像素5022沿第一方向X排列，第三子像素5023和第四子像素5024沿第二方向Y排列，第一方向X和第二方向Y分别为在同一平面内(例如平行于衬底基板501的表面的平面)相互垂直的两个方向。
例如，在每个重复单元502内，第一子像素5021的中心和第二子像素5022 的中心的连线为第一中心线，第三子像素5023的中心和第四子像素5024的中心的连线为第二中心线。第一中心线的长度短于第二中心线的长度。例如，第一中心线和第二中心线相互垂直平分，且第一中心线与第一方向X平行，第二中心线与第二方向Y平行。
例如，如图9所示，多个重复单元502沿第二方向Y排列以形成多个重复单元组，图9示出了两个重复单元组，且两个重复单元组分别为第P个重复单元组和第P+1个重复单元组，第P个重复单元组和第P+1个重复单元组为相邻的两个重复单元组，例如，P为大于等于1的正整数。多个重复单元组沿第一方向X排列。也就是说，多个重复单元502沿第一方向X和第二方向Y呈阵列排布。
例如，第P个重复单元组中的重复单元的第一子像素和第二子像素的中心的连线的延长线和第P+1个重复单元组中的重复单元的第一子像素和第二子像素的中心的连线的延长线不重合。例如，第P个重复单元组中的重复单元的第一子像素和第二子像素的中心的连线的延长线穿过第P+1个重复单元组中相邻两个重复单元之间的间隔的中心，类似地，第P+1个重复单元组中的重复单元的第一子像素和第二子像素的中心的连线的延长线穿过第P个重复单元组中相邻两个重复单元之间的间隔的中心。
图13为本公开一些实施例提供的一种显示面板上的重复单元的示意图。
例如，如图13所示，第一子像素5021的第一发光元件的第一发光电压施加电极包括第一驱动电极块De1和第一连接电极块Ce1，第一驱动电极块De1和第一连接电极块Ce1电连接。在每个重复单元502中，在第一方向X上，第一连接电极块Ce1位于第一驱动电极块De1的远离第二子像素5022的第二发光元件的一侧。
例如，第一连接电极块Ce1用于连接第一驱动电极块De1与第一子像素5021的第一像素电路。
例如，在一些实施例中，第一连接电极块Ce1和第一驱动电极块De1一体设置。需要说明的是，在另一些示例中，第一连接电极块Ce1和第一驱动电极块De1也可以分别单独设置，只要第一连接电极块Ce1和第一驱动电极块De1能够彼此电连接即可。
例如，如图13所示，第二子像素5022的第二发光元件的第一发光电压施加电极包括第二驱动电极块De2和第二连接电极块Ce2，第二驱动电极块De2和第二连接电极块Ce2电连接。在每个重复单元502中，在第一方向X上，第二连接电极块Ce2位于第二驱动电极块De2的远离第一子像素5021的第一发光元件的一侧。
例如，第二连接电极块Ce2用于连接第二驱动电极块De2与第二子像素 5022的第二像素电路。
例如，在一些实施例中，第二连接电极块Ce2和第二驱动电极块De2一体设置。需要说明的是，在另一些示例中，第二连接电极块Ce2和第二驱动电极块De2也可以分别单独设置，只要第二连接电极块Ce2和第二驱动电极块De2能够彼此电连接即可。
例如，在第一方向X上，第一驱动电极块De1位于第一连接电极块Ce1和第二驱动电极块De2之间，第二驱动电极块De2位于第二连接电极块Ce2和第一驱动电极块De1之间。
例如，第一驱动电极块De1的中心和第二驱动电极块De2的中心之间的连线与第一方向X平行。
例如，第一驱动电极块De1的形状和第二驱动电极块De2的形状可以相同，第一驱动电极块De1在衬底基板110上的正投影的面积与第二驱动电极块De2在衬底基板110上的正投影的面积相同。第一连接电极块Ce1的形状和第二连接电极块Ce2的形状也可以相同，第一连接电极块Ce1在衬底基板110上的正投影的面积与第二连接电极块Ce2在衬底基板110上的正投影的面积相同。例如，第一驱动电极块De1的形状和第二驱动电极块De2的形状均可以为矩形、五边形或菱形等。第一连接电极块Ce1的形状和第二连接电极块Ce2的形状可以为规则形状，例如，矩形、菱形等；第一连接电极块Ce1的形状和第二连接电极块Ce2的形状也可以为不规则形状。
需要说明的是，在一些实施例中，第一驱动电极块De1的形状与第二驱动电极块De2的形状也可以为矩形或菱形等。第一驱动电极块De1的形状与第二驱动电极块De2的形状也可以不相同，本公开对此不作限制。
例如，在第二方向Y上，第一连接电极块Ce1的宽度小于第一驱动电极块De1的最大宽度，第二连接电极块Ce2的宽度小于第二驱动电极块De2的最大宽度。
例如，如图13所示，第三子像素5023的第三发光元件的第一发光电压施加电极包括第三驱动电极块De3和第三连接电极块Ce3，第三驱动电极块De3和第三连接电极块Ce3电连接。在每个重复单元502中，在第一方向X上，第三连接电极Ce3位于第三驱动电极块De3的远离第二子像素5022的第二连接电极块Ce2的一侧，在第二方向Y上，第三连接电极Ce3位于第三驱动电极块De3的靠近第四驱动电极块De4的一侧，也就是说，在图13所示的示例中，第三连接电极块Ce3位于第三驱动电极块De3的左下侧，即第三子像素5023的第三发光元件的第一发光电压施加电极的形状可以与Q字形类似。
例如，第三连接电极块Ce3用于连接第三驱动电极块De3与第三子像素5023的第三像素电路。
例如，在一些实施例中，第三驱动电极块De3和第三连接电极块Ce3一体设置。需要说明的是，在另一些示例中，第三驱动电极块De3和第三连接电极块Ce3也可以分别单独设置，只要第三驱动电极块De3和第三连接电极块Ce3能够彼此电连接即可。
例如，如图13所示，第四子像素5024的第四发光元件的第一发光电压施加电极包括第四驱动电极块De4和第四连接电极块Ce4，第四驱动电极块De4和第四连接电极块Ce4电连接。例如，如图13所示，在每个重复单元502中，在第一方向X上，第四连接电极Ce4位于第四驱动电极块De4的远离第二子像素5022的第二连接电极块Ce2的一侧，在第二方向Y上，第四连接电极Ce4位于第四驱动电极块De4的靠近第三驱动电极块De3的一侧，也就是说，在图13所示的示例中，第四连接电极块Ce4位于第四驱动电极块De4的右下侧，即第四子像素5024的第四发光元件的第一发光电压施加电极的形状可以与Q字镜像对称的形状类似。
例如，第四连接电极块Ce4用于连接第四驱动电极块De4与第四子像素5024的第四像素电路。
例如，在一些实施例中，第四连接电极块Ce4和第四驱动电极块De4一体设置。需要说明的是，在另一些示例中，第四连接电极块Ce4和第四驱动电极块De4也可以分别单独设置，只要第四连接电极块Ce4和第四驱动电极块De4能够彼此电连接即可。
例如，第三驱动电极块De3的中心和第四驱动电极块De4的中心之间的连线与第二方向Y平行。
例如，第三驱动电极块De3的形状和第四驱动电极块De4的形状可以相同，而第三驱动电极块De3在衬底基板110上的正投影的面积和第四驱动电极块De4在衬底基板110上的正投影的面积不相同。例如，第三驱动电极块De3的形状和第四驱动电极块De4的形状均为矩形、六边形或长椭圆形等。第三驱动电极块De3的面积小于第四驱动电极块De4的面积。
例如，第三连接电极块Ce3的形状和面积和第四连接电极块Ce4的形状和面积可以不相同。例如，第三连接电极块Ce3的形状和第四连接电极块Ce4的形状可以为规则形状，例如，矩形、菱形等；第三连接电极块Ce3的形状和第四连接电极块Ce4的形状也可以为不规则形状，例如，图13所示的示例中，第三连接电极块Ce3的形状和第四连接电极块Ce4的形状为不规则的六边形。
例如，在第一方向X上，第一连接电极块Ce1、第二连接电极块Ce2、第三连接电极块Ce3和第四连接电极块Ce4位于相邻两个重复单元组之间。例如，在一些实施例中，对于位于第P+1个重复单元组中的重复单元502，第一连接电极块Ce1、第三连接电极块Ce3和第四连接电极块Ce4位于第P+1个重复单 元组和相邻下一个重复单元组(即第P+2个重复单元组)之间，第二连接电极块Ce2位于第P个重复单元组和第P+1个重复单元组之间。
例如，第一驱动电极块De1在衬底基板501上的正投影和第一像素电路的驱动晶体管的栅极在衬底基板501上的正投影至少部分重叠。第二驱动电极块De2在衬底基板501上的正投影和第二像素电路的驱动晶体管的栅极在衬底基板501上的正投影完全不重叠。第三驱动电极块De3在衬底基板501上的正投影和第三像素电路的驱动晶体管的栅极在衬底基板501上的正投影至少部分重叠。第四驱动电极块De4在衬底基板501上的正投影和第四像素电路的驱动晶体管的栅极在衬底基板501上的正投影至少部分重叠。
例如，在垂直于衬底基板501的表面的方向上，每个子像素的像素电路位于中间层和衬底基板501之间，每个子像素的发光元件位于中间层的远离衬底基板501的一侧，也就是说，第一像素电路、第二像素电路、第三像素电路和第四像素电路均位于中间层和衬底基板501之间，第一发光元件、第二发光元件、第三发光元件和第四发光元件均位于中间层的远离衬底基板501的一侧。
例如，中间层可以为一平坦绝缘层。在垂直于衬底基板501的表面的方向上，第一子像素5021的第一发光元件的第一发光电压施加电极设置在第一子像素5021的第一发光元件的发光层的靠近中间层的一侧，第一子像素5021的第一发光元件的第二发光电压施加电极设置在第一子像素5021的第一发光元件的发光层的远离中间层的一侧。第二子像素5022中的第二发光元件、第三子像素5023中的第三发光元件和第四子像素5024中的第四发光元件与第一发光元件的层结构相似，在此不再赘述。
例如，如图13所示，中间层包括第一过孔h1、第二过孔h2、第三过孔h3和第四过孔h4等。
例如，每个像素电路可以包括有源半导体层、栅极金属层和源漏极金属层，在垂直于衬底基板501的方向上，有源半导体层位于衬底基板501与栅极金属层之间，栅极金属层位于有源半导体层和源漏极金属层之间。
例如，在本公开中，每个子像素的像素电路中的各个晶体管(例如，驱动晶体管M1、发光控制晶体管M2、数据写入晶体管M3、阈值补偿晶体管M4、参考电压写入晶体管M5、第一复位晶体管M6、第二复位晶体管M7等)的有源层均位于有源半导体层内，每个子像素的像素电路中的各个晶体管的栅极均位于栅极金属层内，像素电路中的各个晶体管的源极和漏极均位于源漏极金属层内。各有源层可包括源极区域、漏极区域和源极区域和漏极区域之间的沟道区。例如，各晶体管的有源层一体设置。
例如，第一连接电极块Ce1延伸至第一过孔h1处且通过第一过孔h1与第一子像素5021的第一像素电路电连接，例如，第一连接电极块Ce1通过第一 过孔h1与第一子像素5021的第一像素电路的发光控制晶体管的第二极电连接。例如，第一连接电极块Ce1通过第一过孔h1延伸到源漏极金属层，以与位于源漏极金属层的第一像素电路的发光控制晶体管的第二极电连接。
例如，第二连接电极块Ce2延伸至第二过孔h2处且通过第二过孔h2与第二子像素5022的第二像素电路电连接，例如，第二连接电极块Ce2通过第二过孔h2与第二子像素5022的第二像素电路的发光控制晶体管的第二极电连接。例如，第二连接电极块Ce2通过第二过孔h2延伸到源漏极金属层，以与位于源漏极金属层的第二像素电路的发光控制晶体管的第二极电连接。
例如，第三连接电极块Ce3延伸至第三过孔h3处且通过第三过孔h3与第三子像素5023的第三像素电路电连接。例如，第三连接电极块Ce3通过第三过孔h3与第三子像素5023的第三像素电路的发光控制晶体管的第二极电连接。例如，第三连接电极块Ce3通过第三过孔h3延伸到源漏极金属层，以与位于源漏极金属层的第三像素电路的发光控制晶体管的第二极电连接。
例如，第四连接电极块Ce4延伸至第四过孔h4处且通过第四过孔h4与第四子像素5024的第四像素电路电连接。例如，第四连接电极块Ce4通过第四过孔h4与第四子像素5024的第四像素电路的发光控制晶体管的第二极电连接。例如，第四连接电极块Ce4通过第四过孔h4延伸到源漏极金属层，以与位于源漏极金属层的第四像素电路的发光控制晶体管的第二极电连接。
需要说明的是，各个子像素的连接电极块可以覆盖并填充对应的过孔，例如，第一连接电极块Ce1覆盖并填充第一过孔h1，第二连接电极块Ce2覆盖并填充第二过孔h2，第三连接电极块Ce3覆盖并填充第三过孔h3，第四连接电极块Ce4覆盖并填充第四过孔h4，然而，为了示出各个过孔的位置，在图13中示出的各个过孔位于对应的连接电极块上方。
例如，第一子像素5021的像素电路(即第一像素电路)的驱动晶体管的栅极和第二子像素5022的像素电路(即第二像素电路)的驱动晶体管的栅极沿第一方向X排布。
例如，在第一方向X上，第二驱动电极块De2位于第二子像素的像素电路的驱动晶体管的栅极靠近第一子像素的像素电路的驱动晶体管的栅极的一侧。例如，在第一方向X上，第二驱动电极块De2位于第一子像素的像素电路的驱动晶体管的栅极和第二子像素的像素电路的驱动晶体管的栅极之间。
例如，在第一方向X上，第二连接电极块Ce2位于第二驱动电极块De2的远离第一子像素5021的像素电路的驱动晶体管的栅极的一侧。例如，在第一方向X上，第二连接电极块Ce2位于第一子像素的像素电路的驱动晶体管的栅极和第二子像素的像素电路的驱动晶体管的栅极之间。
例如，在第一方向X上，第一连接电极块Ce1位于第一子像素5021的像 素电路的驱动晶体管的栅极的远离第二子像素5022的像素电路的驱动晶体管的栅极的一侧。
例如，第一子像素5021的像素电路的驱动晶体管的栅极的中心和第一驱动电极块De1的中心之间的距离小于第二子像素5022的像素电路的驱动晶体管的栅极的中心和第二驱动电极块De2的中心之间的距离。
需要说明的是，在本公开中，“中心”可以表示元件的物理形状的几何中心。在对像素排列结构进行设计时，驱动晶体管的栅极、发光元件的阳极等元件一般会设计为规则的形状，比如，矩形、六边形、五边形、梯形或其他形状。在进行设计时，元件(例如，驱动晶体管的栅极或发光元件的阳极等)的中心可以是上述规则形状的几何中心。然而，在实际制造工艺中，所形成的驱动晶体管的栅极、发光元件的阳极等元件的形状一般会与上述设计的规则形状有一定的偏差。例如，上述规则的形状的各个角可能会变成圆角，因此，驱动晶体管的栅极、发光元件的阳极等元件的形状可以为圆角图形。此外，实际制造的驱动晶体管的栅极、发光元件的阳极等元件的形状还可能会与设计的形状有其他的变化。例如，设计为六边形的子像素的形状在实际制造中可能变成近似椭圆形。因此，驱动晶体管的栅极、发光元件的阳极等元件的中心也可能并非制作形成的元件的不规则形状的严格的几何中心。在本公开的实施例中，元件的中心可以与元件的形状的几何中心有一定的偏移量。此外，“中心”也可以表示元件的重心。
例如，如图4所示，对于每个子像素的像素电路，参考电源端REF与参考电源线连接，第一复位电源端VINT与第一复位电源线连接。在一些实施例中，栅线G1和阈值补偿控制线G2可以为同一条信号线，第一复位控制信号线Rst1和第二复位控制信号线Rst2可以为同一条信号线，发光控制线EM和参考电压控制线CR可以为同一条信号线。
例如，在衬底基板上，栅线G1、阈值补偿控制线G2、参考电压控制线CR、第一复位控制信号线Rst1、第二复位控制信号线Rst2、发光控制线EM、参考电源线、第一复位电源线沿第一方向X排布，且均沿第二方向Y延伸。
例如，栅线G1、阈值补偿控制线G2、参考电压控制线CR、第一复位控制信号线Rst1、第二复位控制信号线Rst2、发光控制线EM、参考电源线、第一复位电源线大致平行。
例如，第一电源端VDD与第一电源线连接，第一电源线和数据线D彼此大致平行。例如，第一电源线和数据线D沿第二方向Y排布，且均沿第一方向X延伸。
需要说明的是，在本公开中，“延伸”表示各条信号线(例如，第一栅极信号线、第二栅极信号线、基准控制信号线、发光控制信号线、第一复位信号 线、第二复位信号线、初始化信号线和基准电压信号线)大体上的走线方向，各条信号线在微观上可能并不是直线，而是呈波浪状沿第二方向Y延伸。
图14为本公开一些实施例提供的另一种显示面板的平面局部示意图。
例如，如图14所示，201至206可以为衬底基板110上各个子像素的像素电路所在区域。例如，在图14所示的示例中，在点划线圈出的重复单元502中，第一子像素5021的第一像素电路位于区域202，第二子像素5022的第二像素电路位于区域205，第三子像素5023的第三像素电路位于区域201，第四子像素5024的第四像素电路位于区域203。
例如，如图14所示，有源半导体层28设置在衬底基板501上，有源半导体28的在各个子像素的像素电路所在区域的部分的形状相同。也就是说，例如，有源半导体28位于区域202中的第一部分的形状和有源半导体28位于区域205中的第二部分的形状相同。
例如，如图14所示，与位于区域202中的第一像素电路电连接的信号线25和信号线26均沿第二方向Y延伸，且在垂直于衬底基板501的方向上，信号线25和信号线26与区域202中的第一像素电路至少部分交叠。与位于区域205中的第二像素电路电连接的信号线24和信号线27均沿第二方向Y延伸，且在垂直于衬底基板501的方向上，信号线24和信号线27与区域205中的第二像素电路至少部分交叠。
例如，信号线24、信号线25、信号线26和信号线27彼此大致平行。信号线24、信号线25、信号线26和信号线27沿第一方向X排布。
需要说明的是，在图14所示的示例中，与第一像素电路电连接的栅线G1和补偿控制线G2为同一条信号线25，与第一像素电路电连接的参考电压控制线CR和发光控制线EM为同一条信号线26，即图14所示的信号线25既作为与第一像素电路电连接的栅线G1，也复用为与第一像素电路电连接的补偿控制线G2，图14所示的信号线26既作为与第一像素电路电连接的参考电压控制线CR，又复用为与第一像素电路电连接的发光控制线EM。与第二像素电路电连接的栅线G1和补偿控制线G2为同一条信号线24，与第二像素电路电连接的参考电压控制线CR和发光控制线EM为同一条信号线27。即图14所示的信号线24既作为与第二像素电路电连接的栅线G1，也复用为与第二像素电路电连接的补偿控制线G2，图14所示的信号线27既作为与第二像素电路电连接的参考电压控制线CR，又复用为与第二像素电路电连接的发光控制线EM。
例如，如图4、图6和图14所示，第一像素电路包括第一电容C1，在第一方向X上，第一电容C1的第一电极321位于信号线25和信号线26之间；第一电容C1的第一电极321在衬底基板501上的正投影与第一发光电压施加 电极301在衬底基板501上的正投影至少部分重叠，例如，第一电容C1的第一电极321在衬底基板501上的正投影位于第一发光电压施加电极301在衬底基板501上的正投影内。例如，如图4和图14所示，第一像素电路还包括驱动晶体管M1、发光控制晶体管M2、数据写入晶体管M3和阈值补偿晶体管M4，驱动晶体管M1的第二极(例如，漏极)在衬底基板501上的正投影、发光控制晶体管M2的第一极(例如，源极)在衬底基板501上的正投影、阈值补偿晶体管M4的第一极(例如，源极)在衬底基板501上的正投影彼此至少部分重叠。
需要说明的是，图14中，矩形虚线圈示出的区域分别表示在衬底基板501上驱动晶体管M1的栅极对应的区域、发光控制晶体管M2的栅极对应的区域、数据写入晶体管M3的栅极对应的区域和阈值补偿晶体管M4的栅极对应的区域。例如，从图14中可以看出，驱动晶体管M1的栅极在衬底基板501上的正投影与第一子像素5021的发光元件的阳极(即第一发光电压施加电极)在衬底基板501上的正投影至少部分重叠，发光控制晶体管M2的栅极在衬底基板501上的正投影与信号线26在衬底基板501上的正投影至少部分重叠，阈值补偿晶体管M4的栅极在衬底基板501上的正投影与信号线25在衬底基板501上的正投影至少部分重叠。例如，在垂直于衬底基板501的方向上，信号线26的与有源半导体层28交叠的部分(图中与发光控制晶体管M2对应的矩形虚线框示出的部分)包括发光控制晶体管M2的栅极，信号线25的与有源半导体层28交叠的部分(图中与阈值补偿晶体管M4对应的矩形虚线框示出的部分)包括阈值补偿晶体管M4的栅极。
例如，驱动晶体管M1的栅极(图14所示的电极块29)与信号线25和信号线26位于同一层。
例如，如图4、图6和图14所示，在第一像素电路包括第一电容C1、阈值补偿晶体管M4和发光控制晶体管M2的情况下，在第一方向X上，第一电容C1的第一电极321在衬底基板501上的正投影位于阈值补偿晶体管M4的栅极在衬底基板501上的正投影和发光控制晶体管M2的栅极在衬底基板501上的正投影之间。
例如，如图14所示，第一电容C1的第一电极321在衬底基板501上的正投影与阈值补偿晶体管M4的有源层和发光控制晶体管M2的有源层之间的部分有源半导体层28在衬底基板501上的正投影至少部分重叠。
例如，在一些示例中，驱动晶体管M1的第二极、发光控制晶体管M2的第一极、阈值补偿晶体管M4的第一极可以一体设置。
例如，第一电容C1的第一电极321在衬底基板501上的正投影和驱动晶体管M1的第二极在衬底基板501上的正投影至少部分重叠。例如，在一些实 施例中，驱动晶体管M1的第二极在衬底基板501上的正投影位于第一电容C1的第一电极321在衬底基板501上的正投影之内。
例如，第一电容C1的第一电极321的形状可以为矩形，且矩形的长边例如可以与第一方向X大致平行。
例如，第一电容C1的第一电极321、驱动晶体管M1的第二极、发光控制晶体管M2的第一极、阈值补偿晶体管M4的第一极均电连接。在一些实施例中，用于形成第一电容C1的第一电极321的金属层直接形成在驱动晶体管M1的第二极上，以实现将第一电容C1的第一电极321电连接至驱动晶体管M1的第二极。在另一些实施例中，第一电容C1的第一电极321和驱动晶体管M1的第二极之间具有一绝缘层，第一电容C1的第一电极321通过绝缘层中的过孔与驱动晶体管M1的第二极电连接。
例如，在重复单元502中，第一子像素5021的像素电路的数据写入子电路、第三子像素5023的像素电路的数据写入子电路和第四子像素5024的像素电路的数据写入子电路均与例如第N行栅线电连接以接收扫描信号，而第二子像素5022的像素电路则与第N-1行栅线电连接以接收扫描信号。第N-1行栅线为与第N行栅线相邻的上一行栅线。N为大于1的正整数。例如，如图14所示，信号线24可以表示第N-1行栅线，信号线25可以表示第N行栅线，在第一方向X上，第N-1行栅线(即信号线24)位于信号线25的远离信号线26的一侧，且第N行栅线(即信号线25)在衬底基板501上的正投影与区域201、区域202、区域203均至少部分交叠，第N-1行栅线(即信号线24)在衬底基板501上的正投影与区域204、区域205、区域206均至少部分交叠。
例如，信号线26可以表示第N行参考电压控制线/发光控制线，信号线27可以表示第N-1行参考电压控制线/发光控制线，且第N行参考电压控制线/发光控制线(即信号线26)在衬底基板501上的正投影与区域201、区域202、区域203均至少部分交叠，第N-1行参考电压控制线/发光控制线(即信号线27)在衬底基板501上的正投影与区域204、区域205、区域206均至少部分交叠。
例如，显示面板500可以为有机发光二极管(OLED)显示面板等。
例如，显示面板500可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板500不仅可以为平面面板，也可以为曲面面板，甚至球面面板。
例如，显示面板500还可以具备触控功能，即显示面板500可以为触控显示面板。
例如，显示面板500可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种像素电路，包括：驱动子电路、发光控制子电路、数据写入子电路、存储子电路和第一补偿子电路，其中，
    所述数据写入子电路被配置为在扫描信号的控制下将数据电压写入所述存储子电路；
    所述存储子电路被配置为存储所述数据电压；
    所述驱动子电路电连接至第一节点，发光元件电连接至第二节点，所述驱动子电路被配置为基于所述数据电压驱动所述发光元件发光；
    所述发光控制子电路分别电连接至所述第一节点和所述第二节点，所述发光控制子电路被配置为实现所述驱动子电路和所述发光元件之间的连接导通或断开；
    所述第一补偿子电路分别电连接至所述第一节点和所述第二节点，且被配置为基于所述第一节点的电平对所述第二节点的电平进行补偿。
  2. 根据权利要求1所述的像素电路，其中，所述第一补偿子电路包括第一电容，
    所述第一电容的第一端电连接至所述第一节点，所述第一电容的第二端电连接至所述第二节点。
  3. 根据权利要求1或2所述的像素电路，其中，所述发光控制子电路包括发光控制晶体管，
    所述发光控制晶体管的第一极与所述第一节点电连接，所述发光控制晶体管的第二极与所述第二节点电连接，所述发光控制晶体管的栅极被配置为接收发光控制信号。
  4. 根据权利要求1～3任一所述的像素电路，其中，所述驱动子电路包括驱动晶体管，
    所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述第一节点电连接，所述驱动晶体管的栅极与第三节点电连接。
  5. 根据权利要求4所述的像素电路，其中，所述数据写入子电路包括数据写入晶体管，所述存储子电路包括第二电容，
    所述数据写入晶体管的第一极被配置为接收所述数据电压，所述数据写入晶体管的第二极与所述第二电容的第一端电连接，所述数据写入晶体管的栅极 被配置为接收所述扫描信号，
    所述第二电容的第二端与所述第三节点电连接。
  6. 根据权利要求5所述的像素电路，还包括第二补偿子电路，
    其中，所述第二补偿子电路被配置为接收阈值补偿控制信号并根据所述阈值补偿控制信号向所述第三节点写入阈值补偿电压。
  7. 根据权利要求5或6所述的像素电路，还包括参考电压写入子电路，
    其中，所述参考电压写入子电路被配置为接收参考电压控制信号并根据所述参考电压控制信号向所述第二电容的第一端写入参考电压。
  8. 根据权利要求4～7任一项所述的像素电路，还包括第一复位子电路，
    其中，所述第一复位子电路被配置为接收第一复位控制信号并根据所述第一复位控制信号向所述第三节点写入第一复位电压。
  9. 根据权利要求5～8任一项所述的像素电路，还包括第二复位子电路，
    其中，所述第二复位子电路被配置为接收第二复位控制信号并根据所述第二复位控制信号向所述第二电容的第一端写入第二复位电压。
  10. 根据权利要求1～3任一所述的像素电路，还包括第二补偿子电路、参考电压写入子电路、第一复位子电路和第二复位子电路，
    其中，所述第一补偿子电路包括第一电容，所述发光控制子电路包括发光控制晶体管，所述驱动子电路包括驱动晶体管，所述数据写入子电路包括数据写入晶体管，所述存储子电路包括第二电容，所述第二补偿子电路包括阈值补偿晶体管，所述参考电压写入子电路包括参考电压写入晶体管，所述第一复位子电路包括第一复位晶体管，所述第二复位子电路包括第二复位晶体管，
    所述第一电容的第一端电连接至所述第一节点，所述第一电容的第二端电连接至所述第二节点，
    所述发光控制晶体管的第一极与所述第一节点电连接，所述发光控制晶体管的第二极与所述第二节点电连接，所述发光控制晶体管的栅极被配置为接收发光控制信号；
    所述驱动晶体管的第一极与第一电源端电连接，所述驱动晶体管的第二极与所述第一节点电连接，所述驱动晶体管的栅极与第三节点电连接；
    所述发光元件的第一发光电压施加电极电连接至所述第二节点，所述发光元件的第二发光电压施加电极电连接至第二电源端；
    所述数据写入晶体管的第一极被配置为接收所述数据电压，所述数据写入 晶体管的第二极与所述第二电容的第一端电连接，所述数据写入晶体管的栅极被配置为接收所述扫描信号；
    所述第二电容的第二端与所述第三节点电连接；
    所述阈值补偿晶体管的第一极电连接至所述第一节点，所述阈值补偿晶体管的第二极电连接至所述第三节点，所述阈值补偿晶体管的栅极被配置为接收阈值补偿控制信号；
    所述参考电压写入晶体管的第一极被配置为接收参考电压，所述参考电压写入晶体管的第二极电连接至所述第二电容的第一端，所述参考电压写入晶体管的栅极被配置为接收参考电压控制信号；
    所述第一复位晶体管的第一极被配置为接收第一复位电压，所述第一复位晶体管的第二极电连接至所述第三节点，所述第一复位晶体管的栅极被配置为接收第一复位控制信号；
    所述第二复位晶体管的第一极电连接至所述第一电源端，所述第二复位晶体管的第二极电连接至所述第二电容的第一端，所述第二复位晶体管的栅极被配置为接收第二复位控制信号。
  11. 一种显示基板，包括衬底基板和根据权利要求1～10任一项所述的像素电路和所述发光元件，
    其中，所述发光元件和所述像素电路设置在所述衬底基板上。
  12. 根据权利要求11所述的显示基板，其中，在所述第一补偿子电路包括第一电容的情况下，
    所述第一电容包括第一电极和第二电极，所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，
    所述第一电容的第一电极电连接至所述第一节点，所述第一电容的第二电极电连接至所述第二节点，
    所述第一电容的第二电极和所述第一发光电压施加电极一体设置，
    在垂直于所述衬底基板的方向上，所述第一电容的第一电极位于所述第一发光电压施加电极和所述衬底基板之间，所述第一发光电压施加电极位于所述第一电容的第一电极和所述发光层之间。
  13. 根据权利要求12所述的显示基板，其中，所述第一电容的第一电极在所述衬底基板上的正投影与所述第一发光电压施加电极在所述衬底基板上 的正投影至少部分重叠。
  14. 一种根据权利要求1～10任一项所述的像素电路的驱动方法，包括：
    在数据写入阶段，向所述驱动子电路写入所述数据电压，并且基于所述第一节点的电平对所述第二节点的电平进行补偿；
    在发光阶段，所述驱动子电路基于所述数据电压驱动所述发光元件发光。
  15. 一种显示面板，包括衬底基板和位于所述衬底基板上的多个重复单元，
    其中，所述多个重复单元中的每个重复单元包括第一子像素和第二子像素，
    所述第一子像素包括第一发光元件和第一像素电路，
    所述第一像素电路为根据权利要求1～10任一项所述的像素电路，所述第一发光元件是由所述第一像素电路驱动的所述发光元件。
  16. 根据权利要求15所述的显示面板，其中，所述第二子像素包括第二发光元件和第二像素电路，所述第二像素电路被配置为驱动所述第二发光元件发光，
    在垂直于所述衬底基板的方向上，所述第一像素电路中的驱动子电路位于所述衬底基板和所述第一发光元件之间，所述第二像素电路中的驱动子电路位于所述衬底基板和所述第二发光元件之间，
    所述第一像素电路中的驱动子电路在所述衬底基板上的正投影和所述第一发光元件在所述衬底基板上的正投影至少部分重叠，
    所述第二像素电路中的驱动子电路在所述衬底基板上的正投影和所述第二发光元件在所述衬底基板上的正投影不重叠。
  17. 根据权利要求16所述的显示面板，其中，所述第一像素电路中的驱动子电路在所述衬底基板上的正投影位于所述第一发光元件在所述衬底基板上的正投影内。
  18. 根据权利要求15～17任一项所述的显示面板，其中，所述每个重复单元还包括第三子像素和第四子像素，
    所述第一子像素和所述第二子像素均为绿色子像素，所述第三子像素为红色子像素，所述第四子像素为蓝色子像素。
  19. 根据权利要求15～18任一项所述的显示面板，其中，所述每个重复单元还包括第三子像素和第四子像素，在所述每个重复单元中，所述第一子像素和所述第二子像素沿第一方向排列，所述第三子像素和所述第四子像素沿第二方向排列，所述第一方向和所述第二方向分别为在同一平面内相互垂直的两个 方向。
  20. 根据权利要求19所述的显示面板，其中，所述多个重复单元沿所述第二方向排列以形成多个重复单元组，所述多个重复单元组沿所述第一方向排列。
  21. 根据权利要求19或20所述的显示面板，其中，在所述第一像素电路包括第一电容、阈值补偿晶体管和发光控制晶体管的情况下，
    在所述第一方向上，所述第一电容的第一电极在所述衬底基板上的正投影位于所述阈值补偿晶体管的栅极在衬底基板上的正投影和所述发光控制晶体管的栅极在所述衬底基板上的正投影之间。
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