WO2023245671A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023245671A1
WO2023245671A1 PCT/CN2022/101312 CN2022101312W WO2023245671A1 WO 2023245671 A1 WO2023245671 A1 WO 2023245671A1 CN 2022101312 W CN2022101312 W CN 2022101312W WO 2023245671 A1 WO2023245671 A1 WO 2023245671A1
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WIPO (PCT)
Prior art keywords
sub
active part
transistor
base substrate
pixel
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PCT/CN2022/101312
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English (en)
French (fr)
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WO2023245671A9 (zh
Inventor
张舜航
张振宇
刘冬妮
玄明花
林允植
张震
李佩柔
郑皓亮
肖丽
李卓
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/101312 priority Critical patent/WO2023245671A1/zh
Priority to CN202280001907.2A priority patent/CN117859416A/zh
Publication of WO2023245671A1 publication Critical patent/WO2023245671A1/zh
Publication of WO2023245671A9 publication Critical patent/WO2023245671A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

Definitions

  • the present disclosure relates to the field of display technology, and specifically, to a display panel and a display device.
  • LED displays are widely used in outdoor and central control large-screen displays.
  • the current application of LED is mainly for long-distance viewing, the pixel pitch is relatively large and the PPI is low.
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art and provide a display panel and a display device.
  • a display panel including a plurality of pixel units distributed in an array along the row and column directions.
  • the pixel unit includes: a pixel driving circuit for providing a driving current; a plurality of sub-pixels, the sub-pixels having The first electrode is used to connect the pixel driving circuit, the second electrode of the sub-pixel is connected to the second power terminal, and the sub-pixel emits light under the action of the driving current;
  • the switching circuit includes a plurality of switching units, so The switch unit is arranged corresponding to the sub-pixel, the switch unit is connected in series between the pixel drive circuit and the corresponding sub-pixel, the control end of the switch unit is used to receive a switch signal, and the first end of the switch unit The second end of the switch unit is connected to the first electrode of the corresponding sub-pixel, and the switch unit conducts a communication path between the sub-pixel and the pixel drive circuit in response to the switch signal.
  • the display panel includes a base substrate; in the same pixel unit, the pixel driving circuit is located where the first electrode of the sub-pixel is located in an orthographic projection of the base substrate.
  • the front projection of the base substrate is away from the second electrode on one side of the front projection of the base substrate, and the switch unit is located on the front projection of the base substrate corresponding to the first electrode of the sub-pixel.
  • the orthographic projection of the base substrate and the second electrode are between the orthographic projection of the base substrate.
  • the display panel further includes: a first drive circuit located in the display area of the display panel, the first drive circuit is used to output a gate control signal; the pixel driver The circuit transmits the data signal at the data signal terminal to the drive signal terminal in response to the gate control signal.
  • the first driving circuit includes a plurality of cascaded first shift register units, and the first shift register unit that provides gate control signals to the pixel units in this row is located in this row. between the pixel unit and the next row of pixel units.
  • the display panel further includes: a switch driving circuit located in a display area of the display panel, and the switch driving circuit is configured to output the switching signal.
  • the switch driving circuit includes a plurality of sub-switch driving circuits, one sub-switch driving circuit drives a column of switch units; the sub-switch driving circuit includes a plurality of cascaded third shift registers unit, the third shift register unit that provides switching signals to the switching circuit of this row is located in the gap between the pixel unit of this row and the pixel unit of the next row.
  • the pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel;
  • the switch circuit includes a first switch unit, a second switch unit and a third switch unit , the first switch unit is connected to the first sub-pixel, the second switch unit is connected to the second sub-pixel, and the third switch unit is connected to the third sub-pixel;
  • the switch driver The circuit includes a first sub-switch driving circuit, a second sub-switch driving circuit and a third sub-switch driving circuit. The first sub-switch driving circuit is used to output a first switching signal to the first switching unit, and the second sub-switch driving circuit is used to output a first switching signal to the first switching unit.
  • the sub-switch driving circuit is used to output a second switching signal to the second switching unit, and the third sub-switching unit is used to output a third switching signal to the third switching unit; wherein the first sub-switch driving circuit The circuit, the second sub-switch driving circuit and the third sub-switch driving circuit successively output the first switch signal, the second switch signal and the third switch signal row by row; and in the first During the time when the sub-switch driving circuit outputs the first switch signal, during the time when the second sub-switch driving circuit outputs the second switch signal, and when the third sub-switch driving circuit outputs the third switch During the signal period, the first driving circuit outputs the gate control signal respectively.
  • the display panel includes two switch driving circuits, and the two switch driving circuits are separately arranged on both sides of the display area along the row direction.
  • the display panel further includes: a driving integrated circuit configured to output the switching signal to each of the switching units respectively.
  • the first driving circuit is located in a non-display area of the display panel.
  • the pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel;
  • the switch circuit includes a first switch unit, a second switch unit and a third switch unit , the first switch unit is correspondingly connected to the first sub-pixel, the second switch unit is correspondingly connected to the second sub-pixel, and the third switch unit is correspondingly connected to the third sub-pixel; wherein, in In the frame data, the driving integrated circuit outputs the first switching signal, the second switching signal and the third switching signal in sequence; during the time when the driving integrated circuit outputs the first switching signal, the first driving circuit A first gate control signal is output to each pixel driving circuit in turn, and the pixel driving circuit provides a driving current to the first sub-pixel in response to the first gate control signal; when the driving integrated circuit outputs the first Within two switching signals, the first driving circuit sequentially outputs a second gate control signal to each pixel driving circuit, and the pixel driving circuit provides a second gate control signal to the second sub-pixel;
  • Driving current within the time when each driving integrated circuit outputs the third switching signal, the first driving circuit outputs a third gate control signal to each pixel driving circuit in turn, and the pixel driving circuit responds to the The third gate control signal provides a driving current to the third sub-pixel.
  • the first switch signal, the second switch signal and the third switch signal have the same duration.
  • the first driving circuit outputs a gate control signal according to a first frequency
  • the driving integrated circuit outputs a switching signal according to a second frequency
  • the first frequency is the second frequency. 3 times the frequency.
  • the pixel driving circuit includes: a driving module connected to a first node, a second node, and a third node, and the driving module is configured to respond to the voltage signal of the first node using The voltage difference between the second node and the third node provides a driving current; a first reset module is connected to the first node, the first reset signal terminal and the initial signal terminal, and the first reset module is used to respond to the first reset signal terminal.
  • a reset signal at the reset signal terminal transmits the initial signal at the initial signal terminal to the first node; a transmission module connects the first node, the gate signal terminal and the second node, and the transmission module is used to respond The signal from the gate signal terminal conducts the communication path between the first node and the second node; the data writing module connects the data signal terminal, the gate signal terminal and the third node, and the data The writing module is used to transmit the second data signal of the data signal terminal to the third node in response to the signal of the gate signal terminal; the second reset module is connected to the fourth node, the initial signal terminal and the third node.
  • a reset signal terminal the second reset module is used to respond to the reset signal of the first reset signal terminal and transmit the initial signal of the initial signal terminal to the fourth node;
  • a first lighting control module is connected to the third node, an enable signal terminal and a first power supply terminal, the first lighting control module is configured to respond to the enable signal of the enable signal terminal to conduct a communication path between the third node and the first power supply terminal;
  • the second A lighting control module connected to the second node, the fourth node and an adjustment module.
  • the second lighting control module is used to connect the fourth node and the second node in response to a signal from the adjustment module.
  • the adjustment module is connected to the data signal end, the second reset signal end, the first reset signal end, the initial signal end and the enable signal end.
  • the adjustment module is used to close all the signals in response to the first data signal of the data signal end. the second lighting control module, or for opening the second lighting control module in response to the second data signal at the data signal terminal.
  • the driving module includes: a driving transistor, a control terminal connected to the first node, a first terminal connected to the third node, and a second terminal connected to the second node;
  • the first reset module includes: a first transistor, the control end is connected to the first reset signal end, the first end is connected to the first node, and the second end is connected to the initial signal end;
  • the transmission module includes: a second transistor, The control terminal is connected to the gate signal terminal, the first terminal is connected to the first node, and the second terminal is connected to the second node;
  • the data writing module includes: a fourth transistor, the control terminal is connected to the gate signal terminal, The first end is connected to the data signal end, the second end is connected to the third node;
  • the second reset module includes: a seventh transistor, the control end is connected to the first reset signal end, and the first end is connected to the initial signal end.
  • the second end is connected to the fourth node;
  • the first light-emitting control module includes: a fifth transistor, the control end is connected to the enable signal end, the first end is connected to the first power end, and the second end is connected to the The third node;
  • the second lighting control module includes: a sixth transistor, the control end is connected to the seventh node, the first end is connected to the second node, and the second end is connected to the fourth node;
  • the adjustment module includes: Eight transistors, the control terminal is connected to the second reset signal terminal, the first terminal is connected to the data signal terminal, the second terminal is connected to the fifth node, and the eighth transistor is used to respond to the reset signal of the second reset signal terminal.
  • the data signal at the data signal terminal is transmitted to the fifth node;
  • the ninth transistor has a control terminal connected to the fifth node, a first terminal connected to the enable signal terminal, a second terminal connected to the seventh node, and the Nine transistors are used to transmit the enable signal of the enable signal terminal to the seventh node in response to the voltage signal of the fifth node;
  • a first capacitor is connected to the fifth node and the initial signal terminal, the The first capacitor is used to store the voltage signal written to the fifth node;
  • the tenth transistor has a control terminal connected to the first reset signal terminal, a first terminal connected to the data signal terminal, and a second terminal connected to the sixth node, The tenth transistor is used to transmit the data signal of the data signal terminal to the sixth node in response to the reset signal of the first reset signal terminal;
  • the control terminal of the eleventh transistor is connected to the sixth node, and the first terminal
  • the high-frequency signal terminal is connected, the second terminal is connected to the seventh node, and the eleventh transistor is
  • the switch unit is a transistor.
  • the pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel
  • the switch circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor.
  • the control terminal of the twelfth transistor receives the first switching signal, the first terminal of the twelfth transistor is connected to the fourth node, and the second terminal of the twelfth transistor is connected to the first electrode of the first sub-pixel
  • the control terminal of the thirteenth transistor receives the second switching signal, the first terminal of the thirteenth transistor is connected to the fourth node, and the second terminal of the thirteenth transistor is connected to the first electrode of the second sub-pixel
  • the control end of the fourteenth transistor receives the third switching signal, the first end of the fourteenth transistor is connected to the fourth node, and the second end of the fourteenth transistor is connected to the first electrode of the third sub-pixel .
  • the display panel includes: a base substrate; a first conductive layer located on one side of the base substrate, the first conductive layer includes: a third conductive portion, To form the first electrode of the storage capacitor; an active layer is located on a side of the first conductive layer facing away from the base substrate, the active layer includes: a first active portion, on the substrate
  • the orthographic projection of the base substrate is located between the orthographic projection of the first conductive part on the base substrate and the orthographic projection of the third conductive part on the base substrate, and the first active part is used to form The channel region of the first transistor; the first sub-active part, connected to one side of the first active part, for forming the first end of the first transistor; the second sub-active part, Connected to the other side of the first active part, used to form the second end of the first transistor and the first end of the seventh transistor; the seventh active part, connected to the second sub-section The source part is connected, and the seventh active part is used to form the channel region of the seventh transistor;
  • the source part is used to form the channel region of the driving transistor; the fifth sub-active part is connected to one side of the third active part along the column direction, and the fifth sub-active part is used to form the The first end of the driving transistor; the sixth sub-active part, connected to the other side of the third active part; the sixth sub-active part is used to form the second end of the driving transistor; the second The active part is located on one side of the third active part along the row direction. The second active part is used to form the channel region of the second transistor; the third sub-active part is connected along the row direction.
  • the third sub-active part is used to form the first end of the second transistor; the fourth sub-active part is connected to The second active part is on a side away from the third active part, and the fourth sub-active part is used to form the second end of the second transistor; the fourth active part is located on the side of the third active part.
  • the third active part is on a side away from the second active part, the fourth active part is used to form the channel region of the fourth transistor; the seventh sub-active part is connected to the fourth active part.
  • the seventh sub-active part is used to form the first end of the fourth transistor;
  • the eighth sub-active part is connected to the fourth active part part is close to the side of the third active part, the eighth sub-active part is used to form the second end of the fourth transistor;
  • the fifth active part is located at the orthographic projection of the base substrate
  • the third active portion is between an orthographic projection of the base substrate and the third conductive portion is an orthographic projection of the base substrate, and the fifth active portion is used to form the fifth transistor.
  • channel region the ninth sub-active part is connected to the side of the fifth active part away from the third active part, and the ninth sub-active part is used to form the fifth transistor.
  • the first end; the tenth sub-active part is connected to the side of the fifth active part close to the third active part, and the tenth sub-active part is used to form the third active part of the fifth transistor.
  • the second conductive layer includes: a third conductive block, the third conductive block includes a first component, a second component, and a third component connected in sequence, and the third conductive block
  • the orthographic projection of a component on the base substrate partially overlaps the orthographic projection of the third conductive part on the base substrate, and the orthographic projection of the third component on the base substrate covers the The orthographic projection of the third active part on the base substrate, part of the structure of the third conductive block is used to form the second electrode of the storage capacitor, part of the structure is used to form the top gate of the driving transistor; gate
  • the gate signal line extends along the row direction in the orthographic projection of the base substrate, and the gate signal line in the orthographic projection of the base substrate is located away from the third component in the orthographic projection of the base substrate.
  • the first component is on one side of the base substrate, and the front projection of the gate signal line on the base substrate covers the front projection of the second active part on the base substrate.
  • the gate electrode; the enable signal line includes a main body part, a first sub-extension part and a second sub-extension part connected in sequence, the orthographic projection of the main part on the substrate is located where the third conductive block is The front projection of the base substrate is away from the gate signal on one side of the front projection of the base substrate, and the second sub-extension portion covers the fifth active portion in the front projection of the base substrate.
  • the sixth conductive block includes a first sub-conductive block and a second sub-conductive block, so The orthographic projection of the first conductive sub-block on the base substrate extends along the column direction, and the orthographic projection of the second conductive sub-block on the base substrate covers the sixth active part on the base substrate.
  • the orthographic projection of the sixth conductive block is used to form the gate of the sixth transistor; the first reset signal line extends along the row direction in the orthographic projection of the base substrate and is located on the third The conductive block is on a side of the orthographic projection of the base substrate away from the third active part and the orthographic projection of the base substrate, and the first reset signal line covers all the orthographic projections of the base substrate.
  • the orthographic projection of the first active part on the base substrate and the orthographic projection of the seventh active part on the base substrate, part of the structure of the first reset signal line is used to form the first The gate electrode of the transistor and the gate electrode of the seventh transistor; a third conductive layer, located on the side of the second conductive layer facing away from the base substrate, the third conductive layer includes: a third transfer part, One end of the third transfer part is connected to the third sub-active part through a via hole, and the other end is connected to the third conductive block through a via hole; the fourth transfer part is respectively connected to the fourth sub-active part through a via hole.
  • the sub-active part, the sixth sub-active part and the eleventh sub-active part; the fifth adapter part is respectively connected to the fifth sub-active part and the eighth sub-active part through via holes.
  • the source part and the tenth sub-active part; the sixth transfer part is connected to the twelfth sub-active part through a via hole;
  • the seventeenth conductive block includes a main conductive part and a sub-conductive part, the main conductive part
  • the orthographic projection of the third conductive block on the base substrate is located on the orthographic projection of the third conductive block on the base substrate, and the seventeenth conductive block is connected to the third conductive portion and the third conductive portion through via holes respectively.
  • part of the structure of the seventeenth conductive block is used to form the first electrode of the storage capacitor, part of the structure is used to form the first end of the fifth transistor; the data signal line, in the The orthographic projection of the base substrate extends along the column direction, and the data line is connected to the seventh sub-active part through a via hole.
  • the first conductive layer further includes: a first conductive part for forming a first electrode of the first capacitor; a second conductive part for forming the second The second electrode of the capacitor; the fourth conductive part is located on the side of the third conductive part away from the first conductive part, and the fourth conductive part covers the third conductive part in the orthographic projection of the base substrate
  • the source part is an orthographic projection of the base substrate, and the fourth conductive part is used to form a bottom gate of the driving transistor; a fifth conductive part is connected to one side of the fourth conductive part, and the fifth conductive part is The conductive part is connected to the third transfer part through a via hole;
  • the active layer further includes: an eighth active part, the first conductive part is located on the orthographic projection of the base substrate on the base substrate The eighth active part is used to form a channel region of the eighth transistor and the third conductive part is between the orthographic projection of the substrate and the third conductive part, and the fifteenth sub-active part is connected to One side
  • the ninth active portion the first conductive portion is located in the orthographic projection of the base substrate and the third conductive portion is located in the orthographic projection of the base substrate
  • the ninth active part is used to form the channel region of the ninth transistor
  • the seventeenth sub-active part is connected to one side of the ninth active part, used to form the first end of the ninth transistor
  • the eighteenth sub-active part connected to the other side of the ninth active part, used to form the second end of the ninth transistor
  • the tenth The active portion is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate, the The tenth active part is used to form the channel region of the tenth transistor
  • the nineteenth sub-active part is connected to one side of the tenth active part and is used to form the first channel region of the tenth transistor.
  • the twentieth sub-active part is connected to the other side of the tenth active part and is used to form the second end of the tenth transistor;
  • the eleventh active part is on the base substrate
  • the orthographic projection of the first conductive part on the base substrate and the orthographic projection of the third conductive part on the base substrate are located between the orthographic projection of the first conductive part on the base substrate, and the eleventh active part is used to form the The channel region of the eleventh transistor;
  • the twenty-first sub-active part connected to one side of the eleventh active part, used to form the first end of the eleventh transistor;
  • the twentieth Two sub-active parts are connected to the other side of the eleventh active part and are used to form the second end of the eleventh transistor;
  • the second conductive layer also includes: a first high-frequency signal line , the orthographic projection of the base substrate extends along the row direction and is located on a side of the orthographic projection of the first conductive portion on the base substrate away from the orthographic projection of the third conductive portion on the base
  • the third power line extends along the row direction in the orthographic projection of the base substrate and is located in the orthographic projection of the first high-frequency signal line in the base substrate and the first conductive portion in the substrate Between the orthographic projection of the substrate, the third power line is used to provide the second power terminal of the first sub-pixel; the second power line extends along the row direction in the orthographic projection of the substrate and is located at the A third power line is between an orthographic projection of the base substrate and an orthographic projection of the first conductive portion on the base substrate, and the second power line is used to provide the second sub-pixel and the The second power terminal of the third sub-pixel; the initial signal line, which extends along the row direction in the orthographic projection of the base substrate and is located in the orthographic projection of the first conductive portion in the base substrate and the third conductive part
  • the second reset signal line extends along the row direction from the orthographic projection of the base substrate and is located between the orthographic projection of the base substrate and the original signal line.
  • the third conductive block is between the orthographic projection of the base substrate, and the orthographic projection of the second reset signal line on the base substrate covers the orthographic projection of the eighth active part on the base substrate. , part of the structure of the second reset signal line is used to form the gate of the eighth transistor; the first power line extends along the row direction in the orthographic projection of the substrate and is located where the first reset signal.
  • the orthographic projection of the base substrate and the third conductive block are between the orthographic projection of the base substrate, and the main body portion of the enable signal line is located on the third conductive block in the orthographic projection of the base substrate.
  • a power line is between the orthographic projection of the base substrate and the third conductive block on the orthographic projection of the base substrate; the first conductive block is located on the first conductive block in the orthographic projection of the base substrate.
  • the conductive part is on the orthographic projection of the base substrate, and the first conductive block is used to form the second electrode of the first capacitor;
  • the second conductive block is on the orthographic projection of the base substrate on the third.
  • the two conductive parts are on the orthographic projection of the base substrate, and the second conductive block is used to form the second electrode of the second capacitor;
  • the third conductive block includes a first component and a second component connected in sequence. and a third component.
  • the orthographic projection of the first component on the base substrate is located on the orthographic projection of the third conductive part on the base substrate.
  • the first component is used to form the storage capacitor. the second electrode; the orthographic projection of the third component on the base substrate covers the orthographic projection of the third active part on the base substrate, and the third component is used to form the gate of the driving transistor; fourth A conductive block, the orthographic projection of the base substrate covers the orthographic projection of the ninth active part on the base substrate, and part of the structure of the fourth conductive block is used to form the gate of the ninth transistor. ;
  • the sixth conductive block includes a first sub-conductive block and a second sub-conductive block. The first sub-conductive block extends along the column direction in the orthographic projection of the base substrate, and the second sub-conductive block extends in the orthographic projection of the base substrate.
  • the orthographic projection of the second sub-conductive block on the base substrate covers the orthographic projection of the sixth active part on the base substrate, and part of the structure of the sixth conductive block is used to form the third The gates of the six transistors; the ninth conductive block, the orthographic projection of the eleventh active part on the base substrate covers the orthographic projection of the eleventh active part on the base substrate, and part of the structure of the ninth conductive block is used to form the first The gate electrode of the eleven transistor, the ninth conductive block is connected to the eleventh transfer part and the twelfth transfer part respectively through a via hole; the tenth conductive block is connected to the seventeenth transfer part through a via hole Sub-active part; the third conductive layer also includes: a second high-frequency signal line extending in the column direction in the orthographic projection of the substrate substrate, the second high-frequency signal line is connected to the third through a via hole A high-frequency signal line; a data signal line extending along the column direction in the orthographic projection of the base substrate,
  • the eighteenth sub-active part and the twenty-second sub-active part a tenth transfer part, respectively connected to the fifth conductive block and the sixth conductive block through via holes; an eleventh transfer part , connecting the twentieth sub-active part and the ninth conductive block respectively through via holes; a twelfth transfer part connecting the ninth conductive block and the second conductive block respectively through via holes; Sixteen transfer parts, respectively connected to the twenty-first sub-active part and the seventh conductive block located on the second conductive layer through via holes, and the seventh conductive block is also connected to the second high frequency through via holes Signal line; wherein, the orthographic projection of the first reset signal line on the base substrate also covers the orthographic projection of the tenth active part on the base substrate, and part of the structure of the first reset signal line used to form the gate of the tenth transistor.
  • the active layer further includes: a twelfth active part for forming a channel region of the twelfth transistor, a twenty-third sub-active part connected On one side of the twelfth active part, the twenty-third sub-active part is used to form the first end of the twelfth transistor, and the twenty-third sub-active part passes through a via hole Connected to the sixth switching part; the twenty-fourth sub-active part is connected to the other side of the twelfth active part, and the twenty-fourth sub-active part is used to form the tenth The second end of the second transistor; the thirteenth active part, used to form the channel region of the thirteenth transistor; the twenty-fifth sub-active part, connected to one side of the thirteenth active part , used to form the first end of the thirteenth transistor, the twenty-fifth sub-active part is connected to the sixth transfer part through a via hole; the twenty-sixth sub-active part is connected to the The other
  • the twenty-seventh sub-active part is connected to the first through a via hole.
  • the second conductive layer also includes : A twelfth conductive block, the orthographic projection of the base substrate covers the orthographic projection of the twelfth active part on the base substrate, the twelfth conductive block is used to form the twelfth The gate of the transistor;
  • the fourteenth conductive block, the orthographic projection on the base substrate covers the orthographic projection of the fourteenth active part on the base substrate, the fourteenth conductive block used to form the gate of the fourteenth transistor;
  • the third conductive layer also includes:
  • a display device including the display panel according to any embodiment of the present disclosure.
  • the display panel provided by the present disclosure includes a plurality of sub-pixels in a pixel unit and a pixel drive circuit.
  • the plurality of sub-pixels are connected to the pixel drive through a switch circuit provided, so that the multiple sub-pixels in a pixel unit pass through the switch.
  • the circuit multiplexes a pixel drive circuit.
  • Each switch unit in the switch circuit can switch the connection between the pixel drive circuit and the sub-pixels by responding to the corresponding switch signal.
  • the pixel drive circuit can provide the connected sub-pixels with information according to the set timing. The corresponding driving current realizes the normal display of the display panel.
  • Multiple sub-pixels in a pixel unit of the present disclosure multiplex a pixel driving circuit, which can reduce the space occupied by a single pixel unit, thereby increasing the number of pixels that can be arranged in the display area, that is, increasing the pixel density.
  • Figure 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a pixel unit in Figure 1;
  • Figure 3 is a driving timing diagram according to an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • Figure 7 is a driving timing diagram according to another embodiment of the present disclosure.
  • Figure 8 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • Figure 9 is a timing diagram of each node in Figure 8 according to a driving method of the present disclosure.
  • Figure 10 is a timing diagram of each node in Figure 8 according to another driving method of the present disclosure.
  • Figure 11 is a structural layout according to an embodiment of the present disclosure.
  • Figure 12 is a structural layout of the first conductive layer in Figure 11;
  • Figure 13 is the structural layout of the active layer in Figure 11;
  • Figure 14 is a structural layout of the second conductive layer in Figure 11;
  • Figure 15 is a structural layout of the third conductive layer in Figure 11;
  • Figure 16 is a structural layout of the fourth conductive layer in Figure 11;
  • FIG. 17 is a partial cross-sectional view along the dotted line AA in FIG. 11 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • Figure 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • Figure 2 is a schematic structural diagram of a pixel unit in Figure 1.
  • the display panel may include X and columns along the row direction A plurality of pixel units distributed in the direction Y array, the pixel unit may include a pixel drive circuit P-Drive, a plurality of sub-pixels and a switch circuit MSW, where the pixel drive circuit P-Drive is used to provide drive current; the first electrode P of the sub-pixel -AOD is used to connect the pixel drive circuit P-Drive, the second electrode P-CTO of the sub-pixel is connected to the second power supply terminal, and the sub-pixel emits light under the action of the drive current; the switch circuit MSW can include multiple switch units, and the switch unit is connected to the second power supply terminal.
  • the sub-pixels are set correspondingly.
  • the switch unit is connected in series between the pixel drive circuit P-Drive and the corresponding sub-pixel.
  • the control end of the switch unit is used to receive the switch signal.
  • the first end of the switch unit is connected to the pixel drive circuit P-Drive.
  • the switch unit The second end is connected to the second electrode P-CTO of the corresponding sub-pixel, and the switching unit responds to the switching signal to conduct a communication path between the sub-pixel and the pixel driving circuit P-Drive.
  • the display panel provided by the present disclosure includes multiple sub-pixels in one pixel unit and includes a pixel drive circuit P-Drive.
  • the multiple sub-pixels are connected to the pixel drive through the provided switch circuit MSW, so that multiple sub-pixels in one pixel unit
  • the sub-pixel multiplexes a pixel drive circuit P-Drive through the switch circuit MSW.
  • Each switch unit in the switch circuit MSW can connect and switch the pixel drive circuit P-Drive and the sub-pixel by responding to the corresponding switch signal. According to the set
  • the timing is provided by the pixel drive circuit P-Drive to provide corresponding drive current to the connected sub-pixels to achieve normal display of the display panel.
  • Multiple sub-pixels in a pixel unit of the present disclosure multiplex a pixel drive circuit P-Drive, which can reduce the space occupied by a single pixel unit, thereby increasing the number of pixels that can be arranged in the display area, that is, increasing the pixel density.
  • the sub-pixels in the pixel unit are set to share the same pixel drive circuit P-Drive, and the switch circuit MSW performs conduction switching between the sub-pixels and the pixel drive circuit P-Drive, because the switch unit in the switch circuit MSW takes up space. It is much smaller than the space occupied by one pixel drive circuit P-Drive, which can greatly reduce the space occupied by the pixel unit, thereby increasing the pixel layout density in the display area.
  • the display panel of the present disclosure in the display panel of the present disclosure, the overall occupied area of a single pixel unit can be reduced by more than 30%. Obviously, the display panel of the present disclosure can greatly improve the pixel count. density.
  • the number of switch units included in the switch circuit MSW in each pixel unit may be the same as the number of sub-pixels in the pixel unit.
  • a pixel unit may include a first sub-pixel, a second sub-pixel and a third sub-pixel.
  • the first sub-pixel may be an R pixel, for example, the second sub-pixel may be a G pixel, and the third sub-pixel may be a B pixel, for example.
  • the switch circuit MSW may include a first switch unit MUX1, a second switch unit MUX2 and a third switch unit MUX3.
  • the first switch unit MUX1 is connected in series between the first sub-pixel and the pixel drive circuit P-Drive.
  • the two switch units MUX2 are connected in series between the second sub-pixel and the pixel drive circuit P-Drive, and the third switch unit MUX3 is connected in series between the third sub-pixel and the pixel drive circuit P-Drive.
  • Each switch unit responds to its respective The obtained switching signal turns on the communication path between the corresponding sub-pixel and the pixel drive circuit P-Drive.
  • the first switch unit MUX1 acquires the first switch signal
  • the first sub-pixel establishes a connection with the pixel drive circuit P-Drive.
  • the pixel drive circuit P-Drive can switch to the third sub-pixel under the action of the current data signal.
  • One sub-pixel provides a driving current to drive the first sub-pixel to perform light-emitting display.
  • the second switch unit MUX2 obtains the second switch signal
  • the second sub-pixel establishes a connection with the pixel drive circuit P-Drive.
  • the pixel drive circuit P-Drive can provide the second sub-pixel with the current data signal.
  • the driving current drives the second sub-pixel to perform light-emitting display.
  • the third switching unit MUX3 obtains the third switching signal
  • the third sub-pixel establishes a connection with the pixel driving circuit P-Drive.
  • the pixel driving circuit P-Drive switches to the third sub-pixel under the action of the corresponding data signal.
  • the pixel provides a driving current to drive the third sub-pixel to emit light and display.
  • the pixel driving circuit P-Drive is located in the orthographic projection of the base substrate and the first electrode P-AOD of the sub-pixel is far away from the orthographic projection of the base substrate.
  • the second electrode P-CTO is on the front projection side of the base substrate.
  • the switching unit is on the front projection side of the base substrate.
  • the first electrode P-AOD of the corresponding sub-pixel is on the front projection side of the base substrate and the second electrode P- The CTO is between the orthographic projections of the base substrate.
  • the pixel unit may include a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel may be arranged along the column direction Y, and the switch circuit MSW may include a
  • the first switch unit MUX1, the second switch unit MUX2 and the third switch unit MUX3 are arranged in the column direction Y and respectively correspond to the three sub-pixels.
  • the first switch unit MUX1 is connected to the first sub-pixel.
  • the first switch unit MUX1 The orthographic projection on the base substrate may be located between the orthographic projection of the first electrode P-AOD of the first sub-pixel on the base substrate and the orthographic projection of the second electrode P-CTO on the base substrate.
  • the second switching unit MUX2 is connected to the second sub-pixel, so the orthographic projection of the second switching unit MUX2 on the substrate is located at the orthographic projection of the first electrode P-AOD of the second sub-pixel on the substrate and the second electrode P-CTO. between orthographic projections of the base substrate.
  • the third switching unit MUX3 is connected to the third sub-pixel, then the orthographic projection of the third switching unit MUX3 on the base substrate is located at the orthographic projection of the first electrode P-AOD of the third sub-pixel on the base substrate and the second electrode P-CTO between orthographic projections of the base substrate.
  • the pixel driving circuit P-Drive is located on a side of the first electrode away from the second electrode.
  • the first electrode P-AOD may be, for example, an anode
  • the second electrode P-CTO may be, for example, a cathode.
  • the first electrode P-AOD can also be a cathode
  • the second electrode P-CTO can be an anode, which is not limited in this disclosure.
  • orthographic projection of the pixel driving circuit P-Drive described in the present disclosure on the substrate can be understood as the orthographic projection of the layout structure of each device in the pixel driving circuit P-Drive on the substrate.
  • orthographic projection of the switch unit on the substrate substrate can be understood as the orthographic projection of the layout structure forming the switch unit on the substrate substrate.
  • the switching circuit MSW may be controlled by a switching signal output by the switch driving circuit MOA.
  • the switch drive circuit MOA may include a plurality of cascaded third shift register units. Each third shift register provides a switching signal to the switch unit in its corresponding pixel row. Each shift register is connected in cascade, thereby switching the drive circuit.
  • the MOA provides switching signals to the switching units in each row in turn.
  • the pixel unit may include three sub-pixels
  • the switch driving circuit MOA may include a first sub-switch driving circuit MOAR, a second sub-switch driving circuit MOAG and a third sub-switch driving circuit MOAB.
  • the first The sub-switch driving circuit MOAR can be used to provide the corresponding switching signal to the first switch unit MUX1 to control the connection between the first sub-pixel and the pixel driving circuit P-Drive;
  • the second sub-switch driving circuit MOAG can be used to provide the corresponding switch signal to the second switch unit MUX1.
  • the unit MUX2 provides a corresponding switch signal to control the connection between the second sub-pixel and the pixel drive circuit P-Drive; the third sub-switch drive circuit MOAB can be used to provide a corresponding switch signal to the third switch unit MUX3 to control the third sub-switch unit MUX3.
  • the first sub-switch driving circuit MOAR, the second sub-switch driving circuit MOAG, and the third sub-switch driving circuit MOAB each include a plurality of cascaded third shift register units.
  • the third shift register in the first sub-switch driving circuit MOAR The register unit is used to provide a first switch signal to the first switch unit MUX1 of the corresponding row to control the connection between the first sub-pixel of the corresponding row and the pixel drive circuit P-Drive; the third shifter in the second sub-switch drive circuit MOAG
  • the bit register unit is used to provide a second switch signal to the second switch unit MUX2 of the corresponding row to control the connection between the second sub-pixel of the corresponding row and the pixel drive circuit P-Drive; the third sub-switch drive circuit MOAB
  • the shift register unit is used to provide a third switch signal to the third switch of the corresponding row to control the connection between the third sub-pixel of the corresponding row and the pixel drive circuit P-Drive.
  • Figure 3 is a driving timing diagram according to an embodiment of the present disclosure.
  • the switch drive circuit MOA can sequentially connect each sub-pixel of each row with the pixel drive circuit P-Drive in a row-by-row manner. connection, and within the time when the switch drive circuit MOA outputs the switching signal, other drive circuits in the display panel provide the reset signal, gate control signal and enable control signal to the pixel drive circuit P-Drive, so that the pixel drive circuit P-Drive It can provide driving current to the sub-pixels connected thereto to drive the sub-pixels connected thereto to emit light and display.
  • the first sub-switch driving circuit MOAR in the first row can first output the first switch signal to turn on all the first switch units MUX1 in the first row, so that each first sub-pixel in the first row is connected to the corresponding The pixel drive circuit P-Drive is connected.
  • the third drive circuit RST GOA, the first drive circuit Gate GOA, and the second drive circuit EM GOA in the display panel can provide reset signals to the pixel drive circuit P-Drive of the first row in sequence. , gate control signal and enable signal, the pixel drive circuit P-Drive provides drive current to each first sub-pixel in the first row in response to the above signal, so that each first sub-pixel in the first row responds to the first switching signal Illuminated display within the effective time.
  • the second sub-switch drive circuit MOAG in the first row outputs a second switch signal to turn on all the second switch units MUX2 in the first row, and connects the second sub-pixel in the first row with the corresponding pixel drive circuit P-Drive.
  • the third drive circuit RST GOA, the first drive circuit Gate GOA and the second drive circuit EM GOA repeat the above process to output the reset signal, gate control signal and enable signal respectively, so that the first row
  • the pixel driving circuit P-Drive can provide driving current to each second sub-pixel to drive the second sub-pixel in the first row to perform light-emitting display.
  • the third sub-switch driving circuit MOAB of the first row outputs an electrical switching signal to turn on all the third switch units MUX3 of the first row, and connects the pixel driving circuit P-Drive of the first row to the third sub-pixel
  • the third drive circuit RST GOA, the first drive circuit Gate GOA and the second drive circuit EM GOA of the display panel respectively output the reset signal, the gate control signal and the enable signal respectively.
  • the pixel drive circuit P-Drive of the first row A driving current can be provided to the third sub-pixel to drive the third sub-pixel in the first row to perform light-emitting display.
  • the switch drive circuit MOA, the third drive circuit RST GOA, the first drive circuit Gate GOA and the second drive circuit EM GOA respectively repeat the above signal output process, lighting up the first sub-pixel and the second sub-pixel row by row and time-sharing. and the third subpixel.
  • the present disclosure can drive the present disclosure by increasing the operating frequency of the third drive circuit RST GOA, the first drive circuit Gate GOA and the second drive circuit EM GOA, and cooperating with the set switch drive circuit MOA to output corresponding switching signals.
  • the display panel performs luminous display, which realizes the normal luminous display of the display panel under the structure of improving the pixel PPI. It should be understood that in other embodiments, the display panel can also have other driving methods, and the display panel of the present disclosure can also be driven to display normally based on other driving methods.
  • FIG 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the switch driving circuit MOA may include a first sub-switch driving circuit MOAR, a second sub-switch driving circuit MOAG and a third sub-switch driving circuit.
  • each sub-switch driving circuit may include a plurality of cascaded third shift register units, and each third shift register unit may be disposed in the gap between two adjacent rows of pixels, whereby each third shift The register unit does not need to occupy additional space in the display area, and the PPI of the display panel can be improved by utilizing the existing space in the display area.
  • the display panel usually includes a third driving circuit RST GOA, a first driving circuit Gate GOA and a second driving circuit EM GOA.
  • Each driving circuit includes a plurality of cascaded shift register units. And the shift register units of each driving circuit are distributed between two adjacent rows of pixels.
  • a driving circuit only distributes one or several columns of shift register units, which is far less than the number of pixel columns in the display panel. Therefore, the gap between two adjacent rows of most columns is not used.
  • the present disclosure can use these existing unoccupied gaps between rows to place the shift registers at all levels in the switch driving circuit MOA, thereby eliminating the need to occupy additional display area space and improving the space utilization of the display area.
  • This structure is especially suitable for splicing screen display products, because splicing screen display products only have a display area.
  • This layout method can utilize the existing space, and the switch drive circuit MOA does not need to occupy other display space.
  • FIG. 5 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel may include two switch driving circuits MOA, and the two switch driving circuits MOA are provided separately. on both sides of the display area.
  • one switch driving circuit MOA is located on the left side of the display area, and another switch circuit MSW is located on the right side of the display area.
  • the advantage of this arrangement is that by setting the switch drive circuit MOA on both sides of the display area, the distance between a single switch drive circuit MOA and the remote switch unit connected to it can be reduced, thereby reducing the transmission line of the corresponding switch signal. line loss.
  • each switch driving circuit MOA has the structure described above, which will not be described in detail here.
  • three or more switch driving circuits MOA can also be provided, which all fall within the protection scope of the present disclosure.
  • the switch circuit MSW may not be driven in a time-sharing manner without the switch driving circuit MOA.
  • the driving integrated circuit DIC may output corresponding switching signals to control each switch unit in the switch circuit MSW to be turned on in a time-sharing manner.
  • FIG. 6 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in FIG. 6, the driving integrated circuit DIC can be disposed on one side of the display area along the column direction Y, and the driving integrated circuit DIC can pass through The signal line S outputs a switching signal to the switching circuit MSW.
  • the switch circuit MSW may include the first switch unit MUX1, the second switch unit MUX2, and the third switch unit MUX3.
  • the driver integrated circuit DIC may first switch all the first switch units in the display panel.
  • MUX1 provides a first switch signal to connect all first sub-pixels to the corresponding pixel drive circuit P-Drive.
  • the corresponding pixel drive current provides a drive current to the first sub-pixel to drive the first sub-pixel to perform light-emitting display; and then drives the integrated
  • the circuit DIC provides the second switching signal to all the second switching units MUX2 in the display panel, connects all the second sub-pixels to the corresponding pixel drive circuit P-Drive, and the corresponding pixel drive circuit P-Drive provides drive to the second sub-pixel current to drive the second sub-pixel to perform light-emitting display; finally, the driving integrated circuit DIC provides the third switching signal to all the third switching units MUX3 in the display panel, connecting all the third sub-pixels to the corresponding pixel driving circuit P-Drive.
  • the corresponding pixel drive circuit P-Drive provides a drive current to the third sub-pixel to drive the third sub-pixel to
  • Figure 7 is a driving timing diagram according to another embodiment of the present disclosure.
  • the driving integrated circuit DIC successively outputs a first switch signal, a second switch signal and a third switch signal.
  • the first switch signal is used to turn on all the first switch units MUX1 in the display panel to connect the first sub-pixel in each pixel unit with the pixel drive circuit P-Drive in the pixel unit ;
  • the second switch signal is used to turn on all the second switch units MUX2 in the display panel to connect the second sub-pixel in each pixel unit with the pixel drive circuit P-Drive of the pixel unit;
  • the third switch signal It is used to turn on all the third switch units MUX3 in the display panel to connect the third sub-pixel in each pixel unit with the pixel drive circuit P-Drive of the pixel unit.
  • the driving integrated circuit DIC first outputs the first switching signal.
  • the driving integrated circuit DIC outputs the first switching signal.
  • all the first sub-pixels in the display panel are connected to the corresponding pixel driving circuit P-.
  • the second drive circuit EM GOA, the third drive circuit RST GOA, and the first drive circuit Gate GOA in the display panel sequentially provide enable signals, reset signals, and gate control to the pixel drive circuit P-Drive.
  • each pixel drive circuit P-Drive provides a drive current to the first sub-pixel of this pixel unit, driving the first sub-pixel of this pixel unit to perform light-emitting display.
  • the driving integrated circuit DIC outputs the second switching signal.
  • the second switching unit MUX2 in each switching circuit MSW is turned on, and all the second sub-pixels in the display panel is connected to the corresponding pixel drive circuit P-Drive.
  • the second drive circuit EM GOA, the third drive circuit RST GOA and the first drive circuit Gate GOA respectively output the enable signal, reset signal and gate control signal in turn.
  • Each pixel drive The circuit P-Drive provides a driving current to the connected second sub-pixel to drive the second sub-pixel of the current pixel unit to perform light-emitting display.
  • the driving integrated circuit DIC outputs the third switching signal.
  • the third switching unit MUX3 in each switching circuit MSW is turned on, and all third sub-pixels in the display panel are connected to the corresponding pixel driving circuit P.
  • -Drive, the second drive circuit EM GOA, the third drive circuit RST GOA and the first drive circuit Gate GOA respectively output the enable signal, reset signal and gate control signal in sequence, and each pixel drive circuit P-Drive drives the connected third drive circuit P-Drive.
  • the three sub-pixels provide driving current to drive the third sub-pixel connected thereto to emit light and display.
  • the driving integrated circuit DIC outputs three switching signals in one frame time, and during each switching signal time, the corresponding sub-pixel is charged and displayed, so that the three sub-pixels are charged and displayed.
  • Pixel time-sharing display For example, the first sub-pixel is an R pixel, the second sub-pixel is a G pixel, and the third sub-pixel is a B pixel.
  • the driving integrated circuit DIC first controls the pixels in the display panel within one frame. All R pixels are displayed, then all G pixels are controlled to display, and finally all B pixels are controlled to display.
  • the second driving circuit EM GOA, the third driving circuit RST GOA and the first driving circuit Gate GOA can be disposed on both sides of the display area without occupying the space of the display area, and the switching signal is provided by the driving integrated circuit
  • the output of DIC and the driving integrated circuit DIC do not occupy the display space, so the pixel density of the display area can be further increased to achieve a higher PPI.
  • the duration of the first switch signal, the second switch signal and the third switch signal can be the same.
  • the driving integrated circuit DIC controls all the signals in the first 1/3 of the frame of data.
  • the first sub-pixel is displayed, all the second sub-pixels are controlled to display in the middle 1/3 of a frame of data, and all the third sub-pixels are controlled to display in the last 1/3 of a frame of data. Therefore, in one frame of data, the three sub-pixels have the same display duration.
  • This luminous display method can improve display uniformity, solve the display color cast problem, and improve the display effect.
  • the second drive circuit EM GOA, the third drive circuit RST GOA and the first drive circuit Gate GOA all need to output enable signals to the pixel drive circuit P-Drive in sequence.
  • Reset signal, gate control signal therefore, the frequency of the second driving circuit EM GOA, the third driving circuit RST GOA and the first driving circuit Gate GOA output driving signals is three times the frequency of the driving integrated circuit DIC output switching signal.
  • FIG. 8 is an equivalent circuit diagram of a pixel drive circuit according to an embodiment of the present disclosure.
  • the pixel drive circuit P-Drive may include a drive module 10, a first reset module 40, a transmission module 30, a data write module The input module 20, the second reset module 50, the first lighting control module 60, the second lighting control module 70, the storage module 80 and the adjustment module 90, wherein the driving module 10 is connected to the first node N1, the second node N2 and the third Node N3, the driving module 10 is used to provide a driving current by using the voltage difference between the second node N2 and the third node N3 in response to the voltage signal of the first node N1; the first reset module 40 is connected to the first node N1, the first reset signal terminal and The initial signal terminal, the first reset module 40 is used to respond to the reset signal of the first reset signal terminal and transmit the initial signal of the initial signal terminal to the first node N1; the transmission module 30 connects the first node N1, the gate signal terminal Gate and the second node N2, the transmission
  • the second lighting control module 70 is used to respond to the output signal of the adjustment module 90 to conduct the communication path between the fourth node N4 and the second node N2; the adjustment module 90 is connected to the data signal terminal Vdata, the second reset signal terminal RSTB, the first reset signal terminal RSTA, the initial signal terminal Vinit and the enable signal terminal EM.
  • the adjustment module 90 is used to close the second data signal in response to the first data signal of the data signal terminal Vdata.
  • the lighting control module 70 is configured to open the second lighting control module 70 in response to the second data signal at the data signal terminal Vdata.
  • each functional module in the pixel driving circuit P-Drive may be implemented by a transistor.
  • the driving module 10 may include a driving transistor M3.
  • the control terminal of the driving transistor M3 is connected to the first node N1, the first terminal of the driving transistor M3 is connected to the third node N3, and the second terminal of the driving transistor M3 is connected to the third node N3.
  • the terminal is connected to the second node N2.
  • the first reset module 40 may include a first transistor M1, a control terminal of the first transistor M1 is connected to the first reset signal terminal RSTA, a first terminal of the first transistor M1 is connected to the first node N1, and a second terminal of the first transistor M1 is connected to the first node N1.
  • the transmission module 30 may include a second transistor M2, a control terminal of the second transistor M2 is connected to the gate signal terminal Gate, a first terminal of the second transistor M2 is connected to the first node N1, and a second terminal of the second transistor M2 is connected to the second node. N2.
  • the data writing module 20 may include a fourth transistor M4, a gate of the fourth transistor M4 is connected to the gate signal terminal Gate, a first terminal of the fourth transistor M4 is connected to the data signal terminal Vdata, and a second terminal of the fourth transistor M4 is connected to the gate signal terminal Gate.
  • the second reset module 50 may include a seventh transistor M7. The control terminal of the seventh transistor M7 is connected to the first reset signal terminal RSTA.
  • the first terminal of the seventh transistor M7 is connected to the initial signal terminal Vinit.
  • the second terminal of the seventh transistor M7 is connected to the initial signal terminal Vinit.
  • the first lighting control module 60 may include a fifth transistor M5.
  • the control terminal of the fifth transistor M5 is connected to the enable signal terminal EM.
  • the first terminal of the fifth transistor M5 is connected to the first power supply terminal VDD.
  • the second terminal of the fifth transistor M5 is connected to the enable signal terminal EM.
  • the second lighting control module 70 may include a sixth transistor M6.
  • the control terminal of the sixth transistor M6 is connected to the output terminal of the adjustment module 90.
  • the first terminal of the sixth transistor M6 is connected to the second node N2.
  • the second terminal of the sixth transistor M6 is connected to the second node N2. Connect the fourth node N4.
  • the storage module 80 may include a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected to the first power terminal VDD, and a second electrode of the storage capacitor Cst is connected to the first node N1.
  • the storage capacitor Cst can be used to store the voltage signal written to the first node N1.
  • the adjustment module 90 may include an eighth transistor M8 , a ninth transistor M9 , a tenth transistor M10 and an eleventh transistor M11 and a first capacitor C1 and a second capacitor C2 , wherein the control of the eighth transistor M8 The terminal is connected to the second reset signal terminal RSTB, the first terminal of the eighth transistor M8 is connected to the data signal terminal Vdata, the second terminal of the eighth transistor M8 is connected to the fifth node N5, and the eighth transistor M8 can respond to the second reset signal terminal RSTB.
  • the reset signal transmits the data signal of the data signal terminal Vdata to the fifth node N5; the control terminal of the ninth transistor M9 is connected to the fifth node N5, the first terminal of the ninth transistor M9 is connected to the enable signal terminal EM, and the control terminal of the ninth transistor M9 is connected to the enable signal terminal EM.
  • the second terminal is connected to the control terminal of the sixth transistor M6, and the ninth transistor M9 can transmit the enable signal of the enable signal terminal EM to the control terminal of the sixth transistor M6 in response to the voltage signal of the fifth node N5.
  • the first electrode of the first capacitor C1 is connected to the initial signal terminal Vinit, and the second electrode of the first capacitor C1 is connected to the fifth node N5.
  • the initial signal output by the initial signal terminal Vinit can reset the first capacitor C1, and the first capacitor C1 can The voltage signal written to the fifth node N5 is stored.
  • the control terminal of the tenth transistor M10 is connected to the first reset signal terminal RSTA, the first terminal of the tenth transistor M10 is connected to the data signal terminal Vdata, the second terminal of the tenth transistor M10 is connected to the sixth node N6, and the tenth transistor M10 can respond to The reset signal of the first reset signal terminal RSTA transmits the data signal of the data signal terminal Vdata to the sixth node N6.
  • the control terminal of the eleventh transistor M11 is connected to the sixth node N6, the first terminal of the eleventh transistor M11 is connected to the high-frequency signal terminal HF, and the second terminal of the eleventh transistor M11 is connected to the control terminal of the sixth transistor M6.
  • a transistor M11 can transmit the voltage signal of the high-frequency signal terminal HF to the control terminal of the sixth transistor M6 in response to the voltage signal of the sixth node N6.
  • the first electrode of the second capacitor C2 is connected to the initial signal terminal Vinit, and the second electrode of the second capacitor C2 is connected to the sixth node N6.
  • the initial signal terminal Vinit can reset the second capacitor C2, and the second capacitor C2 can store and write The voltage signal of the sixth node N6.
  • the above-mentioned first to eleventh transistors M1 to M11 may be P-type transistors, for example, they may be P-type low-temperature polysilicon transistors.
  • the eighth to eleventh transistors M8 to M11 may also be N-type transistors, such as N-type oxide transistors.
  • Figure 9 is a timing diagram of each node in Figure 8 according to a driving method of the present disclosure.
  • the pixel drive circuit P-Drive can include a reset phase, a compensation phase and a light-emitting phase, where:
  • the second reset signal terminal RSTB outputs a low-level second reset signal to turn on the eighth transistor M8, and the low-level signal output by the data signal terminal Vdata is transmitted to the fifth node N5 and is passed by the first capacitor C1.
  • the ninth transistor M9 is turned on under the signal of the fifth node N5, writing the high-level signal of the enable signal terminal EM to the control terminal of the sixth transistor M6, and the sixth transistor M6 is turned off.
  • the first reset signal terminal RSTA outputs a first reset signal to respectively turn on the first transistor M1 and the seventh transistor M7, and the initial signal terminal Vinit outputs an initial signal to the first node N1 and the fourth node N4 as well as the first capacitor C1 and the second capacitor C1. Capacitor C2 resets. Thereafter, the ninth transistor M9 maintains the on state under the action of the low-level signal stored in the first capacitor C1, and the eleventh transistor M11 is turned off.
  • the gate signal terminal Gate outputs a low-level gate control signal to turn on the fourth transistor M4.
  • the fourth transistor M4 writes the data signal of the data signal terminal Vdata into the third node N3, and passes the driving transistor M3 The function is written into the gate of the driving transistor M3 to realize the threshold voltage compensation of the driving transistor M3.
  • the enable signal terminal EM outputs a low-level signal, turning on the fifth transistor M5, and the low-level signal output by the enable signal terminal EM is written into the gate of the sixth transistor M6 through the ninth transistor M9. pole, the sixth transistor M6 is controlled to be turned on.
  • the turned-on switch unit connects the first electrode P-AOD of the corresponding sub-pixel to the fourth node N4, thereby being driven to emit light.
  • Figure 10 is a timing diagram of each node in Figure 8 according to another driving method of the present disclosure. As shown in Figure 10, the driving method can also include a reset phase, a compensation phase and a lighting phase, where,
  • the second reset signal terminal RSTB outputs a low-level second reset signal to turn on the eighth transistor M8, the high-level signal output by the data signal terminal Vdata is transmitted to the fifth node N5, and the ninth transistor M9 is turned off.
  • the first reset signal terminal RSTA outputs a low-level first reset signal to turn on the tenth transistor M10, and the low-level data signal output by the data signal terminal Vdata is transmitted to the sixth node N6, and the eleventh transistor M11 It is turned on under the action of the low-level signal of the sixth node N6, and thereafter, under the action of the low-level signal stored in the second capacitor C2, the eleventh transistor M11 remains in the on-state, and the ninth transistor M9 is turned off.
  • the gate signal terminal Gate outputs a low-level gate control signal to turn on the fourth transistor M4.
  • the fourth transistor M4 writes the data signal written by the data signal terminal Vdata into the third node N3, and drives the The function of the transistor M3 is written into the first node N1 to realize threshold voltage compensation of the driving transistor M3.
  • the low-level signal output by the enable signal terminal EM turns on the fifth transistor M5, and the high-frequency signal terminal HF outputs a low-level signal, and is transmitted to the gate of the sixth transistor M6 through the eleventh transistor M11. , the sixth transistor M6 is turned on. At this time, the turned-on switch unit connects the first electrode P-AOD of the corresponding sub-pixel to the fourth node N4, thereby being driven to emit light.
  • Figure 11 is a structural layout according to an embodiment of the present disclosure.
  • Figure 12 is a structural layout of the first conductive layer in Figure 11.
  • Figure 13 is a structural layout of the active layer in Figure 11.
  • Figure 14 is a second conductive layer in Figure 11.
  • Figure 15 is the structural layout of the third conductive layer in Figure 11, and
  • Figure 16 is the structural layout of the fourth conductive layer in Figure 11.
  • the first conductive layer 1 may include a first conductive part 101 , a second conductive part 102 , and a third conductive part 103 .
  • the portion 102 and the third conductive portion 103 are respectively used to form the first electrode of the first capacitor C1, the first electrode of the second capacitor C2, and the first electrode of the storage capacitor Cst.
  • the first conductive layer 1 may further include a fourth conductive part 104 and a fifth conductive part 105, and the fourth conductive part 104 is used to form the bottom gate of the driving transistor M3.
  • the fifth conductive part 105 is connected to one end of the fourth conductive part 104 , and the fifth conductive part 105 is also connected to the third transfer part 403 of the third conductive layer 4 through a via hole, so that the driving transistor is connected through the third transfer part 403
  • the gate of M3 is connected to the first node N1.
  • the first conductive layer 1 may also include a sixth conductive part 106 and a seventh conductive part 107.
  • the sixth conductive part 106 and the seventh conductive part 107 are connected to both sides of the third conductive part 103 along the row direction
  • the six conductive parts 106 may be connected to the seventh conductive part 107 in the adjacent pixel unit, and the seventh conductive part 107 may be connected to the sixth conductive part 106 in the adjacent pixel unit, because the third conductive part 103 is connected to the first power line VDD is connected, so that the first power line VDD and the third conductive part 103, the sixth conductive part 106, and the seventh conductive part 107 can form a grid structure.
  • the power line of the grid structure can reduce the voltage drop of the power signal thereon.
  • the active layer 2 may include first to fourteenth active portions 21 to 270 and first to twenty-eighth sub-active portions 201 to 28th sub-active portions.
  • the two ends of the first transistor M1 form the first end and the second end of the first transistor M1 respectively.
  • the second sub-active part 202 is also connected to the seventh active part 27 to form the first end of the seventh transistor M7.
  • the second The sub-active part 202 may be connected to the second transfer part 402 of the third conductive layer 4 through a via hole, so as to connect the second end of the first transistor M1 and the first end of the seventh transistor M7 through the second transfer part 402 to the initial signal line Vinit.
  • the second active part 22 is used to form the channel region of the second transistor M2.
  • the third sub-active part 203 and the fourth sub-active part 204 are connected to both sides of the second active part 22 to form the second transistor respectively.
  • the first end and the second end of M2, the third sub-active part 203 can be connected to the third transfer part 403 of the third conductive layer through a via hole, so as to connect the first end of the second transistor M2 through the third transfer part 403.
  • the terminal is connected to the first node N1, and the fourth sub-active part 204 can be connected to the fourth transfer part 404 of the third conductive layer through a via hole, so as to connect the second terminal of the second transistor M2 through the fourth transfer part 404. Connected to the second terminal of drive transistor M3.
  • the third active part 23 is used to form the channel region of the driving transistor M3.
  • the fifth sub-active part 205 and the sixth sub-active part 206 are connected to both sides of the third active part 23 to respectively form the channel region of the driving transistor M3.
  • the first end and the second end, the fifth sub-active part 205 can be connected to the fifth switching part 405 located on the third conductive layer 4 through a via hole, so as to connect the first end of the driving transistor M3 to the third node N3.
  • the sixth sub-active part 206 may be connected to the fourth transfer part 404 through a via hole, so as to connect the second end of the driving transistor M3 to the second node N2, that is, to connect the second end of the second transistor M2.
  • the fourth active part 24 is used to form the channel region of the fourth transistor M4.
  • the seventh sub-active part 207 and the eighth sub-active part 208 are connected to both sides of the fourth active part 24 to form the fourth transistor respectively.
  • the first end and the second end of M4, the seventh sub-active part 207 can be connected to the data signal line Data through a via hole to connect the first end of the fourth transistor M4 to the data signal terminal Vdata, and the eighth sub-active part 208 can be
  • the fifth transfer portion 405 located on the third conductive layer 4 is connected through a via hole, so that the second end of the fourth transistor M4 is connected to the third node N3 through the fifth transfer portion 405 .
  • the fifth active part 25 is used to form the channel region of the fifth transistor M5.
  • the ninth sub-active part 209 and the tenth sub-active part 210 are respectively connected to both ends of the fifth active part 25 to form the fifth transistor.
  • the first end and the second end of M5, the ninth sub-active part 209 can be connected to the seventeenth conductive block 417 through a via hole (specifically, the sub-conductive part of the seventeenth conductive block 417 can be connected), so as to connect the fifth transistor M5
  • the first end of the transistor M5 is connected to the first power supply terminal VDD, and the tenth sub-active part 210 can be connected to the fifth switching part 405 through a via hole to connect the second end of the fifth transistor M5 to the third node N3.
  • the sixth active part 26 is used to form the channel region of the sixth transistor M6.
  • the eleventh sub-active part 211 and the twelfth sub-active part 212 are connected to both ends of the sixth active part 26 to respectively form the first sub-active part 211 and the twelfth sub-active part 212.
  • the first end and the second end of the six transistor M6, the eleventh sub-active part 211 can be connected to the fourth adapter part 404 through the via hole to connect the first end of the sixth transistor M6 to the second node N2, the twelfth node N2
  • the sub-active part 212 may be connected to the sixth switching part 406 through a via hole to connect the second end of the sixth transistor M6 to the fourth node N4.
  • the seventh active part 27 is used to form the channel region of the seventh transistor M7.
  • the second sub-active part 202 and the fourteenth sub-active part 214 are connected to both sides of the seventh active part 27 to form the seventh transistor.
  • the first end and the second end of M7, the second sub-active part 202 can be connected to the second transfer part 402 through the via hole, so that the first end of the seventh transistor M7 is connected to the initial connection part through the second transfer part 402.
  • the signal terminal Vinit, the fourteenth sub-active part 214 may be connected to the sixth switching part 406 through a via hole, so as to connect the second end of the seventh transistor M7 to the fourth node N4 through the sixth switching part 406.
  • the eighth active part 28 is used to form the channel region of the eighth transistor M8.
  • the fifteenth sub-active part 215 and the sixteenth sub-active part 216 are connected to both ends of the eighth active part 28 to respectively form a third active part 28.
  • the first end and the second end of the eight transistor M8, the fifteenth sub-active part 215 can be connected to the data signal line Data through a via hole to connect the first end of the eighth transistor M8 to the data signal terminal Vdata, and the sixteenth sub-active part 215 has
  • the source part 216 may be connected to the seventh adapter part 407 through a via hole, and the seventh adapter part 407 may be connected to the first electrode of the first capacitor C1.
  • the ninth active part 29 is used to form the channel region of the ninth transistor M9.
  • the seventeenth sub-active part 217 and the eighteenth sub-active part 218 are connected to both sides of the ninth active part 29 to respectively form a third active part 29.
  • the first end and the second end of the nine-transistor M9, the seventeenth sub-active part 217 can be connected to the tenth conductive block 310 through the via hole, (the tenth conductive block 310 is connected to the eighth switching part 408 through the via hole), so as to
  • the first end of the ninth transistor M9 is connected to the enable signal terminal EM through the tenth conductive block 310
  • the eighteenth sub-active part 218 can be connected to the ninth transfer part 409 through a via hole, so as to pass through the ninth transfer part 409 connects the second terminal of the ninth transistor M9 to the gate of the sixth transistor M6.
  • the tenth active part 230 is used to form the channel region of the tenth transistor M10.
  • the nineteenth sub-active part 219 and the twentieth sub-active part 220 are connected to both sides of the tenth active part 230 to respectively form the tenth active part 230.
  • the first terminal and the second terminal of the tenth transistor M10, the nineteenth sub-active part 219 can be connected to the data signal line Data through a via hole, so as to connect the first terminal of the tenth transistor M10 to the data signal terminal Vdata.
  • the twentieth sub-active part 220 can be connected to the eleventh transfer part 411 through a via hole.
  • the eleventh transfer part 411 can be connected to the ninth conductive block 39 through the via hole.
  • the ninth conductive block 39 is also connected to the ninth conductive block 39 through the via hole.
  • the twelfth transfer part 412 is connected through a via hole, and the other end of the twelfth transfer part 412 is connected to the second conductive block 32 (the second electrode of the second capacitor C2) through the via hole, thereby connecting the tenth transistor M10
  • the second terminal is connected to the second electrode of the second capacitor C2.
  • the eleventh active part 240 is used to form the channel region of the eleventh transistor M11.
  • the twenty-first sub-active part 221 and the twenty-second sub-active part 222 are connected to both sides of the eleventh active part 240.
  • the twenty-first sub-active part 221 can be connected to the sixteenth transfer part 416 through the via hole, and the sixteenth transfer part 416 passes through the seventh
  • the conductive block 37 is connected to the second high-frequency signal line HF2, and further connects the first end of the eleventh transistor M11 to the high-frequency signal terminal HF.
  • the twenty-second sub-active part 222 may be connected to the ninth transfer part 409 through a via hole, and the ninth transfer part 409 connects the second end of the eleventh transistor M11 to the gate of the sixth transistor M6.
  • the twelfth active part 250 is used to form the channel region of the twelfth transistor M12.
  • the twenty-third sub-active part 223 and the twenty-fourth sub-active part 224 are connected to both sides of the twelfth active part 250.
  • the twenty-third sub-active part 223 can be connected to the sixth transfer part 406 through the via hole, so as to connect the tenth transistor M12 through the sixth transfer part 406.
  • the first terminal of the two transistors M12 is connected to the fourth node N4.
  • the twenty-fourth sub-active part 224 may be connected to the thirteenth transfer part 413 through a via hole, so as to connect the second end of the twelfth transistor M12 to the first end of the first sub-pixel through the thirteenth transfer part 413. electrode.
  • the thirteenth active part 260 is used to form the channel region of the thirteenth transistor M13.
  • the twenty-fifth sub-active part 225 and the twenty-sixth sub-active part 226 are connected to both sides of the thirteenth active part 260.
  • the twenty-fifth sub-active part 225 can be connected to the sixth transfer part 406 through the via hole, so as to connect the tenth transistor M13 through the sixth transfer part 406.
  • the first terminal of the three transistor M13 is connected to the fourth node N4.
  • the twenty-sixth sub-active part 226 may be connected to the fourteenth transfer part 414 through a via hole, so as to connect the second end of the thirteenth transistor M13 to the first end of the second sub-pixel through the fourteenth transfer part 414. electrode.
  • the fourteenth active part 270 is used to form the channel region of the fourteenth transistor M14.
  • the twenty-seventh sub-active part 227 and the twenty-eighth sub-active part 228 are connected to both sides of the fourteenth active part 270.
  • the twenty-seventh sub-active part 227 can be connected to the sixth transfer part 406 through the via hole, so as to connect the sixth transfer part 406 through the sixth transfer part 406
  • the first terminal of the fourteenth transistor M14 is connected to the fourth node N4.
  • the twenty-eighth sub-active part 228 may be connected to the fifteenth transfer part 415 through a via hole, so as to connect the second end of the fourteenth transistor M14 to the third sub-pixel through the fifteenth transfer part 415.
  • the active layer 2 of the present disclosure may be formed of polysilicon semiconductor material.
  • the transistors in the display panel of the present disclosure may be P-type low-temperature polysilicon thin film transistors.
  • the second conductive layer 3 may include a first conductive block 31 , a second conductive block 32 , and a third conductive block 33 .
  • the first conductive block 31 is on the base substrate.
  • the orthographic projection of is located on the orthographic projection of the first conductive part 101 on the base substrate, and the first conductive block 31 is used to form the second electrode of the first capacitor C1.
  • the orthographic projection of the second conductive block 32 on the base substrate is located on the orthographic projection of the second conductive part 102 on the base substrate.
  • the second conductive block 32 is used to form the second electrode of the second capacitor C2.
  • the third conductive block 33 may include a first component 331, a second component 332 and a third component 333.
  • the orthographic projection of the first component 331 on the base substrate is located at the orthographic projection of the third conductive part 103 on the base substrate.
  • the first component part 331 of the third conductive block 33 is used to form the second electrode of the storage capacitor Cst.
  • the second component part 332 of the third conductive block 33 extends along the column direction Y in the orthographic projection of the base substrate.
  • the third component part 333 of the third conductive block 33 extends in the row direction X in the orthographic projection of the base substrate.
  • the second component part 332 of the conductive block 33 is connected between the first component part 331 and the third component part 333 , and the third component part 333 of the third conductive block 33 covers the third active part 23 in the orthographic projection of the base substrate.
  • part of the structure of the third component part 333 of the third conductive block 33 is used to form the gate of the driving transistor M3.
  • the second conductive layer 3 may also include fourth conductive blocks 34 to seventh conductive blocks 37 .
  • the fourth conductive block 34 covers the third conductive block 34 in the orthographic projection of the substrate.
  • the ninth active portion 29 is in the orthographic projection of the base substrate, and a partial structure of the fourth conductive block 34 is used to form the gate of the ninth transistor M9.
  • the fourth conductive block 34 is connected to the seventh transfer portion 407 through a via hole to connect the gate of the ninth transistor M9 to the second electrode of the first capacitor C1 through the seventh transfer portion 407 .
  • the orthographic projection of the fifth conductive block 35 on the base substrate may extend along the row direction X.
  • the fifth conductive block 35 is connected to the ninth transfer part 409 and the tenth transfer part 410 through via holes respectively.
  • the eighteenth sub-active part 218 (the second end of the ninth transistor M9) and the twenty-second sub-active part 222 (the second end of the eleventh transistor M11) and the tenth transfer part are connected through via holes.
  • 410 is connected to the sixth conductive block 36 (forming the gate of the sixth transistor M6) through a via hole, so that the second end of the ninth transistor M9 and the eleventh transistor M6 are connected through the ninth transfer part 409 and the tenth transfer part 410.
  • the second terminal of the transistor M11 is connected to the gate of the sixth transistor M6.
  • the sixth conductive block 36 may include a first sub-conductive block 361 and a plurality of second sub-conductive blocks 362.
  • the orthographic projection of the first sub-conductive block 361 on the substrate may extend along the column direction Y, and the second sub-conductive block 362 may extend along the column direction Y.
  • the orthographic projection of the base substrate may extend along the row direction In the orthographic projection of the six active portions 26 on the base substrate, the second sub-conductive block 362 can be used to form the gate of the sixth transistor M6.
  • the orthographic projection of the seventh conductive block 37 on the base substrate may extend along the row direction
  • the adapter 416 connects the first end of the eleventh transistor M11 to the high-frequency signal terminal HF.
  • the second conductive layer 3 may also include a first high-frequency signal line HF1, a third power line VSS2, a second power line VSS1, an initial signal line Vinit, a third The second reset signal line RSTB, the first reset signal line RSTA, the first power line VDD, the enable signal line EM and the gate signal line Gate, the first high-frequency signal line HF1, the third power line VSS2, and the second power line VSS1 , the orthographic projections of the initial signal line Vinit, the second reset signal line RSTB, the first reset signal line RSTA, the first power supply line VDD, the enable signal line EM and the gate signal line Gate on the substrate all extend along the row direction X And are distributed at intervals in the column direction Y, where the first high-frequency signal line HF1, the third power line VSS2 and the second power line VSS1 are located on the side of the first conductive block 31 away from the third conductive block 33.
  • the signal line HF1 is used to form the high-frequency signal terminal HF in FIG. 8 .
  • the first high-frequency signal line HF1 can be connected to the second high-frequency signal line HF2 of the third conductive layer 4 through a via hole.
  • the third power supply line VSS2 is used to form the second power terminal of the second sub-pixel and the second power terminal of the third sub-pixel in Figure 8.
  • the second power line VSS1 is used to form the second power terminal of the first sub-pixel in Figure 8. power supply terminal.
  • the initial signal line Vinit, the second reset signal line RSTB, the first reset signal line RSTA, the first power supply line VDD, and the enable signal line EM are located in the first conductive block 31 and between the third conductive blocks 33.
  • the initial signal line Vinit is used to form the initial signal terminal Vinit in Figure 8.
  • the initial signal line Vinit is connected to the second transfer part 402, the eighteenth conductive block 418 and the nineteenth conductive block of the third conductive layer 4 through via holes respectively. 419.
  • the second reset signal line RSTB is used to form the second reset signal terminal RSTB in FIG. 8 .
  • the second reset signal line RSTB covers the orthographic projection of the eighth active part 28 on the substrate.
  • Part of the structure of the two reset signal lines RSTB is used to form the gate of the eighth transistor M8.
  • the first reset signal line RSTA is used to form the first reset signal terminal RSTA in FIG. 8.
  • the first reset signal line RSTA covers the front projection part of the substrate substrate of the first active part 21 on the substrate substrate. Covering the orthographic projection of the seventh active part 27 on the base substrate and partially covering the orthographic projection of the tenth active part 230 on the base substrate, part of the structure of the first reset signal line RSTA is used to form the gate of the first transistor M1 , part of the structure is used to form the gate of the seventh transistor M7, and part of the structure is used to form the gate of the tenth transistor M10.
  • the first power line VDD is used to form the first power terminal VDD in FIG. 8.
  • the first power line VDD is connected to the seventeenth conductive block 417 of the third conductive layer 4 through a via hole to connect the first electrode of the storage capacitor Cst. to the first power terminal VDD.
  • the enable signal line EM is used to form the enable signal terminal EM in Figure 8.
  • the enable signal line EM includes a main body part EM0, a first sub-extension part EM1 and a plurality of second sub-extension parts EM2.
  • the enable signal line EM The main part EM0 and the second sub-extension part EM2 extend along the row direction X in the orthographic projection of the base substrate, and the first sub-extension part EM1 of the enable signal line EM extends in the column direction Y in the orthographic projection of the base substrate.
  • the second sub-extension part EM2 is connected to the main body part EM0 through the first sub-extension part EM1.
  • the plurality of second sub-extension parts EM2 are arranged in one-to-one correspondence with the plurality of fifth active parts 25 and the second sub-extension part EM2 is on the base substrate.
  • the orthographic projection covers the orthographic projection of the fifth active part 25 on the base substrate, and the second sub-extension part EM2 is used to form the gate of the fifth transistor M5.
  • the gate signal line Gate is located on the side of the twentieth conductive block 500 away from the first conductive block 31.
  • the gate signal line Gate is used to form the gate signal terminal Gate in FIG. 8.
  • the gate signal line Gate is on the base substrate.
  • the front projection partially covers the front projection of the second active part 22 on the base substrate, and partially covers the front projection of the fourth active part 24 on the base substrate. Part of the structure of the gate signal line Gate is used to form the second transistor M2
  • the gate electrode and part of the structure are used to form the gate electrode of the fourth transistor M4.
  • the second conductive layer 3 may also include a ninth conductive block 39 and a tenth conductive block 310 .
  • the ninth conductive block 39 covers the third conductive block 39 in the orthographic projection of the substrate. In the orthographic projection of the eleventh active part 240 on the base substrate, part of the structure of the ninth conductive block 39 is used to form the gate of the eleventh transistor M11.
  • the ninth conductive block 39 is also connected to the eleventh transfer part 411 and the twelfth transfer part 412 through via holes respectively (the twelfth transfer part 412 is also connected to the second conductive block 32), thereby connecting the eleventh transistor M11
  • the gate electrode and the second terminal of the tenth transistor M10 are respectively connected to the second electrode of the second capacitor C2.
  • the tenth conductive block 310 is respectively connected to the seventeenth sub-active part 217 and the eighth switching part 408 through via holes to connect the first end of the ninth transistor M9 to the enable signal terminal EM.
  • the second conductive layer 3 may also include a plurality of twelfth conductive blocks 312 , a plurality of thirteenth conductive blocks 313 and a plurality of fourteenth conductive blocks 314 , the plurality of twelfth conductive blocks 312 are arranged in one-to-one correspondence with the plurality of twelfth active portions 250 , and the orthographic projection of the twelfth active portion 250 on the base substrate covers the twelfth active portion 250 on the base substrate In the orthographic projection, the twelfth active part 250 is used to form the gate of the twelfth transistor M12.
  • the plurality of thirteenth conductive blocks 313 are arranged in one-to-one correspondence with the plurality of thirteenth active portions 260.
  • the front projection of the thirteenth conductive blocks 313 on the base substrate covers the front projection of the thirteenth active portions 260 on the base substrate. Projection, the thirteenth conductive block 313 is used to form the gate of the thirteenth transistor M13.
  • the plurality of fourteenth conductive blocks 314 are arranged in one-to-one correspondence with the plurality of fourteenth active portions 270.
  • the front projection of the fourteenth conductive blocks 314 on the base substrate covers the front projection of the fourteenth active portions 270 on the base substrate. Projection, the fourteenth conductive block 314 is used to form the gate of the fourteenth transistor M14.
  • the display panel of the present disclosure can use the second conductive layer 3 as a mask to conduct conduction processing on the active layer 2, that is, the active layer 2 covered by the second conductive layer 3 forms the channel region of the transistor, and the active layer 2 covered by the second conductive layer 3 does not The area covered by 3 forms a conductive structure.
  • a described in this disclosure extends along direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, and the main part extends along direction B.
  • the length of the main part extending along direction B is greater than the length of the minor part extending along other directions.
  • the third conductive layer 4 may include first to sixteenth adapter portions 401 to 416 , wherein one end of the first adapter portion 401 passes through The hole is connected to the first sub-active part 201 to connect the first end of the first transistor M1, and the other end of the first transfer part 401 is connected to the third conductive block 33 of the second conductive layer 3 through the via hole.
  • the adapter 401 connects the first terminal of the first transistor M1 to the second electrode of the storage capacitor Cst.
  • One end of the second transfer part 402 is connected to the second sub-active part 202 through a via hole to connect the second end of the first transistor M1 and the first end of the seventh transistor M7 .
  • the other end of the second transfer part 402 is connected to the second sub-active part 202 through a via hole.
  • the hole is connected to the initial signal line Vinit of the second conductive layer 3 to connect the second terminal of the first transistor M1 and the first terminal of the seventh transistor M7 to the initial signal terminal Vinit through the second adapter 402 .
  • One end of the third transfer part 403 is connected to the third sub-active part 203 through a via hole to connect the first end of the second transistor M2, and the other end of the third transfer part 403 is connected to the third conductive block 33 (specifically, The third component 333) of the third conductive block 33 can be connected to connect the first end of the second transistor M2 to the second electrode of the storage capacitor Cst through the third adapter 403, that is, the first terminal in FIG. 8 Node N1.
  • the fourth transfer part 404 is respectively connected to the fourth sub-active part 204, the sixth sub-active part 206, and the eleventh sub-active part 211 through via holes to connect the second end of the second transistor M2 and the driving transistor respectively. the second terminal of M3 and the first terminal of the sixth transistor M6.
  • the fifth transfer part 405 may be connected to the fifth sub-active part 205 and the eighth sub-active part 208 through via holes, respectively, to respectively connect the first sub-active part of the driving transistor M3 terminal and the second terminal of the fourth transistor M4, the fifth transfer part 405 is also connected to the tenth sub-active part 210 through a via hole, so as to connect the first terminal of the driving transistor M3, the second terminal of the fourth transistor M4 and the fifth terminal of the fourth transistor M4.
  • the second terminal of the transistor M5 is connected to the third node N3.
  • the sixth transfer portion 406 can be used to form the fourth node N4 in FIG. 8 .
  • the partial structure of the sixth transfer portion 406 covers the orthographic projection of the twelfth sub-active portion 212 on the base substrate.
  • the orthographic projection of part of the structure on the base substrate covers the twenty-third sub-active part 223 on the base substrate
  • the orthographic projection of part of the structure on the base substrate covers the twenty-fifth sub-active part 225 on the substrate
  • the orthographic projection of the substrate and the orthographic projection of some structures on the substrate cover the orthographic projection of the twenty-seventh sub-active part 227 on the substrate.
  • the sixth adapter part 406 can be connected to the twelfth sub-active part through via holes respectively.
  • the seventh transfer part 407 can be connected to the first conductive block 31, the sixteenth sub-active part 216 and the fourth conductive block 34 respectively through via holes to connect the second end of the eighth transistor M8 and the gate of the ninth transistor M9.
  • the poles are respectively connected to the second electrodes of the first capacitor C1.
  • the eighth transfer part 408 connects the seventeenth sub-active part 217 and the enable signal line EM through via holes respectively, so that the first end of the ninth transistor M9 is connected to the enable signal terminal EM through the eighth transfer part 408 .
  • one end of the ninth transfer part 409 is connected to the fifth conductive block 35 through via holes, and the other end is connected to the eighteenth sub-active part 218 and the twentieth sub-active part 218 through via holes respectively.
  • the second sub-active part 222 is used to connect the second terminal of the ninth transistor M9 and the second terminal of the eleventh transistor M11 to the gate of the sixth transistor M6.
  • the tenth transfer part 410 may connect the sixth conductive block 36 (forming the gate of the sixth transistor M6) and the fifth conductive block 35 through a via hole.
  • the eleventh transfer part 411 is connected to the twentieth sub-active part 220 and the ninth conductive block 39 respectively through via holes, and the twelfth transfer part 412 is connected to the ninth conductive block 39 and the second conductive block 32 respectively through via holes. Therefore, the second terminal of the tenth transistor M10 and the gate electrode of the eleventh transistor M11 are connected to the second electrode of the second capacitor C2.
  • the thirteenth transfer part 413 connects the twenty-fourth sub-active part 224 and the first electrode P-AOD of the first sub-pixel through a via hole to connect the tenth
  • the second terminal of the two transistors M12 is connected to the first electrode P-AOD of the first sub-pixel.
  • the fourteenth transfer part 414 is connected to the twenty-sixth sub-active part 226 through a via hole to connect the second end of the thirteenth transistor M13 to the first electrode P-AOD of the second sub-pixel.
  • the fifteenth transfer part 415 may be connected to the twenty-eighth sub-active part 228 through a via hole to connect the second end of the fourteenth transistor M14 to the first electrode P-AOD of the third sub-pixel.
  • the sixteenth transfer part 416 is connected to the twenty-first sub-active part 221 and the seventh conductive block 37 through via holes respectively (the seventh conductive block 37 is connected to the second high conductive block 37 ).
  • frequency signal line HF2 frequency signal line
  • the third conductive layer 4 may also include seventeenth conductive blocks 417 to 19 conductive blocks 419 , wherein the seventeenth conductive block 417 may include a main conductive block 417 .
  • the main conductive part 4171 and the sub-conductive part 4172, the orthographic projection of the main conductive part 4171 on the base substrate is located on the orthographic projection of the third conductive part 103 on the base substrate, and the main conductive part 4171 can be connected to the third conductive part 103 through a via hole.
  • the seventeen conductive blocks 417 and the third conductive portion 103 are respectively used to form the first electrode of the storage capacitor Cst.
  • the sub-conductive part 4172 of the seventeenth conductive block 417 is connected to the ninth sub-active part 209 through a via hole to connect the first end of the fifth transistor M5.
  • the orthographic projection of the eighteenth conductive block 418 on the base substrate is located on the orthographic projection of the first conductive part 101 on the base substrate.
  • the eighteenth conductive block 418 is connected to the first conductive part 101 through a via hole.
  • the eighteenth conductive block 418 and the first conductive part 101 are used to form the first electrode of the first capacitor C1.
  • the orthographic projection of the nineteenth conductive block 419 on the base substrate is located on the orthographic projection of the second conductive part 102 on the base substrate.
  • the nineteenth conductive block 419 is connected to the second conductive part 102 through a via hole.
  • the nineteenth conductive block 419 and the second conductive part 102 are used to form the first electrode of the second capacitor C2. It can be understood that by arranging the seventeenth conductive block 417 on the third conductive layer 4 to connect the third conductive part 103 of the first conductive layer 1 to form a parallel structure with the first conductive part 101 , the amount of memory formed can be reduced.
  • the resistance of the first electrode of the capacitor Cst helps to reduce the voltage drop loss on the storage capacitor Cst.
  • the eighteenth conductive block 418 on the third conductive layer 4 to form a parallel structure with the first conductive part 101, the voltage drop loss on the first electrode of the first capacitor C1 can be reduced.
  • the conductive block 419 and the second conductive part 102 form a parallel structure, which can reduce the voltage drop loss on the first electrode of the second capacitor C2.
  • the third conductive layer 4 may also include a data signal line Data.
  • the data signal line Data may be used to form the data signal terminal Vdata in FIG. 8 .
  • the data signal line Data is on the substrate.
  • the orthographic projection of the base substrate extends along the column direction Y, and the data signal line Data can be connected to the seventh sub-active part 207, the fifteenth sub-active part 215 and the nineteenth sub-active part 219 through via holes respectively, so as to respectively connect the The first terminal of the fourth transistor M4, the first terminal of the eighth transistor M8, and the first terminal of the tenth transistor M10 are connected to the data signal terminal Vdata.
  • the fourth conductive layer 5 may include twentieth conductive blocks 500 to twenty-fifth conductive blocks 505 , wherein the twentieth conductive block 500 is used to form the second conductive block 500 .
  • the first electrode P-AOD of a sub-pixel, the twentieth conductive block 500 can be connected to the thirteenth transfer part 413 through a via hole, so as to connect the first electrode P-AOD of the first sub-pixel through the thirteenth transfer part 413 AOD is connected to the second terminal of the twelfth transistor M12.
  • the twenty-first conductive block 501 is used to form the first electrode P-AOD of the second sub-pixel.
  • the twenty-first conductive block 501 can be connected to the fourteenth transfer part 414 through a via hole, so as to pass through the fourteenth transfer part 414 connects the first electrode P-AOD of the second sub-pixel to the second terminal of the thirteenth transistor M13.
  • the twenty-second conductive block 502 is used to form the first electrode P-AOD of the third sub-pixel.
  • the twenty-second conductive block 502 can be connected to the fifteenth transfer part 415 through a via hole to pass the fifteenth transfer part. Part 415 connects the first electrode P-AOD of the third sub-pixel to the second terminal of the fourteenth transistor M14.
  • the twenty-third conductive block 503 is used to form the second electrode P-CTO of the first sub-pixel.
  • the twenty-third conductive block 503 can be connected to the second power line VSS1 of the second conductive layer 3 through a via hole to connect the first
  • the second electrode P-CTO of the sub-pixel is connected to the corresponding second power terminal.
  • the twenty-fourth conductive block 504 is used to form the second electrode P-CTO of the second sub-pixel.
  • the twenty-fifth conductive block 505 is used to form the second electrode P-CTO of the third sub-pixel.
  • the twenty-fifth conductive block 505 can be connected to the third power line VSS2 of the second conductive layer 3 through via holes respectively, so as to connect the second electrode P-CTO of the second sub-pixel and the second electrode P of the third sub-pixel. -CTO is connected to the corresponding second power terminal.
  • the layout structure forming the pixel drive circuit P-Drive is located in the orthographic projection of the base substrate and the first electrode P-AOD of the sub-pixel is in the orthogonal projection of the base substrate.
  • the second electrode P-CTO is projected away from the front projection side of the base substrate, and the layout structure forming the switching circuit MSW is located in the front projection of the base substrate.
  • the first electrode P-AOD of the sub-pixel is on the front side of the base substrate.
  • the projection and the second electrode P-CTO of the sub-pixel are between the front projection of the base substrate.
  • the pixel drive circuit P-Drive, the switch circuit MSW, and the first electrode and the second electrode of the sub-pixel in the pixel unit may also have other layout structures, for example, the layout structure forming the switch circuit MSW. It can be located below the first electrode and the second electrode of the sub-pixel, that is, the orthographic projection of the layout structure forming the switch circuit MSW on the substrate can intersect with the orthographic projection of the first electrode and the second electrode of the sub-pixel on the substrate. Stack, these all belong to the protection scope of the present disclosure and will not be described in detail here.
  • Figure 17 is a partial cross-sectional view along the dotted line AA in Figure 11.
  • the display panel may include a first insulating layer 81, a second insulating layer 82, a third insulating layer 83, an interlayer dielectric layer ILD, and a third insulating layer 83.
  • insulating layers 84 the first planar layer PLN1, the first passivation layer PVX1, the second planar layer PLN2 and the second passivation layer PVX2, wherein the base substrate 80, the first insulating layer 81, the first conductive layer 1, The second insulating layer 82, the active layer 2, the third insulating layer 83, the second conductive layer 3, the interlayer dielectric layer ILD, the fourth insulating layer 84, the third conductive layer 4, the first planarization layer PLN1, the first The passivation layer PVX1, the fourth conductive layer 5, the second planarization layer PLN2, and the second passivation layer PVX2 are stacked in sequence.
  • the first insulating layer 81 and the second insulating layer 82 may be silicon oxide layers, and the first dielectric layer 86 may be a silicon nitride layer.
  • the base substrate may include a glass substrate, a barrier layer, and a polyimide layer that are stacked in sequence.
  • the barrier layer may be an inorganic material.
  • the material of the first conductive layer 1 and the second conductive layer 3 may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate.
  • the material of the third conductive layer 4 and the fourth conductive layer 5 may include metal materials, for example, it may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or laminate, or it may be titanium /aluminum/titanium laminate.
  • the present disclosure also provides a display device, which may include the display panel described in any embodiment of the present disclosure.

Abstract

本公开提供一种显示面板及显示装置。该显示面板包括沿行列方向阵列分布的多个像素单元，所述像素单元包括：像素驱动电路(P-Drive)、多个子像素、开关电路(MSW)，像素驱动电路(P-Drive)用于提供驱动电流；所述子像素的第一电极(P-AOD)用于连接所述像素驱动电路(P-Drive)，所述子像素的第二电极(P-CTO)连接第二电源端，所述子像素在所述驱动电流的作用下发光；开关电路(MSW)包括多个开关单元，所述开关单元与所述子像素对应设置，所述开关单元串接于所述像素驱动电路(P-Drive)与对应子像素之间，所述开关单元的控制端用于接收开关信号，所述开关单元的第一端连接所述像素驱动电路(P-Drive)，所述开关单元的第二端连接对应子像素的第一电极(P-AOD)，所述开关单元响应于所述开关信号导通所述子像素与所述像素驱动电路(P-Drive)的连通路径。 (图11)

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
当前LED显示在户外和中控大屏显示上得到广泛应用。目前LED的应用主要是远距离观看，像素Pitch相对较大，PPI较低。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及显示装置。
根据本公开的一个方面，提供一种显示面板，包括沿行列方向阵列分布的多个像素单元，所述像素单元包括：像素驱动电路，用于提供驱动电流；多个子像素，所述子像素的第一电极用于连接所述像素驱动电路，所述子像素的第二电极连接第二电源端，所述子像素在所述驱动电流的作用下发光；开关电路，包括多个开关单元，所述开关单元与所述子像素对应设置，所述开关单元串接于所述像素驱动电路与对应子像素之间，所述开关单元的控制端用于接收开关信号，所述开关单元的第一端连接所述像素驱动电路，所述开关单元的第二端连接对应子像素的第一电极，所述开关单元响应于所述开关信号导通所述子像素与所述像素驱动电路的连通路径。
在本公开的一示例性实施例中，所述显示面板包括衬底基板；同一像素单元中，所述像素驱动电路在所述衬底基板的正投影位于所述子像素的第一电极在所述衬底基板的正投影远离所述第二电极在所述衬底基板的正投影的一侧，所述开关单元在所述衬底基板的正投影位于对应所 述子像素的第一电极在所述衬底基板的正投影和第二电极在所述衬底基板的正投影之间。
在本公开的一示例性实施例中，所述显示面板还包括：第一驱动电路，位于所述显示面板的显示区，所述第一驱动电路用于输出栅极控制信号；所述像素驱动电路响应于所述栅极控制信号将数据信号端的数据信号传输至驱动信号端。
在本公开的一示例性实施例中，所述第一驱动电路包括多个级联的第一移位寄存器单元，向本行像素单元提供栅极控制信号的第一移位寄存器单元位于本行像素单元和下一行像素单元之间。
在本公开的一示例性实施例中，所述显示面板还包括：开关驱动电路，位于所述显示面板的显示区，所述开关驱动电路用于输出所述开关信号。
在本公开的一示例性实施例中，所述开关驱动电路包括多个子开关驱动电路，一个子开关驱动电路驱动一列开关单元；所述子开关驱动电路包括多个级联的第三移位寄存器单元，向本行开关电路提供开关信号的第三移位寄存器单元位于本行像素单元和下一行像素单元之间的间隙内。
在本公开的一示例性实施例中，所述像素单元包括第一子像素、第二子像素和第三子像素；所述开关电路包括第一开关单元、第二开关单元和第三开关单元，所述第一开关单元对应连接所述第一子像素，所述第二开关单元对应连接所述第二子像素，所述第三开关单元对应连接所述第三子像素；所述开关驱动电路包括第一子开关驱动电路、第二子开关驱动电路和第三子开关驱动电路，所述第一子开关驱动电路用于向所述第一开关单元输出第一开关信号，所述第二子开关驱动电路用于向所述第二开关单元输出第二开关信号，所述第三子开关单元用于向所述第三开关单元输出第三开关信号；其中，所述第一子开关驱动电路、所述第二子开关驱动电路和所述第三子开关驱动电路先后逐行输出所述第一开关信号、所述第二开关信号和所述第三开关信号；且在所述第一子开关驱动电路输出所述第一开关信号的时间内、在所述第二子开关驱动电路输出所述第二开关信号的时间内以及在所述第三子开关驱动电路输出 所述第三开关信号的时间内，所述第一驱动电路分别输出所述栅极控制信号。
在本公开的一示例性实施例中，所述显示面板包括两个所述开关驱动电路，两个所述开关驱动电路沿行方向分开设置于所述显示区的两侧。
在本公开的一示例性实施例中，所述显示面板还包括：驱动集成电路，用于分别向各所述开关单元输出所述开关信号。
在本公开的一示例性实施例中，所述第一驱动电路位于所述显示面板的非显示区。
在本公开的一示例性实施例中，所述像素单元包括第一子像素、第二子像素和第三子像素；所述开关电路包括第一开关单元、第二开关单元和第三开关单元，所述第一开关单元对应连接所述第一子像素，所述第二开关单元对应连接所述第二子像素，所述第三开关单元对应连接所述第三子像素；其中，在一帧数据中，所述驱动集成电路先后依次输出第一开关信号、第二开关信号和第三开关信号；在所述驱动集成电路输出所述第一开关信号的时间内，所述第一驱动电路依次向各像素驱动电路输出第一栅极控制信号，所述像素驱动电路响应于所述第一栅极控制信号向所述第一子像素提供驱动电流；在所述驱动集成电路输出所述第二开关信号的时间内，所述第一驱动电路依次向各像素驱动电路输出第二栅极控制信号，所述像素驱动电路响应于所述第二栅极控制信号向所述第二子像素提供驱动电流；在各所述驱动集成电路输出所述第三开关信号的时间内，所述第一驱动电路依次向各像素驱动电路输出第三栅极控制信号，所述像素驱动电路响应于所述第三栅极控制信号向所述第三子像素提供驱动电流。
在本公开的一示例性实施例中，在一帧数据中，所述第一开关信号、所述第二开关信号和所述第三开关信号的持续时长相同。
在本公开的一示例性实施例中，所述第一驱动电路按照第一频率输出栅极控制信号，所述驱动集成电路按照第二频率输出开关信号，所述第一频率为所述第二频率的3倍。
在本公开的一示例性实施例中，所述像素驱动电路包括：驱动模块，连接第一节点、第二节点和第三节点，所述驱动模块用于响应所述第一 节点的电压信号利用所述第二节点和所述第三节点的电压差提供驱动电流；第一复位模块，连接第一节点、第一复位信号端和初始信号端，所述第一复位模块用于响应所述第一复位信号端的复位信号将所述初始信号端的初始信号传输至所述第一节点；传输模块，连接所述第一节点、栅极信号端和所述第二节点，所述传输模块用于响应所述栅极信号端的信号导通所述第一节点和所述第二节点的连通路径；数据写入模块，连接数据信号端、所述栅极信号端和所述第三节点，所述数据写入模块用于响应所述栅极信号端的信号将所述数据信号端的第二数据信号传输至所述第三节点；第二复位模块，连接第四节点、所述初始信号端和所述第一复位信号端，所述第二复位模块用于响应所述第一复位信号端的复位信号将所述初始信号端的初始信号传输至所述第四节点；第一发光控制模块，连接所述第三节点、使能信号端和第一电源端，所述第一发光控制模块用于响应所述使能信号端的使能信号导通所述第三节点与所述第一电源端的连通路径；第二发光控制模块，连接所述第二节点、所述第四节点和调节模块，所述第二发光控制模块用于响应所述调节模块的信号导通所述第四节点与所述第二节点的连通路径；调节模块，连接数据信号端、第二复位信号端、第一复位信号端、初始信号端和使能信号端，所述调节模块用于响应所述数据信号端的第一数据信号关闭所述第二发光控制模块，或者用于响应所述数据信号端的第二数据信号打开所述第二发光控制模块。
在本公开的一示例性实施例中，所述驱动模块包括：驱动晶体管，控制端连接所述第一节点，第一端连接所述第三节点，第二端连接所述第二节点；所述第一复位模块包括：第一晶体管，控制端连接第一复位信号端，第一端连接所述第一节点，第二端连接所述初始信号端；所述传输模块包括：第二晶体管，控制端连接栅极信号端，第一端连接所述第一节点，第二端连接所述第二节点；所述数据写入模块包括：第四晶体管，控制端连接所述栅极信号端，第一端连接所述数据信号端，第二端连接所述第三节点；所述第二复位模块包括：第七晶体管，控制端连接所述第一复位信号端，第一端连接初始信号端，第二端连接所述第四节点；所述第一发光控制模块包括：第五晶体管，控制端连接所述使能 信号端，第一端连接所述第一电源端，第二端连接所述第三节点；所述第二发光控制模块包括：第六晶体管，控制端连接第七节点，第一端连接所述第二节点，第二端连接第四节点；所述调节模块包括：第八晶体管，控制端连接第二复位信号端，第一端连接所述数据信号端，第二端连接第五节点，所述第八晶体管用于响应所述第二复位信号端的复位信号将所述数据信号端的数据信号传输至所述第五节点；第九晶体管，控制端连接所述第五节点，第一端连接所述使能信号端，第二端连接所述第七节点，所述第九晶体管用于响应所述第五节点的电压信号将所述使能信号端的使能信号传输至所述第七节点；第一电容，连接所述第五节点和所述初始信号端，所述第一电容用于存储写入所述第五节点的电压信号；第十晶体管，控制端连接所述第一复位信号端，第一端连接所述数据信号端，第二端连接第六节点，所述第十晶体管用于响应所述第一复位信号端的复位信号将所述数据信号端的数据信号传输至所述第六节点；第十一晶体管，控制端连接所述第六节点，第一端连接高频信号端，第二端连接所述第七节点，所述第十一晶体管用于响应所述第六节点的电压信号将所述高频信号端的信号传输至所述第七节点；第二电容，连接所述第六节点和所述使能信号端，所述第二电容用于存储写入所述第六节点的电压信号。
在本公开的一示例性实施例中，所述开关单元为晶体管。
在本公开的一示例性实施例中，所述像素单元包括第一子像素、第二子像素和第三子像素，所述开关电路包括第十二晶体管、第十三晶体管和第十四晶体管；所述第十二晶体管的控制端接收第一开关信号，所述第十二晶体管的第一端连接第四节点，所述第十二晶体管的第二端连接第一子像素的第一电极；所述第十三晶体管的控制端接收第二开关信号，所述第十三晶体管的第一端连接第四节点，所述第十三晶体管的第二端连接第二子像素的第一电极；所述第十四晶体管的控制端接收第三开关信号，所述第十四晶体管的第一端连接第四节点，所述第十四晶体管的第二端连接第三子像素的第一电极。
在本公开的一示例性实施例中，所述显示面板包括：衬底基板；第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：第三导电 部，用于形成所述存储电容的第一电极；有源层，位于所述第一导电层被背离所述衬底基板的一侧，所述有源层包括：第一有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第一有源部用于形成所述第一晶体管的沟道区；第一子有源部，连接于所述第一有源部的一侧，用于形成所述第一晶体管的第一端；第二子有源部，连接于所述第一有源部的另一侧，用于形成所述第一晶体管的第二端和所述第七晶体管的第一端；第七有源部，与所述第二子有源部连接，所述第七有源部用于形成第七晶体管的沟道区；第十四子有源部，连接于所述第七有源部的另一侧，用于形成所述第七晶体管的第二端；第三有源部，在所述衬底基板的正投影沿列方向位于所述第三导电部在所述衬底基板的正投影的一侧，所述第三有源部用于形成所述驱动晶体管的沟道区；第五子有源部，沿列方向连接于所述第三有源部的一侧，所述第五子有源部用于形成所述驱动晶体管的第一端；第六子有源部，连接于所述第三有源部的另一侧，所述第六子有源部用于形成所述驱动晶体管的第二端；第二有源部，沿行方向位于所述第三有源部的一侧，所述第二有源部用于形成所述第二晶体管的沟道区；第三子有源部，沿行方向连接于所述第二有源部靠近所述第三有源部的一侧，所述第三子有源部用于形成所述第二晶体管的第一端；第四子有源部，连接于所述第二有源部远离所述第三有源部的一侧，所述第四子有源部用于形成所述第二晶体管的第二端；第四有源部，位于所述第三有源部远离所述第二有源部的一侧，所述第四有源部用于形成所述第四晶体管的沟道区；第七子有源部，连接于所述第四有源部远离所述第三有源部的一侧，所述第七子有源部用于形成所述第四晶体管的第一端；第八子有源部，连接于所述第四有源部靠近所述第三有源部的一侧，所述第八子有源部用于形成所述第四晶体管的第二端；第五有源部，在所述衬底基板的正投影位于所述第三有源部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第五有源部用于形成所述第五晶体管的沟道区；第九子有源部，连接于所述第五有源部远离所述第三有源部的一侧，所述第九子有源部用于形成所述第五晶体管的第一端；第十子有源部，连接于所述第五有源 部靠近所述第三有源部的一侧，所述第十子有源部用于形成所述第五晶体管的第二端；第六有源部，沿行方向位于所述第五有源部的一侧，所述第六有源部用于形成所述第六晶体管的沟道区；第十一子有源部，连接于所述第六有源部靠近所述第三有源部的一侧，所述第十一子有源部用于形成所述第六晶体管的第一端；第十二子有源部，连接于所述第六有源部的另一端，所述第十二子有源部用于形成所述第六晶体管的第二端；第二导电层，位于所述有源层背离所述衬底基板的一侧，所述第二导电层包括：第三导电块，所述第三导电块包括依次连接的第一组成部、第二组成部和第三组成部，所述第一组成部在所述衬底基板的正投影与所述第三导电部在所述衬底基板的正投影部分交叠，所述第三组成部在所述衬底基板的正投影覆盖所述第三有源部在所述衬底基板的正投影，所述第三导电块的部分结构用于形成所述存储电容的第二电极、部分结构用于形成所述驱动晶体管的顶栅；栅极信号线，在所述衬底基板的正投影沿行方向延伸，所述栅极信号线在所述衬底基板的正投影位于所述第三组成部在所述衬底基板的正投影远离所述第一组成部在所述衬底基板的一侧，所述栅极信号线在所述衬底基板的正投影部分覆盖所述第二有源部在所述衬底基板的正投影、部分覆盖所述第四有源部在所述衬底基板的正投影，所述栅极信号线的部分结构用于形成所述第二晶体管的栅极、部分结构用于形成所述第四晶体管的栅极；使能信号线，包括依次连接的主体部、第一子延伸部和第二子延伸部，所述主体部在所述衬底基板的正投影位于所述第三导电块在所述衬底基板的正投影远离所述栅极信号在所述衬底基板的正投影的一侧，所述第二子延伸部在所述衬底基板的正投影覆盖所述第五有源部在所述衬底基板的正投影，所述使能信号线的部分结构用于形成所述第五晶体管的栅极；第六导电块，包括第一子导电块和第二子导电块，所述第一子导电块在所述衬底基板的正投影沿列方向延伸，所述第二子导电块在所述衬底基板的正投影覆盖所述第六有源部在所述衬底基板的正投影，所述第六导电块的部分结构用于形成所述第六晶体管的栅极；第一复位信号线，在所述衬底基板的正投影沿行方向延伸且位于所述第三导电块在所述衬底基板的正投影远离所述第三有源部在所述衬底基板的正投影的一侧，所述第一复位信号 线在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影和所述第七有源部在所述衬底基板的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极和所述第七晶体管的栅极；第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：第三转接部，所述第三转接部的一端通过过孔连接所述第三子有源部，另一端通过过孔连接所述第三导电块；第四转接部，分别通过过孔连接所述第四子有源部、所述第六子有源部和所述第十一子有源部；第五转接部，分别通过过孔连接所述第五子有源部、所述第八子有源部和所述第十子有源部；第六转接部，通过过孔连接所述第十二子有源部；第十七导电块，包括主导电部和子导电部，所述主导电部在所述衬底基板的正投影位于所述第三导电块在所述衬底基板的正投影上，所述第十七导电块分别通过过孔连接所述第三导电部和所述第九子有源部，所述第十七导电块的部分结构用于形成所述存储电容的第一电极，部分结构用于形成所述第五晶体管的第一端；数据信号线，在所述衬底基板的正投影沿列方向延伸，所述数据线通过过孔连接所述第七子有源部。
在本公开的一示例性实施例中，所述第一导电层还包括：第一导电部，用于形成所述第一电容的第一电极；第二导电部，用于形成所述第二电容的第二电极；第四导电部，位于所述第三导电部远离所述第一导电部的一侧，所述第四导电部在所述衬底基板的正投影覆盖所述第三有源部在所述衬底基板的正投影，所述第四导电部用于形成所述驱动晶体管的底栅；第五导电部，连接于所述第四导电部的一侧，所述第五导电部通过过孔连接所述第三转接部；所述有源层还包括：第八有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第八有源部用于形成第八晶体管的沟道区；第十五子有源部，连接于所述第八有源部的一侧，用于形成所述第八晶体管的第一端；第十六子有源部，连接于所述第八有源部的另一侧，用于形成所述第八晶体管的第二端；第九有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第九有源部用于形成所述第九晶体管的沟道区；第十七子有源部，连接于所述第九有源 部的一侧，用于形成所述第九晶体管的第一端；第十八子有源部，连接于所述第九有源部的另一侧，用于形成所述第九晶体管的第二端；第十有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第十有源部用于形成所述第十晶体管的沟道区；第十九子有源部，连接于所述第十有源部的一侧，用于形成所述第十晶体管的第一端；第二十子有源部，连接于所述第十有源部的另一侧，用于形成所述第十晶体管的第二端；第十一有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第十一有源部用于形成所述第十一晶体管的沟道区；第二十一子有源部，连接于所述第十一有源部的一侧，用于形成所述第十一晶体管的第一端；第二十二子有源部，连接于所述第十一有源部的另一侧，用于形成所述第十一晶体管的第二端；所述第二导电层还包括：第一高频信号线，在所述衬底基板的正投影沿行方向延伸且位于所述第一导电部在所述衬底基板的正投影远离所述第三导电部在所述衬底基板的正投影的一侧；第三电源线，在所述衬底基板的正投影沿行方向延伸且位于所述第一高频信号线在所述衬底基板的正投影和所述第一导电部在所述衬底基板的正投影之间，所述第三电源线用于提供所述第一子像素的第二电源端；第二电源线，在所述衬底基板的正投影沿行方向延伸且位于所述第三电源线在所述衬底基板的正投影和所述第一导电部在所述衬底基板的正投影之间，所述第二电源线用于提供所述第二子像素和所述第三子像素的第二电源端；初始信号线，在所述衬底基板的正投影沿行方向延伸且位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间；第二复位信号线，在所述衬底基板的正投影沿行方向延伸且位于所述初始信号线在所述衬底基板的正投影和所述第三导电块在所述衬底基板的正投影之间，所述第二复位信号线在所述衬底基板的正投影覆盖所述第八有源部在所述衬底基板的正投影，所述第二复位信号线的部分结构用于形成所述第八晶体管的栅极；第一电源线，在所述衬底基板的正投影沿行方向延伸且位于所述第一复位信号在所述衬底基板的正投影和所述第三导电块在所述衬底基板的正投影之间， 且所述使能信号线的主体部在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影和所述第三导电块在所述衬底基板的正投影之间；第一导电块，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上，所述第一导电块用于形成所述第一电容的第二电极；第二导电块，在所述衬底基板的正投影位于所述第二导电部在所述衬底基板的正投影上，所述第二导电块用于形成所述第二电容的第二电极；第三导电块，包括依次连接的第一组成部、第二组成部和第三组成部，所述第一组成部在衬底基板的正投影位于所述第三导电部在衬底基板的正投影上，所述第一组成部用于形成所述存储电容的第二电极；所述第三组成部在衬底基板的正投影覆盖所述第三有源部在衬底基板的正投影，所述第三组成部用于形成驱动晶体管的栅极；第四导电块，在所述衬底基板的正投影覆盖所述第九有源部在所述衬底基板的正投影，所述第四导电块的部分结构用于形成所述第九晶体管的栅极；第六导电块，包括第一子导电块和第二子导电块，所述第一子导电块在衬底基板的正投影沿列方向延伸，第二子导电块在衬底基板的正投影沿行方向延伸，所述第二子导电块在衬底基板的正投影覆盖所述第六有源部在衬底基板的正投影，所述第六导电块的部分结构用于形成所述第六晶体管的栅极；第九导电块，在衬底基板的正投影覆盖所述第十一有源部在衬底基板的正投影，所述第九导电块的部分结构用于形成所述第十一晶体管的栅极，所述第九导电块分别通过过孔连接所述第十一转接部和所述第十二转接部；第十导电块，通过过孔连接所述第十七子有源部；所述第三导电层还包括：第二高频信号线，在所述衬底基板的正投影沿列方向延伸，所述第二高频信号线通过过孔连接所述第一高频信号线；数据信号线，在所述衬底基板的正投影沿列方向延伸，所述数据信号线通过过孔连接所述第七子有源部、所述第十五子有源部和所述第十九子有源部；第一转接部，分别通过过孔连接所述第一子有源部和所述第三导电块；第二转接部，分别通过过孔连接第二子有源部和所述初始信号线；第七转接部，分别通过过孔连接所述第一导电块、所述第十六子有源部和所述第四导电块；第八转接部，分别通过过孔连接所述第十七子有源部和所述使能信号线；第九转接部，分别通过过孔连接位于第二导电层的第 五导电块以及所述第十八子有源部和所述第二十二子有源部；第十转接部，分别通过过孔连接所述第五导电块和所述第六导电块；第十一转接部，分别通过过孔连接所述第二十子有源部和所述第九导电块；第十二转接部，分别通过过孔连接所述第九导电块和所述第二导电块；第十六转接部，分别通过过孔连接所述第二十一子有源部和位于第二导电层的第七导电块，所述第七导电块还通过过孔连接所述第二高频信号线；其中，所述第一复位信号线在所述衬底基板的正投影还覆盖所述第十有源部在所述衬底基板的正投影，所述第一复位信号线的部分结构用于形成所述第十晶体管的栅极。
在本公开的一示例性实施例中，所述有源层还包括：第十二有源部，用于形成所述第十二晶体管的沟道区，第二十三子有源部，连接于所述第十二有源部的一侧，所述第二十三子有源部用于形成所述第十二晶体管的第一端，所述第二十三子有源部通过过孔连接所述第六转接部；第二十四子有源部，连接于所述第十二有源部的另一侧，所述第二十四子有源部用于形成所述第十二晶体管的第二端；第十三有源部，用于形成所述第十三晶体管的沟道区；第二十五子有源部，连接于所述第十三有源部的一侧，用于形成所述第十三晶体管的第一端，所述第二十五子有源部通过过孔连接所述第六转接部；第二十六子有源部，连接于所述第十三有源部的另一侧，用于形成所述第十三晶体管的第二端；第十四有源部，用于形成所述第十四晶体管的沟道区；第二十七子有源部，连接于所述第十四有源部的一侧，用于形成所述第十四晶体管的第一端，所述第二十七子有源部通过过孔连接所述第六转接部；第二十八子有源部，连接于所述第十四有源部的另一端，用于形成所述第十四晶体管的第二端；所述第二导电层还包括：第十二导电块，在所述衬底基板的正投影覆盖所述第十二有源部在所述衬底基板的正投影，所述第十二导电块用于形成所述第十二晶体管的栅极；第十三导电块，在所述衬底基板的正投影覆盖所述第十三有源部在所述衬底基板的正投影，所述第十三导电块用于形成所述第十三晶体管的栅极；第十四导电块，在所述衬底基板的正投影覆盖所述第十四有源部在所述衬底基板的正投影，所述第十四导电块用于形成所述第十四晶体管的栅极；所述第三导电层还包括：第 十三转接部，通过过孔连接所述第二十四子有源部；第十四转接部，通过过孔连接所述第二十六子有源部；第十五转接部，通过过孔连接所述第二十八子有源部；所述显示面板还包括：第四导电层，位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括：第二十导电块，用于形成所述第一子像素的第一电极，所述第二十导电块通过过孔连接所述第十三转接部；第二十一导电块，用于形成所述第二子像素的第一电极，所述第二十一导电块通过过孔连接所述第十四转接部；第二十二导电块，用于形成所述第三子像素的第一电极，所述第二十二导电块通过过孔连接所述第十五转接部。
根据本公开的第二方面，还提供一种显示装置，包括本公开任意实施例所述的显示面板。
本公开提供的显示面板，在一个像素单元中包括多个子像素且包括一个像素驱动电路，多个子像素通过所设置的开关电路与该像素驱动进行连接，从而一个像素单元中的多个子像素通过开关电路复用一个像素驱动电路，开关电路中的各开关单元通过响应对应的开关信号可以对像素驱动电路与子像素进行连接切换，可以根据设定的时序由像素驱动电路向所连接的子像素提供相应的驱动电流，实现显示面板的正常显示。本公开一个像素单元中的多个子像素复用一个像素驱动电路，可以减少单个像素单元的占用空间，从而可以提高显示区所能布设的像素数量，即提高像素密度。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开一种实施方式的显示面板的结构示意图；
图2为图1中一个像素单元的结构示意图；
图3为根据本公开一种实施方式的驱动时序图；
图4为根据本公开一种实施方式的显示面板的结构示意图；
图5为根据本公开另一种实施方式的显示面板的结构示意图；
图6为根据本公开一种实施方式的显示面板的结构示意图；
图7为根据本公开另一种实施方式的驱动时序图；
图8为根据本公开一种实施方式的像素驱动电路的等效电路图；
图9为根据本公开一种驱动方式的图8中各节点的时序图；
图10为根据本公开另一种驱动方式的图8中各节点的时序图；
图11为根据本公开一种实施方式的结构版图；
图12为图11中第一导电层的结构版图；
图13为图11中有源层的结构版图；
图14为图11中第二导电层的结构版图；
图15为图11中第三导电层的结构版图；
图16为图11中第四导电层的结构版图；
图17为图11中沿虚线AA的部分剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
图1为根据本公开一种实施方式的显示面板的结构示意图，图2为图1中一个像素单元的结构示意图，如图1、图2所示，该显示面板可以包括沿行方向X和列方向Y阵列分布的多个像素单元，像素单元可以包括像素驱动电路P-Drive、多个子像素和开关电路MSW，其中，像素驱动电路P-Drive用于提供驱动电流；子像素的第一电极P-AOD用于连接像素驱动电路P-Drive，子像素的第二电极P-CTO连接第二电源端， 子像素在驱动电流的作用下发光；开关电路MSW可以包括多个开关单元，开关单元与子像素对应设置，开关单元串接于像素驱动电路P-Drive与对应子像素之间，开关单元的控制端用于接收开关信号，开关单元的第一端连接像素驱动电路P-Drive，开关单元的第二端连接对应子像素的第二电极P-CTO，开关单元响应于开关信号导通子像素与像素驱动电路P-Drive的连通路径。
本公开提供的显示面板，在一个像素单元中包括多个子像素且包括一个像素驱动电路P-Drive，多个子像素通过所设置的开关电路MSW与该像素驱动进行连接，从而一个像素单元中的多个子像素通过开关电路MSW复用一个像素驱动电路P-Drive，开关电路MSW中的各开关单元通过响应对应的开关信号可以对像素驱动电路P-Drive与子像素进行连接切换，可以根据设定的时序由像素驱动电路P-Drive向所连接的子像素提供相应的驱动电流，实现显示面板的正常显示。本公开一个像素单元中的多个子像素复用一个像素驱动电路P-Drive，可以减少单个像素单元的占用空间，从而可以提高显示区所能布设的像素数量，即提高像素密度。
本公开通过将像素单元中的子像素设置为共用同一像素驱动电路P-Drive，由开关电路MSW进行子像素与像素驱动电路P-Drive的导通切换，因为开关电路MSW中的开关单元占用空间远小于一个像素驱动电路P-Drive的占用空间，由此可以极大地减小像素单元的占用空间，从而提升显示区的像素布设密度。相比于一个子像素对应一个像素驱动电路P-Drive的显示面板结构，本公开显示面板中，单个像素单元的整体占用面积可以减小30％以上，显然，本公开显示面板可以极大地提升像素密度。
如图2所示，在示例性实施例中，每个像素单元中开关电路MSW包含的开关单元数量可以与像素单元中子像素的数量相同。通常，一个像素单元可以包括第一子像素、第二子像素和第三子像素，第一子像素例如可以为R像素，第二子像素例如可以为G像素，第三子像素例如可以为B像素，则开关电路MSW中可以包括第一开关单元MUX1、第二开关单元MUX2和第三开关单元MUX3，第一开关单元MUX1串接于 第一子像素与像素驱动电路P-Drive之间，第二开关单元MUX2串接于第二子像素与像素驱动电路P-Drive之间，第三开关单元MUX3串接于第三子像素与像素驱动电路P-Drive之间，每个开关单元响应于各自获取到的开关信号导通对应子像素与像素驱动电路P-Drive的连通路径。示例性的，当第一开关单元MUX1获取到第一开关信号时，第一子像素与像素驱动电路P-Drive建立连接，此时像素驱动电路P-Drive可以在当前数据信号的作用下向第一子像素提供驱动电流，以驱动第一子像素进行发光显示。当第二开关单元MUX2获取到第二开关信号时，第二子像素与像素驱动电路P-Drive建立连接，此时像素驱动电路P-Drive可以在当前数据信号的作用下向第二子像素提供驱动电流，驱动第二子像素进行发光显示。同样地，当第三开关单元MUX3获取到第三开关信号时，第三子像素与像素驱动电路P-Drive建立连接，此时像素驱动电路P-Drive在对应的数据信号作用下向第三子像素提供驱动电流，驱动第三子像素进行发光显示。
在示例性实施例中，如图1所示，在同一像素单元中，像素驱动电路P-Drive在衬底基板的正投影位于子像素的第一电极P-AOD在衬底基板的正投影远离第二电极P-CTO在衬底基板的正投影的一侧，开关单元在衬底基板的正投影位于对应子像素的第一电极P-AOD在衬底基板的正投影和第二电极P-CTO在衬底基板的正投影之间。举例而言，像素单元可以包括第一子像素、第二子像素和第三子像素，第一子像素、第二子像素和第三子像素可以沿列方向Y排列，开关电路MSW可以包括沿列方向Y排列且与三个子像素分别对应的第一开关单元MUX1、第二开关单元MUX2和第三开关单元MUX3，第一开关单元MUX1与第一子像素连接，相应地，第一开关单元MUX1在衬底基板的正投影可以位于第一子像素的第一电极P-AOD在衬底基板的正投影和第二电极P-CTO在衬底基板的正投影之间。第二开关单元MUX2连接第二子像素，则第二开关单元MUX2在衬底基板的正投影位于第二子像素的第一电极P-AOD在衬底基板的正投影和第二电极P-CTO在衬底基板的正投影之间。第三开关单元MUX3连接第三子像素，则第三开关单元MUX3在衬底基板的正投影位于第三子像素的第一电极P-AOD在衬底基板的正 投影和第二电极P-CTO在衬底基板的正投影之间。像素驱动电路P-Drive位于第一电极远离第二电极的一侧。第一电极P-AOD例如可以为阳极，第二电极P-CTO例如可以为阴极。当然，第一电极P-AOD也可以为阴极，第二电极P-CTO可以为阳极，本公开对此不作限定。通过将像素单元中的像素驱动电路P-Drive、开关单元以及子像素按照如上关系进行设置，可以进一步节省子像素的占用空间，有利于进一步提升显示区的像素密度。
应该理解的是，本公开所述的像素驱动电路P-Drive在衬底基板的正投影可以理解为形成像素驱动电路P-Drive中各器件的版图结构在衬底基板的正投影。类似地，开关单元在衬底基板的正投影可以理解为形成开关单元的版图结构在衬底基板的正投影。
在示例性实施例中，开关电路MSW可以由开关驱动电路MOA输出的开关信号进行控制。开关驱动电路MOA可以包括多个级联的第三移位寄存器单元，每一第三移位寄存器向与其对应的像素行中的开关单元提供开关信号，各移位寄存器级联，从而开关驱动电路MOA依次向各行的开关单元提供开关信号。
示例性的，如图2所示，像素单元可以包括三个子像素，开关驱动电路MOA可以包括第一子开关驱动电路MOAR、第二子开关驱动电路MOAG和第三子开关驱动电路MOAB，第一子开关驱动电路MOAR可以用于向第一开关单元MUX1提供对应的开关信号，以控制第一子像素与像素驱动电路P-Drive的连接；第二子开关驱动电路MOAG可以用于向第二开关单元MUX2提供对应的开关信号，以控制第二子像素与像素驱动电路P-Drive的连接；第三子开关驱动电路MOAB可以用于向第三开关单元MUX3提供对应的开关信号，以控制第三子像素与像素驱动电路P-Drive的连接。第一子开关驱动电路MOAR、第二子开关驱动电路MOAG、第三子开关驱动电路MOAB均包括多个级联的第三移位寄存器单元，第一子开关驱动电路MOAR中的第三移位寄存器单元用于向对应行的第一开关单元MUX1提供第一开关信号，以控制对应行的第一子像素与像素驱动电路P-Drive的连接；第二子开关驱动电路MOAG中的第 三移位寄存器单元用于向对应行的第二开关单元MUX2提供第二开关信号，以控制对应行的第二子像素与像素驱动电路P-Drive的连接；第三子开关驱动电路MOAB中的第三移位寄存器单元用于向对应行的第三开关但愿他共第三开关信号，以控制对应行第三子像素与像素驱动电路P-Drive的连接。
图3为根据本公开一种实施方式的驱动时序图，如图3所示，开关驱动电路MOA可以按照逐行输出开关信号的方式依次将每一行的各子像素与像素驱动电路P-Drive进行连接，并且在开关驱动电路MOA输出开关信号的时间内，显示面板中的其他驱动电路向像素驱动电路P-Drive提供复位信号、栅极控制信号和使能控制信号，使得像素驱动电路P-Drive能够向与其连接的子像素提供驱动电流，驱动与其连接的子像素发光显示。
举例而言，第一行的第一子开关驱动电路MOAR可以先输出第一开关信号以导通第一行的所有第一开关单元MUX1，从而第一行的各第一子像素均与对应的像素驱动电路P-Drive连接，同时，显示面板中的第三驱动电路RST GOA、第一驱动电路Gate GOA、第二驱动电路EM GOA可以依次向第一行的像素驱动电路P-Drive提供复位信号、栅极控制信号和使能信号，像素驱动电路P-Drive响应于上述的信号为第一行的各第一子像素提供驱动电流，从而第一行的各第一子像素在第一开关信号的有效时间内发光显示。然后，第一行的第二子开关驱动电路MOAG输出第二开关信号以导通第一行的所有第二开关单元MUX2，将第一行的第二子像素与对应像素驱动电路P-Drive连接，在第二开关信号期间，第三驱动电路RST GOA、第一驱动电路Gate GOA和第二驱动电路EM GOA重复上述过程分别输出复位信号、栅极控制信号和使能信号，使得第一行的像素驱动电路P-Drive此时可以向各第二子像素提供驱动电流，驱动第一行的第二子像素进行发光显示。然后，第一行的第三子开关驱动电路MOAB输出电开关信号以导通第一行的所有第三开关单元MUX3，将第一行的像素驱动电路P-Drive与第三子像素进行连接，显示面板的第三驱动电路RST GOA、第一驱动电路Gate GOA和第二驱动电路EM GOA分别依次输出复位信号、栅极控制信号和使能信号，第一行 的像素驱动电路P-Drive此时可以向第三子像素提供驱动电流，驱动第一行的第三子像素进行发光显示。此后，开关驱动电路MOA、第三驱动电路RST GOA、第一驱动电路Gate GOA和第二驱动电路EM GOA分别重复上述的信号输出过程，逐行分时点亮第一子像素、第二子像素和第三子像素。
可以看出，本公开通过提高第三驱动电路RST GOA、第一驱动电路Gate GOA和第二驱动电路EM GOA的工作频率，配合所设置的开关驱动电路MOA输出相应的开关信号，可以驱动本公开显示面板进行发光显示，即实现了在提升像素PPI的结构下显示面板的正常发光显示。应该理解的是，在其他实施例中，显示面板还可以具有其他的驱动方式，基于其他的驱动方式同样可以驱动本公开显示面板正常显示。
图4为根据本公开一种实施方式的显示面板的结构示意图，如图4所示，开关驱动电路MOA可以包括第一子开关驱动电路MOAR、第二子开关驱动电路MOAG和第三子开关驱动电路MOAB，每一子开关驱动电路可以包括多个级联的第三移位寄存器单元，可以将各第三移位寄存器单元设置于相邻两行像素的间隙内，由此各第三移位寄存器单元无需额外占用显示区空间，通过利用显示区的已有空间而实现提升显示面板的PPI。
举例而言，如上文所述，显示面板通常包括第三驱动电路RST GOA、第一驱动电路Gate GOA和第二驱动电路EM GOA，每一个驱动电路均包括多个级联的移位寄存器单元，并且各驱动电路的移位寄存器单元是分布于相邻两行像素之间。而可以知道的是，一个驱动电路仅分布有一列或几列的移位寄存器单元，其远远少于显示面板中的像素列数量，由此多数列相邻两行之间的间隙未被使用，本公开可以利用这些已有的未被占用的行与行之间的间隙来放置开关驱动电路MOA中的各级移位寄存器，从而无需额外占用显示区空间，提升对于显示区的空间利用率。此结构尤其适用于拼接屏显示产品，因为拼接屏显示产品只有显示区，通过该布局方式能够利用已有空间，开关驱动电路MOA无需占用其他显示空间。
图5为根据本公开另一种实施方式的显示面板的结构示意图，如图 5所示，在示例性实施例中，显示面板可以包括两个开关驱动电路MOA，两个开关驱动电路MOA分开设置于显示区的两侧。例如，一个开关驱动电路MOA位于显示区靠左的一侧，另一开关电路MSW位于显示区靠右的一侧。这样设置的好处在于，通过在显示区的两侧分别设置开关驱动电路MOA，可以减小单个开关驱动电路MOA和与其连接的远端的开关单元的距离，从而可以减小对应开关信号在传输线上的线损。应该理解的是，在显示面板包括两个开关驱动电路MOA的情况下，每一开关驱动电路MOA均具有上文所述的结构，此处不再详述。此外，在其他实施例中，还可以设置三个或更多个开关驱动电路MOA，这些都属于本公开的保护范围。
在一些实施例中，开关电路MSW也可以不用开关驱动电路MOA进行分时驱动，例如可以由驱动集成电路DIC输出对应的开关信号以控制开关电路MSW中的各开关单元分时导通。示例性的，图6为根据本公开一种实施方式的显示面板的结构示意图，如图6所示，驱动集成电路DIC可以沿列方向Y设置于显示区的一侧，驱动集成电路DIC可以通过信号线S向开关电路MSW输出开关信号。如上文所述，开关电路MSW可以包括第一开关单元MUX1、第二开关单元MUX2和第三开关单元MUX3，在一帧数据中，驱动集成电路DIC可先向显示面板中的全部第一开关单元MUX1提供第一开关信号，以将全部第一子像素与对应像素驱动电路P-Drive连接，由对应像素驱动电流向第一子像素提供驱动电流，驱动第一子像素进行发光显示；然后驱动集成电路DIC向显示面板中的全部第二开关单元MUX2提供第二开关信号，将全部第二子像素与对应像素驱动电路P-Drive连接，由对应像素驱动电路P-Drive向第二子像素提供驱动电流，驱动第二子像素进行发光显示；最后驱动集成电路DIC向显示面板中的全部第三开关单元MUX3提供第三开关信号，将全部第三子像素与对应像素驱动电路P-Drive连接，由对应像素驱动电路P-Drive向第三子像素提供驱动电流，驱动第三子像素进行发光显示。
示例性的，图7为根据本公开另一种实施方式的驱动时序图，如图 7所示，在一帧数据中，驱动集成电路DIC先后输出第一开关信号、第二开关信号和第三开信号，其中的第一开关信号用于导通显示面板中的全部第一开关单元MUX1，以将每个像素单元中的第一子像素与该像素单元中的像素驱动电路P-Drive进行连接；第二开关信号用于导通显示面板中的全部第二开关单元MUX2，以将每个像素单元中的第二子像素与该像素单元的像素驱动电路P-Drive进行连接；第三开关信号用于导通显示面板中的全部第三开关单元MUX3，以将每个像素单元中的第三子像素与该像素单元的像素驱动电路P-Drive进行连接。
如图7所示，驱动集成电路DIC先输出第一开关信号，在驱动集成电路DIC输出第一开关信号的时间内，显示面板中的所有第一子像素被连接至对应的像素驱动电路P-Drive，在此过程中，显示面板中的第二驱动电路EM GOA、第三驱动电路RST GOA、第一驱动电路Gate GOA依次向像素驱动电路P-Drive提供使能信号、复位信号、栅极控制信号，各像素驱动电路P-Drive向本像素单元的第一子像素提供驱动电流，驱动本像素单元的第一子像素进行发光显示。然后，驱动集成电路DIC输出第二开关信号，在驱动集成电路DIC输出第二开关信号的时间内，各开关电路MSW中的第二开关单元MUX2被导通，显示面板中的所有第二子像素被连接至对应的像素驱动电路P-Drive，第二驱动电路EM GOA、第三驱动电路RST GOA和第一驱动电路Gate GOA依次分别输出使能信号、复位信号和栅极控制信号，各像素驱动电路P-Drive向所连接的第二子像素提供驱动电流，驱动本像素单元的第二子像素进行发光显示。最后，驱动集成电路DIC输出第三开关信号，在此时间内，各开关电路MSW中的第三开关单元MUX3被导通，显示面板中的全部第三子像素被连接至对应的像素驱动电路P-Drive，第二驱动电路EM GOA、第三驱动电路RST GOA和第一驱动电路Gate GOA依次分别输出使能信号、复位信号和栅极控制信号，各像素驱动电路P-Drive向所连接的第三子像素提供驱动电流，驱动与其连接的第三子像素进行发光显示。可以看出，与上述MOA驱动方式的不同的是，驱动集成电路DIC在一帧时间内分时输出三个开关信号，并且在每一开关信号时间内，对应子像素被充电显示，从而三种子像素分时显示。例如，第一子像素为R像素，第二子 像素为G像素，第三子像素为B像素，则在该示例性实施例中，驱动集成电路DIC在一帧时间内先控制显示面板中的全部R像素进行显示，再控制全部的G像素进行显示，最后控制全部的B像素进行显示。在示例性实施例中，第二驱动电路EM GOA、第三驱动电路RST GOA和第一驱动电路Gate GOA可以设置于显示区的两侧，不占用显示区空间，并且开关信号是由驱动集成电路DIC所输出，驱动集成电路DIC也不占用显示空间，由此显示区的像素密度可以进一步增加，实现更高PPI。
如图7所示，在一帧数据中，第一开关信号、第二开关信号和第三开关信号的持续时长可以相同，换言之，驱动集成电路DIC在一帧数据的前1/3时间控制全部第一子像素进行显示，在一帧数据的中间1/3时间控制全部第二子像素进行显示，在一帧数据的后1/3时间控制全部第三子像素进行显示。由此在一帧数据中，三种子像素的显示时长相同，该发光显示方式能够提高显示均一性，解决显示偏色问题，提升显示效果。可以理解的是，在每一开关信号的有效时长内，第二驱动电路EM GOA、第三驱动电路RST GOA和第一驱动电路Gate GOA均需要依次向像素驱动电路P-Drive输出使能信号、复位信号、栅极控制信号，因此，第二驱动电路EM GOA、第三驱动电路RST GOA和第一驱动电路Gate GOA输出驱动信号的频率为驱动集成电路DIC输出开关信号的频率的三倍。
图8为根据本公开一种实施方式的像素驱动电路的等效电路图，如图8所示，该像素驱动电路P-Drive可以包括驱动模块10、第一复位模块40、传输模块30、数据写入模块20、第二复位模块50、第一发光控制模块60、第二发光控制模块70、存储模块80和调节模块90，其中，驱动模块10连接第一节点N1、第二节点N2和第三节点N3，驱动模块10用于响应第一节点N1的电压信号利用第二节点N2和第三节点N3的电压差提供驱动电流；第一复位模块40连接第一节点N1、第一复位信号端和初始信号端，第一复位模块40用于响应第一复位信号端的复位信号将初始信号端的初始信号传输至第一节点N1；传输模块30连接第一节点N1、栅极信号端Gate和第二节点N2，传输模块30用于响应栅极信号端Gate的信号导通第一节点N1和第二节点N2的连通路径；数据 写入模块20连接数据信号端Vdata、栅极信号端Gate和第三节点N3，数据写入模块20用于响应栅极信号端Gate的信号将数据信号端Vdata的第二数据信号传输至第三节点N3；第二复位模块50连接第四节点N4、初始信号端Vinit和第一复位信号端RSTA，第二复位模块50用于响应第一复位信号端RSTA的复位信号将初始信号端Vinit的初始信号传输至第四节点N4；第一发光控制模块60连接第三节点N3、使能信号端EM和第一电源端VDD，第一发光控制模块60用于响应使能信号端EM的使能信号导通第三节点N3与第一电源端VDD的连通路径；第二发光控制模块70连接第二节点N2、第四节点N4和调节模块90，第二发光控制模块70用于响应调节模块90的输出信号导通第四节点N4与第二节点N2的连通路径；调节模块90连接数据信号端Vdata、第二复位信号端RSTB、第一复位信号端RSTA、初始信号端Vinit和使能信号端EM，调节模块90用于响应数据信号端Vdata的第一数据信号关闭第二发光控制模块70，或者用于响应数据信号端Vdata的第二数据信号打开第二发光控制模块70。
在示例性实施例中，像素驱动电路P-Drive中的各功能模块可以通过晶体管来实现。示例性的，如图8所示，驱动模块10可以包括驱动晶体管M3，驱动晶体管M3的控制端连接第一节点N1，驱动晶体管M3的第一端连接第三节点N3，驱动晶体管M3的第二端连接第二节点N2。第一复位模块40可以包括第一晶体管M1，第一晶体管M1的控制端连接第一复位信号端RSTA，第一晶体管M1的第一端连接第一节点N1，第一晶体管M1的第二端连接初始信号端Vinit。传输模块30可以包括第二晶体管M2，第二晶体管M2的控制端连接栅极信号端Gate，第二晶体管M2的第一端连接第一节点N1，第二晶体管M2的第二端连接第二节点N2。数据写入模块20可以包括第四晶体管M4，第四晶体管M4的栅极连接栅极信号端Gate，第四晶体管M4的第一端连接数据信号端Vdata，第四晶体管M4的第二端连接第三节点N3。第二复位模块50可以包括第七晶体管M7，第七晶体管M7的控制端连接第一复位信号端RSTA，第七晶体管M7的第一端连接初始信号端Vinit，第七晶体管M7的第二端连接第四节点N4。第一发光控制模块60可以包括第五晶体管 M5，第五晶体管M5的控制端连接使能信号端EM，第五晶体管M5的第一端连接第一电源端VDD，第五晶体管M5的第二端连接第三节点N3。第二发光控制模块70可以包括第六晶体管M6，第六晶体管M6的控制端连接调节模块90的输出端，第六晶体管M6的第一端连接第二节点N2，第六晶体管M6的第二端连接第四节点N4。
如图8所示，存储模块80可以包括存储电容Cst，存储电容Cst的第一电极连接第一电源端VDD，存储电容Cst的第二电极连接第一节点N1。存储电容Cst可用于存储写入第一节点N1的电压信号。
如图8所示，调节模块90可以包括第八晶体管M8、第九晶体管M9、第十晶体管M10和第十一晶体管M11以及第一电容C1和第二电容C2，其中，第八晶体管M8的控制端连接第二复位信号端RSTB，第八晶体管M8的第一端连接数据信号端Vdata，第八晶体管M8的第二端连接第五节点N5，第八晶体管M8可以响应第二复位信号端RSTB的复位信号将数据信号端Vdata的数据信号传输至第五节点N5；第九晶体管M9的控制端连接第五节点N5，第九晶体管M9的第一端连接使能信号端EM，第九晶体管M9的第二端连接第六晶体管M6的控制端，第九晶体管M9可以响应第五节点N5的电压信号将使能信号端EM的使能信号传输至第六晶体管M6的控制端。第一电容C1的第一电极连接初始信号端Vinit，第一电容C1的第二电极连接第五节点N5，初始信号端Vinit输出的初始信号可以对第一电容C1进行复位，第一电容C1可以存储写入第五节点N5的电压信号。第十晶体管M10的控制端连接第一复位信号端RSTA，第十晶体管M10的第一端连接数据信号端Vdata，第十晶体管M10的第二端连接第六节点N6，第十晶体管M10可以响应于第一复位信号端RSTA的复位信号将数据信号端Vdata的数据信号传输至第六节点N6。第十一晶体管M11的控制端连接第六节点N6，第十一晶体管M11的第一端连接高频信号端HF，第十一晶体管M11的第二端连接第六晶体管M6的控制端，第十一晶体管M11可以响应于第六节点N6的电压信号将高频信号端HF的电压信号传输至第六晶体管M6的控制端。第二电容C2的第一电极连接初始信号端Vinit，第二电容C2的第二电极连接第六节点N6，初始信号端Vinit可以对第二电容C2进行复位， 并且第二电容C2可以存储写入第六节点N6的电压信号。上述的第一晶体管M1～第十一晶体管M11可以为P型晶体管，例如可以为P型低温多晶硅晶体管。当然，在其他实施例中，第八晶体管M8～第十一晶体管M11也可以为N型晶体管，例如可以为N型氧化晶体管等。
图9为根据本公开一种驱动方式的图8中各节点的时序图，如图9所示，该像素驱动电路P-Drive可以包括复位阶段、补偿阶段和发光阶段，其中：
在复位阶段t1，第二复位信号端RSTB输出低电平的第二复位信号导通第八晶体管M8，数据信号端Vdata输出的低电平信号被传输至第五节点N5并被第一电容C1存储，第九晶体管M9在第五节点N5的信号作用下导通，将使能信号端EM的高电平信号写入第六晶体管M6的控制端，第六晶体管M6关闭。然后，第一复位信号端RSTA输出第一复位信号分别打开第一晶体管M1、第七晶体管M7，初始信号端Vinit输出初始信号对第一节点N1和第四节点N4以及第一电容C1和第二电容C2进行复位。此后，第九晶体管M9在第一电容C1存储的低电平信号作用下维持导通状态，第十一晶体管M11关闭。
在补偿阶段t2，栅极信号端Gate输出低电平的栅极控制信号导通第四晶体管M4，第四晶体管M4将数据信号端Vdata的数据信号写入第三节点N3，并通过驱动晶体管M3的作用写入驱动晶体管M3的栅极，实现对驱动晶体管M3的阈值电压补偿。
在发光阶段t3，使能信号端EM输出低电平信号，将第五晶体管M5导通，且使能信号端EM输出的低电平信号通过第九晶体管M9被写入第六晶体管M6的栅极，控制第六晶体管M6导通，此时，导通的开关单元将对应子像素的第一电极P-AOD连接至第四节点N4，从而被驱动发光。
图10为根据本公开另一种驱动方式的图8中各节点的时序图，如图10所示，该驱动方法同样可以包括复位阶段、补偿阶段和发光阶段，其中，
在复位阶段t1，第二复位信号端RSTB输出低电平的第二复位信号导通第八晶体管M8，数据信号端Vdata输出的高电平信号被传输至第五 节点N5，第九晶体管M9关闭。然后，第一复位信号端RSTA输出低电平的第一复位信号将第十晶体管M10导通，数据信号端Vdata输出的低电平的数据信号被传输至第六节点N6，第十一晶体管M11在第六节点N6的低电平信号作用下导通，此后，在第二电容C2存储的低电平信号作用下，第十一晶体管M11维持导通状态，第九晶体管M9被关闭。
在补偿阶段t2，栅极信号端Gate输出低电平的栅极控制信号导通第四晶体管M4，第四晶体管M4将数据信号端Vdata写入的数据信号写入第三节点N3，并通过驱动晶体管M3的作用写入第一节点N1，实现对驱动晶体管M3的阈值电压补偿。
在发光阶段t3，使能信号端EM输出的低电平信号导通第五晶体管M5，高频信号端HF输出低电平信号，并通过第十一晶体管M11传输至第六晶体管M6的栅极，第六晶体管M6被导通，此时，导通的开关单元将对应子像素的第一电极P-AOD连接至第四节点N4，从而被驱动发光。
图11为根据本公开一种实施方式的结构版图，图12为图11中第一导电层的结构版图，图13为图11中有源层的结构版图，图14为图11中第二导电层的结构版图，图15为图11中第三导电层的结构版图，图16为图11中第四导电层的结构版图。
如图11、图12所示，在示例性实施例中，第一导电层1可以包括第一导电部101、第二导电部102、第三导电部103，第一导电部101、第二导电部102、第三导电部103分别用于形成第一电容C1的第一电极、第二电容C2的第一电极、存储电容Cst的第一电极。第一导电层1还可以包括第四导电部104和第五导电部105，第四导电部104用于形成驱动晶体管M3的底栅。第五导电部105连接于第四导电部104的一端，且第五导电部105还通过过孔连接第三导电层4的第三转接部403，以通过第三转接部403将驱动晶体管M3的栅极连接至第一节点N1。此外，第一导电层1还可以包括第六导电部106和第七导电部107，第六导电部106和第七导电部107沿行方向X连接于第三导电部103的两侧，并且第六导电部106可以与相邻像素单元中的第七导电部107连接，第七 导电部107可以与相邻像素单元中的第六导电部106连接，因为第三导电部103与第一电源线VDD连接，从而第一电源线VDD和第三导电部103、第六导电部106、第七导电部107可以形成网格结构，该网格结构的电源线可以降低其上电源信号的压降。
如图11、图13所示，在示例性实施例中，有源层2可以包括第一有源部21～第十四有源部270以及第一子有源部201～第二十八子有源部228，其中，第一有源部21用于形成第一晶体管M1的沟道区，第一子有源部201、第二子有源部202连接于所述第一有源部21的两端以分别形成第一晶体管M1的第一端和第二端，此外，第二子有源部202还连接第七有源部27，以形成第七晶体管M7的第一端，第二子有源部202可通过过孔连接第三导电层4的第二转接部402，以通过第二转接部402将第一晶体管M1的第二端和第七晶体管M7的第一端连接至初始信号线Vinit。第二有源部22用于形成第二晶体管M2的沟道区，第三子有源部203、第四子有源部204连接于第二有源部22的两侧以分别形成第二晶体管M2的第一端和第二端，第三子有源部203可通过过孔连接第三导电层的第三转接部403，以通过第三转接部403将第二晶体管M2的第一端连接至第一节点N1，第四子有源部204可通过过孔连接第三导电层的第四转接部404，以通过该第四转接部404将第二晶体管M2的第二端连接至驱动晶体管M3的第二端。
第三有源部23用于形成驱动晶体管M3的沟道区，第五子有源部205、第六子有源部206连接于第三有源部23的两侧以分别形成驱动晶体管M3的第一端和第二端，第五子有源部205可通过过孔连接位于第三导电层4的第五转接部405，以将驱动晶体管M3的第一端连接第三节点N3。第六子有源部206可通过过孔连接第四转接部404，以将驱动晶体管M3的第二端连接第二节点N2，即连接第二晶体管M2的第二端。
第四有源部24用于形成第四晶体管M4的沟道区，第七子有源部207、第八子有源部208连接于第四有源部24的两侧以分别形成第四晶体管M4的第一端和第二端，第七子有源部207可通过过孔连接数据信号线Data以将第四晶体管M4的第一端连接数据信号端Vdata，第八子有源部208可通过过孔连接位于第三导电层4的第五转接部405，以通 过该第五转接部405将第四晶体管M4的第二端连接至第三节点N3。
第五有源部25用于形成第五晶体管M5的沟道区，第九子有源部209、第十子有源部210分别连接于第五有源部25的两端以形成第五晶体管M5的第一端和第二端，第九子有源部209可通过过孔连接第十七导电块417(具体可连接第十七导电块417的子导电部)，以将第五晶体管M5的第一端连接第一电源端VDD，第十子有源部210可通过过孔连接第五转接部405以将第五晶体管M5的第二端连接第三节点N3。
第六有源部26用于形成第六晶体管M6的沟道区，第十一子有源部211、第十二子有源部212连接于第六有源部26的两端以分别形成第六晶体管M6的第一端和第二端，第十一子有源部211可通过过孔连接第四转接部404以将第六晶体管M6的第一端连接第二节点N2，第十二子有源部212可通过过孔连接第六转接部406以将第六晶体管M6的第二端连接第四节点N4。
第七有源部27用于形成第七晶体管M7的沟道区，第二子有源部202、第十四子有源部214连接于第七有源部27的两侧以形成第七晶体管M7的第一端和第二端，第二子有源部202可通过过孔连接第二转接部402，以将第七晶体管M7的第一端通过该第二转接部402连接至初始信号端Vinit，第十四子有源部214可通过过孔连接第六转接部406，以通过该第六转接部406将第七晶体管M7的第二端连接第四节点N4。
第八有源部28用于形成第八晶体管M8的沟道区，第十五子有源部215、第十六子有源部216连接于第八有源部28的两端以分别形成第八晶体管M8的第一端和第二端，第十五子有源部215可通过过孔连接数据信号线Data以将第八晶体管M8的第一端连接数据信号端Vdata，第十六子有源部216可通过过孔连接第七转接部407，通过第七转接部407连接第一电容C1的第一电极。
第九有源部29用于形成第九晶体管M9的沟道区，第十七子有源部217、第十八子有源部218连接于第九有源部29的两侧以分别形成第九晶体管M9的第一端和第二端，第十七子有源部217可通过过孔连接第十导电块310,(第十导电块310通过过孔连接第八转接部408)，以通过该第十导电块310将第九晶体管M9的第一端连接使能信号端EM，第十 八子有源部218可通过过孔连接第九转接部409，以通过第九转接部409将第九晶体管M9的第二端连接第六晶体管M6的栅极。
第十有源部230用于形成第十晶体管M10的沟道区，第十九子有源部219、第二十子有源部220连接于第十有源部230的两侧以分别形成第十晶体管M10的第一端和第二端，第十九子有源部219可通过过孔连接数据信号线Data，以将第十晶体管M10的第一端连接数据信号端Vdata。第二十子有源部220可通过过孔连接第十一转接部411，第十一转接部411可通过过孔连接第九导电块39第九导电块39，第九导电块39又通过过孔连接第十二转接部412，第十二转接部412的另一端通过过孔连接第二导电块32(第二电容C2的第二电极)，从而通过将第十晶体管M10的第二端连接第二电容C2的第二电极。
第十一有源部240用于形成第十一晶体管M11的沟道区，第二十一子有源部221、第二十二子有源部222连接于第十一有源部240的两侧以分别形成第十晶体管M10的第一端和第二端，第二十一子有源部221可通过过孔连接第十六转接部416，由第十六转接部416通过第七导电块37连接第二高频信号线HF2，进而将第十一晶体管M11的第一端连接至高频信号端HF。第二十二子有源部222可通过过孔连接第九转接部409，由第九转接部409将第十一晶体管M11的第二端连接至第六晶体管M6的栅极。
第十二有源部250用于形成第十二晶体管M12的沟道区，第二十三子有源部223、第二十四子有源部224连接于第十二有源部250的两侧以分别形成第十二晶体管M12的第一端和第二端，第二十三子有源部223可通过过孔连接第六转接部406，以通过第六转接部406将第十二晶体管M12的第一端连接至第四节点N4。第二十四子有源部224可通过过孔连接第十三转接部413，以通过第十三转接部413将第十二晶体管M12的第二端连接至第一子像素的第一电极。
第十三有源部260用于形成第十三晶体管M13的沟道区，第二十五子有源部225、第二十六子有源部226连接于第十三有源部260的两侧以分别形成第十三晶体管M13的第一端和第二端，第二十五子有源部225可通过过孔连接第六转接部406，以通过第六转接部406将第十三晶 体管M13的第一端连接至第四节点N4。第二十六子有源部226可通过过孔连接第十四转接部414，以通过第十四转接部414将第十三晶体管M13的第二端连接至第二子像素的第一电极。
第十四有源部270用于形成第十四晶体管M14的沟道区，第二十七子有源部227、第二十八子有源部228连接于第十四有源部270的两侧以分别形成第十四晶体管M14的第一端和第二端，第二十七子有源部227可通过过孔连接第六转接部406，以通过该第六转接部406将第十四晶体管M14的第一端连接至第四节点N4。第二十八子有源部228可通过过孔连接第十五转接部415，以通过该第十五转接部415将第十四晶体管M14的第二端连接至第三子像素的第一电极。
本公开有源层2可以由多晶硅半导体材料形成，相应的，本公开显示面板中的晶体管可以为P型低温多晶硅薄膜晶体管。
如图11、图14所示，在示例性实施例中，第二导电层3可以包括第一导电块31、第二导电块32、第三导电块33，第一导电块31在衬底基板的正投影位于第一导电部101在衬底基板的正投影上，第一导电块31用于形成第一电容C1的第二电极。第二导电块32在衬底基板的正投影位于第二导电部102在衬底基板的正投影上，第二导电块32用于形成第二电容C2的第二电极。第三导电块33可以包括第一组成部331、第二组成部332和第三组成部333，第一组成部331在衬底基板的正投影位于第三导电部103在衬底基板的正投影上，第三导电块33的第一组成部331用于形成存储电容Cst的第二电极。第三导电块33的第二组成部332在衬底基板的正投影沿列方向Y延伸，第三导电块33的第三组成部333在衬底基板的正投影沿行方向X延伸，第三导电块33的第二组成部332连接于第一组成部331和第三组成部333之间，第三导电块33的第三组成部333在衬底基板的正投影覆盖第三有源部23在衬底基板的正投影，第三导电块33的第三组成部333的部分结构用于形成驱动晶体管M3的栅极。
如图11、图14所示，在示例性实施例中，第二导电层3还可以包括第四导电块34～第七导电块37，第四导电块34在衬底基板的正投影 覆盖第九有源部29在衬底基板的正投影，第四导电块34的部分结构用形成第九晶体管M9的栅极。第四导电块34通过过孔连接第七转接部407以将第九晶体管M9的栅极通过第七转接部407连接至第一电容C1的第二电极。第五导电块35在衬底基板的正投影可以沿行方向X延伸，第五导电块35分别通过过孔连接第九转接部409和第十转接部410，而第九转接部409又通过过孔连接第十八子有源部218(第九晶体管M9的第二端)和第二十二子有源部222(第十一晶体管M11的第二端)、第十转接部410又通过过孔连接第六导电块36(形成第六晶体管M6的栅极)，从而通过第九转接部409和第十转接部410将第九晶体管M9的第二端和第十一晶体管M11的第二端连接第六晶体管M6的栅极。第六导电块36可以包括第一子导电块361和多个第二子导电块362，第一子导电块361在衬底基板的正投影可以沿列方向Y延伸，第二子导电块362在衬底基板的正投影可以沿行方向X延伸，多个第二子导电块362与多个第六有源部26一一对应设置，第二子导电块362在衬底基板的正投影覆盖第六有源部26在衬底基板的正投影，第二子导电块362可用于形成第六晶体管M6的栅极。第七导电块37在衬底基板的正投影可以沿行方向X延伸，第七导电块37可通过过孔连接第十六转接部416和第二高频信号线HF2，从而通过第十六转接部416将第十一晶体管M11的第一端连接至高频信号端HF。
如图11、图14所示，在示例性实施例中，第二导电层3还可以包括第一高频信号线HF1、第三电源线VSS2、第二电源线VSS1、初始信号线Vinit、第二复位信号线RSTB、第一复位信号线RSTA、第一电源线VDD、使能信号线EM和栅极信号线Gate，第一高频信号线HF1、第三电源线VSS2、第二电源线VSS1、初始信号线Vinit、第二复位信号线RSTB、第一复位信号线RSTA、第一电源线VDD、使能信号线EM和栅极信号线Gate在衬底基板的正投影均沿行方向X延伸且在列方向Y依次间隔分布，其中，第一高频信号线HF1、第三电源线VSS2和第二电源线VSS1位于第一导电块31远离第三导电块33的一侧，第一高频信号线HF1用于形成图8中的高频信号端HF，第一高频信号线HF1可通过过孔连接第三导电层4的第二高频信号线HF2。第三电源线VSS2用 于形成图8中的第二子像素的第二电源端和第三子像素的第二电源端，第二电源线VSS1用于形成图8中第一子像素的第二电源端。
如图14所示，在示例性实施例中，初始信号线Vinit、第二复位信号线RSTB、第一复位信号线RSTA、第一电源线VDD、使能信号线EM位于第一导电块31和第三导电块33之间。初始信号线Vinit用于形成图8中的初始信号端Vinit，初始信号线Vinit分别通过过孔连接第三导电层4的第二转接部402、第十八导电块418和第十九导电块419。第二复位信号线RSTB用于形成图8中的第二复位信号端RSTB，第二复位信号线RSTB在衬底基板的正投影部分覆盖第八有源部28在衬底基板的正投影，第二复位信号线RSTB的部分结构用于形成第八晶体管M8的栅极。第一复位信号线RSTA用于形成图8中的第一复位信号端RSTA，第一复位信号线RSTA在衬底基板的正投影部分覆盖第一有源部21在衬底基板的正投影、部分覆盖第七有源部27在衬底基板的正投影、部分覆盖第十有源部230在衬底基板的正投影，第一复位信号线RSTA的部分结构用于形成第一晶体管M1的栅极、部分结构用于形成第七晶体管M7的栅极、部分结构用于形成第十晶体管M10的栅极。第一电源线VDD用于形成图8中的第一电源端VDD，第一电源线VDD通过过孔连接第三导电层4的第十七导电块417，以将存储电容Cst的第一电极连接至第一电源端VDD。使能信号线EM用于形成图8中的使能信号端EM，使能信号线EM包括主体部EM0、第一子延伸部EM1和多个第二子延伸部EM2，使能信号线EM的主体部EM0和第二子延伸部EM2在衬底基板的正投影沿行方向X延伸，使能信号线EM的第一子延伸部EM1在衬底基板的正投影沿列方向Y延伸，多个第二子延伸部EM2通过第一子延伸部EM1连接主体部EM0，多个第二子延伸部EM2与多个第五有源部25一一对应设置且第二子延伸部EM2在衬底基板的正投影覆盖第五有源部25在衬底基板的正投影，第二子延伸部EM2用于形成第五晶体管M5的栅极。栅极信号线Gate位于第二十导电块500远离第一导电块31的一侧，栅极信号线Gate用于形成图8中的栅极信号端Gate，栅极信号线Gate在衬底基板的正投影部分覆盖第二有源部22在衬底基板的正投影、部分覆盖第四有源部24在衬底基板的正投影，栅极信号线Gate 的部分结构用于形成第二晶体管M2的栅极、部分结构用于形成第四晶体管M4的栅极。
如图11、图14所示，在示例性实施例中，第二导电层3还可以包括第九导电块39和第十导电块310，第九导电块39在衬底基板的正投影覆盖第十一有源部240在衬底基板的正投影，第九导电块39的部分结构用于形成第十一晶体管M11的栅极。第九导电块39还分别通过过孔连接第十一转接部411和第十二转接部412(第十二转接部412还连接第二导电块32)，从而将第十一晶体管M11的栅极、第十晶体管M10的第二端分别连接至第二电容C2的第二电极。第十导电块310分别通过过孔连接第十七子有源部217和第八转接部408，以将第九晶体管M9的第一端连接至使能信号端EM。
如图11、图14所示，在示例性实施例中，第二导电层3还可以包括多个第十二导电块312、多个第十三导电块313和多个第十四导电块314，多个第十二导电块312与多个第十二有源部250一一对应设置，第十二有源部250在衬底基板的正投影覆盖第十二有源部250在衬底基板的正投影，第十二有源部250用于形成第十二晶体管M12的栅极。多个第十三导电块313与多个第十三有源部260一一对应设置，第十三导电块313在衬底基板的正投影覆盖第十三有源部260在衬底基板的正投影，第十三导电块313用于形成第十三晶体管M13的栅极。多个第十四导电块314与多个第十四有源部270一一对应设置，第十四导电块314在衬底基板的正投影覆盖第十四有源部270在衬底基板的正投影，第十四导电块314用于形成第十四晶体管M14的栅极。
本公开显示面板可以以第二导电层3为掩膜对有源层2进行导体化处理，即被第二导电层3覆盖的有源层2形成晶体管的沟道区，未被第二导电层3覆盖的区域形成导体结构。
应该理解的是，本公开所述的某一结构A在衬底基板的正投影覆盖另一结构B在衬底基板的正投影可以理解为，B在衬底基板平面的投影的轮廓完全位于A在同一平面内投影的轮廓的内部。
此外，本公开所述的某一结构A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分为线、线段或条形状体， 主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其他方向伸展的长度。
如图11、图15所示，在示例性实施例中，第三导电层4可以包括第一转接部401～第十六转接部416，其中，第一转接部401的一端通过过孔连接第一子有源部201以连接第一晶体管M1的第一端，第一转接部401的另一端通过过孔连接第二导电层3的第三导电块33，以通过该第一转接部401将第一晶体管M1的第一端连接至存储电容Cst的第二电极。第二转接部402的一端通过过孔连接第二子有源部202以连接第一晶体管M1的第二端和第七晶体管M7的第一端，第二转接部402的另一端通过过孔连接第二导电层3的初始信号线Vinit，以通过该第二转接部402将第一晶体管M1的第二端和第七晶体管M7的第一端连接至初始信号端Vinit。第三转接部403的一端通过过孔连接第三子有源部203以连接第二晶体管M2的第一端，第三转接部403的另一端通过过孔连接第三导电块33(具体可连接第三导电块33的第三组成部333)，以通过该第三转接部403将第二晶体管M2的第一端连接至存储电容Cst的第二电极，即图8中的第一节点N1。第四转接部404分别通过过孔连接第四子有源部204、第六子有源部206、第十一子有源部211以分别连接第第二晶体管M2的第二端、驱动晶体管M3的第二端和第六晶体管M6的第一端。
如图15所示，在示例性实施例中，第五转接部405可分别通过过孔连接第五子有源部205和第八子有源部208，以分别连接驱动晶体管M3的第一端和第四晶体管M4第二端，第五转接部405还通过过孔连接第十子有源部210，以将驱动晶体管M3的第一端、第四晶体管M4的第二端以及第五晶体管M5的第二端连接第三节点N3。第六转接部406可用于形成图8中的第四节点N4，第六转接部406的部分结构在衬底基板的正投影覆盖第十二子有源部212在衬底基板的正投影、部分结构在衬底基板的正投影覆盖第二十三子有源部223在衬底基板的正投影、部分结构在衬底基板的正投影覆盖第二十五子有源部225在衬底基板的正投影、部分结构在衬底基板的正投影覆盖第二十七子有源部227在衬底基板的正投影，第六转接部406可分别通过过孔连接第十二子有源部212、第 二十三子有源部223、第二十五子有源部225和第二十七子有源部227，以分别连接第六晶体管M6的第二端、第十二晶体管M12的第一端、第十三晶体管M13的第一端和第十四晶体的第一端。第七转接部407可分别通过过孔连接第一导电块31、第十六子有源部216和第四导电块34，以将第八晶体管M8的第二端、第九晶体管M9的栅极分别连接第一电容C1的第二电极。第八转接部408分别通过过孔连接第十七子有源部217和使能信号线EM，以将第九晶体管M9的第一端通过该第八转接部408连接使能信号端EM。
如图15所示，在示例性实施例中，第九转接部409的一端通过过孔连接第五导电块35，另一端分别通过过孔连接第十八子有源部218和第二十二子有源部222，以将第九晶体管M9的第二端和第十一晶体管M11的第二端连接第六晶体管M6的栅极。第十转接部410可通过过孔连接第六导电块36(形成第六晶体管M6的栅极)和第五导电块35。第十一转接部411分别通过过孔连接第二十子有源部220和第九导电块39，第十二转接部412分别通过过孔连接第九导电块39和第二导电块32，从而第十晶体管M10的第二端、第十一晶体管M11的栅极被连接至第二电容C2的第二电极。
如图15所示，在示例性实施例中，第十三转接部413通过过孔连接第二十四子有源部224和第一子像素的第一电极P-AOD，以将第十二晶体管M12的第二端连接第一子像素的第一电极P-AOD。第十四转接部414通过过孔连接第二十六子有源部226，以将第十三晶体管M13的第二端连接至第二子像素的第一电极P-AOD。第十五转接部415可通过过孔连接第二十八子有源部228，以将第十四晶体管M14的第二端连接至第三子像素的第一电极P-AOD。
如图15所示，在示例性实施例中，第十六转接部416分别通过过孔连接第二十一子有源部221和第七导电块37(第七导电块37连接第二高频信号线HF2)，从而将第十一晶体管M11的第一端连接至高频信号端HF。
如图11、图15所示，在示例性实施例中，第三导电层4还可以包括第十七导电块417～第十九导电块419，其中，第十七导电块417可以 包括主导电部4171和子导电部4172，主导电部4171在衬底基板的正投影位于第三导电部103在衬底基板的正投影上，且主导电部4171可通过过孔连接第三导电部103，第十七导电块417与第三导电部103分别用于形成存储电容Cst的第一电极。第十七导电块417的子导电部4172通过过孔连接第九子有源部209以连接第五晶体管M5的第一端。第十八导电块418在衬底基板的正投影位于第一导电部101在衬底基板的正投影上，第十八导电块418与第一导电部101通过过孔连接，第十八导电块418和第一导电部101用于形成第一电容C1的第一电极。第十九导电块419在衬底基板的正投影位于第二导电部102在衬底基板的正投影上，第十九导电块419与第二导电部102通过过孔连接，第十九导电块419和第二导电部102用于形成第二电容C2的第一电极。可以理解的是，通过在第三导电层4设置第十七导电块417连接第一导电层1的第三导电部103，以与第一导电部101形成并联结构，由此可以减小形成存储电容Cst的第一电极的阻值，从而有助于减小存储电容Cst上的压降损耗。同样地，通过在第三导电层4设置第十八导电块418与第一导电部101形成并联结构，可以减小第一电容C1的第一电极上的压降损耗，所设置的第十九导电块419与第二导电部102形成并联结构，可以减小第二电容C2的第一电极上的压降损耗。
如图15所示，在示例性实施例中，第三导电层4还可以包括数据信号线Data，数据信号线Data可用于形成图8中的数据信号端Vdata，数据信号线Data在所述衬底基板的正投影沿列方向Y延伸，数据信号线Data可分别通过过孔连接第七子有源部207、第十五子有源部215和第十九子有源部219，以分别将第四晶体管M4的第一端、第八晶体管M8的第一端和第十晶体管M10的第一端连接至数据信号端Vdata。
如图11、图16所示，在示例性实施例中，第四导电层5可以包括第二十导电块500～第二十五导电块505，其中，第二十导电块500用于形成第一子像素的第一电极P-AOD，第二十导电块500可通过过孔连接第十三转接部413，以通过第十三转接部413将第一子像素的第一电极P-AOD连接至第十二晶体管M12的第二端。第二十一导电块501用于 形成第二子像素的第一电极P-AOD，第二十一导电块501可通过过孔连接第十四转接部414，以通过第十四转接部414将第二子像素的第一电极P-AOD连接至第十三晶体管M13的第二端。第二十二导电块502用于形成第三子像素的第一电极P-AOD，第二十二导电块502可通过过孔连接第十五转接部415，以通过该第十五转接部415将第三子像素的第一电极P-AOD连接至第十四晶体管M14的第二端。
第二十三导电块503用于形成第一子像素的第二电极P-CTO，第二十三导电块503可通过过孔连接第二导电层3的第二电源线VSS1，以将第一子像素的第二电极P-CTO连接至对应的第二电源端。第二十四导电块504用于形成第二子像素的第二电极P-CTO，第二十五导电块505用于形成第三子像素的第二电极P-CTO，第二十四导电块504、第二十五导电块505可分别通过过孔连接第二导电层3的第三电源线VSS2，以将第二子像素的第二电极P-CTO和第三子像素的第二电极P-CTO连接至对应的第二电源端。
如图11所示，在示例性实施例中，像素单元中，形成像素驱动电路P-Drive的版图结构在衬底基板的正投影位于子像素的第一电极P-AOD在衬底基板的正投影远离第二电极P-CTO在衬底基板的正投影的一侧，并且形成开关电路MSW的版图结构在衬底基板的正投影位于子像素的第一电极P-AOD在衬底基板的正投影和子像素的第二电极P-CTO在衬底基板的正投影之间。当然，在其他实施例中，像素单元中的像素驱动电路P-Drive、开关电路MSW以及子像素的第一电极和第二电极还可以具有其他的版图结构，例如，形成开关电路MSW的版图结构可以位于子像素的第一电极和第二电极的下方，即形成开关电路MSW的版图结构在衬底基板的正投影与子像素的第一电极和第二电极在衬底基板的正投影可以交叠，这些都属于本公开的保护范围，此处不再详述。
图17为图11中沿虚线AA的部分剖视图，如图17所示，该显示面板可以包括第一绝缘层81、第二绝缘层82、第三绝缘层83、层间介电层ILD、第四绝缘层84、第一平坦层PLN1、第一钝化层PVX1、第二平坦层PLN2和第二钝化层PVX2，其中，衬底基板80、第一绝缘层81、第一导电层1、第二绝缘层82、有源层2、第三绝缘层83、第二导电层 3、层间介电层ILD、第四绝缘层84、第三导电层4、第一平坦层PLN1、第一钝化层PVX1、第四导电层5、第二平坦层PLN2、第二钝化层PVX2依次层叠设置。第一绝缘层81、第二绝缘层82可以氧化硅层，第一介电层86可以为氮化硅层。衬底基板可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层1、第二导电层3的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层4、第四导电层5的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。
本公开还提供一种显示装置，该显示装置可以包括本公开任意实施例所述的显示面板。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (21)

  1. 一种显示面板，其中，包括沿行列方向阵列分布的多个像素单元，所述像素单元包括：
    像素驱动电路，用于提供驱动电流；
    多个子像素，所述子像素的第一电极用于连接所述像素驱动电路，所述子像素的第二电极连接第二电源端，所述子像素在所述驱动电流的作用下发光；
    开关电路，包括多个开关单元，所述开关单元与所述子像素对应设置，所述开关单元串接于所述像素驱动电路与对应子像素之间，所述开关单元的控制端用于接收开关信号，所述开关单元的第一端连接所述像素驱动电路，所述开关单元的第二端连接对应子像素的第一电极，所述开关单元响应于所述开关信号导通所述子像素与所述像素驱动电路的连通路径。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板包括衬底基板；
    同一像素单元中，所述像素驱动电路在所述衬底基板的正投影位于所述子像素的第一电极在所述衬底基板的正投影远离所述第二电极在所述衬底基板的正投影的一侧，所述开关单元在所述衬底基板的正投影位于对应所述子像素的第一电极在所述衬底基板的正投影和第二电极在所述衬底基板的正投影之间。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第一驱动电路，位于所述显示面板的显示区，所述第一驱动电路用于输出栅极控制信号；
    所述像素驱动电路响应于所述栅极控制信号将数据信号端的数据信号传输至驱动信号端。
  4. 根据权利要求3所述的显示面板，其中，
    所述第一驱动电路包括多个级联的第一移位寄存器单元，向本行像素单元提供栅极控制信号的第一移位寄存器单元位于本行像素单元和下一行像素单元之间。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    开关驱动电路，位于所述显示面板的显示区，所述开关驱动电路用于输出所述开关信号。
  6. 根据权利要求5所述的显示面板，其中，所述开关驱动电路包括多个子开关驱动电路，一个子开关驱动电路驱动一列开关单元；
    所述子开关驱动电路包括多个级联的第三移位寄存器单元，向本行开关电路提供开关信号的第三移位寄存器单元位于本行像素单元和下一行像素单元之间的间隙内。
  7. 根据权利要求5所述的显示面板，其中，所述像素单元包括第一子像素、第二子像素和第三子像素；
    所述开关电路包括第一开关单元、第二开关单元和第三开关单元，所述第一开关单元对应连接所述第一子像素，所述第二开关单元对应连接所述第二子像素，所述第三开关单元对应连接所述第三子像素；
    所述开关驱动电路包括第一子开关驱动电路、第二子开关驱动电路和第三子开关驱动电路，所述第一子开关驱动电路用于向所述第一开关单元输出第一开关信号，所述第二子开关驱动电路用于向所述第二开关单元输出第二开关信号，所述第三子开关单元用于向所述第三开关单元输出第三开关信号；
    其中，所述第一子开关驱动电路、所述第二子开关驱动电路和所述第三子开关驱动电路先后逐行输出所述第一开关信号、所述第二开关信号和所述第三开关信号；
    且在所述第一子开关驱动电路输出所述第一开关信号的时间内、在所述第二子开关驱动电路输出所述第二开关信号的时间内以及在所述第三子开关驱动电路输出所述第三开关信号的时间内，所述第一驱动电路分别输出所述栅极控制信号。
  8. 根据权利要求5-7任一项所述的显示面板，其中，所述显示面板包括两个所述开关驱动电路，两个所述开关驱动电路沿行方向分开设置于所述显示区的两侧。
  9. 根据权利要求3所述的显示面板，其中，所述显示面板还包括：
    驱动集成电路，用于分别向各所述开关单元输出所述开关信号。
  10. 根据权利要求9所述的显示面板，其中，所述第一驱动电路位 于所述显示面板的非显示区。
  11. 根据权利要求10所述的显示面板，其中，所述像素单元包括第一子像素、第二子像素和第三子像素；
    所述开关电路包括第一开关单元、第二开关单元和第三开关单元，所述第一开关单元对应连接所述第一子像素，所述第二开关单元对应连接所述第二子像素，所述第三开关单元对应连接所述第三子像素；
    其中，在一帧数据中，所述驱动集成电路先后依次输出第一开关信号、第二开关信号和第三开关信号；
    在所述驱动集成电路输出所述第一开关信号的时间内，所述第一驱动电路依次向各像素驱动电路输出第一栅极控制信号，所述像素驱动电路响应于所述第一栅极控制信号向所述第一子像素提供驱动电流；
    在所述驱动集成电路输出所述第二开关信号的时间内，所述第一驱动电路依次向各像素驱动电路输出第二栅极控制信号，所述像素驱动电路响应于所述第二栅极控制信号向所述第二子像素提供驱动电流；
    在各所述驱动集成电路输出所述第三开关信号的时间内，所述第一驱动电路依次向各像素驱动电路输出第三栅极控制信号，所述像素驱动电路响应于所述第三栅极控制信号向所述第三子像素提供驱动电流。
  12. 根据权利要求11所述的显示面板，其中，在一帧数据中，所述第一开关信号、所述第二开关信号和所述第三开关信号的持续时长相同。
  13. 根据权利要求11所述的显示面板，其中，所述第一驱动电路按照第一频率输出栅极控制信号，所述驱动集成电路按照第二频率输出开关信号，所述第一频率为所述第二频率的3倍。
  14. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括：
    驱动模块，连接第一节点、第二节点和第三节点，所述驱动模块用于响应所述第一节点的电压信号利用所述第二节点和所述第三节点的电压差提供驱动电流；
    第一复位模块，连接第一节点、第一复位信号端和初始信号端，所述第一复位模块用于响应所述第一复位信号端的复位信号将所述初始信号端的初始信号传输至所述第一节点；
    传输模块，连接所述第一节点、栅极信号端和所述第二节点，所述传输模块用于响应所述栅极信号端的信号导通所述第一节点和所述第二节点的连通路径；
    数据写入模块，连接数据信号端、所述栅极信号端和所述第三节点，所述数据写入模块用于响应所述栅极信号端的信号将所述数据信号端的第二数据信号传输至所述第三节点；
    第二复位模块，连接第四节点、所述初始信号端和所述第一复位信号端，所述第二复位模块用于响应所述第一复位信号端的复位信号将所述初始信号端的初始信号传输至所述第四节点；
    第一发光控制模块，连接所述第三节点、使能信号端和第一电源端，所述第一发光控制模块用于响应所述使能信号端的使能信号导通所述第三节点与所述第一电源端的连通路径；
    第二发光控制模块，连接所述第二节点、所述第四节点和调节模块，所述第二发光控制模块用于响应所述调节模块的信号导通所述第四节点与所述第二节点的连通路径；
    调节模块，连接数据信号端、第二复位信号端、第一复位信号端、初始信号端和使能信号端，所述调节模块用于响应所述数据信号端的第一数据信号关闭所述第二发光控制模块，或者用于响应所述数据信号端的第二数据信号打开所述第二发光控制模块。
  15. 根据权利要求14所述的显示面板，其中，
    所述驱动模块包括：
    驱动晶体管，控制端连接所述第一节点，第一端连接所述第三节点，第二端连接所述第二节点；
    所述第一复位模块包括：
    第一晶体管，控制端连接第一复位信号端，第一端连接所述第一节点，第二端连接所述初始信号端；
    所述传输模块包括：
    第二晶体管，控制端连接栅极信号端，第一端连接所述第一节点，第二端连接所述第二节点；
    所述数据写入模块包括：
    第四晶体管，控制端连接所述栅极信号端，第一端连接所述数据信号端，第二端连接所述第三节点；
    所述第二复位模块包括：
    第七晶体管，控制端连接所述第一复位信号端，第一端连接初始信号端，第二端连接所述第四节点；
    所述第一发光控制模块包括：
    第五晶体管，控制端连接所述使能信号端，第一端连接所述第一电源端，第二端连接所述第三节点；
    所述第二发光控制模块包括：
    第六晶体管，控制端连接第七节点，第一端连接所述第二节点，第二端连接第四节点；
    所述调节模块包括：
    第八晶体管，控制端连接第二复位信号端，第一端连接所述数据信号端，第二端连接第五节点，所述第八晶体管用于响应所述第二复位信号端的复位信号将所述数据信号端的数据信号传输至所述第五节点；
    第九晶体管，控制端连接所述第五节点，第一端连接所述使能信号端，第二端连接所述第七节点，所述第九晶体管用于响应所述第五节点的电压信号将所述使能信号端的使能信号传输至所述第七节点；
    第一电容，连接所述第五节点和所述初始信号端，所述第一电容用于存储写入所述第五节点的电压信号；
    第十晶体管，控制端连接所述第一复位信号端，第一端连接所述数据信号端，第二端连接第六节点，所述第十晶体管用于响应所述第一复位信号端的复位信号将所述数据信号端的数据信号传输至所述第六节点；
    第十一晶体管，控制端连接所述第六节点，第一端连接高频信号端，第二端连接所述第七节点，所述第十一晶体管用于响应所述第六节点的电压信号将所述高频信号端的信号传输至所述第七节点；
    第二电容，连接所述第六节点和所述使能信号端，所述第二电容用于存储写入所述第六节点的电压信号。
  16. 根据权利要求15所述的显示面板，其中，所述开关单元为晶体管。
  17. 根据权利要求16所述的显示面板，其中，所述像素单元包括第一子像素、第二子像素和第三子像素，所述开关电路包括第十二晶体管、第十三晶体管和第十四晶体管；
    所述第十二晶体管的控制端接收第一开关信号，所述第十二晶体管的第一端连接第四节点，所述第十二晶体管的第二端连接第一子像素的第一电极；
    所述第十三晶体管的控制端接收第二开关信号，所述第十三晶体管的第一端连接第四节点，所述第十三晶体管的第二端连接第二子像素的第一电极；
    所述第十四晶体管的控制端接收第三开关信号，所述第十四晶体管的第一端连接第四节点，所述第十四晶体管的第二端连接第三子像素的第一电极。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板包括：
    衬底基板；
    第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：
    第三导电部，用于形成所述存储电容的第一电极；
    有源层，位于所述第一导电层被背离所述衬底基板的一侧，所述有源层包括：
    第一有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第一有源部用于形成所述第一晶体管的沟道区；
    第一子有源部，连接于所述第一有源部的一侧，用于形成所述第一晶体管的第一端；
    第二子有源部，连接于所述第一有源部的另一侧，用于形成所述第一晶体管的第二端和所述第七晶体管的第一端；
    第七有源部，与所述第二子有源部连接，所述第七有源部用于形成第七晶体管的沟道区；
    第十四子有源部，连接于所述第七有源部的另一侧，用于形成所述第七晶体管的第二端；
    第三有源部，在所述衬底基板的正投影沿列方向位于所述第三导电 部在所述衬底基板的正投影的一侧，所述第三有源部用于形成所述驱动晶体管的沟道区；
    第五子有源部，沿列方向连接于所述第三有源部的一侧，所述第五子有源部用于形成所述驱动晶体管的第一端；
    第六子有源部，连接于所述第三有源部的另一侧，所述第六子有源部用于形成所述驱动晶体管的第二端；
    第二有源部，沿行方向位于所述第三有源部的一侧，所述第二有源部用于形成所述第二晶体管的沟道区；
    第三子有源部，沿行方向连接于所述第二有源部靠近所述第三有源部的一侧，所述第三子有源部用于形成所述第二晶体管的第一端；
    第四子有源部，连接于所述第二有源部远离所述第三有源部的一侧，所述第四子有源部用于形成所述第二晶体管的第二端；
    第四有源部，位于所述第三有源部远离所述第二有源部的一侧，所述第四有源部用于形成所述第四晶体管的沟道区；
    第七子有源部，连接于所述第四有源部远离所述第三有源部的一侧，所述第七子有源部用于形成所述第四晶体管的第一端；
    第八子有源部，连接于所述第四有源部靠近所述第三有源部的一侧，所述第八子有源部用于形成所述第四晶体管的第二端；
    第五有源部，在所述衬底基板的正投影位于所述第三有源部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第五有源部用于形成所述第五晶体管的沟道区；
    第九子有源部，连接于所述第五有源部远离所述第三有源部的一侧，所述第九子有源部用于形成所述第五晶体管的第一端；
    第十子有源部，连接于所述第五有源部靠近所述第三有源部的一侧，所述第十子有源部用于形成所述第五晶体管的第二端；
    第六有源部，沿行方向位于所述第五有源部的一侧，所述第六有源部用于形成所述第六晶体管的沟道区；
    第十一子有源部，连接于所述第六有源部靠近所述第三有源部的一侧，所述第十一子有源部用于形成所述第六晶体管的第一端；
    第十二子有源部，连接于所述第六有源部的另一端，所述第十二子 有源部用于形成所述第六晶体管的第二端；
    第二导电层，位于所述有源层背离所述衬底基板的一侧，所述第二导电层包括：
    第三导电块，所述第三导电块包括依次连接的第一组成部、第二组成部和第三组成部，所述第一组成部在所述衬底基板的正投影与所述第三导电部在所述衬底基板的正投影部分交叠，所述第三组成部在所述衬底基板的正投影覆盖所述第三有源部在所述衬底基板的正投影，所述第三导电块的部分结构用于形成所述存储电容的第二电极、部分结构用于形成所述驱动晶体管的顶栅；
    栅极信号线，在所述衬底基板的正投影沿行方向延伸，所述栅极信号线在所述衬底基板的正投影位于所述第三组成部在所述衬底基板的正投影远离所述第一组成部在所述衬底基板的一侧，所述栅极信号线在所述衬底基板的正投影部分覆盖所述第二有源部在所述衬底基板的正投影、部分覆盖所述第四有源部在所述衬底基板的正投影，所述栅极信号线的部分结构用于形成所述第二晶体管的栅极、部分结构用于形成所述第四晶体管的栅极；
    使能信号线，包括依次连接的主体部、第一子延伸部和第二子延伸部，所述主体部在所述衬底基板的正投影位于所述第三导电块在所述衬底基板的正投影远离所述栅极信号在所述衬底基板的正投影的一侧，所述第二子延伸部在所述衬底基板的正投影覆盖所述第五有源部在所述衬底基板的正投影，所述使能信号线的部分结构用于形成所述第五晶体管的栅极；
    第六导电块，包括第一子导电块和第二子导电块，所述第一子导电块在所述衬底基板的正投影沿列方向延伸，所述第二子导电块在所述衬底基板的正投影覆盖所述第六有源部在所述衬底基板的正投影，所述第六导电块的部分结构用于形成所述第六晶体管的栅极；
    第一复位信号线，在所述衬底基板的正投影沿行方向延伸且位于所述第三导电块在所述衬底基板的正投影远离所述第三有源部在所述衬底基板的正投影的一侧，所述第一复位信号线在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影和所述第七有源部在所述衬 底基板的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极和所述第七晶体管的栅极；
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：
    第三转接部，所述第三转接部的一端通过过孔连接所述第三子有源部，另一端通过过孔连接所述第三导电块；
    第四转接部，分别通过过孔连接所述第四子有源部、所述第六子有源部和所述第十一子有源部；
    第五转接部，分别通过过孔连接所述第五子有源部、所述第八子有源部和所述第十子有源部；
    第六转接部，通过过孔连接所述第十二子有源部；
    第十七导电块，包括主导电部和子导电部，所述主导电部在所述衬底基板的正投影位于所述第三导电块在所述衬底基板的正投影上，所述第十七导电块分别通过过孔连接所述第三导电部和所述第九子有源部，所述第十七导电块的部分结构用于形成所述存储电容的第一电极，部分结构用于形成所述第五晶体管的第一端；
    数据信号线，在所述衬底基板的正投影沿列方向延伸，所述数据线通过过孔连接所述第七子有源部。
  19. 根据权利要求18所述的显示面板，其中，
    所述第一导电层还包括：
    第一导电部，用于形成所述第一电容的第一电极；
    第二导电部，用于形成所述第二电容的第二电极；
    第四导电部，位于所述第三导电部远离所述第一导电部的一侧，所述第四导电部在所述衬底基板的正投影覆盖所述第三有源部在所述衬底基板的正投影，所述第四导电部用于形成所述驱动晶体管的底栅；
    第五导电部，连接于所述第四导电部的一侧，所述第五导电部通过过孔连接所述第三转接部；
    所述有源层还包括：
    第八有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所 述第八有源部用于形成第八晶体管的沟道区；
    第十五子有源部，连接于所述第八有源部的一侧，用于形成所述第八晶体管的第一端；
    第十六子有源部，连接于所述第八有源部的另一侧，用于形成所述第八晶体管的第二端；
    第九有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第九有源部用于形成所述第九晶体管的沟道区；
    第十七子有源部，连接于所述第九有源部的一侧，用于形成所述第九晶体管的第一端；
    第十八子有源部，连接于所述第九有源部的另一侧，用于形成所述第九晶体管的第二端；
    第十有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第十有源部用于形成所述第十晶体管的沟道区；
    第十九子有源部，连接于所述第十有源部的一侧，用于形成所述第十晶体管的第一端；
    第二十子有源部，连接于所述第十有源部的另一侧，用于形成所述第十晶体管的第二端；
    第十一有源部，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间，所述第十一有源部用于形成所述第十一晶体管的沟道区；
    第二十一子有源部，连接于所述第十一有源部的一侧，用于形成所述第十一晶体管的第一端；
    第二十二子有源部，连接于所述第十一有源部的另一侧，用于形成所述第十一晶体管的第二端；
    所述第二导电层还包括：
    第一高频信号线，在所述衬底基板的正投影沿行方向延伸且位于所述第一导电部在所述衬底基板的正投影远离所述第三导电部在所述衬底基板的正投影的一侧；
    第三电源线，在所述衬底基板的正投影沿行方向延伸且位于所述第一高频信号线在所述衬底基板的正投影和所述第一导电部在所述衬底基板的正投影之间，所述第三电源线用于提供所述第一子像素的第二电源端；
    第二电源线，在所述衬底基板的正投影沿行方向延伸且位于所述第三电源线在所述衬底基板的正投影和所述第一导电部在所述衬底基板的正投影之间，所述第二电源线用于提供所述第二子像素和所述第三子像素的第二电源端；
    初始信号线，在所述衬底基板的正投影沿行方向延伸且位于所述第一导电部在所述衬底基板的正投影和所述第三导电部在所述衬底基板的正投影之间；
    第二复位信号线，在所述衬底基板的正投影沿行方向延伸且位于所述初始信号线在所述衬底基板的正投影和所述第三导电块在所述衬底基板的正投影之间，所述第二复位信号线在所述衬底基板的正投影覆盖所述第八有源部在所述衬底基板的正投影，所述第二复位信号线的部分结构用于形成所述第八晶体管的栅极；
    第一电源线，在所述衬底基板的正投影沿行方向延伸且位于所述第一复位信号在所述衬底基板的正投影和所述第三导电块在所述衬底基板的正投影之间，且所述使能信号线的主体部在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影和所述第三导电块在所述衬底基板的正投影之间；
    第一导电块，在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影上，所述第一导电块用于形成所述第一电容的第二电极；
    第二导电块，在所述衬底基板的正投影位于所述第二导电部在所述衬底基板的正投影上，所述第二导电块用于形成所述第二电容的第二电极；
    第三导电块，包括依次连接的第一组成部、第二组成部和第三组成部，所述第一组成部在衬底基板的正投影位于所述第三导电部在衬底基板的正投影上，所述第一组成部用于形成所述存储电容的第二电极；所 述第三组成部在衬底基板的正投影覆盖所述第三有源部在衬底基板的正投影，所述第三组成部用于形成驱动晶体管的栅极；
    第四导电块，在所述衬底基板的正投影覆盖所述第九有源部在所述衬底基板的正投影，所述第四导电块的部分结构用于形成所述第九晶体管的栅极；
    第六导电块，包括第一子导电块和第二子导电块，所述第一子导电块在衬底基板的正投影沿列方向延伸，第二子导电块在衬底基板的正投影沿行方向延伸，所述第二子导电块在衬底基板的正投影覆盖所述第六有源部在衬底基板的正投影，所述第六导电块的部分结构用于形成所述第六晶体管的栅极；
    第九导电块，在衬底基板的正投影覆盖所述第十一有源部在衬底基板的正投影，所述第九导电块的部分结构用于形成所述第十一晶体管的栅极，所述第九导电块分别通过过孔连接所述第十一转接部和所述第十二转接部；
    第十导电块，通过过孔连接所述第十七子有源部；
    所述第三导电层还包括：
    第二高频信号线，在所述衬底基板的正投影沿列方向延伸，所述第二高频信号线通过过孔连接所述第一高频信号线；
    数据信号线，在所述衬底基板的正投影沿列方向延伸，所述数据信号线通过过孔连接所述第七子有源部、所述第十五子有源部和所述第十九子有源部；
    第一转接部，分别通过过孔连接所述第一子有源部和所述第三导电块；
    第二转接部，分别通过过孔连接第二子有源部和所述初始信号线；
    第七转接部，分别通过过孔连接所述第一导电块、所述第十六子有源部和所述第四导电块；
    第八转接部，分别通过过孔连接所述第十七子有源部和所述使能信号线；
    第九转接部，分别通过过孔连接位于第二导电层的第五导电块以及所述第十八子有源部和所述第二十二子有源部；
    第十转接部，分别通过过孔连接所述第五导电块和所述第六导电块；
    第十一转接部，分别通过过孔连接所述第二十子有源部和所述第九导电块；
    第十二转接部，分别通过过孔连接所述第九导电块和所述第二导电块；
    第十六转接部，分别通过过孔连接所述第二十一子有源部和位于第二导电层的第七导电块，所述第七导电块还通过过孔连接所述第二高频信号线；
    其中，所述第一复位信号线在所述衬底基板的正投影还覆盖所述第十有源部在所述衬底基板的正投影，所述第一复位信号线的部分结构用于形成所述第十晶体管的栅极。
  20. 根据权利要求19所述的显示面板，其中，
    所述有源层还包括：
    第十二有源部，用于形成所述第十二晶体管的沟道区，
    第二十三子有源部，连接于所述第十二有源部的一侧，所述第二十三子有源部用于形成所述第十二晶体管的第一端，所述第二十三子有源部通过过孔连接所述第六转接部；
    第二十四子有源部，连接于所述第十二有源部的另一侧，所述第二十四子有源部用于形成所述第十二晶体管的第二端；
    第十三有源部，用于形成所述第十三晶体管的沟道区；
    第二十五子有源部，连接于所述第十三有源部的一侧，用于形成所述第十三晶体管的第一端，所述第二十五子有源部通过过孔连接所述第六转接部；
    第二十六子有源部，连接于所述第十三有源部的另一侧，用于形成所述第十三晶体管的第二端；
    第十四有源部，用于形成所述第十四晶体管的沟道区；
    第二十七子有源部，连接于所述第十四有源部的一侧，用于形成所述第十四晶体管的第一端，所述第二十七子有源部通过过孔连接所述第六转接部；
    第二十八子有源部，连接于所述第十四有源部的另一端，用于形成 所述第十四晶体管的第二端；
    所述第二导电层还包括：
    第十二导电块，在所述衬底基板的正投影覆盖所述第十二有源部在所述衬底基板的正投影，所述第十二导电块用于形成所述第十二晶体管的栅极；
    第十三导电块，在所述衬底基板的正投影覆盖所述第十三有源部在所述衬底基板的正投影，所述第十三导电块用于形成所述第十三晶体管的栅极；
    第十四导电块，在所述衬底基板的正投影覆盖所述第十四有源部在所述衬底基板的正投影，所述第十四导电块用于形成所述第十四晶体管的栅极；
    所述第三导电层还包括：
    第十三转接部，通过过孔连接所述第二十四子有源部；
    第十四转接部，通过过孔连接所述第二十六子有源部；
    第十五转接部，通过过孔连接所述第二十八子有源部；
    所述显示面板还包括：
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括：
    第二十导电块，用于形成所述第一子像素的第一电极，所述第二十导电块通过过孔连接所述第十三转接部；
    第二十一导电块，用于形成所述第二子像素的第一电极，所述第二十一导电块通过过孔连接所述第十四转接部；
    第二十二导电块，用于形成所述第三子像素的第一电极，所述第二十二导电块通过过孔连接所述第十五转接部。
  21. 一种显示装置，其中，包括权利要求1-20任一项所述的显示面板。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111474758A (zh) * 2020-05-13 2020-07-31 上海天马微电子有限公司 一种显示面板及显示装置
WO2021017840A1 (zh) * 2019-07-31 2021-02-04 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板和显示面板
CN112825233A (zh) * 2019-11-21 2021-05-21 北京小米移动软件有限公司 显示面板和电子设备
CN114284303A (zh) * 2021-12-29 2022-04-05 长沙惠科光电有限公司 显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021017840A1 (zh) * 2019-07-31 2021-02-04 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板和显示面板
CN112825233A (zh) * 2019-11-21 2021-05-21 北京小米移动软件有限公司 显示面板和电子设备
CN111474758A (zh) * 2020-05-13 2020-07-31 上海天马微电子有限公司 一种显示面板及显示装置
CN114284303A (zh) * 2021-12-29 2022-04-05 长沙惠科光电有限公司 显示面板

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