WO2024088027A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

Info

Publication number
WO2024088027A1
WO2024088027A1 PCT/CN2023/123236 CN2023123236W WO2024088027A1 WO 2024088027 A1 WO2024088027 A1 WO 2024088027A1 CN 2023123236 W CN2023123236 W CN 2023123236W WO 2024088027 A1 WO2024088027 A1 WO 2024088027A1
Authority
WO
WIPO (PCT)
Prior art keywords
selection signal
signal line
sub
electrically connected
signals
Prior art date
Application number
PCT/CN2023/123236
Other languages
English (en)
French (fr)
Inventor
周宏军
周桢力
嵇凤丽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024088027A1 publication Critical patent/WO2024088027A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and specifically to a display substrate and a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, comprising: a plurality of sub-pixels arranged in an array, a multiplexing circuit, a plurality of data signal lines, a plurality of selection signal lines and a plurality of data transmission lines, the plurality of sub-pixels comprising: a plurality of color sub-pixels, the data signal lines being electrically connected to the plurality of sub-pixels;
  • the multiplexing circuit comprises: a plurality of multiplexing transistors, the multiplexing transistors being electrically connected to the data transmission line, the selection signal line and the data signal line respectively, the multiplexing transistors being configured to transmit the signal of the data transmission line to the data signal line under the control of the selection signal line;
  • the plurality of selection signal lines are divided into a plurality of selection signal groups, at least one selection signal group includes: a plurality of selection signal lines, different selection signal groups include different selection signal lines, and the selection signal groups are electrically connected to the sub-pixels through the multiplexing transistors and the data signal lines;
  • the sub-pixels electrically connected to the same selection signal group have the same color, the sub-pixels electrically connected to different selection signal groups have different colors, and the effective time periods of any two selection signal groups among the multiple selection signal groups do not overlap, wherein the effective time period of the selection signal group refers to the time period between the earliest start time when the signal in the selection signal line of the selection signal group is a valid level signal and the latest end time when the signal is a valid level signal.
  • the sub-pixel includes: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, the first color, the second color, and the third color are different colors, and are respectively one of red, blue, and green;
  • the i-th data signal line is electrically connected to the i-th column of sub-pixels, the 3 ⁇ i-2-th column of sub-pixels are first color sub-pixels, the 3 ⁇ i-1-th column of sub-pixels are second color sub-pixels, and the 3 ⁇ i-th column of sub-pixels are third color sub-pixels, wherein 1 ⁇ i ⁇ N/3, ⁇ is a multiplication operation, / is a quotient operation, N is the number of data signal lines, and N is a positive integer greater than or equal to 6.
  • the plurality of selection signal groups include: a first selection signal group, a second selection signal group, and a third selection signal group;
  • the sub-pixels electrically connected to the first selection signal group are first color sub-pixels
  • the sub-pixels electrically connected to the second selection signal group are second color sub-pixels
  • the sub-pixels electrically connected to the third selection signal group are third color sub-pixels.
  • an effective period of a selection signal group electrically connected to a blue sub-pixel is earlier than an effective period of a selection signal group electrically connected to a red sub-pixel and a green sub-pixel.
  • the multiplexing circuit includes: N/M multiplexing sub-circuits;
  • the number of the multiplexing transistors is N, and the N multiplexing transistors are all N-type transistors or all P-type transistors;
  • the jth multiplexing sub-circuit includes: the M ⁇ (j-1)+1th multiplexing transistor to the M ⁇ jth multiplexing transistor.
  • a plurality of scan signal lines further comprising: a plurality of scan signal lines, the plurality of scan signal lines being electrically connected to the plurality of sub-pixels;
  • the content displayed by the display substrate includes multiple display frames.
  • the end time of the signals in the multiple selection signal lines being valid level signals at the latest is earlier than the start time of the signals of the scanning signal lines electrically connected to the k-th row of sub-pixels being valid level signals.
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals when all rows in the same display frame are displayed is the same;
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals when different rows are displayed is different, and the occurrence time of the signal of the same selection signal line being a valid level signal is in different positions when different rows are displayed;
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals when all rows in the same display frame are displayed is the same;
  • the occurrence time sequence of the signals of multiple selection signal lines being valid level signals is different when different display frames are displayed, and the occurrence time of the signal of the same selection signal line being a valid level signal is in different positions when different display frames are displayed.
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals when different rows are displayed is different, and the occurrence time of the signal of the same selection signal line being a valid level signal is in different positions when different rows are displayed;
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is the same;
  • the method comprises: a first signal line, the first signal line at least comprising: a scanning signal line, the first signal line and the data signal line are arranged in different layers, and the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate, and the capacitance between the overlapping area of the data signal line and the first signal line is the data parasitic capacitance of the data signal line;
  • data parasitic capacitances of a plurality of data signal lines electrically connected to sub-pixels of the same color are different.
  • a signal of a selection signal line electrically connected to a multiplexing transistor connected to an a-th data signal line among a plurality of data signal lines electrically connected to sub-pixels of the same color is a valid level signal earlier than a signal of a selection signal line connected to a multiplexing transistor connected to a b-th data signal line is a valid level signal
  • a data parasitic capacitance of the a-th data signal line is greater than a data parasitic capacitance of the b-th data signal line.
  • data parasitic capacitances of at least two data signal lines electrically connected to sub-pixels of different colors are equal.
  • data parasitic capacitances of the 3i-2 th to 3i th data signal lines are equal.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate.
  • the present disclosure further provides a method for driving a display substrate, for driving the above-mentioned display substrate, the method comprising:
  • Signals are supplied to the plurality of selection signal lines so that effective time periods of any two selection signal groups among the plurality of selection signal groups do not overlap.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a display substrate
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate
  • FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG5 is a working timing diagram of a pixel driving circuit
  • FIG6 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure.
  • FIG7 is a circuit structure diagram of a multiplexing circuit
  • FIG8 is an equivalent circuit diagram of a multiplexing circuit
  • FIG9 is an equivalent circuit diagram of another multiplexing circuit
  • FIG10 is an equivalent circuit diagram of another multiplexing circuit
  • FIG11 is a working timing diagram of the display substrate
  • FIG12 is a second working timing diagram of the display substrate
  • FIG13 is a third working timing diagram of the display substrate
  • FIG14 is a fourth working timing diagram of the display substrate
  • FIG15 is a fifth working timing diagram of the display substrate
  • FIG16 is a sixth working timing diagram of the display substrate
  • FIG. 17 is a seventh working timing diagram of the display substrate.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • the data driver chip in the display device provides data signals to the sub-pixels in the display through the data signal lines. Since the number of data signal lines in the display device is large, the data driver chip requires more pins, so the data transmission lines for transmitting data signals to the data signal lines are also correspondingly large, which is not conducive to achieving a narrow frame of the display.
  • the display substrate sets a multiplexing circuit MUX between the data transmission line and the data signal line, and the multiplexing circuit MUX is electrically connected to multiple selection signal lines and data transmission lines.
  • the commonly used scheme is that the data driver chip sets a multiplexing circuit MUX so that one data transmission line can connect multiple columns of sub-pixels, which can greatly reduce the number of data transmission lines, reduce the size of the data driver chip, and reduce the size of the display frame.
  • the multiplexing circuit MUX and the multiple selection signal line circuits are connected.
  • the connection is made by providing the data transmission line signal to the data signal line under the control of the selection signal line.
  • the multiple selection signals of the multiple selection signal lines must be turned on in sequence. Therefore, when each row of sub-pixels is displayed, the data voltages of the multiple data signal lines are not kept in the parasitic capacitors on the data signal lines for the same time. In this process, leakage is inevitable.
  • the voltage of the data written first decays the most seriously, while the voltage of the data written last decays relatively slowly. This results in a brightness difference caused by the data voltage difference, which may form vertical light and dark stripes, reducing the display effect of the display substrate.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, wherein the timing controller is respectively connected to the data driver, the scan driver, and the light emitting driver, wherein the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • D1 to Dn data signal lines
  • S1 to Sm scan signal lines
  • E1 to Eo light emitting signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal line, the light emitting signal line, and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc.
  • the data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values and control signals received from the timing controller. For example, the data driver can sample grayscale values using a clock signal, and apply data voltages corresponding to grayscale values to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number.
  • the light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller.
  • the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.
  • FIG2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal, or hexagonal.
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and FIG3 only takes one transistor 101 and one storage capacitor 101A as an example.
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the driving transistor 210 through a via
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer 303.
  • the organic light-emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304.
  • the encapsulation structure layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 stacked together.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light emitting layer 303 may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7), 1 storage capacitor C, and the pixel driving circuit may be connected to 7 signal lines (a data signal line D, a scanning signal line Gate, a reset signal line Reset, a light emitting signal line EM, an initial signal line INIT, a first power line VDD, and a second power line VSS).
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.
  • a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .
  • the control electrode of the first transistor T1 is connected to the reset signal line Reset, the first electrode of the first transistor T1 is connected to the initialization signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the scanning signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the scanning signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 can be called a switching transistor, a scanning transistor, etc. When the on-level scanning signal is applied to the scanning signal line Gate, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line EM, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.
  • the control electrode of the seventh transistor T7 is connected to the scanning signal line Gate, the first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.
  • the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal.
  • the scanning signal line Gate is the scanning signal line in the pixel driving circuit of the current display row
  • the reset signal line Reset is the scanning signal line Gate in the pixel driving circuit of the previous display row
  • the reset signal line Reset of the current display row is the same as the scanning signal line Gate in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, realize low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.
  • OLED organic light emitting diode
  • FIG5 is a working timing diagram of a pixel driving circuit. The following is an explanation of an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit shown in FIG4.
  • the pixel driving circuit in FIG4 includes 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and all 7 transistors are P-type transistors.
  • the operation process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signal of the reset signal line Reset is a low-level signal, and the signals of the scanning signal line Gate and the light-emitting signal line EM are high-level signals.
  • the signal of the reset signal line Reset is a low-level signal, which turns on the first transistor T1.
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize (reset) the storage capacitor C and clear the original charge in the storage capacitor.
  • the signals of the scanning signal line Gate and the light-emitting signal line EM are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the scanning signal line Gate is a low level signal
  • the signals of the reset signal line Reset and the luminous signal line EM are high level signals
  • the data signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the scanning signal line Gate is a low level signal to turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage of the second end (the second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light.
  • the signal of the reset signal line Reset is a high-level signal, which turns off the first transistor T1.
  • the signal of the luminous signal line EM is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, and the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals.
  • the signal of the light-emitting signal line EM is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • )-Vth] 2 K*[(Vdd-Vd] 2
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, which can ensure the uniform display brightness of the display product and improve the display effect of the entire display product.
  • FIG6 is a schematic diagram of the structure of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate provided by an embodiment of the present disclosure may include: a plurality of sub-pixels P arranged in an array, a multiplexing circuit MUX, a plurality of data signal lines D, a plurality of selection signal lines MUX, and a plurality of data transmission lines S.
  • the plurality of sub-pixels include: a plurality of color sub-pixels, and the data signal lines are electrically connected to the plurality of sub-pixels. Di in FIG6 represents the i-th data signal line, MUX i represents the i-th selection signal line, and Si represents the i-th data transmission line.
  • the multiplexing circuit may include: a plurality of multiplexing transistors electrically connected to the data transmission line, the selection signal line and the data signal line, respectively.
  • the multiplexing transistors are configured to transfer the signal of the data transmission line to the data signal line under the control of the selection signal line.
  • a plurality of selection signal lines may be divided into a plurality of selection signal groups, at least one selection signal group includes: a plurality of selection signal lines, different selection signal groups include different selection signal lines, the selection signal groups are electrically connected to the sub-pixels through multiplexing transistors and data signal lines.
  • the sub-pixels electrically connected to the same selection signal group have the same color, and the sub-pixels electrically connected to different selection signal groups have different colors, and the effective time periods of any two selection signal groups in the plurality of selection signal groups do not overlap, wherein the effective time period of the selection signal group refers to the time period between the earliest start time when the signal in the selection signal line of the selection signal group is a valid level signal and the latest end time when the signal is a valid level signal.
  • the display substrate provided by the embodiment of the present disclosure may further include: a scanning signal line Gate, wherein the plurality of sub-pixels are electrically connected to the scanning signal line.
  • the display substrate includes: a display area and a non-display area, wherein the scan signal lines, the data signal lines and the sub-pixels are located in the display area, and the multiplexing circuit is located in the non-display area.
  • the display substrate further includes: a source driver chip located in the non-display area, and the source driver chip is electrically connected to the plurality of data transmission lines.
  • the display substrate provided in the embodiments of the present disclosure may adopt a low temperature polysilicon technology (Low Temperature Poly-silicon, abbreviated as LTPS) process or an oxide process, and the present disclosure does not make any limitation to this.
  • LTPS Low Temperature Poly-silicon
  • the present disclosure sets the sub-pixels electrically connected to the same selection signal group to have the same color, and the sub-pixels electrically connected to different selection signal groups to have different colors, and the effective time periods of any two selection signal groups in the multiple selection signal groups do not overlap, so as to ensure that the occurrence times of the signals of the multiple selection signal lines in the selection signal group controlling the sub-pixels of the same color are adjacent to each other, so that the time difference of the stored data voltages on the multiple data signal lines electrically connected to the same selection signal group is minimized, which can reduce or avoid the problem of pixel brightness difference caused by the successive opening of the multiple selection signal lines, eliminate the poor light and dark vertical stripes in the macroscopic visual sense, and improve the display effect of the display substrate.
  • the sub-pixel may include: a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, and the first color, the second color, and the third color are different colors and are respectively one of red, blue, and green.
  • the first color may be red, the second color may be green, and the third color may be blue, or the first color may be red, the second color may be blue, and the third color may be green, or the first color may be blue, the second color may be red, and the third color may be green, or the first color may be blue, the second color may be green, and the third color may be red, or the first color may be green, the second color may be blue, and the third color may be red, or the first color may be green, the second color may be blue, and the third color may be red, or the first color may be green, the second color may be blue, and the third color may be red, or the first color may be green, the second color may be blue, and the third color may be red, or the first color may be green, the second color may be red, and the third color may be blue.
  • the i-th data signal line is electrically connected to the i-th column sub-pixel
  • the 3i-2-th column sub-pixel is a first color sub-pixel
  • the 3i-1-th column sub-pixel is a second color sub-pixel
  • the 3i-th column sub-pixel is a third color sub-pixel, wherein 1 ⁇ i ⁇ N/3, / is a quotient operation
  • N is the number of data signal lines, and N can be a positive integer greater than or equal to 6.
  • FIG6 is illustrated by taking the first color as red, the second color as green, and the third color as blue as an example, and the present disclosure does not make any limitation to this.
  • the plurality of selection signal groups may include: a first selection signal group, a second selection signal group, and a third selection signal group.
  • the sub-pixels electrically connected to the first selection signal group are first color sub-pixels
  • the second selection signal group The sub-pixels electrically connected are second color sub-pixels
  • the sub-pixels electrically connected to the third selection signal group are third color sub-pixels.
  • the effective period of the selection signal group electrically connected to the blue sub-pixel can be earlier than the effective period of the selection signal group electrically connected to the red sub-pixel and the green sub-pixel.
  • the effective time period of the selection signal group electrically connected to the red sub-pixel is earlier than the effective time period of the selection signal group electrically connected to the blue sub-pixel and the green sub-pixel, or the effective time period of the selection signal group electrically connected to the green sub-pixel can be earlier than the effective time period of the selection signal group electrically connected to the blue sub-pixel and the red sub-pixel.
  • the order in which the effective time periods of the selection signals occur can be determined based on the characteristics of the light-emitting device, and the present disclosure does not impose any limitation on this.
  • Fig. 7 is a circuit structure diagram of a multiplexing circuit
  • Fig. 8 is an equivalent circuit diagram of a multiplexing circuit
  • Fig. 9 is an equivalent circuit diagram of another multiplexing circuit
  • Fig. 10 is an equivalent circuit diagram of yet another multiplexing circuit.
  • the jth multiplexing subcircuit may be electrically connected to the M ⁇ (j-1)+1th data signal line to the M ⁇ jth data signal line.
  • the first multiplexing subcircuit is electrically connected to the first data signal line to the Mth data signal line, the first data transmission line, and the first selection signal line to the Mth selection signal line, respectively;
  • the second multiplexing subcircuit is electrically connected to the M+1th data signal line to the 2Mth data signal line, the second data transmission line, and the first selection signal line to the Mth selection signal line, respectively;
  • the N/Mth multiplexing subcircuit is electrically connected to the N-M+1th data signal line to the Nth data signal line, the N/Mth data transmission line, and the first selection signal line to the Mth selection signal line, respectively.
  • M 3 ⁇ S
  • S is a positive integer greater than or equal to 2
  • M is a positive integer greater than or equal to 6, and is an integer multiple of 3.
  • M can be 6, 9, or 12, and the present disclosure does not impose any limitation on this.
  • the N/6th multiplexing sub-circuit is electrically connected to the N-5th data signal line to the Nth data signal line, the N/6th data transmission line and the first selection signal line to the sixth selection signal line, respectively.
  • the N/9th multiplexing sub-circuit is electrically connected to the N-8th data signal line to the Nth data signal line, the N/9th data transmission line and the first selection signal line to the ninth selection signal line, respectively.
  • the first selection signal line is electrically connected to the twelfth selection signal line.
  • the number of reset transistors may be the same as the number of data signal lines, that is, the number of multiplexing transistors may be N.
  • the control electrode of the nth multiplexing transistor Fn is electrically connected to the lth selection signal line MUX l
  • the first electrode of the nth multiplexing transistor Fn is electrically connected to the nth data signal line Dn
  • l may satisfy the following formula:
  • n is a multiple of 6, such as 6, 12, 18, etc.
  • l 6, that is, the control electrodes of the sixth multiplexing transistor, the twelfth multiplexing transistor, the eighteenth multiplexing transistor, etc.
  • the present disclosure does not make any limitation on this.
  • w satisfies the following formula:
  • the second electrode of the sixth multiplexed transistor is electrically connected to the 6th/6th data transmission line, that is, the first data transmission line
  • the second electrode of the twelfth multiplexed transistor is electrically connected to the 12th/6th data transmission line, that is, the second data transmission line
  • the second electrode of the eighteenth multiplexed transistor is electrically connected to the 18th/6th data transmission line, that is, the third data transmission line, and so on.
  • the second electrodes of the first multiplexed transistor to the fifth multiplexed transistor are all electrically connected to the first data transmission line
  • the second electrodes of the seventh multiplexed transistor to the eleventh multiplexed transistor are all electrically connected to the second data transmission line, and so on.
  • the jth multiplexing subcircuit may include: the M ⁇ (j-1)+1th multiplexing transistor to the M ⁇ jth multiplexing transistor.
  • the first multiplexing subcircuit includes: the first multiplexing transistor to the sixth multiplexing transistor
  • the second multiplexing subcircuit includes: the seventh multiplexing transistor to the twelfth multiplexing transistor, and so on.
  • the second multiplexing subcircuit includes: the tenth multiplexing transistor to the eighteenth multiplexing transistor, and so on.
  • the first multiplexing sub-circuit includes: the first multiplexing transistor to the twelfth multiplexing transistor
  • the second multiplexing sub-circuit includes: the thirteenth multiplexing transistor to the twenty-fourth multiplexing transistor, and so on.
  • the N multiplexing transistors may all be N-type transistors or all be P-type transistors, which is not limited in the present disclosure.
  • the first selection signal group electrically connected to the first color sub-pixel may include: a first selection signal line MUX 1 and a fourth selection signal line MUX 4
  • the second selection signal group electrically connected to the second color sub-pixel may include: a second selection signal line MUX 2 and a fifth selection signal line MUX 5
  • the third selection signal group electrically connected to the third color sub-pixel may include: a third selection signal line MUX 3 and a sixth selection signal line MUX 6 .
  • a control electrode of a first multiplexing transistor F1 is electrically connected to a first selection signal line MUX 1
  • a first electrode of the first multiplexing transistor F1 is electrically connected to a first data signal line D 1
  • a second electrode of the first multiplexing transistor F1 is electrically connected to a first data transmission line S 1
  • a control electrode of a second multiplexing transistor F2 is electrically connected to a second selection signal line MUX 2
  • a first electrode of the second multiplexing transistor F2 is electrically connected to a second data signal line D 2
  • a second electrode of the second multiplexing transistor F2 is electrically connected to the first data transmission line S 1
  • a control electrode of a third multiplexing transistor F3 is electrically connected to a third selection signal line MUX 3
  • a first electrode of the third multiplexing transistor F3 is electrically connected to a third data signal line D 3
  • a first electrode of the twelfth multiplexing transistor F12 is electrically connected to the twelfth data signal line D12
  • a second electrode of the twelfth multiplexing transistor F12 is electrically connected to the second data transmission line S2 , and so on.
  • a first selection signal group electrically connected to the first color sub-pixel may include: a first selection signal line MUX 1 , a fourth selection signal line MUX 4 and a seventh selection signal line MUX 7
  • a second selection signal group electrically connected to the second color sub-pixel may include: a second selection signal line MUX 2 , a fifth selection signal line MUX 5 and an eighth selection signal line MUX 8
  • a third selection signal group electrically connected to the third color sub-pixel may include: a third selection signal line MUX 3 , a sixth selection signal line MUX 6 and a ninth selection signal line MUX 9 .
  • a control electrode of a first multiplexing transistor F1 is electrically connected to a first selection signal line MUX 1
  • a first electrode of the first multiplexing transistor F1 is electrically connected to a first data signal line D 1
  • a second electrode of the first multiplexing transistor F1 is electrically connected to a first data transmission line S 1
  • a control electrode of a second multiplexing transistor F2 is electrically connected to a second selection signal line MUX 2
  • a first electrode of the second multiplexing transistor F2 is electrically connected to a second data signal line D 2
  • a second electrode of the second multiplexing transistor F2 is electrically connected to the first data transmission line S 1
  • a control electrode of a third multiplexing transistor F3 is electrically connected to a third selection signal line MUX 3
  • a first electrode of the third multiplexing transistor F3 is electrically connected to a third data signal line D 3
  • the first selection signal group may include: a first selection signal line MUX 1 , a fourth selection signal line MUX 4 , a seventh selection signal line MUX 7 and a tenth selection signal line MUX 10
  • the second selection signal group may include: a second selection signal line MUX 2 , a fifth selection signal line MUX 5 , an eighth selection signal line MUX 8 and an eleventh selection signal line MUX 11
  • the third selection signal group may include: a third selection signal line MUX 3 , a sixth selection signal line MUX 6 , a ninth selection signal line MUX 9 and a twelfth selection signal line MUX 12 .
  • a control electrode of a first multiplexing transistor F1 is electrically connected to a first selection signal line MUX 1
  • a first electrode of the first multiplexing transistor F1 is electrically connected to a first data signal line D 1
  • a second electrode of the first multiplexing transistor F1 is electrically connected to a first data transmission line S 1
  • a control electrode of a second multiplexing transistor F2 is electrically connected to a second selection signal line MUX 2
  • a first electrode of the second multiplexing transistor F2 is electrically connected to a second data signal line D 2
  • a second electrode of the second multiplexing transistor F2 is electrically connected to the first data transmission line S 1
  • a control electrode of a third multiplexing transistor F3 is electrically connected to a third selection signal line MUX 3
  • a first electrode of the third multiplexing transistor F3 is electrically connected to a third data signal line D 3
  • FIG11 is a working timing diagram of the display substrate 1
  • FIG12 is a working timing diagram of the display substrate 2
  • FIG13 is a working timing diagram of the display substrate 3
  • FIG14 is a working timing diagram of the display substrate 4
  • FIG15 is a working timing diagram of the display substrate 5
  • FIG16 is a working timing diagram of the display substrate 6
  • FIG17 is a working timing diagram of the display substrate 7.
  • Gate 1 is a signal of a scanning signal line electrically connected to the first row of sub-pixels
  • EM 1 is a signal of a light emitting signal line electrically connected to the first row of sub-pixels
  • Reset 1 is a signal of a reset signal line electrically connected to the first row of sub-pixels
  • the i-th row indicates that the i-th row of sub-pixels is displayed
  • the signals of all the remaining selection signal lines are invalid level signals.
  • the content displayed by the display substrate includes a plurality of display frames, and when the k-th row of sub-pixels of at least one display frame is displayed, the latest end time of the signals in the plurality of selection signal lines being valid level signals is earlier than the start time of the signals of the scanning signal lines electrically connected to the k-th row of sub-pixels being valid level signals.
  • the latest end time of the signals in the plurality of selection signal lines being valid level signals refers to the end time of the signals of the fifth selection signal line being valid level signals, taking FIG.
  • the latest end time of the signals in the plurality of selection signal lines being valid level signals refers to the end time of the signals of the eighth selection signal line MUX 8 being valid level signals
  • the latest end time of the signals in the plurality of selection signal lines being valid level signals refers to the end time of the signals of the eleventh selection signal line MUX 11 being valid level signals.
  • FIG. 11 is explained by taking the first selection signal line MUX 1 as the first signal line whose signal in the first selection signal group is the valid level signal at the earliest, and the fourth selection signal line MUX 4 as the signal line whose signal is the valid level signal at the latest, as an example, and the valid time period t1 of the first selection signal group refers to the time period between the start time when the signal of the first selection signal line MUX 1 is the valid level signal and the end time when the signal of the fourth selection signal line MUX 4 is the valid level signal.
  • the signal line whose signal in the second selection signal group is the valid level signal at the earliest is the second selection signal line MUX 2
  • the signal line whose signal is the valid level signal at the latest is the fifth selection signal line MUX 5
  • the effective time period t2 of the second selection signal group refers to the time period between the start time when the signal of the second selection signal line MUX 2 is an effective level signal and the end time when the signal of the fifth selection signal line MUX 5 is an effective level signal.
  • the signal line whose signal in the third selection signal group is the earliest effective level signal is the third selection signal line MUX 3
  • the signal line whose signal is the latest effective level signal is the sixth selection signal line MUX 6.
  • the effective time period t3 of the third selection signal group refers to the time period between the start time when the signal of the third selection signal line MUX 3 is an effective level signal and the end time when the signal of the sixth selection signal line MUX 6 is an effective level signal.
  • the light emission order of the sub-pixels electrically connected thereto is the sub-pixel in the third column of the first row, the sub-pixel in the sixth column of the first row, the sub-pixel in the first column of the first row, the sub-pixel in the fourth column of the first row, the sub-pixel in the second column of the first row, and the sub-pixel in the fifth column of the first row, and the present disclosure does not make any limitation on this.
  • FIG. 12 is explained by taking the first selection signal line MUX 1 as the earliest signal line whose signal in the first selection signal group is a valid level signal, and the seventh selection signal line MUX 7 as the latest signal line whose signal is a valid level signal, as an example, and the valid time period t1 of the first selection signal group refers to the time period between the start time when the signal of the first selection signal line MUX 1 is a valid level signal and the end time when the signal of the seventh selection signal line MUX 7 is a valid level signal.
  • the second selection signal line MUX 2 is explained by taking the second selection signal line MUX 8 as the earliest signal line whose signal in the second selection signal group is a valid level signal, and the eighth selection signal line MUX 8 as the latest signal line whose signal is a valid level signal, as an example, and the valid time period t2 of the second selection signal group refers to the time period between the start time when the signal of the second selection signal line MUX 2 is a valid level signal and the end time when the signal of the eighth selection signal line MUX 8 is a valid level signal.
  • the signal line whose earliest signal in the third selection signal group is a valid level signal is the third selection signal line MUX 3
  • the signal line whose latest signal is a valid level signal is the ninth selection signal line MUX 9.
  • the valid time period t3 of the third selection signal group refers to the time period between the start time when the signal of the third selection signal line MUX 3 is a valid level signal and the end time when the signal of the ninth selection signal line MUX 9 is a valid level signal.
  • the light emission order of the electrically connected sub-pixels is the third column sub-pixel in the first row, the sixth column sub-pixel in the first row, the ninth column sub-pixel in the first row, the first column sub-pixel in the first row, the fourth column sub-pixel in the first row, the seventh column sub-pixel in the first row, the second column sub-pixel in the first row, the fifth column sub-pixel in the first row, the eighth column sub-pixel in the first row, and the present disclosure does not make any limitation on this.
  • FIG. 13 is explained by taking the first selection signal line MUX 1 as the earliest signal line that is a valid level signal, and the tenth selection signal line MUX 10 as the latest signal line that is a valid level signal in the first selection signal group as an example, and the valid time period t1 of the first selection signal group refers to the time period between the start time when the signal of the first selection signal line MUX 1 is a valid level signal and the end time when the signal of the tenth selection signal line MUX 10 is a valid level signal.
  • the second selection signal line MUX 2 is explained by taking the second selection signal line MUX 2 as the earliest signal line that is a valid level signal, and the eleventh selection signal line MUX 11 as the latest signal line that is a valid level signal, and the valid time period t2 of the second selection signal group refers to the time period between the start time when the signal of the second selection signal line MUX 2 is a valid level signal and the end time when the signal of the eleventh selection signal line MUX 11 is a valid level signal.
  • the signal line whose earliest signal in the third selection signal group is a valid level signal is the third selection signal line MUX 3
  • the signal line whose latest signal is a valid level signal is the twelfth selection signal line MUX 12.
  • the effective time period t3 of the third selection signal group refers to the time period between the start time when the signal of the third selection signal line MUX 3 is a valid level signal and the end time when the signal of the twelfth selection signal line MUX 12 is a valid level signal.
  • the light emission order of the electrically connected sub-pixels is, in sequence, the sub-pixels in the third column of the first row, the sub-pixels in the sixth column of the first row, the sub-pixels in the ninth column of the first row, the sub-pixels in the twelfth column of the first row, the sub-pixels in the first column of the first row, the sub-pixels in the fourth column of the first row, the sub-pixels in the seventh column of the first row, the sub-pixels in the tenth column of the first row, the sub-pixels in the second column of the first row, the sub-pixels in the fifth column of the first row, the sub-pixels in the eighth column of the first row, the sub-pixels in the eleventh column of the first row, and the present disclosure is in this regard. No restrictions.
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals is the same, and in different display frames, when the same row is displayed, when the signals of the plurality of selection signal lines being valid level signals is the same.
  • the occurrence time sequence of the plurality of selection signal lines may be the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the second selection signal line MUX 2 , and the fifth selection signal line MUX 5.
  • the occurrence time sequence of the plurality of selection signal lines may be the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the ninth selection signal line MUX 9 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the seventh selection signal line MUX 7 , the second selection signal line MUX 2 , the fifth selection signal line MUX 5 , and the eighth selection signal line MUX 8 .
  • the occurrence time sequence of the multiple selection signal lines is the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the ninth selection signal line MUX 9 , the twelfth selection signal line MUX 12 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the seventh selection signal line MUX 7 , the tenth selection signal line MUX 10 , the second selection signal line MUX 2 , the fifth selection signal line MUX 5 , the eighth selection signal line MUX 8 , and the eleventh selection signal line MUX 11 .
  • the same occurrence time sequence of the signals of multiple selection signal lines being valid level signals when the same row is displayed means that when the i-th row in any two display frames is displayed, the same occurrence time sequence of the signals of multiple selection signal lines being valid level signals is displayed.
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is the same.
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is different, and the occurrence time of the signal of the same selection signal line being a valid level signal is in different positions when displayed in different display frames.
  • the occurrence order of the signals of the multiple selection signal lines being valid level signals when different display frames are displayed is different, and the occurrence order of the signal of the same selection signal line being a valid level signal when different display frames are displayed is different.
  • the occurrence order of the signals of the multiple selection signal lines being valid level signals may be the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the second selection signal line MUX 2 , and the fifth selection signal line MUX 5
  • the occurrence order of the signals of the multiple selection signal lines being valid level signals may be the sixth selection signal line MUX 6 , the third selection signal line MUX 3 , the fourth selection signal line MUX 4 , the first selection signal line MUX 1 , the fifth selection signal line MUX 5 , and the second selection signal line MUX 2 .
  • the time when the signal of the first selection signal line MUX 1 is a valid level signal is the third in the odd display frame, and is the fourth in the even display frame, that is, the positions in the odd display frame and the even display frame are different.
  • the time when the signals of the remaining selection signal lines are valid level signals are different in the odd display frame and the even display frame.
  • the order in which the signals of the plurality of selection signal lines are valid level signals is the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the ninth selection signal line MUX 9 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the seventh selection signal line MUX 7 , the second selection signal line MUX 2 , the fifth selection signal line MUX 5 , and the eighth selection signal line MUX 8.
  • the signals of the plurality of selection signal lines are valid level signals.
  • the occurrence order of the level signals may be the sixth selection signal line MUX 6 , the ninth selection signal line MUX 9 , the third selection signal line MUX 3 , the fourth selection signal line MUX 4 , the seventh selection signal line MUX 7 , the first selection signal line MUX 1 , the fifth selection signal line MUX 5 , the eighth selection signal line MUX 8 , and the second selection signal line MUX 2.
  • the occurrence order of the signals of the plurality of selection signal lines being valid level signals may be the ninth selection signal line MUX 9 , the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the seventh selection signal line MUX 7 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the eighth selection signal line MUX 8 , the second selection signal line MUX 2 , and the fifth selection signal line MUX 5 .
  • the occurrence time of the signal of the first selection signal line MUX 1 being a valid level signal is the fourth position when the first display frame is displayed, the sixth position when the second display frame is displayed, and the fifth position when the third display frame is displayed, that is, the positions are not the same from the first display frame to the third display frame, and similarly, the occurrence time of the signals of the remaining selection signal lines being valid level signals are all different in the positions of the three adjacent display frames.
  • the present invention can avoid the occurrence of light and dark stripes in odd and even columns by having the signals of multiple selection signal lines being valid level signals in different display frames in adjacent M/3 display frames, and the occurrence time of the signal of the same selection signal line being a valid level signal in different display frames.
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is different when different rows are displayed, and the occurrence time of the signal of the same selection signal line being a valid level signal is in different positions when different rows are displayed.
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals when the same row is displayed is the same.
  • the present invention can avoid the occurrence of light and dark stripes in odd and even columns by configuring, in the same display frame, for adjacent M/3 rows, that the occurrence time sequences of signals of multiple selection signal lines in the same selection signal group being valid level signals are different when different rows are displayed, and that the occurrence time of signals of the same selection signal line being valid level signals are different in positions when different rows are displayed.
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals when different rows are displayed is different, and the occurrence time of the signal of the same selection signal line being a valid level signal has different positions when different rows are displayed.
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals when all odd rows are displayed is the same, and the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals when all even rows are displayed is the same.
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is the same, when all rows satisfying the 3r-1 row (the second row, the fifth row, the eighth row, etc.) are displayed, the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is the same, and when all rows satisfying the 3r row (the third row, the sixth row, the ninth row, etc.) are displayed, the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is the same.
  • the occurrence time sequence of the signals of multiple selection signal lines being valid level signals when different rows are displayed is different, and the occurrence time of the signal of the same selection signal line being a valid level signal has different positions when different rows are displayed.
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals is the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the second selection signal line MUX 2 , and the fifth selection signal line MUX 5 .
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals is the sixth selection signal line MUX 6 , the third selection signal line MUX 3 , the fourth selection signal line MUX 4 , the first selection signal line MUX 1 , the fifth selection signal line MUX 5 , and the second selection signal line MUX 2 .
  • the occurrence time sequence of the signals of the selection signal lines being valid level signals is different.
  • the time when the signal of the first selection signal line MUX 1 is a valid level signal is the third when displayed in odd rows, and is the fourth when displayed in even rows, that is, the positions in odd rows and even rows are different.
  • the time when the signals of the remaining selection signal lines are valid level signals are different in odd rows and even rows.
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals is the sixth selection signal line MUX 6 , the third selection signal line MUX 3 , the fourth selection signal line MUX 4 , the first selection signal line MUX 1 , the fifth selection signal line MUX 5 , and the second selection signal line MUX 2 .
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals is the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the second selection signal line MUX 2 , and the fifth selection signal line MUX 5 , and the occurrence time sequence of the signals of the plurality of selection signal lines in the third selection signal group being valid level signals is.
  • the occurrence time sequence of the signals of the selection signal lines being valid level signals is For example, the occurrence time when the signal of the first selection signal line MUX 1 is a valid level signal is the fourth when displayed in odd rows, and the third when displayed in even rows, that is, the positions are different for odd rows and even rows, and similarly, the occurrence time when the signals of the remaining selection signal lines are valid level signals is different for odd rows and even rows.
  • the occurrence time sequence of the signals of the plurality of selection signal lines being valid level signals is the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the ninth selection signal line MUX 9 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the seventh selection signal line MUX 7 , the second selection signal line MUX 2 , the fifth selection signal line MUX 5 , and the eighth selection signal line MUX 8 .
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is the sixth selection signal line MUX 6 , the ninth selection signal line MUX 9 , the third selection signal line MUX 3 , the fourth selection signal line MUX 4 , the seventh selection signal line MUX 7 , the first selection signal line MUX 1 , the fifth selection signal line MUX 5 , the eighth selection signal line MUX 8 , and the second selection signal line MUX 2 .
  • the occurrence time order of the signals of the multiple selection signal lines being valid level signals is the ninth selection signal line MUX 9 , the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the seventh selection signal line MUX 7 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the eighth selection signal line MUX 8 , the second selection signal line MUX 2 , and the fifth selection signal line MUX 5 , and the occurrence time order of the signals of the multiple selection signal lines in the third selection signal group being valid level signals is.
  • the time when the signal of the selection signal line is a valid level signal is ranked different.
  • the time when the signal of the first selection signal line MUX 1 is a valid level signal is ranked fourth when displayed in the first row, ranked sixth when displayed in the second row, and ranked fifth when displayed in the third row, namely, the positions in the first to third rows are not the same.
  • the time when the signals of the remaining selection signal lines are valid level signals are all different in the three adjacent rows.
  • the occurrence time order of the signals of the plurality of selection signal lines being valid level signals may be the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the ninth selection signal line MUX 9 , the twelfth selection signal line MUX 12 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the seventh selection signal line MUX 7 , the tenth selection signal line MUX 10 , the second selection signal line MUX 2 , the fifth selection signal line MUX 5 , the eighth selection signal line MUX 8 , and the eleventh selection signal line MUX 11 .
  • the occurrence time order of the signals of the multiple selection signal lines being valid level signals may be the twelfth selection signal line MUX 12 , the ninth selection signal line MUX 9 , the sixth selection signal line MUX 6 , the third selection signal line MUX 3 , the tenth selection signal line MUX 10 , the seventh selection signal line MUX 7 , the fourth selection signal line MUX 4 , the first selection signal line MUX 1 , the eleventh selection signal line MUX 11 , the eighth selection signal line MUX 8 , the fifth selection signal line MUX 5 , and the second selection signal line MUX 2 .
  • the occurrence time order of the signals of the multiple selection signal lines being valid level signals may be the sixth selection signal line MUX 6 , the third selection signal line MUX 3 , the twelfth selection signal line MUX 12 , the ninth selection signal line MUX 9 , the fourth selection signal line MUX 4 , the first selection signal line MUX 1 , the tenth selection signal line MUX 10 , the seventh selection signal line MUX 7 , the fifth selection signal line MUX 5 , the second selection signal line MUX 2 , the eleventh selection signal line MUX 11 , and the eighth selection signal line MUX 8 .
  • the order of the occurrence time when the signals of the multiple selection signal lines are valid level signals is the ninth selection signal line MUX 9 , the twelfth selection signal line MUX 12 , the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the seventh selection signal line MUX 7 , the tenth selection signal line MUX 10 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the eighth selection signal line MUX 8 , the eleventh selection signal line MUX 11 , the second selection signal line MUX 2 , and the fifth selection signal line MUX 5.
  • the positions of the occurrence time when the signals of the selection signal lines are valid level are different. For example, taking the first to fourth rows as an example, the position of the occurrence time when the signal of the first selection signal line MUX 1 is valid level signal when the first row is displayed is the 4rth row. 5. When displayed in the second row, the position is eighth, when displayed in the third row, the position is sixth, and when displayed in the fourth row, the position is seventh, that is, the positions in the first row to the fourth row are not the same. Similarly, the occurrence time of the signals of the remaining selection signal lines as valid level signals is different in the positions of the four adjacent rows.
  • the signals of the multiple selection signal lines are valid level signals in the same occurrence time sequence
  • the signals of the multiple selection signal lines are valid level signals in the same occurrence time sequence
  • the signals of the multiple selection signal lines are valid level signals in the same occurrence time sequence
  • the signals of the multiple selection signal lines are valid level signals in the same occurrence time sequence
  • the signals of the multiple selection signal lines are valid level signals in the same occurrence time sequence
  • the signals of the multiple selection signal lines are valid level signals in the same occurrence time sequence
  • the signals of the multiple selection signal lines are valid level signals in the same occurrence time sequence
  • the signals of the multiple selection signal lines are valid level signals in the same occurrence time sequence.
  • the occurrence time sequence of the signals of multiple selection signal lines in the same selection signal group being valid level signals is different, and the occurrence time of the signals of the same selection signal line being valid level signals is different in the positions when different rows are displayed.
  • adjacent M/3 display frames when different display frames are displayed, the occurrence time sequence of the signals of multiple selection signal lines in the same selection signal group being valid level signals is different, and the occurrence time of the signals of the same selection signal line being valid level signals is different in the positions when different display frames are displayed.
  • the occurrence time sequence of the signals of the multiple selection signal lines being valid level signals is the same.
  • the order in which the signals of the multiple selection signal lines are valid level signals is the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the second selection signal line MUX 2 , and the fifth selection signal line MUX 5 ;
  • the order in which the signals of the multiple selection signal lines are valid level signals is the sixth selection signal line MUX 6 , the third selection signal line MUX 3 , the fourth selection signal line MUX 4 , the first selection signal line MUX 1 , the fifth selection signal line MUX 5 , and the second selection signal line MUX 2 ;
  • the even-numbered rows in the even-numbered frame are displayed the order in which the signals of the multiple selection signal lines are valid level signals is the third selection signal line MUX 3 , the sixth selection signal line MUX 6 , the first selection signal line MUX 1 , the fourth selection signal line MUX 4 , the second selection signal line MUX
  • the signals of the multiple selection signal lines are valid level signals in the same time sequence
  • the signals of the multiple selection signal lines are valid level signals.
  • the occurrence time sequence of the signals of multiple selection signal lines as valid level signals is the same; when all even-numbered lines are displayed, the occurrence time sequence of the signals of multiple selection signal lines as valid level signals is the same.
  • the display substrate may include: a first signal line, the first signal line includes at least: a scanning signal line, the first signal line and the data signal line are arranged in different layers, and the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate, and the capacitance located between the overlapping area of the data signal line and the first signal line is the data parasitic capacitance of the data signal line.
  • the first signal line may further include at least one of a reset signal line and an initial signal line.
  • data parasitic capacitances of a plurality of data signal lines electrically connected to the same color sub-pixel are different.
  • the data parasitic capacitance of the ath data signal line is greater than the data parasitic capacitance of the bth data signal line.
  • the data parasitic capacitance of the ath data signal line is greater than the data parasitic capacitance of the bth data signal line, which can ensure that the attenuation of the data voltage of the data signal line that is written first is reduced, and further, the attenuation consistency of the stored data voltages on the multiple data signal lines electrically connected to the same selection signal group is reduced, which can improve the display effect of the display substrate.
  • data parasitic capacitances of at least two data signal lines electrically connected to different color sub-pixels may be unequal.
  • data parasitic capacitances of at least two data signal lines electrically connected to sub-pixels of different colors are equal.
  • data parasitic capacitances of the 3i-2 th to 3i th data signal lines may be equal.
  • the embodiment of the present disclosure further provides a display device, including: a display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are well understood by those skilled in the art and are not described in detail herein, nor should they be used as limitations on the present application.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the embodiment of the present disclosure further provides a method for driving a display substrate, which is used to drive the above-mentioned display substrate.
  • the method includes:
  • Signals are supplied to the plurality of selection signal lines so that effective time periods of any two selection signal groups among the plurality of selection signal groups do not overlap.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the thickness and size of the layer or microstructure are exaggerated. It is understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示基板及其驱动方法、显示装置，其中，显示基板包括：阵列排布的多个子像素、多路复用电路、多条数据信号线，多条选择信号线和多条数据传输线，多个子像素包括：多种颜色子像素，数据信号线与多个子像素电连接；多路复用电路包括：多个复用晶体管，复用晶体管分别与数据传输线、选择信号线和数据信号线电连接；多条选择信号线被划分为多个选择信号组，至少一个选择信号组包括：多条选择信号线，不同选择信号组包括的选择信号线不同，选择信号组通过复用晶体管和数据信号线与子像素电连接；同一选择信号组电连接的子像素的颜色相同，不同选择信号组电连接的子像素颜色不同，多个选择信号组中的任意两个选择信号组的有效时间段不交叠。

Description

显示基板及其驱动方法、显示装置
本申请要求于2022年10月27日提交中国专利局、申请号为202211329365.X、发明名称为“显示基板及其驱动方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引入的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本申请详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：阵列排布的多个子像素、多路复用电路、多条数据信号线，多条选择信号线和多条数据传输线，所述多个子像素包括：多种颜色子像素，所述数据信号线与所述多个子像素电连接；
所述多路复用电路包括：多个复用晶体管，所述复用晶体管分别与所述数据传输线、所述选择信号线和所述数据信号线电连接，所述复用晶体管被配置为在所述选择信号线的控制下，将所述数据传输线的信号传递给所述数据信号线；
所述多条选择信号线被划分为多个选择信号组，至少一个选择信号组包括：多条选择信号线，不同选择信号组包括的选择信号线不同，所述选择信号组通过所述复用晶体管和所述数据信号线与所述子像素电连接；
同一选择信号组电连接的子像素的颜色相同，不同选择信号组电连接的子像素颜色不同，多个选择信号组中的任意两个选择信号组的有效时间段不交叠，其中，所述选择信号组的有效时间段指的是所述选择信号组的选择信号线中信号最早为有效电平信号的开始时间与信号最晚为有效电平信号的结束时间之间的时间段。
在示例性实施方式中，所述子像素包括：第一颜色子像素、第二颜色子像素和第三颜色子像素，第一颜色、第二颜色和第三颜色为不同颜色，且分别为红色、蓝色和绿色中的一种；
第i条数据信号线与第i列子像素电连接，第3×i-2列子像素为第一颜色子像素，第3×i-1列子像素为第二颜色子像素，第3×i列子像素为第三颜色子像素，其中，1≤i≤N/3，×为乘法运算，/为取商运算，N为数据信号线的数量，N为大于或者等于6的正整数。
在示例性实施方式中，所述多个选择信号组包括：第一选择信号组、第二选择信号组和第三选择信号组；
所述第一选择信号组电连接的子像素为第一颜色子像素，所述第二选择信号组电连接的子像素为第二颜色子像素，所述第三选择信号组电连接的子像素为第三颜色子像素。
在示例性实施方式中，与蓝色子像素电连接的选择信号组的有效时间段早于与红色子像素和绿色子像素电连接的选择信号组的有效时间段。
在示例性实施方式中，所述多路复用电路包括：N/M个复用子电路；
第j个复用子电路，分别与M条数据信号线、第j条数据传输线和M条选择信号线电连接，M为选择信号线的数量，j＝1，2，.......，N/M，M＝3×S，M为大于或者等于6的正整数，S为大于或者等于2的正整数。
在示例性实施方式中，所述复用晶体管的数量为N个，N个复用晶体管均为N型晶体管或均为P型晶体管；
第n个复用晶体管的控制极与第l条选择信号线电连接，第n个复用晶体管的第一极与第n条数据信号线电连接，第n个复用晶体管的第二极与第w条数据传输线电连接，％为取余运算，n＝1，2，.......，N；

第j个复用子电路包括：第M×(j-1)+1个复用晶体管至第M×j个复用晶体管。
在示例性实施方式中，还包括：多条扫描信号线，所述多条扫描信号线与所述多个子像素电连接；
在第m条选择信号线的信号为有效电平信号时，除第m条选择信号线之外的选择信号线的信号均为无效电平信号，m＝1，2，.......，M；
所述显示基板所显示的内容包括多个显示帧，在至少一个显示帧的第k行子像素显示时，多条选择信号线中的信号最晚为有效电平信号的结束时间早于与第k行子像素电连接的扫描信号线的信号为有效电平信号的开始时间。
在示例性实施方式中，在同一显示帧，同一显示帧中的所有行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同；
在不同显示帧，同一行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。
在示例性实施方式中，在同一显示帧，对于相邻的M/3行，不同行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同；
在不同显示帧，同一行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。
在示例性实施方式中，在同一显示帧，所在行数x满足x％(M/3)＝y的多行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，(M/3)-1。
在示例性实施方式中，在同一显示帧，同一显示帧中的所有行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同；
在相邻的M/3个显示帧，不同显示帧显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同显示帧显示时所在的位次不同。
在示例性实施方式中，对于所有显示帧，所在帧数z满足z％(M/3)＝y的多个显示帧显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，(M/3)-1。
在示例性实施方式中，在同一显示帧，对于相邻的M/3行，不同行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同；
在相邻的M/3个显示帧，不同显示帧同一行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同显示帧的同一行显示时所在的位次不同。
在示例性实施方式中，在同一显示帧，所在行数x满足x％(M/3)＝y的多行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同；
对于所有显示帧，所在帧数z满足z％(M/3)＝y的多个显示帧的同一行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，M/3-1。
在示例性实施方式中，包括：第一信号线，所述第一信号线至少包括：扫描信号线，所述第一信号线与数据信号线异层设置，且在基底上的正投影与数据信号线在基底上的正投影至少部分交叠，位于所述数据信号线与所述第一信号线的重叠区域之间的电容为数据信号线的数据寄生电容；
对于至少一个复用子电路，与同一颜色子像素电连接的多条数据信号线的数据寄生电容不同。
在示例性实施方式中，对于至少一个复用子电路，当与同一颜色子像素电连接的多条数据信号线中的第a条数据信号线所连接的复用晶体管所电连接的选择信号线的信号为有效电平信号的时间早于第b条数据信号线所连接的复用晶体管所连接的选择信号线的信号为有效电平信号的时间时，第a条数据信号线的数据寄生电容大于第b条数据信号线的数据寄生电容。
在示例性实施方式中，对于至少一个复用子电路，与不同颜色子像素电连接的至少两条数据信号线的数据寄生电容相等。
在示例性实施方式中，第3i-2条数据信号线至第3i条数据信号线的数据寄生电容相等。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
第三方面，本公开还提供了一种显示基板的驱动方法，用于驱动上述显示基板，所述方法包括：
向多条选择信号线提供信号，使得多个选择信号组中的任意两个选择信号组的有效时间段不交叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为一种像素驱动电路的工作时序图；
图6为本公开实施例提供的显示基板的结构示意图；
图7为多路复用电路的电路结构图；
图8为一种多路复用电路的等效电路图；
图9为另一多路复用电路的等效电路图；
图10为又一多路复用电路的等效电路图；
图11为显示基板的工作时序图一；
图12为显示基板的工作时序图二；
图13为显示基板的工作时序图三；
图14为显示基板的工作时序图四；
图15为显示基板的工作时序图五；
图16为显示基板的工作时序图六；
图17为显示基板的工作时序图七。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水 平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示装置中数据驱动芯片通过数据信号线向显示器中的子像素提供数据信号。由于显示装置中数据信号线数量较多，数据驱动芯片需要较多的引脚，这样向数据信号线传输数据信号的数据传输线也相应较多，不利于实现显示器的窄边框。为了实现全面屏，通过减少数据传输线的数量，显示基板在数据传输线和数据信号线之间设置多路复用电路MUX，多路复用电路MUX与多条选择信号线和数据传输线电连接。目前常用的方案是数据驱动芯片通过设置多路复用电路MUX使得一个数据传输线可以连接多列子像素，这样可以大大减少数据传输线的数量，降低数据驱动芯片的尺寸，减少显示器边框的尺寸。
为了保证可以向所有子像素提供数据信号，多路复用电路MUX与多条选择信号线电 连接，通过在选择信号线的控制下，向数据信号线提供数据传输线的信号。为了正常显示，多条选择信号线的多个选择信号必须依次打开，故在每行子像素显示时，多个数据信号线的数据电压在数据信号线上的寄生电容中保存的时间并不一致，而在此过程中不可避免地会有漏电产生，先写入的数据电压衰减最严重，而最后写入数据电压的衰减相对较低，这样便产生了数据电压差异引起的亮度差异，可能形成竖向的亮暗条纹，降低了显示基板的显示效果。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路可以分别与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元，多个像素单元的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形。
图3为一种显示基板的剖面结构示意图，示意了OLED显示基板三个子像素的结构。 如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中仅以一个晶体管101和一个存储电容101A作为示例。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括发光层(EML)以及如下任意一层或多层：空穴注入层HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的。
图4为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C，像素驱动电路可以与7个信号线(数据信号线D、扫描信号线Gate、复位信号线Reset、发光信号线EM、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与复位信号线Reset连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到复位信号线Reset时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与扫描信号线Gate连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到扫描信号线Gate时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的大小。
第四晶体管T4的控制极与扫描信号线Gate连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到扫描信号线Gate时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线EM时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与扫描信号线Gate连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到扫描信号线Gate时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。扫描信号线Gate为本显示行像素驱动电路中的扫描信号线，复位信号线Reset为上一显示行像素驱动电路中的扫描信号线Gate，本显示行的复位信号线Reset与上一显示行像素驱动电路中的扫描信号线Gate为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，复位信号线Reset的信号为低电平信号，扫描信号线Gate和发光信号线EM的信号为高电平信号。复位信号线Reset的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化(复位)，清除存储电容中原有电荷。扫描信号线Gate和发光信号线EM的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate的信号为低电平信号，复位信号线Reset和发光信号线EM的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。扫描信号线Gate的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。复位信号线Reset的信号为高电平信号，使第一晶体管T1断开。发光信号线EM的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线EM的信号为低电平信号，扫描信号线Gate和复位信号线Reset的信号为高电平信号。发光信号线EM的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[(Vdd-Vd]2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述电流公式的推导结果可以看出，在发光阶段，第三晶体管T3的驱动电流已经不受第三晶体管T3的阈值电压的影响，从而消除了第三晶体管T3的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
图6为本公开实施例提供的显示基板的结构示意图，如图6所示，本公开实施例提供的显示基板可以包括：阵列排布的多个子像素P、多路复用电路MUX、多条数据信号线D，多条选择信号线MUX和多条数据传输线S，多个子像素包括：多种颜色子像素，数据信号线与多个子像素电连接。图6中的Di表示第i条数据信号线，MUXi表示第i条选择信号线，Si表示第i条数据传输线。
在示例性实施方式中，多路复用电路可以包括：多个复用晶体管，复用晶体管分别与数据传输线、选择信号线和数据信号线电连接。复用晶体管被配置为在选择信号线的控制下，将数据传输线的信号传递给数据信号线。
在示例性实施方式中，多条选择信号线可以被划分为多个选择信号组，至少一个选择信号组包括：多条选择信号线，不同选择信号组包括的选择信号线不同，选择信号组通过复用晶体管和数据信号线与子像素电连接。同一选择信号组电连接的子像素的颜色相同，不同选择信号组电连接的子像素颜色不同，多个选择信号组中的任意两个选择信号组的有效时间段不交叠，其中，选择信号组的有效时间段指的是选择信号组的选择信号线中信号最早为有效电平信号的开始时间与信号最晚为有效电平信号的结束时间之间的时间段。
在示例性实施方式中，如图6所示，本公开实施例提供的显示基板还可以包括：扫描信号线Gate，其中，多个子像素与扫描信号线电连接。
在示例性实施方式中，显示基板包括：显示区域和非显示区域，其中，扫描信号线、数据信号线和子像素位于显示区域，多路复用电路位于非显示区域。
在示例性实施方式中，显示基板还包括：位于非显示区域的源极驱动芯片，源极驱动芯片与多条数据传输线电连接。
本公开实施例提供的显示基板可以采用低温多晶硅技术(Low Temperature Poly-silicon，简称LTPS)制程或者氧化物制程，本公开对此不作任何限定。
本公开通过设置同一选择信号组电连接的子像素的颜色相同，不同选择信号组电连接的子像素颜色不同，多个选择信号组中的任意两个选择信号组的有效时间段不交叠可以保证控制同一颜色子像素的选择信号组中的多条选择信号线的信号为有效电平信号的发生时间相邻，使得同一选择信号组电连接的多条数据信号线上的保存的数据电压的时间差异最小，可以减轻或避免因多条选择信号线先后开启造成的像素亮度差异问题，在宏观视觉上消除亮暗竖向条纹不良，提升了显示基板的显示效果。
在示例性实施方式中，如图6所示，子像素可以包括：第一颜色子像素、第二颜色子像素和第三颜色子像素，第一颜色、第二颜色和第三颜色为不同颜色，且分别为红色、蓝色和绿色中的一种。第一颜色可以为红色，第二颜色可以为绿色，第三颜色可以为蓝色，或者，第一颜色可以为红色，第二颜色可以为蓝色，第三颜色可以为绿色，或者，第一颜色可以为蓝色，第二颜色可以为红色，第三颜色可以为绿色，或者，第一颜色可以为蓝色，第二颜色可以为绿色，第三颜色可以为红色，或者，第一颜色可以为绿色，第二颜色可以为蓝色，第三颜色可以为红色，或者，第一颜色可以为绿色，第二颜色可以为红色，第三颜色可以为蓝色。
在示例性实施方式中，如图6所示，第i条数据信号线与第i列子像素电连接，第3i-2列子像素为第一颜色子像素，第3i-1列子像素为第二颜色子像素，第3i列子像素为第三颜色子像素，其中，1≤i≤N/3，/为取商运算，N为数据信号线的数量，N可以为大于或者等于6的正整数。示例性地，第一列子像素、第四列子像素、第七列子像素等列子像素的颜色为第一颜色，第二列子像素、第五列子像素、第八列子像素等列子像素的颜色为第二颜色，第三列子像素、第六列子像素、第九列子像素等的颜色为第三颜色。图6是以第一颜色为红色，第二颜色为绿色，第三颜色为蓝色为例进行说明的，本公开对此不做任何限定。
在示例性实施方式中，取商运算/具有如下定义：当a＝b×c+h时，a、b和c满足a/b＝c，其中，a、b、c、h为正整数，h大于或者等于0，且小于b，例如，1/6＝0，2/6＝0，3/6＝0，4/6＝0，5/6＝0，6/6＝1，7/6＝1，8/6＝1，12/6＝2，13/6＝2，14/6＝2，15/6＝2，14/9＝2，依次类推。
在示例性实施方式中，多个选择信号组可以包括：第一选择信号组、第二选择信号组和第三选择信号组。第一选择信号组电连接的子像素为第一颜色子像素，第二选择信号组 电连接的子像素为第二颜色子像素，第三选择信号组电连接的子像素为第三颜色子像素。
在示例性实施方式中，由于显示基板中发光器件的材料的特性，可以使得与蓝色子像素电连接的选择信号组的有效时间段早于与红色子像素和绿色子像素电连接的选择信号组的有效时间段。
在示例性实施方式中，与红色子像素电连接的选择信号组的有效时间段早于与蓝色子像素和绿色子像素电连接的选择信号组的有效时间段，或者可以使得与绿色子像素电连接的选择信号组的有效时间段早于与蓝色子像素和红色子像素电连接的选择信号组的有效时间段，选择信号的是有效时间段的发生顺序可以根据发光器件的特点确定，本公开对此不做任何限定。
在示例性实施方式中，图7为多路复用电路的电路结构图，图8为一种多路复用电路的等效电路图，图9为另一多路复用电路的等效电路图，图10为又一多路复用电路的等效电路图。如图7至图10所示，多路复用电路10可以包括：N/M个复用子电路20；第j个复用子电路，分别与M条数据信号线、第j条数据传输线Sj和M条选择信号线MUX1至MUXM电连接，M为选择信号线的数量，j＝1，2，.......，N/M。
在示例性实施方式中，第j个复用子电路可以与第M×(j-1)+1条数据信号线至第M×j条数据信号线电连接。示例性地，第一个复用子电路，分别与第一条数据信号线至第M条数据信号线、第一条数据传输线和第一条选择信号线至第M条选择信号线电连接，第二个复用子电路，分别与第M+1条数据信号线至第2M条数据信号线、第二条数据传输线和第一条选择信号线至第M条选择信号线电连接，依次类推，第N/M个复用子电路，分别与第N-M+1条数据信号线至第N条数据信号线、第N/M条数据传输线和第一条选择信号线至第M条选择信号线电连接。
在示例性实施方式中，M＝3×S，S为大于或者等于2的正整数，M为大于或者等于6的正整数，且为3的整数倍。示例性地，M可以为6、9或者12，本公开对此不做任何限定。图8是以M＝6为例进行说明的，图9是以M＝9为例进行说明的，图10是以M＝12为例进行说明的。
示例性地，如图8所示，当M＝6时，第一个复用子电路分别与第一条数据信号线至第六条数据信号线、第一条数据传输线和第一条选择信号线至第六条选择信号线电连接，第二个复用子电路分别与第七条数据信号线至第十二条数据信号线、第二条数据传输线和第一条选择信号线至第六条选择信号线电连接，依次类推，第N/6个复用子电路，分别与第N-5条数据信号线至第N条数据信号线、第N/6条数据传输线和第一条选择信号线至第六条选择信号线电连接。
示例性地，如图9所示，当M＝9时，第一个复用子电路分别与第一条数据信号线至第九条数据信号线、第一条数据传输线和第一条选择信号线至第九条选择信号线电连接，第二个复用子电路分别与第十条数据信号线至第十八条数据信号线、第二条数据传输线和第一条选择信号线至第九条选择信号线电连接，依次类推，第N/9个复用子电路，分别与第N-8条数据信号线至第N条数据信号线、第N/9条数据传输线和第一条选择信号线至第九条选择信号线电连接。
示例性地，如图10所示，当M＝12时，第一个复用子电路分别与第一条数据信号线至第十二条数据信号线、第一条数据传输线和第一条选择信号线至第十二条选择信号线电连接，第二个复用子电路分别与第十三条数据信号线至第二十四条数据信号线、第二条数据传输线和第一条选择信号线至第九条选择信号线电连接，依次类推，第N/12个复用子电路，分别与第N-11条数据信号线至第N条数据信号线、第N/12条数据传输线和第一 条选择信号线至第十二条选择信号线电连接。
在示例性实施方式中，如图8至图10所示，复位晶体管的数量与数据信号线的数量可以相同，也就是说，复用晶体管的数量可以为N个。
在示例性实施方式中，如图8至图10所示，第n个复用晶体管Fn的控制极与第l条选择信号线MUXl电连接，第n个复用晶体管Fn的第一极与第n条数据信号线Dn电连接，第n个复用晶体管Fn的第二极与第w条数据传输线Sw电连接，％为取余运算，n＝1，2，.......，N。
在示例性实施方式中，l可以满足如下公式：
在示例性实施方式中，取余运算％具有如下定义：当a＝b×c+h时，a、c、h满足a％b＝h，其中，a、b、c、h为正整数，h大于或者等于0，且小于b，例如，1％6＝1，2％6＝2，3％6＝3，4％6＝4，5％6＝5，6％6＝0，7％6＝1，8％6＝2，12％6＝0，13％6＝1，3％9＝3，10％9＝1，依次类推。
示例性地，以M＝6为例，n为6的倍数时例如6、12、18等，l＝6，也就是说，第六个复用晶体管、第十二复用晶体管、第十八复用晶体管等的控制极与第六选择信号线电连接，n不为6的倍数时，l＝n％M，也就是说，满足n％6＝1的所有复用晶体管例如第一个复用晶体管、第七个复用晶体管、第十三个复用晶体管等的控制极与第一选择信号线电连接，满足n％6＝2的所有复用晶体管例如第二个复用晶体管、第八个复用晶体管、第十四个复用晶体管等的控制极与第二选择信号线电连接，满足n％6＝3的所有复用晶体管例如第三个复用晶体管、第九个复用晶体管、第十五个复用晶体管等的控制极与第三选择信号线电连接，满足n％6＝4的所有复用晶体管例如第四个复用晶体管、第十个复用晶体管、第十六个复用晶体管等的控制极与第四选择信号线电连接，满足n％6＝5的所有复用晶体管例如第五个复用晶体管、第十一个复用晶体管、第十七个复用晶体管等的控制极与第五选择信号线电连接，M＝9或者12时，依次类推，本公开对此不做任何限定。
在示例性实施方式中，w满足如下公式：
示例性地，以M＝6为例，n为6的整数倍时，第六个复用晶体管的第二极与第6/6条数据传输线，即第一条数据传输线电连接，第十二个复用晶体管的第二极与第12/6条数据传输线，即第二条数据传输线电连接，第十八个复用晶体管的第二极与第18/6条数据传输线，即第三条数据传输线电连接，依次类推。n不为6的整数倍时，第一个复用晶体管至第五个复用晶体管的第二极均与第一条数据传输线电连接，第七个复用晶体管至第十一个复用晶体管的第二极均与第二条数据传输线电连接，依次类推，M＝9或者12时，依次类推，本公开对此不做任何限定。
在示例性实施方式，第j个复用子电路可以包括：第M×(j-1)+1个复用晶体管至第M×j个复用晶体管。示例性地，当M＝6时，第一个复用子电路包括：第一个复用晶体管至第六个复用晶体管，第二复用子电路包括：第七个复用晶体管至第十二个复用晶体管，依次类推。当M＝9时，第一个复用子电路包括：第一个复用晶体管至第九个复用晶体管，第二复用子电路包括：第十个复用晶体管至第十八个复用晶体管，依次类推。当M＝12 时，第一个复用子电路包括：第一个复用晶体管至第十二个复用晶体管，第二复用子电路包括：第十三个复用晶体管至第二十四个复用晶体管，依次类推。
在示例性实施方式，N个复用晶体管可以均为N型晶体管或均为P型晶体管。本公开对此不做任何限定。
在示例性实施方式，如图8所示，当M＝6时，与第一颜色子像素电连接的第一选择信号组可以包括：第一条选择信号线MUX1和第四条选择信号线MUX4，与第二颜色子像素电连接的第二选择信号组可以包括：第二条选择信号线MUX2和第五条选择信号线MUX5，与第三颜色子像素电连接的第三选择信号组可以包括：第三条选择信号线MUX3和第六条选择信号线MUX6。
在示例性实施方式中，如图8所示，第一个复用晶体管F1的控制极与第一条选择信号线MUX1电连接，第一个复用晶体管F1的第一极与第一条数据信号线D1电连接，第一个复用晶体管F1的第二极与第一条数据传输线S1电连接，第二个复用晶体管F2的控制极与第二条选择信号线MUX2电连接，第二个复用晶体管F2的第一极与第二条数据信号线D2电连接，第二个复用晶体管F2的第二极与第一条数据传输线S1电连接，第三个复用晶体管F3的控制极与第三条选择信号线MUX3电连接，第三个复用晶体管F3的第一极与第三条数据信号线D3电连接，第三个复用晶体管F3的第二极与第一条数据传输线S1电连接，第四个复用晶体管F4的控制极与第四条选择信号线MUX4电连接，第四个复用晶体管F4的第一极与第四条数据信号线D4电连接，第四个复用晶体管F4的第二极与第一条数据传输线S1电连接，第五个复用晶体管F5的控制极与第五条选择信号线MUX5电连接，第五个复用晶体管F5的第一极与第五条数据信号线D5电连接，第五个复用晶体管F5的第二极与第一条数据传输线S1电连接，第六个复用晶体管F6的控制极与第六条选择信号线MUX6电连接，第六个复用晶体管F6的第一极与第六条数据信号线D6电连接，第六个复用晶体管F6的第二极与第一条数据传输线S1电连接，第七个复用晶体管F7的控制极与第一条选择信号线MUX1电连接，第七个复用晶体管F7的第一极与第七条数据信号线D7电连接，第七个复用晶体管F7的第二极与第二条数据传输线S2电连接，第八个复用晶体管F8的控制极与第二条选择信号线MUX2电连接，第八个复用晶体管F8的第一极与第八条数据信号线D8电连接，第八个复用晶体管F8的第二极与第二条数据传输线S2电连接，第九个复用晶体管F9的控制极与第三条选择信号线MUX3电连接，第九个复用晶体管F9的第一极与第九条数据信号线D9电连接，第九个复用晶体管F9的第二极与第二条数据传输线S2电连接，第十个复用晶体管F10的控制极与第四条选择信号线MUX4电连接，第十个复用晶体管F10的第一极与第十条数据信号线D10电连接，第十个复用晶体管F10的第二极与第二条数据传输线S2电连接，第十一个复用晶体管F11的控制极与第五条选择信号线MUX5电连接，第十一个复用晶体管F11的第一极与第十一条数据信号线D11电连接，第十一个复用晶体管F11的第二极与第二条数据传输线S2电连接，第十二个复用晶体管F12的控制极与第六条选择信号线MUX6电连接，第十二个复用晶体管F12的第一极与第十二条数据信号线D12电连接，第十二个复用晶体管F12的第二极与第二条数据传输线S2电连接，依次类推。
在示例性实施方式，如图9所示，当M＝9时，与第一颜色子像素电连接的第一选择信号组可以包括：第一条选择信号线MUX1、第四条选择信号线MUX4和第七条选择信号线MUX7，与第二颜色子像素电连接的第二选择信号组可以包括：第二条选择信号线MUX2、第五条选择信号线MUX5和第八条选择信号线MUX8，与第三颜色子像素电连接的第三选择信号组可以包括：第三条选择信号线MUX3、第六条选择信号线MUX6和第九条选择信号线MUX9。
在示例性实施方式中，如图9所示，第一个复用晶体管F1的控制极与第一条选择信号线MUX1电连接，第一个复用晶体管F1的第一极与第一条数据信号线D1电连接，第一个复用晶体管F1的第二极与第一条数据传输线S1电连接，第二个复用晶体管F2的控制极与第二条选择信号线MUX2电连接，第二个复用晶体管F2的第一极与第二条数据信号线D2电连接，第二个复用晶体管F2的第二极与第一条数据传输线S1电连接，第三个复用晶体管F3的控制极与第三条选择信号线MUX3电连接，第三个复用晶体管F3的第一极与第三条数据信号线D3电连接，第三个复用晶体管F3的第二极与第一条数据传输线S1电连接，第四个复用晶体管F4的控制极与第四条选择信号线MUX4电连接，第四个复用晶体管F4的第一极与第四条数据信号线D4电连接，第四个复用晶体管F4的第二极与第一条数据传输线S1电连接，第五个复用晶体管F5的控制极与第五条选择信号线MUX5电连接，第五个复用晶体管F5的第一极与第五条数据信号线D5电连接，第五个复用晶体管F5的第二极与第一条数据传输线S1电连接，第六个复用晶体管F6的控制极与第六条选择信号线MUX6电连接，第六个复用晶体管F6的第一极与第六条数据信号线D6电连接，第六个复用晶体管F6的第二极与第一条数据传输线S1电连接，第七个复用晶体管F7的控制极与第七条选择信号线MUX7电连接，第七个复用晶体管F7的第一极与第七条数据信号线D7电连接，第七个复用晶体管F7的第二极与第一条数据传输线S1电连接，第八个复用晶体管F8的控制极与第八条选择信号线MUX8电连接，第八个复用晶体管F8的第一极与第八条数据信号线D8电连接，第八个复用晶体管F8的第二极与第一条数据传输线S1电连接，第九个复用晶体管F9的控制极与第九条选择信号线MUX9电连接，第九个复用晶体管F9的第一极与第九条数据信号线D9电连接，第九个复用晶体管F9的第二极与第一条数据传输线S1电连接，第十个复用晶体管F10的控制极与第一条选择信号线MUX1电连接，第十个复用晶体管F10的第一极与第十条数据信号线D10电连接，第十个复用晶体管F10的第二极与第二条数据传输线S2电连接，第十一个复用晶体管F11的控制极与第二条选择信号线MUX2电连接，第十一个复用晶体管F11的第一极与第十一条数据信号线D11电连接，第十一个复用晶体管F11的第二极与第二条数据传输线S2电连接，第十二个复用晶体管F12的控制极与第三条选择信号线MUX3电连接，第十二个复用晶体管F12的第一极与第十二条数据信号线D12电连接，第十二个复用晶体管F12的第二极与第二条数据传输线S2电连接，依次类推。
在示例性实施方式，如图10所示，当M＝12时，第一选择信号组可以包括：第一条选择信号线MUX1、第四条选择信号线MUX4、第七条选择信号线MUX7和第十条选择信号线MUX10，第二选择信号组可以包括：第二条选择信号线MUX2、第五条选择信号线MUX5、第八条选择信号线MUX8和第十一条选择信号线MUX11，第三选择信号组可以包括：第三条选择信号线MUX3、第六条选择信号线MUX6、第九条选择信号线MUX9和第十二条选择信号线MUX12。
在示例性实施方式中，如图10所示，第一个复用晶体管F1的控制极与第一条选择信号线MUX1电连接，第一个复用晶体管F1的第一极与第一条数据信号线D1电连接，第一个复用晶体管F1的第二极与第一条数据传输线S1电连接，第二个复用晶体管F2的控制极与第二条选择信号线MUX2电连接，第二个复用晶体管F2的第一极与第二条数据信号线D2电连接，第二个复用晶体管F2的第二极与第一条数据传输线S1电连接，第三个复用晶体管F3的控制极与第三条选择信号线MUX3电连接，第三个复用晶体管F3的第一极与第三条数据信号线D3电连接，第三个复用晶体管F3的第二极与第一条数据传输线S1电连接，第四个复用晶体管F4的控制极与第四条选择信号线MUX4电连接，第四个复用晶体管F4的第一极与第四条数据信号线D4电连接，第四个复用晶体管F4的第二极与第一条数据传输线S1电连接，第五个复用晶体管F5的控制极与第五条选择信号线 MUX5电连接，第五个复用晶体管F5的第一极与第五条数据信号线D5电连接，第五个复用晶体管F5的第二极与第一条数据传输线S1电连接，第六个复用晶体管F6的控制极与第六条选择信号线MUX6电连接，第六个复用晶体管F6的第一极与第六条数据信号线D6电连接，第六个复用晶体管F6的第二极与第一条数据传输线S1电连接，第七个复用晶体管F7的控制极与第七条选择信号线MUX7电连接，第七个复用晶体管F7的第一极与第七条数据信号线D7电连接，第七个复用晶体管F7的第二极与第一条数据传输线S1电连接，第八个复用晶体管F8的控制极与第八条选择信号线MUX8电连接，第八个复用晶体管F8的第一极与第八条数据信号线D8电连接，第八个复用晶体管F8的第二极与第一条数据传输线S1电连接，第九个复用晶体管F9的控制极与第九条选择信号线MUX9电连接，第九个复用晶体管F9的第一极与第九条数据信号线D9电连接，第九个复用晶体管F9的第二极与第一条数据传输线S1电连接，第十个复用晶体管F10的控制极与第十条选择信号线MUX10电连接，第十个复用晶体管F10的第一极与第十条数据信号线D10电连接，第十个复用晶体管F10的第二极与第一条数据传输线S1电连接，第十一个复用晶体管F11的控制极与第十一条选择信号线MUX11电连接，第十一个复用晶体管F11的第一极与第十一条数据信号线D11电连接，第十一个复用晶体管F11的第二极与第一条数据传输线S1电连接，第十二个复用晶体管F12的控制极与第十二条选择信号线MUX12电连接，第十二个复用晶体管F12的第一极与第十二条数据信号线D12电连接，第十二个复用晶体管F12的第二极与第一条数据传输线S1电连接，依次类推。
图11为显示基板的工作时序图一，图12为显示基板的工作时序图二，图13为显示基板的工作时序图三，图14为显示基板的工作时序图四，图15为显示基板的工作时序图五，图16为显示基板的工作时序图六，图17为显示基板的工作时序图七。图11至图17中的Gate1为第一行子像素电连接的扫描信号线的信号，EM1为第一行子像素电连接的发光信号线的信号，Reset1为第一行子像素电连接的复位信号线的信号，第i行表示第i行子像素显示时，图11、图14和图15是以M＝6为例进行说明的，图12和图16是以M＝9为例进行说明的，图13和图17是以M＝12为例进行说明的。
在示例性实施方式中，如图11至图17所示，在第m条选择信号线的信号为有效电平信号时，除第m条选择信号线之外的选择信号线的信号均为无效电平信号，m＝1，2，.......，M。示例性地，当第一条选择信号线的信号为有效电平信号时，其余的所有选择信号线的信号为无效电平信号。
在示例性实施方式中，如图11至图17所示，显示基板所显示的内容包括多个显示帧，在至少一个显示帧的第k行子像素显示时，多条选择信号线中的信号最晚为有效电平信号的结束时间早于与第k行子像素电连接的扫描信号线的信号为有效电平信号的开始时间。以图11为例，多条选择信号线中的信号最晚为有效电平信号的结束时间指的是第五条选择信号线的信号为有效电平信号的结束时间，以图12为例，多条选择信号线中的信号最晚为有效电平信号的结束时间指的是第八条选择信号线MUX8的信号为有效电平信号的结束时间，以图13为例，多条选择信号线中的信号最晚为有效电平信号的结束时间指的是第十一条选择信号线MUX11的信号为有效电平信号的结束时间。
在示例性实施方式中，当M＝6时，图11是以第一选择信号组中的信号最早为有效电平信号的信号线为第一条选择信号线MUX1，信号最晚为有效电平信号的信号线为第四条选择信号线MUX4为例进行说明的，第一选择信号组的有效时间段t1指的是第一条选择信号线MUX1的信号为有效电平信号的开始时间与第四条选择信号线MUX4的信号为有效电平信号的结束时间之间的时间段。第二选择信号组中的信号最早为有效电平信号的信号线为第二条选择信号线MUX2，信号最晚为有效电平信号的信号线为第五条选择信号线 MUX5为例进行说明的，第二选择信号组的有效时间段t2指的是第二条选择信号线MUX2的信号为有效电平信号的开始时间与第五条选择信号线MUX5的信号为有效电平信号的结束时间之间的时间段。第三选择信号组中的信号最早为有效电平信号的信号线为第三条选择信号线MUX3，信号最晚为有效电平信号的信号线为第六条选择信号线MUX6为例进行说明的。第三选择信号组的有效时间段t3指的是第三条选择信号线MUX3的信号为有效电平信号的开始时间与第六条选择信号线MUX6的信号为有效电平信号的结束时间之间的时间段。以位于第一行，且第一个复用子电路电连接的子像素为例，根据图11提供的工作时序可知，其电连接的子像素发光顺序依次为第一行第三列子像素、第一行第六列子像素、第一行第一列子像素、第一行第四列子像素、第一行第二列子像素、第一行第五列子像素，本公开对此不做任何限定。
在示例性实施方式中，当M＝9时，图12是以第一选择信号组中的信号最早为有效电平信号的信号线为第一条选择信号线MUX1，信号最晚为有效电平信号的信号线为第七条选择信号线MUX7为例进行说明的，第一选择信号组的有效时间段t1指的是第一条选择信号线MUX1的信号为有效电平信号的开始时间与第七条选择信号线MUX7的信号为有效电平信号的结束时间之间的时间段。第二选择信号组中的信号最早为有效电平信号的信号线为第二条选择信号线MUX2，信号最晚为有效电平信号的信号线为第八条选择信号线MUX8为例进行说明的，第二选择信号组的有效时间段t2指的是第二条选择信号线MUX2的信号为有效电平信号的开始时间与第八条选择信号线MUX8的信号为有效电平信号的结束时间之间的时间段。第三选择信号组中的信号最早为有效电平信号的信号线为第三条选择信号线MUX3，信号最晚为有效电平信号的信号线为第九条选择信号线MUX9为例进行说明的，第三选择信号组的有效时间段t3指的是第三条选择信号线MUX3的信号为有效电平信号的开始时间与第九条选择信号线MUX9的信号为有效电平信号的结束时间之间的时间段。以位于第一行，且第一个复用子电路电连接的子像素为例，根据图12提供的工作时序可知，其电连接的子像素发光顺序依次为第一行第三列子像素、第一行第六列子像素、第一行第九列子像素、第一行第一列子像素、第一行第四列子像素、第一行第七列子像素、第一行第二列子像素、第一行第五列子像素，第一行第八列子像素、本公开对此不做任何限定。
在示例性实施方式中，当M＝12时，图13是以第一选择信号组中的信号最早为有效电平信号的信号线为第一条选择信号线MUX1，信号最晚为有效电平信号的信号线为第十条选择信号线MUX10为例进行说明的，第一选择信号组的有效时间段t1指的是第一条选择信号线MUX1的信号为有效电平信号的开始时间与第十条选择信号线MUX10的信号为有效电平信号的结束时间之间的时间段。第二选择信号组中的信号最早为有效电平信号的信号线为第二条选择信号线MUX2，信号最晚为为有效电平信号的信号线为第十一条选择信号线MUX11为例进行说明的，第二选择信号组的有效时间段t2指的是第二条选择信号线MUX2的信号为有效电平信号的开始时间与第十一条选择信号线MUX11的信号为有效电平信号的结束时间之间的时间段。第三选择信号组中的信号最早为有效电平信号的信号线为第三条选择信号线MUX3，信号最晚为为有效电平信号的信号线为第十二条选择信号线MUX12为例进行说明的，第三选择信号组的有效时间段t3指的是第三条选择信号线MUX3的信号为有效电平信号的开始时间与第十二条选择信号线MUX12的信号为有效电平信号的结束时间之间的时间段。以位于第一行，且第一个复用子电路电连接的子像素为例，根据图13提供的工作时序可知，其电连接的子像素发光顺序依次为第一行第三列子像素、第一行第六列子像素、第一行第九列子像素、第一行第十二列子像素、第一行第一列子像素、第一行第四列子像素、第一行第七列子像素、第一行第十列子像素、第一行第二列子像素、第一行第五列子像素，第一行第八列子像素、第一行第十一列子像素、本公开对此 不做任何限定。
在示例性实施方式中，如图11至图13所示，在同一显示帧，同一显示帧中的所有行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，在不同显示帧，同一行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。
在示例性实施方式中，以图11为例，在每一帧所有行显示时，多条选择信号线的发生时间顺序可以依次为第三条选择信号线MUX3、第六条选择信号线MUX6、第一条选择信号线MUX1、第四条选择信号线MUX4，第二条选择信号线MUX2、第五条选择信号线MUX5。以图12为例，在每一帧所有行显示时，多条选择信号线的发生时间顺序依次为第三条选择信号线MUX3、第六条选择信号线MUX6、第九条选择信号线MUX9、第一条选择信号线MUX1、第四条选择信号线MUX4、第七条选择信号线MUX7、第二条选择信号线MUX2、第五条选择信号线MUX5、第八条选择信号线MUX8。以图13为例，在每一帧所有行显示时，多条选择信号线的发生时间顺序依次为第三条选择信号线MUX3、第六条选择信号线MUX6、第九条选择信号线MUX9、第十二条选择信号线MUX12、第一条选择信号线MUX1、第四条选择信号线MUX4、第七条选择信号线MUX7、第十条选择信号线MUX10、第二条选择信号线MUX2、第五条选择信号线MUX5、第八条选择信号线MUX8、第十一条选择信号线MUX11。
在示例性实施方式中，在不同显示帧，同一行显示时的多条选择信号线的信号为有效电平信号的发生时间顺序相同指的是任意两个显示帧中的第i行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序均一致。
在示例性实施方式中，如图11至图13所示，在同一显示帧，同一显示帧中的所有行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。在相邻的M/3个显示帧，不同显示帧显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同显示帧显示时所在的位次不同。对于所有显示帧，所在帧数z满足z％(M/3)＝y的多个显示帧显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，(M/3)-1。
示例性地，当M＝6时，在相邻的2个显示帧，不同显示帧显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同显示帧显示时所在的位次不同。例如，奇数显示帧中的所有行显示时，多条选择信号线的信号为有效电平信号的发生顺序可以依次为第三条选择信号线MUX3、第六条选择信号线MUX6、第一条选择信号线MUX1、第四条选择信号线MUX4、第二条选择信号线MUX2、第五条选择信号线MUX5，偶数显示帧中的所有行显示时，多条选择信号线的信号为有效电平信号的发生顺序可以依次为第六条选择信号线MUX6、第三条选择信号线MUX3、第四条选择信号线MUX4、第一条选择信号线MUX1、第五条选择信号线MUX5，第二条选择信号线MUX2。其中，第一选择信号线MUX1的信号为有效电平信号的发生时间在奇数显示帧显示时所在的位次为第三，在偶数显示帧显示时所在的位次为第四，即在奇数显示帧和偶数显示帧时所在的位次并不相同，同样的其余选择信号线的信号为有效电平信号的发生时间在奇数显示帧和偶数显示帧所在的位次均不相同。
示例性地，以M＝9为例，第3j-2显示帧(例如第一显示帧、第四显示帧、第七显示帧等)中的所有行显示时，多条选择信号线的信号为有效电平信号的发生顺序依次为第三条选择信号线MUX3、第六条选择信号线MUX6、第九条选择信号线MUX9、第一条选择信号线MUX1、第四条选择信号线MUX4、第七条选择信号线MUX7、第二条选择信号线MUX2、第五条选择信号线MUX5，第八条选择信号线MUX8。第3j-1显示帧(例如第二显示帧、第五显示帧、第八显示帧等)中的所有行显示时，多条选择信号线的信号为有效 电平信号的发生顺序可以依次为第六条选择信号线MUX6、第九条选择信号线MUX9、第三条选择信号线MUX3、第四条选择信号线MUX4、第七条选择信号线MUX7、第一条选择信号线MUX1、第五条选择信号线MUX5，第八条选择信号线MUX8、第二条选择信号线MUX2。第3j显示帧(例如第三显示帧、第六显示帧、第九显示帧等)中的所有行显示时，多条选择信号线的信号为有效电平信号的发生顺序可以依次为第九条选择信号线MUX9、第三条选择信号线MUX3、第六条选择信号线MUX6、第七条选择信号线MUX7、第一条选择信号线MUX1、第四条选择信号线MUX4、第八条选择信号线MUX8、第二条选择信号线MUX2、第五条选择信号线MUX5。当M＝12时依次类推。其中，以第一显示帧至第三显示帧为例，第一选择信号线MUX1的信号为有效电平信号的发生时间在第一显示帧显示时所在的位次为第四，在第二显示帧显示时所在的位次为第六，在第三显示帧显示时所在的位次为第五，即在第一显示帧至第三显示帧时所在的位次并不相同，同样的其余选择信号线的信号为有效电平信号的发生时间在相邻三个显示帧所在的位次均不相同。
本公开通过在相邻的M/3个显示帧，不同显示帧显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同显示帧显示时所在的位次不同可以为避免出现奇偶列亮暗条纹。
示例性地，当M＝6时，所在帧数满足z％2＝0的所有显示帧例如第二显示帧、第四显示帧、第六显示帧等偶数显示帧显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。所在帧数满足z％2＝1的所有显示帧例如第一显示帧、第三显示帧、第五显示帧等奇数显示帧显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。示例性地，当M＝9时，所在帧数满足z％3＝1的所有显示帧(第一显示帧、第四显示帧、第七显示帧等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所在帧数满足z％3＝2的所有显示帧(第二显示帧、第五显示帧、第八显示帧等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有满足z％3＝0的所有显示帧(第三显示帧、第六显示帧、第九显示帧等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。示例性地，当M＝12时，所在帧数满足z％4＝1的所有显示帧(第一显示帧、第五显示帧、第九显示帧等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所在帧数满足z％4＝2的所有显示帧(第二显示帧、第六显示帧、第十显示帧等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所在帧数满足z％4＝3的所有显示帧(第三显示帧、第七显示帧、第十一显示帧等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所在帧数满足z％4＝0的所有显示帧(第四显示帧、第八显示帧、第十二显示帧等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。
在示例性实施方式中，如图14至图17所示，在同一显示帧，对于相邻的M/3行，不同行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同。在不同显示帧，同一行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。在同一显示帧，所在行数x满足x％(M/3)＝y的多行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，(M/3)-1。
本公开通过在同一显示帧，对于相邻的M/3行，不同行显示时同一选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同可以为避免出现奇偶列亮暗条纹。
示例性地，如图14所示，当M＝6时，在同一显示帧，对于相邻的2行，不同行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同。示例性地，所有奇数行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有偶数行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。
示例性地，当M＝9时，如图16所示，对于相邻的3行，不同行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同。示例性地，所有满足第3r-2行的所有行(第一行、第四行、第七行等)显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有满足第3r-1行的所有行(第二行、第五行、第八行等)显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有满足第3r行的所有行(第三行、第六行、第九行等)显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同。其中，(3r-2)％3＝1，(3r-1)％3＝2，(3r)％3＝0。
示例性地，如图17所示，当M＝12时，对于相邻的4行，不同行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同。所有满足第4r-3行的所有行(第一行、第五行、第九行等)显示时，同一选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有满足第4r-2行的所有行(第二行、第六行、第十行等)显示时，同一选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有满足第4r-1行的所有行(第三行、第七行、第十一行等)显示时，同一选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有满足第4r行的所有行(第四行、第八行、第十二行等)显示时，同一选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序相同，其中，(4r-3)％4＝1，(4r-2)％4＝2，(4r-1)％4＝3，(4r)％4＝0。
在示例性实施方式中，如图14所示，当M＝6时，在每一显示帧，对于相邻的两行，奇数行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序为第三条选择信号线MUX3、第六条选择信号线MUX6、第一条选择信号线MUX1、第四条选择信号线MUX4、第二条选择信号线MUX2、第五条选择信号线MUX5。偶数行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序为第六条选择信号线MUX6、第三条选择信号线MUX3、第四条选择信号线MUX4、第一条选择信号线MUX1、第五条选择信号线MUX5、第二条选择信号线MUX2。在奇数行和偶数行显示时，选择信号线的信号为有效电平信号的发生时间所在的位次不同。示例性地，第一选择信号线MUX1的信号为有效电平信号的发生时间在奇数行显示时所在的位次为第三，在偶数行显示时所在的位次为第四，即在奇数行和偶数行时所在的位次并不相同，同样的其余选择信号线的信号为有效电平信号的发生时间在奇数行和偶数行所在的位次均不相同。
在示例性实施方式中，如图15所示，在每一显示帧，当M＝6时，对于相邻的两行，奇数行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序为第六条选择信号线MUX6、第三条选择信号线MUX3、第四条选择信号线MUX4、第一条选择信号线MUX1、第五条选择信号线MUX5、第二条选择信号线MUX2。偶数行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序为第三条选择信号线MUX3、第六条选择信号线MUX6、第一条选择信号线MUX1、第四条选择信号线MUX4、第二条选择信号线MUX2、第五条选择信号线MUX5，第三选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序为。在奇数行和偶数行显示时，选择信号线的信号为有效电平信号的发生时 间所在的位次不同。示例性地，第一选择信号线MUX1的信号为有效电平信号的发生时间在奇数行显示时所在的位次为第四，在偶数行显示时所在的位次为第三，即在奇数行和偶数行时所在的位次并不相同，同样的其余选择信号线的信号为有效电平信号的发生时间在奇数行和偶数行所在的位次均不相同。
在示例性实施方式中，如图16所示，当M＝9时，在每一显示帧，对于第3r-2行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序为第三条选择信号线MUX3、第六条选择信号线MUX6、第九条选择信号线MUX9、第一条选择信号线MUX1、第四条选择信号线MUX4、第七条选择信号线MUX7、第二条选择信号线MUX2、第五条选择信号线MUX5、第八条选择信号线MUX8。对于第3r-1行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序为第六条选择信号线MUX6、第九条选择信号线MUX9、第三条选择信号线MUX3、第四条选择信号线MUX4、第七条选择信号线MUX7、第一条选择信号线MUX1、第五条选择信号线MUX5、第八条选择信号线MUX8、第二条选择信号线MUX2。对于第3r行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序为第九条选择信号线MUX9、第三条选择信号线MUX3、第六条选择信号线MUX6、第七条选择信号线MUX7、第一条选择信号线MUX1、第四条选择信号线MUX4、第八条选择信号线MUX8、第二条选择信号线MUX2、第五条选择信号线MUX5，第三选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序为。在相邻三行显示时，选择信号线的信号为有效电平的发生时间所在的位次不同，例如，以第一行至第三行为例，第一选择信号线MUX1的信号为有效电平信号的发生时间在第一行显示时所在的位次为第四，在第二行显示时所在的位次为第六，在第三行显示时所在的位次为第五，即在第一行至第三行时所在的位次并不相同，同样的其余选择信号线的信号为有效电平信号的发生时间在相邻三行所在的位次均不相同。
在示例性实施方式中，如图17所示，当M＝12时，在每一显示帧，对于第4r-3行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序可以为第三条选择信号线MUX3、第六条选择信号线MUX6、第九条选择信号线MUX9、第十二条选择信号线MUX12、第一条选择信号线MUX1、第四条选择信号线MUX4、第七条选择信号线MUX7、第十条选择信号线MUX10、第二条选择信号线MUX2、第五条选择信号线MUX5、第八条选择信号线MUX8、第十一条选择信号线MUX11。对于第4r-2行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序可以为第十二条选择信号线MUX12、第九条选择信号线MUX9、第六条选择信号线MUX6、第三条选择信号线MUX3、第十条选择信号线MUX10、第七条选择信号线MUX7、第四条选择信号线MUX4、第一条选择信号线MUX1、第十一条选择信号线MUX11、第八条选择信号线MUX8、第五条选择信号线MUX5、第二条选择信号线MUX2。对于第4r-1行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序可以为第六条选择信号线MUX6、第三条选择信号线MUX3、第十二条选择信号线MUX12、第九条选择信号线MUX9、第四条选择信号线MUX4、第一条选择信号线MUX1、第十条选择信号线MUX10、第七条选择信号线MUX7、第五条选择信号线MUX5、第二条选择信号线MUX2、第十一条选择信号线MUX11、第八条选择信号线MUX8。对于第4r行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序为第九条选择信号线MUX9、第十二条选择信号线MUX12、第三条选择信号线MUX3、第六条选择信号线MUX6、第七条选择信号线MUX7、第十条选择信号线MUX10、第一条选择信号线MUX1、第四条选择信号线MUX4、第八条选择信号线MUX8、第十一条选择信号线MUX11、第二条选择信号线MUX2、第五条选择信号线MUX5。在相邻四行显示时，选择信号线的信号为有效电平的发生时间所在的位次不同，例如，以第一行至第四行为例，第一选择信号线MUX1的信号为有效电平信号的发生时间在第一行显示时所在的位次为第 五，在第二行显示时所在的位次为第八，在第三行显示时所在的位次为第六，在第四行显示时所在的位次为第七，即在第一行至第四行时所在的位次并不相同，同样的其余选择信号线的信号为有效电平信号的发生时间在相邻四行所在的位次均不相同。
示例性地，当M＝6时，所在行数满足z％2＝0的所有行例如第二行、第四行、第六行等偶数行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。所在行数满足z％2＝1的所有行例如第一行、第三行、第五行等奇数行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。示例性地，当M＝9时，所在行数满足z％3＝1的所有行(第一行、第四行、第七行等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所在行数满足z％3＝2的所有行(第二行、第五行、第八行等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有满足z％3＝0的所有行(第三行、第六行、第九行等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。示例性地，当M＝12时，所在行数满足z％4＝1的所有行(第一行、第五行、第九行等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所在行数满足z％4＝2的所有行(第二行、第六行、第十行等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所在行数满足z％4＝3的所有行(第三行、第七行、第十一行等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同，所在行数满足z％4＝0的所有行(第四行、第八行、第十二行等)显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。
在示例性实施方式中，如图14和图15所示，在同一显示帧，对于相邻的M/3行，不同行显示时同一选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同。在相邻的M/3个显示帧，不同显示帧显示时同一选择信号组中的多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同显示帧显示时所在的位次不同。在同一显示帧，所在行数x满足x％(M/3)＝y的多行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同。对于所有显示帧，所在帧数z满足z％(M/3)＝y的多个显示帧同一行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，M/3-1。
示例性地，以M＝6为例，奇数帧中的奇数行显示时，多条选择信号线的信号为有效电平信号的发生顺序依次为第三条选择信号线MUX3、第六条选择信号线MUX6、第一条选择信号线MUX1、第四条选择信号线MUX4、第二条选择信号线MUX2、第五条选择信号线MUX5，奇数帧中的偶数行显示时，多条选择信号线的信号为有效电平信号的发生顺序依次为第六条选择信号线MUX6、第三条选择信号线MUX3、第四条选择信号线MUX4、第一条选择信号线MUX1、第五条选择信号线MUX5，第二条选择信号线MUX2，偶数帧中的偶数行显示时，多条选择信号线的信号为有效电平信号的发生顺序依次为第三条选择信号线MUX3、第六条选择信号线MUX6、第一条选择信号线MUX1、第四条选择信号线MUX4、第二条选择信号线MUX2、第五条选择信号线MUX5，偶数帧中的奇数行显示时，多条选择信号线的信号为有效电平信号的发生顺序依次为第六条选择信号线MUX6、第三条选择信号线MUX3、第四条选择信号线MUX4、第一条选择信号线MUX1、第五条选择信号线MUX5，第二条选择信号线MUX2。图14可以表示显示基板在奇数帧的时序，图15可以表示显示基板在偶数帧的时序。图14和图15是以M＝6为例进行限定的，本公开对此不做任何限定。
示例性地，当M＝6时，所有奇数帧同一行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有偶数帧同一行显示时，多条选择信号线的信号为有效电 平信号的发生时间顺序相同。在同一显示帧，所有奇数行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，所有偶数行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同。
在示例性实施方式中，显示基板可以包括：第一信号线，第一信号线至少包括：扫描信号线，第一信号线与数据信号线异层设置，且在基底上的正投影与数据信号线在基底上的正投影至少部分交叠，位于数据信号线与第一信号线的重叠区域之间的电容为数据信号线的数据寄生电容。
在示例性实施方式中，第一信号线还可以包括：复位信号线和初始信号线中的至少一个。
在示例性实施方式中，对于至少一个复用子电路，与同一颜色子像素电连接的多条数据信号线的数据寄生电容不同。
在示例性实施方式中，对于至少一个复用子电路，当同一颜色子像素电连接的多条数据信号线中的第a条数据信号线所连接的复用晶体管所电连接的选择信号线的信号为有效电平信号的时间早于第b条数据信号线所连接的复用晶体管所连接的选择信号线的信号为有效电平信号的时间时，第a条数据信号线的数据寄生电容大于第b条数据信号线的数据寄生电容。当连接同一颜色子像素的多条数据信号线中的第a条数据信号线所连接的复用晶体管所电连接的选择信号线的信号为有效电平信号的时间早于第b条数据信号线所连接的复用晶体管所连接的选择信号线的信号为有效电平信号的时间时，第a条数据信号线的数据寄生电容大于第b条数据信号线的数据寄生电容可以保证优先写入的数据信号线的数据电压的衰减降低，进一步地，减少与同一选择信号组电连接的多条数据信号线上的保存的数据电压的衰减一致性，可以提升显示基板的显示效果。
在示例性实施方式中，对于至少一个复用子电路，与不同颜色子像素电连接的至少两条数据信号线的数据寄生电容可以不相等。
在示例性实施方式中，对于至少一个复用子电路，与不同颜色子像素电连接的至少两条数据信号线的数据寄生电容相等。
在示例性实施方式中，第3i-2条数据信号线至第3i条数据信号线的数据寄生电容可以相等。
本公开实施例还提供了一种显示装置，包括：显示基板。
在示例性实施方式中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本申请的限制。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
本公开实施例还提供了一种显示基板的驱动方法，用于驱动上述显示基板，所述方法包括：
向多条选择信号线提供信号，使得多个选择信号组中的任意两个选择信号组的有效时间段不交叠。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在阅读并理解了附图和详细描述后，可以明白其他方面。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括：阵列排布的多个子像素、多路复用电路、多条数据信号线，多条选择信号线和多条数据传输线，所述多个子像素包括：多种颜色子像素，所述数据信号线与所述多个子像素电连接；
    所述多路复用电路包括：多个复用晶体管，所述复用晶体管分别与所述数据传输线、所述选择信号线和所述数据信号线电连接，所述复用晶体管被配置为在所述选择信号线的控制下，将所述数据传输线的信号传递给所述数据信号线；
    所述多条选择信号线被划分为多个选择信号组，至少一个选择信号组包括：多条选择信号线，不同选择信号组包括的选择信号线不同，所述选择信号组通过所述复用晶体管和所述数据信号线与所述子像素电连接；
    同一选择信号组电连接的子像素的颜色相同，不同选择信号组电连接的子像素颜色不同，多个选择信号组中的任意两个选择信号组的有效时间段不交叠，其中，所述选择信号组的有效时间段指的是所述选择信号组的选择信号线中信号最早为有效电平信号的开始时间与信号最晚为有效电平信号的结束时间之间的时间段。
  2. 根据权利要求1所述的显示基板，其中，所述子像素包括：第一颜色子像素、第二颜色子像素和第三颜色子像素，第一颜色、第二颜色和第三颜色为不同颜色，且分别为红色、蓝色和绿色中的一种；
    第i条数据信号线与第i列子像素电连接，第3×i-2列子像素为第一颜色子像素，第3×i-1列子像素为第二颜色子像素，第3×i列子像素为第三颜色子像素，其中，1≤i≤N/3，×为乘法运算，/为取商运算，N为数据信号线的数量，N为大于或者等于6的正整数。
  3. 根据权利要求2所述的显示基板，其中，所述多个选择信号组包括：第一选择信号组、第二选择信号组和第三选择信号组；
    所述第一选择信号组电连接的子像素为第一颜色子像素，所述第二选择信号组电连接的子像素为第二颜色子像素，所述第三选择信号组电连接的子像素为第三颜色子像素。
  4. 根据权利要求2或3所述的显示基板，其中，与蓝色子像素电连接的选择信号组的有效时间段早于与红色子像素和绿色子像素电连接的选择信号组的有效时间段。
  5. 根据权利要求4所述的显示基板，其中，所述多路复用电路包括：N/M个复用子电路；
    第j个复用子电路，分别与M条数据信号线、第j条数据传输线和M条选择信号线电连接，M为选择信号线的数量，j＝1，2，.......，N/M，M＝3×S，M为大于或者等于6的正整数，S为大于或者等于2的正整数。
  6. 根据权利要求5所述的显示基板，其中，所述复用晶体管的数量为N个，N个复用晶体管均为N型晶体管或均为P型晶体管；
    第n个复用晶体管的控制极与第l条选择信号线电连接，第n个复用晶体管的第一极与第n条数据信号线电连接，第n个复用晶体管的第二极与第w条数据传输线电连接，％为取余运算，n＝1，2，.......，N；

    第j个复用子电路包括：第M×(j-1)+1个复用晶体管至第M×j个复用晶体管。
  7. 根据权利要求5或6所述的显示基板，还包括：多条扫描信号线，所述多条扫描信号线与所述多个子像素电连接；
    在第m条选择信号线的信号为有效电平信号时，除第m条选择信号线之外的选择信号线的信号均为无效电平信号，m＝1，2，.......，M；
    所述显示基板所显示的内容包括多个显示帧，在至少一个显示帧的第k行子像素显示时，多条选择信号线中的信号最晚为有效电平信号的结束时间早于与第k行子像素电连接的扫描信号线的信号为有效电平信号的开始时间。
  8. 根据权利要求7所述的显示基板，其中，在同一显示帧，同一显示帧中的所有行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同；
    在不同显示帧，同一行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。
  9. 根据权利要求7所述的显示基板，其中，在同一显示帧，对于相邻的M/3行，不同行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同；
    在不同显示帧，同一行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同。
  10. 根据权利要求9所述的显示基板，其中，在同一显示帧，所在行数x满足x％(M/3)＝y的多行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，(M/3)-1。
  11. 根据权利要求7所述的显示基板，其中，在同一显示帧，同一显示帧中的所有行显示时多条选择信号线的信号为有效电平信号的发生时间顺序相同；
    在相邻的M/3个显示帧，不同显示帧显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同显示帧显示时所在的位次不同。
  12. 根据权利要求11所述的显示基板，其中，对于所有显示帧，所在帧数z满足z％(M/3)＝y的多个显示帧显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，(M/3)-1。
  13. 根据权利要求7所述的显示基板，其中，在同一显示帧，对于相邻的M/3行，不同行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同行显示时所在的位次不同；
    在相邻的M/3个显示帧，不同显示帧同一行显示时多条选择信号线的信号为有效电平信号的发生时间顺序不同，且同一选择信号线的信号为有效电平信号的发生时间在不同显示帧的同一行显示时所在的位次不同。
  14. 根据权利要求13所述的显示基板，其中，在同一显示帧，所在行数x满足x％(M/3)＝y的多行显示时，多条选择信号线的信号为有效电平信号的发生时间顺序相同；
    对于所有显示帧，所在帧数z满足z％(M/3)＝y的多个显示帧的同一行显示时，多 条选择信号线的信号为有效电平信号的发生时间顺序相同，y＝0，…，M/3-1。
  15. 根据权利要求7所述的显示基板，包括：第一信号线，所述第一信号线至少包括：扫描信号线，所述第一信号线与数据信号线异层设置，且在基底上的正投影与数据信号线在基底上的正投影至少部分交叠，位于所述数据信号线与所述第一信号线的重叠区域之间的电容为数据信号线的数据寄生电容；
    对于至少一个复用子电路，与同一颜色子像素电连接的多条数据信号线的数据寄生电容不同。
  16. 根据权利要求15所述的显示基板，其中，对于至少一个复用子电路，当与同一颜色子像素电连接的多条数据信号线中的第a条数据信号线所连接的复用晶体管所电连接的选择信号线的信号为有效电平信号的时间早于第b条数据信号线所连接的复用晶体管所连接的选择信号线的信号为有效电平信号的时间时，第a条数据信号线的数据寄生电容大于第b条数据信号线的数据寄生电容。
  17. 根据权利要求16所述的显示基板，其中，对于至少一个复用子电路，与不同颜色子像素电连接的至少两条数据信号线的数据寄生电容相等。
  18. 根据权利要求17所述的显示基板，其中，第3i-2条数据信号线至第3i条数据信号线的数据寄生电容相等。
  19. 一种显示装置，包括：如权利要求1至18任一项所述的显示基板。
  20. 一种显示基板的驱动方法，用于驱动如权利要求1至18任一项所述的显示基板，所述方法包括：
    向多条选择信号线提供信号，使得多个选择信号组中的任意两个选择信号组的有效时间段不交叠。
PCT/CN2023/123236 2022-10-27 2023-10-07 显示基板及其驱动方法、显示装置 WO2024088027A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211329365.XA CN115662331A (zh) 2022-10-27 2022-10-27 显示基板及其驱动方法、显示装置
CN202211329365.X 2022-10-27

Publications (1)

Publication Number Publication Date
WO2024088027A1 true WO2024088027A1 (zh) 2024-05-02

Family

ID=84992845

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/123236 WO2024088027A1 (zh) 2022-10-27 2023-10-07 显示基板及其驱动方法、显示装置

Country Status (2)

Country Link
CN (1) CN115662331A (zh)
WO (1) WO2024088027A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115662331A (zh) * 2022-10-27 2023-01-31 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090070324A (ko) * 2007-12-27 2009-07-01 엘지디스플레이 주식회사 액정표시장치와 그 구동 방법
CN108335675A (zh) * 2017-12-18 2018-07-27 友达光电股份有限公司 显示面板
CN109637414A (zh) * 2018-12-28 2019-04-16 厦门天马微电子有限公司 一种显示面板驱动电路及其驱动方法、显示装置
CN110930938A (zh) * 2019-12-23 2020-03-27 厦门天马微电子有限公司 一种显示面板及显示装置
CN110955091A (zh) * 2019-12-19 2020-04-03 京东方科技集团股份有限公司 一种显示面板及其驱动方法、显示装置
CN112687237A (zh) * 2020-12-28 2021-04-20 上海天马有机发光显示技术有限公司 显示面板及其显示控制方法、显示装置
CN114120925A (zh) * 2021-11-29 2022-03-01 京东方科技集团股份有限公司 源极驱动电路及显示装置
CN115662331A (zh) * 2022-10-27 2023-01-31 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090070324A (ko) * 2007-12-27 2009-07-01 엘지디스플레이 주식회사 액정표시장치와 그 구동 방법
CN108335675A (zh) * 2017-12-18 2018-07-27 友达光电股份有限公司 显示面板
CN109637414A (zh) * 2018-12-28 2019-04-16 厦门天马微电子有限公司 一种显示面板驱动电路及其驱动方法、显示装置
CN110955091A (zh) * 2019-12-19 2020-04-03 京东方科技集团股份有限公司 一种显示面板及其驱动方法、显示装置
CN110930938A (zh) * 2019-12-23 2020-03-27 厦门天马微电子有限公司 一种显示面板及显示装置
CN112687237A (zh) * 2020-12-28 2021-04-20 上海天马有机发光显示技术有限公司 显示面板及其显示控制方法、显示装置
CN114120925A (zh) * 2021-11-29 2022-03-01 京东方科技集团股份有限公司 源极驱动电路及显示装置
CN115662331A (zh) * 2022-10-27 2023-01-31 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置

Also Published As

Publication number Publication date
CN115662331A (zh) 2023-01-31

Similar Documents

Publication Publication Date Title
US11508298B2 (en) Display panel and driving method thereof and display device
US9959801B2 (en) Display device and method for driving same with light-emission enable signal switching unit
US20180374414A1 (en) Display apparatus
US7365714B2 (en) Data driving apparatus and method of driving organic electro luminescence display panel
US8736521B2 (en) Display device and electronic apparatus have the same
JP5453121B2 (ja) 表示装置および表示装置の駆動方法
JP6159965B2 (ja) 表示パネル、表示装置ならびに電子機器
US20040004591A1 (en) Image display apparatus
WO2022237095A1 (zh) 发光控制移位寄存器、栅极驱动电路、显示装置及方法
CN104361862A (zh) 阵列基板及其驱动方法、显示面板、显示装置
CN110010072A (zh) 像素电路及其驱动方法、显示装置
CN102214438A (zh) 显示设备、显示设备的布局方法和电子设备
JP5780650B2 (ja) レベルシフタ回路、走査回路、表示装置、及び、電子機器
WO2020238490A1 (zh) 像素电路、显示基板、显示装置及驱动方法
KR20200013923A (ko) 게이트 구동부 및 이를 이용한 전계발광 표시장치
JP2014029424A (ja) 表示装置および電子機器、ならびに表示パネルの駆動方法
CN108376534A (zh) 像素电路及其驱动方法、显示面板
US20220270530A1 (en) Driving Circuit and Driving Method of Display Panel, Display Panel, and Display Apparatus
KR102612390B1 (ko) 표시 패널 및 표시 장치
WO2024088027A1 (zh) 显示基板及其驱动方法、显示装置
TWI832398B (zh) 顯示面板及包含該顯示面板的顯示裝置
CN207966467U (zh) 像素电路及显示面板
WO2022227485A1 (zh) 像素电路及其驱动方法、显示基板及显示装置
WO2022193359A1 (zh) 一种背光驱动电路及液晶显示装置
KR102554380B1 (ko) 전계발광표시장치