WO2022227485A1 - 像素电路及其驱动方法、显示基板及显示装置 - Google Patents

像素电路及其驱动方法、显示基板及显示装置 Download PDF

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WO2022227485A1
WO2022227485A1 PCT/CN2021/129786 CN2021129786W WO2022227485A1 WO 2022227485 A1 WO2022227485 A1 WO 2022227485A1 CN 2021129786 W CN2021129786 W CN 2021129786W WO 2022227485 A1 WO2022227485 A1 WO 2022227485A1
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Prior art keywords
light
node
emitting
coupled
control
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PCT/CN2021/129786
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English (en)
French (fr)
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梁恒镇
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2022227485A1 publication Critical patent/WO2022227485A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • This article relates to, but is not limited to, the field of display technology, especially a pixel circuit and a driving method thereof, a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display substrate and a display device.
  • an embodiment of the present disclosure provides a pixel circuit for driving a first light-emitting unit and a second light-emitting unit of a sub-pixel to emit light.
  • the pixel circuit includes: an input circuit, a first lighting control circuit and a second lighting control circuit.
  • the input circuit is respectively coupled to the data signal line, the scanning signal line, the first node and the first power supply line, and is configured to write the data signal line to the first node under the control of the scanning signal provided by the scanning signal line to provide the data signal, and store the data signal written to the first node.
  • the first lighting control circuit is respectively coupled to the first node, the second node, the first power supply line and the lighting control signal line, and is configured to provide the first power supply signal, the first node and the first power supply line on the first power supply line. Under the control of the light-emitting control signal provided by the light-emitting control signal line, a driving current is provided to the second node; the second node is coupled to the first pole of the first light-emitting unit.
  • the second lighting control circuit is respectively coupled to the control terminal, the second node and the third node, and is configured to turn on the second node and the third node under the control of the control terminal; the third node is connected to the third node.
  • the first poles of the two light-emitting units are coupled.
  • the second pole of the first light emitting unit and the second pole of the second light emitting unit are both coupled to the second power line.
  • control terminal is coupled to the first node.
  • the input circuit includes: a data writing transistor and a storage capacitor.
  • the control electrode of the data writing transistor is coupled to the scan signal line, the first electrode of the data writing transistor is coupled to the data signal line, and the second electrode of the data writing transistor is coupled to the first node;
  • the first end of the storage capacitor is coupled to the first power line, and the second end of the storage capacitor is coupled to the first node.
  • the first lighting control circuit includes: a driving transistor and a first lighting control transistor.
  • the control electrode of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the first power supply line, and the second electrode of the driving transistor is coupled to the first electrode of the first light-emitting control transistor coupled.
  • the control electrode of the first light-emitting control transistor is coupled to the light-emitting control signal line, and the second electrode of the first light-emitting control transistor is coupled to the second node.
  • the second lighting control circuit includes: a second lighting control transistor.
  • the control electrode of the second light-emitting control transistor is coupled to the control terminal, the first electrode of the second light-emitting control transistor is coupled to the second node, and the second electrode of the second light-emitting control transistor is coupled to the third node Node coupling.
  • the input circuit includes: a data writing transistor and a storage capacitor; the first lighting control circuit includes: a driving transistor and a first lighting control transistor; the second lighting control circuit includes: The second light emission control transistor.
  • the control electrode of the data writing transistor is coupled to the scan signal line, the first electrode of the data writing transistor is coupled to the data signal line, and the second electrode of the data writing transistor is coupled to the first node.
  • the first end of the storage capacitor is coupled to the first power line, and the second end of the storage capacitor is coupled to the first node.
  • the control electrode of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the first power supply line, and the second electrode of the driving transistor is coupled to the first electrode of the first light-emitting control transistor coupled.
  • the control electrode of the first light-emitting control transistor is coupled to the light-emitting control signal line, and the second electrode of the first light-emitting control transistor is coupled to the second node.
  • the control electrode of the second light-emitting control transistor is coupled to the first node, the first electrode of the second light-emitting control transistor is coupled to the second node, and the second electrode of the second light-emitting control transistor is coupled to the third node coupled.
  • an embodiment of the present disclosure provides a method for driving a pixel circuit, which is used for driving the above-mentioned pixel circuit.
  • the driving method includes: when displaying the gray scale of the first range, under the control of the scan signal provided by the scan signal line, the input circuit writes the data signal provided by the data signal line to the first node, and stores and writes the first node.
  • the data signal of the node under the control of the first power signal provided by the first power line, the first node and the light-emitting control signal provided by the light-emitting control signal line, the first light-emitting control circuit provides the driving current to the second node, and controls the Under the control of the terminal, the second lighting control circuit provides a driving current to the third node.
  • the input circuit When displaying the gray scale of the second range, under the control of the scan signal provided by the scan signal line, the input circuit writes the data signal provided by the data signal line to the first node, and stores the data signal written in the first node; Under the control of the first power signal provided by the first power line, the first node, and the light-emitting control signal provided by the light-emitting control signal line, the first light-emitting control circuit provides a driving current to the second node, and under the control of the control terminal, the second The lighting control circuit disconnects the second node and the third node.
  • the grayscale of the first range is greater than the grayscale of the second range.
  • an embodiment of the present disclosure provides a display substrate, including: a plurality of sub-pixels disposed on a substrate. At least one sub-pixel includes the pixel circuit as described above, and a first light-emitting unit and a second light-emitting unit coupled to the pixel circuit.
  • the first light-emitting unit includes: a first anode, a first cathode, and a first organic light-emitting layer disposed between the first anode and the first cathode.
  • the second light-emitting unit includes: a second anode, a second cathode, and a second organic light-emitting layer disposed between the second anode and the second cathode.
  • the first anode and the second anode are isolated from each other, and the first anode and the second anode are coupled to the pixel circuit; the first organic light-emitting layer and the second organic light-emitting layer are isolated from each other, and the first cathode is It is integrated with the second cathode.
  • the first light emitting unit is located on one side of the second light emitting unit.
  • the first light emitting unit surrounds the perimeter of the second light emitting unit.
  • the first light emitting unit includes a first light emitting part and a second light emitting part
  • the second light emitting unit is located between the first light emitting part and the second light emitting part.
  • the at least one subpixel includes at least a green subpixel.
  • an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to at least one embodiment of the disclosure
  • FIG. 2 is another schematic structural diagram of a pixel circuit according to at least one embodiment of the disclosure.
  • FIG. 3 is an equivalent circuit diagram of an input circuit of a pixel circuit according to at least one embodiment of the disclosure
  • FIG. 4 is an equivalent circuit diagram of a first light emission control circuit of a pixel circuit according to at least one embodiment of the disclosure
  • FIG. 5 is an equivalent circuit diagram of a second light emission control circuit of a pixel circuit according to at least one embodiment of the disclosure
  • FIG. 6 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the disclosure.
  • FIG. 7 is a working timing diagram of the pixel circuit provided in FIG. 6;
  • FIG. 8 is a schematic structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 9 is a schematic partial plan structure diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic partial cross-sectional structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of another partial plan structure of the display substrate according to at least one embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of another partial plan structure of the display substrate according to at least one embodiment of the disclosure.
  • FIG. 13 is a schematic diagram of another partial plan structure of the display substrate according to at least one embodiment of the disclosure.
  • FIG. 14 is a schematic diagram of another partial plan structure of the display substrate according to at least one embodiment of the disclosure.
  • 15 is a schematic diagram of another partial plan structure of the display substrate according to at least one embodiment of the disclosure.
  • FIG. 16 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • ordinal numbers such as “first”, “second”, and “third” are provided to avoid confusion of constituent elements, and are not intended to be limited in quantity.
  • a “plurality” in this disclosure means a quantity of two or more.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed e.g., it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region or drain) and a source electrode (source electrode terminal, source region or source), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the gate electrode may be a gate electrode.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • connection and “coupling” include the case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • the OLED light-emitting device includes: a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode.
  • the organic light-emitting layer emits light of corresponding color under the driving of the first pole and the second pole.
  • the film uniformity of the organic light-emitting layer of the light-emitting device of the display substrate and the thin film transistor (TFT) of the pixel circuit will affect the display uniformity. In high-gray-scale display, due to the high brightness of the light-emitting device, it is difficult for the human eye to detect the display difference.
  • the driving current is small, and the film thickness difference between the TFT and the organic light-emitting layer will significantly affect The display effect causes the human eye to observe the uneven display, which makes the picture appear grainy, that is, the low grayscale display is uneven (mura).
  • At least one embodiment of the present disclosure provides a pixel circuit and a driving method thereof, a display substrate and a display device, which can improve the display effect by performing partition display control on sub-pixels.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to at least one embodiment of the disclosure.
  • the pixel circuit of the present exemplary embodiment is used to drive the first light-emitting unit and the second light-emitting unit of the sub-pixel to emit light.
  • the brightness of the sub-pixels is the result of being jointly displayed by the first light-emitting unit and the second light-emitting unit.
  • the light-emitting area of the sub-pixel is divided into two parts: a first light-emitting unit and a second light-emitting unit.
  • the light-emitting area of the sub-pixel is the sum of the light-emitting area of the first light-emitting unit and the light-emitting area of the second light-emitting unit.
  • the light emitting area corresponds to the area of the opening of the pixel definition layer.
  • the pixel circuit includes an input circuit, a first light emission control circuit, and a second light emission control circuit.
  • the input circuit is respectively coupled to the data signal line DL, the scan signal line GL, the first power supply line PL1 and the first node N1, and is configured to write to the first node N1 under the control of the scan signal provided by the scan signal line GL
  • the data signal line DL provides the data signal, and stores the data signal written to the first node N1.
  • the first lighting control circuit is respectively coupled to the first node N1, the second node N2, the first power supply line PL1 and the lighting control signal line EML, and is configured to provide a first power supply signal, a first node on the first power supply line PL1
  • the driving current is supplied to the second node N2 under the control of the light-emitting control signal provided by N1 and the light-emitting control signal line EML.
  • the second node N2 is coupled to the first pole of the first light emitting unit.
  • the second lighting control circuit is respectively coupled to the control terminal CL, the second node N2 and the third node N3, and is configured to turn on the second node N2 and the third node N3 under the control of the control terminal CL.
  • the third node N3 is coupled to the first pole of the second light emitting unit.
  • the second pole of the first light emitting unit and the second pole of the second light emitting unit are both coupled to the second power line PL2.
  • the first node N1 is coupled to the output end of the input circuit and one input end of the first lighting control circuit
  • the second node N2 is coupled to the output of the first lighting control circuit
  • the terminal is coupled to the first pole of the first lighting unit
  • the third node N3 is coupled to the output terminal of the second lighting control circuit and the first pole of the second lighting unit.
  • the first node N1 is equipotential with the output end of the input circuit and an input end of the first light emitting control circuit
  • the second node N2 is equipotential with the output end of the first light emitting control circuit and the first pole of the first light emitting unit
  • the third The node N3 has the same potential as the output terminal of the second light-emitting control circuit and the first pole of the second light-emitting unit.
  • the first node N1, the second node N2, and the third node N3 do not represent actual components, but rather represent the confluence of related circuit connections in the circuit diagram.
  • the first light emitting unit and the second light emitting unit included in one sub-pixel may both be organic light emitting diodes (OLEDs).
  • the first electrode of the first light-emitting unit and the first electrode of the second light-emitting unit may be anodes, and the second electrode of the first light-emitting unit and the second electrode of the second light-emitting unit may be cathodes.
  • the anode of the first light-emitting unit is coupled to the second node N2, the cathode of the first light-emitting unit is coupled to the second power line PL2; the anode of the second light-emitting unit is coupled to the third node N3, and the cathode of the second light-emitting unit is coupled to the second power line PL2.
  • the second power line PL2 is coupled.
  • the cathode of the first light-emitting unit and the cathode of the second light-emitting unit may have an integrated structure. However, this embodiment does not limit this.
  • the first light-emitting unit and the second light-emitting unit included in the sub-pixel may be a quantum dot light-emitting diode (QLED, Quantum Dot Light Emitting Diode), a micro light-emitting diode (Micro-LED, Micro Light Emitting Diode), or a miniature light-emitting diode (QLED). Diode (Mini-LED).
  • QLED quantum dot light-emitting diode
  • Micro-LED Micro Light Emitting Diode
  • QLED miniature light-emitting diode
  • the first power line PL1 may continuously provide a high-level signal, for example, the first power line PL1 may provide the first power signal VDD; the second power line PL2 may continuously provide a low-level signal, for example, The second power supply line PL2 provides the second power supply signal VSS.
  • this embodiment does not limit this.
  • the first light-emitting unit of the sub-pixel is controlled to emit light by the first light-emitting control circuit
  • the second light-emitting unit of the sub-pixel is controlled to emit light by the first light-emitting control circuit and the second light-emitting control circuit.
  • the pixel circuit of this embodiment can respectively drive the first light-emitting unit and the second light-emitting unit of the sub-pixel to emit light through different voltages, so as to realize the sub-pixel driving by partition. Driven by different voltages, the light-emitting areas of the sub-pixels are different. In this way, the light-emitting area of the sub-pixels can be reduced during low-gray-scale display, so as to increase the driving current and improve the display effect at low-gray-scale.
  • FIG. 2 is another schematic structural diagram of a pixel circuit according to at least one embodiment of the disclosure.
  • the pixel circuit includes: an input circuit, a first lighting control circuit and a second lighting control circuit.
  • the control terminal CL is coupled to the first node N1.
  • the second lighting control circuit is respectively coupled to the first node N1, the second node N2 and the third node N3, and is configured to turn on the second node N2 and the third node under the control of the first node N1 N3.
  • the input circuit in the pixel circuit of this exemplary embodiment includes: a data writing transistor M1 and a storage capacitor Cst.
  • the control electrode of the data writing transistor M1 is coupled to the scan signal line GL
  • the first electrode of the data writing transistor M1 is coupled to the data signal line DL
  • the second electrode of the data writing transistor M1 is coupled to the first node N1.
  • the first end of the storage capacitor Cst is coupled to the first power line PL1, and the second end of the storage capacitor Cst is coupled to the first node N1.
  • FIG. 3 shows an exemplary structure of the input circuit, and those skilled in the art can easily understand that the implementation manner of the input circuit is not limited to this, as long as its function can be realized.
  • the first light emission control circuit in the pixel circuit of the present exemplary embodiment includes: a driving transistor M2 and a first light emission control transistor M3.
  • the control electrode of the driving transistor M2 is coupled to the first node N1, the first electrode of the driving transistor M2 is coupled to the first power line PL1, and the second electrode of the driving transistor M2 is coupled to the first electrode of the first light-emitting control transistor M3 .
  • the control electrode of the first light emission control transistor M3 is coupled to the light emission control signal line EML, and the second electrode of the first light emission control transistor M3 is coupled to the second node N2.
  • the second node N2 is coupled to the first pole of the first light emitting unit.
  • FIG. 4 shows an exemplary structure of the first lighting control circuit. Those skilled in the art can easily understand that the implementation of the first lighting control circuit is not limited to this, as long as its function can be realized.
  • FIG. 5 is an equivalent circuit diagram of a second light emission control circuit of a pixel circuit according to at least one embodiment of the disclosure.
  • the second light emission control circuit in the pixel circuit of the present exemplary embodiment includes: a second light emission control transistor M4 .
  • the control electrode of the second light-emitting control transistor M4 is coupled to the first node N1, the first electrode of the second light-emitting control transistor M4 is coupled to the second node N2, and the second electrode of the second light-emitting control transistor M4 is coupled to the third node N3 coupled.
  • the third node N3 is coupled to the first pole of the second light emitting unit.
  • FIG. 5 shows an exemplary structure of the second lighting control circuit. Those skilled in the art can easily understand that the implementation of the second lighting control circuit is not limited to this, as long as its function can be achieved.
  • FIG. 6 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the disclosure.
  • the input circuit includes: a data writing transistor M1 and a storage capacitor Cst;
  • the first light emission control circuit includes: a driving transistor M2 and a third A light-emitting control transistor M3;
  • the second light-emitting control circuit includes: a second light-emitting control transistor M4.
  • the control electrode of the data writing transistor M1 is coupled to the scan signal line GL
  • the first electrode of the data writing transistor M1 is coupled to the data signal line DL
  • the data writing The second pole of the transistor M1 is coupled to the first node N1.
  • the first end of the storage capacitor Cst is coupled to the first power line PL1, and the second end of the storage capacitor Cst is coupled to the first node N1.
  • the control electrode of the driving transistor M2 is coupled to the first node N1, the first electrode of the driving transistor M2 is coupled to the first power line PL1, and the second electrode of the driving transistor M2 is coupled to the first electrode of the first light-emitting control transistor M3 .
  • the control electrode of the first light emission control transistor M3 is coupled to the light emission control signal line EML, and the second electrode of the first light emission control transistor M3 is coupled to the second node N2.
  • the control electrode of the second light-emitting control transistor M4 is coupled to the first node N1, the first electrode of the second light-emitting control transistor M4 is coupled to the second node N2, and the second electrode of the second light-emitting control transistor M4 is coupled to the third node N3 coupled.
  • the first pole of the first light emitting unit EL1 is coupled to the second node N2, and the second pole of the first light emitting unit EL1 is coupled to the second power line PL2.
  • the first pole of the second light emitting unit EL2 is coupled to the third node N3, and the second pole of the second light emitting unit EL2 is coupled to the second power line PL2.
  • the data writing transistor M1 , the driving transistor M2 , the first light-emitting control transistor M3 and the second light-emitting control transistor M4 in the pixel circuit provided in FIG. 6 are all P-type thin film transistors for description.
  • the P-type transistor is turned on when the control level is extremely low, and turned off when the control level is extremely high.
  • the plurality of transistors in this embodiment can also be N-type transistors.
  • the N-type transistor is turned on when the control level is extremely high, and turned off when the control level is extremely low.
  • Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.
  • the embodiments of the present disclosure are not limited thereto.
  • some of the transistors in this embodiment are P-type transistors, and another part of the transistors are N-type transistors.
  • the data writing transistor M1, the driving transistor M2, the first light emission control transistor M3 and the second light emission control transistor M4 in the pixel circuit may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, Alternatively, low temperature polysilicon thin film transistors and oxide thin film transistors may be used.
  • the active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor adopts oxide (Oxide).
  • LTPS low Temperature Poly-Silicon
  • oxide thin film transistor adopts oxide (Oxide).
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • a low temperature polycrystalline silicon thin film transistor and an oxide thin film transistor can be integrated on one display substrate to form a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display substrate, and the advantages of both can be utilized, It can achieve high resolution (PPI, Pixel Per Inch), low frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 7 is an operation timing diagram of the pixel circuit provided in FIG. 6 .
  • the pixel circuit involved in this embodiment includes: 4 transistors (ie, a data writing transistor M1, a driving transistor M2, a first light-emitting control transistor M3 and a second light-emitting control transistor M4), and a capacitor unit (ie storage capacitor Cst), 3 signal input terminals (ie scan signal line GL, data signal line DL and light emission control signal line EML), 2 power supply terminals (ie first power line PL1 and second power line PL2).
  • the first power line PL1 continuously provides a high-level signal, such as the first power signal VDD;
  • the second power line PL2 continuously provides a low-level signal, such as the second power signal VSS.
  • the pixel circuit may include the following operating states: a data writing phase and a light emitting phase.
  • the first stage S1 that is, the data writing stage, as shown in FIG. 7 , the scanning signal SCAN provided by the scanning signal line GL is at a low level, the data writing transistor M1 is turned on, and the light-emitting control signal EM provided by the light-emitting control signal line EML At a high level, the first light-emitting control transistor M3 is turned off.
  • the data writing transistor M1 is turned on to charge the storage capacitor Cst to store the data signal DATA provided by the data signal line DL in the storage capacitor Cst.
  • the data signal DATA stored in the storage capacitor Cst can control the degree of conduction of the driving transistor M2.
  • the second stage S2 is the light-emitting stage. As shown in FIG. 7 , the scanning signal SCAN provided by the scanning signal line GL is at a high level, the data writing transistor M1 is turned off, and the light-emitting control signal EM provided by the light-emitting control signal line EML is low. level, the first light-emitting control transistor M3 is turned on.
  • the driving current provided by the driving transistor M2 flows into the first light-emitting unit EL1 through the first light-emitting control transistor M3, so that the first light-emitting unit EL1 emits light , and flows into the second light-emitting unit EL2 through the first light-emitting control transistor M3 and the second light-emitting control transistor M4 at the same time, so that the second light-emitting unit EL2 emits light.
  • the driving current provided by the driving transistor M2 flows into the first light-emitting unit EL1 through the first light-emitting control transistor M3, so that the first light-emitting unit EL1 emits light; the second light-emitting control transistor M4 Off, the second light emitting unit EL2 is turned off.
  • the threshold voltages of the driving transistor M2 and the second light emission control transistor M4 are the same.
  • the turn-on voltage of the driving transistor M2 depends on (V N1 -VDD), and the turn-on voltage of the second light emission control transistor M4 depends on [V N1 -(VDD-Vth (M2) -Vth (M3) )].
  • V N1 represents the voltage of the first node N1
  • VDD is the first power supply signal provided by the first power line PL1
  • Vth (M2) is the threshold voltage of the driving transistor M2
  • Vth (M3) is the first light-emitting control transistor M3. threshold voltage.
  • the driving transistor M2 when V N1 -VDD>0V, the driving transistor M2 is turned off, and when V N1 -VDD ⁇ 0V, the driving transistor M2 is turned on.
  • V N1 -VDD when (V N1 -VDD) is a positive value, the driving transistor M2 is completely turned off; when (V N1 -VDD) is a negative value and the absolute value is larger, the driving current provided by the driving transistor M2 is larger, so that the sub-pixel the higher the brightness.
  • the threshold voltage Vth is about 0.2V to 0.3V. Since [V N1 -(VDD-Vth (M2) -Vth (M3) )] is greater than (V N1 -VDD), the driving transistor M2 is turned on when the second light emission control transistor M4 is turned off. For example, in the light-emitting stage S2, when the voltage of the first node N1 is greater than (VDD-Vth (M2) -Vth (M3) ) and less than VDD, the second light-emitting control transistor M4 is turned off, and the driving transistor M2 is turned on, then the first The light emitting unit EL1 continues to emit light, while the second light emitting unit EL2 is turned off and stops emitting light.
  • the light-emitting area of the sub-pixel is reduced to the light-emitting area of the first light-emitting unit EL1, and the driving current of the first light-emitting unit EL1 is increased, thereby increasing the brightness of the first light-emitting unit EL1.
  • a single light-emitting area of a sub-pixel is divided into two light-emitting areas (corresponding to the area where the first light-emitting unit is located and the area where the second light-emitting unit is located), and different voltages are used to drive the two light-emitting areas, so that the different voltages Under driving, the light-emitting areas of the sub-pixels are different.
  • the light-emitting area of the sub-pixel can be reduced, the driving current of the first light-emitting unit can be increased, and the brightness of the sub-pixel can be improved.
  • the brightness of the partial light-emitting area of the sub-pixel is greater than that of the entire light-emitting area of the sub-pixel, which is beneficial to reduce the brightness difference between sub-pixels at low gray levels and improve the display at low gray levels. Effect.
  • the brightness of the gray scale is displayed according to the set requirements, the set data voltage is obtained through gamma debugging, and the required driving current is obtained through the pixel circuit.
  • the red (R) sub-pixel when the driving voltage of the red sub-pixel is about 6.3V, the red sub-pixel corresponds to displaying one gray scale.
  • the red sub-pixel including a first light-emitting unit and a second light-emitting unit, and the threshold voltage of the transistor is about 0.3V as an example
  • the second light-emitting unit is turned off when the driving voltage is about 5.7V, and the red sub-pixel can display 11 gray at this time. order.
  • the second light-emitting unit By turning off the second light-emitting unit, the light-emitting area of the sub-pixel is reduced, and the driving current of the first light-emitting unit is increased, thereby increasing the brightness of the sub-pixel and improving the display effect under low gray scale.
  • At least one embodiment of the present disclosure further provides a method for driving a pixel circuit, which is used for driving the above-mentioned pixel circuit.
  • the driving method of this embodiment includes: when displaying the gray scale of the first range, under the control of the scan signal provided by the scan signal line, the input circuit writes the data signal provided by the data signal line to the first node, and stores the written data signal.
  • the data signal of the first node; under the control of the first power signal provided by the first power line, the first node and the light-emitting control signal provided by the light-emitting control signal line, the first light-emitting control circuit provides a driving current to the second node, and Under the control of the control terminal, the second lighting control circuit provides a driving current to the third node.
  • the input circuit When displaying the gray scale of the second range, under the control of the scan signal provided by the scan signal line, the input circuit writes the data signal provided by the data signal line to the first node, and stores the data signal written in the first node; Under the control of the first power signal provided by the first power line, the first node, and the light-emitting control signal provided by the light-emitting control signal line, the first light-emitting control circuit provides a driving current to the second node, and under the control of the control terminal, the second The lighting control circuit disconnects the second node and the third node.
  • the gray level of the first range is greater than the gray level of the second range.
  • both the first light-emitting unit and the second light-emitting unit emit light when displaying the gray scale of the first range, and the first light-emitting unit emits light and the second light-emitting unit does not emit light when the gray scale of the second range is displayed.
  • the first range is a high grayscale range and the second range is a low grayscale range.
  • the first range may be greater than 32 grayscales, and the second range may be less than or equal to 32 grayscales.
  • this embodiment does not limit this.
  • control method of the pixel circuit provided in this embodiment is used in the pixel circuit provided by the foregoing embodiment, and the implementation principle and effect thereof are similar, so they are not repeated here.
  • At least one embodiment of the present disclosure further provides a display substrate, including: a plurality of sub-pixels disposed on a substrate. At least one sub-pixel includes the pixel circuit as described in the previous embodiments, and a first light-emitting unit and a second light-emitting unit coupled to the pixel circuit. Regarding the structure of the pixel circuit, reference may be made to the descriptions of the foregoing embodiments, and thus will not be repeated here.
  • the first light emitting unit includes a first anode, a first cathode, and a first organic light emitting layer disposed between the first anode and the first cathode.
  • the second light-emitting unit includes: a second anode, a second cathode, and a second organic light-emitting layer disposed between the second anode and the second cathode.
  • the first anode and the second anode are isolated from each other, and the first anode and the second anode are coupled to the pixel circuit.
  • the first organic light-emitting layer and the second organic light-emitting layer are isolated from each other, and the first cathode and the second cathode have an integrated structure.
  • the first light-emitting unit and the second light-emitting unit of the sub-pixel are driven by different voltages by using the pixel circuit.
  • the first light emitting unit is located on one side of the second light emitting unit.
  • the light-emitting area of the sub-pixel is divided into symmetrical first light-emitting units and second light-emitting units.
  • the ratio of the light emitting areas of the first light emitting unit and the second light emitting unit may be about 1:1. However, this embodiment does not limit this.
  • the first light emitting unit surrounds the perimeter of the second light emitting unit.
  • the light-emitting areas of the sub-pixels are divided in a center and peripheral manner.
  • the ratio of the light emitting areas of the first light emitting unit and the second light emitting unit may be about 2:1. However, this embodiment does not limit this.
  • the first light emitting unit surrounds the perimeter of the second light emitting unit.
  • the first light emitting unit includes a first light emitting part and a second light emitting part, and the second light emitting unit is located between the first light emitting part and the second light emitting part.
  • the first light emitting part and the second light emitting part may be coupled and coupled with the pixel circuit.
  • the at least one subpixel includes at least a green subpixel.
  • the light-emitting regions of the green sub-pixels on the display substrate may be partitioned, or the light-emitting regions of both the green sub-pixels and the red sub-pixels (or blue sub-pixels) on the display substrate may be partitioned, or, The light-emitting regions of all sub-pixels on the display substrate are partitioned.
  • this embodiment does not limit this.
  • the structure of the display substrate of the present embodiment will be illustrated below through some examples.
  • FIG. 8 is a schematic structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • the display substrate may include an array of pixels.
  • the pixel array is connected with the data signal driver, the scanning signal driver and the light emitting signal driver, and the data signal driver, the scanning signal driver and the light emitting signal driver are connected with the timing controller.
  • the pixel array may include a plurality of scan signal lines (eg, S1 to Sm), a plurality of data signal lines (eg, D1 to Dn), a plurality of light emission control signal lines (eg, E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller may provide grayscale values and control signals suitable for the specifications of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver to the data signal driver
  • the scan signal driver can supply the light-emitting signal driver with a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting signal driver.
  • the data signal driver may generate data signals to be supplied to the data signal lines D1 , D2 , D3 , . . . and Dn using the grayscale values and control signals received from the timing controller.
  • the data signal driver may sample grayscale values with a clock signal and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in pixel row units, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1 , S2 , S3 , . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver may be constructed in the form of a shift register, and may generate scans in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal signal, m can be a natural number.
  • the light emission signal driver may generate emission signals to be supplied to the light emission control signal lines E1 , E2 , E3 , . . . and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the emission signal driver may sequentially supply emission signals having off-level pulses to the emission control signal lines E1 to Eo.
  • the light-emitting signal driver may be constructed in the form of a shift register, and may generate the light-emitting signal in such a manner that a light-emitting stop signal provided in the form of an off-level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, o can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line and a corresponding light emission control signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.
  • FIG. 9 is a schematic partial plan structure diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, and a first sub-pixel P2 that emits light of a third color Three sub-pixels P3.
  • the first sub-pixel P1 may include a first pixel circuit, a first light-emitting unit P11 and a second light-emitting unit P12
  • the second sub-pixel P2 may include a second pixel circuit and a second light-emitting element
  • the third sub-pixel P3 may include a third pixel circuit and a third light emitting element.
  • the first pixel circuit may be the pixel circuit shown in FIG. 6 , and outputs a driving current to the first light-emitting unit P11 and the second light-emitting unit P12 .
  • the second pixel circuit may be a pixel circuit with a 3T1C structure, which is respectively coupled to the scanning signal line, the data signal line and the light-emitting control signal line, and is configured to receive the data transmitted by the data signal line under the control of the scanning signal line and the light-emitting control signal line.
  • the data signal outputs the corresponding driving current to the second light-emitting element.
  • the second light emitting element is configured to emit light of corresponding brightness in response to the driving current output by the second pixel circuit.
  • the third pixel circuit may be a pixel circuit with a 3T1C structure, and outputs a corresponding driving current to the third light-emitting element, and the third light-emitting element is configured to emit light with corresponding brightness in response to the driving current output by the third pixel circuit.
  • this embodiment does not limit this.
  • the second pixel circuit and the third pixel circuit may include other numbers of transistors and capacitors.
  • the first color light may be green light
  • the second color light may be blue light
  • the third color light may be red light.
  • Different color sub-pixels have different luminous efficiencies.
  • the luminous efficiency of the blue sub-pixel is lower than that of the red sub-pixel
  • the luminous efficiency of the red sub-pixel is lower than that of the green sub-pixel. Since the green sub-pixel has the highest light-emitting efficiency and low current, in this example, only the first sub-pixel P1 (ie, the green sub-pixel) can be partitioned to form two light-emitting units (ie, the first light-emitting unit P11 and the second light-emitting unit P11).
  • the two light-emitting units P12) are driven by the pixel circuits provided by the above embodiments through different voltages, so as to improve the display effect under low gray scale.
  • this embodiment does not limit this.
  • a repeating unit in the pixel array includes: two first sub-pixels P1 arranged in the second direction D2, The second subpixel P2 and the third subpixel P3 on both sides in the first direction D1.
  • the first sub-pixel P1 (for example, the green sub-pixel) and the third sub-pixel P3 (for example, the red sub-pixel) in one repeating unit constitute one pixel unit, and use the second sub-pixel in another repeating unit adjacent to it.
  • Pixel P2 (eg, the blue sub-pixel) constitutes a dummy pixel for display.
  • the second sub-pixel P2 (for example, the blue sub-pixel) and the other first sub-pixel P1 (for example, the green sub-pixel) in the repeating unit constitute one pixel, and the first sub-pixel in another repeating unit adjacent to it is borrowed.
  • Three sub-pixels (eg, red sub-pixels) constitute a dummy pixel for display.
  • the second subpixels P2 and the third subpixels P3 are arranged at intervals
  • the third direction D3 the second subpixels P2 and the first subpixels P1 are arranged at intervals.
  • the first direction D1 is perpendicular to the second direction D2, and the third direction D3 intersects both the first direction D1 and the second direction D2.
  • this embodiment does not limit this.
  • one pixel unit includes three sub-pixels (for example, red sub-pixels, green sub-pixels and blue sub-pixels), and the three sub-pixels can be arranged in a horizontal parallel and vertical parallel manner;
  • one pixel unit includes four sub-pixels (for example, red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels), the four sub-pixels can be arranged horizontally, vertically or squarely.
  • the shapes of the second subpixel P2 and the third subpixel P3 may be rectangular.
  • the first light emitting unit P11 and the second light emitting unit P12 of the first sub-pixel P1 may have a rectangular shape.
  • this embodiment does not limit this.
  • the second sub-pixel, the third sub-pixel, the first light emitting unit and the second light emitting unit may have other shapes, such as a rhombus, a pentagon or a hexagon.
  • the first light emitting unit P11 and the second light emitting unit P12 of the first subpixel P1 are symmetrical to each other about an axis parallel to the third direction D3.
  • the ratio of the light emitting areas of the first light emitting unit P11 and the second light emitting unit P12 may be about 1:1.
  • the light emitting area of the first light emitting unit P11 and the second light emitting unit P12 may refer to the area of the light emitting area exposed by the opening of the pixel definition layer.
  • this embodiment does not limit this.
  • the ratio of the light-emitting areas of the first light-emitting unit and the second light-emitting unit the current increasing speed of the first light-emitting unit can be adjusted.
  • FIG. 10 is a schematic partial cross-sectional structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 10 is a schematic partial cross-sectional view along the Q-Q direction in FIG. 9 , which only illustrates a partial cross-sectional structure of the first sub-pixel P1 of the display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on the substrate 100 , a driving circuit layer 102 disposed on a side of the driving circuit layer 102 away from the substrate 100 .
  • the light-emitting structure layer 103 and the encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 100 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • substrate 100 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit, and the driving circuit layer 102 in FIG. 10 only shows the first transistor 210, the second transistor 211 and one storage capacitor 212 as an example.
  • the first transistor 210 may be the first light-emitting control transistor M3 in the pixel circuit shown in FIG. 6
  • the second transistor 211 may be the second light-emitting control transistor M4 in the pixel circuit shown in FIG. 6
  • the storage capacitor 212 may be is the storage capacitor Cst in the pixel circuit shown in FIG. 6 .
  • the light emitting structure layer 103 may at least include: a pixel definition layer 304, a first light emitting unit and a second light emitting unit.
  • the first light-emitting unit includes: a first anode 301a , a first organic light-emitting layer 302a and a cathode 303 .
  • the first anode 301a is connected to the drain electrode of the first transistor 210 through a via hole
  • the first organic light-emitting layer 303a is connected to the first anode 301a
  • the cathode 303 is connected to the first organic light-emitting layer 303a
  • the first organic light-emitting layer 303a is in the first organic light-emitting layer 303a.
  • the anode 301a and the cathode 303 are driven to emit light of the first color.
  • the second light-emitting unit includes: a second anode 301b , a second organic light-emitting layer 302b and a cathode 303 .
  • the second anode 301b is connected to the drain electrode of the second transistor 211 through a via hole
  • the second organic light-emitting layer 303b is connected to the second anode 301b
  • the cathode 303 is connected to the second organic light-emitting layer 303b
  • the second organic light-emitting layer 303b is in the second
  • the anode 301b and the cathode 303 are driven to emit light of the first color.
  • both the first light emitting unit and the second light emitting unit emit green light.
  • the light-emitting regions of the first light-emitting unit and the second light-emitting unit are regions corresponding to the openings of the pixel definition layer 304 .
  • the light-emitting structure layer 103 may further include: a second light-emitting element of the second sub-pixel P2 and a third light-emitting element of the third sub-pixel P3.
  • the second light-emitting element may include a first electrode, a second electrode and an organic light-emitting layer disposed between the first electrode and the second electrode, the first electrode of the second light-emitting element is coupled to the second pixel circuit;
  • the third light-emitting element It may include a first pole, a second pole and an organic light emitting layer disposed between the first pole and the second pole, and the first pole of the third light emitting element is coupled to the third pixel circuit.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401 , a second encapsulation layer 402 and a third encapsulation layer 403 , the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 401 may be made of inorganic materials.
  • the layer 402 can be made of organic material, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer may include a stacked hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), an electron blocking layer (EBL, Electron Block Layer), a light-emitting layer (EML, Emitting Layer), hole blocking layer (HBL, Hole Block Layer), electron transport layer (ETL, Electron Transport Layer) and electron injection layer (EIL, Electron Injection Layer).
  • HIL Hole Injection Layer
  • HTL Hole Injection Layer
  • HTL Hole Transport Layer
  • EBL Electron Block Layer
  • EML Emitting Layer
  • hole blocking layer HBL, Hole Block Layer
  • ETL Electron Transport Layer
  • EIL Electron Injection Layer
  • the first organic light emitting layer of the first light emitting unit and the second organic light emitting layer of the second light emitting unit are isolated from each other. However, this embodiment does not limit this.
  • the hole injection layers of all subpixels may be a common layer connected together
  • the electron injection layers of all subpixels may be a common layer connected together
  • the hole transport layers of all subpixels may be A common layer connected together
  • the electron transport layer of all subpixels can be a common layer connected together
  • the hole blocking layer of all subpixels can be a common layer connected together
  • the light emitting layers of adjacent subpixels can have a small amount of The electron blocking layers of adjacent sub-pixels may overlap slightly, or may be isolated.
  • the light-emitting area of the green sub-pixel is divided into two half-areas (that is, the light-emitting area corresponding to the first light-emitting unit and the light-emitting area corresponding to the second light-emitting unit), and the above embodiment is used.
  • the provided pixel circuit uses different voltages to drive the two half regions of the green sub-pixel, so that the light-emitting area of the green sub-pixel can be reduced under low gray scale, the display brightness can be increased, and the display effect under low gray scale can be improved.
  • FIG. 11 is another partial schematic plan view of the display substrate according to at least one embodiment of the disclosure.
  • the first sub-pixel P1 that emits light of the first color includes a first pixel circuit, a first light-emitting unit P11 and a second light-emitting unit P12.
  • the first light emitting unit P11 surrounds the second light emitting unit P12.
  • the ratio of the light emitting areas of the first light emitting unit P11 to the second light emitting unit P12 is about 2:1.
  • the second light-emitting unit P12 may be rectangular, and the first light-emitting unit P11 may be annular surrounding the second light-emitting unit P12 and having a gap.
  • a fine metal mask FMM, Fine Metal Mask
  • this embodiment does not limit this.
  • FIG. 12 is another partial schematic plan view of the display substrate according to at least one embodiment of the disclosure.
  • the first sub-pixel P1 that emits light of the first color includes a first pixel circuit, a first light-emitting unit P11 and a second light-emitting unit P12.
  • the first light emitting unit P11 surrounds the second light emitting unit P12.
  • the ratio of the light emitting areas of the first light emitting unit P11 to the second light emitting unit P12 is about 2:1.
  • the second light emitting unit P12 may have a rectangular shape.
  • the first light emitting unit P11 has a first light emitting part P11a and a second light emitting part P11b connected to each other.
  • the organic light emitting layers of the first light emitting part P11a and the second light emitting part P11b may communicate.
  • the first light emitting part P11a and the second light emitting part P11b may be symmetrical to each other about an axis parallel to the first direction D1.
  • this embodiment does not limit this.
  • by dividing the first light-emitting unit into two symmetrical parts the uniformity of display brightness of the first sub-pixel can be improved when the second light-emitting unit is turned off.
  • FIG. 13 is another partial schematic plan view of the display substrate according to at least one embodiment of the disclosure.
  • the first sub-pixel P1 that emits light of the first color the second sub-pixel P2 that emits light of the second color, and the third sub-pixel P3 that emits light of the third color are each It includes a pixel circuit, and a first light-emitting unit and a second light-emitting unit connected to the pixel circuit.
  • a pixel circuit reference may be made to the description of the pixel circuit provided in the foregoing embodiments.
  • the description of the first light-emitting unit and the second light-emitting unit reference may be made to the related description shown in FIG. 9 , so it will not be repeated here.
  • the structures (or methods) shown in this embodiment mode can be appropriately combined with the structures (or methods) shown in other embodiments.
  • FIG. 14 is another partial schematic plan view of the display substrate according to at least one embodiment of the disclosure.
  • each of the first sub-pixel P1 that emits light of the first color, the second sub-pixel P2 that emits light of the second color, and the third sub-pixel P3 that emits light of the third color It includes a pixel circuit, and a first light-emitting unit and a second light-emitting unit connected to the pixel circuit.
  • pixel circuit For the structure of the pixel circuit, reference may be made to the description of the pixel circuit provided in the foregoing embodiments.
  • the description of the first light-emitting unit and the second light-emitting unit reference may be made to the related description shown in FIG. 11 , and thus will not be repeated here.
  • the structures (or methods) shown in this embodiment mode can be appropriately combined with the structures (or methods) shown in other embodiments.
  • FIG. 15 is another partial schematic plan view of the display substrate according to at least one embodiment of the disclosure.
  • each of the first sub-pixel P1 that emits light of the first color, the second sub-pixel P2 that emits light of the second color, and the third sub-pixel P3 that emits light of the third color It includes a pixel circuit, and a first light-emitting unit and a second light-emitting unit connected to the pixel circuit.
  • pixel circuit For the structure of the pixel circuit, reference may be made to the description of the pixel circuit provided in the foregoing embodiments.
  • the description of the first light-emitting unit and the second light-emitting unit reference may be made to the related description shown in FIG. 12 , and thus will not be repeated here.
  • the structures (or methods) shown in this embodiment mode can be appropriately combined with the structures (or methods) shown in other embodiments.
  • each sub-pixel is divided into two light-emitting units, and different voltages are provided through the pixel circuit for driving, so as to reduce the light-emitting area of the sub-pixel under low gray scale, thereby Improve the display brightness of sub-pixels and improve the display effect under low gray scale.
  • FIG. 16 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • this embodiment provides a display device 91 including the display substrate 910 of the previous embodiment.
  • the display substrate 910 may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device 91 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator. However, this embodiment does not limit this.

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Abstract

一种像素电路，用于驱动子像素的第一发光单元和第二发光单元发光，像素电路包括：输入电路、第一发光控制电路和第二发光控制电路，输入电路配置为在扫描信号线（GL）提供的扫描信号的控制下，向第一节点（N1）写入数据信号线（DL）提供的数据信号，并存储写入第一节点（N1）的数据信号，第一发光控制电路配置为在第一电源线（PL1）提供的第一电源信号、第一节点（N1）以及发光控制信号线（EML）提供的发光控制信号的控制下，向第二节点（N2）提供驱动电流，第二发光控制电路，配置为在控制端（CL）的控制下，导通第二节点（N2）和第三节点（N3），第二节点（N2）与第一发光单元的第一极耦接，第三节点（N3）与第二发光单元的第一极耦接。

Description

像素电路及其驱动方法、显示基板及显示装置
本申请要求于2021年4月29日提交中国专利局、申请号为202110476792.X、发明名称为“像素电路及其驱动方法、显示基板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种像素电路及其驱动方法、显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(TFT，Thin Film Transistor)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种像素电路及其驱动方法、显示基板及显示装置。
一方面，本公开实施例提供一种像素电路，用于驱动子像素的第一发光单元和第二发光单元发光。所述像素电路包括：输入电路、第一发光控制电路和第二发光控制电路。所述输入电路，分别与数据信号线、扫描信号线、第一节点和第一电源线耦接，配置为在扫描信号线提供的扫描信号的控制下，向第一节点写入数据信号线提供的数据信号，并存储写入所述第一节点的数据信号。所述第一发光控制电路，分别与第一节点、第二节点、第一电源线和发光控制信号线耦接，配置为在所述第一电源线提供的第一电源信号、第一节点以及发光控制信号线提供的发光控制信号的控制下，向第二节点提供 驱动电流；所述第二节点与第一发光单元的第一极耦接。所述第二发光控制电路，分别与控制端、第二节点和第三节点耦接，配置为在所述控制端的控制下，导通第二节点和第三节点；所述第三节点与第二发光单元的第一极耦接。所述第一发光单元的第二极和第二发光单元的第二极均与第二电源线耦接。
在一些示例性实施方式中，所述控制端与所述第一节点耦接。
在一些示例性实施方式中，所述输入电路包括：数据写入晶体管和存储电容。所述数据写入晶体管的控制极与扫描信号线耦接，所述数据写入晶体管的第一极与数据信号线耦接，所述数据写入晶体管的第二极与第一节点耦接；所述存储电容的第一端与第一电源线耦接，所述存储电容的第二端与第一节点耦接。
在一些示例性实施方式中，所述第一发光控制电路包括：驱动晶体管和第一发光控制晶体管。所述驱动晶体管的控制极与第一节点耦接，所述驱动晶体管的第一极与第一电源线耦接，所述驱动晶体管的第二极与所述第一发光控制晶体管的第一极耦接。所述第一发光控制晶体管的控制极与发光控制信号线耦接，所述第一发光控制晶体管的第二极与第二节点耦接。
在一些示例性实施方式中，所述第二发光控制电路，包括：第二发光控制晶体管。所述第二发光控制晶体管的控制极与所述控制端耦接，所述第二发光控制晶体管的第一极与第二节点耦接，所述第二发光控制晶体管的第二极与第三节点耦接。
在一些示例性实施方式中，所述输入电路包括：数据写入晶体管和存储电容；所述第一发光控制电路包括：驱动晶体管和第一发光控制晶体管；所述第二发光控制电路，包括：第二发光控制晶体管。所述数据写入晶体管的控制极与扫描信号线耦接，所述数据写入晶体管的第一极与数据信号线耦接，所述数据写入晶体管的第二极与第一节点耦接。所述存储电容的第一端与第一电源线耦接，所述存储电容的第二端与第一节点耦接。所述驱动晶体管的控制极与第一节点耦接，所述驱动晶体管的第一极与第一电源线耦接，所述驱动晶体管的第二极与所述第一发光控制晶体管的第一极耦接。所述第一发光控制晶体管的控制极与发光控制信号线耦接，所述第一发光控制晶体管的 第二极与第二节点耦接。所述第二发光控制晶体管的控制极与第一节点耦接，所述第二发光控制晶体管的第一极与第二节点耦接，所述第二发光控制晶体管的第二极与第三节点耦接。
另一方面，本公开实施例提供一种像素电路的驱动方法，用于驱动如上所述的像素电路。所述驱动方法包括：在显示第一范围的灰阶时，在扫描信号线提供的扫描信号的控制下，输入电路向第一节点写入数据信号线提供的数据信号，并存储写入第一节点的数据信号；在第一电源线提供的第一电源信号、第一节点以及发光控制信号线提供的发光控制信号的控制下，第一发光控制电路向第二节点提供驱动电流，并在控制端的控制下，第二发光控制电路向第三节点提供驱动电流。在显示第二范围的灰阶时，在扫描信号线提供的扫描信号的控制下，输入电路向第一节点写入数据信号线提供的数据信号，并存储写入第一节点的数据信号；在第一电源线提供的第一电源信号、第一节点以及发光控制信号线提供的发光控制信号的控制下，第一发光控制电路向第二节点提供驱动电流，并在控制端的控制下，第二发光控制电路使第二节点和第三节点断开。其中，所述第一范围的灰阶大于第二范围的灰阶。
另一方面，本公开实施例提供一种显示基板，包括：设置在基底上的多个子像素。至少一个子像素包括：如上所述的像素电路、以及与所述像素电路耦接的第一发光单元和第二发光单元。
在一些示例性实施方式中，所述第一发光单元包括：第一阳极、第一阴极以及设置在所述第一阳极和第一阴极之间的第一有机发光层。所述第二发光单元包括：第二阳极、第二阴极以及设置在所述第二阳极和第二阴极之间的第二有机发光层。所述第一阳极和第二阳极相互隔离，所述第一阳极和第二阳极与所述像素电路耦接；所述第一有机发光层和第二有机发光层相互隔离，所述第一阴极和第二阴极为一体结构。
在一些示例性实施方式中，所述第一发光单元位于所述第二发光单元的一侧。
在一些示例性实施方式中，所述第一发光单元围绕在所述第二发光单元的周边。
在一些示例性实施方式中，所述第一发光单元包括第一发光部分和第二 发光部分，所述第二发光单元位于所述第一发光部分和第二发光部分之间。
在一些示例性实施方式中，所述至少一个子像素至少包括绿色子像素。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的像素电路的结构示意图；
图2为本公开至少一实施例的像素电路的另一结构示意图；
图3为本公开至少一实施例的像素电路的输入电路的等效电路图；
图4为本公开至少一实施例的像素电路的第一发光控制电路的等效电路图；
图5为本公开至少一实施例的像素电路的第二发光控制电路的等效电路图；
图6为本公开至少一实施例的像素电路的等效电路图；
图7为图6提供的像素电路的工作时序图；
图8为本公开至少一实施例的显示基板的结构示意图；
图9为本公开至少一实施例的显示基板的局部平面结构示意图；
图10为本公开至少一实施例的显示基板的局部剖面结构示意图；
图11为本公开至少一实施例的显示基板的另一局部平面结构示意图；
图12为本公开至少一实施例的显示基板的另一局部平面结构示意图；
图13为本公开至少一实施例的显示基板的另一局部平面结构示意图；
图14为本公开至少一实施例的显示基板的另一局部平面结构示意图；
图15为本公开至少一实施例的显示基板的另一局部平面结构示意图；
图16为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为多种的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理 解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电极(源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，控制极可以为栅电极。第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”、“耦接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
OLED发光器件包括：第一极、第二极以及设置在第一极和第二极之间的有机发光层。有机发光层在第一极和第二极的驱动下出射相应颜色的光线。显示基板的发光器件的有机发光层和像素电路的薄膜晶体管(TFT)的膜层均一性会影响显示均一性。在高灰阶显示时，由于发光器件的亮度高，人眼较难发现显示区别，然而，在低灰阶显示时，驱动电流较小，TFT和有机发光层的膜厚差异性会明显地影响显示效果，导致人眼观察到显示不均的情况，使得画面存在颗粒感，即低灰阶显示不均(mura)。
本公开至少一实施例提供一种像素电路及其驱动方法、显示基板及显示装置，通过对子像素进行分区显示控制，从而改善显示效果。
图1为本公开至少一实施例的像素电路的结构示意图。如图1所示，本示例性实施例的像素电路用于驱动子像素的第一发光单元和第二发光单元发光。本示例中，子像素的亮度是由第一发光单元和第二发光单元共同显示的结果。子像素的发光区域被划分为第一发光单元和第二发光单元两个部分。子像素的发光面积为第一发光单元的发光面积和第二发光单元的发光面积之和。例如，发光面积对应于像素定义层的开口的面积。
在本示例性实施方式中，如图1所示，像素电路包括：输入电路、第一发光控制电路和第二发光控制电路。输入电路，分别与数据信号线DL、扫描信号线GL、第一电源线PL1和第一节点N1耦接，配置为在扫描信号线GL提供的扫描信号的控制下，向第一节点N1写入数据信号线DL提供的数据信号，并存储写入第一节点N1的数据信号。第一发光控制电路，分别与第一节点N1、第二节点N2、第一电源线PL1和发光控制信号线EML耦接，配置为在第一电源线PL1提供的第一电源信号、第一节点N1以及发光控制信号线EML提供的发光控制信号的控制下，向第二节点N2提供驱动电流。第二节点N2与第一发光单元的第一极耦接。第二发光控制电路，分别与控制端CL、第二节点N2和第三节点N3耦接，配置为在控制端CL的控制下，导通第二节点N2和第三节点N3。第三节点N3与第二发光单元的第一极耦接。第一发光单元的第二极和第二发光单元的第二极均与第二电源线PL2耦接。
在本示例性实施方式中，如图1所示，第一节点N1与输入电路的输出端、以及第一发光控制电路的一个输入端耦接，第二节点N2与第一发光控制电路的输出端和第一发光单元的第一极耦接，第三节点N3与第二发光控制电路的输出端和第二发光单元的第一极耦接。第一节点N1与输入电路的输出端和第一发光控制电路的一个输入端等电位，第二节点N2与第一发光控制电路的输出端和第一发光单元的第一极等电位，第三节点N3与第二发光控制电路的输出端和第二发光单元的第一极等电位。在一些示例中，第一节点N1、第二节点N2和第三节点N3并非表示实际存在的部件，而是表示 电路图中相关电路连接的汇合点。
在一些示例性实施方式中，一个子像素包括的第一发光单元和第二发光单元可以均为有机发光二极管(OLED)。第一发光单元的第一极和第二发光单元的第一极可以为阳极，第一发光单元的第二极和第二发光单元的第二极可以为阴极。第一发光单元的阳极与第二节点N2耦接，第一发光单元的阴极与第二电源线PL2耦接；第二发光单元的阳极与第三节点N3耦接，第二发光单元的阴极与第二电源线PL2耦接。第一发光单元的阴极和第二发光单元的阴极可以为一体结构。然而，本实施例对此并不限定。在一些示例中，子像素包括的第一发光单元和第二发光单元可以为量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微发光二极管(Micro-LED，Micro Light Emitting Diode)、或者迷你二极管(Mini-LED)。
在一些示例性实施方式中，第一电源线PL1可以持续提供高电平信号，例如，第一电源线PL1提供第一电源信号VDD；第二电源线PL2可以持续提供低电平信号，例如，第二电源线PL2提供第二电源信号VSS。然而，本实施例对此并不限定。
本实施例提供的像素电路中，通过第一发光控制电路控制子像素的第一发光单元发光，通过第一发光控制电路和第二发光控制电路控制子像素的第二发光单元发光。本实施例的像素电路可以通过不同电压分别驱动子像素的第一发光单元和第二发光单元发光，以实现对子像素的分区驱动。在不同电压驱动下，子像素的发光面积不同。如此一来，可以在低灰阶显示时减小子像素的发光面积，从而实现驱动电流的提升，以改善低灰阶下的显示效果。
图2为本公开至少一实施例的像素电路的另一结构示意图。如图2所示，像素电路包括：输入电路、第一发光控制电路和第二发光控制电路。其中，控制端CL与第一节点N1耦接。在本示例中，第二发光控制电路分别与第一节点N1、第二节点N2和第三节点N3耦接，配置为在第一节点N1的控制下，导通第二节点N2和第三节点N3。本实施例通过将控制端CL与第一节点N1耦接，无需栅极驱动电路给控制端CL提供信号，可以简化栅极驱动电路的结构，节约布线，有利于显示装置的窄边框设计。
关于本实施例的像素电路的其余结构可以参照图1所述的像素电路的说 明，故于此不再赘述。
图3为本公开至少一实施例的像素电路的输入电路的等效电路图。如图3所示，本示例性实施例的像素电路中的输入电路包括：数据写入晶体管M1和存储电容Cst。数据写入晶体管M1的控制极与扫描信号线GL耦接，数据写入晶体管M1的第一极与数据信号线DL耦接，数据写入晶体管M1的第二极与第一节点N1耦接。存储电容Cst的第一端与第一电源线PL1耦接，存储电容Cst的第二端与第一节点N1耦接。
图3示出了输入电路的示例性结构，本领域技术人员容易理解的是，输入电路的实现方式并不限于此，只要能够实现其功能即可。
图4为本公开至少一实施例的像素电路的第一发光控制电路的等效电路图。如图4所示，本示例性实施例的像素电路中的第一发光控制电路包括：驱动晶体管M2、第一发光控制晶体管M3。驱动晶体管M2的控制极与第一节点N1耦接，驱动晶体管M2的第一极与第一电源线PL1耦接，驱动晶体管M2的第二极与第一发光控制晶体管M3的第一极耦接。第一发光控制晶体管M3的控制极与发光控制信号线EML耦接，第一发光控制晶体管M3的第二极与第二节点N2耦接。第二节点N2与第一发光单元的第一极耦接。
图4示出了第一发光控制电路的示例性结构，本领域技术人员容易理解的是，第一发光控制电路的实现方式并不限于此，只要能够实现其功能即可。
图5为本公开至少一实施例的像素电路的第二发光控制电路的等效电路图。如图5所示，本示例性实施例的像素电路中的第二发光控制电路包括：第二发光控制晶体管M4。第二发光控制晶体管M4的控制极与第一节点N1耦接，第二发光控制晶体管M4的第一极与第二节点N2耦接，第二发光控制晶体管M4的第二极与第三节点N3耦接。第三节点N3与第二发光单元的第一极耦接。
图5示出了第二发光控制电路的示例性结构，本领域技术人员容易理解的是，第二发光控制电路的实现方式并不限于此，只要能够实现其功能即可。
图6为本公开至少一实施例的像素电路的等效电路图。在一些示例性实施方式中，如图6所示，本示例性实施例的像素电路中，输入电路包括：数 据写入晶体管M1和存储电容Cst；第一发光控制电路包括：驱动晶体管M2和第一发光控制晶体管M3；第二发光控制电路包括：第二发光控制晶体管M4。
在一些示例性实施方式中，如图6所示，数据写入晶体管M1的控制极与扫描信号线GL耦接，数据写入晶体管M1的第一极与数据信号线DL耦接，数据写入晶体管M1的第二极与第一节点N1耦接。存储电容Cst的第一端与第一电源线PL1耦接，存储电容Cst的第二端与第一节点N1耦接。驱动晶体管M2的控制极与第一节点N1耦接，驱动晶体管M2的第一极与第一电源线PL1耦接，驱动晶体管M2的第二极与第一发光控制晶体管M3的第一极耦接。第一发光控制晶体管M3的控制极与发光控制信号线EML耦接，第一发光控制晶体管M3的第二极与第二节点N2耦接。第二发光控制晶体管M4的控制极与第一节点N1耦接，第二发光控制晶体管M4的第一极与第二节点N2耦接，第二发光控制晶体管M4的第二极与第三节点N3耦接。第一发光单元EL1的第一极与第二节点N2耦接，第一发光单元EL1的第二极与第二电源线PL2耦接。第二发光单元EL2的第一极与第三节点N3耦接，第二发光单元EL2的第二极与第二电源线PL2耦接。
下面通过图6提供的像素电路的工作过程进一步说明本实施例的方案。
以图6提供的像素电路中的数据写入晶体管M1、驱动晶体管M2、第一发光控制晶体管M3和第二发光控制晶体管M4均为P型薄膜晶体管为例进行说明。其中，P型晶体管在控制极为低电平时导通，在控制极为高电平时截止。在一些示例中，本实施例中的多个晶体管亦可以为N型晶体管。其中，N型晶体管在控制极为高电平时导通，在控制极为低电平时截止。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。然而，本公开实施例对此并不限定。在一些示例中，本实施例中的多个晶体管中的一部分晶体管为P型晶体管，另一部分晶体管为N型晶体管。
在一些示例性实施方式中，像素电路中的数据写入晶体管M1、驱动晶体管M2、第一发光控制晶体管M3和第二发光控制晶体管M4可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多 晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在一些示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现高分辨率(PPI，Pixel Per Inch)，低频驱动，可以降低功耗，可以提高显示品质。
图7为图6提供的像素电路的工作时序图。如图6所示，本实施例中涉及的像素电路包括：4个晶体管(即数据写入晶体管M1、驱动晶体管M2、第一发光控制晶体管M3和第二发光控制晶体管M4)、1个电容单元(即存储电容Cst)、3个信号输入端(即扫描信号线GL、数据信号线DL和发光控制信号线EML)、2个电源端(即第一电源线PL1和第二电源线PL2)。其中，第一电源线PL1持续提供高电平信号，例如第一电源信号VDD；第二电源线PL2持续提供低电平信号，例如第二电源信号VSS。
在一帧时间段内，像素电路可以包括以下工作状态：数据写入阶段和发光阶段。
第一阶段S1，即数据写入阶段，如图7所示，扫描信号线GL提供的扫描信号SCAN为低电平，数据写入晶体管M1导通，发光控制信号线EML提供的发光控制信号EM为高电平，第一发光控制晶体管M3断开。数据写入晶体管M1导通，对存储电容Cst充电，以将数据信号线DL提供的数据信号DATA存储在存储电容Cst中。存储电容Cst存储的数据信号DATA可以控制驱动晶体管M2的导通程度。
第二阶段S2，即发光阶段，如图7所示，扫描信号线GL提供的扫描信号SCAN为高电平，数据写入晶体管M1断开，发光控制信号线EML提供的发光控制信号EM为低电平，第一发光控制晶体管M3导通。当第一节点N1的电压使驱动晶体管M2和第二发光控制晶体管M4均导通，驱动晶体管M2提供的驱动电流经过第一发光控制晶体管M3流入第一发光单元EL1，使第一发光单元EL1发光，同时经过第一发光控制晶体管M3和第二发光控制 晶体管M4流入第二发光单元EL2，使第二发光单元EL2发光。当第一节点N1的电压仅使驱动晶体管M2导通，驱动晶体管M2提供的驱动电流经过第一发光控制晶体管M3流入第一发光单元EL1，使第一发光单元EL1发光；第二发光控制晶体管M4断开，第二发光单元EL2关闭。
在本示例中，驱动晶体管M2和第二发光控制晶体管M4的阈值电压相同。驱动晶体管M2的开启电压取决于(V N1-VDD)，第二发光控制晶体管M4的开启电压取决于[V N1-(VDD-Vth (M2)-Vth (M3))]。其中，V N1表示第一节点N1的电压，VDD为第一电源线PL1提供的第一电源信号，Vth (M2)为驱动晶体管M2的阈值电压，Vth (M3)为第一发光控制晶体管M3的阈值电压。
在一些示例中，V N1-VDD＞0V，则驱动晶体管M2断开，当V N1-VDD＜0V，则驱动晶体管M2导通。当(V N1-VDD)为正值时，驱动晶体管M2完全关断；当(V N1-VDD)为负值，且绝对值越大时，驱动晶体管M2提供的驱动电流越大，使得子像素的亮度越高。
在一些示例中，阈值电压Vth约为0.2V至0.3V。由于[V N1-(VDD-Vth (M2)-Vth (M3))]大于(V N1-VDD)，在第二发光控制晶体管M4断开时驱动晶体管M2会导通。例如，在发光阶段S2，当第一节点N1的电压大于(VDD-Vth (M2)-Vth (M3))且小于VDD，第二发光控制晶体管M4断开，驱动晶体管M2导通，则第一发光单元EL1继续发光，而第二发光单元EL2关闭，停止发光。在第二发光单元EL2关闭后，子像素的发光面积减少至第一发光单元EL1的发光面积，第一发光单元EL1的驱动电流得到提升，从而提高第一发光单元EL1的亮度。
本示例性实施方式中，将子像素的单个发光区域划分为两个发光区域(对应第一发光单元所在区域和第二发光单元所在区域)，并采用不同电压驱动两个发光区域，使得不同电压驱动下，子像素的发光面积不同。本实施例通过关闭子像素的第二发光单元，维持子像素的第一发光单元发光，可以减小子像素的发光面积，提升第一发光单元的驱动电流，从而提高子像素的亮度。在实现相同显示灰阶时，子像素的部分发光面积发光的亮度大于子像素的整体发光面积发光的亮度，有利于减弱低灰阶下子像素之间的亮度差异，以改善低灰阶下的显示效果。
在一些示例性实施方式中，显示灰阶的亮度是按照设定要求，通过伽马(gamma)调试获得设定的数据电压，通过像素电路获得所需的驱动电流。以红色(R)子像素为例，红色子像素的驱动电压约为6.3V时，红色子像素对应显示1灰阶。以红色子像素包括第一发光单元和第二发光单元，且晶体管的阈值电压约为0.3V为例，第二发光单元在驱动电压约为5.7V时关闭，此时红色子像素可以显示11灰阶。通过关闭第二发光单元，减小子像素的发光面积，提升第一发光单元的驱动电流，从而提升子像素的亮度，改善低灰阶下的显示效果。
本公开至少一实施例还提供一种像素电路的驱动方法，用于驱动如上所述的像素电路。本实施例的驱动方法包括：在显示第一范围的灰阶时，在扫描信号线提供的扫描信号的控制下，输入电路向第一节点写入数据信号线提供的数据信号，并存储写入第一节点的数据信号；在第一电源线提供的第一电源信号、第一节点以及发光控制信号线提供的发光控制信号的控制下，第一发光控制电路向第二节点提供驱动电流，并在控制端的控制下，第二发光控制电路向第三节点提供驱动电流。在显示第二范围的灰阶时，在扫描信号线提供的扫描信号的控制下，输入电路向第一节点写入数据信号线提供的数据信号，并存储写入第一节点的数据信号；在第一电源线提供的第一电源信号、第一节点以及发光控制信号线提供的发光控制信号的控制下，第一发光控制电路向第二节点提供驱动电流，并在控制端的控制下，第二发光控制电路使第二节点和第三节点断开。其中，第一范围的灰阶大于第二范围的灰阶。在本示例中，在显示第一范围的灰阶时，第一发光单元和第二发光单元均发光，在显示第二范围的灰阶时，第一发光单元发光，且第二发光单元不发光。
在一些示例中，第一范围为高灰阶范围，第二范围为低灰阶范围。例如，第一范围可以为大于32灰阶，第二范围可以为小于或等于32灰阶。然而，本实施例对此并不限定。
本实施例提供的像素电路的控制方法用于前述实施例提供的像素电路中，其实现原理和效果类似，故在此不再赘述。
本公开至少一实施例还提供一种显示基板，包括：设置在基底上的多个子像素。至少一个子像素包括如前述实施例所述的像素电路、以及与像素电 路耦接的第一发光单元和第二发光单元。关于像素电路的结构可以参照前述实施例的说明，故于此不再赘述。
在一些示例性实施方式中，第一发光单元包括：第一阳极、第一阴极以及设置在第一阳极和第一阴极之间的第一有机发光层。第二发光单元包括：第二阳极、第二阴极以及设置在第二阳极和第二阴极之间的第二有机发光层。第一阳极和第二阳极相互隔离，且第一阳极和第二阳极与像素电路耦接。第一有机发光层和第二有机发光层相互隔离，第一阴极和第二阴极为一体结构。本示例性实施方式中，利用像素电路采用不同电压驱动子像素的第一发光单元和第二发光单元。
在一些示例性实施方式中，第一发光单元位于第二发光单元的一侧。例如，子像素的发光区域被划分为对称的第一发光单元和第二发光单元。例如，第一发光单元和第二发光单元的发光面积之比可以约为1:1。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一发光单元围绕在第二发光单元的周边。例如，子像素的发光区域按照中心和周边围绕方式进行划分。例如，第一发光单元和第二发光单元的发光面积之比可以约为2:1。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一发光单元围绕在第二发光单元的周边。第一发光单元包括第一发光部分和第二发光部分，第二发光单元位于第一发光部分和第二发光部分之间。第一发光部分和第二发光部分可以耦接，并与像素电路耦接。
在一些示例性实施方式中，至少一个子像素至少包括绿色子像素。例如，可以仅对显示基板上的绿色子像素的发光区域进行分区，或者，可以对显示基板上的绿色子像素和红色子像素(或蓝色子像素)的发光区域均进行分区，或者，可以对显示基板上的所有子像素的发光区域均进行分区。然而，本实施例对此并不限定。
下面通过一些示例对本实施例的显示基板的结构进行举例说明。
图8为本公开至少一实施例的显示基板的结构示意图。在一些示例性实 施方式中，如图8所示，显示基板可以包括像素阵列。像素阵列与数据信号驱动器、扫描信号驱动器和发光信号驱动器相连，数据信号驱动器、扫描信号驱动器和发光信号驱动器与时序控制器相连。像素阵列可以包括多个扫描信号线(例如，S1到Sm)、多个数据信号线(例如，D1到Dn)、多个发光控制信号线(例如，E1到Eo)和多个子像素Pxij。在一些示例中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据信号。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光控制信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光控制信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素Pxij。每个子像素Pxij可以连接到对应的数据信号线、对应的扫描信号线和对应的发光控制信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图9为本公开至少一实施例的显示基板的局部平面结构示意图。在一些示例性实施方式中，如图9所示，显示基板可以包括：出射第一颜色光线的 第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3。在一些示例中，第一子像素P1可以包括第一像素电路、第一发光单元P11和第二发光单元P12，第二子像素P2可以包括第二像素电路和第二发光元件，第三子像素P3可以包括第三像素电路和第三发光元件。在一些示例中，第一像素电路可以为如图6所示的像素电路，向第一发光单元P11和第二发光单元P12输出驱动电流。第二像素电路可以为3T1C结构的像素电路，分别与扫描信号线、数据信号线和发光控制信号线耦接，配置为在扫描信号线和发光控制信号线的控制下，接收数据信号线传输的数据信号，向第二发光元件输出相应的驱动电流。第二发光元件配置为响应于第二像素电路输出的驱动电流发出相应亮度的光。第三像素电路可以为3T1C结构的像素电路，向第三发光元件输出相应的驱动电流，第三发光元件配置为响应第三像素电路输出的驱动电流发出相应亮度的光。然而，本实施例对此并不限定。例如，第二像素电路和第三像素电路可以包括其他数目的晶体管和电容器。
在一些示例性实施方式中，第一颜色光线可以为绿光，第二颜色光线可以为蓝光，第三颜色光线可以为红光。不同颜色子像素的发光效率不同。其中，蓝色子像素的发光效率小于红色子像素的发光效率，红色子像素的发光效率小于绿色子像素的发光效率。由于绿色子像素的发光效率最高，电流低，因此，在本示例中，可以仅对第一子像素P1(即绿色子像素)进行分区，形成两个发光单元(即第一发光单元P11和第二发光单元P12)并由上述实施例提供的像素电路通过不同电压进行驱动，以改善低灰阶下的显示效果。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图9所示，像素阵列中的一个重复单元包括：在第二方向D2上排列的两个第一子像素P1、分设在所述两个第一子像素P1在第一方向D1上的两侧的第二子像素P2和第三子像素P3。一个重复单元中的第一子像素P1(例如，绿色子像素)和第三子像素P3(例如，红色子像素)构成一个像素单元，并借用与其相邻的另一重复单元中的第二子像素P2(例如，蓝色子像素)构成一个虚拟像素以进行显示。该重复单元中的第二子像素P2(例如，蓝色子像素)和另一个第一子像素P1(例如，绿 色子像素)构成一个像素，并借用与其相邻的另一重复单元中的第三子像素(例如，红色子像素)构成一个虚拟像素以进行显示。在第二方向D2上，第二子像素P2和第三子像素P3间隔排布，在第三方向D3上，第二子像素P2和第一子像素P1间隔排布。其中，第一方向D1垂直于第二方向D2，第三方向D3与第一方向D1和第二方向D2均交叉。然而，本实施例对此并不限定。例如，一个像素单元包括三个子像素(例如，红色子像素、绿色子像素和蓝色子像素)，三个子像素可以采用水平并列、竖直并列方式排列；一个像素单元包括四个子像素(例如，红色子像素、绿色子像素、蓝色子像素和白色子像素)，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列。
在一些示例中，第二子像素P2和第三子像素P3的形状可以是矩形状。第一子像素P1的第一发光单元P11和第二发光单元P12可以为矩形状。然而，本实施例对此并不限定。例如，第二子像素、第三子像素、第一发光单元和第二发光单元可以为其他形状，例如菱形、五边形或六边形。
在一些示例中，第一子像素P1的第一发光单元P11和第二发光单元P12关于平行于第三方向D3的轴线相互对称。第一发光单元P11和第二发光单元P12的发光面积之比可以约为1:1。在本示例中，第一发光单元P11和第二发光单元P12的发光面积可以指由像素定义层的开口暴露出的发光区域的面积。然而，本实施例对此并不限定。在本示例中，通过控制第一发光单元和第二发光单元的发光面积之比，可以调节第一发光单元的电流增加倍速。
图10为本公开至少一实施例的显示基板的局部剖面结构示意图。图10为图9中沿Q-Q方向的局部剖面示意图，仅示意了显示基板的第一子像素P1的局部剖面结构。在一些示例性实施方式中，如图10所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底100上的驱动电路层102、设置在驱动电路层102远离基底100一侧的发光结构层103以及设置在发光结构层103远离基底100一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在一些示例性实施方式中，基底100可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素电路的多个晶体管和 存储电容，图10中的驱动电路层102仅示出第一晶体管210、第二晶体管211和一个存储电容212作为示例。例如，第一晶体管210可以为图6所示的像素电路中的第一发光控制晶体管M3，第二晶体管211可以为图6所示的像素电路中的第二发光控制晶体管M4，存储电容212可以为图6所示的像素电路中的存储电容Cst。
在一些示例中，发光结构层103可以至少包括：像素定义层304、第一发光单元和第二发光单元。第一发光单元包括：第一阳极301a、第一有机发光层302a和阴极303。第一阳极301a通过过孔与第一晶体管210的漏电极连接，第一有机发光层303a与第一阳极301a连接，阴极303与第一有机发光层303a连接，第一有机发光层303a在第一阳极301a和阴极303驱动下出射第一颜色光线。第二发光单元包括：第二阳极301b、第二有机发光层302b和阴极303。第二阳极301b通过过孔与第二晶体管211的漏电极连接，第二有机发光层303b与第二阳极301b连接，阴极303与第二有机发光层303b连接，第二有机发光层303b在第二阳极301b和阴极303驱动下出射第一颜色光线。在本示例中，第一发光单元和第二发光单元均出射绿光。第一发光单元和第二发光单元的发光区域为像素定义层304的开口对应区域。发光结构层103还可以包括：第二子像素P2的第二发光元件、第三子像素P3的第三发光元件。第二发光元件可以包括第一极、第二极和设置在第一极和第二极之间的有机发光层，第二发光元件的第一极与第二像素电路耦接；第三发光元件可以包括第一极、第二极和设置在第一极和第二极之间的有机发光层，第三发光元件的第一极与第三像素电路耦接。
在一些示例中，封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在一些示例中，有机发光层可以包括叠设的空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、电子阻挡层(EBL，Electron Block Layer)、发光层(EML，Emitting Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子传输层(ETL，Electron Transport Layer) 和电子注入层(EIL，Electron Injection Layer)。在一些示例中，第一发光单元的第一有机发光层和第二发光单元的第二有机发光层相互隔离。然而，本实施例对此并不限定。例如，在一些示例中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
本示例性实施方式提供的显示基板，将绿色子像素的发光区域划分为两个半区(即，第一发光单元对应的发光区域和第二发光单元对应的发光区域)，并利用上述实施例提供的像素电路采用不同电压驱动绿色子像素的两个半区，从而在低灰阶下可以减小绿色子像素的发光面积，提升显示亮度，改善低灰阶下的显示效果。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图11为本公开至少一实施例的显示基板的另一局部平面示意图。在一些示例性实施方式中，如图11所示，出射第一颜色光线的第一子像素P1包括第一像素电路、第一发光单元P11和第二发光单元P12。第一发光单元P11围绕在第二发光单元P12的周围。第一发光单元P11与第二发光单元P12的发光面积之比约为2:1。例如，第二发光单元P12可以为矩形状，第一发光单元P11可以为围绕第二发光单元P12且具有一个缺口的环状。在本示例中，通过将第一发光单元P11隔断，可以给精细金属掩模版(FMM，Fine Metal Mask)提供支撑，以满足工艺需求，便于制备有机发光层。然而，本实施例对此并不限定。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图12为本公开至少一实施例的显示基板的另一局部平面示意图。在一些示例性实施方式中，如图12所示，出射第一颜色光线的第一子像素P1包括 第一像素电路、第一发光单元P11和第二发光单元P12。第一发光单元P11围绕在第二发光单元P12的周围。第一发光单元P11与第二发光单元P12的发光面积之比约为2:1。例如，第二发光单元P12可以为矩形状。第一发光单元P11具有相互连接的第一发光部分P11a和第二发光部分P11b。例如，第一发光部分P11a和第二发光部分P11b的有机发光层可以连通。第一发光部分P11a和第二发光部分P11b可以关于平行于第一方向D1的轴线相互对称。然而，本实施例对此并不限定。本示例性实施方式中，通过将第一发光单元划分为对称的两个部分，可以在第二发光单元关闭时，提高第一子像素的显示亮度的均一性。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图13为本公开至少一实施例的显示基板的另一局部平面示意图。在一些示例性实施方式中，如图13所示，出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3各自包括像素电路、以及与像素电路连接的第一发光单元和第二发光单元。关于像素电路的结构可以参照前述实施例提供的像素电路的说明，关于第一发光单元和第二发光单元的说明可以参照图9所示的相关说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图14为本公开至少一实施例的显示基板的另一局部平面示意图。在一些示例性实施方式中，如图14所示，出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3各自包括像素电路、以及与像素电路连接的第一发光单元和第二发光单元。关于像素电路的结构可以参照前述实施例提供的像素电路的说明，关于第一发光单元和第二发光单元的说明可以参照图11所示的相关说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图15为本公开至少一实施例的显示基板的另一局部平面示意图。在一些 示例性实施方式中，如图15所示，出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3各自包括像素电路、以及与像素电路连接的第一发光单元和第二发光单元。关于像素电路的结构可以参照前述实施例提供的像素电路的说明，关于第一发光单元和第二发光单元的说明可以参照图12所示的相关说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
在图13至图15所示的显示基板中，每个子像素均被划分为两个发光单元，并通过像素电路提供不同电压进行驱动，以在低灰阶下减小子像素的发光面积，从而提高子像素的显示亮度，改善低灰阶下的显示效果。
图16为本公开至少一实施例的显示装置的示意图。如图16所示，本实施例提供一种显示装置91，包括前述实施例的显示基板910。在一些示例中，显示基板910可以为OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (14)

  1. 一种像素电路，用于驱动子像素的第一发光单元和第二发光单元发光，所述像素电路包括：输入电路、第一发光控制电路和第二发光控制电路；
    所述输入电路，分别与数据信号线、扫描信号线、第一电源线和第一节点耦接，配置为在扫描信号线提供的扫描信号的控制下，向第一节点写入数据信号线提供的数据信号，并存储写入所述第一节点的数据信号；
    所述第一发光控制电路，分别与第一电源线、发光控制信号线、第一节点和第二节点耦接，配置为在所述第一电源线提供的第一电源信号、第一节点以及发光控制信号线提供的发光控制信号的控制下，向第二节点提供驱动电流；所述第二节点与所述第一发光单元的第一极耦接；
    所述第二发光控制电路，分别与控制端、第二节点和第三节点耦接，配置为在所述控制端的控制下，导通第二节点和第三节点；所述第三节点与所述第二发光单元的第一极耦接；
    所述第一发光单元的第二极和第二发光单元的第二极均与第二电源线耦接。
  2. 根据权利要求1所述的像素电路，其中，所述控制端与所述第一节点耦接。
  3. 根据权利要求1或2所述的像素电路，其中，所述输入电路包括：数据写入晶体管和存储电容；
    所述数据写入晶体管的控制极与扫描信号线耦接，所述数据写入晶体管的第一极与数据信号线耦接，所述数据写入晶体管的第二极与第一节点耦接；
    所述存储电容的第一端与第一电源线耦接，所述存储电容的第二端与第一节点耦接。
  4. 根据权利要求1或2所述的像素电路，其中，所述第一发光控制电路包括：驱动晶体管和第一发光控制晶体管；所述驱动晶体管的控制极与第一节点耦接，所述驱动晶体管的第一极与第一电源线耦接，所述驱动晶体管的第二极与所述第一发光控制晶体管的第一极耦接；所述第一发光控制晶体管 的控制极与发光控制信号线耦接，所述第一发光控制晶体管的第二极与第二节点耦接。
  5. 根据权利要求1或2所述的像素电路，其中，所述第二发光控制电路，包括：第二发光控制晶体管；所述第二发光控制晶体管的控制极与所述控制端耦接，所述第二发光控制晶体管的第一极与第二节点耦接，所述第二发光控制晶体管的第二极与第三节点耦接。
  6. 根据权利要求2所述的像素电路，其中，所述输入电路包括：数据写入晶体管和存储电容；所述第一发光控制电路包括：驱动晶体管和第一发光控制晶体管；所述第二发光控制电路，包括：第二发光控制晶体管；
    所述数据写入晶体管的控制极与扫描信号线耦接，所述数据写入晶体管的第一极与数据信号线耦接，所述数据写入晶体管的第二极与第一节点耦接；
    所述存储电容的第一端与第一电源线耦接，所述存储电容的第二端与第一节点耦接；
    所述驱动晶体管的控制极与第一节点耦接，所述驱动晶体管的第一极与第一电源线耦接，所述驱动晶体管的第二极与所述第一发光控制晶体管的第一极耦接；
    所述第一发光控制晶体管的控制极与发光控制信号线耦接，所述第一发光控制晶体管的第二极与第二节点耦接；
    所述第二发光控制晶体管的控制极与第一节点耦接，所述第二发光控制晶体管的第一极与第二节点耦接，所述第二发光控制晶体管的第二极与第三节点耦接。
  7. 一种像素电路的驱动方法，用于驱动如权利要求1至6中任一项所述的像素电路，所述驱动方法包括：
    在显示第一范围的灰阶时，在扫描信号线提供的扫描信号的控制下，输入电路向第一节点写入数据信号线提供的数据信号，并存储写入第一节点的数据信号；在第一电源线提供的第一电源信号、第一节点以及发光控制信号线提供的发光控制信号的控制下，第一发光控制电路向第二节点提供驱动电流，并在控制端的控制下，第二发光控制电路向第三节点提供驱动电流；
    在显示第二范围的灰阶时，在扫描信号线提供的扫描信号的控制下，输入电路向第一节点写入数据信号线提供的数据信号，并存储写入第一节点的数据信号；在第一电源线提供的第一电源信号、第一节点以及发光控制信号线提供的发光控制信号的控制下，第一发光控制电路向第二节点提供驱动电流，并在控制端的控制下，第二发光控制电路使第二节点和第三节点断开；
    其中，所述第一范围的灰阶大于第二范围的灰阶。
  8. 一种显示基板，包括：设置在基底上的多个子像素；至少一个子像素包括：如权利要求1至6中任一项所述的像素电路、以及与所述像素电路耦接的第一发光单元和第二发光单元。
  9. 根据权利要求8所述的显示基板，其中，所述第一发光单元包括：第一阳极、第一阴极以及设置在所述第一阳极和第一阴极之间的第一有机发光层；
    所述第二发光单元包括：第二阳极、第二阴极以及设置在所述第二阳极和第二阴极之间的第二有机发光层；
    所述第一阳极和第二阳极相互隔离，所述第一阳极和第二阳极与所述像素电路耦接；所述第一有机发光层和第二有机发光层相互隔离，所述第一阴极和第二阴极为一体结构。
  10. 根据权利要求8所述的显示基板，其中，所述第一发光单元位于所述第二发光单元的一侧。
  11. 根据权利要求8所述的显示基板，其中，所述第一发光单元围绕在所述第二发光单元的周边。
  12. 根据权利要求11所述的显示基板，其中，所述第一发光单元包括第一发光部分和第二发光部分，所述第二发光单元位于所述第一发光部分和第二发光部分之间。
  13. 根据权利要求8至12中任一项所述的显示基板，其中，所述至少一个子像素至少包括绿色子像素。
  14. 一种显示装置，包括如权利要求8至13中任一项所述的显示基板。
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