WO2022267559A1 - 一种显示基板和显示装置 - Google Patents

一种显示基板和显示装置 Download PDF

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Publication number
WO2022267559A1
WO2022267559A1 PCT/CN2022/080319 CN2022080319W WO2022267559A1 WO 2022267559 A1 WO2022267559 A1 WO 2022267559A1 CN 2022080319 W CN2022080319 W CN 2022080319W WO 2022267559 A1 WO2022267559 A1 WO 2022267559A1
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WIPO (PCT)
Prior art keywords
display area
row
scanning
sub
pixels
Prior art date
Application number
PCT/CN2022/080319
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English (en)
French (fr)
Inventor
汪杨鹏
何帆
王琦伟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/033,363 priority Critical patent/US20230403894A1/en
Publication of WO2022267559A1 publication Critical patent/WO2022267559A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of display technologies, and in particular, relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • LCD Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • the concept of a full-screen mobile phone has received widespread attention in the mobile phone market, and it is also the development direction of future mobile phones.
  • the camera can be hidden so that the front viewable area is almost entirely the screen, so that the user can obtain a better display effect.
  • the present disclosure provides a display substrate, including: a display area and a non-display area surrounding the display area, and the display area includes: a plurality of scanning lines extending along a first direction and a plurality of scanning lines arranged in an array sub-pixels, the display area includes: a first display area and a second display area, the first display area is located at the periphery of the second display area, and the second display area includes: a light-transmitting display area and a transitional display area, the transition display area is located on the side of the light-transmitting display area;
  • the light-transmitting display area includes: m rows and n columns of sub-pixels, each sub-pixel located in the light-transmitting display area includes: a light-emitting element, the light-emitting element of each sub-pixel located in the i-th row of the light-transmitting display area and the light-emitting element located in the light-transmitting display area
  • the i+1th row of the area, and the light-emitting elements of the sub-pixels of the same color are electrically connected, and i is an odd number less than or equal to m;
  • the transition display area includes: m rows and n columns of sub-pixels, the i-th row of sub-pixels in the light-transmitting display area and the i-th row of sub-pixels in the transition display area are located in the same row; each sub-pixel located in the transition display area includes : pixel circuit and light-emitting element, the light-emitting element of each sub-pixel located in the i-th row of the transition display area is electrically connected to the light-emitting element of the sub-pixel of the same color located in the i+1-th row of the transition display area; located in the transition display The pixel circuit of the i-th row of the sub-pixel in the transition display area is electrically connected to the light-emitting element, and the pixel circuit of the sub-pixel located in the i+1-th row and j-th column of the transition display area is connected to the i+1-th row and j-th column of the light-transmitting display area.
  • the pixel circuits of the i-th row and i+1th row of sub-pixels in the transitional display area are connected to the same scanning line.
  • the pixel circuits of the i-th row and i+1-th row of sub-pixels in the transitional display area are connected to the first scan line or the second scan line;
  • the first scan line is a scan line that is located in the same row as the i-th row of sub-pixels located in the transition display area and is connected to the sub-pixels located in the first display area;
  • the sub-pixels in the i+1th row of the region are located in the same row, and are located on the scanning line connected to the sub-pixels in the first display region.
  • the first display area includes: a plurality of sub-pixels, and each sub-pixel located in the first display area includes: a pixel circuit and a light-emitting element; at least three sub-pixels located in the same row form a pixel unit;
  • the light-emitting element includes: an anode, an organic light-emitting layer and a cathode;
  • the anode of the light-emitting element of each sub-pixel in the i-th row and k-column pixel unit in the light-transmitting display area is respectively connected to a sub-pixel of the same color in the i+1-th row and k-column pixel unit in the light-transmitting display area
  • the anode of the light-emitting element of each sub-pixel in the i-th row and j-column pixel unit in the transitional display area respectively emits light from a sub-pixel of the same color in the i+1-th row and j-column pixel unit in the transitional display area anodic electrical connection of the component;
  • the pixel circuit of the sub-pixel located in the i+1th row and j-th column of the transitional display area is electrically connected to the anode of the light-emitting element of the sub-pixel located in the i+1th row and j-th column of the light-transmitting display area;
  • the pixel circuit of the sub-pixel located in the first display area is electrically connected to the anode of the light emitting element.
  • the display substrate further includes: a plurality of data lines extending along the second direction, the pixel circuit of the i-th row and j-th column sub-pixel in the transition display area is electrically connected to the first data line, The pixel circuit of the sub-pixel in the i+1th row and the jth column of the transitional display area is electrically connected to the second data line, and the first direction intersects the second direction;
  • the first data line is located in the same column as the i-th row and j-th column sub-pixel in the transitional display area, and is connected to the pixel circuit of the sub-pixel in the first display area;
  • the second data line It is a data line connected to the pixel circuit of the sub-pixel located in the same column as the sub-pixel located in the i+1th row and j-th column of the light-transmitting display area and located in the first display area.
  • it also includes: a data connection line, the data connection line and the data line are arranged in different layers;
  • the data connection line is a second data line connected to the pixel circuit of the i+1th row and jth column sub-pixel in the transitional display area and the pixel circuit of the i+1th row and jth column sub-pixel in the transitional display area electrical connection.
  • the light-transmitting display area includes: a first side and a second side that are oppositely arranged, and a third side and a fourth side that are oppositely arranged;
  • the transitional display area includes: a first transitional display area and the second transitional display area;
  • the first transitional display area is located on the first side of the light-transmitting display area
  • the second transitional display area is located on the second side of the light-transmitting display area
  • the first transitional display area and the second transitional display area are arranged along the first direction.
  • the first display area when the number of the second display area is one, includes: a first normal display area, a second normal display area, a third normal display area and a fourth normal display area ;
  • the k-th line of the first normal display area is the same row as the k-th line of the light-transmitting display area
  • the k-th line of the second normal display area is the same line as the k-th line of the light-transmitting display area
  • k is greater than or equal to 1 and less than a positive integer equal to m
  • the first normal display area is located on a side of the first transitional display area away from the light-transmitting display area, and the second normal display area is located on a side of the second transitional display area away from the light-transmitting display area. side; the third normal display area is located on the third side of the light-transmitting display area, and the fourth normal display area is located on the fourth side of the light-transmitting display area; the third normal display area and the The fourth normal display area is arranged along the second direction.
  • the first scanning line when the pixel circuits of the i-th row and i+1-th row of sub-pixels in the transitional display area are connected to the first scanning line, the first scanning line includes: first scanning parts arranged at intervals and a second scanning part; the second scanning line includes: a third scanning part and a fourth scanning part arranged at intervals and extending along the first direction;
  • the first scanning part is electrically connected to the pixel circuits of the i-th row and i+1-th row of sub-pixels in the first transition display area and the pixel circuits of the i-th row of sub-pixels in the first normal display area;
  • the second scanning part is electrically connected to the pixel circuits of the i-th row and i+1th row of sub-pixels in the second transitional display area and the pixel circuit of the i-th row of sub-pixels in the second normal display area;
  • the third scanning part is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area;
  • the fourth scanning part is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second normal display area.
  • the first scanning part includes: a first connecting part, a second connecting part and a third connecting part, the first connecting part and the third connecting part extend along the first direction, and the second connecting part extends in a second direction;
  • the first connection part is respectively electrically connected to the pixel circuit of the i-th row of sub-pixels in the first normal display area, the pixel circuit of the i-th row of sub-pixels in the first transitional display area, and the second connection part; the second connection part is electrically connected to the second connection part.
  • the third connecting portion is electrically connected; the third connecting portion is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first transitional display area;
  • the second scanning part includes: a fourth connection part, a fifth connection part and a sixth connection part, the fourth connection part and the sixth connection part extend along the first direction, and the fifth connection part extends along the second direction;
  • the fourth connecting portion is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area, the pixel circuit of the i-th row of sub-pixels located in the second transitional display area, and the fifth connecting portion; the fifth connecting portion is electrically connected to the fifth connecting portion.
  • the sixth connection portion is electrically connected; the sixth connection portion is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second transitional display area.
  • the first scanning part further includes: a seventh connecting part extending along the second direction, the seventh connecting part is electrically connected to the first connecting part and the third connecting part respectively;
  • the second scanning part further includes: an eighth connecting part extending along the second direction, the eighth connecting part is electrically connected to the fourth connecting part and the sixth connecting part respectively.
  • the first scan line further includes: a first scan connection part
  • the first scanning connection part is electrically connected to the first scanning part and the second scanning part respectively.
  • the second scanning line further includes: a second scanning part
  • the second scanning connection part is electrically connected to the third scanning part and the fourth scanning part respectively
  • the second scanning line when the pixel circuits of the i-th row and i+1-th row of sub-pixels in the transitional display area are connected to the second scanning line, the second scanning line includes: first scanning parts arranged at intervals and a second scanning part; the first scanning line includes: a third scanning part and a fourth scanning part arranged at intervals and extending along the first direction;
  • the first scanning part is electrically connected to the pixel circuits of the i-th row and i+1th row of sub-pixels in the first transition display area and the pixel circuits of the i+1-th row of sub-pixels in the first normal display area;
  • the second scanning part is electrically connected to the pixel circuits of the i-th row and the i+1th row of sub-pixels in the second transition display area and the pixel circuits of the i+1-th row of sub-pixels in the second normal display area;
  • the third scanning part is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area;
  • the fourth scanning part is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area.
  • the first scanning part includes: a first connecting part, a second connecting part and a third connecting part, the first connecting part and the third connecting part extend along the first direction, and the second connecting part extending along the second direction; the first connection part is respectively connected with the pixel circuit of the i+1th row of sub-pixels located in the first normal display area, the pixel circuit of the i+1th row of sub-pixels located in the first transitional display area, and the second The connecting part is electrically connected; the second connecting part is electrically connected to the third connecting part; the third connecting part is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first transitional display area;
  • the second scanning part includes: a fourth connecting part, a fifth connecting part and a sixth connecting part, the fourth connecting part and the sixth connecting part extend along the first direction, the fifth connecting part extends along the second direction;
  • the connection part is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second normal display area, the pixel circuit of the i+1th row of sub-pixels located in the second transitional display area, and the fifth connection part;
  • the fifth connection The portion is electrically connected to the sixth connection portion;
  • the sixth connection portion is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second transitional display area.
  • the first scanning part further includes: a seventh connecting part extending along the second direction, and the seventh connecting part is respectively electrically connected to the first connecting part and the third connecting part;
  • the second scanning part further includes: an eighth connecting part extending along the second direction, and the eighth connecting part is electrically connected to the fourth connecting part and the sixth connecting part respectively.
  • the second scan line further includes: a first scan connection part
  • the first scanning connection part is electrically connected to the first scanning part and the second scanning part respectively.
  • the first scan line further includes: a second scan connection part
  • the second scanning connection part is electrically connected to the third scanning part and the fourth scanning part respectively.
  • the first display area when the number of the second display area is at least two, includes: a first normal display area, a second normal display area, a third normal display area, a fourth normal display area display area and Q-1 fifth normal display areas;
  • the kth line of the first normal display area is the same row as the kth line of the light-transmitting display area
  • the k-th line of the second normal display area is the same as the k-th line of the light-transmitting display area
  • the k row is the same row
  • the kth row of the fifth normal display area is the same row as the kth row of the light-transmitting display area
  • k is a positive integer greater than or equal to 1 and less than or equal to m
  • Q is the number of the second display area;
  • the first normal display area is located on the side of the first transitional display area away from the light-transmitting display area
  • the second normal display area is located on the side of the second transitional display area away from the light-transmitting display area
  • the third normal display area is located in the light-transmitting display area
  • the fourth normal display area is located on the fourth side of the light-transmitting display area
  • the third normal display area and the fourth normal display area are arranged along the second direction
  • the i-th fifth normal display area is located in the i-th Between the second display area and the i+1th second display area.
  • the first scanning line is respectively connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, and the pixels of the i-th row of sub-pixels located in the first transition display area and the second transition display area of all the second display areas circuit, the pixel circuit of the i+1th row of sub-pixels located in the first transitional display area and the second transitional display area of all the second display areas, the pixel circuit of the i-th row of sub-pixels of all the fifth normal display area, and the pixel circuit of the i-th row of sub-pixels located in the fifth normal display area
  • the pixel circuits of the i-th row of sub-pixels in the normal display area are electrically connected;
  • the second scanning line is respectively connected with the pixel circuit of the i+1th row of sub-pixels in the first normal display area, the pixel circuit of the i+1th row of sub-pixels in the second normal display area, and all the pixel circuits in the fifth normal display area.
  • the pixel circuits of the i+1th row of sub-pixels in the region are electrically connected;
  • the first scanning line includes: a first scanning part, Q-1 second scanning parts and third scanning parts, and Q first scanning connecting parts;
  • the first scanning part is respectively connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, and the pixels of the i-th row and i+1-th row of sub-pixels located in the first transitional display area of the first second display area. electrical circuit connection;
  • the t-th second scanning part is respectively connected with the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area, the i-th row and the i+1-th row of the t-th second transition display area in the t-th second display area
  • the pixel circuit of the sub-pixel is electrically connected to the pixel circuit of the i-th row and the i+1-th row of the first transition display area of the t+1-th second display area, and t is a positive integer smaller than Q;
  • the third scanning part is respectively connected with the pixel circuit of the i-th row and the i+1th row of sub-pixels in the second transitional display area of the Q-th second display area and the pixel circuit of the i-th row of sub-pixels in the second normal display area electrical connection;
  • the first first scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, and the t-th first scanning connection part is respectively connected to the t-1th second scanning part and the t-th second scanning part.
  • the scanning part is electrically connected;
  • the Qth first scanning connection part is electrically connected to the Q-1th second scanning part and the third scanning part respectively;
  • the second scanning line includes: a fourth scanning part, Q-1 fifth scanning parts and sixth scanning parts, and Q second scanning connecting parts;
  • the fourth scanning part is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area;
  • the tth fifth scanning part is electrically connected to the pixel circuit of the i+1th row of sub-pixels in the tth fifth normal display area;
  • the sixth scanning part is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second first display area;
  • the first second scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, and the t second scanning connection part is respectively connected to the t-1th second scanning part and the t second scanning part.
  • the scanning part is electrically connected; the Qth second scanning connection part is electrically connected to the Q-1th second scanning part and the third scanning part respectively.
  • the first scanning line is respectively connected with the pixel circuit of the i-th row of sub-pixels in the first normal display area, the pixel circuit of the i-th row of sub-pixels in the second normal display area, and the i-th row of sub-pixels in all the fifth normal display areas.
  • the pixel circuits of the row sub-pixels are electrically connected;
  • the second scanning line is respectively connected with the pixel circuit of the i+1th row of sub-pixels located in the first normal display area, the i-th row and the i-th row of the first transitional display area and the second transitional display area of all the second display areas.
  • the pixel circuit of the i+1 row of sub-pixels, the pixel circuits of the i+1th row of sub-pixels in all the fifth normal display areas, and the pixel circuits of the i+1th row of sub-pixels in the second normal display area are electrically connected;
  • the second scanning line includes: a first scanning part, Q-1 second scanning parts and third scanning parts, and Q first scanning connecting parts;
  • the first scanning part is respectively connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area and the i-th row and i+1th row of sub-pixels located in the first transitional display area of the first second display area
  • the pixel circuit is electrically connected
  • the t-th second scanning part is respectively connected with the pixel circuit of the i+1th row of sub-pixels in the t-th fifth normal display area, the i-th row and the i+th row of the t-th second transitional display area in the t-th second display area
  • the pixel circuits of the sub-pixels in row 1 are electrically connected to the pixel circuits of the i-th row and the i+1-th row of sub-pixels in the first transitional display region of the t+1th second display region;
  • the third scanning part is respectively connected with the pixel circuits of the i-th row and the i+1th row of sub-pixels in the second transitional display area of the Q-th second display area and the i+1th row of sub-pixels in the second normal display area.
  • the pixel circuit is electrically connected;
  • the first first scanning connecting part is electrically connected to the first scanning part and the first second scanning part respectively, and the t second scanning connecting part is respectively connected to the t-1th second scanning part and the t second scanning part.
  • the scanning part is electrically connected;
  • the Qth second scanning connection part is electrically connected to the Q-1th second scanning part and the third scanning part respectively;
  • the first scanning line includes: a fourth scanning part, Q-1 fifth scanning parts, a sixth scanning part and Q second scanning connecting parts;
  • the fourth scanning part is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area;
  • the t-th fifth scanning part is electrically connected to the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area;
  • the sixth scanning part is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area;
  • the first second scanning connection part is electrically connected to the first scanning part and the first second scanning part respectively, and the t second scanning connection part is respectively connected to the t-1th second scanning part and the t second scanning part.
  • the scanning part is electrically connected; the Qth second scanning connection part is electrically connected to the Q-1th second scanning part and the third scanning part respectively.
  • the present disclosure further provides a display device, including: the above-mentioned display substrate.
  • FIG. 1 is a schematic structural view of a display substrate
  • Fig. 2 is a schematic plan view of a display area of a display substrate provided by an exemplary embodiment
  • FIG. 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a working timing diagram of a pixel circuit
  • Fig. 6 is a first structural schematic diagram of a display substrate provided by an exemplary embodiment
  • Fig. 7 is a schematic structural diagram of a display substrate provided by another exemplary embodiment.
  • FIG. 8 is a first schematic diagram of division of the display area
  • FIG. 9 is a second schematic diagram of the division of the display area
  • Fig. 10 is a first schematic diagram of multiple scanning lines provided by an exemplary embodiment
  • Fig. 11 is a second schematic diagram of multiple scanning lines provided by an exemplary embodiment
  • FIG. 12 is a third schematic diagram of multiple scanning lines provided by an exemplary embodiment
  • FIG. 13 is a fourth schematic diagram of multiple scanning lines provided by an exemplary embodiment
  • FIG. 14 is a fifth schematic diagram of multiple scanning lines provided by an exemplary embodiment
  • Fig. 15 is a sixth schematic diagram of multiple scanning lines provided by an exemplary embodiment
  • FIG. 16 is a seventh schematic diagram of multiple scanning lines provided by an exemplary embodiment
  • Fig. 17 is a schematic diagram eight of multiple scanning lines provided by an exemplary embodiment
  • Fig. 18 is a first schematic diagram of multiple scanning lines provided by another exemplary embodiment
  • Fig. 19 is a second schematic diagram of multiple scanning lines provided by another exemplary embodiment.
  • FIG. 20 is a third schematic diagram of multiple scanning lines provided by another exemplary embodiment.
  • Fig. 21 is a fourth schematic diagram of multiple scanning lines provided by another exemplary embodiment.
  • Fig. 22 is a fifth schematic diagram of multiple scanning lines provided by another exemplary embodiment.
  • Fig. 23 is a sixth schematic diagram of multiple scanning lines provided by another exemplary embodiment.
  • Fig. 24 is a seventh schematic diagram of multiple scanning lines provided by another exemplary embodiment.
  • Fig. 25 is an eighth schematic diagram of multiple scanning lines provided by another exemplary embodiment.
  • Fig. 26 is a first schematic diagram of multiple scanning lines provided by yet another exemplary embodiment
  • Fig. 27 is a second schematic diagram of multiple scanning lines provided by yet another exemplary embodiment
  • Fig. 28 is a third schematic diagram of multiple scanning lines provided by yet another exemplary embodiment.
  • Fig. 29 is a fourth schematic diagram of multiple scanning lines provided by yet another exemplary embodiment.
  • Fig. 30 is a timing diagram of some signals provided by an exemplary embodiment
  • Fig. 31 is a timing diagram of some signals provided by another exemplary embodiment.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • FIG. 1 is a schematic structural view of a display substrate.
  • the display substrate may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines ( D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller can provide the grayscale value and control signal suitable for the specification of the data signal driver to the data signal driver, and can supply the clock signal and the scanning signal suitable for the specification of the scanning signal driver.
  • a start signal and the like are supplied to the scan signal driver, and a clock signal, an emission stop signal, and the like suitable for the specifications of the light emission signal driver can be supplied to the light emission signal driver.
  • the data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller.
  • the data signal driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . .
  • the scan signal driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver can be constructed in the form of a shift register, and can generate scans in such a way that a scan start signal supplied in the form of a conduction level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal signal, m can be a natural number.
  • the lighting signal driver may generate emission signals to be supplied to the lighting signal lines E1, E2, E3, . . . , and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission signal driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting signal driver can be configured in the form of a shift register, and can generate the light emitting signal in a manner of sequentially transmitting the light emitting stop signal provided in the form of off-level pulses to the next-stage circuit under the control of the clock signal, o can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scanning signal line, and a corresponding light emitting signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to an i-th scan signal line and connected to a j-th data signal line.
  • Full-screen display products include: a light-transmitting display area for setting optical devices and a transitional display area on the side of the light-transmitting display area.
  • the light-transmitting display area and the transition display area are not displayed at the same time, which affects the display effect of the display product.
  • FIG. 2 is a schematic plan view of a display area of a display substrate provided by an exemplary embodiment
  • FIG. 3 is a schematic view of a structure of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate provided by the embodiment of the present disclosure includes: a display area R10 and a non-display area surrounding the display area, and the display area includes: a plurality of scanning lines G extending along the first direction and an array arrangement
  • the display area includes: a first display area R10 and a second display area R20, the first display area R10 is located at the periphery of the second display area R20, and the second display area R20 includes: a light-transmitting display area R21 and a transition The display area R22, the transitional display area R22 is located at the side of the light-transmitting display area R21.
  • the light-transmitting display area includes: m rows and n-columns of sub-pixels P, and each sub-pixel located in the light-transmitting display area includes: a light emitting element 11 .
  • the light-emitting element 11 of each sub-pixel located in the i-th row of the light-transmitting display area is electrically connected to the light-emitting element 11 of the sub-pixel of the same color located in the i+1-th row of the light-transmitting display area, and i is less than or equal to m odd number of .
  • each sub-pixel located in the light-transmitting display area does not include a pixel circuit.
  • the transition display area includes: m rows and n columns of sub-pixels, the i-th row of sub-pixels in the light-transmitting display area and the i-th row of sub-pixels in the transition display area are located in the same row; each sub-pixel located in the transition display area includes : pixel circuit 10 and light-emitting element 11, the light-emitting element of each sub-pixel located in row i of the transition display area is electrically connected to the light-emitting element of the sub-pixel of the same color located in row i+1 of the transition display area.
  • the pixel circuit of the i-th row sub-pixel located in the transitional display area is electrically connected to the light-emitting element, and the pixel circuit of the sub-pixel located in the i+1th row and j-th column of the transitional display area is connected to the pixel circuit located in the light-transmitting display area.
  • the light-emitting elements of the sub-pixels in the i+1th row and the jth column are electrically connected, and j is a positive integer less than or equal to n.
  • the pixel circuits of sub-pixels in row i and row i+1 located in the transitional display area are connected to the same scan line.
  • the first display area and the second display area have the same resolution.
  • the resolution Pixels Per Inch, referred to as PPI
  • PPI the resolution
  • the resolution refers to the number of pixels per unit area, which can be called pixel density. The higher the PPI value, the higher the density of the display substrate, the more detailed the picture. Rich.
  • the position of the light-transmitting display area may correspond to the position of the optical device, and has the functions of displaying images and transmitting light, and the transmitted light is received by the optical device.
  • the transitional display area has the functions of displaying images and providing signals for the light-transmitting display area.
  • the values of m and n may be determined according to the size of the optical device.
  • the shape of the light-transmitting display area in a plane parallel to the display substrate, can be any one or more of the following: rectangle, polygon, circle and ellipse, and the optical device can be a fingerprint identification Devices, camera devices, or optical sensors such as 3D imaging, the present disclosure is not limited here.
  • the shape of the light-transmitting display area is a circle
  • the diameter of the circle may be about 3 mm to 5 mm.
  • the side length of the rectangle may be about 3 mm to 5 mm.
  • FIG. 2 to FIG. 5 are illustrated by taking the shape of the light-transmitting display area as a rectangle as an example.
  • the shape of the transitional display region may be any one or more of the following: rectangle, polygon, circle and ellipse.
  • the shape of the sub-pixels can be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons and other polygons, and the arrangement can be It is X-shaped, cross-shaped or character-shaped, etc., which is not limited in the present disclosure.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel circuit. As shown in Figure 4, the pixel circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data signal line Data, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third The gate connection of transistor T3.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be called a switch transistor, a scan transistor, etc., and when a turn-on level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line Data to be input to the pixel circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initialization voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or released to emit light The amount of charge accumulated in the first pole of a device.
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is continuously provided with a high level. Signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the pixel circuit of the previous display row, that is, for the nth display row
  • the first scanning signal line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same signal line as the first scanning signal line S1 in the pixel circuit of the previous display row
  • the signal lines of the display substrate can be reduced, and the narrow frame of the display substrate can be realized.
  • the first transistor T1 to the seventh transistor T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E and the initial signal line INIT extend along the horizontal direction
  • the second power supply line VSS, the first power supply line VDD and The data signal line Data extends in the vertical direction.
  • FIG. 5 is a working timing diagram of a pixel circuit.
  • the pixel circuit in FIG. 4 includes 7 transistors (the first transistor T1 to the sixth transistor T7), a storage capacitor C and 7 signal Lines (data signal line Data, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), all 7 transistors are P type transistor.
  • the working process of the pixel circuit may include:
  • the first stage A1 is called the reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal, and the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals.
  • the signal line Data outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line Data is provided to the second node N2, and charge the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage of the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the first power line VDD.
  • the display substrate provided by the embodiment of the present disclosure includes: a display area and a non-display area surrounding the display area.
  • the display area includes: a plurality of scanning lines extending along the first direction and a plurality of sub-pixels arranged in an array.
  • the display area includes: a first The display area and the second display area, the first display area is located at the periphery of the second display area, the second display area includes: a light-transmitting display area and a transition display area, the transition display area is located on the side of the light-transmitting display area;
  • the light-transmitting display area It includes: m rows and n columns of sub-pixels, each sub-pixel located in the light-transmitting display area includes: a light-emitting element, the light-emitting element of each sub-pixel located in the i-th row of the light-transmitting display area and the i+1th light-emitting element located in the light-transmitting display area and the light-emitting elements of sub-pixels of the same color are electrically connected, and i is an odd number less than or equal to m;
  • the transition display area includes: m rows of n-column sub-pixels, the i-th row of sub-pixels in the light-trans
  • the pixel circuit of the sub-pixel located in the i+1th row and j-th column of the transitional display area is electrically connected to the light-emitting element of the sub-pixel located in the i+1th row and j-th column of the light-transmitting display area.
  • the pixel circuits of the i-th row and the i+1th row of sub-pixels are connected to the same scan line, which can ensure simultaneous display of the light-transmitting display area and the transitional display area, thereby improving the display effect of the display substrate.
  • FIG. 6 is a schematic structural diagram of a display substrate provided by an exemplary embodiment
  • FIG. 7 is a schematic structural diagram of a display substrate provided by another exemplary embodiment.
  • the pixel circuits of sub-pixels located in row i and row i+1 of the transitional display area are connected to the first scanning line G1 or the second scanning line G2 .
  • the first scanning line G1 is located in the same row as the i-th row of sub-pixels located in the transitional display area and is connected to the sub-pixels located in the first display area; the second scanning line G2 is connected to the sub-pixels located in the transitional display area
  • the sub-pixels in the (i+1)th row are located in the same row, and are located in the scanning line connected to the sub-pixels in the first display area.
  • FIG. 3 , FIG. 6 and FIG. 7 are illustrated by taking the pixel circuits of the i-th row and i+1th row of sub-pixels in the transitional display area connected to the first scanning line as an example for illustration.
  • the first display area may include: a plurality of sub-pixels.
  • Each sub-pixel located in the first display area may include: a pixel circuit and a light emitting element.
  • the light emitting element 11 includes: an anode, an organic light emitting layer and a cathode.
  • the organic light-emitting layer may include a stacked hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer, referred to as HTL), an electron blocking layer (Electron Block Layer) , referred to as EBL), light emitting layer (Emitting Layer, referred to as EML), hole blocking layer (Hole Block Layer, referred to as HBL), electron transport layer (Electron Transport Layer, referred to as ETL) and electron injection layer (Electron Injection Layer, referred to as EIL) ).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EML electron blocking layer
  • EML light emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels The layer can be a common layer connected together
  • the electron transport layer of all sub-pixels can be a common layer connected together
  • the hole blocking layer of all sub-pixels can be a common layer connected together
  • the light-emitting layer of adjacent sub-pixels can be a common layer connected together.
  • a pixel unit may include, or may include, red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, which are not limited in this disclosure.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically or squarely.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely. Arrangement, the disclosure is not limited here.
  • each pixel unit includes four sub-pixels, and the four sub-pixels are red sub-pixels, green sub-pixels, blue sub-pixels and green sub-pixels or blue sub-pixels, green sub-pixels, red sub-pixels, green sub-pixels pixel as an example.
  • pixel units located in the same row have the same arrangement of sub-pixels.
  • the arrangement of the sub-pixels in the pixel units in the same column may be the same or different, and the present disclosure is described by taking the pixel units in the same column as different.
  • the anode of the light-emitting element of each sub-pixel in the i-th row and k-column pixel unit of the light-transmitting display area is respectively connected to the light-emitting element located in the light-transmitting display area.
  • the anode of the light-emitting element of the sub-pixel located in the i-th row, k-column pixel unit of the light-transmitting display area and the i+1-th row, k-column pixel unit located in the light-transmitting display area The anodes of the light-emitting elements of the sub-pixels with the closest distance and the same color are electrically connected.
  • the anode of the light-emitting element of each sub-pixel in the i-th row and j-th column pixel unit in the transition display area is respectively connected to the anode of the light-emitting element in the transition display area
  • the anodes of the light-emitting elements of a sub-pixel of the same color in the i+1-th row and j-th column pixel unit are electrically connected.
  • the anode of the light-emitting element of each sub-pixel located in the i-th row and j-th column pixel unit of the transition display area is respectively connected to the i+1-th row j-th column pixel unit in the transition display area
  • the anodes of the light-emitting elements of the sub-pixels with the closest distance and the same color are electrically connected.
  • the pixel circuit of the sub-pixel located in the i+1th row and jth column of the transitional display area is connected to the i+th sub-pixel located in the light-transmitting display area.
  • the anodes of the light emitting elements of the sub-pixels in row 1 and column j are electrically connected.
  • the pixel circuit of the sub-pixel located in the first display area is electrically connected to the anode of the light emitting element.
  • the display substrate may further include: a plurality of data lines D extending along the second direction, located in row i and column j of the transitional display area.
  • the pixel circuit of the pixel is electrically connected to the first data line D1
  • the pixel circuit of the sub-pixel located in the i+1th row and jth column of the transitional display area is electrically connected to the second data line D2.
  • the first direction and the second direction intersect.
  • the first data line D1 is a data line connected to the pixel circuit of the sub-pixel in the i-th row and j-th column located in the transition display area in the same column and located in the first display area;
  • the second data line D2 is connected to the pixel circuit located in the transparent display area.
  • the sub-pixels in the i+1th row and the jth column of the light display area are located in the same column, and are located in the data line connected to the pixel circuits of the sub-pixels in the first display area.
  • the display substrate may further include: a data connection line DL, and the data connection line DL and the data line D are arranged in different layers.
  • the data connecting line is the second data line connected to the pixel circuit of the i+1th row, jth column sub-pixel located in the transitional display area and the pixel circuit of the i+1th row, jth column sub-pixel located in the transitional display area electrical connection.
  • the data connection line DL may be located on a side of the data line D close to the substrate, or may be located on a side of the data line away from the substrate.
  • the light-transmitting display region R21 includes: a first side and a second side that are oppositely arranged, and a third side that is oppositely arranged and a second side.
  • the transitional display area R22 includes: a first transitional display area R221 and a second transitional display area R222.
  • the first transitional display area R221 is located on the first side of the light-transmitting display area R21
  • the second transitional display area R222 is located on the second side of the light-transmitting display area R21
  • the first transitional display area R221 and the second transitional display area R222 are along the first direction arrangement.
  • the number of the second display area is at least one. As shown in Fig. 2, Fig. 3, Fig. 6 and Fig. 7, the number of the second display area is one for illustration.
  • FIG. 8 is a first schematic diagram of the division of the display area.
  • the first display area R10 when the number of the second display area is one, the first display area R10 includes: a first normal display area R11, a second normal display area R12, a third normal display area The display area R13 and the fourth normal display area R14.
  • the k-th row of the first normal display region R11 is the same row as the k-th row of the light-transmitting display region R21
  • the k-th row of the second normal display region R12 is the same row as the k-th row of the light-transmitting display region R21
  • k is A positive integer greater than or equal to 1 and less than or equal to m;
  • the first normal display area R11 is located on the side of the first transitional display area R221 away from the light-transmitting display area R21, and the second normal display area R12 is located on the side of the second transitional display area R222 away from the light-transmitting display area R21;
  • the third normal display The region R13 is located on the third side of the light-transmitting display region R21, and the fourth normal display region R14 is located on the fourth side of the light-transmitting display region R21; the third normal display region R13 and the fourth normal display region R14 are arranged along the second direction.
  • FIG. 9 is a second schematic diagram of division of the display area.
  • the first display area includes: a first normal display area R11, a second normal display area R12, a third The normal display area R13, the fourth normal display area R14 and Q-1 fifth normal display areas R15;
  • the kth line of the first normal display area R11 is the same line as the kth line of the light-transmitting display area R21, and the second normal display area
  • the k-th row of the region R12 is the same row as the k-th row of the light-transmitting display region R21
  • the k-th row of the fifth normal display region R15 is the same row as the k-th row of the light-transmitting display region R21
  • k is greater than or equal to 1 and less than A positive integer equal to m
  • Q is the quantity of the second display area;
  • the first normal display area R11 is located on the side of the first transitional display area R221 away from the light-transmitting display area R21, and the second normal display area R12 is located on the side of the second transitional display area R222 away from the light-transmitting display area R21;
  • the third normal display The region R13 is located on the third side of the light-transmitting display region R21, and the fourth normal display region R14 is located on the fourth side of the light-transmitting display region R21;
  • the third normal display region R13 and the fourth normal display region R14 are arranged along the second direction;
  • the i-th fifth normal display region R15 is located between the i-th second display region and the i+1-th second display region.
  • the first data line D1 may be located in the same column as the sub-pixels located in the i-th row and j-th column of the light-transmitting display area, and located in The pixel circuits of the sub-pixels in the third normal display area and the fourth normal display area are electrically connected to the pixel circuits of the sub-pixels located in row i and column j of the light-transmitting display area.
  • the second data line D2 may include: first sub-data lines and second sub-data lines that are arranged at intervals and extend along the second direction. lines, the first sub-data lines and the second sub-data lines are arranged along the second direction.
  • the first sub-data line is located in the same column as the sub-pixel located in the i+1th row and j-th column of the light-transmitting display area, and is electrically connected to the pixel circuit of the sub-pixel located in the third normal display area.
  • the second sub-data line is located in the same column as the sub-pixel located in row i+1 and column j of the light-transmitting display area, and is electrically connected to the pixel circuit of the sub-pixel located in the fourth normal display area.
  • Fig. 10 is a first schematic diagram of a plurality of scanning lines provided by an exemplary embodiment
  • Fig. 11 is a second schematic diagram of a plurality of scanning lines provided by an exemplary embodiment.
  • the first scan line G1 when there is one second display area, and the pixel circuits of sub-pixels in row i and row i+1 in the transitional display area are connected to the first scan line, the first scan line G1 includes : the first scanning part G11 and the second scanning part G12 arranged at intervals.
  • the second scanning line G2 includes: a third scanning portion G13 and a fourth scanning portion G14 arranged at intervals and extending along the first direction.
  • the first scanning part G11 is respectively connected with the pixel circuit of the i-th row of sub-pixels in the first transition display region R221, the pixel circuit of the i+1-th row of sub-pixels in the first transition display region R221, and the first normal display region R221.
  • the pixel circuits of the i-th row of sub-pixels in the region are electrically connected.
  • the second scanning part G12 is electrically connected to the pixel circuits of the i-th row and i+1th row of sub-pixels in the second transitional display region R222 and the pixel circuit of the i-th row of sub-pixels in the second normal display region R222 .
  • the third scanning part G13 is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area.
  • the fourth scanning part G14 is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second normal display area.
  • the first scanning part may include: a first connecting part G111 , a second connecting part G112 and a third connecting part G113 .
  • the first connecting portion G111 and the third connecting portion G113 extend along a first direction, and the second connecting portion G112 extends along a second direction.
  • the first connecting portion G111 is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the pixel circuit of the i-th row of sub-pixels located in the first transitional display area R221, and the second connecting portion G112;
  • the second connection portion G112 is electrically connected to the third connection portion G113;
  • the third connection portion G113 is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first transitional display region R221.
  • the first scanning part in FIG. 10 is an open loop.
  • the second scanning part G12 includes: a fourth connecting part G121, a fifth connecting part G122 and a sixth connecting part G123, and the fourth connecting part G121 and the sixth connecting part G121
  • the six connecting portions G123 extend along the first direction
  • the fifth connecting portion G122 extends along the second direction.
  • the fourth connecting portion G121 is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area, the pixel circuit of the i-th row of sub-pixels located in the second transitional display area R222, and the fifth connecting portion G122;
  • the connection part G122 is electrically connected to the sixth connection part G123, and the sixth connection part G123 is electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second transitional display region R222.
  • the second scanning part in Fig. 10 is an open loop.
  • the first scanning part G11 may further include: a seventh connecting part G114 .
  • the seventh connection portion G114 extends along the second direction. Wherein, the seventh connecting portion G114 is electrically connected to the first connecting portion G111 and the third connecting portion G113 respectively.
  • the first scanning part in FIG. 11 includes a closed loop, and the first scanning part located in the transitional display area is a closed loop.
  • the first scanning part located in the transitional display area is a closed loop, which can reduce the load of the first scanning line.
  • the second scanning part G12 may further include: an eighth connecting part G124.
  • the eighth connection portion G124 extends along the second direction.
  • the eighth connecting portion G124 is electrically connected to the fourth connecting portion G121 and the sixth connecting portion G123.
  • the second scanning part in FIG. 11 includes a closed loop, and the second scanning part located in the transitional display area is a closed loop.
  • the second scanning part located in the transitional display area is a closed loop to reduce the load of the first scanning line.
  • Figure 12 is a schematic diagram three of multiple scanning lines provided by an exemplary embodiment
  • Figure 13 is a schematic diagram four of multiple scanning lines provided by an exemplary embodiment
  • Figure 14 is a schematic diagram of multiple scanning lines provided by an exemplary embodiment Schematic diagram five of scanning lines
  • Figure 15 is a schematic diagram six of multiple scanning lines provided in an exemplary embodiment
  • Figure 16 is a schematic diagram VII of multiple scanning lines provided in an exemplary embodiment
  • Figure 17 is a schematic diagram of a plurality of scanning lines provided in an exemplary embodiment
  • the first scan line G1 may further include: a first scan connection portion GC1
  • the second scan line G2 may further include: a second scan line G2 .
  • the first scanning connection part GC1 is electrically connected to the first scanning part G11 and the second scanning part G12 respectively; the second scanning connection part GC2 is electrically connected to the third scanning part G13 and the fourth scanning part G14 respectively.
  • FIG. 12 is illustrated by taking the first scanning part and the second scanning part as an open loop, and the first scanning line includes the first scanning connection part GC1 as an example.
  • FIG. 13 is illustrated by taking the first scanning part and the second scanning part as an open loop, and the second scanning line includes the second scanning connection part GC2 as an example.
  • FIG. 14 is illustrated by taking the first scanning part and the second scanning part as an open loop, and the first scanning line includes the first scanning connecting part GC1 and the second scanning line includes the second scanning connecting part GC2.
  • FIG. 15 is illustrated by taking the example that the first scanning part and the second scanning part include closed loops, and the first scanning line includes the first scanning connection part GC1 .
  • FIG. 16 is illustrated by taking the example that the first scanning part and the second scanning part include closed loops, and the second scanning line includes the second scanning connection part GC2.
  • Fig. 17 is illustrated by taking the example that the first scanning part and the second scanning part include a closed loop, and include the first scanning connection part GC1 and the second scanning line includes the second scanning connection part GC2.
  • FIG. 18 is a first schematic diagram of a plurality of scanning lines provided by another exemplary embodiment
  • FIG. 19 is a second schematic diagram of a plurality of scanning lines provided by another exemplary embodiment.
  • the second scan line G2 when there is one second display area, and the pixel circuits of sub-pixels in row i and row i+1 in the transitional display area are connected to the second scan line, the second scan line G2 includes : the first scanning part G21 and the second scanning part G22 arranged at intervals.
  • the first scanning line G1 includes: a third scanning portion G23 and a fourth scanning portion G24 arranged at intervals and extending along the first direction.
  • the first scanning part G21 can respectively communicate with the pixel circuits of the i-th row and the i+1th row of sub-pixels in the first transitional display region R221, and the i-th row of sub-pixels in the first normal display region R221.
  • the pixel circuits of the +1 row of sub-pixels are electrically connected.
  • the second scanning part G22 can respectively communicate with the pixel circuits of the i-th row and the i+1th row of sub-pixels in the second transitional display region R222 and the i+th row of sub-pixels in the second normal display region R222.
  • the pixel circuits of one row of sub-pixels are electrically connected.
  • the third scanning part G23 may be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area.
  • the fourth scanning part G24 may be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area.
  • the first scanning part G21 may include: a first connecting part G211 , a second connecting part G212 and a third connecting part G213 .
  • the first connecting portion G211 and the third connecting portion G213 extend along the first direction
  • the second connecting portion G212 extends along the second direction.
  • the first connecting portion G211 can be respectively connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area and the i+1th row of sub-pixels located in the first transitional display area R221
  • the pixel circuit is electrically connected to the second connection part G212.
  • the second connection part G212 may be electrically connected to the third connection part G213.
  • the third connection portion G213 may be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first transitional display region R221.
  • the first scanning section in FIG. 18 is an open loop.
  • the second scanning part G22 may include: a fourth connecting part G221 , a fifth connecting part G222 and a sixth connecting part G223 .
  • the fourth connecting portion G221 and the sixth connecting portion G223 extend along the first direction
  • the fifth connecting portion G222 extends along the second direction.
  • the fourth connecting portion G221 is respectively connected to the pixel circuit of the i+1th row of sub-pixels located in the second normal display area and the i+1th row of sub-pixels located in the second transitional display area R222.
  • the pixel circuit is electrically connected to the fifth connection portion; the fifth connection portion G222 is electrically connected to the sixth connection portion G223; the sixth connection portion G223 is electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second transition display region R222.
  • the second scanning section in FIG. 18 is an open loop.
  • the first scanning part G21 may further include: a seventh connecting part G214 extending along the second direction.
  • the seventh connecting portion G214 is electrically connected to the first connecting portion G211 and the third connecting portion G213 respectively.
  • the first scanning part in FIG. 19 includes a closed loop, and the first scanning part located in the transitional display area is a closed loop.
  • the first scanning part located in the transitional display area is a closed loop, which can reduce the load of the first scanning line.
  • the second scanning part G22 may further include: an eighth connecting part G224 extending along the second direction.
  • the eighth connecting portion G224 is electrically connected to the fourth connecting portion G221 and the sixth connecting portion G223 respectively.
  • the second scanning part in FIG. 19 includes a closed loop, and the second scanning part located in the transitional display area is a closed loop.
  • the second scanning part located in the transitional display area is a closed loop to reduce the load of the first scanning line.
  • Fig. 20 is a third schematic diagram of multiple scanning lines provided by another exemplary embodiment
  • Fig. 21 is a fourth schematic diagram of multiple scanning lines provided by another exemplary embodiment
  • Fig. 22 is a schematic diagram of multiple scanning lines provided by another exemplary embodiment Schematic diagram five of scanning lines
  • FIG. 23 is a schematic diagram six of multiple scanning lines provided by another exemplary embodiment
  • FIG. 24 is a schematic diagram VII of multiple scanning lines provided by another exemplary embodiment
  • FIG. 25 is another schematic diagram of multiple scanning lines
  • the first scan line G1 may further include: a first scan connection portion GC1
  • the second scan line G2 may further include: a second scan line G2 .
  • the first scanning connection part GC1 is electrically connected to the first scanning part G11 and the second scanning part G12 respectively; the second scanning connection part GC2 is respectively connected to the third scanning part G13 and the fourth scanning part G14 electrical connection.
  • FIG. 20 is illustrated by taking the first scanning part and the second scanning part as an open loop, and the first scanning line includes the first scanning connection part GC1 as an example.
  • FIG. 21 is illustrated by taking the first scanning part and the second scanning part as an open loop, and the second scanning line includes the second scanning connection part GC2 as an example.
  • Fig. 22 takes the first scanning part and the second scanning part as an open loop, and the first scanning line includes the first scanning connection part GC1 and the second scanning line includes the second scanning connection part GC2 for illustration.
  • FIG. 20 is illustrated by taking the first scanning part and the second scanning part as an open loop, and the first scanning line includes the first scanning connection part GC1 as an example.
  • FIG. 21 is illustrated by taking the first scanning part and the second scanning part as an open loop,
  • FIG. 23 is illustrated by taking the example that the first scanning part and the second scanning part include closed loops, and the first scanning line includes the first scanning connection part GC1 .
  • FIG. 24 is illustrated by taking the example that the first scanning part and the second scanning part include closed loops, and the second scanning line includes the second scanning connection part GC2.
  • FIG. 25 is illustrated by taking an example in which the first scanning part and the second scanning part include closed loops, and the first scanning line includes the first scanning connection part GC1 and the second scanning line includes the second scanning connection part GC2 .
  • the driving mode of the scan lines can be determined according to the load of the scan lines and the space of the display substrate.
  • the first scanning line G1 adopts double-sided driving
  • the second scanning line can adopt double-sided driving, except for the first scanning line and the second scanning line.
  • the scanning lines G other than the two scanning lines may adopt double-sided driving or may adopt single-sided driving.
  • the first scan line G1 can be driven by single side or double side, and the second scan line can be driven by double side.
  • the scanning lines G other than the scanning line and the second scanning line may adopt double-sided driving or may adopt single-sided driving.
  • the first scan line G1 can be driven by double-side area
  • the second scan line can be driven by single-side area or double-side area.
  • the scanning lines G other than the scanning line and the second scanning line may adopt double-sided driving or may adopt single-sided driving.
  • all scan lines can be driven by double sides or driven by single sides.
  • the scanning line is driven by double sides to reduce the load on the scanning line.
  • the use of a single side area for the scan line can realize a narrow border of the display substrate.
  • FIG. 26 is a first schematic diagram of multiple scanning lines provided by yet another exemplary embodiment
  • FIG. 27 is a second schematic diagram of multiple scanning lines provided by yet another exemplary embodiment.
  • the first scanning line G1 can be respectively connected with the pixel circuit of the i-th row of sub-pixels in the first normal display area, and the i-th row of sub-pixels in the first transitional display area R221 and the second transitional display area R222 of all the second display areas.
  • the pixel circuits of the i+1th row of sub-pixels located in the first transitional display area and the second transitional display area R221 of all the second display area R221, the pixel circuit of the i-th row of sub-pixels of all the fifth normal display area and The pixel circuits of the i-th row of sub-pixels located in the second normal display area are electrically connected.
  • the second scanning line can be respectively connected with the pixel circuit of the i+1th row of sub-pixels in the first normal display area, the pixel circuit of the i+1th row of sub-pixels in the second normal display area, and all the pixel circuits in the fifth normal display area.
  • the pixel circuits of the i+1th row of sub-pixels are electrically connected.
  • the first scanning line may include: a first scanning part G31, Q-1 second scanning parts G32, a third scanning part G33, and Qth scanning parts G33.
  • a scan connector G34 the first scanning part G31 can respectively communicate with the pixel circuit of the i-th row of sub-pixels located in the first normal display area, the i-th row and the i+1th row of the first transitional display area R221 located in the first second display area The pixel circuits of the row of sub-pixels are electrically connected.
  • the t-th second scanning part G32 is respectively connected with the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area, the i-th row and the i+1-th row of the t-th second transition display area in the t-th second display area
  • the pixel circuits of the row sub-pixels are electrically connected to the pixel circuits of the i-th row and i+1-th row sub-pixels in the first transition display area of the t+1th second display area, and t is a positive integer smaller than Q.
  • the third scanning part G33 is respectively connected with the pixel circuits of the i-th row and the i+1th row of sub-pixels in the second transitional display region R222 of the Q-th second display region and the i-th row of sub-pixels in the second normal display region.
  • the pixel circuits are electrically connected.
  • the first first scanning connection part G34 can be electrically connected to the first scanning part G31 and the first second scanning part G32 respectively, and the tth first scanning connection part G34 can be respectively connected to the t-1th second scanning part
  • the G32 is electrically connected to the t-th second scanning unit G32; the Q-th first scanning connection unit G34 may be electrically connected to the Q-1-th second scanning unit G32 and the third scanning unit G33 respectively.
  • the first scanning part, the second scanning part and the third scanning part may be open loops or include closed loops.
  • the first scanning part located in the transitional display area is a closed loop.
  • the second scanning part includes a closed loop the second scanning part located in the transitional display area is a closed loop.
  • the third scanning part located in the transitional display area is a closed loop.
  • FIG. 26 is illustrated by taking the first scanning part, the second scanning part and the third scanning part as an open loop as an example.
  • FIG. 27 is illustrated by taking the first scanning part, the second scanning part and the third scanning part including a closed loop as an example.
  • the first scanning part, the second scanning part and the third scanning part located in the transitional display area are closed loops to reduce the load on the first scanning line.
  • the second scanning line may include: a fourth scanning part G41, Q-1 fifth scanning parts G42 and sixth scanning parts G43, Qth scanning parts Two scan the connection part G44.
  • the fourth scanning part G41 may be electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the first normal display area.
  • the t-th fifth scanning part G42 may be electrically connected to the pixel circuit of the i+1-th row of sub-pixels in the t-th fifth normal display area.
  • the sixth scanning part G43 may be electrically connected to the pixel circuit of the i+1th row of sub-pixels located in the second first display area.
  • the first second scanning connection part G44 can be electrically connected to the first scanning part G41 and the first second scanning part G42 respectively, and the tth second scanning connection part G44 can be respectively connected to the t-1th second scanning part G42 is electrically connected to the t-th second scanning part G42; the Q-th second scanning connection part G44 can be electrically connected to the Q-1-th second scanning part G42 and the third scanning part G43 respectively.
  • FIG. 28 is a third schematic diagram of multiple scanning lines provided by yet another exemplary embodiment
  • FIG. 29 is a fourth schematic diagram of multiple scanning lines provided by yet another exemplary embodiment.
  • the first The scan line G1 can be respectively connected with the pixel circuit of the i-th row of sub-pixels in the first normal display area, the i-th row of sub-pixels in the second normal display area, and the i-th row of sub-pixels in all the fifth normal display areas.
  • the pixel circuits of the pixels are electrically connected.
  • the second scanning line G2 can be respectively connected with the pixel circuit of the i+1th row of sub-pixels located in the first normal display area, and the i-th row of the first transitional display area R21 and the second transitional display area R222 of all the second display areas. It is electrically connected to the pixel circuit of the i+1th row of sub-pixels, the pixel circuits of the i+1th row of sub-pixels in the fifth normal display area, and the pixel circuits of the i+1th row of sub-pixels in the second normal display area.
  • the second scanning line may include: a first scanning part G31, Q-1 second scanning parts G32, a third scanning part G33, and Qth scanning parts G33.
  • a scan connector G34 the first scanning part G31 can be respectively connected with the pixel circuit of the i+1th row of sub-pixels located in the first normal display area and the i-th row and i+th row of the first transitional display area located in the first second display area.
  • the pixel circuits of one row of sub-pixels are electrically connected.
  • the tth second scanning part G32 can be respectively connected with the pixel circuit of the i+1th row of sub-pixels in the tth fifth normal display area, the ith row and the ith row of the tth second transitional display area in the tth second display area.
  • the pixel circuits of the i+1 row of sub-pixels are electrically connected to the pixel circuits of the i-th row and i+1-th row of sub-pixels in the first transition display area of the t+1-th second display area.
  • the third scanning part G33 is respectively connected with the pixel circuits of the i-th row and the i+1th row of sub-pixels in the second transitional display area of the Q-th second display area and the i+1th row of sub-pixels in the second normal display area.
  • the pixel circuit is electrically connected.
  • the first first scanning connection part G34 is electrically connected to the first scanning part G31 and the first second scanning part G32 respectively, and the tth second scanning connection part G34 can be connected to the t-1th second scanning part G32 respectively. It is electrically connected to the t-th second scanning unit G32; the Q-th second scanning connection unit G34 can be electrically connected to the Q-1-th second scanning unit G32 and the third scanning unit G33 respectively.
  • the first scanning part, the second scanning part and the third scanning part may be open loops, or may include closed loops.
  • the first scanning part located in the transitional display area is a closed loop.
  • the second scanning part includes a closed loop
  • the second scanning part located in the transitional display area is a closed loop.
  • the third scanning part located in the transitional display area is a closed loop.
  • the first scanning part, the second scanning part and the third scanning part include a closed loop to reduce the load on the first scanning line.
  • FIG. 28 is illustrated by taking the first scanning part, the second scanning part and the third scanning part as an open loop as an example.
  • FIG. 29 illustrates an example in which the first scanning unit, the second scanning unit and the third scanning unit include closed loops.
  • the first scanning part, the second scanning part and the third scanning part located in the transitional display area are closed loops to reduce the load of the second scanning line.
  • the first scan line may include: a fourth scan part G41, Q-1 fifth scan parts G42, a sixth scan part G43, and Q-th scan parts G43.
  • the fourth scanning part G41 may be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the first normal display area.
  • the t-th fifth scanning part G42 may be electrically connected to the pixel circuit of the i-th row of sub-pixels in the t-th fifth normal display area.
  • the sixth scanning part G43 may be electrically connected to the pixel circuit of the i-th row of sub-pixels located in the second normal display area.
  • the first second scanning connection part G44 is electrically connected to the first scanning part G41 and the first second scanning part G42 respectively, and the tth second scanning connection part G44 is respectively connected to the t-1th second scanning part G42 and the first second scanning part G42.
  • the t-th second scanning unit G42 is electrically connected; the Q-th second scanning connection unit G44 is electrically connected to the Q-1-th second scanning unit G42 and the third scanning unit G43 respectively.
  • the scanning lines in the display substrate can be driven by single side or double side.
  • the display effect of the display substrate can be improved.
  • FIG. 10 to FIG. 29 are illustrated by taking an example in which the light-transmitting display area includes four rows and four columns of pixel units. Wherein, each pixel unit includes: at least three sub-pixels of different colors. The present disclosure is not limited thereto.
  • the orthographic projection of the first scan line on the substrate and the orthographic projection of the second scan line on the substrate may have an overlapping area, or there may not be an overlapping area, according to the first scanning line and
  • the structure of the second scan line is determined, which is not limited in this disclosure.
  • the first scan line and the second scan line are on the same layer set up.
  • the first scan line may include: The first non-overlapping part and the first overlapping part, the first non-overlapping part and the second scanning line are arranged on the same layer, the first overlapping part can be arranged on the side of the second scanning line close to the substrate, or can be arranged on the side of the second scanning line The side of the wire away from the substrate.
  • the first non-overlapping part is a part where the first scanning line does not overlap with the second scanning line
  • the first overlapping part is a part where the first scanning line overlaps with the second scanning line.
  • the second scan line may include: The second non-overlapping part and the second overlapping part, the second non-overlapping part is set on the same layer as the first scanning line, the second overlapping part can be set on the side of the first scanning line close to the substrate, or can be set on the side of the first scanning line The side of the wire away from the substrate.
  • the second non-overlapping part is a part where the second scanning line does not overlap with the first scanning line
  • the second overlapping part is a part where the second scanning line overlaps with the first scanning line.
  • Fig. 30 is a timing diagram of some signals provided by an exemplary embodiment
  • Fig. 31 is a timing diagram of some signals provided by another exemplary embodiment.
  • Figure 30 is an example of the electrical connection between the pixel circuits of the i-th row and the i+1-th row of the transitional display area and the first scanning line.
  • the pixel circuits of the sub-pixels in the +1 row are electrically connected to the second scanning line as an example for illustration.
  • GR1 in Figure 30 and Figure 31 is the scanning signal connected to the pixel circuit connected to the sub-pixels in the i-th row and i+1-th row in the transparent display area
  • GR2 is the i-th row and i+1-th row in the transitional display area
  • the scan signal connected to the pixel circuit connected to the sub-pixel in the transition display area, GR_1 is the same row as the i-th row in the transition display area, and the scan signal of the scan line connected to the pixel circuit of the sub-pixel located in the first display area
  • GR_2 is the scan signal connected to the pixel circuit of the sub-pixel in the first display area
  • D is the data signal of the data line.
  • GR1 and GR2 are the same as GR_1 .
  • GR1 and GR2 are the same as GR_1 .
  • An embodiment of the present disclosure also provides a display device, which may include: a display substrate.
  • the display substrate is the display substrate provided by any one of the above-mentioned embodiments, and the realization principle and the realization effect are similar, and will not be repeated here.
  • the display device may further include: functional components located in the light-transmitting display area and on the non-light-emitting side of the display device. External ambient light can enter the functional component through the light-transmitting display area.
  • the functional components may include a camera module (for example, a front camera module), a 3D structured light module (for example, a 3D structured light sensor), a time-of-flight 3D imaging module (for example, time-of-flight sensor), an infrared sensing module (for example, an infrared sensing sensor) and the like.
  • a camera module for example, a front camera module
  • a 3D structured light module for example, a 3D structured light sensor
  • a time-of-flight 3D imaging module for example, time-of-flight sensor
  • an infrared sensing module for example, an infrared sensing sensor
  • the front camera module is usually activated when the user takes a selfie or makes a video call, and the display area of the display device displays the image obtained by the selfie for the user to watch.
  • the front camera module includes, for example, a lens, an image sensor, an image processing chip, and the like.
  • the optical image generated by the scene through the lens is projected onto the surface of the image sensor (the image sensor includes CCD and CMOS) and converted into an electrical signal, which is converted into a digital image signal by the image processing chip and then sent to the processor for processing.
  • An image of the scene is output on the display screen.
  • a 3D structured light sensor and a time of flight (Time of Flight, ToF) sensor may be used for face recognition to unlock a display device and the like.
  • the functional component may only include a camera module to realize the function of selfie or video call; for example, the functional component may also include a 3D structured light module or a time-of-flight 3D imaging module to realize face recognition and unlocking, etc., the present disclosure Including but not limited to this.
  • the display device provided by the embodiments of the present disclosure can display images in the light-transmitting display area, so as to maintain the display integrity of the entire display device.

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Abstract

一种显示基板和显示装置，其中，显示基板包括：显示区(R10)和包围显示区的非显示区，显示区(R10)包括：多条沿第一方向延伸的扫描线(G)和阵列排布的多个子像素(P)，显示区(R10)包括：第一显示区(R10)和第二显示区(R20)，第一显示区(R10)位于第二显示区(R20)的外围，第二显示区(R20)包括：透光显示区(R21)和过渡显示区(R22)，过渡显示区(R22)位于透光显示区(R21)的侧面；透光显示区(R21)包括：m行n列子像素(P)，过渡显示区(R22)包括：m行n列子像素(P)，透光显示区(R21)的第i行子像素(P)和过渡显示区(R22)的第i行子像素(P)位于同一行；位于过渡显示区(R22)的每个子像素(P)包括：像素电路(10)和发光元件(11)，位于过渡显示区(R22)的第i行和第i+1行子像素(P)的像素电路(10)连接同一扫描线(G)。

Description

一种显示基板和显示装置
本申请要求于2021年6月24日提交中国专利局、申请号为202110705468.0、发明名称为“一种显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，特别涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
目前，全面屏手机的概念已在手机市场受到广泛的关注，也是未来手机的发展方向。这种全面屏手机中，可以将摄像头隐藏起来以使正面可视区域几乎全是屏幕，从而使用户得到较佳的显示效果。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：显示区和包围所述显示区的非显示区，所述显示区包括：多条沿第一方向延伸的扫描线和阵列排布的多个子像素，所述显示区包括：第一显示区和第二显示区，所述第一显示区位于所述第二显示区的外围，所述第二显示区包括：透光显示区和过渡显 示区，所述过渡显示区位于所述透光显示区的侧面；
所述透光显示区包括：m行n列子像素，位于透光显示区的每个子像素包括：发光元件，位于透光显示区的第i行中的每个子像素的发光元件与位于透光显示区的第i+1行，且同一颜色的子像素的发光元件电连接，i为小于或者等于m的奇数；
所述过渡显示区包括：m行n列子像素，所述透光显示区的第i行子像素和所述过渡显示区的第i行子像素位于同一行；位于过渡显示区的每个子像素包括：像素电路和发光元件，位于过渡显示区的第i行中的每个子像素的发光元件与位于过渡显示区的第i+1行，且同一颜色的子像素的发光元件电连接；位于过渡显示区的第i行子像素的像素电路和发光元件电连接，位于过渡显示区的第i+1行第j列的子像素的像素电路与位于透光显示区的第i+1行第j列的子像素的发光元件电连接，j为小于或者等于n的正整数；
位于过渡显示区的第i行和第i+1行子像素的像素电路连接同一扫描线。
在一些可能的实现方式中，位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线或者第二扫描线；
其中，所述第一扫描线为与位于过渡显示区的第i行子像素位于同一行，且位于第一显示区的子像素所连接的扫描线；所述第二扫描线为与位于过渡显示区的第i+1行子像素位于同一行，且位于第一显示区的子像素所连接的扫描线。
在一些可能的实现方式中，所述第一显示区包括：多个子像素，位于第一显示区的每个子像素包括：像素电路和发光元件；位于同一行的至少三个子像素构成一个像素单元；所述发光元件包括：阳极、有机发光层和阴极；
位于透光显示区的第i行第k列像素单元中的每个子像素的发光元件的阳极分别与位于透光显示区的第i+1行第k列像素单元中的一个相同颜色的子像素的发光元件的阳极电连接，k为小于或者等于K的正整数，K＝n/3或者n/4；
位于过渡显示区的第i行第j列像素单元中的每个子像素的发光元件的阳极分别与位于过渡显示区的第i+1行第j列像素单元中的一个相同颜色的 子像素的发光元件的阳极电连接；
位于过渡显示区的第i+1行第j列的子像素的像素电路与位于透光显示区的第i+1行第j列的子像素的发光元件的阳极电连接；
位于第一显示区的子像素的像素电路和发光元件的阳极电连接。
在一些可能的实现方式中，所述显示基板还包括：多条沿第二方向延伸的数据线，位于过渡显示区的第i行第j列子像素的像素电路与第一数据线电连接，位于过渡显示区的第i+1行第j列子像素的像素电路与第二数据线电连接，所述第一方向和所述第二方向相交；
其中，所述第一数据线为与位于过渡显示区的第i行第j列子像素位于同一列，且位于第一显示区的子像素的像素电路所连接的数据线；所述第二数据线为与位于透光显示区的第i+1行第j列的子像素位于同一列，且位于第一显示区的子像素的像素电路所连接的数据线。
在一些可能的实现方式中，还包括：数据连接线，所述数据连接线与数据线异层设置；
所述数据连接线，分别与位于过渡显示区的第i+1行第j列子像素的像素电路和位于过渡显示区的第i+1行第j列子像素的像素电路所连接的第二数据线电连接。
在一些可能的实现方式中，所述透光显示区包括：相对设置的第一侧和第二侧以及相对设置的第三侧和第四侧；所述过渡显示区包括：第一过渡显示区和第二过渡显示区；
所述第一过渡显示区位于所述透光显示区的第一侧，所述第二过渡显示区位于透光显示区的第二侧，所述第一过渡显示区和所述第二过渡显示区沿第一方向排布。
在一些可能的实现方式中，所述第二显示区的数量为至少一个。
在一些可能的实现方式中，当第二显示区的数量为一个时，所述第一显示区包括：第一正常显示区、第二正常显示区、第三正常显示区和第四正常显示区；
第一正常显示区的第k行与透光显示区的第k行为同一行，第二正常显 示区的第k行与透光显示区的第k行为同一行，k为大于等于1，且小于等于m的正整数；
所述第一正常显示区位于所述第一过渡显示区远离所述透光显示区的一侧，所述第二正常显示区位于所述第二过渡显示区远离所述透光显示区的一侧；所述第三正常显示区位于所述透光显示区的第三侧，所述第四正常显示区位于所述透光显示区的第四侧；所述第三正常显示区和所述第四正常显示区沿第二方向排布。
在一些可能的实现方式中，当位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线时，所述第一扫描线包括：间隔设置的第一扫描部和第二扫描部；所述第二扫描线包括：间隔设置，且沿第一方向延伸的第三扫描部和第四扫描部；
所述第一扫描部分别与位于第一过渡显示区的第i行和第i+1行子像素的像素电路以及位于第一正常显示区的第i行子像素的像素电路电连接；
所述第二扫描部分别与位于第二过渡显示区的第i行和第i+1行子像素的像素电路以及位于第二正常显示区的第i行子像素的像素电路电连接；
所述第三扫描部与位于第一正常显示区的第i+1行子像素的像素电路电连接；
所述第四扫描部与位于第二正常显示区的第i+1行子像素的像素电路电连接。
在一些可能的实现方式中，所述第一扫描部包括：第一连接部、第二连接部和第三连接部，第一连接部和第三连接部沿第一方向延伸，第二连接部沿第二方向延伸；
第一连接部分别与位于第一正常显示区的第i行子像素的像素电路、位于第一过渡显示区的第i行子像素的像素电路和第二连接部电连接；第二连接部与第三连接部电连接；第三连接部与位于第一过渡显示区的第i+1行子像素的像素电路电连接；
所述第二扫描部包括：第四连接部、第五连接部和第六连接部，第四连接部和第六连接部沿第一方向延伸，第五连接部沿第二方向延伸；
第四连接部分别与位于第二正常显示区的第i行子像素的像素电路、位于第二过渡显示区的第i行子像素的像素电路和第五连接部电连接；第五连接部与第六连接部电连接；第六连接部与位于第二过渡显示区的第i+1行子像素的像素电路电连接。
在一些可能的实现方式中，所述第一扫描部还包括：沿第二方向延伸的第七连接部，第七连接部，分别与第一连接部和第三连接部电连接；
所述第二扫描部还包括：沿第二方向延伸的第八连接部，第八连接部，分别与第四连接部和第六连接部电连接。
在一些可能的实现方式中，所述第一扫描线还包括：第一扫描连接部；
所述第一扫描连接部分别与第一扫描部和第二扫描部电连接。
在一些可能的实现方式中，所述第二扫描线还包括：第二扫描部；
所述第二扫描连接部分别与第三扫描部和第四扫描部电连接
在一些可能的实现方式中，当位于过渡显示区的第i行和第i+1行子像素的像素电路连接第二扫描线时，所述第二扫描线包括：间隔设置的第一扫描部和第二扫描部；所述第一扫描线包括：间隔设置，且沿第一方向延伸的第三扫描部和第四扫描部；
所述第一扫描部分别与位于第一过渡显示区的第i行和第i+1行子像素的像素电路以及位于第一正常显示区的第i+1行子像素的像素电路电连接；
所述第二扫描部分别与位于第二过渡显示区的第i行和第i+1行子像素的像素电路以及位于第二正常显示区的第i+1行子像素的像素电路电连接；
所述第三扫描部与位于第一正常显示区的第i行子像素的像素电路电连接；
所述第四扫描部与位于第二正常显示区的第i行子像素的像素电路电连接。
在一些可能的实现方式中，所述第一扫描部包括：第一连接部、第二连接部和第三连接部，第一连接部和第三连接部沿第一方向延伸，第二连接部沿第二方向延伸；第一连接部分别与位于第一正常显示区的第i+1行子像素的像素电路、位于第一过渡显示区的第i+1行子像素的像素电路和第二连接 部电连接；第二连接部与第三连接部电连接；第三连接部与位于第一过渡显示区的第i行子像素的像素电路电连接；
所述第二扫描部包括：第四连接部、第五连接部和第六连接部，第四连接部和第六连接部沿第一方向延伸，第五连接部沿第二方向延伸；第四连接部分别与位于第二正常显示区的第i+1行子像素的像素电路、位于第二过渡显示区的第i+1行子像素的像素电路和第五连接部电连接；第五连接部与第六连接部电连接；第六连接部与位于第二过渡显示区的第i行子像素的像素电路电连接。
在一些可能的实现方式中，所述第一扫描部还包括：沿第二方向延伸的第七连接部，第七连接部分别与第一连接部和第三连接部电连接；
所述第二扫描部还包括：沿第二方向延伸的第八连接部，第八连接部分别与第四连接部和第六连接部电连接。
在一些可能的实现方式中，所述第二扫描线还包括：第一扫描连接部；
所述第一扫描连接部分别与第一扫描部和第二扫描部电连接。
在一些可能的实现方式中，所述第一扫描线还包括：第二扫描连接部；
所述第二扫描连接部分别与第三扫描部和第四扫描部电连接。
在一些可能的实现方式中，当第二显示区的数量为至少两个时，所述第一显示区包括：第一正常显示区、第二正常显示区、第三正常显示区、第四正常显示区和Q-1个第五正常显示区；第一正常显示区的第k行与透光显示区的第k行为同一行,第二正常显示区的第k行与透光显示区的第k行为同一行，第五正常显示区的第k行与透光显示区的第k行为同一行，k为大于等于1，且小于等于m的正整数，Q为第二显示区的数量；
第一正常显示区位于第一过渡显示区远离透光显示区的一侧，第二正常显示区位于第二过渡显示区远离透光显示区的一侧；第三正常显示区位于透光显示区的第三侧，第四正常显示区位于透光显示区的第四侧；第三正常显示区和第四正常显示区沿第二方向排布；第i个第五正常显示区位于第i个第二显示区和第i+1个第二显示区之间。
在一些可能的实现方式中，当位于过渡显示区的第i行和第i+1行子像 素的像素电路连接第一扫描线时，
所述第一扫描线分别与位于第一正常显示区的第i行子像素的像素电路、位于所有第二显示区的第一过渡显示区和第二过渡显示区的第i行子像素的像素电路、位于所有第二显示区的第一过渡显示区和第二过渡显示区的第i+1行子像素的像素电路、所有第五正常显示区的第i行子像素的像素电路以及位于第二正常显示区的第i行子像素的像素电路电连接；
所述第二扫描线分别与位于第一正常显示区的第i+1行子像素的像素电路、位于第二正常显示区的第i+1行子像素的像素电路和位于所有第五正常显示区的第i+1行子像素的像素电路电连接；
所述第一扫描线包括：第一扫描部、Q-1个第二扫描部和第三扫描部、Q个第一扫描连接部；
第一扫描部分别与位于第一正常显示区的第i行子像素的像素电路、位于第一个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接；
第t个第二扫描部分别与第t个第五正常显示区的第i行子像素的像素电路、第t个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路和第t+1个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接，t为小于Q的正整数；
第三扫描部分别与位于第Q个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路以及第二正常显示区的第i行子像素的像素电路电连接；
第一个第一扫描连接部分别与第一扫描部和第一个第二扫描部电连接，第t个第一扫描连接部分别与第t-1个第二扫描部和第t个第二扫描部电连接；第Q个第一扫描连接部分别与第Q-1个第二扫描部和第三扫描部电连接；
所述第二扫描线包括：第四扫描部、Q-1个第五扫描部和第六扫描部、Q个第二扫描连接部；
第四扫描部与位于第一正常显示区的第i+1行子像素的像素电路电连接；
第t个第五扫描部与第t个第五正常显示区的第i+1行子像素的像素电路 电连接；
第六扫描部与位于第二第一显示区的第i+1行子像素的像素电路电连接；
第一个第二扫描连接部分别与第一扫描部和第一个第二扫描部电连接，第t个第二扫描连接部分别与第t-1个第二扫描部和第t个第二扫描部电连接；第Q个第二扫描连接部分别与第Q-1个第二扫描部和第三扫描部电连接。
在一些可能的实现方式中，当位于过渡显示区的第i行和第i+1行子像素的像素电路连接第二扫描线时，
所述第一扫描线分别与位于第一正常显示区的第i行子像素的像素电路、位于第二正常显示区的第i行子像素的像素电路和位于所有第五正常显示区的第i行子像素的像素电路电连接；
所述第二扫描线分别与位于第一正常显示区的第i+1行子像素的像素电路、位于所有第二显示区的第一过渡显示区和第二过渡显示区的第i行和第i+1行子像素的像素电路、所有第五正常显示区的第i+1行子像素的像素电路以及位于第二正常显示区的第i+1行子像素的像素电路电连接；
所述第二扫描线包括：第一扫描部、Q-1个第二扫描部和第三扫描部、Q个第一扫描连接部；
第一扫描部分别与位于第一正常显示区的第i+1行子像素的像素电路和位于第一个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接；
第t个第二扫描部分别与第t个第五正常显示区的第i+1行子像素的像素电路、第t个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路以及第t+1个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接；
第三扫描部分别与位于第Q个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路和第二正常显示区的第i+1行子像素的像素电路电连接；
第一个第一扫描连接部分别与第一扫描部和第一个第二扫描部电连接，第t个第二扫描连接部分别与第t-1个第二扫描部和第t个第二扫描部电连接； 第Q个第二扫描连接部分别与第Q-1个第二扫描部和第三扫描部电连接；
第一扫描线包括：第四扫描部、Q-1个第五扫描部、第六扫描部和Q个第二扫描连接部；
第四扫描部与位于第一正常显示区的第i行子像素的像素电路电连接；
第t个第五扫描部与第t个第五正常显示区的第i行子像素的像素电路电连接；
第六扫描部与位于第二正常显示区的第i行子像素的像素电路电连接；
第一个第二扫描连接部分别与第一扫描部和第一个第二扫描部电连接，第t个第二扫描连接部分别与第t-1个第二扫描部和第t个第二扫描部电连接；第Q个第二扫描连接部分别与第Q-1个第二扫描部和第三扫描部电连接。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示基板的结构示意图；
图2为一种示例性实施例提供的显示基板的显示区的平面结构示意图；
图3为本公开实施例提供的显示基板的结构示意图；
图4为一种像素电路的等效电路示意图；
图5为一种像素电路的工作时序图；
图6为一种示例性实施例提供的显示基板的结构示意图一；
图7为另一示例性实施例提供的显示基板的结构示意图；
图8为显示区的划分示意图一；
图9为显示区的划分示意图二；
图10为一种示例性实施例提供的多条扫描线的示意图一；
图11为一种示例性实施例提供的多条扫描线的示意图二；
图12为一种示例性实施例提供的多条扫描线的示意图三；
图13为一种示例性实施例提供的多条扫描线的示意图四；
图14为一种示例性实施例提供的多条扫描线的示意图五；
图15为一种示例性实施例提供的多条扫描线的示意图六；
图16为一种示例性实施例提供的多条扫描线的示意图七；
图17为一种示例性实施例提供的多条扫描线的示意图八；
图18为另一示例性实施例提供的多条扫描线的示意图一；
图19为另一示例性实施例提供的多条扫描线的示意图二；
图20为另一示例性实施例提供的多条扫描线的示意图三；
图21为另一示例性实施例提供的多条扫描线的示意图四；
图22为另一示例性实施例提供的多条扫描线的示意图五；
图23为另一示例性实施例提供的多条扫描线的示意图六；
图24为另一示例性实施例提供的多条扫描线的示意图七；
图25为另一示例性实施例提供的多条扫描线的示意图八；
图26为又一示例性实施例提供的多条扫描线的示意图一；
图27为又一示例性实施例提供的多条扫描线的示意图二；
图28为又一示例性实施例提供的多条扫描线的示意图三；
图29为又一示例性实施例提供的多条扫描线的示意图四；
图30为一种示例性实施例提供的部分信号的时序图；
图31为另一示例性实施例提供的部分信号的时序图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实 施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的 区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示基板的结构示意图。如图1所示，显示基板可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)、多个发光信号线(E1到Eo)和多个子像素Pxij。在一种示例性实施例中中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施 加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素Pxij。每个子像素Pxij可以连接到对应的数据信号线、对应的扫描信号线和对应的发光信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
全面屏显示产品包括：用于设置光学器件的透光显示区和位于透光显示区侧面的过渡显示区。一种全面屏显示产品中的透光显示区和过渡显示区不同时显示，影响了显示产品的显示效果。
图2为一种示例性实施例提供的显示基板的显示区的平面结构示意图，图3为本公开实施例提供的显示基板的结构示意图。如图2和图3所示，本公开实施例提供的显示基板包括：显示区R10和包围显示区的非显示区，显示区包括：多条沿第一方向延伸的扫描线G和阵列排布的多个子像素P，显示区包括：第一显示区R10和第二显示区R20，第一显示区R10位于第二显示区R20的外围，第二显示区R20包括：透光显示区R21和过渡显示区R22，过渡显示区R22位于透光显示区R21的侧面。
如图3所示，在一种示例性实施例中，透光显示区包括：m行n列子像素P，位于透光显示区的每个子像素包括：发光元件11。位于透光显示区的第i行中的每个子像素的发光元件11与位于透光显示区的第i+1行，且同一 颜色的子像素的发光元件11电连接，i为小于或者等于m的奇数。其中，位于透光显示区的每个子像素不包括像素电路。
如图3所示，过渡显示区包括：m行n列子像素，透光显示区的第i行子像素和过渡显示区的第i行子像素位于同一行；位于过渡显示区的每个子像素包括：像素电路10和发光元件11，位于过渡显示区的第i行中的每个子像素的发光元件与位于过渡显示区的第i+1行，且同一颜色的子像素的发光元件电连接。
如图3所示，位于过渡显示区的第i行子像素的像素电路和发光元件电连接，位于过渡显示区的第i+1行第j列的子像素的像素电路与位于透光显示区的第i+1行第j列的子像素的发光元件电连接，j为小于或者等于n的正整数。
如图3所示，位于过渡显示区的第i行和第i+1行子像素的像素电路连接同一扫描线。
在一种示例性实施例中，第一显示区和第二显示区的分辨率相同。其中，分辨率(Pixels Per Inch，简称PPI)是指单位面积所拥有像素的数量，可以称为像素密度，PPI数值越高，代表显示基板能够以越高的密度显示画面，画面的细节就越丰富。
在一种示例性实施例中，透光显示区的位置可以与光学装置的位置相对应，具有显示画面和透过光线的功能，透过的光线被光学装置接收。过渡显示区具有显示画面和为透光显示区提供信号的功能。
在一种示例性实施例中，m和n的取值可以根据光学装置的尺寸确定。
在一种示例性实施例中，在平行于显示基板的平面内，透光显示区的形状可以是如下任意一种或多种：矩形、多边形、圆形和椭圆形，光学装置可以是指纹识别装置、摄像装置或3D成像等光学传感器，本公开在此不做限定。例如，透光显示区的形状为圆形时，圆形的直径可以约为3mm至5mm。又如，透光显示区的形状为矩形时，矩形的边长可以约为3mm至5mm。图2至图5是以透光显示区的形状为矩形为例进行说明的。
在一种示例性实施例中，在平行于显示基板的平面内，过渡显示区的形 状可以是如下任意一种或多种：矩形、多边形、圆形和椭圆形。
在一种示例性实施例中，子像素的形状可以是三角形、正方形、矩形、菱形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种，排列方式可以是X形、十字形或品字形等，本公开在此不做限定。
在一种示例性实施例中，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图4为一种像素电路的等效电路示意图。如图4所示，像素电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据信号线Data、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)。
在一种示例性实施例中中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第一节点N1连 接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线Data的数据电压输入到像素电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在一种示例性实施例中中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素电路中的扫描信号线，第二扫描信号线S2为上一显示行像素电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素电路中的第一扫描信号线S1为同一信号线，可以减少显示基板的信号线，实现显示基板的窄边框。
在一种示例性实施例中中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在一种示例性实施例中中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一 电源线VDD和数据信号线Data沿竖直方向延伸。
图5为一种像素电路的工作时序图。下面通过图4示例的像素电路的工作过程说明本公开示例性实施例，图4中的像素电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据信号线Data、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在一种示例性实施例中中，像素电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线Data输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线Data输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
本公开实施例提供的显示基板包括：显示区和包围显示区的非显示区，显示区包括：多条沿第一方向延伸的扫描线和阵列排布的多个子像素，显示区包括：第一显示区和第二显示区，第一显示区位于第二显示区的外围，第二显示区包括：透光显示区和过渡显示区，过渡显示区位于透光显示区的侧面；透光显示区包括：m行n列子像素，位于透光显示区的每个子像素包括：发光元件，位于透光显示区的第i行中的每个子像素的发光元件与位于透光显示区的第i+1行，且同一颜色的子像素的发光元件电连接，i为小于或者等于m的奇数；过渡显示区包括：m行n列子像素，透光显示区的第i行子像素和过渡显示区的第i行子像素位于同一行；位于过渡显示区的每个子像素包括：像素电路和发光元件，位于过渡显示区的第i行中的每个子像素的发光元件与位于过渡显示区的第i+1行，且同一颜色的子像素的发光元件电连接；位于过渡显示区的第i行子像素的像素电路和发光元件电连接，位于过渡显示区的第i+1行第j列的子像素的像素电路与位于透光显示区的第i+1行第j列的子像素的发光元件电连接，j为小于或者等于n的正整数；位于过渡显示区的第i行和第i+1行子像素的像素电路连接同一扫描线。本公开通过位于过渡显示区的第i+1行第j列的子像素的像素电路与位于透光显示区 的第i+1行第j列的子像素的发光元件电连接位于过渡显示区的第i行和第i+1行子像素的像素电路连接同一扫描线，可以保证透光显示区和过渡显示区同时显示，提升了显示基板的显示效果。
在一种示例性实施例中，图6为一种示例性实施例提供的显示基板的结构示意图一，图7为另一示例性实施例提供的显示基板的结构示意图。如图3、图6和图7所示，位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线G1或者第二扫描线G2。其中，第一扫描线G1为与位于过渡显示区的第i行子像素位于同一行，且位于第一显示区的子像素所连接的扫描线；第二扫描线G2为与位于过渡显示区的第i+1行子像素位于同一行，且位于第一显示区的子像素所连接的扫描线。图3、图6和图7是以位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线电连接为例进行说明的。
如图3、图6和图7所示，在一种示例性实施例中，第一显示区可以包括：多个子像素。位于第一显示区的每个子像素可以包括：像素电路和发光元件。
如图3、图6和图7所示，在一种示例性实施例中，位于同一行的至少三个子像素构成一个像素单元。发光元件11包括：阳极、有机发光层和阴极。
在一种示例性实施例中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在一种示例性实施例中中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在一种示例性实施例中，像素单元中可以包括，或者可以包括红色子像 素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。本公开是以每个像素单元包括四个子像素，且四个子像素为红色子像素、绿色子像素、蓝色子像素和绿色子像素或者蓝色子像素、绿色子像素、红色子像素、绿色子像素为例进行说明的。
在一种示例性实施例中，位于同一行的像素单元的子像素排布方式相同。位于同一列的像素单元中的子像素的排布方式可以相同，也可以不同，本公开是以位于同一列的像素单元不同为例进行说明的。
如图3、图6和图7所示，在一种示例性实施例中，位于透光显示区的第i行第k列像素单元中的每个子像素的发光元件的阳极分别与位于透光显示区的第i+1行第k列像素单元中的一个相同颜色的子像素的发光元件的阳极电连接，k为小于或者等于K的正整数，K＝n/3或者n/4。
在一种示例性实施例中，位于透光显示区的第i行第k列像素单元中的子像素的发光元件的阳极与位于透光显示区的第i+1行第k列像素单元中的距离最近的，且为相同颜色的子像素的发光元件的阳极电连接。
如图3、图6和图7所示，在一种示例性实施例中，位于过渡显示区的第i行第j列像素单元中的每个子像素的发光元件的阳极分别与位于过渡显示区的第i+1行第j列像素单元中的一个相同颜色的子像素的发光元件的阳极电连接。
在一种示例性实施例中，位于过渡显示区的第i行第j列像素单元中的每个子像素的发光元件的阳极分别与位于过渡显示区的第i+1行第j列像素单元中的距离最近的，且为相同颜色的子像素的发光元件的阳极电连接。
如图3、图6和图7所示，在一种示例性实施例中，位于过渡显示区的第i+1行第j列的子像素的像素电路与位于透光显示区的第i+1行第j列的子像素的发光元件的阳极电连接。
在一种示例性实施例中，位于第一显示区的子像素的像素电路和发光元件的阳极电连接。
如图3、图6和图7所示，在一种示例性实施例中，显示基板还可以包括：多条沿第二方向延伸的数据线D，位于过渡显示区的第i行第j列子像素的像素电路与第一数据线D1电连接，位于过渡显示区的第i+1行第j列子像素的像素电路与第二数据线D2电连接。
在一种示例性实施例中，第一方向和第二方向相交。第一数据线D1为与位于过渡显示区的第i行第j列子像素位于同一列，且位于第一显示区的子像素的像素电路所连接的数据线；第二数据线D2为与位于透光显示区的第i+1行第j列的子像素位于同一列，且位于第一显示区的子像素的像素电路所连接的数据线。
如图3、图6和图7所示，在一种示例性实施例中，显示基板还可以包括：数据连接线DL，数据连接线DL与数据线D异层设置。其中，数据连接线，分别与位于过渡显示区的第i+1行第j列子像素的像素电路和位于过渡显示区的第i+1行第j列子像素的像素电路所连接的第二数据线电连接。
在一种示例性实施例中，数据连接线DL可以位于数据线D靠近衬底的一侧，或者，可以位于数据线远离衬底的一侧。
如图2、图3、图6和图7所示，在一种示例性实施例中，透光显示区R21包括：相对设置的第一侧和第二侧以及相对设置的第三侧和第四侧；过渡显示区R22包括：第一过渡显示区R221和第二过渡显示区R222。
第一过渡显示区R221位于透光显示区R21的第一侧，第二过渡显示区R222位于透光显示区R21的第二侧，第一过渡显示区R221和第二过渡显示区R222沿第一方向排布。
在一种示例性实施例中，第二显示区的数量为至少一个。如图2、图3、图6和图7是以第二显示区的数量为一个进行说明的。
图8为显示区的划分示意图一。如图8所示，在一种示例性实施例中，当第二显示区的数量为一个时，第一显示区R10包括：第一正常显示区R11、第二正常显示区R12、第三正常显示区R13和第四正常显示区R14。其中，第一正常显示区R11的第k行与透光显示区R21的第k行为同一行，第二正常显示区R12的第k行与透光显示区R21的第k行为同一行，k为大于等于1，且小于等于m的正整数；
第一正常显示区R11位于第一过渡显示区R221远离透光显示区R21的一侧，第二正常显示区R12位于第二过渡显示区R222远离透光显示区R21的一侧；第三正常显示区R13位于透光显示区R21的第三侧，第四正常显示区R14位于透光显示区R21的第四侧；第三正常显示区R13和第四正常显示区R14沿第二方向排布。
图9为显示区的划分示意图二。如图9所示，在一种示例性实施例中，当第二显示区的数量为至少两个时，第一显示区包括：第一正常显示区R11、第二正常显示区R12、第三正常显示区R13、第四正常显示区R14和Q-1个第五正常显示区R15；第一正常显示区R11的第k行与透光显示区R21的第k行为同一行,第二正常显示区R12的第k行与透光显示区R21的第k行为同一行，第五正常显示区R15的第k行与透光显示区R21的第k行为同一行，k为大于等于1，且小于等于m的正整数，Q为第二显示区的数量；
第一正常显示区R11位于第一过渡显示区R221远离透光显示区R21的一侧，第二正常显示区R12位于第二过渡显示区R222远离透光显示区R21的一侧；第三正常显示区R13位于透光显示区R21的第三侧，第四正常显示区R14位于透光显示区R21的第四侧；第三正常显示区R13和第四正常显示区R14沿第二方向排布；第i个第五正常显示区R15位于第i个第二显示区和第i+1个第二显示区之间。图9是以Q＝2为例进行说明的。
在一种示例性实施例中，如图3、图6和图7所示，第一数据线D1可以分别与位于透光显示区的第i行第j列的子像素位于同一列，且位于第三正常显示区和第四正常显示区的子像素的像素电路以及位于透光显示区的第i行第j列的子像素的像素电路电连接。
在一种示例性实施例中，如图3、图6和图7所示，第二数据线D2可以包括：间隔设置的，且沿第二方向延伸的第一子数据线和第二子数据线，第一子数据线与第二子数据线沿第二方向排布。其中，第一子数据线与位于透光显示区的第i+1行第j列的子像素位于同一列，且位于第三正常显示区的子像素的像素电路电连接。第二子数据线与位于透光显示区的第i+1行第j列的子像素位于同一列，且位于第四正常显示区的子像素的像素电路电连接。
图10为一种示例性实施例提供的多条扫描线的示意图一，图11为一种 示例性实施例提供的多条扫描线的示意图二。如图10和图11所示，当第二显示区为一个，且位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线时，第一扫描线G1包括：间隔设置的第一扫描部G11和第二扫描部G12。第二扫描线G2包括：间隔设置，且沿第一方向延伸的第三扫描部G13和第四扫描部G14。其中，第一扫描部G11分别与位于第一过渡显示区R221的第i行子像素的像素电路、位于第一过渡显示区R221的第i+1行子像素的像素电路和位于第一正常显示区的第i行子像素的像素电路电连接。第二扫描部G12分别与位于第二过渡显示区R222的第i行和第i+1行子像素的像素电路以及位于第二正常显示区的第i行子像素的像素电路电连接。第三扫描部G13与位于第一正常显示区的第i+1行子像素的像素电路电连接。第四扫描部G14与位于第二正常显示区的第i+1行子像素的像素电路电连接。
在一种示例性实施例中，如图10和图11所示，第一扫描部可以包括：第一连接部G111、第二连接部G112和第三连接部G113。第一连接部G111和第三连接部G113沿第一方向延伸，第二连接部G112沿第二方向延伸。其中，第一连接部G111分别与位于第一正常显示区的第i行子像素的像素电路、位于第一过渡显示区R221的第i行子像素的像素电路和第二连接部G112电连接；第二连接部G112与第三连接部G113电连接；第三连接部G113与位于第一过渡显示区R221的第i+1行子像素的像素电路电连接。其中，图10中的第一扫描部为开环。
在一种示例性实施例中，如图10和图11所示，第二扫描部G12包括：第四连接部G121、第五连接部G122和第六连接部G123，第四连接部G121和第六连接部G123沿第一方向延伸，第五连接部G122沿第二方向延伸。第四连接部G121分别与位于第二正常显示区的第i行子像素的像素电路、位于第二过渡显示区R222的第i行子像素的像素电路和第五连接部G122电连接；第五连接部G122与第六连接部G123电连接，第六连接部G123与位于第二过渡显示区R222的第i+1行子像素的像素电路电连接。图10中的第二扫描部为开环。
在一种示例性实施例中，如图11所示，第一扫描部G11还可以包括： 第七连接部G114。第七连接部G114沿第二方向延伸。其中，第七连接部G114，分别与第一连接部G111和第三连接部G113电连接。图11中的第一扫描部包括闭环，位于过渡显示区的第一扫描部为闭环。
在一种示例性实施例中，位于过渡显示区的第一扫描部为闭环可以减小第一扫描线的负载。
在一种示例性实施例中，如图11所示，第二扫描部G12还可以包括：第八连接部G124。第八连接部G124沿第二方向延伸。其中，第八连接部G124与第四连接部G121和第六连接部G123电连接。图11中的第二扫描部包括闭环，位于过渡显示区的第二扫描部为闭环。
在一种示例性实施例中，位于过渡显示区的第二扫描部为闭环可以减小第一扫描线的负载。
图12为一种示例性实施例提供的多条扫描线的示意图三，图13为一种示例性实施例提供的多条扫描线的示意图四，图14为一种示例性实施例提供的多条扫描线的示意图五，图15为一种示例性实施例提供的多条扫描线的示意图六，图16为一种示例性实施例提供的多条扫描线的示意图七，图17为一种示例性实施例提供的多条扫描线的示意图八。如图12至图17所示，第一扫描线G1还可以包括：第一扫描连接部GC1，或者第二扫描线G2还可以包括：第二扫描线G2。
第一扫描连接部GC1分别与第一扫描部G11和第二扫描部G12电连接；第二扫描连接部GC2分别与第三扫描部G13和第四扫描部G14电连接。图12是以第一扫描部和第二扫描部为开环，且第一扫描线包括第一扫描连接部GC1为例进行说明的。图13是以第一扫描部和第二扫描部为开环，且第二扫描线包括第二扫描连接部GC2为例进行说明的。图14是以第一扫描部和第二扫描部为开环，且第一扫描线包括第一扫描连接部GC1和第二扫描线包括第二扫描连接部GC2为例进行说明的。图15是以第一扫描部和第二扫描部包括闭环，且第一扫描线包括第一扫描连接部GC1为例进行说明的。图16是以第一扫描部和第二扫描部包括闭环，且第二扫描线包括第二扫描连接部GC2为例进行说明的。图17是以第一扫描部和第二扫描部包括闭环，且包括第一扫描连接部GC1和第二扫描线包括第二扫描连接部GC2为例进行 说明的。
图18为另一示例性实施例提供的多条扫描线的示意图一，图19为另一示例性实施例提供的多条扫描线的示意图二。如图18和图19所示，当第二显示区为一个，且位于过渡显示区的第i行和第i+1行子像素的像素电路连接第二扫描线时，第二扫描线G2包括：间隔设置的第一扫描部G21和第二扫描部G22。第一扫描线G1包括：间隔设置，且沿第一方向延伸的第三扫描部G23和第四扫描部G24。
在一种示例性实施例中，第一扫描部G21可以分别与位于第一过渡显示区R221的第i行和第i+1行子像素的像素电路、以及位于第一正常显示区的第i+1行子像素的像素电路电连接。
在一种示例性实施例中，第二扫描部G22可以分别与位于第二过渡显示区R222的第i行和第i+1行子像素的像素电路以及位于第二正常显示区的第i+1行子像素的像素电路电连接。
在一种示例性实施例中，第三扫描部G23可以与位于第一正常显示区的第i行子像素的像素电路电连接。
在一种示例性实施例中，第四扫描部G24可以与位于第二正常显示区的第i行子像素的像素电路电连接。
在一种示例性实施例中，如图18和图19所示，第一扫描部G21可以包括：第一连接部G211、第二连接部G212和第三连接部G213。其中，第一连接部G211和第三连接部G213沿第一方向延伸，第二连接部G212沿第二方向延伸。在一种示例性实施例中，第一连接部G211可以分别与位于第一正常显示区的第i+1行子像素的像素电路、位于第一过渡显示区R221的第i+1行子像素的像素电路和第二连接部G212电连接。第二连接部G212可以与第三连接部G213电连接。第三连接部G213可以与位于第一过渡显示区R221的第i行子像素的像素电路电连接。图18中的第一扫描部为开环。
在一种示例性实施例中，如图18和图19所示，第二扫描部G22可以包括：第四连接部G221、第五连接部G222和第六连接部G223。其中，第四连接部G221和第六连接部G223沿第一方向延伸，第五连接部G222沿第二方向延伸。在一种示例性实施例中，第四连接部G221分别与位于第二正常 显示区的第i+1行子像素的像素电路、位于第二过渡显示区R222的第i+1行子像素的像素电路和第五连接部电连接；第五连接部G222与第六连接部G223电连接；第六连接部G223与位于第二过渡显示区R222的第i行子像素的像素电路电连接。图18中的第二扫描部为开环。
在一种示例性实施例中，如图19所示，第一扫描部G21还可以包括：沿第二方向延伸的第七连接部G214。其中，第七连接部G214分别与第一连接部G211和第三连接部G213电连接。图19中的第一扫描部包括闭环，位于过渡显示区的第一扫描部为闭环。
在一种示例性实施例中，位于过渡显示区的第一扫描部为闭环可以减小第一扫描线的负载。
在一种示例性实施例中，如图19所示，第二扫描部G22还可以包括：沿第二方向延伸的第八连接部G224。其中，第八连接部G224分别与第四连接部G221和第六连接部G223电连接。图19中的第二扫描部包括闭环，位于过渡显示区的第二扫描部为闭环。
在一种示例性实施例中，位于过渡显示区的第二扫描部为闭环可以减小第一扫描线的负载。
图20为另一示例性实施例提供的多条扫描线的示意图三，图21为另一示例性实施例提供的多条扫描线的示意图四，图22为另一示例性实施例提供的多条扫描线的示意图五，图23为另一示例性实施例提供的多条扫描线的示意图六，图24为另一示例性实施例提供的多条扫描线的示意图七，图25为另一示例性实施例提供的多条扫描线的示意图八。如图20至图25所示，第一扫描线G1还可以包括：第一扫描连接部GC1，或者第二扫描线G2还可以包括：第二扫描线G2。
在一种示例性实施例中，第一扫描连接部GC1分别与第一扫描部G11和第二扫描部G12电连接；第二扫描连接部GC2分别与第三扫描部G13和第四扫描部G14电连接。图20是以第一扫描部和第二扫描部为开环，且第一扫描线包括第一扫描连接部GC1为例进行说明的。图21是以第一扫描部和第二扫描部为开环，且第二扫描线包括第二扫描连接部GC2为例进行说明的。图22是以第一扫描部和第二扫描部为开环，且第一扫描线包括第一扫描 连接部GC1和第二扫描线包括第二扫描连接部GC2为例进行说明的。图23是以第一扫描部和第二扫描部包括闭环，且第一扫描线包括第一扫描连接部GC1为例进行说明的。图24是以第一扫描部和第二扫描部包括闭环，且第二扫描线包括第二扫描连接部GC2为例进行说明的。图25是以第一扫描部和第二扫描部包括闭环，且第一扫描线包括第一扫描连接部GC1和第二扫描线包括第二扫描连接部GC2为例进行说明的。
在一种示例性实施例中，扫描线的驱动方式可以根据扫描线的负载以及显示基板的空间确定。
在一种示例性实施例中，如图10、图11、图18、图19、所示，第一扫描线G1采用双边驱动，第二扫描线可以采用双边驱动，除第一扫描线和第二扫描线之外的扫描线G可以采用双边驱动或者可以采用单边驱动。
在一种示例性实施例中，如图12、图15、图21和图24所示，第一扫描线G1可以采用单边驱动或者双边驱动，第二扫描线可以采用双边驱动，除第一扫描线和第二扫描线之外的扫描线G可以采用双边驱动或者可以采用单边驱动。
在一种示例性实施例中，如图13、图16、图20和图23所示，第一扫描线G1可以采用双边驱动，第二扫描线可以采用单边区域或者双边驱动，除第一扫描线和第二扫描线之外的扫描线G可以采用双边驱动或者可以采用单边驱动。
在一种示例性实施例中，如图14、图17、图22和图25所示，所有扫描线可以采用双边驱动或者可以采用单边驱动。
在一种示例性实施例中，扫描线采用双边驱动可以减少扫描线的负载。扫描线采用单边区域可以实现显示基板的窄边框。
图26为又一示例性实施例提供的多条扫描线的示意图一，图27为又一示例性实施例提供的多条扫描线的示意图二。如图26和图27所示，当第二显示区为至少两个时，且位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线G1时，第一扫描线G1可以分别与位于第一正常显示区的第i行子像素的像素电路、位于所有第二显示区的第一过渡显示区R221和第二过渡显示区R222的第i行子像素的像素电路、位于所有第二显示区 R221的第一过渡显示区和第二过渡显示区R221的第i+1行子像素的像素电路、所有第五正常显示区的第i行子像素的像素电路和位于第二正常显示区的第i行子像素的像素电路电连接。第二扫描线可以分别与位于第一正常显示区的第i+1行子像素的像素电路、位于第二正常显示区的第i+1行子像素的像素电路和位于所有第五正常显示区的第i+1行子像素的像素电路电连接。
在一种示例性实施例中，如图26和图27所示，第一扫描线可以包括：第一扫描部G31、Q-1个第二扫描部G32、第三扫描部G33和Q个第一扫描连接部G34。其中，第一扫描部G31可以分别与位于第一正常显示区的第i行子像素的像素电路、位于第一个第二显示区的第一过渡显示区R221的第i行和第i+1行子像素的像素电路电连接。第t个第二扫描部G32分别与第t个第五正常显示区的第i行子像素的像素电路、第t个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路和第t+1个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接，t为小于Q的正整数。第三扫描部G33分别与位于第Q个第二显示区的第二过渡显示区R222的第i行和第i+1行子像素的像素电路以及第二正常显示区的第i行子像素的像素电路电连接。第一个第一扫描连接部G34可以分别与第一扫描部G31和第一个第二扫描部G32电连接，第t个第一扫描连接部G34可以分别与第t-1个第二扫描部G32和第t个第二扫描部G32电连接；第Q个第一扫描连接部G34可以分别与第Q-1个第二扫描部G32和第三扫描部G33电连接。图26和图27是以Q＝2为例进行说明的。
在一种示例性实施例中，第一扫描部、第二扫描部和第三扫描部可以为开环或者包括闭环。当第一扫描部包括闭环时，位于过渡显示区的第一扫描部为闭环。当第二扫描部包括闭环时，位于过渡显示区的第二扫描部为闭环。当第三扫描部包括闭环时，位于过渡显示区的第三扫描部为闭环。图26是以第一扫描部、第二扫描部和第三扫描部为开环为例进行说明的。图27是以第一扫描部、第二扫描部和第三扫描部包括闭环为例进行说明的。
在一种示例性实施例中，位于过渡显示区的第一扫描部、第二扫描部和第三扫描部为闭环可以减小第一扫描线的负载。
在一种示例性实施例中，如图26和图27所示，第二扫描线可以包括： 第四扫描部G41、Q-1个第五扫描部G42和第六扫描部G43、Q个第二扫描连接部G44。其中，第四扫描部G41可以与位于第一正常显示区的第i+1行子像素的像素电路电连接。第t个第五扫描部G42可以与第t个第五正常显示区的第i+1行子像素的像素电路电连接。第六扫描部G43可以与位于第二第一显示区的第i+1行子像素的像素电路电连接。第一个第二扫描连接部G44可以分别与第一扫描部G41和第一个第二扫描部G42电连接，第t个第二扫描连接部G44可以分别与第t-1个第二扫描部G42和第t个第二扫描部G42电连接；第Q个第二扫描连接部G44可以分别与第Q-1个第二扫描部G 42和第三扫描部G43电连接。
图28为又一示例性实施例提供的多条扫描线的示意图三，图29为又一示例性实施例提供的多条扫描线的示意图四。如图28和图29所示，当第二显示区为至少两个时，且位于过渡显示区的第i行和第i+1行子像素的像素电路连接第二扫描线G2时，第一扫描线G1可以分别与位于第一正常显示区的第i行子像素的像素电路、位于第二正常显示区的第i行子像素的像素电路和位于所有第五正常显示区的第i行子像素的像素电路电连接。第二扫描线G2可以分别与位于第一正常显示区的第i+1行子像素的像素电路、位于所有第二显示区的第一过渡显示区R21和第二过渡显示区R222的第i行和第i+1行子像素的像素电路、所有第五正常显示区的第i+1行子像素的像素电路以及位于第二正常显示区的第i+1行子像素的像素电路电连接。
在一种示例性实施例中，如图28和图29所示，第二扫描线可以包括：第一扫描部G31、Q-1个第二扫描部G32、第三扫描部G33和Q个第一扫描连接部G34。其中，第一扫描部G31可以分别与位于第一正常显示区的第i+1行子像素的像素电路和位于第一个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接。第t个第二扫描部G32可以分别与第t个第五正常显示区的第i+1行子像素的像素电路、第t个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路电连接和第t+1个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接。第三扫描部G33分别与位于第Q个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路和第二正常显示区的第i+1行子像素的像素电路电连接。 第一个第一扫描连接部G34分别与第一扫描部G31和第一个第二扫描部G32电连接，第t个第二扫描连接部G34可以分别与第t-1个第二扫描部G32和第t个第二扫描部G32电连接；第Q个第二扫描连接部G34可以分别与第Q-1个第二扫描部G32和第三扫描部G33电连接。图28和图29是以Q＝2为例进行说明的。
在一种示例性实施例中，第一扫描部、第二扫描部和第三扫描部可以为开环，或者可以包括闭环。其中，当第一扫描部包括闭环时，位于过渡显示区的第一扫描部为闭环。当第二扫描部包括闭环时，位于过渡显示区的第二扫描部为闭环。当第三扫描部包括闭环时，位于过渡显示区的第三扫描部为闭环。第一扫描部、第二扫描部和第三扫描部包括闭环可以减少第一扫描线的负载。图28是以第一扫描部、第二扫描部和第三扫描部为开环为例进行说明的。图29是以第一扫描部、第二扫描部和第三扫描部包括闭环为例进行说明的。
在一种示例性实施例中，位于过渡显示区的第一扫描部、第二扫描部和第三扫描部为闭环可以减小第二扫描线的负载。
在一种示例性实施例中，如图28和图29所示，第一扫描线可以包括：第四扫描部G41、Q-1个第五扫描部G42、第六扫描部G43和Q个第二扫描连接部G44。其中，第四扫描部G41可以与位于第一正常显示区的第i行子像素的像素电路电连接。第t个第五扫描部G42可以与第t个第五正常显示区的第i行子像素的像素电路电连接。第六扫描部G43可以与位于第二正常显示区的第i行子像素的像素电路电连接。第一个第二扫描连接部G44分别与第一扫描部G41和第一个第二扫描部G42电连接，第t个第二扫描连接部G44分别与第t-1个第二扫描部G42和第t个第二扫描部G42电连接；第Q个第二扫描连接部G44分别与第Q-1个第二扫描部G42和第三扫描部G43电连接。
在一种示例性实施例中，当第二显示区的数量为至少两个时，显示基板中的扫描线可以采用单边驱动或者双边驱动。当扫描线采用双边驱动时，可以提升显示基板的显示效果。
图10至图29是以透光显示区包括四行四列像素单元为例进行说明的。 其中，每个像素单元包括：至少三个不同颜色的子像素。本公开并不以此为限。
如图10至图29所示，第一扫描线在衬底上的正投影与第二扫描线在衬底上的正投影可以存在重叠区域，或者可以不存在重叠区域，根据第一扫描线和第二扫描线的结构确定，本公开不作任何限定。
在一种示例性实施例中，当第一扫描线在衬底上的正投影与第二扫描线在衬底上的正投影不存在重叠区域时，第一扫描线和第二扫描线同层设置。
在一种示例性实施例中，当第一扫描线和第二扫描线在衬底上的正投影与第二扫描线在衬底上的正投影存在重叠区域时，第一扫描线可以包括：第一非重叠部和第一重叠部，第一非重叠部与第二扫描线同层设置，第一重叠部可以设置在第二扫描线靠近衬底的一侧，或者可以设置在第二扫描线远离衬底的一侧。其中，第一非重叠部为第一扫描线没有与第二扫描线重叠的部分，第一重叠部为第一扫描线有与第二扫描线重叠的部分。
在一种示例性实施例中，当第一扫描线和第二扫描线在衬底上的正投影与第二扫描线在衬底上的正投影存在重叠区域时，第二扫描线可以包括：第二非重叠部和第二重叠部，第二非重叠部与第一扫描线同层设置，第二重叠部可以设置在第一扫描线靠近衬底的一侧，或者可以设置在第一扫描线远离衬底的一侧。其中，第二非重叠部为第二扫描线没有与第一扫描线重叠的部分，第二重叠部为第二扫描线有与第一扫描线重叠的部分。
图30为一种示例性实施例提供的部分信号的时序图，图31为另一示例性实施例提供的部分信号的时序图。图30是以过渡显示区的第i行和第i+1行的子像素的像素电路与第一扫描线电连接为例进行说明的，图31是以过渡显示区的第i行和第i+1行的子像素的像素电路与第二扫描线电连接为例进行说明的。图30和图31中的GR1为透明显示区中第i行和第i+1行的子像素连接的像素电路所连接的扫描信号，GR2为过渡显示区中第i行和第i+1行的子像素连接的像素电路所连接的扫描信号，GR_1为与过渡显示区中第i行同一行，且位于第一显示区中的子像素的像素电路所连接扫描线的扫描信号，GR_2为与过渡显示区中第i+1行同一行，且位于第一显示区中的子像素的像素电路所连接扫描线的扫描信号。D为数据线的数据信号。如图30所示， 当过渡显示区的第i行和第i+1行的子像素的像素电路与第一扫描线电连接时，GR1和GR2与GR_1相同。如图31所示，当过渡显示区的第i行和第i+1行的子像素的像素电路与第一扫描线电连接时，GR1和GR2与GR_1相同。
本公开实施例还提供了一种显示装置，可以包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，显示装置还可以包括：位于透光显示区，且位于显示装置非出光侧的功能部件。外界的环境光可以通过透光显示区射入到功能部件中。
在一种示例性实施例中，功能部件可以包括相机模组(例如，前置摄像模组)、3D结构光模组(例如，3D结构光传感器)、飞行时间法3D成像模组(例如，飞行时间法传感器)、红外感测模组(例如，红外感测传感器)等至少之一。
在一种示例性实施例中，前置摄像模组通常在用户自拍或视频通话时启用，显示装置的显示区显示自拍所得到的图像供用户观看。前置摄像模组例如包括镜头、图像传感器、图像处理芯片等。景物通过镜头生成的光学图像投射到图像传感器表面(图像传感器包括CCD和CMOS两种)变换为电信号，通过图像处理芯片模数转换后变为数字图像信号，再送到处理器中加工处理，在显示屏上输出该景物的图像。
在一种示例性实施例中，3D结构光传感器和飞行时间法(Time of Flight，ToF)传感器可以用于人脸识别以对显示装置进行解锁等。
例如，功能部件可以仅包括相机模组以实现自拍或者视频通话的功能；例如，该功能部件还可以包括3D结构光模组或者飞行时间法3D成像模组以实现人脸识别解锁等，本公开包括但不限于此。
本公开实施例提供的显示装置，可以在透光显示区区显示图像，以保持整个显示装置的显示完整性。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (22)

  1. 一种显示基板，包括：显示区和包围所述显示区的非显示区，所述显示区包括：多条沿第一方向延伸的扫描线和阵列排布的多个子像素，所述显示区包括：第一显示区和第二显示区，所述第一显示区位于所述第二显示区的外围，所述第二显示区包括：透光显示区和过渡显示区，所述过渡显示区位于所述透光显示区的侧面；
    所述透光显示区包括：m行n列子像素，位于透光显示区的每个子像素包括：发光元件，位于透光显示区的第i行中的每个子像素的发光元件与位于透光显示区的第i+1行，且同一颜色的子像素的发光元件电连接，i为小于或者等于m的奇数；
    所述过渡显示区包括：m行n列子像素，所述透光显示区的第i行子像素和所述过渡显示区的第i行子像素位于同一行；位于过渡显示区的每个子像素包括：像素电路和发光元件，位于过渡显示区的第i行中的每个子像素的发光元件与位于过渡显示区的第i+1行，且同一颜色的子像素的发光元件电连接；位于过渡显示区的第i行子像素的像素电路和发光元件电连接，位于过渡显示区的第i+1行第j列的子像素的像素电路与位于透光显示区的第i+1行第j列的子像素的发光元件电连接，j为小于或者等于n的正整数；
    位于过渡显示区的第i行和第i+1行子像素的像素电路连接同一扫描线。
  2. 根据权利要求1所述的显示基板，其中，位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线或者第二扫描线；
    其中，所述第一扫描线为与位于过渡显示区的第i行子像素位于同一行，且位于第一显示区的子像素所连接的扫描线；所述第二扫描线为与位于过渡显示区的第i+1行子像素位于同一行，且位于第一显示区的子像素所连接的扫描线。
  3. 根据权利要求1或2所述的显示基板，其中，所述第一显示区包括：多个子像素，位于第一显示区的每个子像素包括：像素电路和发光元件；位于同一行的至少三个子像素构成一个像素单元；所述发光元件包括：阳极、有机发光层和阴极；
    位于透光显示区的第i行第k列像素单元中的每个子像素的发光元件的阳极分别与位于透光显示区的第i+1行第k列像素单元中的一个相同颜色的子像素的发光元件的阳极电连接，k为小于或者等于K的正整数，K＝n/3或者n/4；
    位于过渡显示区的第i行第j列像素单元中的每个子像素的发光元件的阳极分别与位于过渡显示区的第i+1行第j列像素单元中的一个相同颜色的子像素的发光元件的阳极电连接；
    位于过渡显示区的第i+1行第j列的子像素的像素电路与位于透光显示区的第i+1行第j列的子像素的发光元件的阳极电连接；
    位于第一显示区的子像素的像素电路和发光元件的阳极电连接。
  4. 根据权利要求3所述的显示基板，还包括：多条沿第二方向延伸的数据线，位于过渡显示区的第i行第j列子像素的像素电路与第一数据线电连接，位于过渡显示区的第i+1行第j列子像素的像素电路与第二数据线电连接，所述第一方向和所述第二方向相交；
    其中，所述第一数据线为与位于过渡显示区的第i行第j列子像素位于同一列，且位于第一显示区的子像素的像素电路所连接的数据线；所述第二数据线为与位于透光显示区的第i+1行第j列的子像素位于同一列，且位于第一显示区的子像素的像素电路所连接的数据线。
  5. 根据权利要求4所述的显示基板，还包括：数据连接线，所述数据连接线与数据线异层设置；
    所述数据连接线，分别与位于过渡显示区的第i+1行第j列子像素的像素电路和位于过渡显示区的第i+1行第j列子像素的像素电路所连接的第二数据线电连接。
  6. 根据权利要求2所述的显示基板，其中，所述透光显示区包括：相对设置的第一侧和第二侧以及相对设置的第三侧和第四侧；所述过渡显示区包括：第一过渡显示区和第二过渡显示区；
    所述第一过渡显示区位于所述透光显示区的第一侧，所述第二过渡显示区位于透光显示区的第二侧，所述第一过渡显示区和所述第二过渡显示区沿 第一方向排布。
  7. 根据权利要求6所述的显示基板，其中，所述第二显示区的数量为至少一个。
  8. 根据权利要求7所述的显示基板，其中，当第二显示区的数量为一个时，所述第一显示区包括：第一正常显示区、第二正常显示区、第三正常显示区和第四正常显示区；
    第一正常显示区的第k行与透光显示区的第k行为同一行，第二正常显示区的第k行与透光显示区的第k行为同一行，k为大于等于1，且小于等于m的正整数；
    所述第一正常显示区位于所述第一过渡显示区远离所述透光显示区的一侧，所述第二正常显示区位于所述第二过渡显示区远离所述透光显示区的一侧；所述第三正常显示区位于所述透光显示区的第三侧，所述第四正常显示区位于所述透光显示区的第四侧；所述第三正常显示区和所述第四正常显示区沿第二方向排布。
  9. 根据权利要求8所述的显示基板，其中，当位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线时，所述第一扫描线包括：间隔设置的第一扫描部和第二扫描部；所述第二扫描线包括：间隔设置，且沿第一方向延伸的第三扫描部和第四扫描部；
    所述第一扫描部分别与位于第一过渡显示区的第i行和第i+1行子像素的像素电路以及位于第一正常显示区的第i行子像素的像素电路电连接；
    所述第二扫描部分别与位于第二过渡显示区的第i行和第i+1行子像素的像素电路以及位于第二正常显示区的第i行子像素的像素电路电连接；
    所述第三扫描部与位于第一正常显示区的第i+1行子像素的像素电路电连接；
    所述第四扫描部与位于第二正常显示区的第i+1行子像素的像素电路电连接。
  10. 根据权利要求9所述的显示基板，其中，所述第一扫描部包括：第一连接部、第二连接部和第三连接部，第一连接部和第三连接部沿第一方向 延伸，第二连接部沿第二方向延伸；
    第一连接部分别与位于第一正常显示区的第i行子像素的像素电路、位于第一过渡显示区的第i行子像素的像素电路和第二连接部电连接；第二连接部与第三连接部电连接；第三连接部与位于第一过渡显示区的第i+1行子像素的像素电路电连接；
    所述第二扫描部包括：第四连接部、第五连接部和第六连接部，第四连接部和第六连接部沿第一方向延伸，第五连接部沿第二方向延伸；
    第四连接部分别与位于第二正常显示区的第i行子像素的像素电路、位于第二过渡显示区的第i行子像素的像素电路和第五连接部电连接；第五连接部与第六连接部电连接；第六连接部与位于第二过渡显示区的第i+1行子像素的像素电路电连接。
  11. 根据权利要求10所述的显示基板，其中，所述第一扫描部还包括：沿第二方向延伸的第七连接部，所述第二扫描部还包括：沿第二方向延伸的第八连接部；
    所述第七连接部，分别与第一连接部和第三连接部电连接；
    所述第八连接部，分别与第四连接部和第六连接部电连接。
  12. 根据权利要求10或11所述的显示基板，其中，所述第一扫描线还包括：第一扫描连接部；
    所述第一扫描连接部分别与第一扫描部和第二扫描部电连接。
  13. 根据权利要求10至12任一项所述的显示基板，其中，所述第二扫描线还包括：第二扫描部；
    所述第二扫描连接部分别与第三扫描部和第四扫描部电连接。
  14. 根据权利要求8所述的显示基板，其中，当位于过渡显示区的第i行和第i+1行子像素的像素电路连接第二扫描线时，所述第二扫描线包括：间隔设置的第一扫描部和第二扫描部；所述第一扫描线包括：间隔设置，且沿第一方向延伸的第三扫描部和第四扫描部；
    所述第一扫描部分别与位于第一过渡显示区的第i行和第i+1行子像素的像素电路以及位于第一正常显示区的第i+1行子像素的像素电路电连接；
    所述第二扫描部分别与位于第二过渡显示区的第i行和第i+1行子像素的像素电路以及位于第二正常显示区的第i+1行子像素的像素电路电连接；
    所述第三扫描部与位于第一正常显示区的第i行子像素的像素电路电连接；
    所述第四扫描部与位于第二正常显示区的第i行子像素的像素电路电连接。
  15. 根据权利要求14所述的显示基板，其中，所述第一扫描部包括：第一连接部、第二连接部和第三连接部，第一连接部和第三连接部沿第一方向延伸，第二连接部沿第二方向延伸；第一连接部分别与位于第一正常显示区的第i+1行子像素的像素电路、位于第一过渡显示区的第i+1行子像素的像素电路和第二连接部电连接；第二连接部与第三连接部电连接；第三连接部与位于第一过渡显示区的第i行子像素的像素电路电连接；
    所述第二扫描部包括：第四连接部、第五连接部和第六连接部，第四连接部和第六连接部沿第一方向延伸，第五连接部沿第二方向延伸；第四连接部分别与位于第二正常显示区的第i+1行子像素的像素电路、位于第二过渡显示区的第i+1行子像素的像素电路和第五连接部电连接；第五连接部与第六连接部电连接；第六连接部与位于第二过渡显示区的第i行子像素的像素电路电连接。
  16. 根据权利要求15所述的显示基板，其中，所述第一扫描部还包括：沿第二方向延伸的第七连接部，第七连接部分别与第一连接部和第三连接部电连接；
    所述第二扫描部还包括：沿第二方向延伸的第八连接部，第八连接部分别与第四连接部和第六连接部电连接。
  17. 根据权利要求15或16所述的显示基板，其中，所述第二扫描线还包括：第一扫描连接部；
    所述第一扫描连接部分别与第一扫描部和第二扫描部电连接。
  18. 根据权利要求15至17任一项所述的显示基板，其中，所述第一扫描线还包括：第二扫描连接部；
    所述第二扫描连接部分别与第三扫描部和第四扫描部电连接。
  19. 根据权利要求7所述的显示基板，其中，当第二显示区的数量为至少两个时，所述第一显示区包括：第一正常显示区、第二正常显示区、第三正常显示区、第四正常显示区和Q-1个第五正常显示区；第一正常显示区的第k行与透光显示区的第k行为同一行,第二正常显示区的第k行与透光显示区的第k行为同一行，第五正常显示区的第k行与透光显示区的第k行为同一行，k为大于等于1，且小于等于m的正整数，Q为第二显示区的数量；
    第一正常显示区位于第一过渡显示区远离透光显示区的一侧，第二正常显示区位于第二过渡显示区远离透光显示区的一侧；第三正常显示区位于透光显示区的第三侧，第四正常显示区位于透光显示区的第四侧；第三正常显示区和第四正常显示区沿第二方向排布；第i个第五正常显示区位于第i个第二显示区和第i+1个第二显示区之间。
  20. 根据权利要求19所述的显示基板，其中，当位于过渡显示区的第i行和第i+1行子像素的像素电路连接第一扫描线时，
    所述第一扫描线分别与位于第一正常显示区的第i行子像素的像素电路、位于所有第二显示区的第一过渡显示区和第二过渡显示区的第i行子像素的像素电路、位于所有第二显示区的第一过渡显示区和第二过渡显示区的第i+1行子像素的像素电路、所有第五正常显示区的第i行子像素的像素电路以及位于第二正常显示区的第i行子像素的像素电路电连接；
    所述第二扫描线分别与位于第一正常显示区的第i+1行子像素的像素电路、位于第二正常显示区的第i+1行子像素的像素电路和位于所有第五正常显示区的第i+1行子像素的像素电路电连接；
    所述第一扫描线包括：第一扫描部、Q-1个第二扫描部和第三扫描部、Q个第一扫描连接部；
    第一扫描部分别与位于第一正常显示区的第i行子像素的像素电路、位于第一个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接；
    第t个第二扫描部分别与第t个第五正常显示区的第i行子像素的像素电 路、第t个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路和第t+1个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接，t为小于Q的正整数；
    第三扫描部分别与位于第Q个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路以及第二正常显示区的第i行子像素的像素电路电连接；
    第一个第一扫描连接部分别与第一扫描部和第一个第二扫描部电连接，第t个第一扫描连接部分别与第t-1个第二扫描部和第t个第二扫描部电连接；第Q个第一扫描连接部分别与第Q-1个第二扫描部和第三扫描部电连接；
    所述第二扫描线包括：第四扫描部、Q-1个第五扫描部和第六扫描部、Q个第二扫描连接部；
    第四扫描部与位于第一正常显示区的第i+1行子像素的像素电路电连接；
    第t个第五扫描部与第t个第五正常显示区的第i+1行子像素的像素电路电连接；
    第六扫描部与位于第二第一显示区的第i+1行子像素的像素电路电连接；
    第一个第二扫描连接部分别与第一扫描部和第一个第二扫描部电连接，第t个第二扫描连接部分别与第t-1个第二扫描部和第t个第二扫描部电连接；第Q个第二扫描连接部分别与第Q-1个第二扫描部和第三扫描部电连接。
  21. 根据权利要求19所述的显示基板，其中，当位于过渡显示区的第i行和第i+1行子像素的像素电路连接第二扫描线时，
    所述第一扫描线分别与位于第一正常显示区的第i行子像素的像素电路、位于第二正常显示区的第i行子像素的像素电路和位于所有第五正常显示区的第i行子像素的像素电路电连接；
    所述第二扫描线分别与位于第一正常显示区的第i+1行子像素的像素电路、位于所有第二显示区的第一过渡显示区和第二过渡显示区的第i行和第i+1行子像素的像素电路、所有第五正常显示区的第i+1行子像素的像素电路以及位于第二正常显示区的第i+1行子像素的像素电路电连接；
    所述第二扫描线包括：第一扫描部、Q-1个第二扫描部和第三扫描部、 Q个第一扫描连接部；
    第一扫描部分别与位于第一正常显示区的第i+1行子像素的像素电路和位于第一个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接；
    第t个第二扫描部分别与第t个第五正常显示区的第i+1行子像素的像素电路、第t个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路和第t+1个第二显示区的第一过渡显示区的第i行和第i+1行子像素的像素电路电连接；
    第三扫描部分别与位于第Q个第二显示区的第二过渡显示区的第i行和第i+1行子像素的像素电路和第二正常显示区的第i+1行子像素的像素电路电连接；
    第一个第一扫描连接部分别与第一扫描部和第一个第二扫描部电连接，第t个第二扫描连接部分别与第t-1个第二扫描部和第t个第二扫描部电连接；第Q个第二扫描连接部分别与第Q-1个第二扫描部和第三扫描部电连接；
    第一扫描线包括：第四扫描部、Q-1个第五扫描部、第六扫描部和Q个第二扫描连接部；
    第四扫描部与位于第一正常显示区的第i行子像素的像素电路电连接；
    第t个第五扫描部与第t个第五正常显示区的第i行子像素的像素电路电连接；
    第六扫描部与位于第二正常显示区的第i行子像素的像素电路电连接；
    第一个第二扫描连接部分别与第一扫描部和第一个第二扫描部电连接，第t个第二扫描连接部分别与第t-1个第二扫描部和第t个第二扫描部电连接；第Q个第二扫描连接部分别与第Q-1个第二扫描部和第三扫描部电连接。
  22. 一种显示装置，包括：如权利要求1至21任一项所述的显示基板。
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