WO2021190156A1 - 像素电路及其控制方法、和显示装置 - Google Patents

像素电路及其控制方法、和显示装置 Download PDF

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Publication number
WO2021190156A1
WO2021190156A1 PCT/CN2021/074899 CN2021074899W WO2021190156A1 WO 2021190156 A1 WO2021190156 A1 WO 2021190156A1 CN 2021074899 W CN2021074899 W CN 2021074899W WO 2021190156 A1 WO2021190156 A1 WO 2021190156A1
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Prior art keywords
switch circuit
control
signal line
sub
pixels
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PCT/CN2021/074899
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English (en)
French (fr)
Inventor
董甜
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京东方科技集团股份有限公司
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Priority to US17/600,078 priority Critical patent/US11847954B2/en
Publication of WO2021190156A1 publication Critical patent/WO2021190156A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit and a control method thereof, and a display device.
  • the number of signal lines in the pixel circuit will also increase.
  • the number of signal lines is greater than the number of channels of a single integrated circuit (IC).
  • IC integrated circuit
  • the embodiments of the present disclosure provide a pixel circuit and a control method thereof, and a display device.
  • embodiments of the present disclosure provide a pixel circuit, including:
  • a plurality of sub-pixels arranged in an array
  • the plurality of data lines extending along the second direction, wherein two first signal lines and two second signal lines connected to two adjacent columns of sub-pixels are electrically connected to the same data line.
  • first switch circuit is respectively provided between each data line and the connected first signal line
  • second switch circuit is respectively provided between each data line and the connected second signal line
  • Each first switch circuit is used to control the connection or disconnection between the connected data line and the connected first signal line;
  • Each second switch circuit is used to control the connection or disconnection between the connected data line and the connected second signal line.
  • it further includes four control signal lines extending along the first direction, wherein the two control signal lines are respectively connected to the same data line and the control terminals of the two first switch circuits are electrically connected in a one-to-one correspondence.
  • the two control signal lines are respectively connected to the same data line and the control terminals of the two second switch circuits are electrically connected in a one-to-one correspondence;
  • the four control signal lines are used for time-sharing control of the conduction or disconnection between the data line and a connected first signal line or a second signal line.
  • a first signal line and a second signal line are arranged between the two connected columns of sub-pixels.
  • a third switch circuit is also provided between the two first switch circuits connected to the same data line and the data line, and a third switch circuit is also provided between the two second switch circuits connected to the same data line and the data line.
  • the fourth switch circuit is also provided between the two first switch circuits connected to the same data line and the data line, and a third switch circuit is also provided between the two second switch circuits connected to the same data line and the data line.
  • the third switch circuit is used to control the conduction or disconnection between the data line and the two first switch circuits
  • the fourth switch circuit is used to control the conduction or disconnection between the data line and the two second switch circuits.
  • first control signal line a first control signal line, a second control signal line, a third control signal line, and a fourth control signal line extending along the first direction, wherein,
  • the first control signal line is electrically connected to the control end of the third switch circuit of each data line;
  • the second control signal line is electrically connected to the control end of the fourth switch circuit of each data line;
  • the third control signal line is electrically connected to the control terminal of the first switch circuit connected to the sub-pixels located in odd rows and odd columns and the control terminal of the second switch circuit connected to sub-pixels located in even rows and even columns, respectively;
  • the fourth control signal line is electrically connected to the control terminal of the second switch circuit connected to the sub-pixels in even rows and odd columns and the control terminal of the first switch circuit connected to sub-pixels in odd rows and even columns.
  • first signal lines or two second signal lines are arranged between the two connected columns of sub-pixels.
  • a fifth switch circuit is also provided between the first and second switching circuits connected to one column of sub-pixels and the data line, which is connected to the first column of sub-pixels in another column.
  • a sixth switch circuit is also provided between the switch circuit and the second switch circuit and the data line;
  • the fifth switch circuit is used to control the conduction or disconnection between the data line and the connected first switch circuit or the second switch circuit;
  • the sixth switch circuit is used to control the conduction or disconnection between the data line and the connected first switch circuit or the second switch circuit.
  • first control signal line a first control signal line, a second control signal line, a third control signal line, and a fourth control signal line extending along the first direction, wherein,
  • the first control signal line is electrically connected to the control end of the fifth switch circuit of each data line;
  • the second control signal line is electrically connected to the control end of the sixth switch circuit of each data line;
  • the third control signal line is electrically connected to the control terminal of the first switch circuit connected to the sub-pixels located in odd rows and odd columns and the control terminal of the second switch circuit connected to sub-pixels located in odd rows and even columns;
  • the fourth control signal line is electrically connected to the control terminal of the first switch circuit connected to the sub-pixels in the even rows and odd columns and the control terminal of the second switch circuit connected to the sub-pixels in the even rows and even columns.
  • At least one of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit includes a transistor, and the first pole of the transistor is connected to the data
  • the second electrode of the transistor is electrically connected to the sub-pixel, and the control electrode of the transistor is electrically connected to the control signal line.
  • embodiments of the present disclosure also provide a display device, including the pixel circuit described above.
  • embodiments of the present disclosure also provide a method for driving a pixel circuit, which is applied to the above-mentioned pixel circuit, and the method includes:
  • a plurality of gate lines provide gate scan signals to sub-pixels located in different rows in a time-sharing manner.
  • each data line passes through the first signal line or the second signal connected to it.
  • the line time division provides corresponding data signals to two sub-pixels in the row of sub-pixels.
  • each of the data lines is time-shared to two sub-pixels in the row of sub-pixels through the first signal line or the second signal line connected to it.
  • Provide corresponding data signals including:
  • Control the first control signal line to send an on signal to the control terminal of the third switch circuit, and at the same time control the fourth control signal line to send an on signal to the control terminal of the first switch circuit, so that the data signal is written in the odd-numbered rows and even-numbered columns. Pixels; or,
  • each of the data lines provides corresponding corresponding data to two sub-pixels in the row of sub-pixels through the first signal line or the second signal line connected to it.
  • Data signals including:
  • Control the second control signal line to send an on signal to the control terminal of the fourth switch circuit, and at the same time control the third control signal line to send an on signal to the control terminal of the second switch circuit, so that the data signal is written into the even-numbered rows and even-numbered columns. Pixels.
  • each of the data lines is time-shared to two sub-pixels in the row of sub-pixels through the first signal line or the second signal line connected to it.
  • Provide corresponding data signals including:
  • Control the first control signal line to send an on signal to the control terminal of the fifth switch circuit, and at the same time control the third control signal line to send an on signal to the control terminal of the first switch circuit, so that the data signal is written into the odd-numbered rows and odd-numbered columns.
  • Control the second control signal line to send an open signal to the control terminal of the sixth switch circuit, and at the same time control the third control signal line to send an open signal to the control terminal of the first switch circuit, so that the data signal is written into the sub-rows in odd rows and even columns. Pixels; or,
  • each of the data lines provides corresponding corresponding data to two sub-pixels in the row of sub-pixels through the first signal line or the second signal line connected to it.
  • Data signals including:
  • Control the second control signal line to send an open signal to the control end of the sixth switch circuit, and control the fourth control signal line to send an open signal to the control end of the second switch circuit at the same time, so that the data signal is written into the even-numbered rows and even-numbered columns. Pixels.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by another embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a pixel circuit provided by another embodiment of the present disclosure.
  • FIG. 4 is a timing control diagram of each gate line and each control signal line corresponding to FIG. 3;
  • FIG. 5 is a schematic structural diagram of a pixel circuit provided by another embodiment of the present disclosure.
  • FIG. 6 is a timing control diagram of each gate line and each control signal line corresponding to FIG. 5.
  • the embodiment of the present disclosure provides a pixel circuit, as shown in FIG. 1, including:
  • the rows of sub-pixels 110 are all electrically connected to the same second signal line 140, and the second direction is perpendicular to the first direction;
  • the plurality of data lines 150 extending along the second direction, wherein two first signal lines 130 and two second signal lines 140 connected to two adjacent columns of sub-pixels 120 are electrically connected to the same data line 150.
  • the odd-numbered rows of sub-pixels located in the same column are all electrically connected to the same first signal line
  • the even-numbered rows of sub-pixels located in the same column are all electrically connected to the same second signal line
  • two adjacent columns of sub-pixels are electrically connected to the same second signal line.
  • the two connected first signal lines and two second signal lines are electrically connected to the same data line, so that one data line can charge the two columns of sub-pixels, thereby avoiding insufficient channels when the integrated circuit provides data signals
  • the situation facilitates the development of high-resolution display devices. Therefore, the technical solution provided by the present disclosure can avoid the insufficient number of channels when the integrated circuit provides data signals, and facilitate the development of high-resolution display devices.
  • the plurality of sub-pixels 110 arranged in the above-mentioned array may be a plurality of sub-pixels of different colors arranged in an array on a base substrate in a preset order, and may include red sub-pixels, green sub-pixels, and blue sub-pixels. Of course, It may also include sub-pixels of other colors, such as white sub-pixels, yellow sub-pixels, etc., which are not limited here.
  • the number of the aforementioned gate lines 120 is equal to the number of rows of the sub-pixels 110 arranged in the array, and each row of sub-pixels is connected to each gate line 120 in a one-to-one correspondence.
  • the first direction is the same as the row direction in which the sub-pixels 110 are arranged.
  • the number of the first signal lines 130 is equal to the number of the second signal lines 140 and the number of columns of the sub-pixels 110 arranged in an array.
  • the sub-pixels located in odd rows in each column of sub-pixels are electrically connected to the first signal line 130
  • the sub-pixels in the even rows in each column of sub-pixels are electrically connected to the second signal line 140.
  • the second direction is the same as the column direction in which the sub-pixels 110 are arranged.
  • the above-mentioned data line 150 is located on one side of the plurality of sub-pixels arranged in the array in the column direction, and each data line 150 is respectively connected with two first signal lines 130 and two second signal lines 140, and these four are connected.
  • the signal line of provides a data signal for each sub-pixel in the two columns of sub-pixels corresponding to the data line 150.
  • the four signal lines connected to the same data line 150 time-share the data signal Vdata on the data line 150, that is, one signal line obtains the data signal Vdata on the data line 150 while the other three signal lines do not receive the data line.
  • the data signal Vdata on 150 is not limited to, one signal line.
  • a first switch circuit 210 is provided between each data line 150 and the connected first signal line 130, and each data line 150 is connected to the first signal line 130.
  • a second switch circuit 220 is respectively provided between the two signal lines 140;
  • Each first switch circuit 210 is used to control the connection or disconnection between the connected data line 150 and the connected first signal line 130;
  • Each second switch circuit 220 is used to control the connection or disconnection between the connected data line 150 and the connected second signal line 140.
  • each first switch circuit 210 is electrically connected to the data line 150, and the second end is electrically connected to the first signal line 130; the first end of each second switch circuit 220 is electrically connected to the data line 150.
  • the line 150 is electrically connected, and the second end is electrically connected to the second signal line 140.
  • One data line 150 connects two first switch circuits 210 and two second switch circuits 220 respectively.
  • the four switch circuits work in time-sharing.
  • One switch circuit works to direct the connected data line 150 to the connected first signal line 130 or the second signal line 140, and the other switch circuits disconnect the connected data line 150 from the connected first signal line.
  • One signal line 130 or the second signal line 140 realizes the time-sharing transmission of the data signal Vdata on the data line 150 by four signal lines.
  • the pixel circuit may further include four control signal lines 230 extending along the first direction, wherein the two control signal lines 230 are connected to the same data line 150 respectively.
  • the control terminals of the two connected first switch circuits 210 are electrically connected in a one-to-one correspondence, and the other two control signal lines 230 are respectively connected to the control terminals of the two second switch circuits 220 connected to the same data line 150 in a one-to-one correspondence;
  • the four control signal lines 230 are used to control the conduction or disconnection between the data line 150 and a connected first signal line 130 or second signal line 140 in a time-sharing manner.
  • control signal lines 230 are respectively electrically connected to the two first switch circuits 210 and the two second switch circuits 220, and each control signal line 230 is electrically connected to the control terminal of the respective connected switch circuit. It is used to control the operation of the respective connected switch circuits in a time-sharing manner.
  • control signal line 230 When one control signal line 230 provides a turn-on signal to make the switch circuit connected to it work, the remaining three control signal lines 230 provide turn-off signals, so that the respective connected switch circuits do not work, thereby realizing the time-sharing operation of the four switch circuits .
  • the four control signal lines 230 from top to bottom in FIG. 2 are numbered as No. 1 control signal line L1, No. 2 control signal line L2, No. 3 control signal line L3, and No. 4 control signal.
  • Line L4 the 4 switch circuits connected to the left data line 150 in Figure 2 are numbered from left to right as No. 1 switch circuit K1, No. 2 switch circuit K2, No. 3 switch circuit K3, and No. 4 switch circuit K4;
  • the control terminal of switch circuit K1 is electrically connected to control signal line L4
  • the control terminal of switch circuit K2 is electrically connected to control signal line L3
  • the control terminal of switch circuit K3 is electrically connected to control signal line 2.
  • the No. control signal line L2 is electrically connected, and the control end of the No. 4 switch circuit K4 is electrically connected to the No. 1 control signal line L1.
  • a first signal line 130 and a second signal line 140 may be provided between two consecutive columns of sub-pixels.
  • a third switch circuit 330 is also provided between the two first switch circuits 210 connected to the same data line and the data line, and the two second switch circuits 220 connected to the same data line are connected to the data line.
  • a fourth switch circuit 340 is also provided between the data lines;
  • the third switch circuit 330 is used to control the conduction or disconnection between the data line 150 and the two first switch circuits 210;
  • the fourth switch circuit 340 is used to control the conduction or disconnection between the data line 150 and the two second switch circuits 220.
  • a two-stage switch is used to control the conduction or disconnection of the four signal lines and the data line.
  • the first end of the third switch circuit 330 is electrically connected to the data line 150
  • the second end of the third switch circuit 330 is electrically connected to the first ends of the two first switch circuits 210;
  • the first end is electrically connected to the data line 150
  • the second end of the fourth switch circuit 340 is electrically connected to the first ends of the two second switch circuits 220, respectively.
  • the fourth switch circuit 340 does not work, that is, when the third switch circuit 330 turns on the connection between the data line 150 and the two first switch circuits 210, the fourth switch circuit 340 turns off the data line 150.
  • two columns of sub-pixels corresponding to one data line 150 include one column of sub-pixels located in odd-numbered columns and one column of sub-pixels located in even-numbered columns.
  • the two first signal lines 130 connected to the third switch circuit 330 include a first signal line 130A connecting sub-pixels located in odd rows and odd columns, and a first signal line 130A connecting sub-pixels located in odd rows and even columns.
  • the two second signal lines 140 connected to the fourth switch circuit 340 include the second signal line 140A connecting the sub-pixels located in even-numbered rows and odd-numbered columns and the second signal line 140A connecting the sub-pixels located in even-numbered rows and even-numbered columns.
  • the relationship of the switch circuits that need to be turned on for the sub-pixels corresponding to each position is as follows:
  • the pixel circuit may further include a first control signal line 301, a second control signal line 302, a third control signal line 303, and a fourth control signal line 304 extending along the first direction.
  • the first control signal line 301 is electrically connected to the control end of the third switch circuit 330 of each data line 150;
  • the second control signal line 302 is electrically connected to the control end of the fourth switch circuit 340 of each data line 150;
  • the third control signal line 303 is respectively connected to the control terminal of the first switch circuit 210A connected to the sub-pixels in odd rows and odd columns and the control terminal of the second switch circuit 220B connected to the sub-pixels in even rows and even columns. connect;
  • the fourth control signal line 304 is electrically connected to the control terminal of the second switch circuit 220A connected to the sub-pixels in even rows and odd columns and the control terminal of the first switch circuit 210B connected to the sub-pixels in odd rows and even columns. connect.
  • the first control signal line 301 is required to provide the turn-on signal to the third switch circuit 330 and the third control signal line 303 to provide the turn-on signal to the first switch circuit 210A, so that the first The signal line 130A is connected to the data line 150;
  • the first control signal line 301 is required to provide the turn-on signal to the third switch circuit 330 and the fourth control signal line 304 to provide the turn-on signal to the first switch circuit 210B, so that the first The signal line 130B is connected to the data line;
  • the second control signal line 302 is required to provide the turn-on signal to the fourth switch circuit 340 and the fourth control signal line 304 to provide the turn-on signal to the second switch circuit 220A, so that the second The signal line 140A is connected to the data line;
  • the second control signal line 302 is required to provide the turn-on signal to the fourth switch circuit 340 and the third control signal line 303 to provide the turn-on signal to the second switch circuit 220B, so that the second The signal line 140B is connected to the data line.
  • the timing signal diagrams of the first control signal line 301, the second control signal line 302, the third control signal line 303, the fourth control signal line 304 and each gate line are shown in FIG. 4.
  • two first signal lines 130 or two second signal lines 140 are provided between two adjacent columns of sub-pixels.
  • a fifth switch circuit 530 is also provided between the first switch circuit 210A and the second switch circuit 220A connecting one column of sub-pixels and the data line.
  • a sixth switch circuit 540 is also provided between the first switch circuit 210B and the second switch circuit 220B of the other column of sub-pixels and the data line 150;
  • the fifth switch circuit 530 is used to control the conduction or disconnection between the data line 150 and the connected first switch circuit 210A or the second switch circuit 220A;
  • the sixth switch circuit 540 is used to control the conduction or disconnection between the data line 150 and the connected first switch circuit 210B or the second switch circuit 220B.
  • a two-stage switch is used to control the conduction or disconnection of the four signal lines and the data line.
  • the first end of the fifth switch circuit 530 is electrically connected to the data line 150
  • the second end of the fifth switch circuit 530 is electrically connected to the first end of the first switch circuit 210A and the first end of the second switch circuit 220A, respectively.
  • Connection; the first end of the sixth switch circuit 540 is electrically connected to the data line 150, and the second end of the sixth switch circuit 540 is electrically connected to the first end of the first switch circuit 210B and the first end of the second switch circuit 220B, respectively .
  • the sixth switch circuit 540 does not work, that is, the fifth switch circuit 530 conducts electricity between the data line 150 and the first terminal of the first switch circuit 210A and the first terminal of the second switch circuit 220A.
  • the sixth switch circuit 540 turns off the connection between the data line 150 and the first end of the first switch circuit 210B and the first end of the second switch circuit 220B; similarly, the fifth switch circuit 540 is in operation.
  • the switch circuit 530 does not work, that is, when the sixth switch circuit 540 turns on the connection between the data line 150 and the first terminal of the first switch circuit 210B and the first terminal of the second switch circuit 220B, the fifth switch circuit 530 turns off The connection between the data line 150 and the first end of the first switch circuit 210A and the first end of the second switch circuit 220A.
  • two columns of sub-pixels corresponding to one data line include one column of sub-pixels located in odd-numbered columns and one column of sub-pixels located in even-numbered columns.
  • the first signal line 130 and the second signal line 140 connected to the fifth switch circuit 530 include a first signal line 130A connected to sub-pixels located in odd rows and odd columns, and a first signal line 130A connected to sub pixels located in even rows and odd columns.
  • the second signal line 140A of the sub-pixels in the column, the first signal line 130 and the second signal line 140 connected to the sixth switch circuit 540 include the first signal line 130B that connects the sub-pixels in odd rows and even columns and connects to For the second signal line 140B of the sub-pixels in even rows and even columns, the relationship of the switch circuits that need to be turned on for the sub-pixels corresponding to each position is as follows:
  • the pixel circuit may further include a first control signal line 501, a second control signal line 502, a third control signal line 503, and a fourth control signal line 504 extending along the first direction.
  • the first control signal line 501 is electrically connected to the control end of the fifth switch circuit 530 of each data line;
  • the second control signal line 502 is electrically connected to the control end of the sixth switch circuit 540 of each data line;
  • the third control signal line 503 is electrically connected to the control terminal of the first switch circuit 210A connected to the sub-pixels in odd rows and odd columns and the control terminal of the second switch circuit 210B connected to the sub-pixels in odd rows and even columns. connect;
  • the fourth control signal line 504 is electrically connected to the control terminal of the first switch circuit 220A connected to the sub-pixels in even rows and odd columns and the control terminal of the second switch circuit 220B connected to sub-pixels in even rows and even columns. connect.
  • the first control signal line 501 is required to provide the turn-on signal to the fifth switch circuit 530 and the third control signal line 503 to provide the turn-on signal to the first switch circuit 210A, so that the first The signal line 130A is connected to the data line 150;
  • the second control signal line 502 is required to provide the turn-on signal to the sixth switch circuit 540 and the third control signal line 503 to provide the turn-on signal to the first switch circuit 210B, so that the first The signal line 130B is connected to the data line 150;
  • the first control signal line 501 is required to provide the turn-on signal to the fifth switch circuit 530 and the fourth control signal line 504 to provide the turn-on signal to the second switch circuit 220A, so that the second The signal line 140A is connected to the data line 150;
  • the second control signal line 502 is required to provide the turn-on signal to the fourth switch circuit 540 and the fourth control signal line 504 to provide the turn-on signal to the second switch circuit 220B, so that the second The signal line 140B is connected to the data line.
  • the timing signal diagrams of the first control signal line 501, the second control signal line 502, the third control signal line 503, the fourth control signal line 504 and the gate lines are shown in FIG. 6.
  • the aforementioned first switch circuit 210, the second switch circuit 220, the third switch circuit 330, and the first switch circuit At least one of the four switch circuit 340, the fifth switch circuit 530, and the sixth switch circuit 540 includes a transistor, the first pole of the transistor is electrically connected to the data line, and the second pole of the transistor is connected to the sub-pixel. Electrically connected, the control electrode of the transistor is electrically connected to the control signal line.
  • the transistors can all be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is referred to as the first pole, and the other pole is referred to as the second pole.
  • the control electrode when the transistor is a triode, can be a base electrode, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base.
  • the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • each data line needs to refresh the voltage N times in one frame of display period.
  • N is larger, and the data line
  • the refresh rate of the upper voltage is too fast and the compensation time is short, which will cause the problem of insufficient compensation capability of the threshold voltage Vth in the pixel compensation circuit.
  • the sub-pixels in the same column are electrically connected to the data line 150 through a first signal line 130 and a second signal line 140, so that the first sub-pixels connected to the odd-numbered rows are electrically connected to the data line 150.
  • the signal line 130 refreshes the voltage N/2 times in one frame of display period
  • the second signal line 140 connected to the sub-pixels in even rows also refreshes the voltage N/2 times in one frame of display period.
  • the compensation time is extended, thereby avoiding the problem of insufficient compensation capability of the threshold voltage Vth in the pixel compensation circuit, thereby improving the display quality of the display device.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel.
  • the display device can be a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
  • the embodiments of the present disclosure also provide a method for driving a pixel circuit, which is applied to the above-mentioned pixel circuit, and the method includes:
  • a plurality of gate lines provide gate scan signals to sub-pixels located in different rows in a time-sharing manner.
  • each data line passes through the first signal line or the second signal connected to it.
  • the line time division provides corresponding data signals to two sub-pixels in the row of sub-pixels.
  • the odd-numbered rows of sub-pixels located in the same column are all electrically connected to the same first signal line
  • the even-numbered rows of sub-pixels located in the same column are all electrically connected to the same second signal line
  • two adjacent columns of sub-pixels are electrically connected to the same second signal line.
  • the two connected first signal lines and two second signal lines are electrically connected to the same data line, so that one data line can charge the two columns of sub-pixels, thereby avoiding insufficient channels when the integrated circuit provides data signals
  • the situation facilitates the development of high-resolution display devices. Therefore, the technical solution provided by the present disclosure can avoid the insufficient number of channels when the integrated circuit provides data signals, and facilitate the development of high-resolution display devices.
  • the plurality of sub-pixels 110 arranged in the above-mentioned array may be a plurality of sub-pixels of different colors arranged in an array on a base substrate in a preset order, and may include red sub-pixels, green sub-pixels, and blue sub-pixels. Sub-pixels, of course, may also include sub-pixels of other colors, such as white sub-pixels, yellow sub-pixels, etc., which are not limited here.
  • the number of the aforementioned gate lines 120 is equal to the number of rows of the sub-pixels 110 arranged in the array, and each row of sub-pixels is connected to each gate line 120 in a one-to-one correspondence.
  • the first direction is the same as the row direction in which the sub-pixels 110 are arranged.
  • the number of the first signal lines 130 is equal to the number of the second signal lines 140 and the number of columns of the sub-pixels 110 arranged in an array.
  • the sub-pixels located in odd rows in each column of sub-pixels are electrically connected to the first signal line 130
  • the sub-pixels in the even rows in each column of sub-pixels are electrically connected to the second signal line 140.
  • the second direction is the same as the column direction in which the sub-pixels 110 are arranged.
  • the above-mentioned data line 150 is located on one side of the plurality of sub-pixels arranged in the array in the column direction, and each data line 150 is respectively connected with two first signal lines 130 and two second signal lines 140, and these four are connected.
  • the signal line of provides a data signal for each sub-pixel in the two columns of sub-pixels corresponding to the data line 150.
  • the four signal lines connected to the same data line 150 time-share the data signal Vdata on the data line 150, that is, one signal line obtains the data signal Vdata on the data line 150 while the other three signal lines do not receive the data line.
  • the data signal Vdata on 150 is not limited to, one signal line.
  • a first switch circuit 210 is provided between each data line 150 and the connected first signal line 130, and each data line 150 is connected to the first signal line 130.
  • a second switch circuit 220 is respectively provided between the two signal lines 140;
  • Each first switch circuit 210 is used to control the connection or disconnection between the connected data line 150 and the connected first signal line 130;
  • Each second switch circuit 220 is used to control the connection or disconnection between the connected data line 150 and the connected second signal line 140.
  • each first switch circuit 210 is electrically connected to the data line 150, and the second end is electrically connected to the first signal line 130; the first end of each second switch circuit 220 is electrically connected to the data line 150.
  • the line 150 is electrically connected, and the second end is electrically connected to the second signal line 140.
  • One data line 150 connects two first switch circuits 210 and two second switch circuits 220 respectively.
  • the four switch circuits work in time-sharing.
  • One switch circuit works to direct the connected data line 150 to the connected first signal line 130 or the second signal line 140, and the other switch circuits disconnect the connected data line 150 from the connected first signal line.
  • One signal line 130 or the second signal line 140 realizes the time-sharing transmission of the data signal Vdata on the data line 150 by four signal lines.
  • the method includes:
  • each of the data lines provides corresponding data to two sub-pixels in the row of sub-pixels in a time-sharing manner through the first signal line or the second signal line connected to it.
  • Data signals including:
  • Control the first control signal line to send an on signal to the control terminal of the third switch circuit, and at the same time control the fourth control signal line to send an on signal to the control terminal of the first switch circuit, so that the data signal is written in the odd-numbered rows and even-numbered columns. Pixels; or,
  • each of the data lines provides corresponding corresponding data to two sub-pixels in the row of sub-pixels through the first signal line or the second signal line connected to it.
  • Data signals including:
  • Control the second control signal line to send an on signal to the control terminal of the fourth switch circuit, and at the same time control the third control signal line to send an on signal to the control terminal of the second switch circuit, so that the data signal is written into the even-numbered rows and even-numbered columns. Pixels.
  • a two-level switch is used to control the conduction or disconnection of the four signal lines and the data lines.
  • the first end of the third switch circuit 330 is electrically connected to the data line 150, and the second end of the third switch circuit 330 is electrically connected to the first ends of the two first switch circuits 210;
  • the first end is electrically connected to the data line 150, and the second end of the fourth switch circuit 340 is electrically connected to the first ends of the two second switch circuits 220, respectively.
  • the fourth switch circuit 340 When the third switch circuit 330 is working, the fourth switch circuit 340 does not work, that is, when the third switch circuit 330 turns on the connection between the data line 150 and the two first switch circuits 210, the fourth switch circuit 340 turns off the data line 150.
  • the third switch circuit 330 turns off the connection between the data line 150 and the two first switch circuits 210.
  • the first control signal line 301 is required to provide the turn-on signal to the third switch circuit 330 and the third control signal line 303 to provide the turn-on signal to the first switch circuit 210A, so that the first The signal line 130A is connected to the data line 150;
  • the first control signal line 301 is required to provide the turn-on signal to the third switch circuit 330 and the fourth control signal line 304 to provide the turn-on signal to the first switch circuit 210B, so that the first The signal line 130B is connected to the data line.
  • the second control signal line 302 is required to provide the turn-on signal to the fourth switch circuit 340 and the fourth control signal line 304 to provide the turn-on signal to the second switch circuit 220A, so that the second The signal line 140A is connected to the data line;
  • the second control signal line 302 is required to provide the turn-on signal to the fourth switch circuit 340 and the third control signal line 303 to provide the turn-on signal to the second switch circuit 220B, so that the second The signal line 140B is connected to the data line.
  • the timing signal diagrams of the first control signal line 301, the second control signal line 302, the third control signal line 303, the fourth control signal line 304 and each gate line are shown in FIG. 4.
  • the method includes:
  • each of the data lines provides corresponding data to two sub-pixels in the row of sub-pixels in a time-sharing manner through the first signal line or the second signal line connected to it.
  • Data signals including:
  • Control the first control signal line to send an on signal to the control terminal of the fifth switch circuit, and at the same time control the third control signal line to send an on signal to the control terminal of the first switch circuit, so that the data signal is written into the odd-numbered rows and odd-numbered columns.
  • Control the second control signal line to send an open signal to the control terminal of the sixth switch circuit, and at the same time control the third control signal line to send an open signal to the control terminal of the first switch circuit, so that the data signal is written into the sub-rows in odd rows and even columns. Pixels; or,
  • each of the data lines provides corresponding corresponding data to two sub-pixels in the row of sub-pixels through the first signal line or the second signal line connected to it.
  • Data signals including:
  • Control the second control signal line to send an open signal to the control end of the sixth switch circuit, and control the fourth control signal line to send an open signal to the control end of the second switch circuit at the same time, so that the data signal is written into the even-numbered rows and even-numbered columns. Pixels.
  • a two-level switch is used to control the conduction or disconnection of the four signal lines and the data lines.
  • the first end of the fifth switch circuit 530 is electrically connected to the data line 150
  • the second end of the fifth switch circuit 530 is electrically connected to the first end of the first switch circuit 210A and the first end of the second switch circuit 220A, respectively.
  • Connection; the first end of the sixth switch circuit 540 is electrically connected to the data line 150, and the second end of the sixth switch circuit 540 is electrically connected to the first end of the first switch circuit 210B and the first end of the second switch circuit 220B, respectively .
  • the sixth switch circuit 540 does not work, that is, the fifth switch circuit 530 conducts electricity between the data line 150 and the first terminal of the first switch circuit 210A and the first terminal of the second switch circuit 220A.
  • the sixth switch circuit 540 turns off the connection between the data line 150 and the first terminal of the first switch circuit 210B and the first terminal of the second switch circuit 220B; similarly, the sixth switch circuit 540 is working at the fifth terminal.
  • the switch circuit 530 does not work, that is, when the sixth switch circuit 540 turns on the connection between the data line 150 and the first terminal of the first switch circuit 210B and the first terminal of the second switch circuit 220B, the fifth switch circuit 530 turns off The connection between the data line 150 and the first end of the first switch circuit 210A and the first end of the second switch circuit 220A.
  • the first control signal line 501 is required to provide the turn-on signal to the fifth switch circuit 530 and the third control signal line 503 to provide the turn-on signal to the first switch circuit 210A, so that the first The signal line 130A is connected to the data line 150;
  • the second control signal line 502 is required to provide the turn-on signal to the sixth switch circuit 540 and the third control signal line 503 to provide the turn-on signal to the first switch circuit 210B, so that the first The signal line 130B is electrically connected to the data line 150.
  • the first control signal line 501 is required to provide the turn-on signal to the fifth switch circuit 530 and the fourth control signal line 504 to provide the turn-on signal to the second switch circuit 220A, so that the second The signal line 140A is connected to the data line 150;
  • the second control signal line 502 is required to provide the turn-on signal to the sixth switch circuit 540 and the fourth control signal line 504 to provide the turn-on signal to the second switch circuit 220B, so that the second The signal line 140B is connected to the data line.
  • the timing signal diagrams of the first control signal line 501, the second control signal line 502, the third control signal line 503, the fourth control signal line 504 and the gate lines are shown in FIG. 6.

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Abstract

本公开提供一种像素电路及其控制方法、和显示装置，其中，像素电路，包括：呈阵列排布的多个子像素；沿第一方向延伸的多根栅线，其中，位于同一行的子像素均与同一根栅线电连接；沿第二方向延伸的多根第一信号线和多根第二信号线，其中，位于同一列的奇数行子像素均与同一根第一信号线电连接，位于同一列的偶数行子像素均与同一根第二信号线电连接，所述第二方向与所述第一方向垂直；沿所述第二方向延伸的多根数据线，其中，相邻两列子像素所连的两根第一信号线和两根第二信号线均与同一根数据线电连接。本公开提供的像素电路及其控制方法、和显示装置，能够便于高分辨率显示装置的发展。

Description

像素电路及其控制方法、和显示装置
相关申请的交叉引用
本申请主张在2020年3月27日在中国提交的中国专利申请号No.202010228173.4的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其控制方法、和显示装置。
背景技术
随着科技的不断发展，人们通过显示装置进行娱乐、工作的时间越来越长，随之对于显示装置的屏幕分辨率的要求也越来越高。例如：为了满足虚拟现实(Virtual Reality，VR)游戏、或者增强现实(Augmented Reality，AR)游戏对画面的显示要求，需要不断提高显示装置的屏幕分辨率。
相关技术中，在显示装置的屏幕分辨率提升的过程中，像素电路中信号线的数量也会随之提升，出现信号线的数量大于单个集成电路(Integrated Circuit，IC)通道数的情况，出现集成电路通道数不足的问题。
发明内容
本公开实施例提供一种像素电路及其控制方法、和显示装置。
第一方面，本公开实施例提供一种像素电路，包括：
呈阵列排布的多个子像素；
沿第一方向延伸的多根栅线，其中，位于同一行的子像素均与同一根栅线电连接；
沿第二方向延伸的多根第一信号线和多根第二信号线，其中，位于同一列的奇数行子像素均与同一根第一信号线电连接，位于同一列的偶数行子像素均与同一根第二信号线电连接，所述第二方向与所述第一方向垂直；
沿所述第二方向延伸的多根数据线，其中，相邻两列子像素所连的两根 第一信号线和两根第二信号线均与同一根数据线电连接。
进一步地，每一数据线与相连的第一信号线之间分别设有第一开关电路，每一数据线与相连的第二信号线之间分别设有第二开关电路；
每一第一开关电路用于控制相连的数据线与相连的第一信号线之间导通或断开；
每一第二开关电路用于控制相连的数据线与相连的第二信号线之间导通或断开。
进一步地，还包括四根沿所述第一方向延伸的控制信号线，其中，两根控制信号线分别与同一根数据线相连的两个第一开关电路的控制端一一对应电连接，另两根控制信号线分别与同一根数据线相连的两个第二开关电路的控制端一一对应电连接；
四根控制信号线用于分时控制数据线与相连的一根第一信号线或第二信号线之间导通或断开。
进一步地，相连两列子像素之间设置有一根第一信号线和一根第二信号线。
进一步地，与同一根数据线相连的两个第一开关电路与数据线之间还设有第三开关电路，与同一根数据线相连的两个第二开关电路与数据线之间还设有第四开关电路；
所述第三开关电路用于控制数据线与两个第一开关电路之间的导通或断开；
所述第四开关电路用于控制数据线与两个第二开关电路之间的导通或断开。
进一步地，还包括沿所述第一方向延伸的第一控制信号线、第二控制信号线、第三控制信号线和第四控制信号线，其中，
所述第一控制信号线与每一根数据线的第三开关电路的控制端电连接；
所述第二控制信号线与每一根数据线的第四开关电路的控制端电连接；
所述第三控制信号线分别与位于奇数行且奇数列的子像素相连的第一开关电路的控制端和位于偶数行且偶数列的子像素相连的第二开关电路的控制端电连接；
所述第四控制信号线分别与位于偶数行且奇数列的子像素相连的第二开关电路的控制端和位于奇数行且偶数列的子像素相连的第一开关电路的控制端电连接。
进一步地，相连两列子像素之间设置有两根第一信号线或两根第二信号线。
进一步地，在一根数据线对应的两列子像素中，连接一列子像素的第一开关电路和第二开关电路与数据线之间还设有第五开关电路，连接另一列子像素的第一开关电路和第二开关电路与数据线之间还设有第六开关电路；
所述第五开关电路用于控制数据线与相连的第一开关电路或第二开关电路之间的导通或断开；
所述第六开关电路用于控制数据线与相连的第一开关电路或第二开关电路之间的导通或断开。
进一步地，还包括沿所述第一方向延伸的第一控制信号线、第二控制信号线、第三控制信号线和第四控制信号线，其中，
所述第一控制信号线与每一根数据线的第五开关电路的控制端电连接；
所述第二控制信号线与每一根数据线的第六开关电路的控制端电连接；
所述第三控制信号线分别与位于奇数行且奇数列的子像素相连的第一开关电路的控制端和位于奇数行且偶数列的子像素相连的第二开关电路的控制端电连接；
所述第四控制信号线分别与位于偶数行且奇数列的子像素相连的第一开关电路的控制端和位于偶数行且偶数列的子像素相连的第二开关电路的控制端电连接。
进一步地，所述第一开关电路、所述第二开关电路、所述第三开关电路和所述第四开关电路中至少一种开关电路包括晶体管，所述晶体管的第一极与所述数据线电连接，所述晶体管的第二极与子像素电连接，所述晶体管的控制极与控制信号线电连接。
第二方面，本公开实施例还提供一种显示装置，包括如上所述的像素电路。
第三方面，本公开实施例还提供一种像素电路的驱动方法，应用于如上 所述的像素电路，所述方法包括：
多根栅线分时向位于不同行的子像素提供栅极扫描信号，其中，在向一行子像素提供栅极扫描信号时，每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号。
进一步地，在向奇数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
控制第一控制信号线向第三开关电路的控制端发送开启信号，同时控制第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且奇数列的子像素；
控制第一控制信号线向第三开关电路的控制端发送开启信号，同时控制第四控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且偶数列的子像素；或者，
在向偶数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
控制第二控制信号线向第四开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且奇数列的子像素；
控制第二控制信号线向第四开关电路的控制端发送开启信号，同时控制第三控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且偶数列的子像素。
进一步地，在向奇数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
控制第一控制信号线向第五开关电路的控制端发送开启信号，同时控制第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且奇数列的子像素；
控制第二控制信号线向第六开关电路的控制端发送开启信号，同时控制 第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且偶数列的子像素；或者，
在向偶数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
控制第一控制信号线向第五开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且奇数列的子像素；
控制第二控制信号线向第六开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且偶数列的子像素。
附图说明
图1为本公开一实施例提供的像素电路的结构示意图；
图2为本公开另一实施例提供的像素电路的结构示意图；
图3为本公开另一实施例提供的像素电路的结构示意图；
图4为图3对应的各栅线和各控制信号线的时序控制图；
图5为本公开另一实施例提供的像素电路的结构示意图；
图6为图5对应的各栅线和各控制信号线的时序控制图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种像素电路，如图1所示，包括：
呈阵列排布的多个子像素110；
沿第一方向延伸的多根栅线120，其中，位于同一行的子像素110均与同一根栅线120电连接；
沿第二方向延伸的多根第一信号线130和多根第二信号线140，其中，位于同一列的奇数行子像素110均与同一根第一信号线130电连接，位于同一列的偶数行子像素110均与同一根第二信号线140电连接，所述第二方向与所述第一方向垂直；
沿所述第二方向延伸的多根数据线150，其中，相邻两列子像素120所连的两根第一信号线130和两根第二信号线140均与同一根数据线150电连接。
本公开实施例中，通过位于同一列的奇数行子像素均与同一根第一信号线电连接，位于同一列的偶数行子像素均与同一根第二信号线电连接，相邻两列子像素所连的两根第一信号线和两根第二信号线均与同一根数据线电连接，使得一根数据线能够对两列子像素进行充电，从而避免了集成电路提供数据信号时通道数不足的情况，便于高分辨率显示装置的发展。因此，本公开提供的技术方案能够避免集成电路提供数据信号时通道数不足的情况，便于高分辨率显示装置的发展。
上述阵列排布的多个子像素110可以是多个按照预设顺序在衬底基板上阵列排布的不同颜色的子像素，可以包括红色子像素、绿色子像素和蓝色子像素，当然，也还可以包括其他颜色的子像素，例如：白色子像素、黄色子像素等等，此处不作限定。
上述栅线120的数量与阵列排布的子像素110的行数相等，各行子像素一一对应连接各根栅线120。本公开实施例中，第一方向与子像素110排布的行方向相同。
上述第一信号线130的数量等于上述第二信号线140的数量，且等于阵列排布的子像素110的列数，每一列子像素中位于奇数行的子像素与第一信号线130电连接，每一列子像素中位于偶数行的子像素与第二信号线140电连接。本公开实施例中，第二方向与子像素110排布的列方向相同。
上述数据线150位于阵列排布的多个子像素在列方向上的一侧，每一根数据线150分别两根第一信号线130和两根第二信号线140点连接，由这四根相连的信号线为数据线150所对应的两列子像素中的每一子像素提供数据信号。
其中，与同一根数据线150相连的四根信号线分时传输数据线150上的数据信号Vdata，即一根信号线得到数据线150上的数据信号Vdata的同时其他三根信号线不得到数据线150上的数据信号Vdata。
在本公开一可选的实施例中，如图2所示，每一数据线150与相连的第一信号线130之间分别设有第一开关电路210，每一数据线150与相连的第二信号线140之间分别设有第二开关电路220；
每一第一开关电路210用于控制相连的数据线150与相连的第一信号线130之间导通或断开；
每一第二开关电路220用于控制相连的数据线150与相连的第二信号线140之间导通或断开。
即本实施例中，每一个第一开关电路210的第一端与数据线150电连接，且第二端与第一信号线130电连接；每一个第二开关电路220的第一端与数据线150电连接，且第二端与第二信号线140电连接。一根数据线150分别连接两个第一开关电路210和两个第二开关电路220。
四个开关电路分时工作，一个开关电路工作是指导通相连的数据线150与相连的第一信号线130或第二信号线140，且其他开关电路断开相连的数据线150与相连的第一信号线130或第二信号线140，从而实现四根信号线分时传输数据线150上的数据信号Vdata。
在一可选的实施方式中，如图2所示，像素电路还可以包括四根沿所述第一方向延伸的控制信号线230，其中，两根控制信号线230分别与同一根数据线150相连的两个第一开关电路210的控制端一一对应电连接，另两根控制信号线230分别与同一根数据线150相连的两个第二开关电路220的控制端一一对应电连接；
四根控制信号线230用于分时控制数据线150与相连的一根第一信号线130或第二信号线140之间导通或断开。
本实施方式中，四根控制信号线230分别与两个第一开关电路210和两个第二开关电路220电连接，每一根控制信号线230与各自相连的开关电路的控制端电连接，用于分时控制各自相连的开关电路工作。
在一根控制信号线230提供开启信号，使得与其相连的开关电路工作时， 其余的三根控制信号线230提供关断信号，使得各自相连的开关电路不工作，从而实现四个开关电路分时工作。
如图2所示，将图2从上至下的方向分别将四根控制信号线230编号为1号控制信号线L1、2号控制信号线L2、3号控制信号线L3和4号控制信号线L4，将图2中左侧数据线150连接的4个开关电路按从左至右的方向分别编号为1号开关电路K1、2号开关电路K2、3号开关电路K3和4号开关电路K4；其中，1号开关电路K1的控制端与4号控制信号线L4电连接，2号开关电路K2的控制端与3号控制信号线L3电连接，3号开关电路K3的控制端与2号控制信号线L2电连接，4号开关电路K4的控制端与1号控制信号线L1电连接。
在另一可选的实施方式中，如图3所示，相连两列子像素之间可以设置有一根第一信号线130和一根第二信号线140。
请结合图3所示，与同一根数据线相连的两个第一开关电路210与数据线之间还设有第三开关电路330，与同一根数据线相连的两个第二开关电路220与数据线之间还设有第四开关电路340；
所述第三开关电路330用于控制数据线150与两个第一开关电路210之间的导通或断开；
所述第四开关电路340用于控制数据线150与两个第二开关电路220之间的导通或断开。
本实施方式中，通过两级开关来控制4根信号线与数据线的导通或断开。具体的，第三开关电路330的第一端与数据线150电连接，第三开关电路330的第二端分别与两个第一开关电路210的第一端电连接；第四开关电路340的第一端与数据线150电连接，第四开关电路340的第二端分别与两个第二开关电路220的第一端电连接。
第三开关电路330工作时第四开关电路340不工作，即第三开关电路330导通数据线150与两个第一开关电路210之间的连接时，第四开关电路340关断数据线150与两个第二开关电路220之间的连接；同样的，第四开关电路340工作时第三开关电路330不工作，即第四开关电路340导通数据线150与两个第二开关电路220之间的连接时，第三开关电路330关断数据线150 与两个第一开关电路210之间的连接。
本实施方式中，一根数据线150对应的两列子像素包括一列位于奇数列的子像素和一列位于偶数列的子像素。如图3所示，假设与第三开关电路330连接的两根第一信号线130包括连接位于奇数行且奇数列的子像素的第一信号线130A和连接位于奇数行且偶数列的子像素的第一信号线130B，与第四开关电路340连接的两根第二信号线140包括连接位于偶数行且奇数列的子像素的第二信号线140A和连接位于偶数行且偶数列的子像素的第二信号线140B，则在对应每一种位置的子像素所需要导通的开关电路关系如下：
向位于奇数行且奇数列的子像素提供数据信号，需要控制第三开关电路330和连接第一信号线130A的第一开关电路210A工作；
向位于奇数行且偶数列的子像素提供数据信号，需要控制第三开关电路330和连接第一信号线130B的第一开关电路210B工作；
向位于偶数行且奇数列的子像素提供数据信号，需要控制第四开关电路340和连接第二信号线140A的第二开关电路220A工作；
向位于偶数行且偶数列的子像素提供数据信号，需要控制第四开关电路340和连接第二信号线140B的第二开关电路220B工作。
进一步地，如图3所示，像素电路还可以包括沿所述第一方向延伸的第一控制信号线301、第二控制信号线302、第三控制信号线303和第四控制信号线304，其中，
所述第一控制信号线301与每一根数据线150的第三开关电路330的控制端电连接；
所述第二控制信号线302与每一根数据线150的第四开关电路340的控制端电连接；
所述第三控制信号线303分别与位于奇数行且奇数列的子像素相连的第一开关电路210A的控制端和位于偶数行且偶数列的子像素相连的第二开关电路220B的控制端电连接；
所述第四控制信号线304分别与位于偶数行且奇数列的子像素相连的第二开关电路220A的控制端和位于奇数行且偶数列的子像素相连的第一开关电路210B的控制端电连接。
根据本实施方式中各位置子像素与各开关电路的关系，以及上述每一根控制信号线与开关电路的连接关系，可以得出：
向位于奇数行且奇数列的子像素提供数据信号，需要第一控制信号线301向第三开关电路330提供开启信号且第三控制信号线303向第一开关电路210A提供开启信号，使得第一信号线130A与数据线150导通；
向位于奇数行且偶数列的子像素提供数据信号，需要第一控制信号线301向第三开关电路330提供开启信号且第四控制信号线304向第一开关电路210B提供开启信号，使得第一信号线130B与数据线导通；
向位于偶数行且奇数列的子像素提供数据信号，需要第二控制信号线302向第四开关电路340提供开启信号且第四控制信号线304向第二开关电路220A提供开启信号，使得第二信号线140A与数据线导通；
向位于偶数行且奇数列的子像素提供数据信号，需要第二控制信号线302向第四开关电路340提供开启信号且第三控制信号线303向第二开关电路220B提供开启信号，使得第二信号线140B与数据线导通。
其中，第一控制信号线301、第二控制信号线302、第三控制信号线303和第四控制信号线304与各栅线的时序信号图如图4所示。
在另一可选的实施方式中，如图5所示，相邻两列子像素之间设置有两根第一信号线130或两根第二信号线140。
如图5所示，在一根数据线150对应的两列子像素中，连接一列子像素的第一开关电路210A和第二开关电路220A与数据线之间还设有第五开关电路530，连接另一列子像素的第一开关电路210B和第二开关电路220B与数据线150之间还设有第六开关电路540；
所述第五开关电路530用于控制数据线150与相连的第一开关电路210A或第二开关电路220A之间的导通或断开；
所述第六开关电路540用于控制数据线150与相连的第一开关电路210B或第二开关电路220B之间的导通或断开。
本实施方式中，通过两级开关来控制4根信号线与数据线的导通或断开。具体的，第五开关电路530的第一端与数据线150电连接，第五开关电路530的第二端分别与第一开关电路210A的第一端和第二开关电路220A的第一端 电连接；第六开关电路540的第一端与数据线150电连接，第六开关电路540的第二端分别与第一开关电路210B的第一端和第二开关电路220B的第一端电连接。
第五开关电路530工作时第六开关电路540不工作，即第五开关电路530导通数据线150与第一开关电路210A的第一端和第二开关电路220A的第一端之间的电连接时，第六开关电路540关断数据线150与第一开关电路210B的第一端和第二开关电路220B的第一端之间的连接；同样的，第六开关电路540工作时第五开关电路530不工作，即第六开关电路540导通数据线150与第一开关电路210B的第一端和第二开关电路220B的第一端之间的连接时，第五开关电路530关断数据线150与第一开关电路210A的第一端和第二开关电路220A的第一端之间的连接。
本实施方式中，一根数据线对应的两列子像素包括一列位于奇数列的子像素和一列位于偶数列的子像素。如图5所示，假设与第五开关电路530连接的第一信号线130和第二信号线140包括连接位于奇数行且奇数列的子像素的第一信号线130A和连接位于偶数行且奇数列的子像素的第二信号线140A，与第六开关电路540连接的第一信号线130和第二信号线140包括连接位于奇数行且偶数列的子像素的第一信号线130B和连接位于偶数行且偶数列的子像素的第二信号线140B，则在对应每一种位置的子像素所需要导通的开关电路关系如下：
向位于奇数行且奇数列的子像素提供数据信号，需要控制第五开关电路530和连接第一信号线130A的第一开关电路210A工作；
向位于奇数行且偶数列的子像素提供数据信号，需要控制第四开关电路540和连接第一信号线130B的第一开关电路210B工作；
向位于偶数行且奇数列的子像素提供数据信号，需要控制第三开关电路530和连接第二信号线140A的第二开关电路220A工作；
向位于偶数行且偶数列的子像素提供数据信号，需要控制第四开关电路540和连接第二信号线140B的第二开关电路220B工作。
进一步地，如图5所示，像素电路还可以包括沿所述第一方向延伸的第一控制信号线501、第二控制信号线502、第三控制信号线503和第四控制信 号线504，其中，
所述第一控制信号线501与每一根数据线的第五开关电路530的控制端电连接；
所述第二控制信号线502与每一根数据线的第六开关电路540的控制端电连接；
所述第三控制信号线503分别与位于奇数行且奇数列的子像素相连的第一开关电路210A的控制端和位于奇数行且偶数列的子像素相连的第二开关电路210B的控制端电连接；
所述第四控制信号线504分别与位于偶数行且奇数列的子像素相连的第一开关电路220A的控制端和位于偶数行且偶数列的子像素相连的第二开关电路220B的控制端电连接。
根据本实施方式中各位置子像素与各开关电路的关系，以及上述每一根控制信号线与开关电路的连接关系，可以得出：
向位于奇数行且奇数列的子像素提供数据信号，需要第一控制信号线501向第五开关电路530提供开启信号且第三控制信号线503向第一开关电路210A提供开启信号，使得第一信号线130A与数据线150导通；
向位于奇数行且偶数列的子像素提供数据信号，需要第二控制信号线502向第六开关电路540提供开启信号且第三控制信号线503向第一开关电路210B提供开启信号，使得第一信号线130B与数据线150导通；
向位于偶数行且奇数列的子像素提供数据信号，需要第一控制信号线501向第五开关电路530提供开启信号且第四控制信号线504向第二开关电路220A提供开启信号，使得第二信号线140A与数据线150导通；
向位于偶数行且偶数列的子像素提供数据信号，需要第二控制信号线502向第四开关电路540提供开启信号且第四控制信号线504向第二开关电路220B提供开启信号，使得第二信号线140B与数据线导通。
其中，第一控制信号线501、第二控制信号线502、第三控制信号线503和第四控制信号线504与各栅线的时序信号图如图6所示。
另外，本公开实施例中，如图2、图3和图5所示，上述所提到的第一开关电路210、所述第二开关电路220、所述第三开关电路330、所述第四开 关电路340、第五开关电路530和第六开关电路540中至少一种开关电路包括晶体管，所述晶体管的第一极与所述数据线电连接，所述晶体管的第二极与子像素电连接，所述晶体管的控制极与控制信号线电连接。
晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
另外，相关技术中，假设阵列排布的子像素有N行，则每一根数据线需要在一帧显示时间段中刷新N次电压，在屏幕分辨率较大时，N较大，数据线上电压的刷新速度太快，补偿时间较短，会导致像素补偿电路中的阈值电压Vth补偿能力不足的问题。
而本公开各个实施例中，通过同一列的子像素分别通过一根第一信号线130和一根第二信号线140与数据线150电连接，这样与位于奇数行的子像素相连的第一信号线130在一帧显示时间段中刷新N/2次电压，同样与位于偶数行的子像素相连的第二信号线140在一帧显示时间段中刷新N/2次电压，相较与相关技术中延长了补偿时间，从而避免像素补偿电路中的阈值电压Vth补偿能力不足的问题，从而提高显示装置的显示质量。
本公开实施例还提供了一种显示装置，包括如上所述的显示面板。
显示装置可以是显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
本公开实施例还提供一种像素电路的驱动方法，应用于如上所述的像素电路，所述方法包括：
多根栅线分时向位于不同行的子像素提供栅极扫描信号，其中，在向一行子像素提供栅极扫描信号时，每一根数据线通过与其相连的第一信号线或 第二信号线分时向该行子像素中的两个子像素提供对应的数据信号。
本公开实施例中，通过位于同一列的奇数行子像素均与同一根第一信号线电连接，位于同一列的偶数行子像素均与同一根第二信号线电连接，相邻两列子像素所连的两根第一信号线和两根第二信号线均与同一根数据线电连接，使得一根数据线能够对两列子像素进行充电，从而避免了集成电路提供数据信号时通道数不足的情况，便于高分辨率显示装置的发展。因此，本公开提供的技术方案能够避免集成电路提供数据信号时通道数不足的情况，便于高分辨率显示装置的发展。
如图1所示，上述阵列排布的多个子像素110可以是多个按照预设顺序在衬底基板上阵列排布的不同颜色的子像素，可以包括红色子像素、绿色子像素和蓝色子像素，当然，也还可以包括其他颜色的子像素，例如：白色子像素、黄色子像素等等，此处不作限定。
上述栅线120的数量与阵列排布的子像素110的行数相等，各行子像素一一对应连接各根栅线120。本公开实施例中，第一方向与子像素110排布的行方向相同。
上述第一信号线130的数量等于上述第二信号线140的数量，且等于阵列排布的子像素110的列数，每一列子像素中位于奇数行的子像素与第一信号线130电连接，每一列子像素中位于偶数行的子像素与第二信号线140电连接。本公开实施例中，第二方向与子像素110排布的列方向相同。
上述数据线150位于阵列排布的多个子像素在列方向上的一侧，每一根数据线150分别两根第一信号线130和两根第二信号线140点连接，由这四根相连的信号线为数据线150所对应的两列子像素中的每一子像素提供数据信号。
其中，与同一根数据线150相连的四根信号线分时传输数据线150上的数据信号Vdata，即一根信号线得到数据线150上的数据信号Vdata的同时其他三根信号线不得到数据线150上的数据信号Vdata。
在本公开一可选的实施例中，如图2所示，每一数据线150与相连的第一信号线130之间分别设有第一开关电路210，每一数据线150与相连的第二信号线140之间分别设有第二开关电路220；
每一第一开关电路210用于控制相连的数据线150与相连的第一信号线130之间导通或断开；
每一第二开关电路220用于控制相连的数据线150与相连的第二信号线140之间导通或断开。
即本实施例中，每一个第一开关电路210的第一端与数据线150电连接，且第二端与第一信号线130电连接；每一个第二开关电路220的第一端与数据线150电连接，且第二端与第二信号线140电连接。一根数据线150分别连接两个第一开关电路210和两个第二开关电路220。
四个开关电路分时工作，一个开关电路工作是指导通相连的数据线150与相连的第一信号线130或第二信号线140，且其他开关电路断开相连的数据线150与相连的第一信号线130或第二信号线140，从而实现四根信号线分时传输数据线150上的数据信号Vdata。
在一可选的实施例中，应用于如图3所示的像素电路，所述方法包括：
在向奇数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
控制第一控制信号线向第三开关电路的控制端发送开启信号，同时控制第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且奇数列的子像素；
控制第一控制信号线向第三开关电路的控制端发送开启信号，同时控制第四控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且偶数列的子像素；或者，
在向偶数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
控制第二控制信号线向第四开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且奇数列的子像素；
控制第二控制信号线向第四开关电路的控制端发送开启信号，同时控制 第三控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且偶数列的子像素。
本实施例中，通过两级开关来控制4根信号线与数据线的导通或断开。具体的，第三开关电路330的第一端与数据线150电连接，第三开关电路330的第二端分别与两个第一开关电路210的第一端电连接；第四开关电路340的第一端与数据线150电连接，第四开关电路340的第二端分别与两个第二开关电路220的第一端电连接。
第三开关电路330工作时第四开关电路340不工作，即第三开关电路330导通数据线150与两个第一开关电路210之间的连接时，第四开关电路340关断数据线150与两个第二开关电路220之间的连接；同样的，第四开关电路340工作时第三开关电路330不工作，即第四开关电路340导通数据线150与两个第二开关电路220之间的连接时，第三开关电路330关断数据线150与两个第一开关电路210之间的连接。
在向奇数行子像素提供栅极扫描信号的情况下，包括：
向位于奇数行且奇数列的子像素提供数据信号，需要第一控制信号线301向第三开关电路330提供开启信号且第三控制信号线303向第一开关电路210A提供开启信号，使得第一信号线130A与数据线150导通；
向位于奇数行且偶数列的子像素提供数据信号，需要第一控制信号线301向第三开关电路330提供开启信号且第四控制信号线304向第一开关电路210B提供开启信号，使得第一信号线130B与数据线导通。
在向偶数行子像素提供栅极扫描信号的情况下，包括：
向位于偶数行且奇数列的子像素提供数据信号，需要第二控制信号线302向第四开关电路340提供开启信号且第四控制信号线304向第二开关电路220A提供开启信号，使得第二信号线140A与数据线导通；
向位于偶数行且奇数列的子像素提供数据信号，需要第二控制信号线302向第四开关电路340提供开启信号且第三控制信号线303向第二开关电路220B提供开启信号，使得第二信号线140B与数据线导通。
其中，第一控制信号线301、第二控制信号线302、第三控制信号线303和第四控制信号线304与各栅线的时序信号图如图4所示。
在另一可选的实施例中，应用于如图5所示的像素电路，所述方法包括：
在向奇数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
控制第一控制信号线向第五开关电路的控制端发送开启信号，同时控制第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且奇数列的子像素；
控制第二控制信号线向第六开关电路的控制端发送开启信号，同时控制第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且偶数列的子像素；或者，
在向偶数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
控制第一控制信号线向第五开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且奇数列的子像素；
控制第二控制信号线向第六开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且偶数列的子像素。
本实施例中，通过两级开关来控制4根信号线与数据线的导通或断开。具体的，第五开关电路530的第一端与数据线150电连接，第五开关电路530的第二端分别与第一开关电路210A的第一端和第二开关电路220A的第一端电连接；第六开关电路540的第一端与数据线150电连接，第六开关电路540的第二端分别与第一开关电路210B的第一端和第二开关电路220B的第一端电连接。
第五开关电路530工作时第六开关电路540不工作，即第五开关电路530导通数据线150与第一开关电路210A的第一端和第二开关电路220A的第一端之间的电连接时，第六开关电路540关断数据线150与第一开关电路210B的第一端和第二开关电路220B的第一端之间的连接；同样的，第六开关电路 540工作时第五开关电路530不工作，即第六开关电路540导通数据线150与第一开关电路210B的第一端和第二开关电路220B的第一端之间的连接时，第五开关电路530关断数据线150与第一开关电路210A的第一端和第二开关电路220A的第一端之间的连接。
在向奇数行子像素提供栅极扫描信号的情况下，包括：
向位于奇数行且奇数列的子像素提供数据信号，需要第一控制信号线501向第五开关电路530提供开启信号且第三控制信号线503向第一开关电路210A提供开启信号，使得第一信号线130A与数据线150导通；
向位于奇数行且偶数列的子像素提供数据信号，需要第二控制信号线502向第六开关电路540提供开启信号且第三控制信号线503向第一开关电路210B提供开启信号，使得第一信号线130B与数据线150导通。
在向偶数行子像素提供栅极扫描信号的情况下，包括：
向位于偶数行且奇数列的子像素提供数据信号，需要第一控制信号线501向第五开关电路530提供开启信号且第四控制信号线504向第二开关电路220A提供开启信号，使得第二信号线140A与数据线150导通；
向位于偶数行且奇数列的子像素提供数据信号，需要第二控制信号线502向第六开关电路540提供开启信号且第四控制信号线504向第二开关电路220B提供开启信号，使得第二信号线140B与数据线导通。
其中，第一控制信号线501、第二控制信号线502、第三控制信号线503和第四控制信号线504与各栅线的时序信号图如图6所示。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
以上所述仅是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视本公开的保护范围。

Claims (14)

  1. 一种像素电路，包括：
    呈阵列排布的多个子像素；
    沿第一方向延伸的多根栅线，其中，位于同一行的子像素均与同一根栅线电连接；
    沿第二方向延伸的多根第一信号线和多根第二信号线，其中，位于同一列的奇数行子像素均与同一根第一信号线电连接，位于同一列的偶数行子像素均与同一根第二信号线电连接，所述第二方向与所述第一方向垂直；
    沿所述第二方向延伸的多根数据线，其中，相邻两列子像素所连的两根第一信号线和两根第二信号线均与同一根数据线电连接。
  2. 根据权利要求1所述的像素电路，其中，每一数据线与相连的第一信号线之间分别设有第一开关电路，每一数据线与相连的第二信号线之间分别设有第二开关电路；
    每一第一开关电路用于控制相连的数据线与相连的第一信号线之间导通或断开；
    每一第二开关电路用于控制相连的数据线与相连的第二信号线之间导通或断开。
  3. 根据权利要求2所述的像素电路，其中，还包括四根沿所述第一方向延伸的控制信号线，其中，两根控制信号线分别与同一根数据线相连的两个第一开关电路的控制端一一对应电连接，另两根控制信号线分别与同一根数据线相连的两个第二开关电路的控制端一一对应电连接；
    四根控制信号线用于分时控制数据线与相连的一根第一信号线或第二信号线之间导通或断开。
  4. 根据权利要求2所述的像素电路，其中，相连两列子像素之间设置有一根第一信号线和一根第二信号线。
  5. 根据权利要求4所述的像素电路，其中，与同一根数据线相连的两个第一开关电路与数据线之间还设有第三开关电路，与同一根数据线相连的两个第二开关电路与数据线之间还设有第四开关电路；
    所述第三开关电路用于控制数据线与两个第一开关电路之间的导通或断开；
    所述第四开关电路用于控制数据线与两个第二开关电路之间的导通或断开。
  6. 根据权利要求5所述的像素电路，其中，还包括沿所述第一方向延伸的第一控制信号线、第二控制信号线、第三控制信号线和第四控制信号线，其中，
    所述第一控制信号线与每一根数据线的第三开关电路的控制端电连接；
    所述第二控制信号线与每一根数据线的第四开关电路的控制端电连接；
    所述第三控制信号线分别与位于奇数行且奇数列的子像素相连的第一开关电路的控制端和位于偶数行且偶数列的子像素相连的第二开关电路的控制端电连接；
    所述第四控制信号线分别与位于偶数行且奇数列的子像素相连的第二开关电路的控制端和位于奇数行且偶数列的子像素相连的第一开关电路的控制端电连接。
  7. 根据权利要求2所述的像素电路，其中，相邻两列子像素之间设置有两根第一信号线或两根第二信号线。
  8. 根据权利要求7所述的像素电路，其中，在一根数据线对应的两列子像素中，连接一列子像素的第一开关电路和第二开关电路与数据线之间还设有第五开关电路，连接另一列子像素的第一开关电路和第二开关电路与数据线之间还设有第六开关电路；
    所述第五开关电路用于控制数据线与相连的第一开关电路或第二开关电路之间的导通或断开；
    所述第六开关电路用于控制数据线与相连的第一开关电路或第二开关电路之间的导通或断开。
  9. 根据权利要求8所述的像素电路，其中，还包括沿所述第一方向延伸的第一控制信号线、第二控制信号线、第三控制信号线和第四控制信号线，其中，
    所述第一控制信号线与每一根数据线的第五开关电路的控制端电连接；
    所述第二控制信号线与每一根数据线的第六开关电路的控制端电连接；
    所述第三控制信号线分别与位于奇数行且奇数列的子像素相连的第一开关电路的控制端和位于奇数行且偶数列的子像素相连的第二开关电路的控制端电连接；
    所述第四控制信号线分别与位于偶数行且奇数列的子像素相连的第一开关电路的控制端和位于偶数行且偶数列的子像素相连的第二开关电路的控制端电连接。
  10. 根据权利要求2-9所述的像素电路，其中，所述第一开关电路、所述第二开关电路、所述第三开关电路和所述第四开关电路中至少一种开关电路包括晶体管，所述晶体管的第一极与所述数据线电连接，所述晶体管的第二极与子像素电连接，所述晶体管的控制极与控制信号线电连接。
  11. 一种显示装置，包括如权利要求1-10中任一项所述的像素电路。
  12. 一种像素电路的驱动方法，其中，应用于如权利要求1-10中任一项所述的像素电路，所述方法包括：
    多根栅线分时向位于不同行的子像素提供栅极扫描信号，其中，在向一行子像素提供栅极扫描信号时，每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号。
  13. 根据权利要求12所述的方法，其中，应用于如权利要求6所述的像素电路；
    在向奇数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
    控制第一控制信号线向第三开关电路的控制端发送开启信号，同时控制第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且奇数列的子像素；
    控制第一控制信号线向第三开关电路的控制端发送开启信号，同时控制第四控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且偶数列的子像素；或者，
    在向偶数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过 与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
    控制第二控制信号线向第四开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且奇数列的子像素；
    控制第二控制信号线向第四开关电路的控制端发送开启信号，同时控制第三控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且偶数列的子像素。
  14. 根据权利要求12所述的方法，其中，应用于如权利要求9所述的像素电路；
    在向奇数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
    控制第一控制信号线向第五开关电路的控制端发送开启信号，同时控制第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且奇数列的子像素；
    控制第二控制信号线向第六开关电路的控制端发送开启信号，同时控制第三控制信号线向第一开关电路的控制端发送开启信号，使得数据信号写入位于奇数行且偶数列的子像素；或者，
    在向偶数行子像素提供栅极扫描信号的情况下，所述每一根数据线通过与其相连的第一信号线或第二信号线分时向该行子像素中的两个子像素提供对应的数据信号，包括：
    控制第一控制信号线向第五开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且奇数列的子像素；
    控制第二控制信号线向第六开关电路的控制端发送开启信号，同时控制第四控制信号线向第二开关电路的控制端发送开启信号，使得数据信号写入位于偶数行且偶数列的子像素。
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