WO2019114327A1 - 像素电路、显示面板及显示装置 - Google Patents

像素电路、显示面板及显示装置 Download PDF

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Publication number
WO2019114327A1
WO2019114327A1 PCT/CN2018/103347 CN2018103347W WO2019114327A1 WO 2019114327 A1 WO2019114327 A1 WO 2019114327A1 CN 2018103347 W CN2018103347 W CN 2018103347W WO 2019114327 A1 WO2019114327 A1 WO 2019114327A1
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Prior art keywords
thin film
film transistor
pixel circuit
pole
coupled
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PCT/CN2018/103347
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English (en)
French (fr)
Inventor
郝学光
吴新银
马永达
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京东方科技集团股份有限公司
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Priority to US16/342,039 priority Critical patent/US10978535B2/en
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2019562386A priority patent/JP7186725B2/ja
Priority to EP18874997.2A priority patent/EP3726582A4/en
Publication of WO2019114327A1 publication Critical patent/WO2019114327A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a display panel, and a display device.
  • OLEDs organic electroluminescent display devices
  • LCDs liquid crystal displays
  • OLED displays have many advantages such as high brightness, high color gamut, high contrast, and thinness.
  • the OLED display currently applied on the market has many problems due to the structure of the pixel driving circuit and the pixel arrangement structure, resulting in poor display quality.
  • an embodiment of the present disclosure provides a pixel circuit, including:
  • Driving a thin film transistor configured to provide a driving current to the light emitting device; a second pole of the driving thin film transistor coupled to a first pole of the light emitting device;
  • the light-emitting control thin film transistor is configured to control the light-emitting device to emit light; the first pole of the light-emitting control thin film transistor is coupled to the high-voltage signal line, and the second pole is coupled to the first pole of the driving thin film transistor;
  • a switching thin film transistor configured to control a data voltage to be written to a gate of the driving thin film transistor
  • a reset thin film transistor configured to reset a gate potential of the driving thin film transistor
  • a storage capacitor a storage capacitor, a first pole of the storage capacitor coupled to a control electrode of the driving thin film transistor, and a second pole coupled to a second pole of the driving thin film transistor.
  • a control electrode of the light emission control thin film transistor is coupled to the light emission control signal line.
  • the first pole of the switching thin film transistor is coupled to the data signal line
  • the second pole is coupled to the control electrode of the driving thin film transistor
  • the control electrode is The scan signal lines are coupled.
  • a first pole of the reset thin film transistor is coupled to an initial voltage signal line, and a second pole is coupled to a second pole of the switching thin film transistor, and is controlled.
  • the pole is coupled to the reset signal line.
  • the first extreme source electrode or the drain electrode of the driving thin film transistor the first extreme anode of the light emitting device.
  • the method further includes: a brightness enhancement capacitor, the first pole of the brightness enhancement capacitor is coupled to the high voltage signal line, and the second pole and the light emitting device The first pole is coupled.
  • the brightness enhancement capacitor includes: a first metal pattern, a second metal pattern, and located between the first metal pattern and the second metal pattern An insulating layer; the first metal pattern is over the second metal pattern.
  • the brightness enhancement capacitor further includes: a third metal pattern under the second metal pattern, the second metal pattern, and the first An insulating layer between the three metal patterns.
  • the second metal pattern is the same material as the source and drain electrodes of the thin film transistor
  • the third metal pattern is the same material as the gate electrode of the thin film transistor.
  • the second pole of the driving thin film transistor is coupled to the first pole of the light emitting device through a contact hole; the first metal pattern is in contact with the first metal pattern The distance between the holes is 2 ⁇ m to 5 ⁇ m.
  • an embodiment of the present disclosure further provides a display panel including the above pixel circuit, wherein the pixel circuit includes a red sub-pixel circuit, a green sub-pixel circuit, and a blue sub-pixel circuit.
  • a brightness enhancement capacitor of the red sub-pixel circuit a brightness enhancement capacitor of the green sub-pixel circuit, and a brightness enhancement capacitor of the blue sub-pixel circuit
  • the capacitance difference between any two of the brightness enhancement capacitors is less than 5%.
  • an embodiment of the present disclosure further provides a display device, including: the above display panel.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a timing chart of operation of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a brightness enhancement capacitor in a pixel circuit according to an embodiment of the present disclosure
  • FIG. 4 is another schematic structural diagram of a brightness enhancement capacitor in a pixel circuit according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a pixel circuit arrangement in a display panel according to an embodiment of the present disclosure.
  • an organic light emitting transistor is abbreviated as an OLED.
  • the driving thin film transistor is abbreviated as TFT01
  • the light emitting control thin film transistor is abbreviated as TFT02
  • the reset thin film transistor is abbreviated as TFT03
  • the switching thin film transistor is abbreviated as TFT04
  • the storage capacitor is abbreviated as C05
  • the brightness enhancement capacitor is abbreviated as C06
  • the light emitting device is abbreviated as D07.
  • the first capacitor is abbreviated as C1 and the second capacitor is abbreviated as C2.
  • the source electrode and the drain electrode are mutually replaceable. For example, in the case where the source electrode is replaced with a drain electrode, the drain electrode is also replaced with the source electrode.
  • An embodiment of the present disclosure provides a pixel circuit, as shown in FIG. 1, comprising:
  • the light emitting device D07, the second pole 072 of the light emitting device D07 is coupled to the low voltage signal line ELVSS;
  • the driving thin film transistor TFT01 is configured to supply a driving current to the light emitting device D07; the second electrode 012 of the driving thin film transistor TFT01 is coupled to the first pole 071 of the light emitting device D07;
  • the light-emitting control thin film transistor TFT02 is configured to control the light-emitting device to emit light; the first pole 021 of the light-emitting control thin film transistor TFT02 is coupled to the high-voltage signal line ELVDD, and the second pole 022 is coupled to the first pole 011 of the driving thin film transistor TFT01;
  • the switching thin film transistor TFT04 is configured to control the data voltage to be written to the control electrode 013 of the driving thin film transistor TFT01;
  • the reset thin film transistor TFT03 is configured to reset the potential of the control electrode 013 of the driving thin film transistor TFT01;
  • the storage capacitor C05, the first pole 051 of the storage capacitor C05 is coupled to the control electrode 013 of the driving thin film transistor TFT01, and the second pole 052 is coupled to the second pole 012 of the driving thin film transistor TFT01.
  • the reset thin film transistor TFT03 resets the control electrode 013 of the driving thin film transistor TFT01 before writing the data voltage signal, and stabilizes the potential of the control electrode 013 of the driving thin film transistor TFT01. Effectively improve the reliability of the pixel circuit.
  • control electrode 023 of the light emission control thin film transistor TFT02 is coupled to the light emission control signal line EM.
  • the first pole 041 of the switching thin film transistor TFT04 is coupled to the data signal line Data, and the second pole 042 and the driving thin film transistor TFT01 are controlled.
  • the pole 013 is coupled, and the control pole 043 is coupled to the scan signal line Gate.
  • the first pole 031 of the reset thin film transistor TFT03 is coupled to the initial voltage signal line Vini
  • the second pole 032 and the switching thin film transistor TFT04 are The second pole 042 is coupled
  • the control pole 033 is coupled to the reset signal line Reset.
  • the first pole 011 of the driving thin film transistor TFT01 is a source electrode or a drain electrode, and correspondingly, a second pole 012 bit drain electrode or source
  • the first pole 071 of the light emitting device D07 is an anode
  • the second pole 072 of the light emitting device D07 is a cathode.
  • the driving thin film transistor TFT01, the light emitting control thin film transistor TFT02, the reset thin film transistor TFT03, the switching thin film transistor TFT04 may be an N-type thin film transistor or a P-type thin film transistor; if the thin film transistor TFT01, the light-emitting control thin film transistor TFT02 is driven
  • the reset signal line Reset, the scanning signal line Gate, and the light emission control signal line EM are driven to drive the thin film transistor TFT01 when the high voltage signal is input, and the light emission controlling thin film transistor TFT02 is reset.
  • the thin film transistor TFT03 and the switching thin film transistor TFT04 are turned on; if the thin film transistor TFT01, the light emission controlling thin film transistor TFT02, the reset thin film transistor TFT03, and the switching thin film transistor TFT04 are P-type thin film transistors, the reset signal line Reset, the scanning signal line Gate, When the light-emitting control signal line EM inputs a low-voltage signal, the thin film transistor TFT01, the light-emission control thin film transistor TFT02, the reset thin film transistor TFT03, and the switching thin film transistor TFT04 are turned on.
  • the brightness enhancement capacitor C06 may be further included, and the first pole 061 of the brightness enhancement capacitor C06 is coupled to the high voltage signal line ELVDD.
  • the diode 062 is coupled to the first pole 071 of the light emitting device D07.
  • the brightness enhancement capacitor C06 is added, the light emission brightness of the light emitting device D07 and the display uniformity of the display panel can be effectively improved.
  • the reset signal line Reset inputs a high-level voltage signal, and the reset thin film transistor TFT03 is turned on, and the potential of the node A is reset to the potential of the initial voltage signal line Vini, and the reset operation of the node A is completed.
  • the light emission control signal line EM and the scanning signal line Gate input a low level voltage signal, and the light emission controlling thin film transistor TFT02 and the switching thin film transistor TFT04 are in an off state.
  • the reset signal line Reset inputs a low-level voltage signal, and the reset thin film transistor TFT03 is in an off state.
  • the light emission control signal line EM and the scan signal line Gate input a high level voltage signal, the light emission control thin film transistor TFT02 and the switching thin film transistor TFT04 are turned on, and the node A writes the reference potential Vref of the data signal line Data input, because the driving thin film transistor TFT01 is at In the off state, the voltage of the node B finally becomes Vref-Vth, where Vth is the threshold voltage of the driving thin film transistor TFT01, and the writing operation of the threshold voltage is completed.
  • the reset signal line Reset holds the input low-level voltage signal, and the reset thin film transistor TFT03 remains in the off state.
  • the light emission control signal line EM inputs a low level voltage signal, and the light emission control thin film transistor TFT02 is in an off state.
  • the scanning signal line Gate maintains a high-level voltage signal, the switching thin film transistor TFT04 remains turned on, and the node A writes the data potential Vdata input from the data signal line Data.
  • the potential of the node B eventually changes from Vref-Vth to C05*(Vdata-Vref)/(C05+) due to the coupling effect of the storage capacitor C05 and the voltage division of the capacitor C OLED of the light-emitting device D07.
  • C OLED )+Vref-Vth the writing of the data signal is completed.
  • the potential of the node B eventually changes from Vref-Vth to C05*(Vdata-Vref) due to the coupling effect of the storage capacitor C05 and the voltage division of the brightness enhancement capacitor and the capacitance C OLED of the light-emitting device D07. /(C06+C05+C OLED )+Vref-Vth, the writing of the data signal is completed.
  • the reset signal line Reset holds the input low-level voltage signal, and the reset thin film transistor TFT03 remains in the off state.
  • the scanning signal line Gate inputs a low-level voltage signal, and the switching thin film transistor TFT04 is in an off state.
  • the light emission control signal line EM inputs a high level voltage signal, and the light emission control thin film transistor TFT02 is turned on.
  • the brightness enhancement capacitor structure C06 includes: a first metal pattern 104, a second metal pattern 106, and a first metal pattern 104 and a second A first inorganic insulating layer pattern 105 between the metal patterns 106, and the first metal pattern 104 is located above the second metal pattern 106.
  • the first metal pattern 104 and the second metal pattern 106 are used to form the first capacitor C1 as the brightness enhancement capacitor structure C06.
  • the second metal pattern 106 may be formed of the same material as the source and drain electrodes 107 of the thin film transistor, that is, formed by the same patterning process.
  • the manufacturing process is as follows:
  • a second metal layer is deposited on the glass substrate or the plastic substrate on which the other film layer has been formed, and the second metal pattern 106 forming the source electrode or drain electrode pattern 107 and the brightness enhancement capacitor C06 is formed by exposure, etching, and development.
  • the second metal layer is usually made of a metal material such as aluminum, molybdenum or titanium or an alloy material of any two of the above three materials;
  • a first inorganic insulating layer is deposited on the second metal layer, and a first inorganic layer contact hole and a first inorganic insulating layer pattern 105 are formed in the first inorganic insulating layer by a process similar to the first step, first
  • the inorganic insulating layer is usually made of a non-metal material such as silicon nitride, silicon oxide or silicon oxynitride;
  • a third step depositing a first metal layer on the first inorganic insulating layer, forming a first metal pattern 104 of the brightness enhancement capacitor C06 by substantially the same process as described above;
  • the fourth step is to form a contact hole for forming an organic layer by using a deposition, exposure, and development process
  • the contact hole 110 includes a first inorganic layer contact hole and an organic layer contact hole, and the organic layer contact hole is located above the first inorganic layer contact hole;
  • the fifth step using the deposition, exposure, etching, development process to form the anode layer pattern 102;
  • the pixel defining layer pattern 101 is formed by a deposition, exposure, and development process.
  • the second pole (ie, the source electrode or the drain electrode) of the driving thin film transistor TFT01 passes through the contact hole 110 and the first pole of the light emitting device D07 ( That is, the anode 102) is coupled; the distance between the first metal pattern 104 of the brightness enhancement capacitor C06 and the contact hole 110 may be 2 ⁇ m to 5 ⁇ m.
  • the structure C06 of the brightness enhancement capacitor further includes: a third metal pattern 109 under the second metal pattern 104, located at the second The second inorganic insulating layer pattern 108 between the metal pattern 106 and the third metal pattern 109 is formed.
  • the first metal pattern 104 and the second metal pattern 106 constitute a first capacitor C1
  • the third metal pattern 109 and the second metal pattern 106 constitute a second capacitor C1
  • the first capacitor C1 and the second capacitor C2 are connected in parallel as brightness.
  • the reinforced capacitor structure C06 increases the capacitance value of the brightness enhancement capacitor structure C06, further improving the display brightness.
  • the third metal pattern 109 may be formed in the same layer as the gate electrode of the thin film transistor, that is, formed by the same patterning process.
  • the manufacturing process is as follows:
  • a third metal layer is deposited on the glass or plastic substrate on which other film layers have been formed, and the third metal pattern 109 and the gate electrode pattern of the brightness enhancement capacitor C06 are formed by exposure, etching, and development, and the third metal layer is usually A metal material such as aluminum, molybdenum or titanium or an alloy material of any two of the above three materials;
  • a second inorganic insulating layer is deposited on the third metal layer, and a second inorganic insulating layer pattern 108 of the brightness enhancing capacitor C06 is formed by a process similar to the first step.
  • the second inorganic insulating layer is usually silicon nitride. a non-metallic material such as silicon oxide or silicon oxynitride;
  • a second metal layer is deposited on the second inorganic insulating layer, and the source or drain electrode pattern 107 and the second metal pattern 106 of the brightness enhancement capacitor C06 are formed by exposure, etching, and development.
  • the second metal layer is usually used.
  • a metal material such as aluminum, molybdenum or titanium or an alloy material of any two of the above three materials;
  • a first inorganic insulating layer is deposited on the second metal layer, and a first inorganic layer contact hole and a first inorganic insulating layer pattern 105 are formed in the first inorganic insulating layer by using substantially the same process as the first step.
  • An inorganic insulating layer usually uses a non-metal material such as silicon nitride, silicon oxide or silicon oxynitride;
  • a fifth step depositing a first metal layer on the first inorganic insulating layer, forming a first metal pattern 104 of the brightness enhancement capacitor C06 by substantially the same process as described above;
  • the organic insulating layer contact hole is formed by deposition, exposure, and development, the contact hole 110 includes a first inorganic layer contact hole and an organic layer contact hole, and the organic layer contact hole is located above the first inorganic layer contact hole;
  • the anode layer pattern 102 is formed by deposition, exposure, etching, and development;
  • the pixel defining layer 101 is formed by deposition, exposure, and development.
  • the second pole (ie, the source electrode or the drain electrode) of the driving thin film transistor TFT01 passes through the contact hole 110 and the first pole of the light emitting device D07 ( That is, the anode 102) is coupled; the distance between the first metal pattern 104 of the brightness enhancement capacitor C06 and the contact hole 110 may be 2 ⁇ m to 5 ⁇ m.
  • an embodiment of the present disclosure further provides a display panel including the above pixel circuit provided by an embodiment of the present disclosure; as shown in FIG. 5, the pixel circuit includes a blue sub-pixel circuit 201, a red sub-pixel circuit 202, and Green sub-pixel circuit 203.
  • the second pole (ie, the source electrode or the drain electrode) of the driving thin film transistor TFT01 in the three sub-pixel circuits is coupled to the first pole (ie, the anode 102) of the light emitting device D07.
  • the contact holes 110 are located at different positions, and the center line of the contact holes 110 is not on an imaginary line.
  • the overlapping areas of the first metal pattern 104 and the second metal pattern 106 of the brightness enhancement capacitor C06 of the three sub-pixel circuits are substantially equal.
  • the first metal pattern 104 of the brightness enhancement capacitor C06 can be prevented from overlapping the contact hole 110, resulting in
  • the red metal sub-pixel circuit 202, the green sub-pixel circuit 203, the first metal pattern 104 of the brightness enhancement capacitor C06 of the blue sub-pixel circuit 201, and the first The overlapping portions of the two metal patterns 106 have different shapes.
  • the capacitance difference of the brightness enhancement capacitor C06 of the red sub-pixel circuit 202, the green sub-pixel circuit 203, and the blue sub-pixel circuit 201 Less than 5%.
  • an embodiment of the present invention further provides a display device, which is provided by the embodiment of the present invention.
  • the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator.
  • a display function such as a navigator.

Abstract

一种像素电路、显示面板及显示装置，该显示装置包括第二极与低电压信号线耦接的发光器件；第二极与发光器件的第一极耦接的驱动薄膜晶体管；第一极与高电压信号线耦接，第二极与驱动薄膜晶体管的第一极耦接的发光控制薄膜晶体管；控制数据电压写入驱动薄膜晶体管的控制极的开关薄膜晶体管；复位驱动薄膜晶体管的控制极电位的复位薄膜晶体管；耦接于驱动薄膜晶体管的控制极和第二极的存储电容。

Description

像素电路、显示面板及显示装置
相关申请的交叉引用
本申请要求在2017年12月14日提交中国专利局、申请号为201721749337.8、发明名称为“显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，具体涉及一种像素电路、显示面板及显示装置。
背景技术
越来越多的有机电致发光显示器件(OLED)应用于显示装置的显示屏，相比于液晶显示屏(LCD),OLED显示屏具有高亮度、高色域、高对比度、轻薄等诸多优点，但目前市场上应用的OLED显示屏，由于像素驱动电路结构和像素排列结构存在诸多问题，导致显示质量欠佳。
发明内容
第一方面，本公开实施例提供了一种像素电路，其中，包括：
发光器件，发光器件的第二极与低电压信号线耦接；
驱动薄膜晶体管，被配置为给所述发光器件提供驱动电流；所述驱动薄膜晶体管的第二极与所述发光器件的第一极耦接；
发光控制薄膜晶体管，被配置为控制所述发光器件发光；所述发光控制薄膜晶体管的第一极与高电压信号线耦接，第二极与所述驱动薄膜晶体管的第一极耦接；
开关薄膜晶体管，被配置为控制数据电压写入所述驱动薄膜晶体管的控制极；
复位薄膜晶体管，被配置为复位所述驱动薄膜晶体管的控制极电位；
存储电容，所述存储电容的第一极与所述驱动薄膜晶体管的控制极耦接，第二极与所述驱动薄膜晶体管的第二极耦接。
可选地，在本公开实施例提供的上述像素电路中，所述发光控制薄膜晶体管的控制极与发光控制信号线耦接。
可选地，在本公开实施例提供的上述像素电路中，所述开关薄膜晶体管的第一极与数据信号线耦接，第二极与所述驱动薄膜晶体管的控制极耦接，控制极与扫描信号线耦接。
可选地，在本公开实施例提供的上述像素电路中，所述复位薄膜晶体管的第一极与初始电压信号线耦接，第二极与所述开关薄膜晶体管的第二极耦接，控制极与复位信号线耦接。
可选地，在本公开实施例提供的上述像素电路中，所述驱动薄膜晶体管的第一极为源电极或漏电极；所述发光器件的第一极为阳极。
可选地，在本公开实施例提供的上述像素电路中，还包括：亮度增强电容，所述亮度增强电容的第一极与所述高电压信号线耦接，第二极与所述发光器件的第一极耦接。
可选地，在本公开实施例提供的上述像素电路中，所述亮度增强电容包括：第一金属图形、第二金属图形、位于所述第一金属图形和所述第二金属图形之间的绝缘层；所述第一金属图形位于所述第二金属图形之上。
可选地，在本公开实施例提供的上述像素电路中，所述亮度增强电容还包括：位于所述第二金属图形之下的第三金属图形、位于所述第二金属图形和所述第三金属图形之间的绝缘层。
可选地，在本公开实施例提供的上述像素电路中，所述第二金属图形与薄膜晶体管的源漏电极同层同材质；
所述第三金属图形与薄膜晶体管的栅电极同层同材质。
可选地，在本公开实施例提供的上述像素电路中，所述驱动薄膜晶体管的第二极通过接触孔与所述发光器件的第一极耦接；所述第一金属图形与所 述接触孔之间间隔的距离为2μm-5μm。
第二方面，本公开实施例还提供了一种显示面板，包括上述像素电路，所述像素电路包括红色子像素电路、绿色子像素电路和蓝色子像素电路。
可选地，在本公开实施例提供的上述像素电路中，在所述红色子像素电路的亮度增强电容、所述绿色子像素电路的亮度增强电容和所述蓝色子像素电路的亮度增强电容中，其中任意两个亮度增强电容之间的电容差值小于5％。
第三方面，本公开实施例还提供了一种显示装置，包括：上述显示面板。
附图说明
图1为本公开实施例提供的像素电路的结构示意图；
图2为本公开实施例提供的像素电路的工作时序图；
图3为本公开实施例提供的像素电路中亮度增强电容的结构示意图；
图4为本公开实施例提供的像素电路中亮度增强电容的另一结构示意图；
图5为本公开实施例的显示面板中像素电路排列的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除 其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开中，有机发光晶体管(Organic light emitting transistor)简写为OLED。相应的，驱动薄膜晶体管简写为TFT01，发光控制薄膜晶体管简写为TFT02，复位薄膜晶体管简写为TFT03，开关薄膜晶体管简写为TFT04，存储电容简写为C05，亮度增强电容简写为C06，发光器件简写为D07，第一电容简写为C1，第二电容简写为C2。并且，本公开中，源电极和漏电极相对而言，可相互替换。例如，将源电极替换为漏电极的情况下，漏电极亦替换为源电极。
本公开实施例提供了一种像素电路，如图1所示，包括：
发光器件D07，发光器件D07的第二极072与低电压信号线ELVSS耦接；
驱动薄膜晶体管TFT01，被配置为给发光器件D07提供驱动电流；驱动薄膜晶体管TFT01的第二极012与发光器件D07的第一极071耦接；
发光控制薄膜晶体管TFT02，被配置为控制发光器件发光；发光控制薄膜晶体管TFT02的第一极021与高电压信号线ELVDD耦接，第二极022与驱动薄膜晶体管TFT01的第一极011耦接；
开关薄膜晶体管TFT04，被配置为控制数据电压写入驱动薄膜晶体管TFT01的控制极013；
复位薄膜晶体管TFT03，被配置为复位驱动薄膜晶体管TFT01的控制极013电位；
存储电容C05，存储电容C05的第一极051与驱动薄膜晶体管TFT01的控制极013耦接，第二极052与驱动薄膜晶体管TFT01的第二极012耦接。
具体地，在本发明实施例提供的上述像素电路中，复位薄膜晶体管TFT03在写入数据电压信号前对驱动薄膜晶体管TFT01的控制极013进行复位，稳定了驱动薄膜晶体管TFT01的控制极013电位，有效提高了像素电路的可靠 性。
可选地，在本公开实施例提供的上述像素电路中，如图1所示，发光控制薄膜晶体管TFT02的控制极023与发光控制信号线EM耦接。
可选地，在本公开实施例提供的上述像素电路中，如图1所示，开关薄膜晶体管TFT04的第一极041与数据信号线Data耦接，第二极042与驱动薄膜晶体管TFT01的控制极013耦接，控制极043与扫描信号线Gate耦接。
可选地，在本公开实施例提供的上述像素电路中，如图1所示，复位薄膜晶体管TFT03的第一极031与初始电压信号线Vini耦接，第二极032与开关薄膜晶体管TFT04的第二极042耦接，控制极033与复位信号线Reset耦接。
可选地，在本公开实施例提供的上述像素电路中，如图1所示，驱动薄膜晶体管TFT01的第一极011为源电极或漏电极，对应的，第二极012位漏电极或源电极；发光器件D07的第一极071为阳极，对应的，发光器件D07的第二极072为阴极。
在本公开实施例中，驱动薄膜晶体管TFT01，发光控制薄膜晶体管TFT02，复位薄膜晶体管TFT03，开关薄膜晶体管TFT04可以为N型薄膜晶体管或P型薄膜晶体管；若驱动薄膜晶体管TFT01，发光控制薄膜晶体管TFT02，复位薄膜晶体管TFT03，开关薄膜晶体管TFT04为N型薄膜晶体管时，则复位信号线Reset、扫描信号线Gate、发光控制信号线EM输入高电压信号时驱动薄膜晶体管TFT01，发光控制薄膜晶体管TFT02，复位薄膜晶体管TFT03，开关薄膜晶体管TFT04导通；若驱动薄膜晶体管TFT01，发光控制薄膜晶体管TFT02，复位薄膜晶体管TFT03，开关薄膜晶体管TFT04为P型薄膜晶体管时，则复位信号线Reset、扫描信号线Gate、发光控制信号线EM输入低电压信号时驱动薄膜晶体管TFT01，发光控制薄膜晶体管TFT02，复位薄膜晶体管TFT03，开关薄膜晶体管TFT04导通。
可选地，在本公开实施例提供的上述像素电路中，如图1所示，还可以包括：亮度增强电容C06，亮度增强电容C06的第一极061与高电压信号线 ELVDD耦接，第二极062与发光器件D07的第一极071耦接。
具体地，在本公开实施例提供的上述像素电路中，由于增加了亮度增强电容C06，可以有效提高发光器件D07的发光亮度和显示面板的显示均一性。
下面结合图2所示的工作时序图，以像素电路中的薄膜晶体管全部为N型薄膜晶体管为例，对本公开实施例提供的上述像素电路的工作原理进行详细的描述。具体工作原理如下：
①T1时间段，复位信号线Reset输入高电平电压信号，复位薄膜晶体管TFT03导通，节点A电位复位到初始电压信号线Vini的电位，完成对节点A的复位工作。在此时间段，发光控制信号线EM和扫描信号线Gate输入低电平电压信号，发光控制薄膜晶体管TFT02和开关薄膜晶体管TFT04处于截止状态。
②T2时间段，复位信号线Reset输入低电平电压信号，复位薄膜晶体管TFT03处于截止状态。发光控制信号线EM和扫描信号线Gate输入高电平电压信号，发光控制薄膜晶体管TFT02和开关薄膜晶体管TFT04导通，节点A写入数据信号线Data输入的参考电位Vref，由于驱动薄膜晶体管TFT01处于截止状态，节点B的电压最终变为Vref-Vth，其中Vth为驱动薄膜晶体管TFT01的阈值电压，完成阈值电压的写入工作。
③T3时间段，复位信号线Reset保持输入低电平电压信号，复位薄膜晶体管TFT03保持截止状态。发光控制信号线EM输入低电平电压信号，发光控制薄膜晶体管TFT02处于截止状态。扫描信号线Gate保持高电平电压信号，开关薄膜晶体管TFT04保持导通，节点A写入数据信号线Data输入的数据电位Vdata。
在仅存在存储电容C05时，由于存储电容C05的耦合作用以及发光器件D07的电容C OLED的分压作用，节点B的电位从Vref-Vth最终变为C05*(Vdata-Vref)/(C05+C OLED)+Vref-Vth，完成了数据信号的写入工作。
在存在亮度增强电容时，由于存储电容C05的耦合作用，以及亮度增强电容和发光器件D07的电容C OLED的分压作用，节点B的电位从Vref-Vth最 终变为C05*(Vdata-Vref)/(C06+C05+C OLED)+Vref-Vth，完成了数据信号的写入工作。
④T4时间段，复位信号线Reset保持输入低电平电压信号，复位薄膜晶体管TFT03保持截止状态。扫描信号线Gate输入低电平电压信号，开关薄膜晶体管TFT04处于截止状态。发光控制信号线EM输入高电平电压信号，发光控制薄膜晶体管TFT02导通。此时流过驱动薄膜晶体管TFT01的电流：Ids＝1/2k(Vgs-Vth) 2＝1/2K(V A-V B-Vth) 2；其中k＝μ Cox W/L；μ为离子迁移率、W为沟道宽度、Cox为薄膜氧化物电容、L为沟道长度。
在仅存在存储电容C05时：
Figure PCTCN2018103347-appb-000001
在存在亮度增强电容C06时：
Figure PCTCN2018103347-appb-000002
通过比较上述两个公式可以看出，在存在亮度增强电容C06时流过驱动薄膜晶体管TFT01的电流较大，因此，可以提高发光器件D07的发光亮度。
可选地，在本公开实施例提供的上述像素电路中，如图3所示，亮度增强电容结构C06包括：第一金属图形104、第二金属图形106、位于第一金属图形104和第二金属图形106之间的第一无机绝缘层图形105，且第一金属图 形104位于第二金属图形106之上。采用第一金属图形104和第二金属图形106构成第一电容C1作为亮度增强电容结构C06。
可选地，在本公开实施例提供的上述像素电路中，如图3所示，第二金属图形106可以与薄膜晶体管的源漏电极107同层同材质，即采用同一构图工艺形成。
具体地，以图3所示的结构为例，其制作工艺如下：
第一步，在已形成其它膜层的玻璃基板或塑料基板上沉积第二金属层，采用曝光、刻蚀、显影制作形成源电极或漏电极图形107和亮度增强电容C06的第二金属图形106，第二金属层通常采用铝、钼、钛等金属材料或上述三种材料的任意二种材料的合金材料；
第二步，在第二金属层上沉积第一无机绝缘层，采用与第一步类似的工艺在第一无机绝缘层中形成第一无机层接触孔和第一无机绝缘层图形105，第一无机绝缘层通常采用氮化硅、氧化硅、氮氧化硅等非金属材料；
第三步，在第一无机绝缘层上沉积第一金属层，通过与上述基本相同的工艺形成亮度增强电容C06的第一金属图形104；
第四步，采用沉积、曝光、显影工艺制作形成有机层接触孔，接触孔110包含第一无机层接触孔和有机层接触孔，有机层接触孔位于第一无机层接触孔之上；
第五步，采用沉积、曝光、刻蚀、显影工艺制作形成阳极层图形102；
第六步，采用沉积、曝光、显影工艺制作形成像素界定层图形101。
具体地，在本发明实施例提供的上述像素电路中，如图3所示，驱动薄膜晶体管TFT01的第二极(即源电极或漏电极)通过接触孔110与发光器件D07的第一极(即阳极102)耦接；亮度增强电容C06的第一金属图形104与接触孔110之间间隔的距离可以为2μm-5μm。
可选地，在本公开实施例提供的上述像素电路中，如图4所示，亮度增强电容的结构C06，还包括：位于第二金属图形104之下的第三金属图形109、位于第二金属图形106和第三金属图形109之间的第二无机绝缘层图形108 构成。第一金属图形104和第二金属图形106构成第一电容C1，第三金属图形109和第二金属图形106构成第二电容C1，第一电容C1和第二电容C2采用并联的连接方式作为亮度增强电容结构C06，增加了亮度增强电容结构C06的电容值，进一步提升了显示亮度。
可选地，在本公开实施例提供的上述像素电路中，第三金属图形109可以与薄膜晶体管的栅电极同层同材质，即采用同一构图工艺形成。
具体地，以图4所示的结构为例，其制作工艺如下：
第一步，在已形成其它膜层的玻璃或塑料基板上沉积第三金属层，采用曝光、刻蚀、显影形成亮度增强电容C06的第三金属图形109和栅电极图形，第三金属层通常采铝、钼、钛等金属材料或上述三种材料的任意两种材料的合金材料；
第二步，在第三金属层上沉积第二无机绝缘层，采用与第一步类似的工艺形成亮度增强电容C06的第二无机绝缘层图形108，第二无机绝缘层通常采用氮化硅、氧化硅、氮氧化硅等非金属材料；
第三步，在第二无机绝缘层上沉积第二金属层、采用曝光、刻蚀、显影形成源电极或漏电极图形107和亮度增强电容C06的第二金属图形106，第二金属层通常采用铝、钼、钛等金属材料或上述三种材料的任意两种材料的合金材料；
第四步，在第二金属层上沉积第一无机绝缘层，采用与第一步基本相同的工艺在第一无机绝缘层中形成第一无机层接触孔和第一无机绝缘层图形105，第一无机绝缘层通常采用氮化硅、氧化硅、氮氧化硅等非金属材料；
第五步，在第一无机绝缘层上沉积第一金属层，通过与上述基本相同的工艺形成亮度增强电容C06的第一金属图形104；
第六步，采用沉积、曝光、显影制作形成有机绝缘层接触孔，接触孔110包含第一无机层接触孔和有机层接触孔，有机层接触孔位于第一无机层接触孔之上；
第七步，采用沉积、曝光、刻蚀、显影制作形成阳极层图形102；
第八步，采用沉积、曝光、显影制作形成像素界定层101。
具体地，在本发明实施例提供的上述像素电路中，如图4所示，驱动薄膜晶体管TFT01的第二极(即源电极或漏电极)通过接触孔110与发光器件D07的第一极(即阳极102)耦接；亮度增强电容C06的第一金属图形104与接触孔110之间间隔的距离可以为2μm-5μm。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述像素电路；如图5所示，像素电路包括蓝色子像素电路201，红色子像素电路202和绿色子像素电路203。
具体地，在本公开实施例提供的上述显示面板中，三种子像素电路中驱动薄膜晶体管TFT01的第二极(即源电极或漏电极)与发光器件D07的第一极(即阳极102)耦接的接触孔110位于不同的位置，接触孔110的中心连线不在一条假想线上。
具体地，在本公开实施例提供的上述显示面板中，三种子像素电路的亮度增强电容C06的第一金属图形104和第二金属图形106的交叠面积基本相等。并且，为了使亮度增强电容C06的第一金属图形104和第二金属图形106具有较大的交叠面积的同时，能够避免亮度增强电容C06的第一金属图形104与接触孔110交叠，造成第一金属图形104和驱动薄膜晶体管TFT01的漏电极107发生短路，则要求红色子像素电路202、绿色子像素电路203、蓝色子像素电路201的亮度增强电容C06的第一金属图形104和第二金属图形106的交叠部分具有不同的形状。
可选地，在本公开实施例提供的上述显示面板中，为了具有均匀的显示亮度，红色子像素电路202、绿色子像素电路203、蓝色子像素电路201的亮度增强电容C06的电容差值小于5％。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘 述。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
以上仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (13)

  1. 一种像素电路，其中，包括：
    发光器件，所述发光器件的第二极与低电压信号线耦接；
    驱动薄膜晶体管，被配置为给所述发光器件提供驱动电流；所述驱动薄膜晶体管的第二极与所述发光器件的第一极耦接；
    发光控制薄膜晶体管，被配置为控制所述发光器件发光；所述发光控制薄膜晶体管的第一极与高电压信号线耦接，第二极与所述驱动薄膜晶体管的第一极耦接；
    开关薄膜晶体管，被配置为控制数据电压写入所述驱动薄膜晶体管的控制极；
    复位薄膜晶体管，被配置为复位所述驱动薄膜晶体管的控制极电位；
    存储电容，所述存储电容的第一极与所述驱动薄膜晶体管的控制极耦接，第二极与所述驱动薄膜晶体管的第二极耦接。
  2. 根据权利要求1所述的像素电路，其中，所述发光控制薄膜晶体管的控制极与发光控制信号线耦接。
  3. 根据权利要求1所述的像素电路，其中，所述开关薄膜晶体管的第一极与数据信号线耦接，第二极与所述驱动薄膜晶体管的控制极耦接，控制极与扫描信号线耦接。
  4. 根据权利要求1所述的像素电路，其中，所述复位薄膜晶体管的第一极与初始电压信号线耦接，第二极与所述开关薄膜晶体管的第二极耦接，控制极与复位信号线耦接。
  5. 根据权利要求1所述的像素电路，其中，所述驱动薄膜晶体管的第一极为源电极或漏电极；所述发光器件的第一极为阳极。
  6. 根据权利要求1所述的像素电路，其中，还包括：亮度增强电容，所述亮度增强电容的第一极与所述高电压信号线耦接，第二极与所述发光器件的第一极耦接。
  7. 根据权利要求6所述的像素电路，其中，所述亮度增强电容包括：第一金属图形、第二金属图形、位于所述第一金属图形和所述第二金属图形之间的第一无机绝缘层图形；所述第一金属图形位于所述第二金属图形之上。
  8. 根据权利要求7所述的像素电路，其中，所述亮度增强电容还包括：位于所述第二金属图形之下的第三金属图形、位于所述第二金属图形和所述第三金属图形之间的第二无机绝缘层图形。
  9. 根据权利要求8所述的像素电路，其中，所述第二金属图形与薄膜晶体管的源漏电极同层同材质；
    所述第三金属图形与薄膜晶体管的栅电极同层同材质。
  10. 根据权利要求7或8所述的像素电路，其中，所述驱动薄膜晶体管的第二极通过接触孔与所述发光器件的第一极耦接；所述第一金属图形与所述接触孔之间间隔的距离为2μm-5μm。
  11. 一种显示面板，其中，包括如权利要求1-10任一项所述的像素电路，所述像素电路包括红色子像素电路、绿色子像素电路和蓝色子像素电路。
  12. 根据权利要求11所述的显示面板，其中，在所述红色子像素电路的亮度增强电容、所述绿色子像素电路的亮度增强电容和所述蓝色子像素电路的亮度增强电容中，其中任意两个亮度增强电容之间的电容差值小于5％。
  13. 一种显示装置，其中，包括：根据权利要求11或12所述的显示面板。
PCT/CN2018/103347 2017-12-14 2018-08-30 像素电路、显示面板及显示装置 WO2019114327A1 (zh)

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