WO2023241217A1 - 显示基板、其制作方法及显示装置 - Google Patents

显示基板、其制作方法及显示装置 Download PDF

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WO2023241217A1
WO2023241217A1 PCT/CN2023/089941 CN2023089941W WO2023241217A1 WO 2023241217 A1 WO2023241217 A1 WO 2023241217A1 CN 2023089941 W CN2023089941 W CN 2023089941W WO 2023241217 A1 WO2023241217 A1 WO 2023241217A1
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transistor
electrode
gate
transistors
light
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PCT/CN2023/089941
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English (en)
French (fr)
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赵梦
王超璐
王锦谦
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京东方科技集团股份有限公司
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Publication of WO2023241217A1 publication Critical patent/WO2023241217A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Electro-luminesecent Display
  • OLED driving circuits usually use low temperature polysilicon (Low Temperature Poly-silicon, LTPS) as the channel of driving thin film transistor (Driver Thin Film Transistor, DTFT).
  • LTPS Low Temperature Poly-silicon
  • DTFT Driver Thin Film Transistor
  • LTPS has a higher mobility than a-Si.
  • Vth threshold voltage
  • the 7T1C pixel compensation circuit shown in Figure 1 is often used.
  • the pixel compensation circuit includes seven transistors including T1, T2, T3, T4, T5, T6 and T7.
  • T3 is DTFT and Cst is the storage capacitor.
  • LTPO backplanes that combine LTPS TFT and oxide (Oxide) TFT are often used.
  • the drive circuit in the LTPO backplane can replace T1 and T2 with Oxide TFT based on Figure 1, and use the low leakage characteristics of Oxide TFT to reduce low-frequency Flicker failure caused by Cst leakage. How to avoid uneven DTFT Vth has become an urgent technical problem that needs to be solved.
  • the present disclosure provides a display substrate, its manufacturing method and a display device, which are used to ensure the uniformity of the threshold voltage of the thin film transistor and improve the display effect.
  • an embodiment of the present disclosure provides a display substrate, including:
  • Each of the sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device.
  • the pixel driving circuit includes at least two oxide physical transistors and storage capacitors;
  • the storage capacitor includes a first electrode and a second electrode that are sequentially facing away from the base substrate and arranged oppositely, and the distance between the gate electrode of at least two transistors in the at least two oxide transistors and the active layer are different, and the transistor with a farther distance between the gate electrode and the active layer among the at least two oxide transistors is located above the second electrode.
  • the second electrode partially overlaps the active layers of the at least two oxide transistors.
  • the pixel driving circuit further includes at least one polysilicon transistor coupled to the at least two oxide transistors, and the gate of the at least one polysilicon transistor is in the same layer as the first electrode. is arranged, and the at least two oxide transistors are arranged on a side of the second electrode facing away from the base substrate.
  • the orthographic projection of the active layers of the at least two oxide transistors on the substrate completely falls into the active layer of the at least one polysilicon transistor on the substrate. within the area of the orthographic projection.
  • the orthographic projection of the second electrode on the base substrate completely falls within the area of the orthographic projection of the first electrode on the base substrate.
  • the at least two oxide transistors include a compensation transistor and a first reset transistor
  • the pixel driving circuit also includes driving transistors that are both polysilicon transistors. tube, a first light emitting control transistor, a second light emitting control transistor, a data writing transistor, and a second reset transistor;
  • the compensation transistors are respectively coupled between the gate electrode and the first electrode of the driving transistor, and the gate electrode is coupled to the first scan control terminal;
  • the first reset transistor is respectively coupled between the gate electrode of the driving transistor and the initialization signal terminal, and the gate electrode is coupled to the first scan control terminal;
  • the storage capacitor is respectively coupled between the first power terminal and the gate of the driving transistor
  • the first light-emitting control transistor is respectively coupled between the first power terminal and the second electrode of the driving transistor, and the gate is coupled with the light-emitting control terminal;
  • the second light-emitting control transistor is respectively coupled between the first electrode of the driving transistor and the first electrode of the light-emitting device, and the gate electrode is coupled with the light-emitting control terminal;
  • the data writing transistors are respectively coupled between the second pole of the driving transistor and the data signal terminal, and the gate is coupled to the second scan control terminal;
  • the second reset transistor is respectively coupled between the first pole of the light-emitting device and the initialization signal terminal, and the gate is coupled to the second scan control terminal;
  • the second pole of the light-emitting device is coupled to the second power terminal.
  • the compensation transistor and the first reset transistor are both N-type transistors
  • the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the data Both the write transistor and the second reset transistor are P-type transistors.
  • an embodiment of the present disclosure also provides a display device, including:
  • embodiments of the present disclosure also provide a method for manufacturing a display substrate as described in any one of the above, including:
  • Patterns of the first electrode and the second electrode of the storage capacitor and the active layers of the at least two oxide transistors are sequentially formed on the base substrate;
  • a gate insulating layer is patterned on a side of the active layer of the at least two oxide transistors facing away from the base substrate, so that the at least two oxide transistors are located on the second electrode.
  • the distance between the gate of the square transistor and the active layer is greater than the distance between the gate of the other transistors and the active layer.
  • a gate insulating layer pattern is formed on a side of the active layer of the at least two oxide transistors facing away from the base substrate, including:
  • the gate insulation layer at the corresponding position of the other transistor is etched to a third thickness, wherein the difference between the first thickness and the third thickness is the second thickness , the first thickness is greater than the second thickness;
  • the pattern of the photoresist is removed to form a pattern of the gate insulating layer.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • the display substrate includes a base substrate and a plurality of sub-pixels arranged in an array on the base substrate.
  • Each sub-pixel includes a light-emitting device and a driving device.
  • the pixel driving circuit of the light-emitting device, the pixel driving circuit includes at least two oxide transistors and a storage capacitor; wherein the storage capacitor includes a first electrode and a second electrode that are facing away from the substrate substrate and arranged oppositely, and at least two oxide transistors.
  • the distance between the gate electrode and the active layer of at least two of the object transistors is different, and the transistor with the farther distance between the gate electrode and the active layer of the at least two oxide transistors is located above the second electrode. That is to say, the distance between the gate electrode of the transistor located above the second electrode and the active layer among at least two oxide transistors is greater than the distance between the gate electrode and the active layer of the other transistor not above the second electrode. distance.
  • the gap between the gate of the transistor and the active layer can correspondingly shift its threshold voltage in the opposite direction, and the two cancel each other out, thus ensuring the uniformity of the threshold voltage of the transistor and improving the display effect.
  • Figure 1 is a schematic circuit structure diagram of one of the 7T1C pixel compensation circuits in the related art
  • Figure 2 is a schematic circuit structure diagram of one of the driving circuits used in LTPO backplanes in related technologies
  • Figure 3 is a schematic diagram of one of the film layer structures corresponding to Figure 2;
  • Figure 4 is a schematic diagram of another film layer structure corresponding to Figure 2;
  • FIG. 5 is a schematic structural diagram of a top view of a display substrate provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of one of the cross-sectional structures along the direction shown by MM in Figure 5;
  • FIG. 7 is a schematic circuit structure diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure.
  • Figure 8 is a method flow chart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure
  • Figure 9 is a method flow chart of step S102 in Figure 8.
  • Figure 10 is one of the process flow diagrams corresponding to Figures 8 and 9.
  • the LTPO backplane can adopt the driving circuit shown in Figure 2 and the film layer structure shown in Figure 3.
  • 01 represents Oxide TFT
  • 02 represents storage capacitor
  • 03 represents LTPS TFT.
  • the pitch (Pitch) of the finally formed sub-pixels is 56 ⁇ m
  • the corresponding pixel density (Pixels Per Inch, PPI) is about 450.
  • Oxide TFT avoids all film layers of the underlying LTPS TFT during design, resulting in lower resolution.
  • the film structure shown in Figure 4 can be used, and one of the Oxide TFTs is placed above Cst. Since the upper electrode of Cst is connected to ELVDD, and ELVDD has a DC voltage of 4.6V, which is equivalent to A DC bottom gate is connected under the channel of the Oxide TFT. Since the DC voltage is constant, it will not cause a jump in the channel state when the circuit is working.
  • the pitch of the finally formed sub-pixel is 42 ⁇ m, and the corresponding PPI is about 600. Compared with Figure 3, the PPI is higher.
  • the Oxide TFT located on the DC bottom gate will be negatively biased by approximately 1.2V.
  • T1 and T2 if only one of the tubes is placed on Cst, it will cause a deviation in the turn-on voltage of the two Oxide TFTs, thus causing an Ion deviation. In practical applications, this situation may cause timing problems caused by abnormal capacitor charging and discharging.
  • Vth cannot be adjusted through channel doping, nor can the channel of the TFT in the same layer be adjusted through the oxygen content of indium gallium zinc oxide (IGZO). channel mobility.
  • IGZO indium gallium zinc oxide
  • embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device to ensure the uniformity of the threshold voltage of the thin film transistor and improve the display effect.
  • FIG. 5 is a schematic structural diagram of a top view of the display substrate
  • FIG. 6 is a schematic view of one of the display substrates along the direction indicated by MM in FIG. 5 Schematic cross-sectional structure diagram.
  • the display substrate includes:
  • Each of the sub-pixels 20 includes a light-emitting device 30 and a pixel driving circuit 40 for driving the light-emitting device 30.
  • the driving circuit 40 includes at least two oxide transistors 50 and a storage capacitor 60;
  • the storage capacitor 60 includes a first electrode 61 and a second electrode 62 that are facing away from the base substrate 10 and arranged oppositely.
  • the gates of at least two of the at least two oxide transistors 50 are connected to the active electrodes.
  • the distances between the layers are different, and among the at least two oxide transistors 50 , the transistor with a farther distance between the gate electrode and the active layer is located above the second electrode 62 .
  • the display substrate includes a substrate substrate 10 and a plurality of sub-pixels 20 arranged in an array on the substrate substrate 10.
  • the substrate substrate 10 may be a rigid substrate or a flexible substrate. This is not limited.
  • Each sub-pixel 20 includes a light-emitting device 30 and a pixel driving circuit 40 for driving the light-emitting device 30.
  • the pixel driving circuit 40 includes at least two oxide transistors 50 and a storage capacitor 60.
  • the at least two oxide transistors 50 included in each pixel driving circuit 40 may be two or three, and may be set according to actual application requirements, which is not limited here.
  • the storage capacitor 60 includes a first electrode 61 and a second electrode 62 that are sequentially facing away from the base substrate 10 and arranged oppositely, gates and active layers of at least two of the at least two oxide transistors 30 The distances between them are different, and the transistor with the farther distance between the gate electrode and the active layer among at least two oxide transistors 30 is located above the second electrode 62 . That is to say, the distance between the gate electrode and the active layer of the transistor located above the second electrode 62 among the at least two oxide transistors 30 is larger than the distance between the gate electrode and the active layer of the other transistor not located above the second electrode 62 the distance between.
  • the second electrode 62 may be configured to receive a constant voltage signal, in which case the second electrode 62 may serve as a bottom gate for a transistor located above it, correspondingly improving the stability of the transistor.
  • the distance between the gate electrode of the combined at least two oxide transistors 30 located above the second electrode 62 and the active layer is greater than the distance between the gate electrode and the active layer of other transistors not located above the second electrode 62 .
  • the distance can reduce the layout space of the oxide transistor and improve the resolution. Even if the second electrode 62 receives a constant voltage signal causing the threshold voltage of the transistor above it to shift, the gate of the transistor and the active layer The larger distance between them can correspondingly shift their threshold voltage in the opposite direction. They cancel each other out, thus ensuring the uniformity of the threshold voltage of the transistor and improving the display effect.
  • the transistor whose gate is far away from the active layer may be one, or may be multiple.
  • the transistor whose gate electrode is far away from the active layer may be the second one.
  • the number of oxide transistors above the second electrode 62 may be set according to actual application requirements, and is not limited here.
  • the number of transistors that are not disposed above the second electrode 62 may be one, or there may be multiple transistors, which are not limited here.
  • FIG. 6 illustrates that one transistor is located above the second electrode 62 and the other transistor is not located above the second electrode 62 .
  • the distance between the gate of the transistor located above the second electrode 62 and the active layer is d1
  • the distance between the gates of the other transistors and the active layer is d2, d1>d2 .
  • the threshold voltage of the transistor located above the second electrode 62 shifts due to the second electrode 62 receiving a constant voltage signal
  • the larger distance between the gate of the transistor and the active layer can correspondingly cause its threshold voltage to shift. Reverse offset, the two cancel each other out, thereby ensuring the uniformity of the threshold voltage of the transistor and improving the display effect.
  • the specific value of the distance between the gate 5011 of the oxide transistor located above the second electrode 62 and the active layer, and the distance between the gate 5021 and the active layer of other transistors can be set according to actual application needs.
  • the specific value of the distance between them is not limited here.
  • the N-type oxide transistor is affected by the gate dielectric layer capacitance Cox.
  • Cox the gate dielectric layer capacitance
  • the distance between the gate electrode 5011 of the transistor located above the second electrode 62 and the active layer in the at least two oxide transistors 50 is larger than the distance between the gate electrode 5021 of the other transistors and the active layer.
  • the distance between the layers can offset the influence of the threshold voltage shift of the transistor located above the second electrode 62 due to the second electrode 62 receiving a constant voltage signal, effectively ensuring the uniformity of Vth.
  • the second electrode 62 partially overlaps the active layer 500 of the at least two oxide transistors 50 .
  • the channels of at least two oxide transistors 50 can be protected to a certain extent through the second electrode 62 , thereby ensuring the driving capability of the pixel driving circuit 40 .
  • the pixel driving circuit 40 further includes at least one polysilicon transistor 70 coupled with the at least two oxide transistors 50 , and the gate of the at least one polysilicon transistor 70
  • the electrode 701 is arranged in the same layer as the first electrode 61 , and the at least two oxide transistors 50 are arranged on a side of the second electrode 62 away from the base substrate 10 .
  • the at least one polysilicon transistor 70 coupled to the at least two oxide transistors 50 may be one or multiple, which is not limited here.
  • the gate electrode 701 of at least one polysilicon transistor 70 and the first electrode 61 are arranged in the same layer.
  • the gate 701 and the first electrode 61 of at least one polysilicon transistor 70 can be fabricated on the same layer, thereby simplifying the fabrication process.
  • at least two oxide transistors 50 are disposed on the side of the second electrode 62 facing away from the base substrate 10. In this way, the layout space can be saved, thereby improving the resolution.
  • the orthographic projection of the active layer 500 of the at least two oxide transistors 50 on the base substrate 10 completely falls into the at least one polysilicon transistor 70
  • the active layer 700 is within the orthographic projection area on the base substrate 10 .
  • the orthographic projection of the active layer 500 of the at least two oxide transistors 50 on the base substrate 10 completely falls within the orthographic projection of the active layer 700 of the at least one polysilicon transistor 70 on the base substrate 10 within the area, thereby saving layout space and improving resolution.
  • the orthographic projection of the second electrode 62 on the base substrate 10 completely falls into the orthographic projection of the first electrode 61 on the base substrate 10 . within the projected area. In this way, the first electrode 61 can protect the second electrode 62 to a certain extent, thereby The performance of the storage capacitor 60 is guaranteed.
  • the display substrate provided by the embodiment of the present disclosure also includes a gate insulating layer 80 disposed between the gate electrode and the active layer of the oxide transistor 50, located between the second electrode 62 and The first interlayer insulating layer 90 and the buffer layer 100 between the active layer 500 of the oxide transistor 50, the first gate insulating layer 110 between the active layer 700 of the polysilicon transistor 70 and the first electrode 61, The second gate insulating layer 120 is between the first electrode 61 and the second electrode 62 , and the second interlayer insulating layer 130 is provided on the side of the gate of the oxide transistor 50 facing away from the base substrate 10 .
  • other film layers of the display substrate can also be provided according to actual application requirements. For details, reference can be made to specific implementations in related technologies, which will not be described in detail here.
  • the pixel driving circuit 40 may be arranged in various ways.
  • FIG. 7 is a schematic structural diagram of the pixel driving circuit 40.
  • the at least two oxide transistors 50 include a compensation transistor M2 and a first reset transistor M1.
  • the pixel driving circuit 40 also includes a driving transistor M3, a first luminescence control transistor M5, a second luminescence control transistor M3, which are all polysilicon transistors.
  • the compensation transistor M2 is coupled between the gate and the first electrode of the driving transistor M3, and the gate is coupled to the first scan control terminal S;
  • the first reset transistor M1 is coupled between the gate of the driving transistor M3 and the initialization signal terminal Vinit, and the gate is coupled to the first scan control terminal S;
  • the storage capacitor 60 is respectively coupled between the first power terminal VDD and the gate of the driving transistor M3;
  • the first light-emitting control transistor M5 is respectively coupled between the first power supply terminal VDD and the second electrode of the driving transistor M3, and its gate is coupled with the light-emitting control terminal EM;
  • the second light-emitting control transistor M6 is respectively coupled between the first electrode of the driving transistor M3 and the first electrode of the light-emitting device 30, and its gate is coupled with the light-emitting control terminal EM;
  • the data writing transistor M4 is respectively coupled between the second pole of the driving transistor M3 and the data signal terminal D, and its gate is coupled to the second scan control terminal G;
  • the second reset transistor M7 is respectively coupled between the first electrode of the light-emitting device 30 and the initialization signal terminal Vinit, and its gate is coupled to the second scan control terminal G;
  • the second pole of the light emitting device 30 is coupled to the second power terminal VSS.
  • the pixel driving circuit 40 includes a compensation transistor M2, a first reset transistor M1, a driving transistor M3, a first emission control transistor M5, a second emission control transistor M6, a data writing transistor Seven transistors including transistor M4 and second reset transistor M7.
  • the compensation transistor M2 and the first reset transistor M1 are both oxide transistors 50
  • the driving transistor M3, the first light emission control transistor M5, the second light emission control transistor M6, the data writing transistor M4 and the second reset transistor M7 are all polysilicon.
  • Transistor 70 the compensation transistor M2 is coupled between the gate electrode and the first electrode of the driving transistor M3 respectively, and the gate electrode is coupled to the first scan control terminal S.
  • the first reset transistor M1 is respectively coupled between the gate of the driving transistor M3 and the initialization signal terminal Vinit, and the gate is coupled to the first scan control terminal S. In this case, when the first reset transistor M1 is turned on, The gate of the driving transistor M3 is reset through the first scan control terminal S.
  • the storage capacitor 60 is coupled between the first power terminal VDD and the gate of the driving transistor M3 respectively.
  • the first power terminal VDD can be a high-potential power terminal and can provide a constant high-potential signal.
  • the data writing transistor M4 is respectively coupled between the second electrode of the driving transistor M3 and the data signal terminal D, and its gate is coupled to the second scan control terminal G. In this case, when the data writing transistor M4 is turned on, the second electrode of the driving transistor M3 can be charged through the data signal terminal D, and when the compensation transistor M2 is turned on, the threshold voltage of the driving transistor M3 and the data signal can be charged.
  • the data signal provided by the terminal D is written into the gate of the driving transistor M3, thereby realizing compensation for the threshold voltage of the driving transistor M3.
  • the first light-emitting control transistor M5 is coupled between the first power terminal VDD and the second electrode of the driving transistor M3, and the gate is coupled to the light-emitting control terminal;
  • the second light-emitting control transistor M6 is coupled to the driving transistor respectively. between the second electrode of M3 and the data signal terminal D, and the gate is coupled to the light-emitting control terminal; in this case, when the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned on, the light-emitting device 30 emits light.
  • the second reset transistor M7 is respectively coupled to the first electrode of the light emitting device 30 and the initialization signal. between the signal terminal Vinit, and the gate is coupled to the second scan control terminal G.
  • the initialization signal provided by the initialization signal terminal Vinit can be written into the first terminal of the light-emitting device 30 pole, when the first pole of the light-emitting device 30 is anode, the anode is reset, thereby ensuring low-frequency display.
  • the second pole of the light-emitting device 30 is coupled to the second power terminal VSS.
  • the second power terminal VSS can be a low-potential power terminal and can provide a constant low-potential signal.
  • the storage capacitor 60 is respectively coupled between the first power terminal VDD and the gate of the driving transistor M3. The storage capacitor 60 ensures the stability of the gate of the driving transistor M3, thereby ensuring the driving effect of the pixel driving circuit 40.
  • the compensation transistor M2 and the first reset transistor M1 are both N-type transistors.
  • the data writing transistor M4 and the second reset transistor M7 are both P-type transistors.
  • the active layer of the compensation transistor M2 and the first reset transistor M1 is a metal oxide semiconductor material, which can be IGZO, or a metal oxide such as indium tin zinc oxide (ITZO), which is not discussed here. limited.
  • the compensation transistor M2 and the first reset transistor M1 may be N-type transistors using metal oxide semiconductor materials as active layers.
  • the compensation transistor M2 and the first reset transistor M1 have a small leakage current.
  • the active layers of the driving transistor M3, the first light-emitting control transistor M5, the second light-emitting control transistor M6, the data writing transistor M4 and the second reset transistor M7 are low-temperature multi-transistor materials.
  • the driving transistor M3, the first light emission control transistor M5, the second light emission control transistor M6, the data writing transistor M4 and the second reset transistor M7 may be P-type transistors using low-temperature polysilicon material as the active layer.
  • the driving transistor M3, the first light-emitting control transistor M5, the second light-emitting control transistor M6, the data writing transistor M4 and the second reset transistor M7 have relatively high mobility and low power consumption. Lower, and can be made thinner, etc.
  • the pixel driving circuit 40 shown in FIG. 7 is actually an LTPO pixel circuit, thereby ensuring that the leakage current of the gate of the driving transistor M3 is small and the power consumption is low.
  • the first reset transistor M1 may be disposed above the second electrode 62 , and the compensation transistor M2 may be used as another transistor and is not disposed above the second electrode 62 .
  • the gate and active layer of the first reset transistor M1 The distance between them is greater than the distance between the gate of the compensation transistor M2 and the active layer.
  • the compensation transistor M2 may be disposed above the second electrode 62, and the first reset transistor M1 is used as another transistor and is not disposed above the second electrode 62; the compensation transistor M2 The distance between the gate electrode and the active layer is greater than the distance between the gate electrode of the first reset transistor M1 and the active layer.
  • the transistor located above the second electrode 62 among the at least two oxide transistors 50 may be configured according to actual application requirements, which is not limited herein.
  • the light-emitting device 30 in the embodiment of the present disclosure can be configured as an electroluminescent diode, such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED), a micro-LED At least one of inorganic light emitting diodes (micro Light Emitting Diode/Mini Light Emitting Diode), which is not limited here.
  • the light-emitting device 30 may include a stacked anode, a light-emitting layer, and a cathode.
  • the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the light-emitting device 30 can be designed according to the requirements of the actual application environment, and there is no limitation here.
  • the first pole and the second pole of each transistor mentioned above can be interchangeable according to the corresponding type and the signal at the signal end.
  • the first pole may be the source, and the second pole may be the drain.
  • the first pole may be the drain, and the second pole may be the source.
  • Each transistor can be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor, MOS), which is not limited here.
  • TFT thin film transistor
  • MOS Metal Oxide Semiconductor
  • the specific type of each transistor can also be set according to actual application needs, which is not limited here.
  • the above are only examples to illustrate the specific structure of the display substrate provided by the embodiments of the present disclosure.
  • the specific structure of the above-mentioned display substrate is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may also be other structures known to those skilled in the art. , these are all within the protection scope of the present disclosure and are not limited here.
  • an embodiment of the present disclosure also provides a display device, which includes any of the above display substrates.
  • the principle of solving the problem of this display device is similar to that of the aforementioned display substrate. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display substrate, and repeated descriptions will not be repeated.
  • the display device provided by the embodiments of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • an embodiment of the present disclosure also provides a manufacturing method for the above-mentioned display substrate.
  • the manufacturing method includes:
  • S101 Sequentially form patterns of the first electrode and the second electrode of the storage capacitor and the active layers of the at least two oxide transistors on the base substrate;
  • S102 Form a pattern of a gate insulating layer on a side of the active layer of the at least two oxide transistors facing away from the base substrate, so that the second electrode of the at least two oxide transistors is located The distance between the gate of the upper transistor and the active layer is greater than the distance between the gate of the other transistors and the active layer.
  • step S102 forming a pattern of a gate insulating layer on a side of the active layer of the at least two oxide transistors facing away from the base substrate, including:
  • S201 Deposit a first thickness of the gate insulating layer on the side of the active layer of the at least two oxide transistors facing away from the base substrate;
  • S203 Pattern the photoresist using a patterning process, remove the photoresist at corresponding positions of the other transistors, and form a pattern of the photoresist;
  • S204 According to the pattern of the photoresist, etch away a third thickness of the gate insulating layer at corresponding positions of the other transistors, where the difference between the first thickness and the third thickness is a third thickness. Two thicknesses, the first thickness being greater than the second thickness;
  • the pattern of the active layer 700 of the polysilicon transistor 70 is sequentially formed on the base substrate 10.
  • Vth is negatively biased.
  • the first thickness is greater than the thickness of the gate insulating layer 80 in Figure 3, so that the Vth of the N-type oxide transistor is forward biased.
  • the influence of the DC voltage can be offset, thereby restoring the N-type oxide transistor to a normal level.
  • the first thickness may be 2000 Angstroms.
  • the specific value of the first thickness can also be set according to actual application needs, which is not limited here.
  • photoresist PR is coated on the gate insulating layer 80 of the first thickness. Then, a patterning process is used to pattern the photoresist PR, and the photoresist PR at corresponding positions of other transistors 502 is removed to form a pattern of the photoresist PR.
  • the photoresist PR at a TFT channel that is not on the storage capacitor 60 can be removed by exposure and development, and then the dry etching process can be used to etch this part.
  • the gate insulating layer 80 corresponding to the other transistor 502 may be etched to a third thickness according to the pattern of the photoresist PR. In one exemplary embodiment, the third thickness is 1000 Angstroms. In this case, the The final thickness of the gate insulating layer 80 at this location is 1000 angstroms. In this way, the uniformity of the threshold voltage of each transistor is ensured.
  • a gate electrode of the oxide transistor 50 is deposited, and a pattern of the gate electrode of the oxide transistor 50 is formed; then, a second interlayer insulating layer 130 is deposited on a side of the gate electrode of the oxide transistor 50 facing away from the base substrate 10 . Then, the vias are typed and etched. Considering that in the mass production process, the active layer 700 of the polysilicon transistor 70 needs to be cleaned, which can be done through two masks. The specific layout and etching process can refer to the specific implementation in related technologies, which will not be discussed here. Elaborate. Then, a source and drain electrode layer is deposited, and the source and drain electrodes of the oxide transistor 50 and the source and drain electrodes of the polysilicon transistor 70 are formed on the same layer.
  • the figure only illustrates the location of the metal interconnection, and does not illustrate the signal lines corresponding to the data signal terminal D and the first power terminal VDD. In actual applications, it can be determined according to the layout. If required, use a single-layer source-drain electrode layer or a double-layer source-drain electrode layer to layout the corresponding signal lines, which will not be described in detail here. In addition, for the production process of other film layers in the display substrate, reference can be made to the specific implementation in related technologies, and will not be described in detail here.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • the display substrate includes a base substrate 10 and a plurality of sub-pixels 20 arranged in an array on the base substrate 10.
  • Each sub-pixel 20 includes a light-emitting device. 30 and a pixel driving circuit 40 for driving the light-emitting device 30.
  • the pixel driving circuit 40 includes at least two oxide transistors 50 and a storage capacitor 60; wherein the storage capacitor 60 includes a plurality of pixels that are sequentially away from the base substrate 10 and arranged oppositely.
  • Farther apart transistors are located above the second electrode 62 . That is to say, the distance between the gate electrode and the active layer of the transistor located above the second electrode 62 among the at least two oxide transistors 50 is larger than the distance between the gate electrode and the active layer of the other transistor not located above the second electrode 62 the distance between.
  • the gate electrode 5011 of the transistor will be in contact with the active layer.
  • the larger distance between them can correspondingly shift the threshold voltage in the opposite direction, and the two cancel each other out, thus ensuring the uniformity of the threshold voltage of the transistor and improving the display effect.

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Abstract

本公开提供了一种显示基板、其制作方法及显示装置，该显示基板包括：衬底基板以及阵列排布在所述衬底基板上的多个子像素，各个所述子像素包括发光器件以及用于驱动所述发光器件的像素驱动电路，所述像素驱动电路包括至少两个氧化物晶体管和存储电容；所述存储电容包括依次背离所述衬底基板且相对设置的第一电极和第二电极，所述至少两个氧化物晶体管中至少两个晶体管的栅极与有源层之间的距离不同，且所述至少两个氧化物晶体管中栅极与有源层之间距离远的晶体管位于所述第二电极的上方。用于保证薄膜晶体管的阈值电压的均匀性，提高显示效果。

Description

显示基板、其制作方法及显示装置
相关申请的交叉引用
本公开要求在2022年06月13日提交中国专利局、申请号为202210661034.X、申请名称为“一种显示基板、其制作方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板、其制作方法及显示装置。
背景技术
有机电致发光显示面板(Organic Electro-luminesecent Display，OLED)凭借其低功耗、高色饱和度、广视角、薄厚度、能实现柔性化等优异性能，逐渐成为显示领域的主流，可以广泛应用于智能手机、平板电脑、电视等终端产品。
目前OLED的驱动电路通常采用低温多晶硅(Low Temperature Poly-silicon，LTPS)作为驱动薄膜晶体管(Driver Thin Film Transistor，DTFT)的沟道。LTPS相对于a-Si具有较高的迁移率，但是LTPS由于结晶时产生的晶界，以及晶粒大小的不均匀分布，常常需要复杂的驱动电路对DTFT的阈值电压(Vth)进行补偿，补偿的最终结果是消除DTFT Vth不均匀导致的显示Mura。常采用如图1所示的7T1C像素补偿电路，该像素补偿电路包括T1、T2、T3、T4、T5、T6和T7在内的七个晶体管，T3为DTFT，Cst为存储电容。
目前针对低频降低漏电的需求，常采用将LTPS TFT和氧化物(Oxide)TFT相结合的LTPO背板。该LTPO背板中的驱动电路可以在图1的基础上，将T1和T2替换成Oxide TFT，利用Oxide TFT漏电低的特点，降低低频时 Cst漏电带来的闪烁不良。如何避免DTFT Vth的不均匀成为急需解决的技术问题。
发明内容
本公开提供了一种显示基板、其制作方法及显示装置，用于保证薄膜晶体管的阈值电压的均匀性，提高显示效果。
第一方面，本公开实施例提供了一种显示基板，包括：
衬底基板以及阵列排布在所述衬底基板上的多个子像素，各个所述子像素包括发光器件以及用于驱动所述发光器件的像素驱动电路，所述像素驱动电路包括至少两个氧化物晶体管和存储电容；
其中，所述存储电容包括依次背离所述衬底基板且相对设置的第一电极和第二电极，所述至少两个氧化物晶体管中至少两个晶体管的栅极与有源层之间的距离不同，且所述至少两个氧化物晶体管中栅极与有源层之间距离远的晶体管位于所述第二电极的上方。
在一种可能的实现方式中，所述第二电极与所述至少两个氧化物晶体管的有源层部分交叠。
在一种可能的实现方式中，所述像素驱动电路还包括与所述至少两个氧化物晶体管耦接的至少一个多晶硅晶体管，所述至少一个多晶硅晶体管的栅极与所述第一电极同层设置，且所述至少两个氧化物晶体管设置在所述第二电极背离所述衬底基板的一侧。
在一种可能的实现方式中，所述至少两个氧化物晶体管的有源层在所述衬底基板上的正投影完全落入所述至少一个多晶硅晶体管的有源层在所述衬底基板上的正投影的区域范围内。
在一种可能的实现方式中，所述第二电极在所述衬底基板上的正投影完全落入所述第一电极在所述衬底基板上的正投影的区域范围内。
在一种可能的实现方式中，所述至少两个氧化物晶体管包括补偿晶体管和第一复位晶体管，所述像素驱动电路还包括均为多晶硅晶体管的驱动晶体 管、第一发光控制晶体管、第二发光控制晶体管、数据写入晶体管、第二复位晶体管；
其中，所述补偿晶体管分别耦接于所述驱动晶体管的栅极和第一极之间，且栅极与第一扫描控制端耦接；
所述第一复位晶体管分别耦接于驱动晶体管的栅极和初始化信号端之间，且栅极与所述第一扫描控制端耦接；
所述存储电容分别耦接于第一电源端和所述驱动晶体管的栅极之间；
所述第一发光控制晶体管分别耦接于所述第一电源端和所述驱动晶体管的第二极之间，且栅极与发光控制端耦接；
所述第二发光控制晶体管分别耦接于所述驱动晶体管的第一极和所述发光器件的第一极之间，且栅极与所述发光控制端耦接；
所述数据写入晶体管分别耦接于所述驱动晶体管的第二极和数据信号端之间，且栅极与第二扫描控制端耦接；
所述第二复位晶体管分别耦接于所述发光器件的第一极和所述初始化信号端之间，且栅极与所述第二扫描控制端耦接；
所述发光器件的第二极与第二电源端耦接。
在一种可能的实现方式中，所述补偿晶体管和所述第一复位晶体管均为N型晶体管，所述驱动晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管、所述数据写入晶体管和所述第二复位晶体管均为P型晶体管。
第二方面，本公开实施例还提供了一种显示装置，包括：
如上面任一项所述的显示基板。
第三方面，本公开实施例还提供了一种如上面任一项所述的显示基板的制作方法，包括：
在所述衬底基板上依次形成所述存储电容的所述第一电极和所述第二电极、所述至少两个氧化物晶体管的有源层的图案；
在所述至少两个氧化物晶体管的有源层背离所述衬底基板的一侧，形成栅极绝缘层的图案，以使所述至少两个氧化物晶体管中位于所述第二电极上 方的晶体管的栅极与有源层之间的距离大于其它晶体管的栅极与有源层之间的距离。
在一种可能的实现方式中，在所述至少两个氧化物晶体管的有源层背离所述衬底基板的一侧，形成栅极绝缘层的图案，包括：
在所述至少两个氧化物晶体管的有源层背离所述衬底基板的一侧，沉积第一厚度的所述栅极绝缘层；
在所述栅极绝缘层上涂布光刻胶；
利用构图工艺对所述光刻胶进行图案化，去除所述其它晶体管对应位置的光刻胶，形成所述光刻胶的图案；
根据所述光刻胶的图案，将所述其它晶体管对应位置的所述栅极绝缘层刻蚀掉第三厚度，其中，所述第一厚度与所述第三厚度的差值为第二厚度，所述第一厚度大于所述第二厚度；
去除所述光刻胶的图案，形成所述栅极绝缘层的图案。
本公开的有益效果如下：
本公开实施例提供了一种显示基板、其制作方法及显示装置，该显示基板包括衬底基板以及阵列排布在该衬底基板上的多个子像素，各个子像素包括发光器件以及用于驱动该发光器件的像素驱动电路，该像素驱动电路包括至少两个氧化物晶体管和存储电容；其中，该存储电容包括依次背离衬底基板且相对设置的第一电极和第二电极，至少两个氧化物晶体管中至少两个晶体管的栅极与有源层之间的距离不同，且至少两个氧化物晶体管中栅极与有源层之间距离远的晶体管位于第二电极的上方。也就是说，至少两个氧化物晶体管中位于第二电极上方的晶体管的栅极与有源层之间的距离，大于未在第二电极上方的其它晶体管的栅极与有源层之间的距离。这样的话，在减少氧化物晶体管的布局空间，提高分辨率的同时，即便第二电极接收恒定电压信号致使位于其上方的晶体管的阈值电压偏移时，该晶体管的栅极与有源层之间的较大距离可以相应地使其阈值电压反向偏移，二者相互抵消，从而保证了晶体管的阈值电压的均匀性，提高了显示效果。
附图说明
图1为相关技术中7T1C像素补偿电路的其中一种电路结构示意图；
图2为相关技术中LTPO背板采用的驱动电路的其中一种电路结构示意图；
图3为图2对应的其中一种膜层结构示意图；
图4为图2对应的另外一种膜层结构示意图；
图5为本公开实施例提供的一种显示基板的其中一种俯视结构示意图；
图6为沿图5中MM所示方向的其中一种剖面结构示意图；
图7为本公开实施例提供的一种显示基板中像素驱动电路的其中一种电路结构示意图；
图8为本公开实施例提供的一种显示基板的制作方法的其中一种方法流程图；
图9为图8中步骤S102的其中一种方法流程图；
图10为图8和图9对应的其中一种工艺流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是 示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
在相关技术中，LTPO背板可以采用图2所示的驱动电路以及图3所示的膜层结构。其中，01表示Oxide TFT，02表示存储电容，03表示LTPS TFT。最终形成的子像素的间距(Pitch)为56μm，相应的像素密度(Pixels Per Inch，PPI)约为450。但在图3对应的背板工艺中，Oxide TFT在设计时避开了下方LTPS TFT的所有膜层，导致分辨率较低。
为了提高LTPO背板的PPI，可以采用图4所示的膜层结构，将其中一个Oxide TFT置于Cst上方，由于Cst的上电极接在了ELVDD上，而ELVDD为直流4.6V电压，相当于在该Oxide TFT的沟道下方接入一个直流底栅，由于直流电压恒定，并不会引起电路工作时沟道状态的跳变。最终形成的子像素的间距(Pitch)为42μm，相应的PPI约为600，相较于图3来说PPI较高。本发明人在实际研究中发现，在电路实际版图中，根据设计需求，Cst的大小尺寸通常较为有限，不能将T1和T2两个管子都置于Cst上，也就是说，只能将T1和T2中的其中一个管子置于Cst上。这样的话，4.6V的直流底栅会对置于其上方的管子的Vth产生一定程度的影响。针对图4所示的膜层结构，实际测试中，ELVDD接4.6V正电压时，位于直流底栅上的Oxide TFT将负偏大约1.2V。对于T1和T2来说，如果仅将其中一个管子置于Cst上，就会导致这两个Oxide TFT的开启电压有偏差，从而引起Ion偏差。这种情况在实际应用中，可能引起电容充放电异常的导致的时序问题。此外，由于T1和T2管子的沟道同层制作，不能通过沟道掺杂的方式来进行Vth的调节，也无法通过诸如铟镓锌氧化物(IGZO)的氧含量来调节同层TFT的沟道迁移率。
鉴于此，本公开实施例提供了一种显示基板、其制作方法及显示装置，用于保证薄膜晶体管的阈值电压的均匀性，提高显示效果。
结合图5和图6所示，本公开实施例提供了一种显示基板，其中，图5为显示基板的其中一种俯视结构示意图，图6为沿图5中MM所示方向的其中一种剖面结构示意图，该显示基板包括：
衬底基板10以及阵列排布在所述衬底基板10上的多个子像素20，各个所述子像素20包括发光器件30以及用于驱动所述发光器件30的像素驱动电路40，所述像素驱动电路40包括至少两个氧化物晶体管50和存储电容60；
其中，所述存储电容60包括依次背离所述衬底基板10且相对设置的第一电极61和第二电极62，所述至少两个氧化物晶体管50中至少两个晶体管的栅极与有源层之间的距离不同，且所述至少两个氧化物晶体管50中栅极与有源层之间距离远的晶体管位于所述第二电极62的上方。在具体实施过程中，显示基板包括衬底基板10以及阵列排布在该衬底基板10上的多个子像素20，其中，衬底基板10可以是刚性衬底，还可以是柔性衬底，在此不做限定。此外，可以根据实际应用需要来设置多个子像素20的具体个数，在此不做限定。各个子像素20包括发光器件30以及用于驱动该发光器件30的像素驱动电路40，该像素驱动电路40包括至少两个氧化物晶体管50和存储电容60。其中，各个像素驱动电路40所包括的至少两个氧化物晶体管50可以是两个，还可以是三个，可以根据实际应用需要来设置，在此不做限定。
仍结合图6所示，存储电容60包括依次背离衬底基板10且相对设置的第一电极61和第二电极62，至少两个氧化物晶体管30中至少两个晶体管的栅极与有源层之间的距离不同，且至少两个氧化物晶体管30中栅极与有源层之间距离远的晶体管位于第二电极62的上方。也就是说，至少两个氧化物晶体管30中位于第二电极62上方的晶体管的栅极与有源层之间的距离，大于未在第二电极62上方的其它晶体管的栅极与有源层之间的距离。此外，第二电极62可以被配置为接收恒定电压信号，这样的话，第二电极62可以用作位于其上方的晶体管的底栅，相应地提高了该晶体管的稳定性。结合至少两个氧化物晶体管30中位于第二电极62上方的晶体管的栅极与有源层之间的距离，大于未在第二电极62上方的其它晶体管的栅极与有源层之间的距离，可以在减少氧化物晶体管的布局空间，提高分辨率的同时，即便第二电极62接收恒定电压信号致使位于其上方的晶体管的阈值电压发生偏移时，该晶体管的栅极与有源层之间的较大距离可以相应地使其阈值电压反向偏移，二者 相互抵消，从而保证了晶体管的阈值电压的均匀性，提高了显示效果。
在具体实施过程中，至少两个氧化物晶体管50中栅极与有源层之间距离远的晶体管可以是一个，还可以是多个，相应地，至少两个氧化物晶体管50中位于第二电极62上方的晶体管可以是一个，还可以是多个，当然，可以根据实际应用需要来设置位于第二电极62上方的氧化物晶体管的个数，在此不做限定。而且，至少两个氧化物晶体管50中未设置在第二电极62上方的晶体管可以是一个，还可以是多个，在此不做限定。其中，图6中示意出了两个氧化物晶体管中其中一个晶体管位于第二电极62的上方，另一个晶体管未位于第二电极62的上方。
仍以图6所示为例，位于第二电极62上方的晶体管的栅极与有源层之间的距离为d1，其它晶体管的栅极与有源层之间的距离为d2，d1>d2。这样的话，因第二电极62接收恒定电压信号致使位于第二电极62上方的晶体管的阈值电压偏移时，该晶体管的栅极与有源层之间的较大距离可以相应地使其阈值电压反向偏移，二者相互抵消，从而保证了晶体管的阈值电压的均匀性，提高了显示效果。需要说明的是，可以根据实际应用需要来设置，位于第二电极62上方的氧化物晶体管的栅极5011与有源层之间的距离的具体数值，以及其它晶体管的栅极5021与有源层之间的距离的具体数值，在此不做限定。
需要说明的是，本发明人发现，根据MOSFET经典Vth公式：
针对置于存储电容60的第二电极62上方的N型氧化物晶体管，N型氧化物晶体管受到栅极介质层电容Cox的影响，Cox越大，N型氧化物晶体管的Vth越小。当降低栅极介质层的厚度时，Vth负偏。而当增加栅极介质层的厚度时，Vth正偏。在实际测试中，N型氧化物晶体管的宽长比为：W/L＝2.5/4，数据信号端加载的电压为10.1V时，栅极介质层厚度为1000埃时相应器件的Vth，较栅极介质层厚度为1400埃时相应器件的Vth偏负0.5V左右。如此一 来，在本公开实施例中，通过设置至少两个氧化物晶体管50中位于第二电极62上方的晶体管的栅极5011与有源层之间的距离，大于其它晶体管的栅极5021与有源层之间的距离，可以抵消因第二电极62接收恒定电压信号致使位于第二电极62上方的晶体管的阈值电压偏移的影响，有效保证了Vth的均匀性。
仍结合图6所示，所述第二电极62与所述至少两个氧化物晶体管50的有源层500部分交叠。这样的话，通过第二电极62可以在一定程度上保护至少两个氧化物晶体管50的沟道，从而保证了像素驱动电路40的驱动能力。
在本公开实施例中，仍结合图6所示，所述像素驱动电路40还包括与所述至少两个氧化物晶体管50耦接的至少一个多晶硅晶体管70，所述至少一个多晶硅晶体管70的栅极701与所述第一电极61同层设置，且所述至少两个氧化物晶体管50设置在所述第二电极62背离所述衬底基板10的一侧。
在具体实施过程中，与至少两个氧化物晶体管50耦接的至少一个多晶硅晶体管70可以是一个，还可以是多个，在此不做限定。其中，至少一个多晶硅晶体管70的栅极701与第一电极61同层设置。在实际工艺中，可以同层制作至少一个多晶硅晶体管70的栅极701和第一电极61，从而简化了制作工艺。而且至少两个氧化物晶体管50设置在第二电极62背离衬底基板10的一侧，这样的话，可以节省布局空间，从而提高了分辨率。
在本公开实施例中，仍结合图6所示，所述至少两个氧化物晶体管50的有源层500在所述衬底基板10上的正投影完全落入所述至少一个多晶硅晶体管70的有源层700在所述衬底基板10上的正投影的区域范围内。
在具体实施过程中，至少两个氧化物晶体管50的有源层500在衬底基板10上的正投影完全落入至少一个多晶硅晶体管70的有源层700在衬底基板10上的正投影的区域范围内，从而节省了布局空间，提高了分辨率。
在本公开实施例中，仍结合图6所示，所述第二电极62在所述衬底基板10上的正投影完全落入所述第一电极61在所述衬底基板10上的正投影的区域范围内。如此一来，第一电极61可以在一定程度上保护第二电极62，从而 保证了存储电容60的使用性能。
需要说明的是，仍结合图6所示，本公开实施例提供的显示基板还包括设置在氧化物晶体管50的栅极和有源层之间的栅极绝缘层80，位于第二电极62和氧化物晶体管50的有源层500之间的第一层间绝缘层90和缓冲层100，位于多晶硅晶体管70的有源层700和第一电极61之间的第一栅极绝缘层110，位于第一电极61和第二电极62之间的第二栅极绝缘层120，以及位于氧化物晶体管50的栅极背离衬底基板10一侧设置的第二层间绝缘层130。当然，还可以根据实际应用需要来设置显示基板的其它膜层，具体可以参照相关技术中的具体实现，在此不做详述。
在本公开实施例中，像素驱动电路40可以有多种设置方式。在其中一种示例性实施例中，如图7所示为像素驱动电路40的其中一种结构示意图。其中，所述至少两个氧化物晶体管50包括补偿晶体管M2和第一复位晶体管M1，所述像素驱动电路40还包括均为多晶硅晶体管的驱动晶体管M3、第一发光控制晶体管M5、第二发光控制晶体管M6、数据写入晶体管M4、第二复位晶体管M7；
其中，所述补偿晶体管M2分别耦接于所述驱动晶体管M3的栅极和第一极之间，且栅极与第一扫描控制端S耦接；
所述第一复位晶体管M1分别耦接于驱动晶体管M3的栅极和初始化信号端Vinit之间，且栅极与所述第一扫描控制端S耦接；
所述存储电容60分别耦接于第一电源端VDD和所述驱动晶体管M3的栅极之间；
所述第一发光控制晶体管M5分别耦接于所述第一电源端VDD和所述驱动晶体管M3的第二极之间，且栅极与发光控制端EM耦接；
所述第二发光控制晶体管M6分别耦接于所述驱动晶体管M3的第一极和所述发光器件30的第一极之间，且栅极与所述发光控制端EM耦接；
所述数据写入晶体管M4分别耦接于所述驱动晶体管M3的第二极和数据信号端D之间，且栅极与第二扫描控制端G耦接；
所述第二复位晶体管M7分别耦接于所述发光器件30的第一极和所述初始化信号端Vinit之间，且栅极与所述第二扫描控制端G耦接；
所述发光器件30的第二极与第二电源端VSS耦接。
仍结合图7所示，在本公开实施例中，像素驱动电路40包括补偿晶体管M2、第一复位晶体管M1、驱动晶体管M3、第一发光控制晶体管M5、第二发光控制晶体管M6、数据写入晶体管M4和第二复位晶体管M7在内的七个晶体管。其中，补偿晶体管M2和第一复位晶体管M1均为氧化物晶体管50，驱动晶体管M3、第一发光控制晶体管M5、第二发光控制晶体管M6、数据写入晶体管M4和第二复位晶体管M7均为多晶硅晶体管70。其中，补偿晶体管M2分别耦接于驱动晶体管M3的栅极和第一极之间，且栅极与第一扫描控制端S耦接。第一复位晶体管M1分别耦接于驱动晶体管M3的栅极和初始化信号端Vinit之间，且栅极与第一扫描控制端S耦接，这样的话，在第一复位晶体管M1导通时，可以通过第一扫描控制端S对驱动晶体管M3的栅极进行复位。
存储电容60分别耦接于第一电源端VDD和驱动晶体管M3的栅极之间，第一电源端VDD可以是高电位电源端，可以提供恒定的高电位信号。数据写入晶体管M4分别耦接于驱动晶体管M3的第二极和数据信号端D之间，且栅极与第二扫描控制端G耦接。这样的话，在数据写入晶体管M4导通时，可以通过数据信号端D对驱动晶体管M3的第二极进行充电，且在补偿晶体管M2导通时，可以将驱动晶体管M3的阈值电压以及数据信号端D所提供的数据信号写入驱动晶体管M3的栅极，从而实现了对驱动晶体管M3的阈值电压的补偿。此外，第一发光控制晶体管M5分别耦接于第一电源端VDD和驱动晶体管M3的第二极之间，且栅极与发光控制端耦接；第二发光控制晶体管M6分别耦接于驱动晶体管M3的第二极和数据信号端D之间，且栅极与发光控制端耦接；这样的话，在第一发光控制晶体管M5和第二发光控制晶体管M6均导通时，发光器件30发光。
而且，第二复位晶体管M7分别耦接于发光器件30的第一极和初始化信 号端Vinit之间，且栅极与第二扫描控制端G耦接，这样的话，在第二复位晶体管M7导通时，可以将初始化信号端Vinit提供的初始化信号写入发光器件30的第一极，在发光器件30的第一极为阳极时，实现了阳极重置，从而保证了低频显示。发光器件30的第二极与第二电源端VSS耦接，第二电源端VSS可以为低电位电源端，可以提供恒定的低电位信号。存储电容60分别耦接于第一电源端VDD和驱动晶体管M3的栅极之间，通过存储电容60保证了驱动晶体管M3的栅极的电位稳定，从而保证了像素驱动电路40的驱动效果。
仍结合图7所示，所述补偿晶体管M2和所述第一复位晶体管M1均为N型晶体管，所述驱动晶体管M3、所述第一发光控制晶体管M5、所述第二发光控制晶体管M6、所述数据写入晶体管M4和所述第二复位晶体管M7均为P型晶体管。在具体实施过程中，补偿晶体管M2和第一复位晶体管M1的有源层为金属氧化物半导体材料，可以是IGZO，还可以是铟锡锌氧化物(ITZO)等金属氧化物，在此不做限定。相应地，补偿晶体管M2和第一复位晶体管M1可以是用金属氧化物半导体材料作为有源层的N型晶体管。这样的话，在像素驱动电路40实际工作中，补偿晶体管M2和第一复位晶体管M1具有较小的漏电流。驱动晶体管M3、第一发光控制晶体管M5、第二发光控制晶体管M6、数据写入晶体管M4和第二复位晶体管M7的有源层为低温多晶体管材料。相应地，驱动晶体管M3、第一发光控制晶体管M5、第二发光控制晶体管M6、数据写入晶体管M4和第二复位晶体管M7可以是用低温多晶硅材料作为有源层的P型晶体管。这样的话，在像素驱动电路40实际工作中，驱动晶体管M3、第一发光控制晶体管M5、第二发光控制晶体管M6、数据写入晶体管M4和第二复位晶体管M7具有较高的迁移率，功耗更低，而且可以做的更薄等。如此一来，图7所示的像素驱动电路40实际上为LTPO像素电路，从而保证了驱动晶体管M3的栅极的漏电流较小，功耗较低。
仍结合图7所示的电路结构，在其中一种示例性实施例中，可以将第一复位晶体管M1设置在第二电极62的上方，且将补偿晶体管M2作为其它晶体管，并未设置在第二电极62的上方；第一复位晶体管M1的栅极与有源层 之间的距离，大于补偿晶体管M2的栅极与有源层之间的距离。在另外一种示例性实施例中，可以将补偿晶体管M2设置在第二电极62的上方，且将第一复位晶体管M1作为其它晶体管，并未设置在第二电极62的上方；补偿晶体管M2的栅极与有源层之间的距离，大于第一复位晶体管M1的栅极与有源层之间的距离。在具体实施过程中，可以根据实际应用需要来设置至少两个氧化物晶体管50中位于第二电极62上方的晶体管，在此不做限定。
需要说明的是，本公开实施例中的发光器件30可以设置为电致发光二极管，例如有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型无机发光二极管(micro Light Emitting Diode/Mini Light Emitting Diode)中的至少一种，在此不做限定。其中，所述发光器件30可以包括层叠设置的阳极、发光层、阴极。进一步地，发光层还可以包括空穴注入层、空穴传输层、电子传输层、电子注入层等膜层。当然，在实际应用中，可以根据实际应用环境的需求对发光器件30进行设计，在此不做限定。
上述提及的各个晶体管的第一极和第二极可以根据相应的类型以及信号端的信号的不同，其功能可以互换。比如，可以是第一极为源极，相应地第二极为漏极，再比如，可以是第一极为漏极，相应地第二极为源极，在此不做限定。各个晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)，在此不作限定。当然，还可以根据实际应用需要来设置各个晶体管的具体类型，在此不做限定。
以上仅是举例说明本公开实施例提供的显示基板的具体结构，在具体实施时，上述显示基板的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本公开的保护范围之内，在此不作限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，该显示装置包括上述任一种显示基板。该显示装置解决问题的原理与前述显示基板相似， 因此该显示装置的实施可以参见前述显示基板的实施，重复之处不再赘述。
在具体实施过程中，本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此就不做赘述，也不应作为对本公开的限制。
基于同一发明构思，如图8所示，本公开实施例还提供了上述显示基板的制作方法，该制作方法包括：
S101：在所述衬底基板上依次形成所述存储电容的所述第一电极和所述第二电极、所述至少两个氧化物晶体管的有源层的图案；
S102：在所述至少两个氧化物晶体管的有源层背离所述衬底基板的一侧，形成栅极绝缘层的图案，以使所述至少两个氧化物晶体管中位于所述第二电极上方的晶体管的栅极与有源层之间的距离大于所述其它晶体管的栅极与有源层之间的距离。
在本公开实施例中，如图9所示，步骤S102：在所述至少两个氧化物晶体管的有源层背离所述衬底基板的一侧，形成栅极绝缘层的图案，包括：
S201：在所述至少两个氧化物晶体管的有源层背离所述衬底基板的一侧，沉积第一厚度的所述栅极绝缘层；
S202：在所述栅极绝缘层上涂布光刻胶；
S203：利用构图工艺对所述光刻胶进行图案化，去除所述其它晶体管对应位置的光刻胶，形成所述光刻胶的图案；
S204：根据所述光刻胶的图案，将所述其它晶体管对应位置的所述栅极绝缘层刻蚀掉第三厚度，其中，所述第一厚度与所述第三厚度的差值为第二厚度，所述第一厚度大于所述第二厚度；
S205：去除所述光刻胶的图案，形成所述栅极绝缘层的图案。
下面以制作图6所示的显示基板为例，结合图10所示的工艺过程，对图8和图9的方法流程图进行解释说明。
首先，在衬底基板10上依次形成多晶硅晶体管70的有源层700的图案、 第一栅极绝缘层110、第一电极61的图案、第二栅极绝缘层120、第二电极62的图案、第一层间绝缘层90、缓冲层100和氧化物晶体管50的有源层500的图案；然后，在氧化物晶体管50的有源层500背离衬底基板10的一侧沉积第一厚度的栅极绝缘层80。在其中一种示例性实施例中，由于第二电极62加载的直流电压为+4.6V，对N型氧化物晶体管来说，Vth负偏，在图6中除栅极绝缘层80其它膜层结构参数与图3相应的膜层结构相同时，第一厚度大于图3中栅极绝缘层80的厚度，使得该N型氧化物晶体管的Vth正偏。这样的话，在像素驱动电路40工作时，可以抵消直流电压的影响，从而将N型氧化物晶体管恢复至正常水平。在其中一种示例性实施例中，第一厚度可以是2000埃。当然，还可以根据实际应用需要来设置第一厚度的具体数值，在此不做限定。
然后，在该第一厚度的栅极绝缘层80上涂布光刻胶PR。然后，利用构图工艺对光刻胶PR进行图案化，去除其它晶体管502对应位置的光刻胶PR，形成光刻胶PR的图案。在其中一种示例性实施例中，可以通过曝光-显影的方式去除不在存储电容60上的一个TFT沟道处的光刻胶PR，再用干刻工艺对这一部分进行刻蚀。可以是根据光刻胶PR的图案，将其它晶体管502对应位置的栅极绝缘层80刻蚀掉第三厚度，在其中一种示例性实施例中，第三厚度为1000埃，这样的话，该位置处的栅极绝缘层80的最终厚度为1000埃。如此一来，保证了各个晶体管的阈值电压的均匀性。
然后，沉积氧化物晶体管50的栅极，并形成氧化物晶体管50的栅极的图案；然后，在氧化物晶体管50的栅极背离衬底基板10的一侧沉积第二层间绝缘层130。然后，进行过孔的排版与刻蚀。考虑到量产工艺流程中，多晶硅晶体管70的有源层700需要清洗，可以通过两道掩膜板(Mask)来进行，具体排版与刻蚀过程可以参照相关技术中的具体实现，在此不做详述。然后，沉积源漏电极层，同层形成氧化物晶体管50的源漏电极以及多晶硅晶体管70的源漏电极。需要说明的是，图中仅示意了金属互联的位置，并未示意出数据信号端D和第一电源端VDD对应的信号线，在实际应用中，可以根据layout 需求，用单层源漏电极层或者双层源漏电极层进行相应信号线的排版，在此不做详述。此外，对显示基板中其它膜层的制作过程，可以参照相关技术中的具体实现，在此不做详述。
本公开实施例提供了一种显示基板、其制作方法及显示装置，该显示基板包括衬底基板10以及阵列排布在该衬底基板10上的多个子像素20，各个子像素20包括发光器件30以及用于驱动该发光器件30的像素驱动电路40，该像素驱动电路40包括至少两个氧化物晶体管50和存储电容60；其中，该存储电容60包括依次背离衬底基板10且相对设置的第一电极61和第二电极62，至少两个氧化物晶体管50中至少两个晶体管的栅极与有源层之间的距离不同，且至少两个氧化物晶体管中栅极与有源层之间距离远的晶体管位于第二电极62的上方。也就是说，至少两个氧化物晶体管50中位于第二电极62上方的晶体管的栅极与有源层之间的距离，大于未在第二电极62上方的其它晶体管的栅极与有源层之间的距离。这样的话，在减少氧化物晶体管的布局空间，提高分辨率的同时，即便第二电极62接收恒定电压信号致使位于其上方的晶体管的阈值电压偏移时，该晶体管的栅极5011与有源层之间的较大距离可以相应地使其阈值电压反向偏移，二者相互抵消，从而保证了晶体管的阈值电压的均匀性，提高了显示效果。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种显示基板，其中，包括：
    衬底基板以及阵列排布在所述衬底基板上的多个子像素，各个所述子像素包括发光器件以及用于驱动所述发光器件的像素驱动电路，所述像素驱动电路包括至少两个氧化物晶体管和存储电容；
    其中，所述存储电容包括依次背离所述衬底基板且相对设置的第一电极和第二电极，所述至少两个氧化物晶体管中至少两个晶体管的栅极与有源层之间的距离不同，且所述至少两个氧化物晶体管中栅极与有源层之间距离远的晶体管位于所述第二电极的上方。
  2. 如权利要求1所述的显示基板，其中，所述第二电极与所述至少两个氧化物晶体管的有源层部分交叠。
  3. 如权利要求2所述的显示基板，其中，所述像素驱动电路还包括与所述至少两个氧化物晶体管耦接的至少一个多晶硅晶体管，所述至少一个多晶硅晶体管的栅极与所述第一电极同层设置，且所述至少两个氧化物晶体管设置在所述第二电极背离所述衬底基板的一侧。
  4. 如权利要求3所述的显示基板，其中，所述至少两个氧化物晶体管的有源层在所述衬底基板上的正投影完全落入所述至少一个多晶硅晶体管的有源层在所述衬底基板上的正投影的区域范围内。
  5. 如权利要求1-4任一项所述的显示基板，其中，所述第二电极在所述衬底基板上的正投影完全落入所述第一电极在所述衬底基板上的正投影的区域范围内。
  6. 如权利要求5所述的显示基板，其中，所述至少两个氧化物晶体管包括补偿晶体管和第一复位晶体管，所述像素驱动电路还包括均为多晶硅晶体管的驱动晶体管、第一发光控制晶体管、第二发光控制晶体管、数据写入晶体管、第二复位晶体管；
    其中，所述补偿晶体管分别耦接于所述驱动晶体管的栅极和第一极之间， 且栅极与第一扫描控制端耦接；
    所述第一复位晶体管分别耦接于驱动晶体管的栅极和初始化信号端之间，且栅极与所述第一扫描控制端耦接；
    所述存储电容分别耦接于第一电源端和所述驱动晶体管的栅极之间；
    所述第一发光控制晶体管分别耦接于所述第一电源端和所述驱动晶体管的第二极之间，且栅极与发光控制端耦接；
    所述第二发光控制晶体管分别耦接于所述驱动晶体管的第一极和所述发光器件的第一极之间，且栅极与所述发光控制端耦接；
    所述数据写入晶体管分别耦接于所述驱动晶体管的第二极和数据信号端之间，且栅极与第二扫描控制端耦接；
    所述第二复位晶体管分别耦接于所述发光器件的第一极和所述初始化信号端之间，且栅极与所述第二扫描控制端耦接；
    所述发光器件的第二极与第二电源端耦接。
  7. 如权利要求6所述的显示基板，其中，所述补偿晶体管和所述第一复位晶体管均为N型晶体管，所述驱动晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管、所述数据写入晶体管和所述第二复位晶体管均为P型晶体管。
  8. 一种显示装置，其中，包括：
    如权利要求1-7任一项所述的显示基板。
  9. 一种如权利要求1-7任一项所述的显示基板的制作方法，其中，包括：
    在所述衬底基板上依次形成所述存储电容的所述第一电极和所述第二电极、所述至少两个氧化物晶体管的有源层的图案；
    在所述至少两个氧化物晶体管的有源层背离所述衬底基板的一侧，形成栅极绝缘层的图案，以使所述至少两个氧化物晶体管中位于所述第二电极上方的晶体管的栅极与有源层之间的距离大于其它晶体管的栅极与有源层之间的距离。
  10. 如权利要求9所述的制作方法，其中，在所述至少两个氧化物晶体 管的有源层背离所述衬底基板的一侧，形成栅极绝缘层的图案，包括：
    在所述至少两个氧化物晶体管的有源层背离所述衬底基板的一侧，沉积第一厚度的所述栅极绝缘层；
    在所述栅极绝缘层上涂布光刻胶；
    利用构图工艺对所述光刻胶进行图案化，去除所述其它晶体管对应位置的光刻胶，形成所述光刻胶的图案；
    根据所述光刻胶的图案，将所述其它晶体管对应位置的所述栅极绝缘层刻蚀掉第三厚度，其中，所述第一厚度与所述第三厚度的差值为第二厚度，所述第一厚度大于所述第二厚度；
    去除所述光刻胶的图案，形成所述栅极绝缘层的图案。
PCT/CN2023/089941 2022-06-13 2023-04-21 显示基板、其制作方法及显示装置 WO2023241217A1 (zh)

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CN107424563A (zh) * 2016-05-23 2017-12-01 乐金显示有限公司 有机发光二极管显示装置
CN113270427A (zh) * 2021-06-23 2021-08-17 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示面板

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424563A (zh) * 2016-05-23 2017-12-01 乐金显示有限公司 有机发光二极管显示装置
CN113270427A (zh) * 2021-06-23 2021-08-17 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示面板

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