WO2018201796A1 - 像素电路结构及使用其的显示器件 - Google Patents

像素电路结构及使用其的显示器件 Download PDF

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Publication number
WO2018201796A1
WO2018201796A1 PCT/CN2018/078478 CN2018078478W WO2018201796A1 WO 2018201796 A1 WO2018201796 A1 WO 2018201796A1 CN 2018078478 W CN2018078478 W CN 2018078478W WO 2018201796 A1 WO2018201796 A1 WO 2018201796A1
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Prior art keywords
thin film
film transistor
circuit structure
pixel circuit
shielding layer
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PCT/CN2018/078478
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English (en)
French (fr)
Inventor
肖丽
玄明花
陈小川
杨盛际
刘冬妮
付杰
王磊
卢鹏程
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/301,759 priority Critical patent/US10553670B2/en
Publication of WO2018201796A1 publication Critical patent/WO2018201796A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present disclosure relates to the field of display technologies, and in particular to a pixel circuit structure and a display device using the same.
  • OLED Organic Light-Emitting Diode
  • LCD Organic Light-Emitting Diode
  • OLEDs are current-driven and require a constant current to control illumination.
  • OLEDs typically use Low Temperature Poly-silicon (LTPS) processes, if large and medium-sized PPIs are used.
  • LTPS Low Temperature Poly-silicon
  • the load on the panel will be multiplied by a small amount.
  • the pitch of the pixel becomes smaller, the storage capacitance (Cst) will be sacrificed, which will greatly degrade the display performance.
  • a smaller-sized, low-resolution panel has a larger RC load (and therefore a larger resistive voltage drop), which causes VDD (ie, the thin-film transistor power line) in the LTPS OLED process.
  • VDD the thin-film transistor power line
  • the IR drop of Vdata (that is, the display data line or the display signal line) is more serious, resulting in a significant drop in panel display performance.
  • the pixel size is getting smaller and smaller, and the signal line is The width is limited by the process conditions, and the Cst is sacrificed to ensure the arrangement of the pixel circuit structure. In order to reduce the resistance load and increase the Cst, it is necessary to change the Mask or the material to be changed. Increased process steps and increased product costs.
  • a pixel circuit structure comprising: a metal light shielding layer; at least one buffer layer formed on the metal light shielding layer; a thin film transistor formed on the at least one buffer layer; formed in the An insulating layer on a gate of the thin film transistor; and a second gate formed on the insulating layer to form a storage capacitor with the gate, the second gate being electrically connected to a power line of the thin film transistor; wherein The metal light shielding layer is electrically connected to a power line of the thin film transistor.
  • the electrical connection of the metal light shielding layer to a power supply line of the thin film transistor is performed through a via.
  • the metal light shielding layer is further electrically connected to the display data line, wherein the metal light shielding layer includes at least two patterns electrically insulated from each other, and the metal light shielding layer is The pattern in which the display data lines are electrically connected is different from the pattern electrically connected to the power lines of the thin film transistors.
  • the electrical connection of the metal light shielding layer to the display data line is performed through a via.
  • the via is located at a intersection of a power line of the thin film transistor or a projection of the display data line on the metal light shielding layer and the metal light shielding layer.
  • the thin film transistor is a low temperature polysilicon thin film transistor.
  • the pixel circuit structure is used for an organic electroluminescence display device.
  • a display device comprising: the pixel circuit structure according to any of the foregoing; a display element formed on the pixel circuit structure.
  • the display element includes: a pixel electrode formed on the pixel circuit structure; a light emitting layer formed on the pixel electrode; and a light emitting layer formed on the light emitting layer Top electrode.
  • the light emitting layer is an organic light emitting layer.
  • the metal light shielding layer is electrically connected to the power line of the thin film transistor to form a metal light shielding layer in parallel with the power supply line, thereby reducing the power line resistance, reducing the panel load, reducing the resistance voltage drop, and increasing the storage. capacitance.
  • the metal light shielding layer is electrically connected to the display data line, and the metal light shielding layer is formed in parallel with the display data line to reduce the data line resistance, reduce the panel load, and reduce the resistance voltage drop.
  • FIG. 1 illustrates a top view of a pixel circuit structure in accordance with an example embodiment of the present disclosure.
  • FIG. 2 illustrates a cross-sectional view of a pixel circuit structure in accordance with an example embodiment of the present disclosure.
  • FIG. 3 illustrates a schematic diagram of a display device using a pixel circuit structure in accordance with an example embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • the example embodiments can be embodied in a variety of forms, and should not be construed as being limited to the examples set forth herein; the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are set forth However, one skilled in the art will appreciate that one or more of the specific details may be omitted or other methods, components, devices, steps, etc. may be employed.
  • the present disclosure provides a pixel circuit structure and a display device using the same.
  • the pixel circuit structure includes: a metal light shielding layer; at least one buffer layer formed on the metal light shielding layer; a thin film transistor (ie, TFT) formed on the at least one buffer layer; an insulating layer formed on a gate of the thin film transistor; and forming a second gate of the storage capacitor is formed on the insulating layer and the gate is electrically connected to the power line of the thin film transistor; wherein the metal light shielding layer and the power line of the thin film transistor (that is, the so-called VDD line are thin films) The transistor provides an operating voltage) electrical connection.
  • TFT thin film transistor
  • the metal light shielding layer is electrically connected to the display data line, and the metal light shielding layer can be formed in parallel with the display data line to reduce the data line resistance, reduce the panel load, and reduce the resistance voltage drop.
  • FIG. 1 illustrates a top view of a pixel circuit structure according to an example embodiment of the present disclosure
  • FIG. 2 illustrates an example implementation according to the present disclosure.
  • FIG. 3 shows a schematic view of a display device including a pixel circuit structure according to an example embodiment of the present disclosure.
  • FIG. 1 illustrates a top view of a pixel circuit structure in accordance with an example embodiment of the present disclosure
  • FIG. 2 illustrates a cross-sectional view of a pixel circuit structure in accordance with an example embodiment of the present disclosure.
  • the pixel circuit structure can be applied to the manufacture of a display device using a low temperature poly-silicon (LTPS) process to ensure a stable current to control the illumination while reducing the resistance voltage drop and increasing the storage capacitance, but
  • LTPS low temperature poly-silicon
  • the present invention is not limited thereto, and can also be applied to the manufacture of a display device using other TFT processes;
  • the display device may be an organic electroluminescence display device, that is, an OLED device, but the invention is not limited thereto, and may be other types of display devices.
  • the pixel circuit structure includes: a metal light shielding layer; at least one buffer layer formed on the metal light shielding layer; and a thin film transistor, that is, a TFT formed on at least one buffer layer
  • FIG. 1 is a top view, only the thin film transistor is shown a gate electrode formed on the gate of the thin film transistor; and a second gate formed on the insulating layer to form a storage capacitor with the gate, the second gate and a power line of the thin film transistor (ie, a common
  • the VDD line is said to provide a working voltage (electrical connection) for the thin film transistor; wherein the metal light shielding layer is electrically connected to the power line of the thin film transistor.
  • the metal light shielding layer is electrically connected to the power line of the thin film transistor to form a metal light shielding layer in parallel with the power supply line, thereby reducing the power line resistance, reducing the panel load, reducing the resistance drop IR drop, and increasing the storage capacitor Cst.
  • the electrical connection of the metal light shielding layer to the power supply line of the thin film transistor is performed through the via.
  • the electrical connection between the metal light shielding layer and the power line of the thin film transistor is performed through the via hole, and the metal layer structure of the existing process can be used without adding an additional metal layer, so that the original process flow is not changed and the cost is not increased.
  • the purpose of reducing the resistance voltage drop and increasing the storage capacitance is achieved.
  • the present invention is not limited thereto, and other methods may be used for electrically connecting the metal light shielding layer and the power supply line of the thin film transistor, and the purpose and technical effect of reducing the resistance voltage drop and increasing the storage capacitance can be achieved.
  • Figure 2 is a cross-sectional view taken along the line A-A' and B-B' in a plan view of the pixel circuit structure shown in Figure 1.
  • the power supply line is electrically connected to the metal light shielding layer through the via 2 passing through the buffer layer.
  • the second gate can be electrically connected to the power line of the thin film transistor through the via.
  • the power supply line is electrically connected to the second gate through the via 1 passing through the insulating layer.
  • the present invention is not limited thereto, and other methods may be used to electrically connect the second gate to the power line of the thin film transistor.
  • the metal light shielding layer is further electrically connected to the display data line, wherein the metal light shielding layer includes at least two patterns electrically insulated from each other, and the metal light shielding layer is electrically connected to the display data line The pattern is different from the pattern electrically connected to the power line of the thin film transistor.
  • the pattern in the plurality of metal light shielding layers may be electrically connected to the power line of the thin film transistor at the same time, or the pattern in the plurality of metal light shielding layers may be electrically connected to the display data line at the same time, as long as the pattern insulation electrically connected to the display data line is ensured.
  • the pattern is electrically connected to the power line of the thin film transistor.
  • the metal light shielding layer is electrically connected to the display data line, and the metal light shielding layer can also be formed in parallel with the display data line to achieve the technical effect of reducing the data line resistance, reducing the panel load, and reducing the resistance voltage drop.
  • the electrical connection of the metal light shielding layer to the display data line is performed through the via.
  • the display data lines are electrically connected to the metal light shielding layer through the via holes 3 passing through the buffer layer.
  • the present invention is not limited thereto, and other methods may be employed to electrically connect the metal light shielding layer to the display data line.
  • the via is located at the intersection of the power line of the thin film transistor or the projection of the display data line on the metal light shielding layer and the metal light shielding layer (see the via 1 in FIG. 1 and FIG. 2). Shown at 3).
  • the thin film transistor is a low temperature polysilicon thin film transistor, that is, an LTPS-TFT.
  • the present invention is not limited thereto, and the thin film transistor may be other types of TFTs.
  • a pixel circuit structure is used for an organic electroluminescence display device.
  • the present invention is not limited thereto, and the pixel circuit structure can also be applied to other types of display devices such as liquid crystal displays, inorganic electroluminescence displays, and the like.
  • the current-driven TFT pixel circuit has three-tube TFT structure, four-tube TFT structure, five tubes or even more tubes. TFT structure, but regardless of the current-driven circuit, as long as the metal light-shielding layer is electrically connected to the power line of the thin film transistor and/or the metal light-shielding layer is electrically connected to the display data line, the power line resistance can be reduced and the panel can be reduced.
  • the technical effect of increasing the storage voltage Cst and/or reducing the data line resistance, reducing the panel load, and reducing the resistance voltage drop is independent of the TFT structure of how many tubes are used.
  • FIG. 3 illustrates a schematic diagram of a display device using a pixel circuit structure in accordance with an example embodiment of the present disclosure.
  • the display device may be a display device manufactured by using a low-temperature polysilicon process to ensure that the resistance voltage drop and the storage capacitance are reduced while obtaining a stable current to control the light emission, but the invention is not limited thereto, and other TFTs may be used.
  • the display device manufactured by the process; in addition, the display device may be an organic electroluminescence display device, that is, an OLED device, but the invention is not limited thereto, and may be other types of display devices.
  • a display device includes: a pixel circuit structure according to the above embodiment; a display element formed on a pixel circuit structure.
  • the pixel circuit structure includes at least: a metal light shielding layer; at least one buffer layer formed on the metal light shielding layer; and a thin film transistor formed on the at least one buffer layer
  • FIG. 1 is a plan view showing only a gate of the thin film transistor
  • An insulating layer on the gate of the thin film transistor and a second gate formed on the insulating layer and forming a storage capacitor with the gate; the second gate is electrically connected to the power line of the thin film transistor; wherein the metal light shielding layer and the thin film transistor are powered Line electrical connection.
  • the metal light shielding layer is electrically connected to the power line of the thin film transistor to form a metal light shielding layer in parallel with the power supply line, thereby reducing the power line resistance, reducing the panel load, reducing the resistance drop IR drop, and increasing the storage capacitor Cst.
  • the display element includes: a pixel electrode formed on the pixel circuit structure, the source of the thin film transistor being electrically connected to the pixel electrode to provide a driving current to the display element to cause the display element to emit light; a light emitting layer formed on the pixel electrode; and being formed on the light emitting layer Top electrode on top.
  • the top electrode is a light-emitting surface, and is usually a transparent electrode having a high light transmittance.
  • the commonly used transparent electrode is indium tin oxide or ITO.
  • the light emitting layer is an organic light emitting layer.
  • the display device using the pixel circuit structure described in the foregoing embodiment can achieve a reduction in the resistance voltage drop and an increase in the storage capacitance while obtaining a stable current to control the light emission.
  • the metal light shielding layer is electrically connected to the power line of the thin film transistor to form a metal light shielding layer in parallel with the power supply line, thereby reducing the power line resistance, reducing the panel load, and reducing the resistance voltage drop. ; increase the storage capacitor at the same time.
  • the metal light shielding layer is electrically connected to the display data line, and the metal light shielding layer is formed in parallel with the display data line to reduce the data line resistance, reduce the panel load, and reduce the resistance voltage drop.
  • the electrical connection between the metal light shielding layer and the power supply line and/or the display data line of the thin film transistor is performed through via holes, and the metal layer structure of the prior art can be used without adding an additional metal layer, thereby The purpose of reducing the resistance voltage drop and increasing the storage capacitance is achieved without changing the original process flow and without increasing the cost.

Abstract

一种像素电路结构及其使用其的显示器件。像素电路结构包括：金属遮光层；形成在金属遮光层上的至少一个缓冲层；形成在至少一个缓冲层上的薄膜晶体管；形成在薄膜晶体管的栅极上的绝缘层；以及形成在绝缘层上与栅极形成存储电容的第二栅极，第二栅极与薄膜晶体管的电源线连接；金属遮光层与薄膜晶体管的电源线电连接。通过金属遮光层与薄膜晶体管的电源线电连接，形成金属遮光层与电源线并联，降低电源线电阻，减小面板负载，减小电阻压降IR drop；同时增大存储电容C st。

Description

像素电路结构及使用其的显示器件
交叉引用
本公开要求于2017年5月4日递交的中国专利申请第201710309568.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种像素电路结构及使用其的显示器件。
背景技术
有机发光二极管(Organic Light-Emitting Diode,OLED)是近年来逐渐发展起来的显示照明技术，尤其在显示行业，是当今平板显示器研究领域的热点之一，与液晶显示器相比，由于其具有高响应、高对比度、可柔性化、低能耗、生产成本低、自发光、宽视角及响应速度快等优点，目前，在手机、PDA、数码相机等显示领域OLED已经开始取代传统的LCD显示屏，被视为拥有广泛的应用前景，具有重要的研究意义。尤其是顶发射OLED器件，由于具有更高的开口率，和利用微腔效应实现光取出优化等优点，成为研究的主要方向。
与TFT-LCD利用稳定的电压控制亮度不同，OLED属于电流驱动，需要稳定的电流来控制发光，OLED通常采用的低温多晶硅(Low Temperature Poly-silicon，LTPS)制程，若在中大尺寸的高PPI面板使用时，面板的负载较小尺寸会成倍增大，由于像素间距(Pitch)变小也会牺牲掉部分的存储电容(Cst)，这样会使显示性能大幅下降。
在中尺寸高PPI面板设计中，较小尺寸低分辨率的面板具有较大的RC负载(因此具有较大的电阻压降)，这样在LTPS OLED制程中会造成VDD(即薄膜晶体管的电源线)和Vdata(即显示数据线或者说显示信号线)等的IR压降(drop)较为严重，导致面板显示性能大幅下降，同时，在高PPI面板中，像素尺寸越来越小，信号线的宽度受工艺条件限制较大，会牺牲部分的Cst来保证像素电路结构的排布，为减小电阻负载及增加Cst，就必须从增加Mask即掩模或更换材料等方法进行改变，这样会大大增加了工艺制程的步骤，提高产品成本。
因此，设计一种新的像素电路结构及使用其的显示器件是目前亟待解决的技术问题。
在所述背景技术部分公开的上述信息仅用于加强对本发明的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种像素电路结构及使用其的显示器件，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
本公开的其他特性和优点将通过下面的详细描述变得清晰，或者部分地通过本公开的实践而习得。
根据本公开的第一方面，提供一种像素电路结构，包括：金属遮光层；形成在金属遮光层上的至少一个缓冲层；形成在所述至少一个缓冲层上的薄膜晶体管；形成在所述薄膜晶体管的栅极上的绝缘层；以及形成在所述绝缘层上与所述栅极形成存储电容的第二栅极，所述第二栅极与所述薄膜晶体管的电源线电连接；其中所述金属遮光层与所述薄膜晶体管的电源线电连接。
在本公开的一种示例性实施例中，通过过孔来进行所述金属遮光层与所述薄膜晶体管的电源线的所述电连接。
在本公开的一种示例性实施例中，所述金属遮光层还与显示数据线电连接，其中所述金属遮光层包括相互之间电绝缘的至少两个图案，所述金属遮光层中与所述显示数据线电连接的图案不同于与所述薄膜晶体管的电源线电连接的图案。
在本公开的一种示例性实施例中，通过过孔来进行所述金属遮光层与所述显示数据线的所述电连接。
在本公开的一种示例性实施例中，所述过孔位于所述薄膜晶体管的电源线或所述显示数据线在所述金属遮光层上的投影与所述金属遮光层的交叉处。
在本公开的一种示例性实施例中，所述薄膜晶体管为低温多晶硅薄膜晶体管。
在本公开的一种示例性实施例中，所述像素电路结构用于有机电致发光显示器件。
根据本公开的第二方面，提供一种显示器件，包括：根据任一前述的像素电路结构；形成在所述像素电路结构上的显示元件。
在本公开的一种示例性实施例中，所述显示元件包括：形成在所述像素电路结构上的像素电极；形成在所述像素电极上的发光层；以及形成在所述发光层上的顶电极。
在本公开的一种示例性实施例中，所述发光层为有机发光层。
根据本公开的一些实施方式，通过金属遮光层与薄膜晶体管的电源线电连接，形成金属遮光层与电源线并联，降低电源线电阻，减小面板负载，减小电阻压降；同时增大存储电容。
根据本公开的一些实施方式，通过金属遮光层与显示数据线电连接，形成金属遮光层与显示数据线并联，降低数据线电阻，减小面板负载，减小电阻压降。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
通过参照附图详细描述其示例实施例，本发明的上述和其它目标、特征及优点将变得更加显而易见。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出根据本公开一示例实施方式的像素电路结构的俯视图。
图2示出根据本公开一示例实施方式的像素电路结构的截面图。
图3示出使用根据本公开一示例实施方式的像素电路结构的显示器件的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。
需要指出的是，在附图中，为了图示的清晰可能会夸大层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
本公开提供一种像素电路结构及使用其的显示器件。像素电路结构包括：金属遮光层；形成在金属遮光层上的至少一个缓冲层；形成在至少一个缓冲层上的薄膜晶体管(即TFT)；形成在薄膜晶体管的栅极上的绝缘层；以及形成在绝缘层上与栅极形成存储电容的第二栅极，第二栅极与薄膜晶体管的电源线电连接；其中金属遮光层与薄膜晶体管的电源线(即通常所说的VDD线，为薄膜晶体管提供工作电压)电连接。通过金属遮光层与薄膜晶体管的电源线电连接，形成金属遮光层与电源线并联，降低电源线电阻，减小面板负载，减小电阻压降IR drop；同时增大存储电容Cst；此外，同时通过金属遮光层与显示数据线电连接，也能够形成金属遮光层与显示数据线并联，降低数据线电阻，减小面板负载，减小电阻压降。
下面结合附图对本公开的像素电路结构及使用其的显示器件进行具体说明，其中，图1示出根据本公开一示例实施方式的像素电路结构的俯视图；图2示出根据本公开一示例实施方式的像素电路结构的截面图；图3示出包括根据本公开一示例实施方式的像素电路结构的显示器件的示意图。
首先结合图1-2就像素电路结构进行详细说明。
图1示出根据本公开一示例实施方式的像素电路结构的俯视图；图2示出根据本公开一示例实施方式的像素电路结构的截面图。其中像素电路结构可应用于采用低温多晶硅(Low Temperature Poly-silicon,LTPS)制程的显示器件的制造以保证在获得稳定的电流来控制发光的同时能够减小电阻压降和增大存储电容，但本发明不限于此，也可以应用于采用其他TFT制程的显示器件的制造；显示器件可为有机电致发光显示器件即OLED器件，但本发明不限于此，也可以为其他类型的显示器件。
如图1所示，像素电路结构包括：金属遮光层；形成在金属遮光层上的至少一个缓冲层；形成在至少一个缓冲层上的薄膜晶体管即TFT(图1为俯视图，仅示出薄膜晶体管的栅极)； 形成在薄膜晶体管的栅极上的绝缘层；以及形成在绝缘层上与栅极形成存储电容的第二栅极，该第二栅极与薄膜晶体管的电源线(即通常所说的VDD线，为薄膜晶体管提供工作电压)电连接；其中金属遮光层与薄膜晶体管的电源线电连接。通过金属遮光层与薄膜晶体管的电源线电连接，形成金属遮光层与电源线并联，降低电源线电阻，减小面板负载，减小电阻压降IR drop；同时增大存储电容Cst。
在本公开的一种示例性实施例中，通过过孔来进行金属遮光层与薄膜晶体管的电源线的电连接。通过过孔来进行金属遮光层与薄膜晶体管的电源线的电连接，可使用现有工艺的金属层结构，无需增加额外的金属层，从而在不改变原有的工艺流程及不增加成本的情况下实现减小电阻压降和增大存储电容的目的。但本发明不限于此，也可以采用其他的方式来进行金属遮光层与薄膜晶体管的电源线的电连接，都可实现减小电阻压降和增大存储电容的目的和技术效果。
图2是图1中所示的像素电路结构的俯视图中沿A-A’和B-B’方向的截面图。
如图2中沿A-A’方向的截面图所示，电源线通过穿过缓冲层的过孔2与金属遮光层电连接。
同样的，也可以通过过孔来进行第二栅极与薄膜晶体管的电源线电连接。如图2中沿B-B’方向的截面图所示，电源线通过穿过绝缘层的过孔1与第二栅极电连接。但本发明不限于此，也可以采用其他的方式来进行第二栅极与薄膜晶体管的电源线电连接。
在本公开的一种示例性实施例中，金属遮光层还与显示数据线电连接，其中金属遮光层包括相互之间电绝缘的至少两个图案，金属遮光层中与显示数据线电连接的图案不同于与薄膜晶体管的电源线电连接的图案。
可以同时有多个金属遮光层中的图案与薄膜晶体管的电源线电连接，也可以同时有多个金属遮光层中的图案与显示数据线电连接，只要保证与显示数据线电连接的图案绝缘于与薄膜晶体管的电源线电连接的图案即可。
通过金属遮光层与显示数据线电连接，也能够形成金属遮光层与显示数据线并联，以实现降低数据线电阻，减小面板负载，减小电阻压降的技术效果。
在本公开的一种示例性实施例中，通过过孔来进行金属遮光层与显示数据线的电连接。如图2中沿A-A’方向的截面图所示，显示数据线通过穿过缓冲层的过孔3与金属遮光层电连接。但本发明不限于此，也可以采用其他的方式来进行金属遮光层与显示数据线的电连接。
在本公开的一种示例性实施例中，过孔位于薄膜晶体管的电源线或显示数据线在金属遮光层上的投影与金属遮光层的交叉处(如图1、2中的过孔1-3处所示)。
在本公开的一种示例性实施例中，薄膜晶体管为低温多晶硅薄膜晶体管即LTPS-TFT。但本发明不限于此，薄膜晶体管也可以为其他类型的TFT。
在本公开的一种示例性实施例中，像素电路结构用于有机电致发光显示器件。但本发明不限于此，像素电路结构也可以用于如液晶显示器、无机电致发光显示器等他类型的显示器件。
在此需要特别指出的是，电流驱动的TFT像素电路的具体实现驱动电路结构虽然有很多 种，目前报道过的电流驱动型电路主要有三管TFT结构、四管TFT结构、五管甚至更多管TFT结构，但是不管是何种电流驱动型电路，只要通过金属遮光层与薄膜晶体管的电源线电连接和/或金属遮光层与显示数据线电连接，均可实现降低电源线电阻、减小面板负载、减小电阻压降IR drop同时增大存储电容Cst和/或降低数据线电阻、减小面板负载、减小电阻压降的技术效果，与具体采用多少管的TFT结构无关。
下面结合图3就使用上述实施方式所述的像素电路结构的显示器件进行详细说明。
图3示出使用根据本公开一示例实施方式的像素电路结构的显示器件的示意图。其中显示器件可为采用低温多晶硅制程制造的显示器件以保证在获得稳定的电流来控制发光的同时能够减小电阻压降和增大存储电容，但本发明不限于此，也可以为采用其他TFT制程制造的显示器件；此外，显示器件可为有机电致发光显示器件即OLED器件，但本发明不限于此，也可以为其他类型的显示器件。
如图3所示，显示器件，包括：根据上述实施方式所述的像素电路结构；形成在像素电路结构上的显示元件。
像素电路结构至少包括：金属遮光层；形成在金属遮光层上的至少一个缓冲层；形成在至少一个缓冲层上的薄膜晶体管(图1为俯视图，仅示出薄膜晶体管的栅极)；形成在薄膜晶体管的栅极上的绝缘层；以及形成在绝缘层上与栅极形成存储电容的第二栅极，第二栅极与薄膜晶体管的电源线电连接；其中金属遮光层与薄膜晶体管的电源线电连接。通过金属遮光层与薄膜晶体管的电源线电连接，形成金属遮光层与电源线并联，降低电源线电阻，减小面板负载，减小电阻压降IR drop；同时增大存储电容Cst。
显示元件包括：形成在像素电路结构上的像素电极，薄膜晶体管的源极与像素电极电连接以为显示元件提供驱动电流从而使显示元件发光；形成在像素电极上的发光层；以及形成在发光层上的顶电极。
顶电极为出光面，通常为透光率高的透明电极，常用的透明电极为氧化铟锡即ITO等。
在本公开的一种示例性实施例中，发光层为有机发光层。
使用前述实施方式所述的像素电路结构的显示器件可以实现在获得稳定的电流来控制发光的同时能够减小电阻压降和增大存储电容。
综上所述，根据本公开的一些实施方式，通过金属遮光层与薄膜晶体管的电源线电连接，形成金属遮光层与电源线并联，降低电源线电阻，减小面板负载，减小电阻压降；同时增大存储电容。
根据本公开的一些实施方式，通过金属遮光层与显示数据线电连接，形成金属遮光层与显示数据线并联，降低数据线电阻，减小面板负载，减小电阻压降。
根据本公开的一些实施方式，通过过孔来进行金属遮光层与薄膜晶体管的电源线和/或显示数据线的电连接，可使用现有工艺的金属层结构，无需增加额外的金属层，从而在不改变原有的工艺流程及不增加成本的情况下实现减小电阻压降和增大存储电容的目的。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本发明的其它实施方案。本申请旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应 性变化遵循本发明的一般性原理并包括本发明未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本发明的真正范围和精神由下面的权利要求指出。
应当理解的是，本发明并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本发明的范围仅由所附的权利要求来限制。

Claims (10)

  1. 一种像素电路结构，包括：
    金属遮光层；
    形成在金属遮光层上的至少一个缓冲层；
    形成在所述至少一个缓冲层上的薄膜晶体管；
    形成在所述薄膜晶体管的栅极上的绝缘层；以及
    形成在所述绝缘层上与所述栅极形成存储电容的第二栅极，所述第二栅极与所述薄膜晶体管的电源线电连接；
    其中所述金属遮光层与所述薄膜晶体管的电源线电连接。
  2. 根据权利要求1所述的像素电路结构，其特征在于，通过过孔来进行所述金属遮光层与所述薄膜晶体管的电源线的所述电连接。
  3. 根据权利要求1所述的像素电路结构，其特征在于，所述金属遮光层还与显示数据线电连接，其中所述金属遮光层包括相互之间电绝缘的至少两个图案，所述金属遮光层中与所述显示数据线电连接的图案不同于与所述薄膜晶体管的电源线电连接的图案。
  4. 根据权利要求3所述的像素电路结构，其特征在于，通过过孔来进行所述金属遮光层与所述显示数据线的所述电连接。
  5. 根据权利要求2或4所述的像素电路结构，其特征在于，所述过孔位于所述薄膜晶体管的电源线或所述显示数据线在所述金属遮光层上的投影与所述金属遮光层的交叉处。
  6. 根据权利要求1所述的像素电路结构，其特征在于，所述薄膜晶体管为低温多晶硅薄膜晶体管。
  7. 根据权利要求1所述的像素电路结构，其特征在于，所述像素电路结构用于有机电致发光显示器件。
  8. 一种显示器件，包括：
    根据权利要求1-6任一项所述的像素电路结构；
    形成在所述像素电路结构上的显示元件。
  9. 根据权利要求8所述的显示器件，其特征在于，所述显示元件包括：
    形成在所述像素电路结构上的像素电极；
    形成在所述像素电极上的发光层；以及
    形成在所述发光层上的顶电极。
  10. 根据权利要求9所述的显示器件，其特征在于，所述发光层为有机发光层。
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