CN107527927B - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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CN107527927B
CN107527927B CN201710846528.4A CN201710846528A CN107527927B CN 107527927 B CN107527927 B CN 107527927B CN 201710846528 A CN201710846528 A CN 201710846528A CN 107527927 B CN107527927 B CN 107527927B
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CN107527927A (zh
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石龙强
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Abstract

本发明提供一种阵列基板及其制备方法、显示装置，该阵列基板包括包括衬底基板、金属图案层、数据线图案层及扫描线图案层，金属图案层设置于衬底基板上，数据线图案层与金属图案层异层设置且与金属图案层电连接或扫描线图案层与金属图案层异层设置且与金属图案层电连接，使得数据线图案层或扫描线图案层与金属图案层形成一个并联结构，由于该并联结构的电阻小于数据线图案层或扫描线图案层电阻，使得该并联结构作为数据线或扫描线使用时的电阻变小，提高显示效果。

Description

一种阵列基板及其制备方法、显示装置
技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板及其制备方法、显示装置。
背景技术
随着科技的发展，显示器的尺寸越来越大，而大尺寸的显示器中数据线及扫描线有着很大的电阻电容负载，过大的电阻电容负载会造成输出波形的延迟，导致显示的异常。
发明内容
本发明主要提供一种阵列基板及其制备方法、显示装置，旨在解决数据线或扫描线的电阻过大而导致显示异常的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，所述阵列基板包括衬底基板、金属图案层、数据线图案层及扫描线图案层；其中，所述金属图案层设置于所述衬底基板上，所述数据线图案层或所述扫描线图案层与所述金属图案层不同层设置，且所述数据线图案层或所述扫描线图案层与所述金属图案层电连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示装置，所述显示装置包括上述的阵列基板。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种阵列基板的制备方法，所述方法包括：在衬底基板上沉积金属以形成间隔设置的金属图案层与遮光层；形成覆盖所述金属图案层的缓冲层并开设贯穿所述缓冲层且连通所述金属图案层的第一过孔；在所述缓冲层依次形成层叠设置的有源层及第一绝缘层；通过同一道光刻工艺分别在所述第一绝缘层与所述缓冲层上形成栅极图案层和扫描线图案层，所述扫描线图案层通过所述第一过孔与所述金属图案层电连接；在所述缓冲层上形成第二绝缘层；在所述第二绝缘层上形成源极图案层、漏极图案层和数据线图案层。
本发明的有益效果是：区别于现有技术的情况，本发明通过在基板上设置金属图案层，数据线图案层与金属图案层异层设置且与金属图案层电连接或扫描线图案层与金属图案层异层设置且与金属图案层电连接的方法，使得数据线图案层或扫描线图案层与金属图案层形成一个并联结构，由于该并联结构的电阻小于数据线图案层或扫描线图案层电阻，使得该并联结构作为数据线或扫描线使用时的电阻变小，提高显示效果。
附图说明
图1是本发明提供的阵列基板第一实施例的结构示意图；
图2是本发明提供的阵列基板第二实施例的结构示意图；
图3是本发明提供的阵列基板第三实施例的结构示意图；
图4是本发明提供的阵列基板第四实施例的结构示意图；
图5是本发明提供的阵列基板第五实施例的结构示意图
图6是本发明提供的显示装置实施例的结构示意图；
图7是本发明提供的阵列基板的制备方法实施例的流程示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种阵列基板及其制备方法、显示装置做进一步详细描述。
参阅图1，本发明提供的阵列基板第一实施例包括衬底基板101、金属图案层102、扫描线图案层103及数据线图案层104。
其中，金属图案层102设置于衬底基板101上，进一步的，衬底基板101上还设有遮光层105，遮光层105与金属图案层102同层间隔设置且通过同一道光刻工艺形成。
具体的，可通过物理气相沉积法或等离子体气相沉积法在衬底基板101上沉积金属材料层，然后通过曝光、显影、蚀刻及剥离的光刻工艺在衬底基板101上同时形成金属图案层102以及遮光层105。
可选的，金属材料层的金属材料为包括但不限于铝或钼的金属材料。
进一步的，扫描线图案层103与金属图案层102电连接。
具体的，衬底基板101上还设有覆盖金属图案层102的缓冲层106，缓冲层106设有贯穿缓冲层106且连通金属图案层102的第一过孔1061，具体的，可使用物理气相沉积法或等离子体气相沉积法在衬底基板101上沉积覆盖金属图案层102的氧化硅层以形成缓冲层106，在形成缓冲层106之后，通过曝光、显影、蚀刻及剥离的光刻工艺在缓冲层106蚀刻出连通金属图案层102的第一过孔1061，扫描线图案层103设置于缓冲层102上以通过第一过孔1061与金属图案层102电连接。
进一步的，缓冲层106上设有依次层叠设置的有源层107、第一绝缘层108及栅极图案层109，其中，扫描线图案层103与栅极图案层109通过同一道光刻工艺形成。
具体的，在缓冲层106上且与遮光层105相对的位置通过物理气相沉积法沉积IGZO，然后通过曝光、显影、蚀刻及剥离的光刻工艺在缓冲层106上形成IGZO图案，即可形成有源层107；进而通过物理气相沉积法在有源层107上沉积氧化硅，然后通过曝光、显影、蚀刻及剥离的光刻工艺形成第一绝缘层108；在第一绝缘层108上、缓冲层106上以及第一过孔1061中沉积金属材料，然后通过曝光、显影、蚀刻及剥离的光刻工艺分别在第一绝缘层108和缓冲层106上形成栅极图案层109以及扫描线图案层103，此时，在缓冲层106上形成的扫描线图案层103即可通过第一过孔1061中的金属材料与金属图案层102电连接。
可选的，金属材料为包括但不限于铝或钼的金属材料。
进一步的，缓冲层106上还设有覆盖栅极图案层109的第二绝缘层110，第二绝缘层110上设有源极图案层111和漏极图案层112，其中，数据线图案层104与源极图案层111和漏极图案层112通过同一道光刻工艺形成。
具体的，可通过物理气相沉积法在缓冲层106上沉积氧化硅，通过曝光、显影、蚀刻及剥离的光刻工艺在缓冲层106上形成覆盖栅极图案层109的第二绝缘层110，然后在第二绝缘层110通过曝光、显影、蚀刻及剥离的光刻工艺开设连通有源层107的源极过孔1101及漏极过孔1102，最后可通过物理气相沉积法或等离子体气相沉积法在第二绝缘层110上、源极过孔1101及漏极过孔1102中沉积金属材料，并通过曝光、显影、蚀刻及剥离的光刻工艺同时形成源极图案层111、漏极图案层112以及数据线图案层104。
本实施例中的扫描线图案层103在缓冲层106上通过第一过孔1061与金属图案层102电连接，以与金属图案层102形成一个并联结构，进而使得扫描线图案层103与金属图案层102共同形成的并联结构的电阻小于扫描线图案层103的电阻。
参阅图2，本发明提供的阵列基板第二实施例进一步包括第一导电层213，该第一导电层213与有源层207同层间隔设置且通过同一道光刻工艺形成，并通过第一过孔2061与金属图案层202电连接。
具体的，在如上述第一实施例中形成有源层207时，通过物理气相沉积法在缓冲层206上以及第一过孔2061中沉积IGZO，然后通过曝光、显影、蚀刻及剥离的光刻工艺在缓冲层206上形成两个IGZO图案，其中与遮光层205相对位置的即为有源层207，位于第一过孔2061处的即为第一导电层213，该第一导电层213即可通过第一过孔2061中的IGZO与金属图案层202电连接。
进一步的，本实施例中的扫描线图案层203设置于第一导电层213上，使得扫描线图案层203通过第一导电层213与金属图案层202电连接，以与第一导电层213和金属图案层202共同形成一个并联结构，该并联结构的电阻小于扫描线图案层203的电阻。
本实施例中的其他结构与上述第一实施例相同，在此不再赘述。
参阅图3，本发明提供的阵列基板第三实施例包括衬底基板301、金属图案层302、扫描线图案层303及数据线图案层304。
其中，金属图案层302设置于衬底基板301上，进一步的，衬底基板301上还设有遮光层305，遮光层305与金属图案层302同层间隔设置且通过同一道光刻工艺形成。
具体的，可通过物理气相沉积法或等离子体气相沉积法在衬底基板301上沉积金属材料层，然后通过曝光、显影、蚀刻及剥离的光刻工艺在衬底基板301上同时形成金属图案层302以及遮光层305。
可选的，金属材料层的金属材料为包括但不限于铝或钼的金属材料。
进一步的，遮光层305上设有依次层叠的有源层306、第一绝缘层307以及栅极图案层308，扫描线图案层303设置于衬底基板301上且与栅极图案层308通过同一道光刻工艺形成。
具体的，可通过物理气相沉积法在遮光层上沉积IGZO，然后通过曝光、显影、蚀刻及剥离的光刻工艺形成IGZO图案，即可形成有源层306；进而通过物理气相沉积法在有源层306上沉积氧化硅，然后通过曝光、显影、蚀刻及剥离的光刻工艺形成第一绝缘层307；在第一绝缘层307以及衬底基板301上沉积金属材料，然后通过曝光、显影、蚀刻及剥离的光刻工艺分别在第一绝缘层307和衬底基板301上形成栅极图案层308以及扫描线图案层303。
进一步的，本实施例的阵列基板还包括第二绝缘层309以及设置于第二绝缘层309上的源极图案层310和漏极图案层311，数据图案层304设置于第二绝缘层309上且与源极图案层310和漏极图案层311通过同一道光刻工艺形成，其中，第二绝缘层309上设有贯穿第二绝缘层309且连通金属图案层302的第二过孔3091，数据线图案层304通过该第二过孔3091与金属图案层302电连接。
具体的，可通过物理气相沉积法在衬底基板301上形成覆盖栅极图案层308的氮化硅，并通过曝光、显影、蚀刻及剥离的光刻工艺形成第二绝缘层309，然后通过曝光、显影、蚀刻及剥离的光刻工艺开设贯穿第二绝缘层309且与金属图案层302连通的第二过孔3091、与有源层306连通的源极过孔3092和漏极过孔3093，最后在第二绝缘层309上、第二过孔3091、源极过孔3092和漏极过孔3093中沉积金属，并通过曝光、显影、蚀刻及剥离的光刻工艺即可在第二绝缘层309上同时形成源极图案层310、漏极图案层311和数据线图案层304，该数据线图案层304即可通过第二过孔3091中的金属材料与金属图案层302电连接，以与金属图案层302形成一个并联结构，该并联结构的电阻小于数据线图案层304的电阻。
参阅图4，本发明提供的阵列基板第四实施例进一步包括缓冲层412，缓冲层412设置于衬底基板401上且覆盖金属图案层402。
其中，缓冲层412设有贯穿缓冲层412且与金属图案层402连通的第三过孔4121，进一步的，第二绝缘层409设置于缓冲层412上，且第二过孔4091与第三过孔4121连通，以使得数据线图案层404通过第二过孔4091与第三过孔4121与金属图案层402电连接。
具体的，在如上述第三实施例中形成数据线图案层404时，同时在第二过孔4091和第三过孔4121中沉积金属材料，即可在形成数据线图案层404时，通过第二过孔4091和第三过孔4121中的金属材料与金属图案层402电连接。
本实施例中的其他结构与上述第三实施例相同，在此不再赘述。
参阅图5，本发明提供的阵列基板第五实施例进一步包括第二导电层513，该第二导电层513与有源层506同层间隔设置且通过同一道光刻工艺形成，并位于第二过孔5091和第三过孔5121之间，以使得数据线图案层504通过第二导电层513与金属图案层502电连接。
具体的，在如上述第三实施例中形成有源层506时，在第三过孔5121中同时沉积IGZO，然后通过曝光、显影、蚀刻及剥离的光刻工艺即可同时形成有源层506和第二导电层513，该第二导电层513即可通过第三过孔5121中的IGZO与金属图案层502电连接，同理，在形成数据线图案层504时，数据线图案层504通过第二过孔5091与第二导电层513电连接，进而数据线图案层504通过第二导电层513与金属图案层502电连接。
本实施例中的数据线图案层504通过第二导电层513与金属图案层502电连接，以与第二导电层513与金属图案层502电连接共同形成一个并联结构，该并联结构的电阻小于数据线图案层504的电阻。
本实施例中的其他结构与上述第四实施例相同，在此不再赘述。
参阅图6，本发明提供的显示装置实施例包括背光模组100及上述任一实施例中的阵列基板200。
共同参阅图1和图7，本发明提供的阵列基板的制备方法实施例包括：
S11：在衬底基板101上沉积金属以形成间隔设置的金属图案层102与遮光层105；
S12：形成覆盖金属图案层102的缓冲层106并开设贯穿缓冲层106且连通金属图案层102的第一过孔1061；
S13：在缓冲层106上依次形成层叠设置的有源层107及第一绝缘层108；
S14：通过同一道光刻工艺分别在第一绝缘层108与缓冲层106上形成栅极图案层109和扫描线图案层103，扫描线图案层103通过第一过孔1061与金属图案层102电连接；
S15：在缓冲层106上形成覆盖栅极图案层109的第二绝缘层110；
S16：在第二绝缘层110上形成源极图案层111、漏极图案层112及数据线图案层104。
本实施例中各步骤的详细实施方法可参阅上述阵列基板第一实施例中的描述，在此不再赘述。
区别于现有技术的情况，本发明通过在基板上设置金属图案层，数据线图案层与金属图案层异层设置且与金属图案层电连接或扫描线图案层与金属图案层异层设置且与金属图案层电连接的方法，使得数据线图案层或扫描线图案层与金属图案层形成一个并联结构，由于该并联结构的电阻小于数据线图案层或扫描线图案层电阻，使得该并联结构作为数据线或扫描线使用时的电阻变小，提高显示效果。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (8)

1.一种阵列基板，其特征在于，所述阵列基板包括衬底基板、金属图案层、数据线图案层及扫描线图案层；
其中，所述金属图案层设置于所述衬底基板上，所述数据线图案层与所述金属图案层异层设置，所述扫描线图案层与所述金属图案层异层设置且与所述金属图案层电连接；
所述衬底基板上设有覆盖所述金属图案层的缓冲层，所述缓冲层上设有依次层叠的有源层、第一绝缘层及栅极图案层，所述扫描线图案层与所述栅极图案层通过同一道光刻工艺形成；
所述缓冲层设有贯穿所述缓冲层且连通所述金属图案层的第一过孔，所述扫描线图案层通过所述第一过孔与所述金属图案层电连接；
所述缓冲层上还设有与所述有源层间隔设置且通过同一道光刻工艺形成的第一导电层，所述第一导电层通过所述第一过孔与所述金属图案层电连接，所述扫描线图案层设置于所述第一导电层上。
2.根据权利要求1所述的阵列基板，其特征在于，所述衬底基板上设有遮光层，所述金属图案层与所述遮光层同层间隔设置且通过同一道光刻工艺形成。
3.一种阵列基板，其特征在于，所述阵列基板包括衬底基板、金属图案层、数据线图案层及扫描线图案层；
其中，所述金属图案层设置于所述衬底基板上，所述数据线图案层与所述金属图案层异层设置且与所述金属图案层电连接，所述扫描线图案层与所述金属图案层异层设置；
所述阵列基板进一步包括第二绝缘层以及设置于所述第二绝缘层上的源极图案层和漏极图案层，所述数据线图案层设置于所述第二绝缘层上且与所述源极图案层和漏极图案层通过同一道光刻工艺形成，所述第二绝缘层设有贯穿所述第二绝缘层且与所述金属图案层连通的第二过孔，所述数据线图案层通过所述第二过孔与所述金属图案层电连接。
4.根据权利要求3所述的阵列基板，其特征在于，所述衬底基板上设有遮光层，所述金属图案层与所述遮光层同层间隔设置且通过同一道光刻工艺形成。
5.根据权利要求3所述的阵列基板，其特征在于，所述衬底基板上还设有覆盖所述金属图案层的缓冲层，所述第二绝缘层设置于所述缓冲层上，所述缓冲层设有贯穿所述缓冲层且与所述金属图案层连通的第三过孔，所述第三过孔与所述第二过孔连通，以使得所述数据线图案层通过所述第三过孔与所述第二过孔与所述金属图案层电连接。
6.根据权利要求5所述的阵列基板，其特征在于，所述缓冲层上设有有源层及第二导电层，所述第二导电层与所述有源层间隔设置且通过同一道光刻工艺形成，所述第二导电层位于所述第二过孔和所述第三过孔之间，以使得所述数据线图案层通过所述第二导电层与所述金属图案层电连接。
7.一种显示装置，其特征在于，所述显示装置包括如权利要求1～6任一项所述的阵列基板。
8.一种阵列基板的制备方法，其特征在于，所述方法包括：
在衬底基板上沉积金属以形成间隔设置的金属图案层与遮光层；
形成覆盖所述金属图案层的缓冲层并开设贯穿所述缓冲层且连通所述金属图案层的第一过孔；
在所述缓冲层依次形成层叠设置的有源层及第一绝缘层；
通过同一道光刻工艺分别在所述第一绝缘层与所述缓冲层上形成栅极图案层和扫描线图案层，所述扫描线图案层通过所述第一过孔与所述金属图案层电连接；
在所述缓冲层上形成第二绝缘层；
在所述第二绝缘层上形成源极图案层、漏极图案层和数据线图案层；
所述缓冲层上还设有与所述有源层间隔设置且通过同一道光刻工艺形成的第一导电层，所述第一导电层通过所述第一过孔与所述金属图案层电连接，所述扫描线图案层设置于所述第一导电层上。
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