WO2022199081A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022199081A1
WO2022199081A1 PCT/CN2021/132197 CN2021132197W WO2022199081A1 WO 2022199081 A1 WO2022199081 A1 WO 2022199081A1 CN 2021132197 W CN2021132197 W CN 2021132197W WO 2022199081 A1 WO2022199081 A1 WO 2022199081A1
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WIPO (PCT)
Prior art keywords
base substrate
electrode plate
conductive
conductive pattern
display panel
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PCT/CN2021/132197
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English (en)
French (fr)
Inventor
黄勇潮
王庆贺
程磊磊
苏同上
刘军
王超
成军
闫梁臣
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2022199081A1 publication Critical patent/WO2022199081A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • Self-luminous display devices such as organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panels have the advantages of self-luminescence, lightness, low power consumption, good color reproduction, sensitive response and wide viewing angle, etc., and have been more and more widely used.
  • OLED Organic Light-Emitting Diode
  • display devices such as mobile phones, notebook computers and TVs, it has become the mainstream of the current market.
  • a display panel comprising: a base substrate; and a pixel driving circuit disposed on the base substrate, the pixel driving circuit comprising: a driving transistor and a capacitor; the driving transistor comprising: a gate and a an active layer, the active layer of the driving transistor includes an active part, a first conductive part and a second conductive part, the gate is farther from the base substrate than the active layer, the The active part includes an edge that is flush with the gate; the capacitor includes: a first electrode plate and a second electrode plate opposite to each other along the thickness direction of the base substrate, the first electrode plate and the The gate of the driving transistor is coupled, the second electrode plate is disposed on the side of the gate away from the base substrate, and the second electrode plate can shield light, and the active portion is aligned with the gate.
  • the orthographic projection of the flat edge on the base substrate is located within the orthographic projection of the second plate on the base substrate.
  • the active part of the driving transistor is located within the orthographic projection of the second electrode plate on the base substrate; or, an opening is provided on the second electrode plate, the The second electrode plate has an inner edge and an outer edge, the edge of the opening constitutes the inner edge of the second electrode plate, and the edge of the active part of the driving transistor that is flush with the gate is on the base substrate
  • the orthographic projection on the second pole plate is located between the orthographic projection of the outer edge of the second pole plate on the base substrate and the orthographic projection of the inner edge of the second pole plate on the base substrate.
  • the driving transistor further includes: a first conductive pattern; the first conductive portion of the driving transistor has a first contact, and the second conductive portion of the driving transistor has a second contact part; the first contact part is in contact with the first conductive pattern, and the second contact part is in contact with the second electrode plate.
  • the first conductive pattern and the second electrode plate are disposed in the same layer, and the first contact portion is farther from the active portion than the second contact portion.
  • the pixel driving circuit further includes: a first switch transistor; the first switch transistor includes an active layer, and the active layer of the first switch transistor includes an active part, a first conductive part, and a second conductive part; the first conductive part of the first switch transistor is used to receive a reset signal or provide a sensing signal, and the second conductive part of the first switch transistor is coupled to the second plate catch.
  • the pixel driving circuit further includes: a light-shielding metal layer disposed on the side of the active layer of the driving transistor close to the substrate; the active part of the driving transistor is on the substrate
  • the orthographic projection on the substrate is located within the orthographic projection of the light-shielding metal layer on the base substrate, and the light-shielding metal layer is coupled to the second electrode plate.
  • the pixel driving circuit when the pixel driving circuit further includes a first switching transistor, the pixel driving circuit further includes: a second conductive pattern; the second conductive portion of the first switching transistor has a second conductive pattern. Three contact parts, the third contact part is in contact with the second conductive pattern; the second electrode plate and the second conductive pattern are connected in an integrated structure, or the second electrode plate is on the substrate There is a gap between the orthographic projection on the substrate and the orthographic projection of the second conductive pattern on the base substrate, and the second conductive pattern and the second electrode plate are respectively coupled to the light-shielding metal layer .
  • the active layer of the first switching transistor and the active layer of the driving transistor are arranged in the same layer, and the second conductive pattern and the second electrode plate are arranged in the same layer;
  • the pixel driving The circuit further includes a first insulating layer disposed between the active layer of the first switching transistor and the second conductive pattern, and a second insulating layer disposed between the active layer of the first switching transistor and the light-shielding metal layer an insulating layer;
  • the first insulating layer is provided with a first via hole
  • the second insulating layer is provided with a second via hole, and the first via hole and the second via hole are located in the base substrate
  • the orthographic projections on the top overlap, the second conductive pattern is in contact with the third contact portion through the first via hole, and the light-shielding metal layer is coupled with the third contact portion through the second via hole.
  • the second conductive pattern faces the second electrode plate in both a first direction and a second direction, the first direction and the second direction being parallel to the substrate The plane on which the substrate is located, and two directions that are perpendicular to each other.
  • the first electrode plate is disposed in the same layer as the active layer of the driving transistor, and the orthographic projection of the first electrode plate on the base substrate is at the same level as the second electrode plate.
  • the orthographic projections on the base substrate overlap.
  • the pixel driving circuit further includes: a second switch transistor; the second switch transistor includes an active layer, and the active layer of the second switch transistor includes an active part, a first conductive part, and a second conductive part; the first conductive part of the second switch transistor is used for receiving a data signal, and the second conductive part of the second switch transistor is coupled to the gate of the driving transistor.
  • the method further includes: a power supply line disposed on the base substrate; and the first conductive portion of the driving transistor in the pixel driving circuit is coupled to the power supply line.
  • the driving transistor when the driving transistor further includes a first conductive pattern, the power line and the first conductive pattern are disposed in the same layer, and the power line is in contact with the first conductive pattern.
  • the display panel when the pixel driving circuit further includes a light-shielding metal layer, the display panel further includes: a third conductive pattern provided in the same layer as the light-shielding metal layer, the third conductive patterns are respectively is coupled to the first conductive portion of the driving transistor and the power supply line.
  • the method further includes: a sensing signal line disposed on the base substrate; and a first conductive portion of the first switch transistor is coupled to the sensing signal line.
  • the method further includes: a fourth conductive pattern provided in the same layer as the light-shielding metal layer, the fourth conductive pattern is respectively connected with the first conductive portion of the first switching transistor and the sensing The signal line is coupled.
  • the method further includes: a light emitting device disposed on the base substrate and coupled to the pixel driving circuit; the light emitted by the light emitting device is emitted from a side away from the base substrate.
  • a display device comprising: the above-mentioned display panel.
  • FIG. 1 is a top structural view of a display panel according to some embodiments
  • FIG. 2 is a top-view structural diagram of a pixel driving circuit according to some embodiments.
  • FIG. 3 is a cross-sectional structural view in the direction A-A' based on FIG. 2 according to some embodiments;
  • FIG. 5 is a top-view structural view of another pixel driving circuit provided by the related art.
  • Fig. 6 is a kind of cross-sectional structure diagram in A-A' direction based on Fig. 4 and Fig. 5 that the related art provides;
  • Fig. 7 is a kind of cross-sectional structure diagram in B-B' direction based on Fig. 4 and Fig. 5 that the related art provides;
  • Fig. 8 is a kind of cross-sectional structure diagram in the C-C' direction based on Fig. 4 and Fig. 5 that the related art provides;
  • FIG. 9 is a top structural view of another pixel driving circuit according to some embodiments.
  • Figure 10 is a cross-sectional structural view in the direction A-A' based on Figure 9 according to some embodiments;
  • FIG. 11 is a top structural view of yet another pixel driving circuit according to some embodiments.
  • FIG. 12 is a cross-sectional structural view in the direction B-B' based on FIG. 11 according to some embodiments;
  • 13 is an equivalent circuit diagram of a 3T1C pixel drive circuit according to some embodiments.
  • FIG. 14 is a block diagram of two capacitors in parallel, according to some embodiments.
  • FIG. 15 is a top structural view of a display panel according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C”, and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the "first electrode” is, for example, the source of the thin film transistor
  • the “second electrode” is, for example, the drain of the thin film transistor, and vice versa.
  • the same reference numerals may refer to both signal lines and signal terminals and the signals corresponding to the signal lines and signal terminals.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the display device may be an OLED (Organic Light-Emitting Diode) display device, a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) display device, a MicroLED (Micro Light Emitting Diodes, micro light-emitting diodes), miniLED (mini Light Emitting Diodes, mini light-emitting diodes) display devices and the like.
  • OLED Organic Light-Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode
  • MicroLED Micro Light Emitting Diodes, micro light-emitting diodes
  • miniLED mini Light Emitting Diodes, mini light-emitting diodes
  • the structure of the display device will be introduced by taking the display device as an OLED display device as an example.
  • the display device includes, for example, a display panel. As shown in FIG. 1 , the display panel has a display area A and a peripheral area S disposed around the display area A.
  • the display area A includes a plurality of sub-pixel areas P, and the peripheral area S is used for wiring, such as the gate driving circuit 100 .
  • the display panel includes: a base substrate 1 , a pixel driving circuit 10 disposed on the base substrate 1 and located in the sub-pixel region P, and a pixel driving circuit 10 coupled to the pixel driving circuit 10 .
  • the light emitting device 20 and the gate driving circuit 100 are connected to the pixel driving circuit 10 , and the light emitting device 20 emits light under the driving of the pixel driving circuit 10 .
  • the above-mentioned pixel driving circuit 10 can be, for example, a 2T1C type pixel driving circuit, a 3T1C type pixel driving circuit, or a 7T1C type pixel driving circuit, wherein T represents a thin-film transistor (TFT), and C Representing the storage capacitor, the 2T1C type represents the pixel driving circuit 10 including two TFTs and one storage capacitor Cst, and so on.
  • T represents a thin-film transistor (TFT)
  • the 2T1C type represents the pixel driving circuit 10 including two TFTs and one storage capacitor Cst, and so on.
  • the TFT especially the metal oxide semiconductor TFT, will degrade the characteristics of the TFT device under illumination conditions.
  • NBS namely NBIS (Negative gate bias illumination stress, negative gate bias illumination stress, negative gate bias illumination stress, negative gate bias illumination stress, negative gate bias illumination stress, negative gate bias illumination stress, negative gate bias illumination stress) stress
  • TFT device transfer characteristics will have a significant negative shift, which is manifested as a negative shift of the threshold voltage (V th ) under NBIS. Therefore, it is particularly important to improve the threshold voltage stability of TFTs under NBIS.
  • the pixel driving circuit 10 includes a driving transistor T1 and a capacitor Cst.
  • the driving transistor T1 includes a gate g and an active layer 11
  • the active layer 11 of the driving transistor T1 includes an active part 11 a , a first conductive part 11 b and a second conductive part 11 c
  • the gate g is farther away from the active layer 11
  • the active portion 11a includes an edge i that is flush with the gate g.
  • the driving transistor T1 is a top-gate transistor
  • the active portion 11a is the channel region (referring to the region where the active layer 11 and the gate g overlap)
  • the material of the active portion 11a can be a metal semiconductor material,
  • IGZO indium gallium zinc oxide, indium gallium zinc oxide
  • the first conductive portion 11b and the second conductive portion 11c can be made of materials after conducting IGZO treatment, and serve as the source region and the drain region of the driving transistor T1 ( As shown in FIG. 2, the source region and the drain region are regions located on both sides of the active portion 11a).
  • the capacitor Cst includes a first pole plate C1 and a second pole plate C2 that are oppositely disposed along the thickness direction of the base substrate 1 .
  • the first plate C1 is coupled to the gate g of the driving transistor T1
  • the second plate C2 is disposed on the side of the gate g away from the base substrate 1, and the second plate C2 can shield light
  • the active portion 11a is connected to the gate g.
  • the orthographic projection of the flush edge i of the pole g on the base substrate 1 is located within the orthographic projection of the second pole plate C2 on the base substrate 1 .
  • the orthographic projection of the edge i of the active portion 11a flush with the gate g on the base substrate 1 is located within the orthographic projection of the second electrode plate C2 on the base substrate 1, which means that the active portion 11a and the gate
  • the orthographic projection of the edge i that is flush with the electrode g on the base substrate 1 overlaps with the orthographic projection of the second electrode plate C2 on the base substrate 1, and the edge i of the active portion 11a that is flush with the gate g is on the substrate.
  • the edge of the active portion 11a may include two parts, the first part is the part that is flush with the edge of the gate g , the second part is the part j that is flush with the edge of the active layer 11 .
  • the portion where the edge of the active portion 11A is flush with the edge of the gate g is the edge i where the active portion 11a is flush with the edge of the gate g.
  • the edge i of the active portion 11a that is flush with the gate g may include an upper edge i1 and a lower edge i2.
  • the orthographic projection of the edge i of the active portion 11a flush with the gate g on the base substrate 1 is located within the orthographic projection of the second electrode plate C2 on the base substrate 1, which means that the upper edge i1 and
  • the orthographic projection of the lower edge i2 on the base substrate 1 is located within the orthographic projection of the second pole plate C2 on the base substrate 1 .
  • the light emitted by the light emitting device 20 is emitted from a side away from the base substrate 1 . That is, the display panel may be a top emission type display panel.
  • the orthographic projection of the edge i of the active portion 11a flush with the gate g on the base substrate 1 is located within the orthographic projection of the second electrode plate C2 on the base substrate 1, and there are two possibilities.
  • the orthographic projection of the active portion 11 a on the base substrate 1 is located within the orthographic projection of the second electrode plate C2 on the base substrate 1 . That is, the orthographic projection of the active portion 11a on the base substrate 1 overlaps with the orthographic projection of the second plate C2 on the base substrate 1, and all the edges (including the edge i and the edge j) of the active portion 11a and There is a gap between the edges of the second electrode plate C2.
  • the second situation is provided with opening K on the second pole plate C2, the second pole plate C2 has an inner edge and an outer edge, and the edge of the opening K constitutes the inner edge of the second pole plate C2 , the orthographic projection of the edge i of the active portion 11a flush with the gate g on the base substrate 1 is located in the orthographic projection of the outer edge of the second electrode plate C2 on the base substrate 1, and the inner portion of the second electrode plate C2 The edges are between orthographic projections on the base substrate 1 .
  • the orthographic projection of the edge i of the active portion 11a flush with the gate g on the base substrate 1 overlaps with the orthographic projection of the second electrode plate C2 on the base substrate 1, and the active portion 11a and the gate g
  • the orthographic projection of the flush edge i on the base substrate 1 and the orthographic projection of the outer edge of the second electrode plate C2 on the base substrate 1 and the flush edge i of the active portion 11a and the gate g is between There is a gap between the orthographic projection on the base substrate 1 and the orthographic projection of the inner edge of the second electrode plate C2 on the base substrate 1 .
  • the opening K may be closed, that is, as shown in FIG. 9 , the edge of the opening K constitutes the inner edge of the second pole plate C2, the inner edge of the second pole plate C2 and the second pole plate There is a gap between the outer edges of C2.
  • the opening K may also be a notch formed on the outer edge of the second electrode plate C2. The portion j) of the edge of 11a that is flush with the edge of the active layer 11 is not covered by the second electrode plate C2.
  • the light emitted from the light emitting device 20 is irradiated from the edge i of the active portion 11a flush with the gate g to
  • the active portion 11a is shielded, and the active portion 11a can be illuminated through the opening K under the condition of reducing light as much as possible, which facilitates the optical detection of TFT channel region defects in subsequent production lines.
  • the source and drain regions of the driving transistor T1 serve as the source and drain of the driving transistor T1, respectively.
  • the driving transistor T1 may further include: a first conductive pattern 12a.
  • the first conductive portion 11b of the driving transistor T1 has a first contact portion M
  • the second conductive portion 11c of the driving transistor T1 has a second contact portion L
  • the first contact portion M is in contact with the first conductive pattern 12a
  • the second contact portion L contact with the second plate C2. That is, the first conductive pattern 12a and a portion on the second electrode plate C2 serve as the source and drain of the driving transistor T1, respectively.
  • the second electrode plate C2 is arranged on the side of the grid g away from the base substrate 1, it can be known that an insulating layer is provided between the second electrode plate C2 and the second conductive portion 11c, therefore, the second electrode plate C2 is provided with an insulating layer.
  • the plate C2 and the second conductive portion 11c can be contacted by via holes provided in the insulating layer, and the first conductive pattern 12a can be arranged in the same layer as the second plate C2, or can be arranged in a different layer from the second plate C2.
  • the first conductive pattern 12a can also be in contact with the first conductive portion 11b through the via hole provided in the insulating layer, and the first conductive pattern 12a In the case of a different layer from the second electrode plate C2, for example, the first conductive pattern 12a may be in direct contact with the first conductive portion 11b, that is, there is no other layer between the first conductive pattern 12a and the first conductive portion 11b. .
  • the first conductive pattern 12a and the second electrode plate C2 are disposed in the same layer, and the first contact portion M is farther from the active portion 11a than the second contact portion L.
  • the first conductive pattern 12a and the second electrode plate C2 are disposed in the same layer, the first conductive pattern 12a and the first conductive portion 11b, as well as the second electrode plate C2 and the second conductive portion 11c are all disposed on the insulating
  • the vias in the layer are in contact with the first contact portion M and the second contact portion L respectively. It can be known that when the first contact portion M is farther from the active portion 11a than the second contact portion L, it is beneficial to the first contact portion M. There is a large gap between a conductive pattern 12a and the second electrode plate C2 to avoid short circuit between the first conductive pattern 12a and the second electrode plate C2.
  • the pixel driving circuit 10 further includes a first switch transistor T2 , the first switch transistor T2 includes an active layer 13 , and the active layer of the first switch transistor T2 13 includes an active part 13a, a first conductive part 13b and a second conductive part 13c.
  • the first conductive portion 13b of the first switching transistor T2 is used for receiving a reset signal or providing a sensing signal Sense, wherein the reset signal is used to reset the anode of the light emitting device, and the sensing signal is used to calculate the threshold voltage of the driving transistor T1.
  • the second conductive portion 13c of the first switching transistor T2 is coupled to the second electrode plate C2.
  • the above-mentioned pixel driving circuit 10 may be a 3T1C type pixel driving circuit, and the equivalent circuit diagram of the 3T1C type pixel driving circuit is shown in FIG. 13 .
  • the electrode plate C2 and the anode of the light emitting device 20 intersect at point S. Based on this, the parameters of the driving transistor T1 can be sensed through the sensing signal line Sense to perform threshold voltage compensation in an external manner.
  • the first conductive portion 13b and the second conductive portion 13c of the first switching transistor T2 can also serve as the source and drain of the first switching transistor T2, which are respectively connected with the sense
  • the test signal line Sense is coupled to the second plate C2.
  • the pixel driving circuit 10 further includes: a light shielding metal layer 14 disposed on the side of the active layer 11 a of the driving transistor T1 close to the base substrate 1 .
  • the orthographic projection of the active portion 11 a of the driving transistor T1 on the base substrate 1 is located within the orthographic projection of the light-shielding metal layer 14 on the base substrate 1 .
  • the light-shielding metal layer 14 is coupled to the second electrode plate C2.
  • the orthographic projection of the active portion 11a of the driving transistor T1 on the base substrate 1 is located within the orthographic projection of the light-shielding metal layer 14 on the base substrate 1, which means that the active portion 11a of the driving transistor T1 is on the base substrate 1.
  • the orthographic projection on 1 is completely within the orthographic projection of the light-shielding metal layer 13 on the base substrate 1, and the orthographic projection of the edge of the active portion 11a of the driving transistor T1 on the base substrate 1 is within the edge of the light-shielding metal layer 14. There are gaps between the orthographic projections on the base substrate 1 .
  • the light-shielding metal layer 14 by providing the light-shielding metal layer 14, light can be prevented from being irradiated on the active portion 11a from the side of the base substrate 1, thereby further improving the light stability of the TFT and avoiding the threshold voltage of the driving transistor under NBIS. drift.
  • the light-shielding metal layer 14 in the case where the first electrode plate C1 and the active layer 11a of the driving transistor T1 are arranged in the same layer, as shown in FIG.
  • the light-shielding metal layer 13 and the first electrode plate C1 can also be By forming another capacitor in parallel with the capacitor Cst, the capacitance of the storage capacitor of the capacitor Cst in the pixel driving circuit 10 can be increased, thereby further avoiding uneven display of the display panel.
  • the first switching transistor T2 further includes: a second conductive pattern 15 .
  • the second conductive portion 13 c of the first switching transistor T2 has a third contact portion V, and the third contact portion V is in contact with the second conductive pattern 15 .
  • the second electrode plate C2 is connected to the second conductive pattern 15 as an integral structure. At this time, the second conductive pattern 15 and/or the second electrode plate C2 can be coupled with the light-shielding metal layer 14 to realize the The second electrode plate C2 is coupled to the light-shielding metal layer 14 .
  • the second conductive portion 13 c of the first switching transistor T2 has a third contact portion V, and the third contact portion V is in contact with the second conductive pattern 15 .
  • the second electrode plate C2 is connected to the second conductive pattern 15 as an integral structure.
  • the second conductive pattern 15 and/or the second electrode plate C2 can be coupled with the light-s
  • the light-shielding metal layer 14 also functions as an auxiliary electrode, which can improve the conductive effect of the connection between the second electrode plate C2 and the second conductive portion 14c of the first switching transistor T1.
  • the active layer 13 of the first switching transistor T2 and the active layer 11 of the driving transistor T1 are disposed in the same layer, and the second conductive pattern 15 and the second electrode
  • the board C2 is disposed on the same layer, and the pixel driving circuit 10 further includes a first insulating layer 16 disposed between the active layer 13a of the first switching transistor T2 and the second conductive pattern 15, and an active layer disposed in the first switching transistor T2
  • the second insulating layer 17 between the layer 13 a and the light-shielding metal layer 14 .
  • a first via hole h1 is provided in the first insulating layer 16
  • a second via hole h2 is provided in the second insulating layer 17
  • the orthographic projections of the first via hole h1 and the second via hole h2 on the base substrate 1 overlap.
  • the second conductive pattern 15 is coupled to the third contact portion V through the first via hole h1
  • the light-shielding metal layer 14 is coupled to the third contact portion V through the second via hole h2 .
  • the first via hole h1 and the second via hole h2 occupy a certain space respectively, so as to realize the coupling between the second conductive portion 14c of the first switching transistor T2 and the second conductive pattern 15 and the light-shielding metal layer 14, respectively, the second conductive portion 14c is used as the overlap connection. layer, the second conductive portion 14c of the first switching transistor T2 can be respectively coupled to the light-shielding metal layer 14 and the second conductive pattern 15 through the via hole at the same position, thereby saving space.
  • the second conductive pattern 15 is arranged in a first direction (the direction shown by arrow a in FIG. 9 and FIG. 11 ) and a second direction (arrow in FIG. 9 and FIG. 11 )
  • the directions shown in b) are opposite to the second electrode plate C2, and the first direction and the second direction are two directions parallel to the plane where the base substrate 1 is located and perpendicular to each other.
  • FIG. 9 and FIG. 11 it is an example of the positional relationship between the second conductive pattern 15 and the second electrode plate C2.
  • the second conductive pattern 15 passes through the The two via holes h2 are coupled to the light-shielding metal layer 14 , and the second conductive pattern 15 is only directly opposite to the second electrode plate C2 in the first direction, which can increase the area of the second electrode plate C2 .
  • the area of the first electrode plate C1 can also be increased, thereby increasing the capacitance of the storage capacitor of the capacitor Cst.
  • the first electrode plate C1 and the active layer 11a are disposed in the same layer, and the orthographic projection of the first electrode plate C1 on the base substrate 1 is the same as that of the second electrode plate C2 The orthographic projections on the base substrate 1 overlap.
  • the pixel driving circuit further includes: a second switch transistor T3.
  • the second switching transistor T3 includes an active layer 18, and the active layer 18 of the second switching transistor T3 includes an active part 18a, a first conductive part 18b and a second conductive part 18c.
  • the first conductive portion 18b of the second switch transistor T3 is used for receiving data signals, and the second conductive portion 18c of the second switch transistor T3 is coupled to the gate g of the driving transistor T1.
  • first conductive portion 18b and the second conductive portion 18c of the second switching transistor T3 can also serve as the source and drain of the second switching transistor T3.
  • the second conductive portion 18c of the second switching transistor T3 and the gate g of the driving transistor T1 are connected to point G.
  • the display panel further includes: a power line ELVDD disposed on the base substrate.
  • the first conductive portion 11b of the driving transistor T1 in the pixel driving circuit is coupled to the power line ELVDD.
  • the ELVDD signal is written to the driving transistor T1 through the power supply line ELVDD.
  • the driving transistor T1 when the driving transistor T1 further includes the first conductive pattern 12a, the power supply line ELVDD and the first conductive pattern 12a may be disposed in the same layer, and the power supply line ELVDD and the first conductive pattern 12a may be disposed in the same layer.
  • the pattern 12a is in contact.
  • the display panel when the pixel driving circuit 10 further includes a light-shielding metal layer 14 , the display panel further includes: a third conductive pattern 19 disposed on the same layer as the light-shielding metal layer 14 .
  • the third conductive patterns 19 are respectively coupled to the first conductive portion 11b of the driving transistor T1 and the power supply line ELVDD.
  • the third conductive pattern 19 can be used as an auxiliary electrode, which is beneficial to improve the conductive effect of the connection between the first conductive portion 11b of the driving transistor T1 and the power line ELVDD.
  • each power supply line ELVDD is arranged along the column direction of the sub-pixel region P, and at least one column of pixel driving circuits 10 is connected to one power supply line ELVDD.
  • the display panel may further include: a sensing signal line Sense disposed on the base substrate.
  • the first conductive portion 13b of the first switching transistor T2 is coupled to the sensing signal line Sense.
  • the sensing signal line Sense provides a reset signal to the node S to reset the anode of the driving element 2.
  • the signal of the node S is transmitted to the signal of the sensing signal line Sense through the first switching transistor T2 It is the sensing signal Sense, and the sensing signal is used to calculate the threshold voltage of the driving transistor T1.
  • the sensing signal line Sense may be parallel to the power line ELVDD and disposed in the same layer as the power line ELVDD.
  • the display panel further includes: a fourth conductive pattern 30 provided in the same layer as the light-shielding metal layer 14 , and the fourth conductive pattern 30 is respectively connected with the first conductive portion 13 b of the first switching transistor T2 The part is coupled to the sensing signal line Sense.
  • the fourth conductive pattern 30 can be used as an auxiliary electrode, which is beneficial to improve the conductive effect of the connection between the first conductive portion 13b of the first switching transistor T2 and the sensing signal line Sense.
  • the display panel may further include: data lines Data disposed on the base substrate 1 .
  • the first conductive portion 18b of the second switch transistor T3 is coupled to the data line Data.
  • a data signal is written to the second switching transistor T3 through the data line Data.
  • the data line Data, the sensing signal line Sense and the power line ELVDD may be disposed on the same layer as the second plate C2.
  • the materials of the data line Data, the sensing signal line Sense, the power line ELVDD and the second plate C2 can be selected from copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), and chromium (Cr) and tungsten (W) metal elements and metal alloys composed of these metal elements.
  • the first gate signal terminal G1 is configured to receive the first gate signal G1
  • the second gate signal terminal G2 is configured to receive the second gate signal G2
  • the data line Data is configured to receive a data signal Data
  • the data signal Data includes, for example, a detection data signal Data 1 and a display data signal Data 2
  • the power supply line ELVDD is configured to receive a power supply voltage signal ELVDD
  • the range of the power supply voltage signal ELVDD is, for example, -5V ⁇ 5V
  • the power supply voltage signal terminal ELVSS is configured to receive the power supply voltage signal ELVSS, for example, the power supply voltage signal ELVSS is a fixed voltage signal, such as a voltage signal less than or equal to 0V
  • the sensing signal line Sense is configured to provide a reset signal or obtain The sensing signal Sense, wherein the reset signal is used to reset the anode of the light emitting device 20, and the sensing signal is used to calculate the threshold voltage of the driving transistor T1.
  • the working process of the pixel driving circuit is, for example: under the control of the first gate signal G11 provided by the first gate signal terminal G1 , the second The switch transistor T3 is turned on, and the detection data signal Data 1 is transmitted to the node G through the data line Data; under the control of the second gate signal G2 1 provided by the second gate signal terminal G2, the first switch transistor T2 is turned on, and the node S is turned on.
  • the signal is transmitted to the sensing signal line Sense through the first switching transistor T2; when the detection data signal Data 1 and the power supply voltage signal ELVDD make the node G control the second switching transistor T3 to turn off, the sensing signal on the sensing signal line Sense is measured.
  • the magnitude of the signal Sense can calculate the threshold voltage Vth of the driving transistor T1 according to the difference between the detection data signal Data 1 and the sensing signal Sense.
  • the sensing signal Sense is measured by controlling the sensing transistor, thereby calculating the threshold voltage of the driving transistor, and then compensating the threshold voltage into the display data signal Data 2 after calculating the threshold voltage of the driving transistor.
  • the external compensation to the pixel drive circuit is completed. Referring to FIG. 15 , when performing external compensation, the pixel driving circuit needs to receive the first gate signal G1 1 and the second gate signal G2 1 to turn on the first switching transistor T2 and the second switching transistor T3.
  • the sensing signal terminal Sense is in a floating state, which is equivalent to a capacitor; after the sensing data signal Data 1 controls the driving transistor T1 to turn on, the power supply voltage signal ELVDD will be transmitted to the node S, and the node S will be charged until the potential of the node S does not change any more.
  • the difference between the potential of the node G and the potential of the node S is equal to the threshold voltage of the driving transistor T1, and the first switching transistor T2 is also in an on state, the signal of the node S is transmitted to the sensing signal terminal Sense through the first switching transistor T2.
  • the signal is the sensing signal Sense, and the magnitude of the sensing signal Sense is equal to the potential of the node S, so the threshold voltage of the driving transistor T1 can be calculated by calculating the difference between the sensing data signal Data 1 and the sensing signal Sense.
  • the working process of the pixel driving circuit includes, for example, a reset phase, a data writing phase, and a light-emitting phase.
  • the first switching transistor T2 is turned on, and the reset signal provided by the sensing signal terminal Sense is transmitted to the node S, so as to control the light emission
  • the anode of device 20 is reset.
  • the second switching transistor T3 is turned on, and the display data signal Data2 provided by the data line Data is transmitted to the node G, And the storage capacitor Cst is charged.
  • the driving transistor T3 under the control of node G, the driving transistor T3 is turned on, and the storage capacitor Cst begins to discharge to the node G, so that the potential of the node G is maintained for a period of time, thereby ensuring the turning-on time of the driving transistor T3.
  • a driving signal is output to the light-emitting device 20.
  • the driving signal is, for example, a driving current. Under the control of the driving signal, the light-emitting device 20 Start to shine.
  • the gate signals received by the first gate signal terminal G1 and the second gate signal terminal G2 are both provided by the gate driving circuit.

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Abstract

一种显示面板，包括：衬底基板；以及设置于所述衬底基板上的像素驱动电路，所述像素驱动电路包括：驱动晶体管和电容器；所述驱动晶体管包括：栅极和有源层，所述驱动晶体管的所述有源层包括有源部、第一导电部和第二导电部，所述栅极相比于所述有源层远离所述衬底基板，所述有源部包括与所述栅极齐平的边沿；所述电容器包括：沿所述衬底基板的厚度方向，相对设置的第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极耦接，所述第二极板设置于所述栅极远离所述衬底基板的一侧，且所述第二极板能够遮光，所述有源部与栅极齐平的边沿在所述衬底基板上的正投影位于所述第二极板在所述衬底基板上的正投影以内。

Description

显示面板和显示装置
本申请要求于2021年03月23日提交的、申请号为202110308898.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板和显示装置。
背景技术
自发光显示装置例如有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板具有自发光、轻薄、功耗低、色彩还原度好、反应灵敏以及广视角等有点，已经被越来越广泛的应用在手机、笔记本电脑以及电视等显示设备中，成为目前市场的主流。
发明内容
一方面，提供一种显示面板，包括：衬底基板；以及设置于所述衬底基板上的像素驱动电路，所述像素驱动电路包括：驱动晶体管和电容器；所述驱动晶体管包括：栅极和有源层，所述驱动晶体管的所述有源层包括有源部、第一导电部和第二导电部，所述栅极相比于所述有源层远离所述衬底基板，所述有源部包括与所述栅极齐平的边沿；所述电容器包括：沿所述衬底基板的厚度方向，相对设置的第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极耦接，所述第二极板设置于所述栅极远离所述衬底基板的一侧，且所述第二极板能够遮光，所述有源部与栅极齐平的边沿在所述衬底基板上的正投影位于所述第二极板在所述衬底基板上的正投影以内。
在一些实施例中，所述驱动晶体管的所述有源部位于所述第二极板在所述衬底基板上的正投影以内；或者，所述第二极板上设置有开口，所述第二极板具有内边沿和外边沿，所述开口的边沿构成所述第二极板的内边沿，所述驱动晶体管的所述有源部与栅极齐平的边沿在所述衬底基板上的正投影位于所述第二极板的外边沿在所述衬底基板上的正投影，和所述第二极板的内边沿在所述衬底基板上的正投影之间。
在一些实施例中，所述驱动晶体管还包括：第一导电图案；所述驱动晶体管的所述第一导电部具有第一接触部，所述驱动晶体管的所述第二导电部具有第二接触部；所述第一接触部与所述第一导电图案接触，所述第二接触部与所述第二极板接触。
在一些实施例中，所述第一导电图案和所述第二极板同层设置，且所述第一接触部相比于所述第二接触部远离所述有源部。
在一些实施例中，所述像素驱动电路还包括：第一开关晶体管；所述第一开关晶体管包括有源层，所述第一开关晶体管的有源层包括有源部、第一导电部和第二导电部；所述第一开关晶体管的所述第一导电部用于接收复位信号或提供感测信号，所述第一开关晶体管的所述第二导电部与所述第二极板耦接。
在一些实施例中，所述像素驱动电路还包括：设置于所述驱动晶体管的有源层靠近所述衬底基板一侧的遮光金属层；所述驱动晶体管的有源部在所述衬底基板上的正投影位于所述遮光金属层在所述衬底基板上的正投影以内，且所述遮光金属层与所述第二极板耦接。
在一些实施例中，在所述像素驱动电路还包括第一开关晶体管的情况下，所述像素驱动电路还包括：第二导电图案；所述第一开关晶体管的所述第二导电部具有第三接触部，所述第三接触部与所述第二导电图案接触；所述第二极板与所述第二导电图案连接为一体结构，或者，所述第二极板在所述衬底基板上的正投影和所述第二导电图案在所述衬底基板上的正投影之间具有间隙，且所述第二导电图案和所述第二极板分别与所述遮光金属层耦接。
在一些实施例中，所述第一开关晶体管的有源层和所述驱动晶体管的有源层同层设置，所述第二导电图案和所述第二极板同层设置；所述像素驱动电路还包括设置于所述第一开关晶体管的有源层和所述第二导电图案之间的第一绝缘层，以及设置于第一开关晶体管的有源层和遮光金属层之间的第二绝缘层；所述第一绝缘层中设置有第一过孔，所述第二绝缘层中设置有第二过孔，所述第一过孔和所述第二过孔在所述衬底基板上的正投影重叠，所述第二导电图案通过所述第一过孔与所述第三接触部接触，所述遮光金属层通过所述第二过孔与所述第三接触部耦接。
在一些实施例中，所述第二导电图案在第一方向和第二方向上均与所述第二极板正对，所述第一方向和所述第二方向是平行于所述衬底基板所在的平面，且相互垂直的两个方向。
在一些实施例中，所述第一极板与所述驱动晶体管的有源层同层设置，且所述第一极板在所述衬底基板上的正投影与所述第二极板在所述衬底基板上的正投影重叠。
在一些实施例中，所述像素驱动电路还包括：第二开关晶体管；所述第二开关晶体管包括有源层，所述第二开关晶体管的有源层包括有源部、第一导电部和第二导电部；所述第二开关晶体管的第一导电部用于接收数据信号，所述第二开关晶体管的第二导电部与所述驱动晶体管的栅极耦接。
在一些实施例中，还包括：设置于衬底基板上的电源线；所述像素驱动电路中所述驱动晶体管的第一导电部与所述电源线耦接。
在一些实施例中，在所述驱动晶体管还包括第一导电图案的情况下，所述电源线与所述第一导电图案同层设置，且所述电源线与所述第一导电图案接触。
在一些实施例中，在所述像素驱动电路还包括遮光金属层的情况下，所述显示面板还包括：与所述遮光金属层同层设置的第三导电图案，所述第三导电图案分别与所述驱动晶体管的第一导电部和所述电源线耦接。
在一些实施例中，还包括：设置于所述衬底基板上的感测信号线；所述第一开关晶体管的第一导电部与所述感测信号线耦接。
在一些实施例中，还包括：与所述遮光金属层同层设置的第四导电图案，所述第四导电图案分别与所述第一开关晶体管的所述第一导电部和所述感测信号线耦接。
在一些实施例中，还包括：设置于所述衬底基板上，且与所述像素驱动电路耦接的发光器件；所述发光器件发出的光自远离所述衬底基板的一侧出射。
另一方面，提供一种显示装置，包括：如上所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示面板的俯视结构图；
图2为根据一些实施例的一种像素驱动电路的俯视结构图；
图3为根据一些实施例的基于图2在A-A’方向的剖视结构图；
图4为相关技术提供的一种像素驱动电路的俯视结构图；
图5为相关技术提供的另一种像素驱动电路的俯视结构图；
图6为相关技术提供的一种基于图4和图5在A-A’方向的剖视结构图；
图7为相关技术提供的一种基于图4和图5在B-B’方向的剖视结构图；
图8为相关技术提供的一种基于图4和图5在C-C’方向的剖视结构图；
图9为根据一些实施例的另一种像素驱动电路的俯视结构图；
图10为根据一些实施例的基于图9在A-A’方向的剖视结构图；
图11为根据一些实施例的又一种像素驱动电路的俯视结构图；
图12为根据一些实施例的基于图11在B-B’方向的剖视结构图；
图13为根据一些实施例的3T1C型像素驱动电路的等效电路图；
图14为根据一些实施例的两个电容器并联的结构图；
图15为根据一些实施例的一种显示面板的俯视结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性命名不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个 所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“第一电极”例如为薄膜晶体管的源极，“第二电极”例如为薄膜晶体管的漏极，反之亦然。
如本文所使用的那样，相同的附图标记既可以信号线和信号端也可以表示与信号线和信号端所对应的信号。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供了一种显示装置，显示装置例如可以为OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示装置、MicroLED(Micro Light Emitting Diodes，微发光二极管)、miniLED(mini Light Emitting Diodes，迷你发光二极管)显示装置等中的一种。
下面以该显示装置为OLED显示装置为例，对该显示装置的结构进行介绍。
显示装置例如包括显示面板，如图1所示，显示面板具有显示区A和设置于显示区A周边的周边区S。显示区A包括多个亚像素区P，周边区S用于布线，如栅极驱动电路100。
在一些实施例中，继续参见图1，显示面板包括：衬底基板1，以及设置于衬底基板1上，且位于亚像素区P的像素驱动电路10，和与像素驱动电路10耦接的发光器件20，栅极驱动电路100与像素驱动电路10连接，发光器件20在像素驱动电路10的驱动下发光。
上述像素驱动电路10例如可以为2T1C型的像素驱动电路，也可以为3T1C型的像素驱动电路，还可以为7T1C型的像素驱动电路，其中T代表薄 膜晶体管(Thin-film transistor，TFT)，C代表存储电容，2T1C型即表示包括2个TFT和1个存储电容Cst的像素驱动电路10，依次类推。
无论上述哪种像素驱动电路10，TFT，尤其是金属氧化物半导体TFT在光照条件下TFT器件特性将发生退化，此外，在光照时NBS下即NBIS(Negative gate bias illumination stress，负栅偏压光照应力)TFT器件转移特性将发生明显的负向漂移，具体表现为在NBIS下阈值电压(V th)负漂。因此，提高TFT在NBIS下的阈值电压稳定性显得尤为重要。
在一些实施例中，如图2所示，像素驱动电路10包括驱动晶体管T1和电容器Cst。驱动晶体管T1包括栅极g和有源层11，驱动晶体管T1的有源层11包括有源部11a、第一导电部11b和第二导电部11c，栅极g相比于有源层11远离衬底基板1，有源部11a包括与栅极g齐平的边沿i。也即，驱动晶体管T1为顶栅型晶体管，有源部11a即为沟道区(是指有源层11与栅极g交叠的区域)，有源部11a的材料可以为金属半导体材料，如IGZO(indium gallium zinc oxide，氧化铟镓锌)，第一导电部11b和第二导电部11c可以为对IGZO导体化处理后的材料，分别作为驱动晶体管T1的源极区和漏极区(如图2所示，源极区和漏极区是位于有源部11a两侧的区域)。
电容器Cst包括：沿衬底基板1的厚度方向，相对设置的第一极板C1和第二极板C2。第一极板C1与驱动晶体管T1的栅极g耦接，第二极板C2设置于栅极g远离衬底基板1的一侧，且第二极板C2能够遮光，有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影位于第二极板C2在衬底基板1上的正投影以内。
其中，有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影位于第二极板C2在衬底基板1上的正投影以内，是指，有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影与第二极板C2在衬底基板1上的正投影重叠，且有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影和第二极板C2的边沿在衬底基板1上的正投影之间具有间隙。
由有源部11a是有源层11上与栅极g具有交叠区域的部分，可以得知，有源部11a的边沿可以包括两部分，第一部分是与栅极g的边沿齐平的部分，第二部分是与有源层11的边沿齐平的部分j。
其中，有源部11A的边沿与栅极g的边沿齐平的部分即为有源部11a与栅极g的边沿齐平的边沿i。如图2所示，有源部11a与栅极g齐平的边沿i可以包括上边沿i1和下边沿i2。这样一来，有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影位于第二极板C2在衬底基板1上的正投影以内， 是指，上边沿i1和下边沿i2在衬底基板1上的正投影位于第二极板C2在衬底基板1上的正投影以内。
这样，在发光器件20在像素驱动电路10的驱动下发光时，由于第二极板C2能够遮光，且有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影位于第二极板C2在衬底基板1上的正投影以内，因此，能够防止发光器件20发出的光从有源部11a与栅极g齐平的边沿i(如图2所示的上边沿i1和下边沿i2)照射到有源部11a上，与相关技术中，如图4和图5所示，有源部11a与栅极g齐平的部分边沿(如图4中的下边沿i2)在衬底基板1上的正投影位于第二极板C2在衬底基板1上的正投影以内相比，能够减少光照干扰，从而能够提高驱动晶体管T1在NBIS下的阈值电压稳定性。
基于此，在一些实施例中，发光器件20发出的光自远离衬底基板1的一侧出射。也即，该显示面板可以为顶发射型显示面板。
在一些实施例中，有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影位于第二极板C2在衬底基板1上的正投影以内，具有两种可能的情况，第一种情况，如图2和图3所示，有源部11a在衬底基板1上的正投影位于第二极板C2在衬底基板1上的正投影以内。也即，有源部11a在衬底基板1上的正投影与第二极板C2在衬底基板1上的正投影重叠，且有源部11a的所有边沿(包括边沿i和边沿j)与第二极板C2的边沿之间具有间隙。第二种情况，如图9和图11所示，第二极板C2上设置有开口K，第二极板C2具有内边沿和外边沿，开口K的边沿构成第二极板C2的内边沿，有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影位于第二极板C2的外边沿在衬底基板1上的正投影，和第二极板C2的内边沿在衬底基板1上的正投影之间。也即有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影与第二极板C2在衬底基板1上的正投影重叠，且有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影与第二极板C2的外边沿在衬底基板1上的正投影之间，以及有源部11a与栅极g齐平的边沿i在衬底基板1上的正投影与第二极板C2的内边沿在衬底基板1上的正投影之间均具有间隙。
这里，在一些实施例中，开口K可以是封闭的，也即如图9所示，开口K的边沿构成第二极板C2的内边沿，第二极板C2的内边沿和第二极板C2的外边沿之间具有间隙。在另一些实施例中，如图11所示，开口K也可以是形成在第二极板C2的外边沿上的缺口，这时，有源部11a的部分边沿(如可以是上述有源部11a的边沿中与有源层11的边沿齐平的部分j)未被第二极板C2遮盖。
这里，与上述第一种情况相比，在第二种情况下，继续参见图9和图11，通过对发光器件20发出的光从有源部11a与栅极g齐平的边沿i照射到有源部11a进行遮挡，能够在尽可能减少光照的情况下，通过开口K对有源部11a进行光照，为后续产线光学检测TFT沟道区不良提供便利。
在一些实施例中，驱动晶体管T1的源极区和漏极区分别作为驱动晶体管T1的源极和漏极。
在另一些实施例中，如图2和图3所示，驱动晶体管T1还可以包括：第一导电图案12a。驱动晶体管T1的第一导电部11b具有第一接触部M，驱动晶体管T1的第二导电部11c具有第二接触部L，第一接触部M与第一导电图案12a接触，第二接触部L与第二极板C2接触。也即，第一导电图案12a和第二极板C2上的一部分分别作为驱动晶体管T1的源极和漏极。
其中，根据上述第二极板C2设置于栅极g远离衬底基板1的一侧，可以得知，第二极板C2和第二导电部11c之间设置有绝缘层，因此，第二极板C2与第二导电部11c之间可以通过设置在绝缘层中的过孔接触，而第一导电图案12a可以与第二极板C2同层设置，也可以与第二极板C2不同层设置，在第一导电图案12a与第二极板C2同层设置的情况下，第一导电图案12a同样可以通过设置在绝缘层中的过孔与第一导电部11b接触，在第一导电图案12a与第二极板C2不同层的情况下，示例的，第一导电图案12a可以与第一导电部11b直接接触，也即，第一导电图案12a和第一导电部11b之间不存在其他层。
在一些实施例中，如图2和图3所示，第一导电图案12a与第二极板C2同层设置，且第一接触部M相比于第二接触部L远离有源部11a。
根据上述在第一导电图案12a与第二极板C2同层设置的情况下，第一导电图案12a和第一导电部11b，以及第二极板C2和第二导电部11c均通过设置于绝缘层中的过孔分别与第一接触部M和第二接触部L接触，可以得知，在第一接触部M相比于第二接触部L远离有源部11a的情况下，有利于第一导电图案12a和第二极板C2之间具有较大的间隙，避免第一导电图案12a和第二极板C2之间发生短路。
在一些实施例中，如图2、图9和图11所示，像素驱动电路10还包括第一开关晶体管T2，第一开关晶体管T2包括有源层13，第一开关晶体管T2的有源层13包括有源部13a、第一导电部13b和第二导电部13c。第一开关晶体管T2的第一导电部13b用于接收复位信号或提供感测信号Sense，其中，复位信号用于对发光器件的阳极进行复位，感测信号用于计算驱动晶体管T1 的阈值电压。第一开关晶体管T2的第二导电部13c与第二极板C2耦接。
也即，上述像素驱动电路10可以为3T1C型的像素驱动电路，3T1C型的像素驱动电路的等效电路图如图13所示，此时，第一开关晶体管T2的第一导电部13c、第二极板C2和发光器件20的阳极相交于S点，基于此，可通过感测信号线Sense感测驱动晶体管T1的参数，以通过外部方式进行阈值电压的补偿。
在这些实施例中，与上述驱动晶体管T1相类似地，第一开关晶体管T2的第一导电部13b和第二导电部13c也可以作为第一开关晶体管T2的源极和漏极，分别与感测信号线Sense和第二极板C2耦接。
在一些实施例中，如图2、图9和图11所示，像素驱动电路10还包括：设置于驱动晶体管T1的有源层11a靠近衬底基板1一侧的遮光金属层14。驱动晶体管T1的有源部11a在衬底基板1上的正投影位于遮光金属层14在衬底基板1上的正投影以内。遮光金属层14与第二极板C2耦接。
其中，驱动晶体管T1的有源部11a在衬底基板1上的正投影位于遮光金属层14在衬底基板1上的正投影以内，是指，驱动晶体管T1的有源部11a在衬底基板1上的正投影完全位于遮光金属层13在衬底基板1上的正投影以内，且驱动晶体管T1的有源部11a的边沿在衬底基板1上的正投影与遮光金属层14的边沿在衬底基板1上的正投影之间具有间隙。
在这些实施例中，通过设置遮光金属层14，能够避免光线从衬底基板1一侧照射到有源部11a上，从而能够进一步提高TFT的光照稳定性，避免驱动晶体管在NBIS下发生阈值电压漂移。同时，通过设置遮光金属层14，在第一极板C1与驱动晶体管T1的有源层11a同层设置的情况下，如图14所示，还能够使遮光金属层13和第一极板C1构成与电容器Cst并联的另一电容器，从而可以增大像素驱动电路10中电容器Cst的存储电容的电容量，进一步避免显示面板画面显示不均。
在一些实施例中，如图9、图10、图11和图12所示，第一开关晶体管T2还包括：第二导电图案15。第一开关晶体管T2的第二导电部13c具有第三接触部V，第三接触部V与第二导电图案15接触。如图11所示，第二极板C2与第二导电图案15连接为一体结构，这时，可以通过第二导电图案15和/或第二极板C2与遮光金属层14耦接，从而实现第二极板C2与遮光金属层14耦接。或者，如图9所示，第二极板C2在衬底基板1上的正投影和第二导电图案15在衬底基板1上的正投影之间具有间隙，且第二导电图案15 和第二极板C2分别与遮光金属层14耦接，从而实现第一开关晶体管T2的第二导电部14c通过第二导电图案15和遮光金属层14与第二极板C2耦接。
在这些实施例中，遮光金属层14还起到辅助电极的作用，可以提高第二极板C2和第一开关晶体管T1的第二导电部14c连接的导电效果。
在一些实施例中，如图9、图11和图12所示，第一开关晶体管T2的有源层13和驱动晶体管T1的有源层11同层设置，第二导电图案15与第二极板C2同层设置，像素驱动电路10还包括设置于第一开关晶体管T2的有源层13a和第二导电图案15之间的第一绝缘层16，以及设置于第一开关晶体管T2的有源层13a和遮光金属层14之间的第二绝缘层17。第一绝缘层16中设置有第一过孔h1，第二绝缘层17中设置有第二过孔h2，第一过孔h1和第二过孔h2在衬底基板1上的正投影重叠。第二导电图案15通过第一过孔h1与第三接触部V耦接，遮光金属层14通过第二过孔h2与第三接触部V耦接。
在这些实施例中，通过使第一过孔h1和第二过孔h2在衬底基板1上的正投影重叠，与相关技术中，如图4和图5所示，第一过孔h1和第二过孔h2分别占用一定的空间，以实现第一开关晶体管T2的第二导电部14c分别与第二导电图案15和遮光金属层14耦接相比，采用第二导电部14c作为搭接层，通过同一位置处的过孔即可将第一开关晶体管T2的第二导电部14c分别与遮光金属层14和第二导电图案15耦接，从而能够节省空间。
在一些实施例中，如9和图11所示，第二导电图案15在第一方向(如图9和图11中箭头a所示方向)和第二方向(如图9和图11中箭头b所示方向)上均与第二极板C2正对，第一方向和第二方向是平行于衬底基板1所在的平面，且相互垂直的两个方向。
如图9和图11所示，为第二导电图案15与第二极板C2的位置关系的一种示例，与相关技术中，如图4和图5所示，第二导电图案15通过第二过孔h2与遮光金属层14耦接，第二导电图案15仅在第一方向上与第二极板C2正对相比，可以增大第二极板C2的面积。同时，在第一极板C1与有源层11同层设置的情况下，还能够增大第一极板C1的面积，从而能够增大电容器Cst的存储电容的电容量。
在一些实施例中，如图9和图11所示，第一极板C1与有源层11a同层设置，且第一极板C1在衬底基板1上的正投影与第二极板C2在衬底基板1上的正投影重叠。
在这些实施例中，仍然以图9和图11为例，在第二导电图案15在第二方向上与第二极板C2正对的情况下，由于第一极板C1在衬底基板1上的正 投影与第二极板C2在衬底基板1上的正投影重叠，因此，与相关技术中如图4所示相比，能够进一步增大电容器Cst的存储电容的电容量。
在一些实施例中，如图11所示，像素驱动电路还包括：第二开关晶体管T3。第二开关晶体管T3包括有源层18，第二开关晶体管T3的有源层18包括有源部18a、第一导电部18b和第二导电部18c。第二开关晶体管T3的第一导电部18b用于接收数据信号，第二开关晶体管T3的第二导电部18c与驱动晶体管T1的栅极g耦接。
在这些实施例中，第二开关晶体管T3的第一导电部18b和第二导电部18c同样可以作为第二开关晶体管T3的源极和漏极。
参考图13所示的3T1C的等效电路图，第二开关晶体管T3的第二导电部18c与驱动晶体管T1的栅极g连接于G点。
在一些实施例中，如图15所示，显示面板还包括：设置于衬底基板上的电源线ELVDD。像素驱动电路中驱动晶体管T1的第一导电部11b与电源线ELVDD耦接。通过电源线ELVDD向驱动晶体管T1写入ELVDD信号。
在一些实施例中，如图15所示，在驱动晶体管T1还包括第一导电图案12a的情况下，电源线ELVDD可以与第一导电图案12a同层设置，且电源线线ELVDD与第一导电图案12a接触。
在一些实施例中，如图15所示，在像素驱动电路10还包括遮光金属层14的情况下，显示面板还包括：与遮光金属层14同层设置的第三导电图案19。第三导电图案19分别与驱动晶体管T1的第一导电部11b和电源线ELVDD耦接。第三导电图案19可以作为辅助电极，有利于提高驱动晶体管T1的第一导电部11b和电源线ELVDD连接的导电效果。
在此，需要说明的是，在显示面板中，如图1所示，多个亚像素区P可以呈阵列形式排布。且电源线ELVDD可以为多条，每条电源线ELVDD沿亚像素区P的列方向排列，至少一列像素驱动电路10与一条电源线ELVDD连接。
在一些实施例中，如图15所示，显示面板还可以包括：设置于衬底基板上的感测信号线Sense。第一开关晶体管T2的第一导电部13b与感测信号线Sense耦接。在复位阶段，感测信号线Sense提供复位信号至节点S，以对驱动件2的阳极进行复位，在感测阶段，节点S的信号通过第一开关晶体管T2传输至感测信号线Sense的信号即为感测信号Sense，感测信号用于计算驱动晶体管T1的阈值电压。
在一些实施例中，感测信号线Sense可以与电源线ELVDD平行，且与电 源线ELVDD同层设置。
在一些实施例中，如图15所示，显示面板还包括：与遮光金属层14同层设置的第四导电图案30，第四导电图案30分别与第一开关晶体管T2的第一导电部13b部和感测信号线Sense耦接。第四导电图案30可以作为辅助电极，有利于提高第一开关晶体管T2的第一导电部13b部和感测信号线Sense连接的导电效果。
在一些实施例中，如图15所示，显示面板还可以包括：设置于衬底基板1上的数据线Data。第二开关晶体管T3的第一导电部18b与数据线Data耦接。通过数据线Data向第二开关晶体管T3写入数据信号。
在一些实施例中，数据线Data、感测信号线Sense和电源线ELVDD可以与第二极板C2同层设置。
其中，数据线Data、感测信号线Sense、电源线ELVDD和第二极板C2的材料可以选自铜(Cu)、铝(Al)、钼(Mo)、钛(Ti)、铬(Cr)和钨(W)的金属单质以及这些金属单质构成的金属合金。
基于上述，以下，将结合图13和图15所示，对像素驱动电路的工作过程进行描述。
其中，如图13和图15所示，第一栅极信号端G1被配置为接收第一栅极信号G1，第二栅极信号端G2被配置为接收第二栅极信号G2，数据线Data被配置为接收数据信号Data，该数据信号Data例如包括检测数据信号Data 1和显示数据信号Data 2，电源线ELVDD被配置为接收电源电压信号ELVDD，该电源电压信号ELVDD的范围例如为-5V～5V，电源电压信号端ELVSS被配置为接收电源电压信号ELVSS，该电源电压信号ELVSS例如为固定电压信号，例如为小于或等于0V的电压信号；感测信号线Sense被配置为提供复位信号或获得感测信号Sense，其中，复位信号用于对发光器件20的阳极进行复位，感测信号用于计算驱动晶体管T1的阈值电压。
当像素驱动电路工作在一图像帧(1Frame)的消隐时段时，像素驱动电路的工作过程例如为：在第一栅极信号端G1提供的第一栅极信号G1 1的控制下，第二开关晶体管T3开启，通过数据线Data向节点G传输检测数据信号Data 1；在第二栅极信号端G2提供的第二栅极信号G2 1的控制下，第一开关晶体管T2开启，将节点S的信号通过第一开关晶体管T2传输至感测信号线Sense；当检测数据信号Data 1和电源电压信号ELVDD使得节点G控制第二开关晶体管T3截止时，测量出感测信号线Sense上的感测信号Sense的大小， 便可根据检测数据信号Data 1与感测信号Sense之差计算出驱动晶体管T1的阈值电压Vth。
上述过程中，通过控制感测晶体管测量出了感测信号Sense，从而计算出了驱动晶体管的阈值电压，计算出驱动晶体管的阈值电压后再将该阈值电压补偿进显示数据信号Data 2中，从而便完成了对像素驱动电路的外部补偿。参考图15所示，在进行外部补偿时，像素驱动电路需要接收第一栅极信号G1 1和第二栅极信号G2 1，以打开第一开关晶体管T2和第二开关晶体管T3，此时感测信号端Sense处于悬浮状态，其相当于电容；感测数据信号Data 1控制驱动晶体管T1打开后，电源电压信号ELVDD将传输至节点S，对节点S充电直至节点S的电位不再变化，此时节点G的电位与节点S的电位之差则等于驱动晶体管T1的阈值电压，而第一开关晶体管T2也处于开启状态，节点S的信号通过第一开关晶体管T2传输至感测信号端Sense的信号即为感测信号Sense，此时感测信号Sense的大小等于节点S的电位，所以可以通过计算感测数据信号Data 1和感测信号Sense之差计算出驱动晶体管T1的阈值电压。
当像素驱动电路工作在一图像帧的显示时段时，像素驱动电路的工作过程例如包括复位阶段、数据写入阶段和发光阶段。
在复位阶段，在第二栅极信号端G2提供的第二栅极信号G2 2的控制下，第一开关晶体管T2开启，将感测信号端Sense提供的复位信号传输至节点S，以对发光器件20的阳极进行复位。
在数据写入阶段，在第一栅极信号端G1提供的第一栅极信号G1 2的控制下，第二开关晶体管T3开启，将数据线Data提供的显示数据信号Data 2传输至节点G，并对存储电容Cst进行充电。
在发光阶段，在节点G的控制下，驱动晶体管T3开启，存储电容Cst开始向节点G放电，使得节点G的电位保持一段时间，从而保证驱动晶体管T3的开启时间。驱动晶体管T3开启后，在电源线ELVDD提供的电源电压信号ELVDD和其栅极电压的控制下，向发光器件20输出驱动信号，驱动信号例如为驱动电流，在驱动信号的控制下，发光器件20开始发光。
在像素驱动电路工作在一图像帧的过程中，第一栅极信号端G1和第二栅极信号端G2所接收的栅极信号均由栅极驱动电路提供。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种显示面板，包括：
    衬底基板；以及
    设置于所述衬底基板上的像素驱动电路，所述像素驱动电路包括：驱动晶体管和电容器；
    所述驱动晶体管包括：栅极和有源层，所述驱动晶体管的所述有源层包括有源部、第一导电部和第二导电部，所述栅极相比于所述有源层远离所述衬底基板，所述有源部包括与所述栅极齐平的边沿；
    所述电容器包括：沿所述衬底基板的厚度方向，相对设置的第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极耦接，所述第二极板设置于所述栅极远离所述衬底基板的一侧，且所述第二极板能够遮光，所述有源部与栅极齐平的边沿在所述衬底基板上的正投影位于所述第二极板在所述衬底基板上的正投影以内。
  2. 根据权利要求1所述的显示面板，其中，
    所述驱动晶体管的所述有源部位于所述第二极板在所述衬底基板上的正投影以内；
    或者，
    所述第二极板上设置有开口，所述第二极板具有内边沿和外边沿，所述开口的边沿构成所述第二极板的内边沿，所述有源部与栅极齐平的边沿在所述衬底基板上的正投影位于所述第二极板的外边沿在所述衬底基板上的正投影，和所述第二极板的内边沿在所述衬底基板上的正投影之间。
  3. 根据权利要求1或2所述的显示面板，其中，所述驱动晶体管还包括：第一导电图案；
    所述驱动晶体管的所述第一导电部具有第一接触部，所述驱动晶体管的所述第二导电部具有第二接触部；所述第一接触部与所述第一导电图案接触，所述第二接触部与所述第二极板接触。
  4. 根据权利要求3所述的显示面板，其中，所述第一导电图案和所述第二极板同层设置，且所述第一接触部相比于所述第二接触部远离所述有源部。
  5. 根据权利要求1～4任一项所述的显示面板，其中，所述像素驱动电路还包括：第一开关晶体管；
    所述第一开关晶体管包括有源层，所述第一开关晶体管的有源层包括有源部、第一导电部和第二导电部；
    所述第一开关晶体管的所述第一导电部用于接收复位信号或提供感测信号，所述第一开关晶体管的所述第二导电部与所述第二极板耦接。
  6. 根据权利要求1～5任一项所述的显示面板，其中，所述像素驱动电路还包括：设置于所述驱动晶体管的有源层靠近所述衬底基板一侧的遮光金属层；
    所述驱动晶体管的有源部在所述衬底基板上的正投影位于所述遮光金属层在所述衬底基板上的正投影以内，且所述遮光金属层与所述第二极板耦接。
  7. 根据权利要求6所述的显示面板，其中，在所述像素驱动电路还包括第一开关晶体管的情况下，所述像素驱动电路还包括：第二导电图案；
    所述第一开关晶体管的所述第二导电部具有第三接触部，所述第三接触部与所述第二导电图案接触；
    所述第二极板与所述第二导电图案连接为一体结构，或者，所述第二极板在所述衬底基板上的正投影和所述第二导电图案在所述衬底基板上的正投影之间具有间隙，且所述第二导电图案和所述第二极板分别与所述遮光金属层耦接。
  8. 根据权利要求7所述的显示面板，其中，所述第一开关晶体管的有源层和所述驱动晶体管的有源层同层设置，所述第二导电图案和所述第二极板同层设置；
    所述像素驱动电路还包括设置于所述第一开关晶体管的有源层和所述第二导电图案之间的第一绝缘层，以及设置于第一开关晶体管的有源层和遮光金属层之间的第二绝缘层；
    所述第一绝缘层中设置有第一过孔，所述第二绝缘层中设置有第二过孔，所述第一过孔和所述第二过孔在所述衬底基板上的正投影重叠，所述第二导电图案通过所述第一过孔与所述第三接触部接触，所述遮光金属层通过所述第二过孔与所述第三接触部耦接。
  9. 根据权利要求7或8所述的显示面板，其中，
    所述第二导电图案在第一方向和第二方向上均与所述第二极板正对，所述第一方向和所述第二方向是平行于所述衬底基板所在的平面，且相互垂直的两个方向。
  10. 根据权利要求1～9任一项所述的显示面板，其中，
    所述第一极板与所述有源层同层设置，且所述第一极板在所述衬底基板上的正投影与所述第二极板在所述衬底基板上的正投影重叠。
  11. 根据权利要求5～10任一项所述的显示面板，其中，
    所述像素驱动电路还包括：第二开关晶体管；
    所述第二开关晶体管包括有源层，所述第二开关晶体管的有源层包括有 源部、第一导电部和第二导电部；
    所述第二开关晶体管的第一导电部用于接收数据信号，所述第二开关晶体管的第二导电部与所述驱动晶体管的栅极耦接。
  12. 根据权利要求1～11任一项所述的显示面板，还包括：设置于衬底基板上的电源线；
    所述像素驱动电路中所述驱动晶体管的第一导电部与所述电源线耦接。
  13. 根据权利要求12所述的显示面板，其中，
    在所述驱动晶体管还包括第一导电图案的情况下，所述电源线与所述第一导电图案同层设置，且所述电源线与所述第一导电图案接触。
  14. 根据权利要求12或13所述的显示面板，其中，在所述像素驱动电路还包括遮光金属层的情况下，所述显示面板还包括：与所述遮光金属层同层设置的第三导电图案，所述第三导电图案分别与所述驱动晶体管的第一导电部和所述电源线耦接。
  15. 根据权利要求5～14任一项所述的显示面板，还包括：设置于所述衬底基板上的感测信号线；
    所述第一开关晶体管的第一导电部与所述感测信号线耦接。
  16. 根据权利要求15所述的显示面板，还包括：与所述遮光金属层同层设置的第四导电图案，所述第四导电图案分别与所述第一开关晶体管的所述第一导电部和所述感测信号线耦接。
  17. 根据权利要求1～16任一项所述的显示面板，还包括：设置于所述衬底基板上，且与所述像素驱动电路耦接的发光器件；
    所述发光器件发出的光自远离所述衬底基板的一侧出射。
  18. 一种显示装置，包括：如权利要求1～17任一项所述的显示面板。
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CN110190091A (zh) * 2019-05-15 2019-08-30 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN111834465A (zh) * 2019-12-09 2020-10-27 云谷（固安）科技有限公司 阵列基板、显示面板及显示装置
CN111276499A (zh) * 2020-03-26 2020-06-12 合肥鑫晟光电科技有限公司 显示用基板及其制备方法、显示装置
CN111863837A (zh) * 2020-07-13 2020-10-30 武汉华星光电半导体显示技术有限公司 阵列基板和显示面板
CN112259595A (zh) * 2020-10-30 2021-01-22 武汉天马微电子有限公司 一种阵列基板以及显示面板
CN113066804A (zh) * 2021-03-23 2021-07-02 合肥鑫晟光电科技有限公司 显示面板和显示装置

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