WO2022041238A1 - 一种显示基板及其制作方法、显示装置 - Google Patents

一种显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022041238A1
WO2022041238A1 PCT/CN2020/112668 CN2020112668W WO2022041238A1 WO 2022041238 A1 WO2022041238 A1 WO 2022041238A1 CN 2020112668 W CN2020112668 W CN 2020112668W WO 2022041238 A1 WO2022041238 A1 WO 2022041238A1
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WIPO (PCT)
Prior art keywords
sub
pixel
substrate
line pattern
transistor
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PCT/CN2020/112668
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English (en)
French (fr)
Inventor
尚庭华
张毅
刘庭良
韩林宏
杨慧娟
张顺
王予
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2020/112668 priority Critical patent/WO2022041238A1/zh
Priority to US17/418,136 priority patent/US20220336562A1/en
Priority to CN202080001739.8A priority patent/CN114450797B/zh
Publication of WO2022041238A1 publication Critical patent/WO2022041238A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • AMOLED (Active-matrix Organic Light-Emitting Diode, Active Matrix Organic Light Emitting Diode) display device has many advantages such as self-luminous, ultra-thin, fast response, high contrast, wide viewing angle, etc. It is a display device that has received widespread attention. .
  • the AMOLED display device includes a plurality of pixel driving circuits and a plurality of light-emitting elements, and the pixel driving circuits are used to drive the corresponding light-emitting elements to emit light, thereby realizing the display function of the AMOLED display device.
  • the pixel driving circuit drives the light-emitting element to emit light
  • it includes a low-frequency driving method and a high-frequency driving method.
  • the pixel driving circuit controls the pixel data writing time of each row for a long time, and the high-frequency driving method is used.
  • the data writing time of each row of pixels is compressed, so that the data writing time of each row of pixels controlled by the pixel driving circuit is shorter.
  • the purpose of the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display substrate, a display substrate comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, the sub-pixels comprising:
  • a power signal line pattern at least a portion of the power signal line pattern extends along a second direction, the second direction intersecting the first direction;
  • a sub-pixel drive circuit includes a drive transistor and a first reset transistor, the gate of the first reset transistor is electrically connected to the reset signal line pattern, and the first pole of the first reset transistor is connected to the reset signal line pattern.
  • the initialization signal line pattern is electrically connected, and the second pole of the first reset transistor is electrically connected to the gate of the driving transistor;
  • the shield pattern is electrically connected to the power signal line pattern, and the orthographic projection of the shield pattern on the substrate overlaps the orthographic projection of the first pole of the first reset transistor on the substrate .
  • the orthographic projection of the shield pattern on the substrate does not overlap with the orthographic projection of the reset signal line pattern on the substrate.
  • the orthographic projection of the shielding pattern on the substrate overlaps the orthographic projection of the second electrode of the first reset transistor on the substrate.
  • the multiple sub-pixels include:
  • the first sub-pixel and the second sub-pixel are arranged along the second direction, the first sub-pixel includes a first data line pattern, the second sub-pixel includes a second data line pattern, and the first data line pattern is Both at least part and at least part of the second data line pattern extend along the second direction, the first data line pattern is located on the first side of the first sub-pixels in the same column extending along the second direction, so The second data line pattern is located on the second side of the second sub-pixels in the same column extending along the second direction, the first side is opposite to the second side along a first direction, and the first direction intersecting the second direction;
  • the third sub-pixel and the fourth sub-pixel are arranged along the second direction, the third sub-pixel and the first sub-pixel are located in the same row along the first direction, and the fourth sub-pixel and the first sub-pixel are located in the same row.
  • Two sub-pixels are located in the same row; the third sub-pixel includes a third data line pattern, the fourth sub-pixel includes a fourth data line pattern, at least part of the third data line pattern and the fourth data line At least part of the patterns all extend along the second direction, the third data line pattern is located on the second side of the third sub-pixels in the same column extending along the second direction, and the fourth data line pattern is located along the second direction.
  • the first side of the fourth sub-pixels in the same column extending in two directions.
  • the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel all include a first conductive connection part and a fifth conductive connection part;
  • the first subpixel In the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel:
  • the sub-pixel drive circuits all include data writing transistors
  • the first conductive connection portion is respectively electrically connected with the corresponding data line pattern and the first pole of the data writing transistor; the second pole of the data writing transistor is electrically connected with the first pole of the driving transistor;
  • the second electrode of the first reset transistor is electrically connected to the gate of the driving transistor through the fifth conductive connection part;
  • the orthographic projection of the shielding pattern on the substrate at least partially overlaps the orthographic projection of the first conductive connection portion on the substrate.
  • the orthographic projection of at least part of the shielding pattern on the substrate, the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the fifth conductive connection portion on the substrate is between orthographic projections.
  • the first sub-pixel in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel:
  • Each of the sub-pixel drive circuits includes a first transistor, a first electrode of the first transistor is electrically connected to a second electrode of the drive transistor, and a second electrode of the first transistor is connected to a gate of the drive transistor. electrical connection;
  • the active pattern of the first transistor includes two semiconductor parts spaced apart, and a first conductor part respectively connecting the two semiconductor parts;
  • the projection of the shielding pattern on the substrate also at least partially overlaps the orthographic projection of the first conductor portion on the substrate.
  • the shielding pattern is located between the first electrode of the first reset transistor and the first conductive connection portion.
  • the power supply signal line pattern includes: a power supply main body part that is electrically connected and power overhangs;
  • the orthographic projection of the protruding portion of the power supply on the substrate overlaps the orthographic projection of the first data line pattern on the substrate, and the main portion of the power supply is on the substrate
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the adjacent data line patterns along the first direction on the substrate.
  • the orthographic projection of the power protruding portion on the substrate does not overlap with the orthographic projection of the second data line pattern on the substrate.
  • the orthographic projection of the power protruding portion on the substrate does not overlap with the orthographic projection of the third data line pattern on the substrate.
  • the orthographic projection of the protruding portion of the power supply on the substrate overlaps with the orthographic projection of the fourth data line pattern on the substrate, and the main portion of the power supply
  • the orthographic projection on the substrate overlaps the orthographic projection of the adjacent data line patterns along the first direction on the substrate.
  • the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel all include:
  • a power compensation pattern at least a part of the power compensation pattern extends along the first direction, and the power signal line pattern and the power compensation pattern are located on the first data line pattern, the second data line pattern, a side of the third data line pattern and the fourth data line pattern close to the substrate;
  • the power compensation patterns are respectively electrically connected with the power signal line patterns in the sub-pixels to which they belong, and the power signal line patterns in the adjacent sub-pixels along the first direction.
  • the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel all include: the reset signal line pattern, the gate line pattern distributed along the second direction and a light emission control signal line pattern; at least part of the grid line pattern extends along the first direction, and at least part of the light emission control signal line pattern extends along the first direction;
  • the orthographic projection of the power compensation pattern on the substrate is located in the grid line pattern Between the orthographic projection on the substrate and the orthographic projection of the light emitting control signal line pattern on the substrate.
  • the power supply signal line pattern includes: a power supply main body part that is electrically connected and a power supply protruding portion with a gap between the power supply protruding portion and the power supply main body portion;
  • the first end of the power compensation pattern is electrically connected to the power protruding portion in the sub-pixel to which it belongs; the second end of the power compensation pattern is electrically connected to the main portion of the power supply in the adjacent sub-pixel along the first direction .
  • each of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel includes: a sixth transistor, and a sixth transistor stacked in a direction away from the substrate.
  • the light-emitting element includes a first light-emitting element, and the first light-emitting element includes a first anode pattern;
  • the orthographic projection of the first anode pattern on the substrate does not overlap with the orthographic projection of the first data line pattern on the substrate.
  • the light-emitting element includes a third light-emitting element, and the third light-emitting element includes a third anode pattern;
  • the fourth conductive connection portion includes a solid portion and a hollow portion
  • the orthographic projection of the third anode pattern on the substrate overlaps with the orthographic projection of the third data line pattern on the substrate, and the data lines adjacent to the third data line pattern along the first direction the orthographic overlap of the graphics on the substrate;
  • the orthographic projection of the third anode pattern on the substrate overlaps with the orthographic projection of the solid portion on the substrate; and/or the orthographic projection of the third anode pattern on the substrate is the same as the orthographic projection of the third anode pattern on the substrate.
  • Orthographic projections of the hollow portion on the base overlap.
  • the light-emitting element includes a second light-emitting element, and the second light-emitting element includes a second anode pattern;
  • the orthographic projection of the second anode pattern on the substrate overlaps the orthographic projection of the second data line pattern on the substrate.
  • the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel all include: a light-emitting element, a grid line pattern and a light-emitting control signal line pattern; the grid at least part of the line pattern and at least part of the light emission control signal line pattern both extend along the first direction;
  • the sub-pixel driving circuit further includes: a first transistor, a data writing transistor, a fifth a transistor, a sixth transistor, a second reset transistor and a storage capacitor;
  • the gate of the drive transistor is electrically connected to the second electrode of the first transistor, the first electrode of the drive transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the drive transistor is electrically connected to the second electrode of the fifth transistor. the first electrode of the first transistor is electrically connected;
  • the gate of the first transistor is electrically connected to the gate line pattern
  • the gate of the data writing transistor is electrically connected to the gate line pattern
  • the first pole of the data writing transistor is electrically connected to the data line pattern in the sub-pixel to which it belongs
  • the second pole of the data writing transistor is electrically connected electrically connected to the first electrode of the driving transistor
  • the gate of the fifth transistor is electrically connected to the light-emitting control signal line pattern, and the first electrode of the fifth transistor is electrically connected to the power supply signal line pattern;
  • the gate of the sixth transistor is electrically connected to the light-emitting control signal line pattern, the first pole of the sixth transistor is electrically connected to the second pole of the driving transistor, and the second pole of the sixth transistor is electrically connected to the second pole of the driving transistor.
  • the anode pattern included in the light-emitting element is electrically connected;
  • the gate of the second reset transistor is electrically connected to the reset signal line pattern in the next sub-pixel adjacent in the second direction, and the first electrode of the second reset transistor is connected to the adjacent sub-pixel in the second direction.
  • the initialization signal line pattern in the next sub-pixel is electrically connected, and the second pole of the second reset transistor is electrically connected to the anode pattern;
  • the first plate of the storage capacitor is multiplexed as the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the power signal line pattern.
  • a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.
  • a third aspect of the present disclosure provides a method for manufacturing a display substrate, including: fabricating a plurality of sub-pixels distributed in an array on a substrate, and the step of fabricating the sub-pixels specifically includes:
  • a sub-pixel drive circuit is fabricated, the sub-pixel drive circuit includes a drive transistor and a first reset transistor, the gate of the first reset transistor is electrically connected to the reset signal line pattern, and the first pole of the first reset transistor is is electrically connected to the initialization signal line pattern, and the second electrode of the first reset transistor is electrically connected to the gate of the driving transistor;
  • the shielding pattern is electrically connected with the power signal line pattern, and the orthographic projection of the shielding pattern on the substrate is orthogonal to the orthographic projection of the first pole of the first reset transistor on the substrate stack.
  • 1a is a schematic diagram of a sub-pixel layout in the prior art
  • Fig. 1b is a schematic diagram of the layout of the active layer in Fig. 1;
  • FIG. 1c is a schematic diagram of the layout of the first gate metal layer in FIG. 1;
  • FIG. 1d is a schematic diagram of the layout of the second gate metal layer in FIG. 1;
  • FIG. 1e is a schematic diagram of the layout of the source-drain metal layer in FIG. 1;
  • FIG. 2 is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a working timing diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a first layout of a sub-pixel according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a second layout of sub-pixels according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of the layout of the active layer and the first gate metal layer in FIG. 5;
  • FIG. 7 is a schematic diagram of the layout of the second gate metal layer in FIG. 5;
  • FIG. 8 is a schematic diagram of the layout of the first source-drain metal layer in FIG. 5;
  • FIG. 9 is a schematic structural diagram of a power supply compensation pattern in FIG. 5;
  • FIG. 10 is a schematic diagram of the layout of the first source-drain metal layer and the second source-drain metal layer in FIG. 5;
  • FIG. 11 is a schematic diagram of the layout of the second source-drain metal layer in FIG. 5;
  • 12 is a schematic diagram of the layout of eight sub-pixels
  • 13a is a schematic cross-sectional view along the direction A1A2 in FIG. 12;
  • Fig. 13b is a schematic cross-sectional view along the direction B1B2 in Fig. 12;
  • Figure 13c is a schematic cross-sectional view along the C1C2 direction in Figure 12;
  • 13d is a schematic cross-sectional view along the D1D2 direction in FIG. 12;
  • FIG. 14 is a schematic diagram of the layout of the two-layer source-drain metal layer and the anode layer in FIG. 12;
  • FIG. 15 is a schematic diagram of the layout of the second source-drain metal layer and the anode layer in FIG. 12;
  • FIG. 16 is a schematic diagram of the layout of the active layer in FIG. 12;
  • FIG. 17 is a schematic diagram of the layout of the first gate metal layer in FIG. 12;
  • FIG. 18 is a schematic diagram of the layout of the second gate metal layer in FIG. 12;
  • FIG. 19 is a schematic diagram of the layout of the first source-drain metal layer in FIG. 12 .
  • the structure of the AMOLED display panel includes: a substrate, a plurality of sub-pixel driving circuits disposed on the substrate, and a plurality of light-emitting elements disposed on the side of the sub-pixel driving circuits facing away from the substrate, the light-emitting elements and the
  • the sub-pixel driving circuits are in one-to-one correspondence, and the sub-pixel driving circuits are used to drive the corresponding light-emitting elements to emit light, thereby realizing the display function of the display panel.
  • the sub-pixel driving circuit generally includes a plurality of thin film transistors. As shown in FIG. 1a, when the sub-pixel driving circuit includes 7 thin film transistors Q1-Q7, The specific layout method, when laid out in this way, the sub-pixel driving circuit includes an active layer as shown in FIG. 1b, a first metal layer as shown in FIG. 1c, and a second metal layer as shown in FIG. 1d. , and the third metal layer as shown in FIG. 1e ; the active layer includes an active pattern for forming the channel region of each thin film transistor (the part in the dashed box in FIG.
  • the The active pattern is electrically connected, which is a doped active pattern with conductive properties (as shown in the part outside the dashed frame in Figure 1b);
  • the first metal layer includes the gate of each thin film transistor, and the scanning of the gate electrical connection
  • the second metal layer includes an initialization signal line VINT, and the sub-pixel driving circuit
  • the third metal layer includes a data line DATA, a power signal line VDD, and some conductive connection parts (such as marks 341-343).
  • some via holes may also be arranged.
  • the sub-pixel driving circuit in the related art implements high-frequency driving, the data writing time of each row of pixels controlled by the pixel driving circuit is short, which easily leads to the problem of insufficient data writing time for each row of pixels.
  • the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, the plurality of sub-pixels can be divided into a plurality of sub-pixels arranged in sequence along the second direction A row of sub-pixels, and a plurality of columns of sub-pixels arranged in sequence along the first direction, each sub-pixel includes: a light-emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92 and a light-emitting control signal line pattern 93 .
  • the plurality of sub-pixels include:
  • a first sub-pixel and a second sub-pixel arranged along the second direction the first sub-pixel includes a first data line pattern 981, the second sub-pixel includes a second data line pattern 982, the first data line At least part of the pattern 981 and at least part of the second data line pattern 982 both extend in the second direction, and the first data line pattern 981 is located in the same column of the first sub-pixels extending in the second direction.
  • the second data line pattern 982 is located on the second side of the second sub-pixels in the same column extending along the second direction, and the first side and the second side are opposite along the first direction , the first direction intersects the second direction.
  • the first side is the right side in FIG. 4
  • the second side is the left side in FIG. 4 .
  • Both the first sub-pixel and the second sub-pixel include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor (ie, the third transistor T3) and a data writing transistor (ie, the fourth transistor T4).
  • the first electrode of the data writing transistor is electrically connected to the first data line pattern 981
  • the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor.
  • the first electrode of the data writing transistor is electrically connected to the second data line pattern 982
  • the second electrode of the data writing transistor is electrically connected to the second electrode of the driving transistor.
  • one of the adjacent sub-pixels includes the first sub-pixel of the data writing transistor.
  • the electrode is electrically connected to the first data line pattern 981
  • the first electrode of the data writing transistor included in another subpixel in the adjacent subpixel is electrically connected to the second data line pattern 982 .
  • the data line patterns electrically connected to the data writing transistors in adjacent sub-pixels are different, so that in the same column of sub-pixels, adjacent sub-pixels are composed of different data lines.
  • the line pattern provides data signals, which ensures that each sub-pixel has sufficient data signal writing time, thereby solving the problem of insufficient data signal writing time for each row of sub-pixels when the display substrate is in high-frequency display.
  • the first electrode of the first reset transistor for example, the second transistor T2
  • the initialization signal transmitted on 94 has an effect, thereby affecting the display effect of the display substrate.
  • an embodiment of the present disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels arrayed on the substrate, the sub-pixels including:
  • a reset signal line pattern 59 at least part of the reset signal line pattern 95 extending along the first direction;
  • a power signal line pattern 91 at least a part of the power signal line pattern 91 extends along a second direction, and the second direction intersects with the first direction;
  • a sub-pixel driving circuit includes a driving transistor (ie the third transistor T3) and a first reset transistor (ie the second transistor T2), the gate of the first reset transistor and the reset signal line pattern 95 is electrically connected, the first pole of the first reset transistor is electrically connected to the initialization signal line pattern 94, and the second pole of the first reset transistor is electrically connected to the gate of the drive transistor;
  • a shielding pattern 80, the shielding pattern 80 is electrically connected to the power supply signal line pattern 91, and the orthographic projection of the shielding pattern 80 on the substrate is the same as that of the first electrode of the first reset transistor on the substrate. Orthographic overlap.
  • the display substrate includes a plurality of sub-pixels distributed on the substrate in an array, and the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels.
  • the plurality of rows of sub-pixels are arranged along the second direction, and each row of sub-pixels includes a plurality of the sub-pixels arranged in sequence along the first direction.
  • the plurality of columns of sub-pixels are arranged along the first direction, and each column of sub-pixels includes a plurality of the sub-pixels arranged in sequence along the second direction.
  • the first direction includes a horizontal direction
  • the second direction includes a vertical direction
  • each sub-pixel includes a data line pattern, and at least part of the data line pattern extends along the second direction.
  • the data line patterns included in each sub-pixel in the same column of sub-pixels are electrically connected in sequence to form an integrated structure.
  • At least a part of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used to transmit an initialization signal having a fixed potential.
  • the initialization signal line patterns 94 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure.
  • At least a portion of the reset signal line pattern 95 extends along the second direction for transmitting reset signals.
  • the reset signal line patterns 95 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure.
  • At least a part of the power signal line pattern 91 extends along the second direction, and is used for transmitting a power signal having a fixed potential.
  • the power signal line patterns 91 included in the sub-pixels located in the same column are electrically connected in sequence to form an integrated structure.
  • Each sub-pixel includes a sub-pixel driving circuit.
  • the sub-pixel driving circuit includes a storage capacitor and a plurality of thin film transistors, as shown in FIG. 2 and FIG. 5 , exemplarily, the sub-pixel driving circuit includes 7T1C, that is, 7 transistors and one storage capacitor.
  • the sub-pixel driving circuit is used for generating a driving signal for driving the light-emitting element to emit light.
  • the sub-pixel drive circuit includes a drive transistor and a first reset transistor, the gate of the first reset transistor is electrically connected to the reset signal line pattern 95, and the first electrode of the first reset transistor is connected to the reset signal line pattern 95.
  • the initialization signal line pattern 94 is electrically connected, and the second electrode of the first reset transistor is electrically connected to the gate of the driving transistor; in the reset period, the first reset transistor can transmit the received initialization signal to The gate of the driving transistor realizes the gate reset of the driving transistor.
  • Each sub-pixel includes a light-emitting element located on a side of the sub-pixel driving circuit facing away from the substrate.
  • the light-emitting element includes an anode pattern, a light-emitting functional layer, and a cathode that are sequentially stacked along a direction away from the substrate.
  • the anode pattern is electrically connected to a sub-pixel driving circuit in the sub-pixel to which it belongs, and receives a driving signal provided by the sub-pixel driving circuit.
  • the light-emitting functional layer includes an organic light-emitting material layer, and in addition, the light-emitting functional layer may also include: an electron transport layer (election transporting layer, referred to as ETL), an electron injection layer (election injection layer, referred to as EIL), empty
  • ETL electron transport layer
  • EIL electron injection layer
  • HTL hole transporting layer
  • HIL hole injection layer
  • the sub-pixel further includes a shielding pattern 80, the orthographic projection of the shielding pattern 80 on the substrate overlaps the orthographic projection of the power signal line pattern 91 on the substrate, the shielding pattern 80 and the The power signal line pattern 91 is electrically connected through via holes provided at the overlap. It should be noted that, in the drawings provided in the present disclosure, the small boxes with intersecting lines in the middle represent via holes.
  • the orthographic projection of the shielding pattern 80 on the substrate and the first electrode of the first reset transistor on the substrate are arranged.
  • the orthographic projections overlap, so that the shielding pattern 80 shields the interference caused by the transition of the data signal to the first pole of the first reset transistor, thereby avoiding the initialization of the transmission on the initialization signal line pattern 94 due to the transition of the data signal.
  • the signal has an impact, which effectively improves the display effect of the display substrate.
  • the above-mentioned shielding pattern 80 is electrically connected to the power signal line pattern 91, so that the shielding pattern 80 has the same stable potential as the power signal transmitted by the power signal line pattern 91, which is not only beneficial to the sub-pixels
  • the driving circuit is in a stable working state, which better ensures the shielding effect of the shielding pattern 80 .
  • the orthographic projection of the shielding pattern 80 on the substrate is set to not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate.
  • the specific layout positions of the shielding pattern 80 are various.
  • the orthographic projection of the shielding pattern 80 on the substrate and the orthographic projection of the reset signal line pattern 95 on the substrate are different.
  • the minimum distance between them is greater than the threshold.
  • the threshold is 5 ⁇ m.
  • the above arrangement makes the shield pattern 80 and the reset signal line pattern 95 not overlap in the direction perpendicular to the substrate, thereby avoiding increasing the load of the reset signal line pattern 95 .
  • the orthographic projection of the shielding pattern 80 on the substrate overlaps the orthographic projection of the second electrode of the first reset transistor on the substrate.
  • the orthographic projection of the shielding pattern 80 on the substrate completely covers the orthographic projection of the second pole of the first reset transistor on the substrate.
  • the above-mentioned setting of the orthographic projection of the shielding pattern 80 on the substrate overlaps with the orthographic projection of the second pole of the first reset transistor on the substrate, so that the shielding pattern 80 shields the transition caused by the data signal.
  • the plurality of sub-pixels are divided into a plurality of columns of sub-pixels, and each column of sub-pixels includes a plurality of the sub-pixels arranged in sequence along the second direction;
  • the sub-pixel driving circuit further includes: a second reset transistor (ie, a seventh transistor T7), the gate of the second reset transistor is connected to the reset signal line pattern in the next sub-pixel adjacent along the second direction 95' is electrically connected, the first pole of the second reset transistor is electrically connected to the initialization signal line pattern 94' in the next sub-pixel adjacent along the second direction, and the second pole of the second reset transistor is electrically connected It is electrically connected to the anode pattern in the sub-pixel to which it belongs;
  • a second reset transistor ie, a seventh transistor T7
  • the gate of the second reset transistor is connected to the reset signal line pattern in the next sub-pixel adjacent along the second direction 95' is electrically connected
  • the first pole of the second reset transistor is electrically connected to the initialization signal line pattern 94' in the next sub-pixel adjacent along the second direction
  • the second pole of the second reset transistor is electrically connected It is electrically connected to the anode pattern in the sub-pixel to which it belongs
  • the orthographic projection of the shield pattern 80 on the substrate overlaps the orthographic projection of the first electrode of the second reset transistor on the substrate.
  • the gate of the second reset transistor is electrically connected to the reset signal line pattern 95' in the next sub-pixel adjacent along the second direction
  • the first pole of the second reset transistor is connected to the reset signal line pattern 95' along the second direction.
  • the initialization signal line pattern 94' in the next sub-pixel adjacent to the second direction is electrically connected
  • the second pole of the second reset transistor is electrically connected to the anode pattern in the sub-pixel to which it belongs
  • the seventh transistor T7 is used for For resetting the anode pattern.
  • the above-mentioned setting of the orthographic projection of the shielding pattern 80 on the substrate overlaps with the orthographic projection of the first pole of the second reset transistor on the substrate, so that the shielding pattern 80 shields the transition caused by the data signal The influence on the first pole, thereby avoiding the influence on the initialization signal transmitted on the initialization signal line pattern 94 .
  • the plurality of sub-pixels include:
  • the second data line pattern 982 is located on the second side of the second sub-pixel M2 in the same column extending along the second direction, the first side and the second sub-pixel M2 The sides are opposite to each other along a first direction, and the first direction intersects with the second direction;
  • the third data line pattern At least a portion of 983 and at least a portion of the fourth data line pattern 984 both extend along the second direction
  • the third data line pattern 983 is located at the second position of the third sub-pixel M3 in the same column extending along the second direction.
  • the fourth data line pattern 984 is located on the first side of the fourth sub-pixel M4 in the same column extending along the second direction.
  • the first data line pattern 981 and at least part of the second data line pattern 982 both extend along the second direction.
  • the first data line pattern 981 is configured to provide a first data signal to the first sub-pixel M1
  • the second data line pattern 982 is configured to provide a second data signal to the second sub-pixel M2; sub-pixels located in the same column
  • the first data line patterns 981 included in each of the first sub-pixels M1 are sequentially electrically connected to form an integrated structure.
  • the second data line patterns 982 included in each of the second sub-pixels M2 located in the same column of sub-pixels are sequentially electrically connected to form an integrated structure.
  • the first data line pattern 981 is: along the second direction, the current data writing position of the first sub-pixel M1 (such as the position where the data line protrusion 9802 is located) and the lower A data line portion between data writing positions of adjacent first sub-pixels M1 in a row.
  • the first sub-pixels M1 and the second sub-pixels M2 are alternately arranged.
  • the third sub-pixels M3 and the fourth sub-pixels M4 are alternately arranged.
  • the first sub-pixel M1 is an odd-numbered sub-pixel, and the odd-numbered sub-pixel receives the first data signal provided by the first data line pattern 981 included therein, and the second sub-pixel M1 is an odd-numbered sub-pixel.
  • the pixel M2 is an even-numbered sub-pixel, and the even-numbered sub-pixel receives a second data signal provided by the second data line pattern 982 included therein.
  • the first side is set as the right side in FIG. 5
  • the second side is set as the left side in FIG. 5
  • the first data line pattern 981 is located on the first side of the same column of sub-pixels
  • the second data line pattern 982 is located on the second side of the same column of sub-pixels.
  • the sub-pixel driving circuit includes a driving transistor and a data writing transistor.
  • a first electrode of the data writing transistor is electrically connected to the first data line pattern 981.
  • the first electrode of the data writing transistor is electrically connected to the second data line pattern 982.
  • the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and the data writing transistor can transmit the data signal received by the first electrode to the driving transistor the first pole.
  • the patterns of data lines electrically connected to the first electrodes of the data writing transistors in adjacent sub-pixels are different.
  • the first electrode of the data writing transistor included in one of the adjacent sub-pixels is electrically connected to the first data line pattern 981
  • the other one of the adjacent sub-pixels is electrically connected to the first data line pattern 981.
  • the first electrode of the data writing transistor included in one sub-pixel is electrically connected to the second data line pattern 982 .
  • the third data line pattern 983 and at least part of the fourth data line pattern 984 both extend along the second direction.
  • the third data line patterns 983 included in each of the third sub-pixels M3 located in the same column of sub-pixels are sequentially electrically connected to form an integrated structure.
  • the fourth data line patterns 984 included in each of the fourth sub-pixels M4 located in the same column of sub-pixels are sequentially electrically connected to form an integrated structure.
  • the third data line pattern is configured to provide a third data signal to a third subpixel
  • the fourth data line pattern is configured to provide a fourth data signal to a fourth subpixel.
  • the third sub-pixel M3 and the first sub-pixel M1 are located in the same row, and the fourth sub-pixel M4 and the second sub-pixel M2 are located in the same row.
  • the third sub-pixel M3 and the fourth sub-pixel M4 also include sub-pixel driving circuits.
  • the first pole of the data writing transistor is connected to the The three data line patterns 983 are electrically connected, and in the fourth sub-pixel M4, the first electrode of the data writing transistor is electrically connected to the fourth data line pattern 984 .
  • the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and the data writing transistor can transmit the data signal received by the first electrode to the driving transistor the first pole.
  • the first side is set as the right side in FIG. 5
  • the second side is set as the left side in FIG. 5
  • the third data line pattern 983 is located on the second side of the third sub-pixel in the same column extending along the second direction
  • the fourth data line pattern 984 is located on the fourth sub-pixel in the same column extending along the second direction the first side of the pixel;
  • the first data line pattern 981 and the third data line pattern 983 are both located in the first sub-pixel M1 and the third data line pattern 981 to which the first data line pattern 981 belongs. Between the third sub-pixels M3 to which the third data line pattern 983 belongs.
  • the second data line pattern 982 and the fourth data line pattern 984 are both located in the second sub-pixel M2 and the fourth data line pattern to which the second data line pattern 982 belongs. Between the fourth sub-pixels M4 to which the line pattern 984 belongs.
  • the structures of the sub-pixel driving circuits included in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 are the same.
  • the differences between M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 lie in the arrangement of the data lines and the structure of the light-emitting element.
  • adjacent sub-pixels are provided with data signals by different data line patterns, ensuring that each sub-pixel has sufficient data signal writing time, thereby solving the problem of solving the problem.
  • the data signal writing time of each row of sub-pixels is insufficient.
  • the plurality of sub-pixels further include: a fifth sub-pixel M5, a sixth sub-pixel M6, a seventh sub-pixel M7 and an eighth sub-pixel M8; the fifth sub-pixel M5 and all The sixth sub-pixels M6 are alternately arranged along the second direction, and the seventh sub-pixels M7 and the eighth sub-pixels M8 are alternately arranged along the second direction; along the first direction, the first The sub-pixel M1, the third sub-pixel M3, the fifth sub-pixel M5, and the seventh sub-pixel M7 are located in the same row; along the first direction, the second sub-pixel M2, the fourth sub-pixel M2, the The sub-pixel M4, the sixth sub-pixel M6 and the eighth sub-pixel M8 are located in the same row.
  • the eight sub-pixels from the first sub-pixel M1 to the eighth sub-pixel M8 form a repeating unit, and the display substrate includes a plurality of the repeating units.
  • the first sub-pixel M1 , the second sub-pixel M2 , the third sub-pixel M3 and the fourth sub-pixel M4 are all including a first conductive connection part 961 and a fifth conductive connection part 965;
  • the sub-pixel drive circuits all include data writing transistors
  • the first conductive connection portion 961 is respectively electrically connected to the corresponding data line pattern and the first electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor;
  • the second pole of the first reset transistor (ie the second transistor T2) is electrically connected to the gate of the driving transistor through the fifth conductive connection part 965;
  • the orthographic projection of the shielding pattern 80 on the substrate at least partially overlaps the orthographic projection of the first conductive connection portion 961 on the substrate.
  • the fifth conductive connection portion 965 extends along the second direction.
  • the orthographic projection of one end of the fifth conductive connection portion 965 on the substrate and the orthographic projection of the second electrode of the second transistor T2 on the substrate have a sixth overlapping area, and the fifth conductive connection One end of the portion 965 is electrically connected to the second electrode of the second transistor T2 through a via hole provided in the sixth overlapping region, and the other end of the fifth conductive connection portion 965 is an orthographic projection on the substrate It overlaps with the orthographic projection of the gate of the driving transistor on the substrate, and the other end of the fifth conductive connection portion 965 is electrically connected to the gate of the driving transistor through a via hole disposed at the overlap. .
  • the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 all include a data line main body portion 9801 and a data line protruding portion 9802, so The data line body portion 9801 extends along the second direction, and the data line protrusion portion 9802 protrudes from the data line body portion 9801 along the first direction.
  • Each of the sub-pixels further includes a first conductive connection portion 961.
  • at least part of the first conductive connection portion 961 extends along the second direction.
  • the orthographic projection of the first end of the first conductive connection portion 961 on the substrate has a first overlapping area with the orthographic projection of the corresponding data line protrusion 9802 on the substrate.
  • the first end of the conductive connection portion 961 is electrically connected to the data line protrusion 9802 through a via hole disposed in the first overlapping region.
  • the orthographic projection of the second end of the first conductive connection portion 961 on the substrate has a second overlapping area with the orthographic projection of the first electrode of the data writing transistor on the substrate.
  • the second end of a conductive connection portion 961 is electrically connected to the first electrode of the data writing transistor through a via hole disposed in the second overlapping region, and the first electrode of the data writing transistor passes through the first electrode of the data writing transistor.
  • a conductive connection portion 961 receives the data signal provided by the corresponding data line pattern.
  • the shielding pattern 80 includes a first shielding portion 801 and a second shielding portion 802 that are electrically connected to each other, and the orthographic projection of the first shielding portion 801 on the substrate is at the same position as the power signal line pattern 91 .
  • the orthographic projections on the substrate overlap, and the first shielding portion 801 and the power signal line pattern 91 are directly electrically connected through the via holes disposed at the overlap.
  • the first shielding portion 801 and the second shielding portion 802 are formed as an integral structure.
  • the first shielding portion 801 is a square structure extending along the first direction, and the orthographic projection of the first shielding portion 801 on the substrate is at the first pole of the second transistor T2.
  • the orthographic projection on the substrate overlaps, and/or, the orthographic projection of the first shielding portion 801 on the substrate is the same as that of the seventh transistor T7 in the adjacent sub-pixels along the second direction.
  • the orthographic projections of a pole on the substrate overlap.
  • the orthographic projection of the first shielding portion 801 on the substrate does not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate.
  • the orthographic projection of the first shielding portion 801 in the shielding pattern 80 on the substrate at least partially overlaps the orthographic projection of the first conductive connecting portion 961 on the substrate.
  • the above-mentioned setting of the orthographic projection of the shielding pattern on the substrate at least partially overlaps the orthographic projection of the first conductive connection portion on the substrate, which can effectively avoid the potential generation of other peripheral functional graphics due to changes in data signals. influence.
  • the orthographic projection of at least part of the shielding pattern 80 on the substrate, the orthographic projection of the first conductive connection portion 961 on the substrate is the same as the orthographic projection of the first conductive connection portion 961 on the substrate.
  • Five conductive connections 965 are between orthographic projections on the substrate.
  • the orthographic projection of the second shielding portion 802 in the shielding pattern 80 on the substrate is located between the second overlapping area and the sixth overlapping area. between.
  • the second shielding portion 802 is a square structure extending along the second direction.
  • the above arrangement enables the second shielding portion 802 to better shield the influence of the data signal change on the second pole of the second transistor T2, thereby avoiding the influence of the data signal change on the gate signal of the driving transistor. Since the gate signal of the driving transistor directly affects the brightness of the sub-pixel, the above arrangement makes the gate potential of the driving transistor more stable, so that the display substrate can obtain better display effect when used for display.
  • the first sub-pixel M1 , the second sub-pixel M2 , the third sub-pixel M3 and the fourth sub-pixel M4 middle in the first sub-pixel M1 , the second sub-pixel M2 , the third sub-pixel M3 and the fourth sub-pixel M4 middle:
  • Each of the sub-pixel driving circuits includes a first transistor T1, a first pole of the first transistor T1 is electrically connected to a second pole of the driving transistor, and a second pole of the first transistor T1 is connected to the driving transistor Grid connection;
  • the active pattern of the first transistor T1 includes two semiconductor parts arranged at intervals, and a first conductor part respectively connecting the two semiconductor parts;
  • the projection of the shielding pattern 80 on the substrate also at least partially overlaps the orthographic projection of the first conductor portion on the substrate.
  • each of the sub-pixels further includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the gate line pattern 92, and the first electrode of the first transistor T1 is connected to the first electrode of the driving transistor.
  • the two electrodes are electrically connected, and the second electrode of the first transistor T1 is electrically connected to the gate of the driving transistor.
  • the first transistor T1 is formed in a double gate structure, and the active pattern of the first transistor T1 includes two semiconductor parts arranged at intervals, and a first conductor part respectively connecting the two semiconductor parts, the first
  • the orthographic projection of the gate of the transistor T1 on the substrate covers the orthographic projection of the two semiconductor parts on the substrate, and the orthographic projection of the gate of the first transistor T1 on the substrate is the same as the orthographic projection of the gate of the first transistor T1 on the substrate.
  • the orthographic projections of the first conductor portions on the substrate do not overlap.
  • the shielding pattern 80 further includes a third shielding portion 803 electrically connected to the first shielding portion 801 , and at least a part of the third shielding portion 803 is a square structure extending along the second direction.
  • the first shielding portion 801 and the third shielding portion 803 are formed as an integral structure.
  • the shielding pattern 80 further includes a third shielding portion 803 electrically connected to the first shielding portion 801 , and the orthographic projection of the third shielding portion 803 on the substrate is the same as the first conductor portion.
  • the orthographic projections on the substrate overlap.
  • the orthographic projection of the third shielding portion 803 on the substrate overlaps the orthographic projection of the first conductor portion on the substrate. This arrangement enables the third shield pattern 80 to shield the first conductor portion, thereby preventing the change of the data signal from affecting the first transistor T1, thereby preventing the change of the data signal from affecting the driving transistor. gate signal has an effect.
  • the shield pattern 80 is located between the first pole of the first reset transistor (ie, the second transistor T2 ) and the first conductive connection portion 961 along a direction perpendicular to the substrate. .
  • the display substrate further includes a second gate insulating layer located between the first electrode of the second transistor T2 and the first conductive connection portion 961, and in each sub-pixel, the initialization signal Both the line pattern 94 and the shielding pattern 80 are located on the surface of the second gate insulating layer facing away from the substrate.
  • both the initialization signal line pattern 94 and the shield pattern 80 are located on the surface of the second gate insulating layer facing away from the substrate, so that the initialization signal line pattern 94 and the shield pattern 80 are arranged on the same layer , when the initialization signal line pattern 94 and the shield pattern 80 are made of the same material, the initialization signal line pattern 94 and the shield pattern 80 can be formed in the same patterning process, so as to simplify the The manufacturing process of the display substrate is improved, and the manufacturing cost is saved.
  • each The power supply signal line patterns 91 in the sub-pixels all include: a power supply main body part (including a first part 911 and a second part 912 ) and a power supply protruding part 913 that are electrically connected to each other;
  • the orthographic projection of the power protruding portion 913 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate, and the main portion of the power supply is on the substrate.
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of an adjacent data line pattern (such as the third data line pattern 983 in FIG. 12 ) on the substrate along the first direction.
  • each sub-pixel includes the power supply signal line pattern 91, and at least a part of the power supply signal line pattern 91 extends along the second direction.
  • the power signal line patterns 91 included in each sub-pixel are electrically connected in sequence to form an integrated structure.
  • the specific structure of the power supply signal line pattern 91 is varied.
  • the power supply signal line pattern 91 includes a first part 911 and a second part 912 that are electrically connected to each other, and the first part 911 and the second part are 912 alternate settings.
  • the second portion 912 protrudes from the first portion 911 along the first direction.
  • the orthographic projection of the first portion 911 on the substrate and the data line main body portion 9801 of the third data line pattern 983 adjacent to the first direction along the first direction are in the same position.
  • the orthographic projections on the substrate overlap, and the orthographic projections of the second portion 912 on the substrate do not overlap with the orthographic projections of the data line main portion 9801 of the third data line pattern 983 on the substrate.
  • At least part of the first part 911 extends along the second direction, and at least part of the second part 912 extends along the second direction, in a direction perpendicular to the second direction, so
  • the width of the first portion 911 is equal to the width of the second portion 912, or the width of the first portion 911 is greater than the width of the second portion 912, or the width of the first portion 911 is smaller than the width of the second portion 912. width.
  • the overlapping area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, and the area along the The orthographic projection of the data line pattern adjacent to the first data line pattern 981 in the first direction on the substrate is close to the overlapping area between the orthographic projection of the functional pattern with a fixed potential on the substrate , thereby effectively reducing the load difference between the first data line pattern 981 and the adjacent data line patterns along the first direction.
  • the function patterns with fixed units include: a power supply signal line pattern 91 , an initialization signal line pattern 94 , and a conductive function pattern electrically connected to the power supply signal line pattern 91 or the initialization signal line pattern 94 (eg: the second conductive connection portion 962) and the like.
  • the orthographic projection of the power protruding portion 913 on the substrate is where the second data line pattern 982 is located.
  • the orthographic projections on the substrates do not overlap.
  • the orthographic projection of the power protruding portion 913 on the substrate, the extension portion of the first data line 981 adjacent to the second direction is on the substrate orthographic overlap.
  • the orthographic projection of the power protruding portion 913 on the substrate is where the third data line pattern 983 is located.
  • the orthographic projections on the substrates do not overlap.
  • the orthographic projection of the power protruding portion 913 on the substrate, and the extension portion of the fourth data line 984 adjacent to the second direction is on the substrate orthographic overlap.
  • the orthographic projection of the power protruding portion 913 on the substrate is where the fourth data line pattern 984 is located.
  • the orthographic projections on the substrate overlap, and the orthographic projections of the power supply main body portion on the substrate overlap with the orthographic projections of the adjacent data line patterns along the first direction on the substrate.
  • the main part of the power supply includes a first part 911 and a second part 912, and the orthographic projection of the first part 911 on the substrate is the same as that along the first direction.
  • the orthographic projection of the data line main portion 9801 of the adjacent sixth data line pattern 986 on the substrate overlaps, and the orthographic projection of the second portion 912 on the substrate overlaps with the data line of the sixth data line pattern 986
  • the orthographic projections of the main body portion 9801 on the substrate do not overlap.
  • the overlapping area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, and the The overlapping area between the orthographic projection of the sixth data line pattern 986 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is close, thereby effectively reducing the fourth data line pattern 984 and the load difference between the sixth data line graph 986 .
  • FIG. 12 also shows that the fifth sub-pixel M5 also includes a fifth data line pattern 985 , the seventh sub-pixel M7 also includes a seventh data line pattern 987 , and the eighth sub-pixel further includes an eighth data line pattern 988 .
  • the overlapping area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, and the area along the The orthographic projection of the data line pattern adjacent to the fourth data line pattern 984 in the first direction on the substrate is close to the overlapping area between the orthographic projection of the functional pattern with a fixed potential on the substrate , thereby effectively reducing the load difference between the fourth data line pattern 984 and the adjacent data line patterns along the first direction.
  • the first sub-pixel M1 and the second sub-pixel M2 include: an initialization signal line pattern 94 , a second transistor T2 and a second conductive line connecting part 962;
  • At least a part of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used for transmitting initialization signals;
  • the first electrode of the second transistor T2 is electrically connected to the initialization signal line pattern 94 through the second conductive connection portion 962, and the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor ;
  • the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate; in the In the second sub-pixel M2, the orthographic projection of the second conductive connection portion 962 on the substrate does not overlap with the orthographic projection of the second data line pattern 982 on the substrate.
  • the third sub-pixel M3 and the fourth sub-pixel M4 include: an initialization signal line pattern 94 , a second transistor T2 and a second conductive connection portion 962 ;
  • At least a part of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used for transmitting initialization signals;
  • the first electrode of the second transistor T2 is electrically connected to the initialization signal line pattern 94 through the second conductive connection portion 962, and the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor ;
  • the orthographic projection of the second conductive connection portion 962 on the substrate does not overlap with the orthographic projection of the third data line pattern 983 on the substrate;
  • the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate.
  • the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 all include the initialization signal line pattern 94, the second transistor T2 and the second conductive connection portion 962 .
  • the orthographic projection of the first pole of the second transistor T2 on the substrate overlaps with the orthographic projection of the first end of the second conductive connection portion 962 on the substrate, and the second The first electrode of the transistor T2 is electrically connected to the first end of the second conductive connection portion 962 through a via hole located at the overlap.
  • the orthographic projection of the second end of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the initialization signal line pattern 94 on the substrate.
  • the terminals are electrically connected to the initialization signal line pattern 94 through vias located at the overlap.
  • the second pole of the second transistor T2 is electrically connected to the gate of the driving transistor, and in a reset period, the second transistor T2 can transmit the received initialization signal to the gate of the driving transistor, A gate reset of the drive transistor is achieved.
  • the initialization signal line pattern 94 Since the second conductive connection portion 962 is electrically connected to the initialization signal line pattern 94, the initialization signal line pattern 94 has a stable potential.
  • the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate;
  • the overlapping area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, and the third data line pattern on the substrate The overlapped area between the orthographic projection of 100 and the orthographic projection of the function pattern with a fixed potential on the substrate is closer, thereby further reducing the gap between the first data line pattern 981 and the third data line pattern load difference.
  • the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate, so that all The overlapping area between the orthographic projection of the second data line pattern 982 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, and the fourth data line pattern 984 on the substrate.
  • the overlapping area between the orthographic projection on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is closer, thereby further reducing the overlap between the second data line pattern 982 and the fourth data line pattern 984 load difference.
  • the overlapping area formed by the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the first portion 911 on the substrate has a first area; the first data The overlapping area formed by the orthographic projection of the line pattern 981 on the substrate and the orthographic projection of the power protruding portion 913 on the substrate has a second area, and the first data line pattern 981 on the substrate has a second area.
  • the orthographic projection and the orthographic projection of the second conductive connection portion 962 in the display substrate on the substrate have a third area; the sum of the second area and the third area is approximately the same as the first area.
  • the above-mentioned setting of the sum of the second area and the third area is approximately the same as the first area, so that the load of the first data line pattern 981 is substantially the same as the load of the third data line pattern, so that the It is good to improve the display uniformity of the display substrate.
  • the overlapping area formed by the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the first portion 911 on the substrate has a first area;
  • the fourth data The overlapping area formed by the orthographic projection of the line pattern 984 on the substrate and the orthographic projection of the power protruding portion 913 on the substrate has a second area, and the fourth data line pattern 984 on the substrate has a second area.
  • the orthographic projection and the orthographic projection of the second conductive connection portion 962 in the display substrate on the substrate have a third area; the sum of the second area and the third area is approximately the same as the first area.
  • the above-mentioned setting of the sum of the second area and the third area is approximately the same as the first area, so that the load of the second data line pattern 982 is substantially the same as the load of the fourth data line pattern 984, so that The display uniformity of the display substrate is better improved.
  • the power protruding portion 913 includes a third portion 9130 , a fourth portion 9131 and a fifth portion 9132 ; the third The portion 9130 extends along the second direction, and in the first sub-pixel M1, the orthographic projection of the third portion 9130 on the substrate intersects with the orthographic projection of the first data line pattern 981 on the substrate stack. In the fourth sub-pixel M4, the orthographic projection of the third portion 9130 on the substrate overlaps the orthographic projection of the fourth data line pattern 984 on the substrate.
  • the overlapping area of the first data line pattern 981 and the third portion 9130 can be controlled, and then the area of the overlapped area of the first data line pattern 981 and the third portion 9130 can be adjusted.
  • the load of the first data line pattern 981 In the third sub-pixel M3, by setting the length of the third portion 9130 along the second direction, the overlapping area of the fourth data line pattern 984 and the third portion 9130 can be controlled, thereby adjusting The load of the fourth data line pattern 984 .
  • the display substrate further includes an interlayer insulating layer ILD and a first flat layer PLN1 that are stacked in sequence along a direction away from the substrate;
  • a data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 are all located on the surface of the first flat layer PLN1 facing away from the substrate;
  • Both the power signal line pattern 91 and the power compensation pattern 97 are located on the surface of the interlayer insulating layer ILD facing away from the substrate.
  • the first data line pattern 981 , the second data line pattern 982 , the third data line pattern 983 and the fourth data line pattern 984 are all located behind the first flat layer PLN1 as described above. toward the surface of the substrate, so that the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 are all arranged on the same layer.
  • the first data line pattern 981 can be , the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 are formed in the same patterning process, thereby better simplifying the production process of the display substrate and saving production cost.
  • first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern 984 may form the second data line pattern in the display substrate source-drain metal layer. It should be noted that the second source-drain metal layer may also include other structures.
  • the first sub-pixel M1 , the second sub-pixel M2 , the third sub-pixel M3 and the fourth sub-pixel Both M4s include:
  • a power compensation pattern 97 at least a part of the power compensation pattern 97 extends along the first direction, the power signal line pattern 91 and the power compensation pattern 97 are located in the first data line pattern 981, the first data line pattern 981, the first Two data line patterns 982, the third data line pattern 983 and the fourth data line pattern 984 are close to one side of the substrate;
  • the power compensation patterns 97 are respectively electrically connected to the power signal line patterns 91 in the sub-pixels to which they belong, and the power signal line patterns 91 in adjacent sub-pixels along the first direction.
  • each of the sub-pixels further includes a power compensation pattern 97, and the power signal line pattern 91 and the power compensation pattern 97 are located in the first data line pattern 981, the second data line pattern 982, and the third data line pattern 981.
  • the line pattern 983 and the fourth data line pattern 984 are close to one side of the substrate; exemplarily, the first data line pattern 981, the second data line pattern 982, the third data line pattern 983 and the fourth data line pattern
  • the side of 984 close to the substrate is provided with an interlayer insulating layer ILD, and the power compensation pattern 97 and the power signal line pattern 91 are both located on the surface of the interlayer insulating layer ILD facing away from the substrate.
  • This arrangement enables the power signal line pattern 91 and the power compensation pattern 97 to be arranged on the same layer.
  • the power signal line pattern 91 and the power compensation pattern 97 are made of the same material, the power supply The signal line pattern 91 and the power compensation pattern 97 are formed in the same patterning process, thereby better simplifying the manufacturing process of the display substrate and saving the manufacturing cost.
  • the power signal line pattern 91 and the power compensation pattern 97 may form the first source-drain metal layer in the display substrate.
  • the first source-drain metal layer may also include other structures.
  • the power compensation pattern 97 corresponds to the power signal line pattern 91 in the sub-pixel to which it belongs, and the power signal line pattern 91 ′ in the adjacent sub-pixel along the first direction. electrical connection.
  • the power compensation pattern 97 and the two power signal line patterns 91 electrically connected to each other are formed into an integrated structure. It is worth noting that the integrated structure includes: the power compensation pattern 97 and the power signal line pattern 91 that are in contact with each other through one patterning process using the same material.
  • the power supply compensation pattern 97 is provided with the power supply signal line pattern 91 in the sub-pixel to which it belongs, and the adjacent sub-pixels located in the same row as the sub-pixel along the first direction.
  • the power supply signal line patterns 91' in the pixels are electrically connected; the power supply signal line patterns 91 included in each sub-pixel located in the same row are electrically connected together, so that the overall resistance of the power supply signal line patterns 91 is reduced, which is more conducive to Improve the uniformity of display substrate display.
  • the power supply compensation pattern 97 and the power supply signal line pattern 91 are both located on the surface of the interlayer insulating layer ILD of the display substrate facing away from the substrate, and the power supply signal The line pattern 91 and the power compensation pattern 97 are formed as the first source-drain metal layer in the display substrate, so that the power signal line pattern 91 and the power compensation pattern 97 can be formed in the same patterning process, thereby The manufacturing process of the display substrate is better simplified, and the manufacturing cost is saved.
  • the power compensation pattern 97 and the power signal line pattern 91 are made of the same source-drain metal material, the resistances of the power compensation pattern 97 and the power signal line pattern 91 are both smaller, so that the better The display uniformity of the display substrate is improved.
  • all the power signal line patterns 91 included are jointly formed into a mesh structure, which effectively improves the stability of the power signal transmitted by the power signal line pattern, and the power signal is used to provide the sub-pixels.
  • the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 include: The reset signal line pattern 95, the gate line pattern 92 and the light emission control signal line pattern 93 distributed in the second direction; at least part of the reset signal line pattern 95 extends along the first direction, and at least part of the gate line pattern 92 extending along the first direction, at least a part of the light-emitting control signal line pattern 93 extends along the first direction;
  • the orthographic projection of the power compensation pattern 97 on the substrate is located at Between the orthographic projection of the grid line pattern 92 on the substrate and the orthographic projection of the light emission control signal line pattern 93 on the substrate.
  • the sub-pixel further includes: a reset signal line pattern 95 , a gate line pattern 92 and a light emission control signal line pattern 93 distributed in sequence along the second direction.
  • the reset signal lines are used to transmit reset signals
  • the gate line patterns 92 are used to transmit scan signals.
  • the light-emitting control signal line pattern 93 is used for transmitting light-emitting control signals.
  • At least a part of the reset signal line pattern 95 extends along the first direction, and the reset signal line pattern 95 included in each sub-pixel located in the same row along the first direction is electrically connected in sequence to form an integrated structure.
  • At least a part of the gate line pattern 92 extends along the first direction, and the gate line patterns 92 included in each sub-pixel located in the same row along the first direction are sequentially electrically connected to form an integrated structure.
  • At least part of the light-emitting control signal line pattern 93 extends along the first direction, and the light-emitting control signal line pattern 93 included in each sub-pixel located in the same row along the first direction is electrically connected in sequence to form an integrated structure.
  • the specific layout positions of the power compensation pattern 97 are various, for example, in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 , the orthographic projection of the power compensation pattern 97 on the substrate does not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate, and the orthographic projection of the power compensation pattern 97 on the substrate Do not overlap with the orthographic projection of the grid line pattern 92 on the substrate, the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the light-emitting control signal line pattern 93 on the substrate Neither overlap.
  • the orthographic projection of the power supply compensation pattern 97 on the substrate the orthographic projection of the grid line pattern 92 on the substrate and the positive projection of the light-emitting control signal line pattern 93 on the substrate. between projections.
  • the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the grid line pattern 92 on the substrate is greater than the power supply
  • the power compensation pattern 97 is laid out in the above-mentioned manner, so that the power compensation pattern 97 and the reset signal line pattern 95 , the gate line pattern 92 and the light emission control signal line pattern 93 are all far away from each other , so as to avoid increasing the load of the reset signal line pattern 95 , the gate line pattern 92 and the light emission control signal line pattern 93 .
  • the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the grid line pattern 92 on the substrate is greater than a threshold; the power compensation pattern 97 The minimum distance between the orthographic projection on the substrate and the orthographic projection of the light emission control signal line pattern 93 on the substrate is greater than the threshold.
  • the threshold is 5 ⁇ m.
  • the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the grid line pattern 92 on the substrate is greater than 5 ⁇ m; the first power compensation pattern 97 is on the substrate and the minimum distance between the orthographic projection of the light-emitting control signal line pattern 93 on the substrate is greater than 5 ⁇ m.
  • the above setting method makes the power compensation pattern 97 and the reset signal line pattern 95, the gate line pattern 92 and the light-emitting control signal line pattern 93 all have a long distance, thereby avoiding increasing the reset signal line pattern 93.
  • the power supply signal line pattern 91 in each sub-pixel includes: a power supply main body part (including a first part 911 and a second part 912) and a power supply protruding part 913 that are electrically connected to each other;
  • the first end of the power compensation pattern 97 is electrically connected to the power protruding portion 913; the second end of the power compensation pattern 97 is connected to the main portion of the power supply in the adjacent sub-pixels along the first direction (ie, as shown in the figure).
  • the power supply main body part) of the power supply signal line pattern 91' in 8) is electrically connected.
  • At least part of the power protruding portion 913 extends along the second direction, and the second end of the power compensation pattern 97 is electrically connected to the middle portion of the power protruding portion 913 .
  • the above arrangement can shorten the length of the power compensation pattern 97 , thereby effectively reducing the layout difficulty of the power compensation pattern 97 .
  • At least part of the power protruding portion 913 extends along the second direction, and the power protruding portion 913 and the There are gaps 50 between the main body parts of the power supply.
  • the power protruding part 913 includes a third part 9130, a fourth part 9131 and a fifth part 9132; the third part 9130 is electrically connected to the power compensation pattern 97, and the third part 9130 is along the The fourth part 9131 is electrically connected with one end of the third part 9130 and the power supply main body part; the fifth part 9132 is respectively connected with the other end of the third part 9130 and the power supply main body part; The main body part of the power supply is electrically connected; there is a gap 50 between the third part 9130 and the main body part of the power supply.
  • the specific structures of the power supply protruding portion 913 are various.
  • the power supply protruding portion 913 includes the third portion 9130 , the fourth portion 9131 and the fifth portion 9132 which are integral structures. .
  • the fourth part 9131 is respectively electrically connected to one end of the third part 9130 and the main body of the power supply; the fifth part 9132 is respectively connected to the other end of the third part 9130 and the main body of the power supply Partial electrical connection can better ensure the connection performance between the protruding part 913 of the power supply and the main part of the power supply, and more effectively improve the display uniformity of the display substrate.
  • the display substrate may further include a fingerprint recognition module.
  • the fingerprint identification module is located on the side of the substrate facing away from the sub-pixel driving circuit.
  • the orthographic projection of the fingerprint recognition area of the fingerprint recognition module on the substrate overlaps the orthographic projection of the gap 50 on the substrate.
  • the gap 50 is arranged between the third part 9130 and the main body part of the power supply, which better improves the light transmittance of the display substrate. Therefore, when the display substrate provided in the above embodiment is compatible with the optical fingerprint identification technology, It can provide good conditions for the sensor to collect optical signals, thereby effectively improving the speed and accuracy of fingerprint identification.
  • the display substrate provided by the above-mentioned embodiment only the gap 50 is formed on the power signal line pattern 91, and the line width of the metal lines other than the power signal line pattern 91 is not narrowed or the light emission is compressed. Therefore, the display substrate provided by the above embodiments is not easy to have a negative impact on the performance of the display substrate while improving the resolution.
  • the first sub-pixel M1 , the second sub-pixel M2 , the third sub-pixel M3 and the fourth sub-pixel M4 all include: storage A capacitor Cst and a driving transistor, in each sub-pixel, the first plate Cst1 of the storage capacitor Cst is electrically connected to the gate of the driving transistor, and the second plate Cst2 of the storage capacitor Cst protrudes from the power supply Section 913 is electrically connected.
  • the orthographic projection of the second pole plate Cst2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the power protruding portion 913 on the substrate, and the second pole of the storage capacitor Cst The plate Cst2 is electrically connected to the power supply protrusion at this overlap.
  • the third portion 9130 includes a first sub-section 9130a and a second sub-section 9130b, the first sub-section 9130a is close to the fourth portion 9131, and the second sub-section 9130b is close to the fifth sub-section 9130b.
  • the width L1 of the first sub-portion 9130a is greater than the width L2 of the second sub-portion 9130b;
  • the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the first subsection 9130a on the substrate, and the second plate Cst2 of the storage capacitor Cst It is electrically connected to the first sub-portion 9130a through vias provided at the overlap.
  • the above arrangement enables a larger overlapping area between the second plate Cst2 of the storage capacitor Cst and the first sub-portion 9130a, which is more conducive to reducing the difficulty of layout of the via hole.
  • the mark 40 in FIG. 13a represents the substrate and some film layers (such as buffer layers, isolation layers, etc.) disposed on the substrate.
  • the first end D of the power compensation pattern 97 is set to have a first width, along the direction close to the first sub-surface.
  • the first width gradually increases in the direction of the power signal line pattern in the sub-pixel to which the pattern belongs (ie, the direction pointed by the dotted line with the arrow in FIG. 9 ).
  • the above arrangement not only enables better connection performance between the power compensation pattern 97 and the power signal line pattern 91, but also avoids the connection between the power compensation pattern 97 and the power signal line pattern 91.
  • a right-angle structure is formed where there is a risk of static electricity.
  • the first data line graph 981 , the second data line graph 982 , the third data line graph 983 and the fourth data line graph 984 Each includes a data line body portion 9801 and a data line protrusion portion 9802, the data line body portion 9801 extends along the second direction, and the data line protrusion portion 9802 protrudes from the data line body portion along the first direction 9801;
  • the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 all include a first conductive connection part 961 and a data writing transistor.
  • the data line protrusion 9802 and the first pole of the data writing transistor pass through the The first conductive connection portion 961 is electrically connected.
  • the first conductive connection portion 961 extends along the second direction.
  • the orthographic projection of the first end of the first conductive connection portion 961 on the substrate has a first overlapping area with the orthographic projection of the data line protrusion 9802 on the substrate, and the first conductive connection The first end of the portion 961 is electrically connected to the data line protrusion 9802 through a via hole provided in the first overlapping region.
  • the orthographic projection of the second end of the first conductive connection portion 961 on the substrate has a second overlapping area with the orthographic projection of the first electrode of the data writing transistor on the substrate.
  • the second end of a conductive connection portion 961 is electrically connected to the first electrode of the data writing transistor through a via hole disposed in the second overlapping region, and the first electrode of the data writing transistor passes through the first electrode of the data writing transistor.
  • a conductive connection portion 961 receives the data signal provided by the corresponding data line pattern.
  • the orthographic projection of the second portion 912 of the power signal line pattern 91 on the substrate and the first overlapping region are arranged along the first direction.
  • the distance between the first conductive connection portion 961 and the power signal line pattern 91 is relatively far.
  • the orthographic projection and the first overlapping area are arranged along the first direction, so that the second part 912 has enough layout space, so that under the condition that the second part 912 has a larger area, The layout difficulty of the display substrate is better reduced.
  • the first sub-pixel M1 , the second sub-pixel M2 , the third sub-pixel M3 and the fourth sub-pixel M4 are all It includes: a sixth transistor T6, and a third conductive connection part 963, a fourth conductive connection part 964 and a light-emitting element that are stacked in sequence along the direction away from the substrate; the light-emitting element includes an anode pattern (as shown in the No.
  • the first electrode of the sixth transistor T6 connected to the second pole of the driving transistor (ie, the third transistor T3); the second pole of the sixth transistor T6 is connected to the light-emitting device through the third conductive connection part 963 and the fourth conductive connection part 964 Components are electrically connected.
  • the gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93, and the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor.
  • the orthographic projection of the second pole of the sixth transistor T6 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have a third overlapping area
  • the sixth transistor T6 The second pole and the third conductive connection part 963 are electrically connected through the first via hole 61 provided in the third overlapping area; the orthographic projection of the third conductive connection part 963 on the substrate is the same as the
  • the orthographic projection of the fourth conductive connection part 964 on the substrate has a fourth overlapping area, and the third conductive connection part 963 and the fourth conductive connection part 964 pass through the space provided in the fourth overlapping area.
  • the second via hole 62 is electrically connected; the fourth conductive connection portion 964 is orthographically projected on the substrate and the anode pattern (eg: the first anode pattern 71 , the second anode pattern 72 , the third anode pattern 73 )
  • the orthographic projection on the substrate has a fifth overlapping area, and the fourth conductive connection portion 964 is electrically connected to the anode pattern through the third via hole 63 disposed in the fifth overlapping area.
  • the sixth transistor T6 transmits the driving signal output from the second electrode of the driving transistor to the anode of the light-emitting element through the third conductive connection portion 963 and the fourth conductive connection portion 964 in sequence.
  • the second pole of the sixth transistor T6 is arranged, and is electrically connected to the anode pattern through the third conductive connection part 963 and the fourth conductive connection part 964 in sequence, so as to better ensure The electrical connection performance between the second electrode of the sixth transistor T6 and the anode pattern is improved.
  • the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642 ; the orthographic projection of the solid portion 9641 on the substrate, and the orthographic projection of the hollow portion 9642 on the substrate at least partially overlap with the orthographic projection of the anode pattern on the substrate; the The orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the fifth data line pattern 985 on the substrate, and the orthographic projection of the anode pattern on the substrate overlaps with the orthographic projection of the anode pattern on the substrate. Orthographic projections of the seventh data line patterns 987 adjacent in direction on the substrate at least partially overlap.
  • the light-emitting element includes a fifth light-emitting element
  • the fifth light-emitting element includes a fifth anode pattern 75, a fifth light-emitting element, and a fifth anode pattern 75, a fifth light-emitting element, and a fifth light-emitting element that are sequentially stacked along a direction away from the substrate.
  • Functional layer and cathode Exemplarily, the fifth light-emitting element includes a blue light-emitting element.
  • the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth intersection. overlapping area; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the fifth anode pattern 75 on the substrate have the fifth overlapping area.
  • the orthographic projection of the first side portion of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the fifth data line pattern 985 in the sub-pixel to which it belongs.
  • the second side of the fifth anode pattern 75 is on the substrate
  • the orthographic projection of the hollow portion 9642 on the substrate overlaps with the orthographic projection of the hollow portion 9642 on the substrate; the first side portion and the second side portion are oppositely arranged along the first direction.
  • the hollowed-out portion 9642 is formed in a mouth shape, and the orthographic projection of the second side portion of the fifth anode pattern 75 on the substrate is opposite to the hollowed-out portion 9642 along the first direction.
  • the orthographic projections of both sides on the base overlap.
  • the orthographic projection of the second side of the fifth anode pattern 75 on the substrate is the same as the orthographic projection of the two sides of the hollow portion 9642 opposite along the second direction on the substrate. overlap.
  • first distance L3 there is a first distance L3 between two opposite sides of the hollow portion 9642 along the first direction, and the adjacent fifth data line patterns 985 of the two adjacent sub-pixels along the first direction are close to each other.
  • second distance L4 along the first direction between the seventh data line pattern 987, and the first distance L3 is equal to the second distance L4.
  • the above arrangement enables the fourth conductive connection portion 964 to compensate for the level difference generated by the fifth data line pattern 985 and the seventh data line pattern 987 below the fifth anode pattern 75, so that the fifth anode
  • the pattern 75 can be formed on a relatively flat surface, so that the fifth anode pattern 75 has a high flatness, which effectively reduces the color shift phenomenon of the display substrate during display.
  • the light-emitting element in some of the first sub-pixels M1 , includes a first light-emitting element, and the first light-emitting element The element includes a first anode pattern 71; the orthographic projection of the first anode pattern 71 on the substrate does not overlap with the orthographic projection of the first data line pattern 981 on the substrate.
  • the fourth conductive connection portion 964 includes a solid portion; the solid portion
  • the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate; the orthographic projection of the anode pattern on the substrate is where the first data line pattern 981 is located.
  • the orthographic projections on the substrate do not overlap, and the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the second data line pattern 982 on the substrate.
  • the light-emitting element includes a first light-emitting element
  • the first light-emitting element includes a first anode pattern 71, a first light-emitting element and a Functional layer and cathode.
  • the first light-emitting element includes a red light-emitting element.
  • the orthographic projection of the solid portion on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlap. area; the orthographic projection of the solid portion on the substrate and the orthographic projection of the first anode pattern 71 on the substrate have the fifth overlapping area.
  • the orthographic projection of the first anode pattern 71 on the substrate does not overlap with the orthographic projection of the first data line pattern 981 on the substrate.
  • the orthographic projection on the substrate does not overlap with the orthographic projection of the third data line pattern 983 adjacent along the first direction on the substrate, and the orthographic projection of the first anode pattern 71 on the substrate does not overlap.
  • the projection at least partially overlaps the orthographic projection of the second data line pattern 982 adjacent in the second direction on the substrate.
  • the orthographic projection of the first side portion of the first anode pattern 71 on the substrate overlaps with the orthographic projection of the second data line pattern 982 adjacent in the second direction on the substrate;
  • the first side portion and the second side portion are oppositely disposed along the first direction.
  • the above arrangement enables the second data line pattern 982 and the eighth data line pattern 988 to compensate for the level difference generated below the first anode pattern 71, so that the first anode pattern 71 can be formed on the On a relatively flat surface, the first anode pattern 71 has a high flatness, which effectively reduces the color shift phenomenon of the display substrate during display.
  • the light-emitting element in some of the second sub-pixels, includes a second light-emitting element, and the second light-emitting element A second anode pattern 72 is included; the orthographic projection of the second anode pattern 72 on the substrate overlaps the orthographic projection of the second data line pattern 982 on the substrate.
  • the fourth conductive connection portion 964 includes a solid portion and a hollow portion
  • the orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate at least partially overlap with the orthographic projection of the anode pattern on the substrate;
  • the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the second data line pattern 982 on the substrate.
  • the light-emitting element includes a second light-emitting element
  • the second light-emitting element includes a second anode pattern 72, a second light-emitting element, and a second anode pattern 72, a second light-emitting element and a Functional layer and cathode.
  • the second light-emitting element includes a blue light-emitting element.
  • the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth intersection. overlapping area; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the second anode pattern 72 on the substrate have the fifth overlapping area.
  • the orthographic projection of the second side portion of the second anode pattern 72 on the substrate is at least partially the orthographic projection of the second data line pattern 982 in the sub-pixel to which it belongs on the substrate Overlapping, the orthographic projection of the second side portion of the second anode pattern 72 on the substrate, the orthographic projection of the solid portion on the substrate, and the orthographic projection of the hollow portion on the substrate
  • the projections all overlap; the orthographic projection of the first side of the second anode pattern 72 on the substrate overlaps with the orthographic projection of the first data line pattern 981 adjacent along the second direction on the substrate , and overlaps the orthographic projection on the substrate of the third data line pattern 983 adjacent to the first data line pattern 981 along the second direction.
  • the first side portion and the second side portion are oppositely disposed along the first direction.
  • the hollowed-out portion 9642 is formed in a mouth shape, and the orthographic projection of the second side portion of the second anode pattern 72 on the substrate is opposite to the hollowed-out portion 9642 along the first direction.
  • the orthographic projections of both sides on the base overlap.
  • the orthographic projection of the second side portion of the second anode pattern 72 on the substrate is the same as the orthographic projection of the two opposite sides of the hollow portion 9642 along the second direction on the substrate. overlap.
  • the above arrangement enables the fourth conductive connection portion 964 and the second data line pattern 982 to compensate for the first data line pattern 981 and the extended portion of the third data line pattern 983 in the second data line pattern 983.
  • the level difference generated under the anode pattern 72 enables the second anode pattern 72 to be formed on a relatively flat surface, so that the second anode pattern 72 has a higher flatness, effectively reducing the display substrate during display. The resulting color cast.
  • the fourth conductive connection portion 964 includes a solid portion
  • the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the sixth data line pattern 986 on the substrate, and the orthographic projection of the anode pattern on the substrate overlaps with the orthographic projection of the anode pattern on the substrate.
  • the orthographic projections of the fourth data line patterns 984 adjacent in the first direction on the substrate at least partially overlap.
  • the light-emitting element includes a sixth light-emitting element
  • the sixth light-emitting element includes a sixth anode pattern 76, a sixth light-emitting element, and a sixth anode pattern 76 and a sixth light-emitting element that are stacked in sequence along a direction away from the substrate.
  • Functional layer and cathode Exemplarily, the sixth light-emitting element includes a red light-emitting element.
  • the orthographic projection of the solid portion on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlap. area; the orthographic projection of the solid portion on the substrate and the orthographic projection of the sixth anode pattern 76 on the substrate have the fifth overlapping area.
  • the orthographic projection of the first side of the sixth anode pattern 76 on the substrate at least partially overlaps the orthographic projection of the sixth data line pattern 986 on the substrate
  • the sixth The orthographic projection of the second side of the anode pattern 76 on the substrate at least partially overlaps the orthographic projection of the fourth data line pattern 984 adjacent along the first direction on the substrate.
  • the first side portion and the second side portion are oppositely disposed along the first direction.
  • the sixth data line pattern 986 and the fourth data line pattern 984 to compensate for the level difference generated below the sixth anode pattern 76, so that the sixth anode pattern 76 can be formed in the opposite direction.
  • the sixth anode pattern 76 On a flat surface, the sixth anode pattern 76 has a high flatness, which effectively reduces the color shift phenomenon of the display substrate during display.
  • the light-emitting element in some of the third sub-pixels M3 , includes a third light-emitting element, and the third light-emitting element
  • the element includes the third anode pattern 73;
  • the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;
  • the orthographic projection of the third anode pattern 73 on the substrate overlaps with the orthographic projection of the third data line pattern 983 on the substrate, and is adjacent to the third data line pattern 983 in the first direction
  • the orthographic projections of the data line graphics on the substrate overlap;
  • the orthographic projection of the third anode pattern 73 on the substrate overlaps with the orthographic projection of the solid portion 9641 on the substrate; and/or, the orthographic projection of the third anode pattern 73 on the substrate The projection overlaps the orthographic projection of the cutout 9642 on the substrate.
  • the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642 ;
  • the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate at least partially overlap with the orthographic projection of the anode pattern on the substrate;
  • the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the third data line pattern 983 on the substrate.
  • the light-emitting element includes a third light-emitting element
  • the third light-emitting element includes a third anode pattern 73, a third light-emitting element, and a third anode pattern 73 and a third light-emitting element that are sequentially stacked along a direction away from the substrate.
  • Functional layer and cathode Exemplarily, the third light-emitting element includes a green light-emitting element.
  • the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth Overlapping area; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third anode pattern 73 on the substrate have the fifth overlapping area.
  • the orthographic projection of the second side portion of the third anode pattern 73 on the substrate is at least partially the orthographic projection of the third data line pattern 983 in the sub-pixel to which it belongs on the substrate Overlapping, the orthographic projection of the second side of the third anode pattern 73 on the substrate at least partially intersects the orthographic projection of the first data line 981 adjacent to the first direction on the substrate stack; the orthographic projection of the first side portion of the third anode pattern 73 on the substrate, the orthographic projection of the solid portion on the substrate, and the orthographic projection of the hollow portion on the substrate Both overlap; the first side portion and the second side portion are oppositely arranged along the first direction.
  • the hollow portion 9642 is formed in a mouth shape, and the orthographic projection of the first side portion of the third anode pattern 73 on the substrate is opposite to the hollow portion 9642 along the first direction.
  • the orthographic projections of both sides on the base overlap.
  • the above arrangement enables the fourth conductive connection portion 964 to compensate for the step difference generated by the first data line pattern 981 and the third data line pattern 983 below the third anode pattern 73, so that the third The anode pattern 73 can be formed on a relatively flat surface, so that the fifth anode pattern 75 has a high flatness, which effectively reduces the color shift phenomenon of the display substrate during display.
  • the fourth conductive connection portion in the seventh sub-pixel M7 , includes a solid portion and a hollow portion;
  • the orthographic projection of the solid portion on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate, and the orthographic projection of the hollow portion on the substrate overlaps with the anode pattern on the substrate. the orthographic projections on the substrate do not overlap;
  • the orthographic projection of the anode pattern on the substrate at least partially overlaps the orthographic projection of the seventh data line pattern 987 on the substrate, and the orthographic projection of the anode pattern on the substrate overlaps with the orthographic projection of the anode pattern on the substrate.
  • the orthographic projections of the fifth data line patterns 985 adjacent in the first direction on the substrate at least partially overlap.
  • the light-emitting element includes a seventh light-emitting element
  • the seventh light-emitting element includes a seventh anode pattern 77 and a seventh light-emitting element that are sequentially stacked along a direction away from the substrate.
  • Functional layer and cathode Exemplarily, the seventh light-emitting element includes a green light-emitting element.
  • the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth intersection. overlapping area; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the seventh anode pattern 77 on the substrate have the fifth overlapping area.
  • the orthographic projection of the second side portion of the seventh anode pattern 77 on the substrate is at least partially the orthographic projection of the seventh data line pattern 987 in the sub-pixel to which it belongs on the substrate Overlapping, the orthographic projection of the second side of the seventh anode pattern 77 on the substrate, and the orthographic projection of the fifth data line pattern 985 adjacent along the first direction on the substrate at least partially overlapping; the orthographic projection of the first side portion of the seventh anode pattern 77 on the substrate overlaps the orthographic projection of the solid portion on the substrate; the first side portion and the third The two side portions are oppositely arranged along the first direction.
  • the above arrangement enables the fourth conductive connection portion 964 to compensate for the seventh data line pattern 987 and the level difference generated by the fifth data line pattern 985 below the seventh anode pattern 77, so that the seventh The anode pattern 77 can be formed on a relatively flat surface, so that the seventh anode pattern 77 has a high flatness, which effectively reduces the color shift phenomenon of the display substrate during display.
  • the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642 ;
  • the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate both at least partially overlap with the orthographic projection of the anode pattern on the substrate;
  • the orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the eighth data line pattern 988 on the substrate, and is adjacent to the sixth data line pattern 986 along the first direction.
  • the orthographic projections on the substrates do not overlap.
  • the light-emitting element includes an eighth light-emitting element
  • the eighth light-emitting element includes an eighth anode pattern 78 and an eighth light-emitting element that are sequentially stacked along a direction away from the substrate.
  • Functional layer and cathode Exemplarily, the eighth light-emitting element includes a green light-emitting element.
  • the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth Overlapping area; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the eighth anode pattern 78 on the substrate have the fifth overlapping area.
  • the orthographic projection of the second side of the eighth anode pattern 78 on the substrate at least partially intersects the orthographic projection of the seventh data line pattern 987 adjacent to it along the second direction on the substrate. stack; the orthographic projection of the second side of the eighth anode pattern 78 on the substrate, the fifth data line pattern 985 adjacent to the seventh data line pattern 987 along the first direction on the substrate
  • the orthographic projection at least partially overlaps; the orthographic projection of the first side portion of the eighth anode pattern 78 on the substrate overlaps with the orthographic projection of the solid portion on the substrate, and also overlaps with the hollow portion
  • the orthographic projections on the substrate overlap; the first side portion and the second side portion are opposed along the first direction.
  • the above arrangement enables the fourth conductive connection portion 964 to compensate for the level difference generated by the seventh data line pattern 987 and the fifth data line pattern 985 under the eighth anode pattern 78, so that the eighth The anode pattern 78 can be formed on a relatively flat surface, so that the eighth anode pattern 78 has a high flatness, which effectively reduces the color shift phenomenon of the display substrate during display.
  • the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642 ;
  • the orthographic projection of the solid portion 9641 on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate, and the orthographic projection of the hollow portion 9642 on the substrate overlaps with the anode pattern.
  • the orthographic projections of the graphics on the substrate do not overlap;
  • the orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the fourth data line pattern 984 on the substrate, and the orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the anode pattern on the substrate.
  • the orthographic projections of the second data line patterns 982 adjacent in one direction on the substrate do not overlap.
  • the light-emitting element includes a fourth light-emitting element
  • the fourth light-emitting element includes a fourth anode pattern 74 and a fourth light-emitting element that are sequentially stacked along a direction away from the substrate.
  • Functional layer and cathode Exemplarily, the fourth light-emitting element includes a green light-emitting element.
  • the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth intersection. overlapping area; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the fourth anode pattern 74 on the substrate have the fifth overlapping area.
  • the orthographic projection of the second side portion of the fourth anode pattern 74 on the substrate at least partially intersects the orthographic projection of the third data line pattern 983 adjacent to it along the second direction on the substrate. stack; the orthographic projection of the second side of the fourth anode pattern 74 on the substrate, the first data line pattern 981 adjacent to the third data line pattern 983 in the first direction on the substrate
  • the orthographic projections at least partially overlap; the orthographic projection of the first side portion of the fourth anode pattern 74 on the substrate overlaps the orthographic projection of the solid portion on the substrate, and overlaps with the hollow portion
  • the orthographic projections on the substrate do not overlap; the first side portion and the second side portion are disposed opposite to each other along the first direction.
  • the above arrangement enables the fourth conductive connection portion 964 to compensate for the level difference generated by the first data line pattern 981 and the third data line pattern 983 under the fourth anode pattern 74, so that the fourth The anode pattern 74 can be formed on a relatively flat surface, so that the fourth anode pattern 74 has a high flatness, which effectively reduces the color shift phenomenon of the display substrate during display.
  • FIG. 16 is a schematic diagram of the layout of the active layer in FIG. 12;
  • FIG. 17 is a schematic diagram of the layout of the first gate metal layer in FIG. 12;
  • FIG. 18 is a schematic diagram of the layout of the second gate metal layer in FIG. 12;
  • 12 is a schematic diagram of the layout of the first source-drain metal layer.
  • the active layer, the first gate metal layer, the second gate metal layer, and the first source-drain metal layer are sequentially stacked in a direction away from the substrate.
  • the first sub-pixel M1 , the second sub-pixel M2 , the third sub-pixel M3 and the fourth sub-pixel M4 are all It includes: a light-emitting element, a grid line pattern 92 and a light-emitting control signal line pattern 93; at least part of the grid line pattern 92 and at least part of the light-emitting control signal line pattern 93 both extend along the first direction;
  • the sub-pixel driving circuit further includes: a first transistor T1, a data write input transistor (ie fourth transistor T4), fifth transistor T5, sixth transistor T6, second reset transistor (ie seventh transistor T7) and storage capacitor Cst;
  • the gate of the drive transistor is electrically connected to the second electrode of the first transistor T1, the first electrode of the drive transistor is electrically connected to the second electrode of the fifth transistor T5, and the second electrode of the drive transistor is electrically connected to the second electrode of the fifth transistor T5.
  • the pole is electrically connected to the first pole of the first transistor T1;
  • the gate of the first transistor T1 is electrically connected to the gate line pattern 92;
  • the gate of the data writing transistor is electrically connected to the gate line pattern 92, the first electrode of the data writing transistor is electrically connected to the data line pattern in the sub-pixel to which it belongs, and the second electrode of the data writing transistor The pole is electrically connected to the first pole of the driving transistor;
  • the gate of the fifth transistor T5 is electrically connected to the light-emitting control signal line pattern 93, and the first pole of the fifth transistor T5 is electrically connected to the power supply signal line pattern 91;
  • the gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93, the first pole of the sixth transistor T6 is electrically connected to the second pole of the driving transistor, and the sixth transistor T6 is electrically connected to the second pole of the driving transistor.
  • the second pole is electrically connected to the anode pattern included in the light-emitting element;
  • the gate of the second reset transistor is electrically connected to the reset signal line pattern 95' in the next sub-pixel adjacent along the second direction, and the first pole of the second reset transistor is connected to the second direction along the second direction.
  • the initialization signal line pattern 94' in the adjacent next sub-pixel is electrically connected, and the second pole of the second reset transistor is electrically connected to the anode pattern;
  • the first plate of the storage capacitor is multiplexed as the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the power signal line pattern 91 .
  • each sub-pixel in the display substrate includes a sub-pixel driving circuit
  • each sub-pixel driving circuit includes: a first transistor T1, a second transistor T2, a driving transistor (such as a third transistor), a data writing transistor (such as a fourth transistor), fifth transistor T5, sixth transistor T6, seventh transistor T7, storage capacitor Cst, first conductive connection part 961, second conductive connection part 962, third conductive connection part 963, fourth conductive connection part 964 and the fifth conductive connection 965 and so on.
  • the plurality of sub-pixels can be divided into a plurality of rows of sub-pixels arranged in sequence along the second direction, and a plurality of columns of sub-pixels arranged in sequence along the first direction, and the sub-pixels located in the same row include the initialization
  • the signal line patterns 94 are electrically connected in sequence to form an integrated structure; the gate line patterns 92 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure; the light-emitting control signal lines included in the sub-pixels located in the same row
  • the patterns 93 are electrically connected in sequence to form an integrated structure;
  • the reset signal line patterns 95 included in the sub-pixels located in the same row are electrically connected in sequence to form an integrated structure;
  • the first data line patterns 981 included in the sub-pixels located in the same column are sequentially electrically connected to form an integrated structure;
  • the second data line patterns 982 included in the sub-pixels located in the same column are electrically connected in turn to form an integrated structure
  • the sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor.
  • the transistors included in the sub-pixel driving circuit are all P-type transistors, the first electrode of each transistor includes a source electrode, and the second electrode of each transistor includes a drain electrode.
  • the first transistor T1 is a double gate structure, the gate 201g of the first transistor T1 is electrically connected to the gate line pattern 92, the source S1 of the first transistor T1 is electrically connected to the drain D3 of the third transistor T3 (ie, the driving transistor), The drain D1 of the first transistor T1 is electrically connected to the gate 203g of the third transistor T3.
  • the second transistor T2 (ie, the first reset transistor) has a double-gate structure, the gate 202g of the second transistor T2 is electrically connected to the reset signal line pattern 95, and the source S2 of the second transistor T2 is connected to the initialization signal line pattern 94 is electrically connected, and the drain D2 of the second transistor T2 is electrically connected to the gate 203g of the third transistor T3.
  • the gate electrode 204g of the fourth transistor T4 (ie, the data writing transistor) is electrically connected to the gate line pattern 92, and the source electrode S4 of the fourth transistor T4 is electrically connected to the first data line pattern 981 or the second data line pattern 982, The drain D4 of the fourth transistor T4 is electrically connected to the source S3 of the third transistor T3.
  • the gate 205g of the fifth transistor T5 is electrically connected to the light-emitting control signal line pattern 93, the source S5 of the fifth transistor T5 is electrically connected to the power supply signal line pattern 91, and the drain D5 of the fifth transistor T5 is electrically connected to the source of the third transistor T3 Pole S3 electrical connection.
  • the gate 206g of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93, the source S6 of the sixth transistor T6 is electrically connected to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is electrically connected to the light-emitting element EL anode electrical connection.
  • the gate 207g of the seventh transistor T7 (ie, the second reset transistor) is electrically connected to the reset signal line pattern 95' in the next sub-pixel adjacent along the second direction, and the drain D7 of the seventh transistor T7 is connected to the corresponding reset signal line pattern 95'.
  • the anode of the light-emitting element EL is electrically connected, and the source S7 of the seventh transistor T7 is electrically connected to the initialization signal line pattern 94' in the next sub-pixel adjacent along the second direction.
  • the first plate Cst1 of the storage capacitor Cst is multiplexed into the gate 203g of the third transistor T3 , and the second plate Cst2 of the storage capacitor Cst is electrically connected to the power signal line pattern 91 .
  • each working cycle includes a reset period P1 , a write compensation period P2 and a light-emitting period P3 .
  • E1 represents the light-emitting control signal transmitted on the light-emitting control signal line pattern 93 in the current sub-pixel
  • R1 represents the reset signal transmitted on the reset signal line pattern 95 in the current sub-pixel
  • D1 represents the target in the current sub-pixel
  • G1 represents the gate scan signal transmitted on the gate line pattern 92 in the current sub-pixel
  • R1' represents the reset in the next sub-pixel adjacent to the current sub-pixel along the second direction
  • the reset signal transmitted on the signal line pattern 95' is the reset period P1 , a write compensation period P2 and a light-emitting period P3 .
  • E1 represents the light-emitting control signal transmitted on the light-emitting control signal line pattern 93 in the current sub-pixel
  • R1 represents the reset signal transmitted on the reset signal line pattern 95 in the current sub-pixel
  • D1 represents the target in the current
  • the reset signal input from the reset signal line pattern 95 is at an active level
  • the second transistor T2 is turned on
  • the initialization signal transmitted from the initialization signal line pattern 94 is input to the third transistor T3
  • the gate 203g of the third transistor T3 is reset, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared, and the gate 203g of the third transistor T3 is reset.
  • the reset signal input from the reset signal line pattern 95 is at an inactive level
  • the second transistor T2 is turned off
  • the gate scan signal input from the gate line pattern 92 is at an active level
  • the first transistor T1 is controlled and the fourth transistor T4 is turned on
  • the target data line pattern writes a data signal, and is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4, and at the same time, the first transistor T1 and the fourth transistor T4 are turned on
  • the third transistor T3 is formed into a diode structure, so the first transistor T1, the third transistor T3 and the fourth transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the compensation time is long enough, it can be controlled
  • the potential of the gate 203g of the third transistor T3 finally reaches Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the reset signal input from the reset signal line pattern 95' is at an active level
  • the seventh transistor T7 is controlled to be turned on
  • the initialization signal transmitted from the initialization signal line pattern 94' is input to the anode of the light-emitting element EL , control the light-emitting element EL not to emit light.
  • the light-emitting control signal written in the light-emitting control signal line pattern 93 is at an active level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power supply signal transmitted by the power supply signal line pattern 91 is input to the third The source S3 of the transistor T3, and the gate 203g of the third transistor T3 is kept at Vdata+Vth, so that the third transistor T3 is turned on, the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, and VDD is the power supply
  • the voltage value corresponding to the signal, the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL, and drives the corresponding light-emitting element EL to emit light.
  • each film layer corresponding to the sub-pixels is as follows:
  • the active film layer is used to form the channel region (the part covered by the gate of each transistor), the source (eg: S1-S7) and the drain (eg, S1-S7) of each transistor in the sub-pixel driving circuit : D1 ⁇ D7), the active film layers corresponding to the source and drain electrodes have better conductivity than the active film layers corresponding to the channel region due to doping; the active film layers can be made of amorphous silicon, polysilicon, oxide Material semiconductor materials, etc. It should be noted that the above-mentioned source and drain electrodes may be doped with n-type impurities or p-type impurities.
  • the first gate metal layer is used to form gates (eg, 201g to 207g ) of the transistors in the sub-pixel driving circuit, as well as the gate line pattern 92 , the light-emitting control signal line pattern 93 , and the reset pattern included in the sub-pixel.
  • the gate 203g of the third transistor T3 in each sub-pixel driving circuit is multiplexed as the first plate Cst1 of the second storage capacitor Cst in the sub-pixel driving circuit.
  • the second gate metal layer is used to form the second electrode plate Cst2 of the second storage capacitor Cst, the initialization signal line pattern 94 included in the sub-pixel, and the shield pattern 80 .
  • the first source-drain metal layer is used to form the power signal line pattern 91 included in the sub-pixel, the power compensation pattern and some conductive connection parts.
  • the second source-drain metal layer is used to form the first data line pattern 981 , the second data line pattern 982 and some conductive connection parts included in the sub-pixel.
  • the gate 204g of the fourth transistor T4 in the second direction, the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1 and the gate 202g of the second transistor T2 are all located at On the first side of the gate of the driving transistor (ie, the gate 203g of the third transistor T3), the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all located at the gate of the driving transistor.
  • the second side of the gate Exemplarily, the first side and the second side of the gate of the driving transistor are opposite sides along the second direction, and further, the first side of the gate of the driving transistor may be the upper side of the gate of the driving transistor.
  • the second side of the gate of the driving transistor may be the lower side of the gate of the driving transistor.
  • the lower side for example, the side of the display substrate used to bind the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor that is closer to the IC.
  • the upper side is the opposite side to the lower side, eg the side of the gate of the drive transistor that is further away from the IC.
  • the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, the gate 201g of the first transistor T1 and the gate of the sixth transistor T6
  • the poles 206g are all located on the fourth side of the gate of the drive transistor.
  • the third side and the fourth side of the gate of the driving transistor are opposite sides along the first direction; further, the third side of the gate of the driving transistor may be the right side of the gate of the driving transistor, The fourth side of the gate of the driving transistor may be the left side of the gate of the driving transistor.
  • the second data line pattern 982 is located on the right side of the gate of the driving transistor, and the first data line pattern 981 is located on the left side of the gate of the driving transistor.
  • Embodiments of the present disclosure further provide a display device including the display substrate provided by the above embodiments.
  • the shielding The pattern 80 shields the interference to the first pole of the first reset transistor due to the transition of the data signal, thereby avoiding the influence of the transition of the data signal on the initialization signal transmitted on the initialization signal line pattern 94, thereby effectively improving the display substrate. display effect.
  • the above-mentioned shielding pattern 80 is electrically connected to the power signal line pattern 91, so that the shielding pattern 80 has the same stable potential as the power signal transmitted by the power signal line pattern 91, which is not only beneficial to the sub-pixels
  • the driving circuit is in a stable working state, which better ensures the shielding effect of the shielding pattern 80 .
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, and can achieve higher picture display quality.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer.
  • An embodiment of the present disclosure also provides a method for fabricating a display substrate, including: fabricating a plurality of sub-pixels distributed in an array on a substrate, and the step of fabricating the sub-pixels specifically includes:
  • a sub-pixel drive circuit is fabricated, the sub-pixel drive circuit includes a drive transistor and a first reset transistor, the gate of the first reset transistor is electrically connected to the reset signal line pattern 95, and the first reset transistor The pole is electrically connected to the initialization signal line pattern 94, and the second pole of the first reset transistor is electrically connected to the gate of the drive transistor;
  • a shield pattern 80 is made, the shield pattern 80 is electrically connected to the power signal line pattern 91, and the orthographic projection of the shield pattern 80 on the substrate and the first pole of the first reset transistor are on the substrate orthographic overlap.
  • the orthographic projection of the shielding pattern 80 on the substrate is set to be orthogonal to the orthographic projection of the first pole of the first reset transistor on the substrate overlapping, so that the shielding pattern 80 shields the interference to the first pole of the first reset transistor due to the transition of the data signal, thereby avoiding the influence of the transition of the data signal on the initialization signal transmitted on the initialization signal line pattern 94, The display effect of the display substrate is effectively improved.
  • the above-mentioned shielding pattern 80 is electrically connected to the power signal line pattern 91, so that the shielding pattern 80 has the same stable potential as the power signal transmitted by the power signal line pattern 91, which is not only beneficial to the sub-pixels
  • the driving circuit is in a stable working state, which better ensures the shielding effect of the shielding pattern 80 .

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Abstract

本公开提供一种显示基板及其制作方法、显示装置，所述显示基板中，子像素驱动电路包括驱动晶体管和第一复位晶体管，第一复位晶体管的栅极与复位信号线图形电连，第一复位晶体管的第一极与初始化信号线图形电连，第一复位晶体管的第二极与驱动晶体管的栅极电连；屏蔽图形与电源信号线图形电连，屏蔽图形在基底上的正投影与第一复位晶体管的第一极在基底上的正投影交叠。

Description

一种显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
AMOLED(Active-matrix Organic Light-Emitting Diode，有源矩阵有机发光二极管)显示器件具有自发光、超薄、反应速度快、对比度高、视角广等诸多优点，是目前受到广泛关注的一种显示器件。这种AMOLED显示器件包括多个像素驱动电路和多个发光元件，像素驱动电路用于驱动对应的发光元件发光，从而实现AMOLED显示器件的显示功能。
像素驱动电路在驱动发光元件发光时，包括低频驱动方式和高频驱动方式，采用低频驱动方式驱动发光元件时，每行像素驱动电路控制像素的数据写入时间较长，采用高频驱动方式驱动发光元件时，会压缩每行像素的数据写入时间，使得每行像素驱动电路控制像素的数据写入时间较短。
发明内容
本公开的目的在于提供一种显示基板及其制作方法、显示装置。
本公开的第一方面提供一种显示基板，一种显示基板，包括：基底和阵列分布在所述基底上的多个子像素，所述子像素包括：
初始化信号线图形，所述初始化信号线图形的至少部分沿第一方向延伸；
复位信号线图形，所述复位信号线图形的至少部分沿所述第一方向延伸；
电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
子像素驱动电路，所述子像素驱动电路包括驱动晶体管和第一复位晶体 管，所述第一复位晶体管的栅极与所述复位信号线图形电连，所述第一复位晶体管的第一极与所述初始化信号线图形电连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连；
屏蔽图形，所述屏蔽图形与所述电源信号线图形电连，所述屏蔽图形在所述基底上的正投影与所述第一复位晶体管的第一极在所述基底上的正投影交叠。
可选的，所述屏蔽图形在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影不交叠。
可选的，所述屏蔽图形在所述基底上的正投影与所述第一复位晶体管的第二极在所述基底上的正投影交叠。
可选的，所述多个子像素包括：
沿第二方向设置的第一子像素和第二子像素，所述第一子像素包括第一数据线图形，所述第二子像素包括第二数据线图形，所述第一数据线图形的至少部分和所述第二数据线图形的至少部分均沿第二方向延伸，所述第一数据线图形位于沿所述第二方向延伸的同一列所述第一子像素的第一侧，所述第二数据线图形位于沿所述第二方向延伸的同一列所述第二子像素的第二侧，所述第一侧与所述第二侧沿第一方向相对，所述第一方向与所述第二方向相交；
沿第二方向设置的第三子像素和第四子像素，沿所述第一方向，所述第三子像素与所述第一子像素位于同一行，所述第四子像素与所述第二子像素位于同一行；所述第三子像素包括第三数据线图形，所述第四子像素包括第四数据线图形，所述第三数据线图形的至少部分和所述第四数据线图形的至少部分均沿第二方向延伸，所述第三数据线图形位于沿所述第二方向延伸的同一列第三子像素的第二侧，所述第四数据线图形位于沿所述第二方向延伸的同一列第四子像素的第一侧。
可选的，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括第一导电连接部和第五导电连接部；
在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中：
所述子像素驱动电路均包括数据写入晶体管；
所述第一导电连接部分别与对应的数据线图形和数据写入晶体管的第一极电连；所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连；
所述第一复位晶体管的第二极通过所述第五导电连接部与所述驱动晶体管的栅极电连；
所述屏蔽图形在所述基底上的正投影与所述第一导电连接部在所述基底上的正投影至少部分交叠。
可选的，所述屏蔽图形的至少部分在所述基底上的正投影，位于所述第一导电连接部在所述基底上的正投影与所述第五导电连接部在所述基底上的正投影之间。
可选的，在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中：
所述子像素驱动电路均包括第一晶体管，所述第一晶体管的第一极与所述驱动晶体管的第二极电连，所述第一晶体管的第二极与所述驱动晶体管的栅极电连；
所述第一晶体管的有源图形包括间隔设置的两个半导体部分，以及分别连接所述两个半导体部分的第一导体部分；
所述屏蔽图形在所述基底上的投影还与所述第一导体部分在所述基底上的正投影至少部分交叠。
可选的，沿垂直于所述基底的方向上，所述屏蔽图形位于所述第一复位晶体管的第一极与所述第一导电连接部之间。
可选的，在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述电源信号线图形均包括：相电连的电源主体部分和电源突出部分；
在所述第一子像素中，所述电源突出部分在所述基底上的正投影与所述第一数据线图形在所述基底上的正投影交叠，所述电源主体部分在所述基底上的正投影与沿所述第一方向相邻的数据线图形在所述基底上的正投影至少部分交叠。
可选的，在所述第二子像素中，所述电源突出部分在所述基底上的正投 影与所述第二数据线图形在所述基底上的正投影不交叠。
可选的，在所述第三子像素中，所述电源突出部分在所述基底上的正投影与所述第三数据线图形在所述基底上的正投影不交叠。
可选的，在所述第四子像素中，所述电源突出部分在所述基底上的正投影与所述第四数据线图形在所述基底上的正投影交叠，所述电源主体部分在所述基底上的正投影与沿所述第一方向相邻的数据线图形在所述基底上的正投影交叠。
可选的，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括：
电源补偿图形，所述电源补偿图形的至少部分沿所述第一方向延伸，所述电源信号线图形和所述电源补偿图形均位于所述第一数据线图形、所述第二数据线图形、所述第三数据线图形和所述第四数据线图形靠近所述基底的一侧；
所述电源补偿图形分别与其所属子像素中的电源信号线图形，以及沿所述第一方向相邻子像素中的电源信号线图形电连。
可选的，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括：沿第二方向分布的所述复位信号线图形、栅线图形和发光控制信号线图形；所述栅线图形的至少部分沿所述第一方向延伸，所述发光控制信号线图形的至少部分沿第一方向延伸；
在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述电源补偿图形在所述基底上的正投影，位于所述栅线图形在所述基底上的正投影与所述发光控制信号线图形在所述基底上的正投影之间。
可选的，在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述电源信号线图形均包括：相电连的电源主体部分和电源突出部分，所述电源突出部分与所述电源主体部分之间具有间隙；
所述电源补偿图形的第一端与其所属子像素中的所述电源突出部分电连；所述电源补偿图形的第二端与沿所述第一方向相邻子像素中的电源主体部分电连。
可选的，所述第一子像素、所述第二子像素、所述第三子像素和所述 第四子像素均包括：第六晶体管，以及沿远离所述基底的方向层叠设置的第三导电连接部、第四导电连接部和发光元件；所述发光元件包括阳极图形；在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述第六晶体管的第一极与所述驱动晶体管的第二极连接；所述第六晶体管的第二极通过所述第三导电连接部、第四导电连接部和所述发光元件电连。
可选的，在部分所述第一子像素中，所述发光元件包括第一发光元件，所述第一发光元件包括第一阳极图形；
所述第一阳极图形在所述基底上的正投影与所述第一数据线图形在所述基底上的正投影不交叠。
可选的，在部分所述第三子像素中，所述发光元件包括第三发光元件，所述第三发光元件包括第三阳极图形；
所述第四导电连接部包括实体部分和镂空部分；
所述第三阳极图形在所述基底上的正投影与所述第三数据线图形在所述基底上的正投影交叠，且与该第三数据线图形沿第一方向相邻的数据线图形在所述基底上的正投影交叠；
所述第三阳极图形在所述基底上的正投影与所述实体部分在所述基底上的正投影交叠；和/或，所述第三阳极图形在所述基底上的正投影与所述镂空部分在所述基底上的正投影交叠。
可选的，在部分所述第二子像素中，所述发光元件包括第二发光元件，所述第二发光元件包括第二阳极图形；
所述第二阳极图形在所述基底上的正投影，与所述第二数据线图形在所述基底上的正投影交叠。
可选的，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括：发光元件、栅线图形和发光控制信号线图形；所述栅线图形的至少部分和所述发光控制信号线图形的至少部分均沿所述第一方向延伸；
在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述子像素驱动电路还包括：第一晶体管、数据写入晶体管、第五晶体管、第六晶体管、第二复位晶体管和存储电容；
所述驱动晶体管的栅极与所述第一晶体管的第二极电连，所述驱动晶体管的第一极与所述第五晶体管的第二极电连，所述驱动晶体管的第二极与所述第一晶体管的第一极电连；
所述第一晶体管的栅极与所述栅线图形电连；
所述数据写入晶体管的栅极与所述栅线图形电连，所述数据写入晶体管的第一极与其所属子像素中的数据线图形电连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连；
所述第五晶体管的栅极与所述发光控制信号线图形电连，所述第五晶体管的第一极与所述电源信号线图形电连；
所述第六晶体管的栅极与所述发光控制信号线图形电连，所述第六晶体管的第一极与所述驱动晶体管的第二极电连，所述第六晶体管的第二极与所述发光元件包括的阳极图形电连；
第二复位晶体管的栅极与沿所述第二方向相邻的下一个子像素中的复位信号线图形电连，所述第二复位晶体管的第一极与沿所述第二方向相邻的下一个子像素中的所述初始化信号线图形电连，所述第二复位晶体管的第二极与所述阳极图形电连；
所述存储电容的第一极板复用为所述驱动晶体管的栅极，所述存储电容的第二极板与所述电源信号线图形电连。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示基板的制作方法，包括：在基底上制作阵列分布的多个子像素，制作所述子像素的步骤具体包括：
制作初始化信号线图形，所述初始化信号线图形的至少部分沿第一方向延伸；
制作复位信号线图形，所述复位信号线图形的至少部分沿所述第一方向延伸；
制作电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
制作子像素驱动电路，所述子像素驱动电路包括驱动晶体管和第一复位晶体管，所述第一复位晶体管的栅极与所述复位信号线图形电连，所述第一复位晶体管的第一极与所述初始化信号线图形电连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连；
制作屏蔽图形，所述屏蔽图形与所述电源信号线图形电连，所述屏蔽图形在所述基底上的正投影与所述第一复位晶体管的第一极在所述基底上的正投影交叠。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1a为现有技术中子像素布局示意图；
图1b为图1中有源层的布局示意图；
图1c为图1中第一栅金属层的布局示意图；
图1d为图1中第二栅金属层的布局示意图；
图1e为图1中源漏金属层的布局示意图；
图2为本公开实施例提供的子像素驱动电路的电路图；
图3为本公开实施例提供的子像素驱动电路的工作时序图；
图4为本公开实施例提供的子像素的第一布局示意图；
图5为本公开实施例提供的子像素的第二布局示意图；
图6为图5中有源层和第一栅金属层的布局示意图；
图7为图5中第二栅金属层的布局示意图；
图8为图5中第一源漏金属层的布局示意图；
图9为图5中电源补偿图形的结构示意图；
图10为图5中第一源漏金属层和第二源漏金属层的布局示意图；
图11为图5中第二源漏金属层的布局示意图；
图12为八个子像素的布局示意图；
图13a为图12中沿A1A2方向的截面示意图；
图13b为图12中沿B1B2方向的截面示意图；
图13c为图12中沿C1C2方向的截面示意图；
图13d为图12中沿D1D2方向的截面示意图；
图14为图12中两层源漏金属层和阳极层的布局示意图；
图15为图12中第二源漏金属层和阳极层的布局示意图；
图16为图12中有源层的布局示意图；
图17为图12中第一栅金属层的布局示意图；
图18为图12中第二栅金属层的布局示意图；
图19为图12中第一源漏金属层的布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
AMOLED显示面板的结构包括：基底，设置在基底上的多个子像素驱动电路，以及设置在所述子像素驱动电路背向所述基底的一侧的多个发光元件，所述发光元件与所述子像素驱动电路一一对应，所述子像素驱动电路用于驱动对应的发光元件发光，从而实现显示面板的显示功能。
相关技术中，所述子像素驱动电路一般包括多个薄膜晶体管，如图1a所示，图1a中示出了所述子像素驱动电路包括7个薄膜晶体管Q1～Q7时，该7个薄膜晶体管的具体布局方式，按照这种方式布局时，所述子像素驱动电路包括如图1b所示的有源层，如图1c所示的第一金属层，如图1d所示的第二金属层，以及如图1e所示的第三金属层；所述有源层包括用于形成各薄膜晶体管的沟道区的有源图形(如图1b中的虚线框内的部分)，以及与所述有源图形电连，具有导电性能的掺杂有源图形(如图1b中的虚线框外的部分)；所述第一金属层包括各薄膜晶体管的栅极，所述栅极电连的扫描信号线GATE，所述子像素驱动电路中存储电容的一个极板CE1，复位信号线RST，以及发光控制信号线EM；所述第二金属层包括初始化信号线VINT，以及所 述子像素驱动电路中存储电容的另一个电极板CE2；所述第三金属层包括数据线DATA，电源信号线VDD，以及一些导电连接部(如标记341～343)。
值得注意，如图1所示，在布局子像素驱动电路时，为了实现异层设置的功能图形之间的电连，还可设置一些过孔(如标记：381～388)。
相关技术中的子像素驱动电路在实现高频驱动时，由于每行像素驱动电路控制像素的数据写入时间较短，容易导致每行像素出现数据写入时间不足的问题。
请参阅图2～图4，本公开提供一种显示基板，包括：基底和阵列分布在所述基底上的多个子像素，所述多个子像素能够划分为沿所述第二方向依次排列的多行子像素，以及沿所述第一方向依次排列的多列子像素，每个子像素均包括：发光元件、初始化信号线图形94、复位信号线图形95、栅线图形92和发光控制信号线图形93。
所述多个子像素包括：
沿第二方向设置的第一子像素和第二子像素，所述第一子像素包括第一数据线图形981，所述第二子像素包括第二数据线图形982，所述第一数据线图形981的至少部分和所述第二数据线图形982的至少部分均沿第二方向延伸，所述第一数据线图形981位于沿所述第二方向延伸的同一列所述第一子像素的第一侧，所述第二数据线图形982位于沿所述第二方向延伸的同一列所述第二子像素的第二侧，所述第一侧与所述第二侧沿第一方向相对，所述第一方向与所述第二方向相交。示例性的，所述第一侧为图4中的右侧，所述第二侧为图4中的左侧。
所述第一子像素和所述第二子像素均包括子像素驱动电路，所述子像素驱动电路包括驱动晶体管(即第三晶体管T3)和数据写入晶体管(即第四晶体管T4)，在所述第一子像素中，所述数据写入晶体管的第一极与所述第一数据线图形981电连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连；在所述第二子像素中，所述数据写入晶体管的第一极与所述第二数据线图形982电连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连。
根据上述显示基板的具体结构可知，本公开提供的显示基板中，在沿所 述第二方向延伸的同一列子像素中，相邻子像素中的其中一个子像素包括的数据写入晶体管的第一极与所述第一数据线图形981电连，相邻子像素中的另一个子像素包括的数据写入晶体管的第一极与所述第二数据线图形982电连。本公开提供的显示基板中，通过设置在同一列子像素中，相邻子像素中数据写入晶体管电连的数据线图形不同，实现了在同一列子像素中，相邻的子像素由不同的数据线图形提供数据信号，保证了每个子像素均具有足够的数据信号写入时间，从而解决了显示基板在高频显示时，每行子像素的数据信号写入时间不足的问题。
但是上述显示基板中，在各子像素中，当数据线图形(如第二数据线图形982)传输的数据信号发生变化时，容易对第一复位晶体管(如第二晶体管T2)的第一极产生干扰。又由于所述第一复位晶体管的第一极与初始化信号线图形94电连，使得数据线图形传输的数据信号发生变化，会通过所述第一复位晶体管的第一极，对初始化信号线图形94上传输的初始化信号产生影响，从而影响显示基板的显示效果。
请参阅图5～图8，本公开实施例提供一种显示基板，包括：基底和阵列分布在所述基底上的多个子像素，所述子像素包括：
初始化信号线图形94，所述初始化信号线图形94的至少部分沿第一方向延伸；
复位信号线图形59，所述复位信号线图形95的至少部分沿所述第一方向延伸；
电源信号线图形91，所述电源信号线图形91的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
子像素驱动电路，所述子像素驱动电路包括驱动晶体管(即第三晶体管T3)和第一复位晶体管(即第二晶体管T2)，所述第一复位晶体管的栅极与所述复位信号线图形95电连，所述第一复位晶体管的第一极与所述初始化信号线图形94电连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连；
屏蔽图形80，所述屏蔽图形80与所述电源信号线图形91电连，所述屏蔽图形80在所述基底上的正投影与所述第一复位晶体管的第一极在所述基 底上的正投影交叠。
具体地，所述显示基板包括阵列分布在基底上的多个子像素，所述多个子像素能够划分为多行子像素和多列子像素。所述多行子像素沿第二方向排布，每行子像素均包括沿第一方向依次排列的多个所述子像素。所述多列子像素沿第一方向排布，每列子像素均包括沿第二方向依次排列的多个所述子像素。
示例性的，所述第一方向包括水平方向，所述第二方向包括竖直方向。
示例性的，每个子像素均包括数据线图形，所述数据线图形的至少部分沿所述第二方向延伸。位于同一列子像素中的各子像素包括的数据线图形依次电连，能够形成一体结构。
所述初始化信号线图形94的至少部分沿所述第二方向延伸，所述初始化信号线图形94用于传输具有固定电位的初始化信号。示例性的，位于同一行的子像素包括的所述初始化信号线图形94依次电连接，形成为一体结构。
所述复位信号线图形95的至少部分沿所述第二方向延伸，用于传输复位信号。示例性的，位于同一行的子像素包括的所述复位信号线图形95依次电连接，形成为一体结构。
所述电源信号线图形91的至少部分沿第二方向延伸，用于传输具有固定电位的电源信号。示例性的，位于同一列的子像素包括的所述电源信号线图形91依次电连接，形成为一体结构。
每个子像素均包括子像素驱动电路。所述子像素驱动电路包括存储电容和多个薄膜晶体管，如图2和图5所示，示例性的，所述子像素驱动电路包括7T1C，即7个晶体管和一个存储电容。所述子像素驱动电路用于产生驱动发光元件发光的驱动信号。
示例性的，所述子像素驱动电路包括驱动晶体管和第一复位晶体管，所述第一复位晶体管的栅极与所述复位信号线图形95电连，所述第一复位晶体管的第一极与所述初始化信号线图形94电连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连；在复位时段，所述第一复位晶体管能够将接收到的初始化信号传输至所述驱动晶体管的栅极，实现对所述驱动晶体管的栅极复位。
每个子像素均包括位于所述子像素驱动电路背向所述基底的一侧的发光元件。所述发光元件包括沿远离基底的方向依次层叠设置的阳极图形、发光功能层和阴极。所述阳极图形与其所属的子像素中的子像素驱动电路电连，接收由该子像素驱动电路提供的驱动信号。所述发光功能层包括有机发光材料层，除此之外，所述发光功能层还可以包括：电子传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)以及空穴注入层(hole injection layer，简称HIL)等整层结构的公共层。所述阴极与所述显示基板中的负电源信号线电连，接收由该负电源信号线提供的负电源信号。所述发光功能层在所述阳极图形和所述阴极的共同作用下发光，实现显示基板的显示功能。
所述子像素还包括屏蔽图形80，所述屏蔽图形80在所述基底上的正投影与所述电源信号线图形91在所述基底上的正投影交叠，所述屏蔽图形80与所述电源信号线图形91通过设置在该交叠处的过孔实现电连。需要说明，本公开提供的附图中，中间设置交叉线的小方框代表过孔。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，通过设置所述屏蔽图形80在所述基底上的正投影与所述第一复位晶体管的第一极在所述基底上的正投影交叠，使得所述屏蔽图形80屏蔽了由于数据信号跳变对第一复位晶体管的第一极产生的干扰，进而避免了由于数据信号跳变对初始化信号线图形94上传输的初始化信号产生影响，有效提升了显示基板的显示效果。
另外，上述将所述屏蔽图形80与所述电源信号线图形91电连，使得所述屏蔽图形80具有与电源信号线图形91传输的电源信号相同的稳定电位，这样不仅有利于所述子像素驱动电路处于稳定的工作状态，还更好的保证了所述屏蔽图形80的屏蔽效果。
如图5～图7所示，在一些实施例中，设置所述屏蔽图形80在所述基底上的正投影与所述复位信号线图形95在所述基底上的正投影不交叠。
具体地，所述屏蔽图形80的具体布局位置多种多样，示例性的，所述屏蔽图形80在所述基底上的正投影与所述复位信号线图形95在所述基底上的正投影之间的最小距离大于阈值。示例性的，所述阈值为5μm。
上述设置方式使得在垂直于所述基底的方向上，所述屏蔽图形80与所述复位信号线图形95不交叠，从而避免了增加所述复位信号线图形95的负载。
如图5～图8所示，在一些实施例中，所述屏蔽图形80在所述基底上的正投影与所述第一复位晶体管的第二极在所述基底上的正投影交叠。
示例性的，所述屏蔽图形80在所述基底上的正投影完全覆盖所述第一复位晶体管的第二极在所述基底上的正投影。
上述设置所述屏蔽图形80在所述基底上的正投影与所述第一复位晶体管的第二极在所述基底上的正投影交叠，使得所述屏蔽图形80屏蔽了由于数据信号跳变对第一复位晶体管的第二极产生的干扰，进而避免了由于数据信号跳变对所述驱动晶体管的栅极产生影响，有效提升了显示基板的显示效果。
如图5～图8所示，在一些实施例中，所述多个子像素划分为多列子像素，每列子像素均包括沿第二方向依次排列的多个所述子像素；
所述子像素驱动电路还包括：第二复位晶体管(即第七晶体管T7)，所述第二复位晶体管的栅极与沿所述第二方向相邻的下一个子像素中的复位信号线图形95'电连，所述第二复位晶体管的第一极与沿所述第二方向相邻的下一个子像素中的初始化信号线图形94'电连，所述第二复位晶体管的第二极与其所属子像素中的阳极图形电连；
所述屏蔽图形80在所述基底上的正投影与所述第二复位晶体管的第一极在所述基底上的正投影交叠。
具体地，所述第二复位晶体管的栅极与沿所述第二方向相邻的下一个子像素中的复位信号线图形95'电连，所述第二复位晶体管的第一极与沿所述第二方向相邻的下一个子像素中的初始化信号线图形94'电连，所述第二复位晶体管的第二极与其所属子像素中的阳极图形电连，所述第七晶体管T7用于对阳极图形进行复位。
上述设置所述屏蔽图形80在所述基底上的正投影与所述第二复位晶体管的第一极在所述基底上的正投影交叠，使得所述屏蔽图形80屏蔽了由于数据信号跳变对所述的第一极产生的影响，进而避免了对初始化信号线图形94上传输的初始化信号产生影响。
如图12所示，在一些实施例中，所述多个子像素包括：
沿第二方向设置的第一子像素M1和第二子像素M2，所述第一子像素M1包括第一数据线图形981，所述第二子像素M2包括第二数据线图形982，所述第一数据线图形981的至少部分和所述第二数据线图形982的至少部分均沿第二方向延伸，所述第一数据线图形981位于沿所述第二方向延伸的同一列所述第一子像素M1的第一侧，所述第二数据线图形982位于沿所述第二方向延伸的同一列所述第二子像素M2的第二侧，所述第一侧与所述第二侧沿第一方向相对，所述第一方向与所述第二方向相交；
沿第二方向设置的第三子像素M3和第四子像素M4，沿所述第一方向，所述第三子像素M3与所述第一子像素M1位于同一行，所述第四子像素M4与所述第二子像素M2位于同一行；所述第三子像素M3包括第三数据线图形983，所述第四子像素M4包括第四数据线图形984，所述第三数据线图形983的至少部分和所述第四数据线图形984的至少部分均沿第二方向延伸，所述第三数据线图形983位于沿所述第二方向延伸的同一列第三子像素M3的第二侧，所述第四数据线图形984位于沿所述第二方向延伸的同一列第四子像素M4的第一侧。
具体地，所述第一数据线图形981的至少部分和所述第二数据线图形982的至少部分均沿所述第二方向延伸。所述第一数据线图形981被配置为给第一子像素M1提供第一数据信号，所述第二数据线图形982被配置为给第二子像素M2提供第二数据信号；位于同一列子像素中的各第一子像素M1包括的所述第一数据线图形981依次电连，能够形成一体结构。位于同一列子像素中的各第二子像素M2包括的所述第二数据线图形982依次电连，能够形成为一体结构。
示例性的，如图15所示，所述第一数据线图形981为：沿所述第二方向，当前第一子像素M1的数据写入位置(如数据线突出部9802所在位置)与下一行相邻第一子像素M1的数据写入位置之间的数据线部分。
示例性的，在同一列子像素中，所述第一子像素M1和所述第二子像素M2交替设置。
示例性的，在同一列子像素中，所述第三子像素M3和所述第四子像素M4交替设置。
示例性的，在同一列子像素中，所述第一子像素M1为第奇数个子像素，该第奇数个子像素接收其包括的第一数据线图形981提供的第一数据信号，所述第二子像素M2为第偶数个子像素，该第偶数个子像素接收其包括的第二数据线图形982提供的第二数据信号。
示例性的，设置所述第一侧为图5中的右侧，所述第二侧为图5中的左侧。在同一列子像素中，所述第一数据线图形981位于该同一列子像素的第一侧，所述第二数据线图形982位于该同一列子像素的第二侧。
示例性的，所述子像素驱动电路包括驱动晶体管和数据写入晶体管，在所述第一子像素M1中，所述数据写入晶体管的第一极与所述第一数据线图形981电连，在所述第二子像素M2中，所述数据写入晶体管的第一极与所述第二数据线图形982电连。在各子像素中所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连，所述数据写入晶体管能够将其第一极接收到的数据信号传输至所述驱动晶体管的第一极。
在同一列子像素中，相邻子像素中数据写入晶体管的第一极电连的数据线图形不同。更详细地说，在同一列子像素中，相邻子像素中的其中一个子像素包括的数据写入晶体管的第一极与所述第一数据线图形981电连，相邻子像素中的另一个子像素包括的数据写入晶体管的第一极与所述第二数据线图形982电连。
具体地，所述第三数据线图形983的至少部分和所述第四数据线图形984的至少部分均沿所述第二方向延伸。位于同一列子像素中的各第三子像素M3包括的所述第三数据线图形983依次电连，能够形成一体结构。位于同一列子像素中的各第四子像素M4包括的所述第四数据线图形984依次电连，能够形成为一体结构。所述第三数据线图形被配置为给第三子像素提供第三数据信号，所述第四数据线图形被配置为给第四子像素提供第四数据信号。
示例性的，沿所述第一方向，所述第三子像素M3与所述第一子像素M1位于同一行，所述第四子像素M4与所述第二子像素M2位于同一行。
同样的，所述第三子像素M3和所述第四子像素M4也均包括子像素驱动电路，在所述第三子像素M3中，所述数据写入晶体管的第一极与所述第三数据线图形983电连，在所述第四子像素M4中，所述数据写入晶体管的 第一极与所述第四数据线图形984电连。在各子像素中所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连，所述数据写入晶体管能够将其第一极接收到的数据信号传输至所述驱动晶体管的第一极。
示例性的，设置所述第一侧为图5中的右侧，所述第二侧为图5中的左侧。所述第三数据线图形983位于沿所述第二方向延伸的同一列第三子像素的第二侧，所述第四数据线图形984位于沿所述第二方向延伸的同一列第四子像素的第一侧；
示例性的，在沿所述第一方向位于同一行的子像素中，第一数据线图形981和第三数据线图形983，均位于该第一数据线图形981所属的第一子像素M1和该第三数据线图形983所属的第三子像素M3之间。在沿所述第一方向位于同一行的子像素中，第二数据线图形982和第四数据线图形984，均位于该第二数据线图形982所属的第二子像素M2和该第四数据线图形984所属的第四子像素M4之间。
值得注意，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4包括的子像素驱动电路的结构相同，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4的区别在于数据线的设置方式和发光元件的结构。
上述实施例提供的显示基板中，实现了在同一列子像素中，相邻的子像素由不同的数据线图形提供数据信号，保证了每个子像素均具有足够的数据信号写入时间，从而解决了显示基板在高频显示时，每行子像素的数据信号写入时间不足的问题。
需要说明，如图12所示，所述多个子像素还包括：第五子像素M5、第六子像素M6、第七子像素M7和第八子像素M8；所述第五子像素M5和所述第六子像素M6沿所述第二方向交替设置，所述第七子像素M7和所述第八子像素M8沿所述第二方向交替设置；沿所述第一方向，所述第一子像素M1、所述第三子像素M3、所述第五子像素M5和所述第七子像素M7位于同一行；沿所述第一方向，所述第二子像素M2、所述第四子像素M4、所述第六子像素M6和所述第八子像素M8位于同一行。
如图12中第一子像素M1至第八子像素M8这八个子像素形成一个重复 单元，所述显示基板中包括多个所述重复单元。
如图5、图7和图18所示，在一些实施例中，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4均包括第一导电连接部961和第五导电连接部965；
在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中：
所述子像素驱动电路均包括数据写入晶体管；
所述第一导电连接部961分别与对应的数据线图形和数据写入晶体管的第一极电连；所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连；
所述第一复位晶体管(即第二晶体管T2)的第二极通过所述第五导电连接部965与所述驱动晶体管的栅极电连；
所述屏蔽图形80在所述基底上的正投影与所述第一导电连接部961在所述基底上的正投影至少部分交叠。
具体地，在每个子像素中，所述第五导电连接部965的至少部分沿所述第二方向延伸。所述第五导电连接部965的一端在所述基底上的正投影与所述第二晶体管T2的第二极在所述基底上的正投影具有第六交叠区域，所述第五导电连接部965的一端与所述第二晶体管T2的第二极通过设置在所述第六交叠区域的过孔电连，所述第五导电连接部965的另一端在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影交叠，所述第五导电连接部965的另一端与所述驱动晶体管的栅极通过设置在该交叠处的过孔电连。
所述第一数据线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984均包括数据线主体部9801和数据线突出部9802，所述数据线主体部9801沿所述第二方向延伸，所述数据线突出部9802沿所述第一方向突出于所述数据线主体部9801。
各所述子像素还包括第一导电连接部961，示例性的，所述第一导电连接部961的至少部分沿所述第二方向延伸。所述第一导电连接部961的第一端在所述基底上的正投影，与对应的所述数据线突出部9802在所述基底上的正投影具有第一交叠区域，所述第一导电连接部961的第一端与该数据线突 出部9802通过设置在所述第一交叠区域的过孔电连。所述第一导电连接部961的第二端在所述基底上的正投影，与所述数据写入晶体管的第一极在所述基底上的正投影具有第二交叠区域，所述第一导电连接部961的第二端与所述数据写入晶体管的第一极通过设置在所述第二交叠区域的过孔电连，所述数据写入晶体管的第一极通过所述第一导电连接部961接收由对应的数据线图形提供的数据信号。
示例性的，所述屏蔽图形80包括相电连的第一屏蔽部801和第二屏蔽部802，所述第一屏蔽部801在所述基底上的正投影与所述电源信号线图形91在所述基底上的正投影交叠，所述第一屏蔽部801与所述电源信号线图形91通过设置在该交叠处的过孔直接电连。
示例性的，所述第一屏蔽部801与所述第二屏蔽部802形成为一体结构。
示例性的，所述第一屏蔽部801为沿所述第一方向延伸的方形结构，所述第一屏蔽部801在所述基底上的正投影与所述第二晶体管T2的第一极在所述基底上的正投影交叠，和/或，所述第一屏蔽部801在所述基底上的正投影与沿所述第二方向相邻子像素中的所述第七晶体管T7的第一极在所述基底上的正投影交叠。
示例性的，所述第一屏蔽部801在所述基底上的正投影与所述复位信号线图形95在所述基底上的正投影不交叠。
示例性的，所述屏蔽图形80中的第一屏蔽部801在所述基底上的正投影与所述第一导电连接部961在所述基底上的正投影至少部分交叠。
上述设置所述屏蔽图形在所述基底上的正投影与所述第一导电连接部在所述基底上的正投影至少部分交叠，能够有效避免由于数据信号变化对周边其它功能图形的电位产生影响。
如图5所示，在一些实施例中，所述屏蔽图形80的至少部分在所述基底上的正投影，位于所述第一导电连接部961在所述基底上的正投影与所述第五导电连接部965在所述基底上的正投影之间。
示例性的，如图13b所示，所述屏蔽图形80中的所述第二屏蔽部802在所述基底上的正投影，位于所述第二交叠区域与所述第六交叠区域之间。
示例性的，所述第二屏蔽部802为沿所述第二方向延伸的方形结构。
上述设置方式使得所述第二屏蔽部802能够更好的屏蔽数据信号变化对第二晶体管T2的第二极产生的影响，进而避免了数据信号的变化对驱动晶体管的栅极信号产生影响。由于驱动晶体管的栅极信号直接影响子像素亮度，因此上述设置方式使所述驱动晶体管的栅极电位更加稳定，从而使得显示基板在用于显示时能够获得更好的显示效果。
如图5、图7和图18所示，在一些实施例中，在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中：
所述子像素驱动电路均包括第一晶体管T1，所述第一晶体管T1的第一极与所述驱动晶体管的第二极电连，所述第一晶体管T1的第二极与所述驱动晶体管的栅极电连；
所述第一晶体管T1的有源图形包括间隔设置的两个半导体部分，以及分别连接所述两个半导体部分的第一导体部分；
所述屏蔽图形80在所述基底上的投影还与所述第一导体部分在所述基底上的正投影至少部分交叠。
具体地，各所述子像素还均包括第一晶体管T1，所述第一晶体管T1的栅极与栅线图形92电连，所述第一晶体管T1的第一极与所述驱动晶体管的第二极电连，所述第一晶体管T1的第二极与所述驱动晶体管的栅极电连。
所述第一晶体管T1形成为双栅结构，所述第一晶体管T1的有源图形包括间隔设置的两个半导体部分，以及分别连接所述两个半导体部分的第一导体部分，所述第一晶体管T1的栅极在所述基底上的正投影，覆盖所述两个半导体部分在所述基底上的正投影，所述第一晶体管T1的栅极在所述基底上的正投影与所述第一导体部分在所述基底上的正投影不交叠。
示例性的，所述屏蔽图形80还包括与所述第一屏蔽部801电连的第三屏蔽部803，所述第三屏蔽部803的至少部分为沿所述第二方向延伸的方形结构。
示例性的，所述第一屏蔽部801与所述第三屏蔽部803形成为一体结构。
示例性的，所述屏蔽图形80还包括与所述第一屏蔽部801电连的第三屏蔽部803，所述第三屏蔽部803在所述基底上的正投影与所述第一导体部分在所述基底上的正投影交叠。
所述第三屏蔽部803在所述基底上的正投影与所述第一导体部分在所述基底上的正投影交叠。这种设置方式使得所述第三屏蔽图形80能够对所述第一导体部分进行遮挡，避免了数据信号的变化对所述第一晶体管T1产生影响，进而避免了数据信号的变化对驱动晶体管的栅极信号产生影响。
在一些实施例中，沿垂直于所述基底的方向上，所述屏蔽图形80位于所述第一复位晶体管(即第二晶体管T2)的第一极与所述第一导电连接部961之间。
示例性的，所述显示基板还包括位于所述第二晶体管T2的第一极与所述第一导电连接部961之间的第二栅极绝缘层，在每个子像素中，所述初始化信号线图形94与所述屏蔽图形80均位于所述第二栅极绝缘层背向所述基底的表面。
上述设置所述初始化信号线图形94与所述屏蔽图形80均位于所述第二栅极绝缘层背向所述基底的表面，使得所述初始化信号线图形94与所述屏蔽图形80同层设置，当所述初始化信号线图形94与所述屏蔽图形80采用相同的材料制作时，能够将所述初始化信号线图形94与所述屏蔽图形80在同一次构图工艺中形成，从而更好的简化了显示基板的制作流程，节约了制作成本。
如图12和图14所示，在一些实施例中，在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中，各子像素中的所述电源信号线图形91均包括：相电连的电源主体部分(包括第一部分911和第二部分912)和电源突出部分913；
在所述第一子像素M1中，所述电源突出部分913在所述基底上的正投影与所述第一数据线图形981在所述基底上的正投影交叠，所述电源主体部分在所述基底上的正投影与沿所述第一方向相邻的数据线图形(如图12中的第三数据线图形983)在所述基底上的正投影至少部分交叠。
具体地，所述显示基板中，每个子像素均包括所述电源信号线图形91，所述电源信号线图形91的至少部分沿所述第二方向延伸。同一列子像素中，各子像素包括的电源信号线图形91依次电连，可形成为一体结构。所述电源信号线图形91的具体结构多种多样，示例性的，所述电源信号线图形91包 括相电连的第一部分911和第二部分912，所述第一部分911与所述第二部分912交替设置。示例性的，所述第二部分912沿所述第一方向突出于所述第一部分911。
示例性的，在所述第一子像素M1中，所述第一部分911在所述基底上的正投影与沿所述第一方向相邻的第三数据线图形983的数据线主体部9801在所述基底上的正投影交叠，所述第二部分912在所述基底上的正投影与该第三数据线图形983的数据线主体部9801在所述基底上的正投影不交叠。
示例性的，所述第一部分911的至少部分沿所述第二方向延伸，所述第二部分912的至少部分沿所述第二方向延伸，在垂直于所述第二方向的方向上，所述第一部分911的宽度等于所述第二部分912的宽度，或者所述第一部分911的宽度大于所述第二部分912的宽度，或者所述第一部分911的宽度小于所述第二部分912的宽度。
上述实施例提供的显示基板中，所述第一数据线图形981在所述基底上的正投影与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积，以及沿所述第一方向与该第一数据线图形981相邻的数据线图形在所述基底上的正投影，与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积相接近，从而有效缩小了所述第一数据线图形981与沿第一方向相邻的数据线图形之间的负载差异。
需要说明的是，所述具有固定单位的功能图形包括：电源信号线图形91，初始化信号线图形94，以及与所述电源信号线图形91或所述初始化信号线图形94电连的导电功能图形(如：第二导电连接部962)等。
如图12和图14所示，在一些实施例中，在所述第二子像素M2中，所述电源突出部分913在所述基底上的正投影与所述第二数据线图形982在所述基底上的正投影不交叠。
示例性的，在所述第二子像素M2中，所述电源突出部分913在所述基底上的正投影，与沿第二方向相邻的第一数据线981的延长部分在所述基底上的正投影交叠。
如图12和图14所示，在一些实施例中，在所述第三子像素M3中，所述电源突出部分913在所述基底上的正投影与所述第三数据线图形983在所 述基底上的正投影不交叠。
示例性的，在所述第三子像素M3中，所述电源突出部分913在所述基底上的正投影，与沿第二方向相邻的第四数据线984的延长部分在所述基底上的正投影交叠。
如图12和图14所示，在一些实施例中，在所述第四子像素M4中，所述电源突出部分913在所述基底上的正投影与所述第四数据线图形984在所述基底上的正投影交叠，所述电源主体部分在所述基底上的正投影与沿所述第一方向相邻的数据线图形在所述基底上的正投影交叠。
示例性的，在所述第四子像素M4中，所述电源主体部分包括第一部分911和第二部分912，所述第一部分911在所述基底上的正投影与沿所述第一方向相邻的第六数据线图形986的数据线主体部9801在所述基底上的正投影交叠，所述第二部分912在所述基底上的正投影与该第六数据线图形986的数据线主体部9801在所述基底上的正投影不交叠。
上述实施例提供的显示基板中，使得所述第四数据线图形984在所述基底上的正投影与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积，和所述第六数据线图形986在所述基底上的正投影与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积接近，从而有效缩小了所述第四数据线图形984与所述第六数据线图形986之间的负载差异。值得注意，图12中还示出了第五子像素M5还包括第五数据线图形985，第七子像素M7还包括第七数据线图形987，第八子像素还包括第八数据线图形988。
上述实施例提供的显示基板中，所述第四数据线图形984在所述基底上的正投影与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积，以及沿所述第一方向与该第四数据线图形984相邻的数据线图形在所述基底上的正投影，与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积相接近，从而有效缩小了所述第四数据线图形984与沿第一方向相邻的数据线图形之间的负载差异。
如图5、图10和图12所示，在一些实施例中，所述第一子像素M1和所述第二子像素M2均包括：初始化信号线图形94、第二晶体管T2和第二导电连接部962；
所述初始化信号线图形94的至少部分沿所述第二方向延伸，所述初始化信号线图形94用于传输初始化信号；
所述第二晶体管T2的第一极通过所述第二导电连接部962与所述初始化信号线图形94电连，所述第二晶体管T2的第二极与所述驱动晶体管的栅极电连；在所述第一子像素M1中，所述第二导电连接部962在所述基底上的正投影与所述第一数据线图形981在所述基底上的正投影交叠；在所述第二子像素M2中，所述第二导电连接部962在所述基底上的正投影与所述第二数据线图形982在所述基底上的正投影不交叠。
如图12所示，在一些实施例中，所述第三子像素M3和所述第四子像素M4均包括：初始化信号线图形94、第二晶体管T2和第二导电连接部962；
所述初始化信号线图形94的至少部分沿所述第二方向延伸，所述初始化信号线图形94用于传输初始化信号；
所述第二晶体管T2的第一极通过所述第二导电连接部962与所述初始化信号线图形94电连，所述第二晶体管T2的第二极与所述驱动晶体管的栅极电连；
在所述第三子像素M3中，所述第二导电连接部962在所述基底上的正投影与所述第三数据线图形983在所述基底上的正投影不交叠；
在所述第四子像素M4中，所述第二导电连接部962在所述基底上的正投影与所述第四数据线图形984在所述基底上的正投影交叠。
具体地，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4均包括所述初始化信号线图形94，所述第二晶体管T2和所述第二导电连接部962。示例性的，所述第二晶体管T2的第一极在所述基底上的正投影与所述第二导电连接部962的第一端在所述基底上的正投影交叠，所述第二晶体管T2的第一极与所述第二导电连接部962的第一端通过位于该交叠处的过孔电连。所述第二导电连接部962的第二端在所述基底上的正投影与所述初始化信号线图形94在所述基底上的正投影交叠，所述第二导电连接部962的第二端与所述初始化信号线图形94通过位于该交叠处的过孔电连。
所述第二晶体管T2的第二极与所述驱动晶体管的栅极电连，在复位时 段，所述第二晶体管T2能够将接收到的所述初始化信号传输至所述驱动晶体管的栅极，实现对所述驱动晶体管的栅极复位。
由于所述第二导电连接部962与所述初始化信号线图形94电连，使得所述初始化信号线图形94具有稳定的电位。上述设置在所述第一子像素M1中，所述第二导电连接部962在所述基底上的正投影与所述第一数据线图形981在所述基底上的正投影交叠；使得所述第一数据线图形981在所述基底上的正投影与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积，和所述第三数据线图形在所述基底上的正投影与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积更加接近，从而进一步缩小了所述第一数据线图形981与所述第三数据线图形之间的负载差异。
上述设置在所述第四子像素M4中，所述第二导电连接部962在所述基底上的正投影与所述第四数据线图形984在所述基底上的正投影交叠，使得所述第二数据线图形982在所述基底上的正投影与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积，和所述第四数据线图形984在所述基底上的正投影与具有固定电位的功能图形在所述基底上的正投影之间的交叠面积更加接近，从而进一步缩小了所述第二数据线图形982与所述第四数据线图形984之间的负载差异。
在一些实施例中，所述第三数据线图形在所述基底上的正投影与所述第一部分911在所述基底上的正投影形成的交叠区域具有第一面积；所述第一数据线图形981在所述基底上的正投影与所述电源突出部分913在所述基底上的正投影形成的交叠区域具有第二面积，所述第一数据线图形981在所述基底上的正投影与显示基板中的第二导电连接部962在所述基底上的正投影具有第三面积；所述第二面积与所述第三面积之和与所述第一面积大致相同。上述设置所述第二面积与所述第三面积之和与所述第一面积大致相同，使得所述第一数据线图形981的负载与所述第三数据线图形的负载基本相同，从而更好的提升了显示基板的显示均一性。
在一些实施例中，所述第二数据线图形在所述基底上的正投影与所述第一部分911在所述基底上的正投影形成的交叠区域具有第一面积；所述第四数据线图形984在所述基底上的正投影与所述电源突出部分913在所述基底 上的正投影形成的交叠区域具有第二面积，所述第四数据线图形984在所述基底上的正投影与显示基板中的第二导电连接部962在所述基底上的正投影具有第三面积；所述第二面积与所述第三面积之和与所述第一面积大致相同。上述设置所述第二面积与所述第三面积之和与所述第一面积大致相同，使得所述第二数据线图形982的负载与所述第四数据线图形984的负载基本相同，从而更好的提升了显示基板的显示均一性。
如图5、图8、图9、图12和图19所示，在一些实施例中，所述电源突出部分913包括第三部分9130、第四部分9131和第五部分9132；所述第三部分9130沿所述第二方向延伸，在第一子像素M1中，所述第三部分9130在所述基底上的正投影与所述第一数据线图形981在所述基底上的正投影交叠。在第四子像素M4中，所述第三部分9130在所述基底上的正投影与所述第四数据线图形984在所述基底上的正投影交叠。
在第一子像素M1中，通过设置所述第三部分9130沿所述第二方向的长度，即可控制所述第一数据线图形981与所述第三部分9130交叠的面积，进而调节所述第一数据线图形981的负载。在第三子像素M3中，通过设置所述第三部分9130沿所述第二方向的长度，即可控制所述第四数据线图形984与所述第三部分9130交叠的面积，进而调节所述第四数据线图形984的负载。
如图5、图12和图13a所示，在一些实施例中，所述显示基板还包括沿远离所述基底的方向依次层叠设置的层间绝缘层ILD和第一平坦层PLN1；所述第一数据线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984均位于所述第一平坦层PLN1背向所述基底的表面；所述电源信号线图形91与所述电源补偿图形97均位于所述层间绝缘层ILD背向所述基底的表面。
具体地，上述设置所述第一数据线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984均位于所述第一平坦层PLN1背向所述基底的表面，使得所述第一数据线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984均同层设置，当所述第一数据线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984采用相同材料制作时，能够将所述第一数据 线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984在同一次构图工艺中形成，从而更好的简化了显示基板的制作流程，节约了制作成本。
需要说明的是，所述第一数据线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984可形成所述显示基板中的第二源漏金属层。值得注意，所述第二源漏金属层还可以包括其它结构。
请参阅图5、图12、图13c和图13d，在一些实施例中，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4均包括：
电源补偿图形97，所述电源补偿图形97的至少部分沿所述第一方向延伸，所述电源信号线图形91和所述电源补偿图形97均位于所述第一数据线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984靠近所述基底的一侧；
所述电源补偿图形97分别与其所属子像素中的电源信号线图形91，以及沿所述第一方向相邻子像素中的电源信号线图形91电连。
具体地，各所述子像素还包括电源补偿图形97，所述电源信号线图形91和所述电源补偿图形97均位于所述第一数据线图形981、第二数据线图形982、第三数据线图形983和第四数据线图形984靠近所述基底的一侧；示例性的，所述第一数据线图形981、第二数据线图形982、第三数据线图形983和第四数据线图形984靠近所述基底的一侧设置有层间绝缘层ILD，所述电源补偿图形97与所述电源信号线图形91均位于所述层间绝缘层ILD背向所述基底的表面。这种设置方式使得所述电源信号线图形91与所述电源补偿图形97同层设置，当所述电源信号线图形91与所述电源补偿图形97采用相同的材料制作时，能够将所述电源信号线图形91与所述电源补偿图形97在同一次构图工艺中形成，从而更好的简化了显示基板的制作流程，节约了制作成本。
需要说明的是，所述电源信号线图形91和所述电源补偿图形97可形成所述显示基板中的第一源漏金属层，当然，所述第一源漏金属层还可以包括其它结构。
如图5所示，示例性的，所述电源补偿图形97分别与其所属子像素中的所述电源信号线图形91，以及沿所述第一方向相邻子像素中的电源信号线图形91'电连。
示例性的，所述电源补偿图形97与其分别电连的两个所述电源信号线图形91形成为一体结构。值得注意，所述一体结构包括：采用同种材料，通过一次构图工艺同时形成接触的所述电源补偿图形97与所述电源信号线图形91。
上述实施例提供的显示基板中，通过设置所述电源补偿图形97分别与其所属子像素中的所述电源信号线图形91，以及与该子像素沿所述第一方向位于同一行的相邻子像素中的电源信号线图形91'电连；使得位于同一行的各子像素包括的电源信号线图形91均电连在一起，使所述电源信号线图形91的整体电阻降低，从而更有利于提升显示基板显示的均一性。同时，通过设置位于同一列的各子像素中的电源信号线图形91依次电连，使得所述显示基板中包括的全部电源信号线图形91共同形成为网状结构，从而进一步提升了显示基板的显示均一性。
上述实施例提供的显示基板中，通过设置所述电源补偿图形97与所述电源信号线图形91均位于所述显示基板的层间绝缘层ILD背向所述基底的表面，以及所述电源信号线图形91和所述电源补偿图形97形成为所述显示基板中的第一源漏金属层，使得所述电源信号线图形91与所述电源补偿图形97能够在同一次构图工艺中形成，从而更好的简化了显示基板的制作流程，节约了制作成本。而且，由于所述电源补偿图形97与所述电源信号线图形91采用相同的源漏金属材料制作，使得所述电源补偿图形97与所述电源信号线图形91的电阻均较小，从而更好的提升了显示基板的显示均一性。
本公开实施例提供的显示基板中，将包括的全部电源信号线图形91共同形成为网状结构，有效提升了电源信号线图形传输的电源信号的稳定性，而电源信号用于提供给子像素驱动电路中的驱动晶体管的源极，而子像素驱动电路产生的发光电流I oled＝k[(Vgs-Vth)] 2，Vgs＝Vg-Vs，Vg为驱动晶体管的栅极电压，Vs为驱动晶体管的源极电压，Vth为驱动晶体管的阈值电压，因此，电源信号作为Vs，会对发光电流I oled的大小产生影响，因此，上述设置方式 在提升电源信号线层的稳定性的同时，更好的保证了发光电流I oled的稳定性，有效避免了动态串扰现象的发生。
如图5和图8所示，在一些实施例中，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4均包括：沿第二方向分布的所述复位信号线图形95、栅线图形92和发光控制信号线图形93；所述复位信号线图形95的至少部分沿第一方向延伸，所述栅线图形92的至少部分沿所述第一方向延伸，所述发光控制信号线图形93的至少部分沿第一方向延伸；
在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中，所述电源补偿图形97在所述基底上的正投影，位于所述栅线图形92在所述基底上的正投影与所述发光控制信号线图形93在所述基底上的正投影之间。
具体的，所述子像素还包括：沿第二方向依次分布的复位信号线图形95、栅线图形92和发光控制信号线图形93。所述复位信号线用于传输复位信号，所述栅线图形92用于传输扫描信号。所述发光控制信号线图形93用于传输发光控制信号。
所述复位信号线图形95的至少部分沿第一方向延伸，沿所述第一方向位于同一行的各子像素包括的所述复位信号线图形95依次电连，可形成为一体结构。所述栅线图形92的至少部分沿所述第一方向延伸，沿所述第一方向位于同一行的各子像素包括的所述栅线图形92依次电连，可形成为一体结构。所述发光控制信号线图形93的至少部分沿第一方向延伸，沿所述第一方向位于同一行的各子像素包括的所述发光控制信号线图形93依次电连，可形成为一体结构。
所述电源补偿图形97的具体布局位置多种多样，示例性的，在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中，所述电源补偿图形97在所述基底上的正投影与所述复位信号线图形95在所述基底上的正投影不交叠，所述电源补偿图形97在所述基底上的正投影与所述栅线图形92在所述基底上的正投影不交叠，所述电源补偿图形97在所述基底上的正投影与所述发光控制信号线图形93在所述基底上的正 投影均不交叠。
示例性的，所述电源补偿图形97在所述基底上的正投影，位于所述栅线图形92在所述基底上的正投影与所述发光控制信号线图形93在所述基底上的正投影之间。
示例性的，沿所述第二方向，所述电源补偿图形97在所述基底上的正投影与所述栅线图形92在所述基底上的正投影之间的最小距离，大于所述电源补偿图形97在所述基底上的正投影与所述发光控制信号线图形93在所述基底上的正投影之间的最小距离。
按照上述方式布局所述电源补偿图形97，使得所述电源补偿图形97与所述复位信号线图形95、所述栅线图形92以及所述发光控制信号线图形93之间均具有较远的距离，从而避免了增加所述复位信号线图形95、所述栅线图形92以及所述发光控制信号线图形93的负载。
在一些实施例中，所述电源补偿图形97在所述基底上的正投影，与所述栅线图形92在所述基底上的正投影之间的最小距离大于阈值；所述电源补偿图形97在所述基底上的正投影，与所述发光控制信号线图形93在所述基底上的正投影之间的最小距离大于所述阈值。
示例性的，所述阈值为5μm。所述电源补偿图形97在所述基底上的正投影，与所述栅线图形92在所述基底上的正投影之间的最小距离大于5μm；所述第电源补偿图形97在所述基底上的正投影，与所述发光控制信号线图形93在所述基底上的正投影之间的最小距离大于5μm。
上述设置方式使得所述电源补偿图形97与所述复位信号线图形95、所述栅线图形92以及所述发光控制信号线图形93之间均具有较远的距离，从而避免了增加所述复位信号线图形95、所述栅线图形92以及所述发光控制信号线图形93的负载。
如图5、图8、图10、图12和图19所示，在一些实施例中，在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中，各子像素中的所述电源信号线图形91均包括：相电连的电源主体部分(包括第一部分911和第二部分912)和电源突出部分913；
所述电源补偿图形97的第一端与所述电源突出部分913电连；所述电源 补偿图形97的第二端与沿所述第一方向相邻子像素中的电源主体部分(即如图8中的电源信号线图形91'的电源主体部分)电连。
示例性的，所述电源突出部分913的至少部分沿所述第二方向延伸，所述电源补偿图形97的第二端与所述电源突出部分913的中间部分电连。
上述设置方式能够缩短所述电源补偿图形97的长度，从而有效降低了所述电源补偿图形97的布局难度。
如图5、图8、图10、图12和图19所示，在一些实施例中，所述电源突出部分913的至少部分沿所述第二方向延伸，所述电源突出部分913与所述电源主体部分之间具有间隙50。
更详细地说，所述电源突出部分913包括第三部分9130、第四部分9131和第五部分9132；所述第三部分9130与所述电源补偿图形97电连，所述第三部分9130沿所述第二方向延伸；所述第四部分9131分别与所述第三部分9130的一端和所述电源主体部分电连；所述第五部分9132分别与所述第三部分9130的另一端和所述电源主体部分电连；所述第三部分9130与所述电源主体部分之间具有间隙50。
具体地，所述电源突出部分913的具体结构多种多样，示例性的，所述电源突出部分913包括一体结构的所述第三部分9130、所述第四部分9131和所述第五部分9132。
上述通过设置所述第四部分9131分别与所述第三部分9130的一端和所述电源主体部分电连；所述第五部分9132分别与所述第三部分9130的另一端和所述电源主体部分电连，更好的保证了所述电源突出部分913与所述电源主体部分之间的连接性能，更有效的提升了显示基板的显示均一性。
另外，所述显示基板还可以包括指纹识别模块。示例性的，所述指纹识别模块位于基底背向所述子像素驱动电路的一侧。示例性的，所述指纹识别模块的指纹识别区域在所述基底上的正投影与所述间隙50在所述基底上的正投影交叠。在进行指纹识别时，手指在发光元件背向所述基底的一侧发生触控，经手指反射的光线能够穿过间隙50被指纹识别模块接收，实现指纹识别功能。
上述设置所述第三部分9130与所述电源主体部分之间具有间隙50，更 好的提升了显示基板的光线透光率，因此，上述实施例提供的显示基板兼容光学式指纹识别技术时，能够为sensor采集光信号提供良好条件，从而有效提高了指纹识别的速度和准确度。
另外，上述实施例提供的显示基板中，仅在所述电源信号线图形91上形成了间隙50，并未进行缩窄除所述电源信号线图形91之外的金属走线线宽、压缩发光元件尺寸、压缩晶体管或电容尺寸等操作，因此，上述实施例提供的显示基板在提升分辨率的同时，不容易对显示基板的性能产生负面影响。
如图5和图9所示，在一些实施例中，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4均包括：存储电容Cst和驱动晶体管，在各子像素中，所述存储电容Cst的第一极板Cst1与所述驱动晶体管的栅极电连，所述存储电容Cst的第二极板Cst2与所述电源突出部分913电连。
示例性的，所述存储电容Cst的第二极板Cst2在所述基底上的正投影与所述电源突出部分913在所述基底上的正投影交叠，所述存储电容Cst的第二极板Cst2与所述电源突出部分在该交叠处电连。
示例性的，所述第三部分9130包括第一子部分9130a和第二子部分9130b，所述第一子部分9130a靠近所述第四部分9131，所述第二子部分9130b靠近所述第五部分9132，在平行于所述基底的平面上，在垂直于所述第二方向的方向上，所述第一子部分9130a的宽度L1大于所述第二子部分9130b的宽度L2；
所述存储电容Cst的第二极板Cst2在所述基底上的正投影，与所述第一子部分9130a在所述基底上的正投影交叠，所述存储电容Cst的第二极板Cst2与所述第一子部分9130a通过设置在该交叠处的过孔电连。
上述设置方式使得所述存储电容Cst的第二极板Cst2能够与所述第一子部分9130a之间形成较大面积的交叠区域，从而更有利于降低该过孔的布局难度。需要说明，图13a中的标记40代表基底以及设置在基底上的一些膜层(如缓冲层、隔离层等)。
如图5和图9所示，在一些实施例中，在垂直于所述第一方向的方向上，设置所述电源补偿图形97的第一端D具有第一宽度，沿靠近该第一子图形 所属子像素中的电源信号线图形的方向(即图9中带箭头的虚线指向的方向)，所述第一宽度逐渐增大。
上述设置方式不仅使得所述电源补偿图形97与所述电源信号线图形91之间具有更好的连接性能，同时还避免了所述电源补偿图形97与所述电源信号线图形91之间的连接处形成直角结构，导致产生静电风险。
如图10和图11所示，在一些实施例中，所述第一数据线图形981、所述第二数据线图形982、所述第三数据线图形983和所述第四数据线图形984均包括数据线主体部9801和数据线突出部9802，所述数据线主体部9801沿所述第二方向延伸，所述数据线突出部9802沿所述第一方向突出于所述数据线主体部9801；
所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4均包括第一导电连接部961和数据写入晶体管，在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中，所述数据线突出部9802与所述数据写入晶体管的第一极通过所述第一导电连接部961电连。
示例性的，所述第一导电连接部961的至少部分沿所述第二方向延伸。所述第一导电连接部961的第一端在所述基底上的正投影，与所述数据线突出部9802在所述基底上的正投影具有第一交叠区域，所述第一导电连接部961的第一端与所述数据线突出部9802通过设置在所述第一交叠区域的过孔电连。所述第一导电连接部961的第二端在所述基底上的正投影，与所述数据写入晶体管的第一极在所述基底上的正投影具有第二交叠区域，所述第一导电连接部961的第二端与所述数据写入晶体管的第一极通过设置在所述第二交叠区域的过孔电连，所述数据写入晶体管的第一极通过所述第一导电连接部961接收由对应的所述数据线图形提供的数据信号。
示例性的，所述电源信号线图形91的第二部分912在所述基底上的正投影与所述第一交叠区域沿所述第一方向排列。
沿所述第一方向，所述第一导电连接部961与所述电源信号线图形91之间的距离较远，通过设置所述电源信号线图形91的第二部分912在所述基底上的正投影与所述第一交叠区域沿所述第一方向排列，使得所述第二部分912 具有足够的布局空间，从而在保证所述第二部分912在具有较大的面积的情况下，更好的降低了显示基板的布局难度。
如图12、图13a和图15所示，在一些实施例中，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4均包括：第六晶体管T6，以及沿远离所述基底的方向依次层叠设置的第三导电连接部963、第四导电连接部964和发光元件；所述发光元件包括阳极图形(如图13a中的第五阳极图形75)；在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中，所述第六晶体管T6的第一极与所述驱动晶体管(即第三晶体管T3)的第二极连接；所述第六晶体管T6的第二极通过所述第三导电连接部963和所述第四导电连接部964与所述发光元件电连。
示例性的，各所述子像素中，所述第六晶体管T6的栅极与发光控制信号线图形93电连，所述第六晶体管T6的第一极与所述驱动晶体管的第二极电连，所述第六晶体管T6的第二极在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有第三交叠区域，所述第六晶体管T6的第二极与所述第三导电连接部963通过设置在所述第三交叠区域的第一过孔61电连；所述第三导电连接部963在所述基底上的正投影与所述第四导电连接部964在所述基底上的正投影具有第四交叠区域，所述第三导电连接部963与所述第四导电连接部964通过设置在所述第四交叠区域的第二过孔62电连；所述第四导电连接部964在所述基底上正投影与所述阳极图形(如：第一阳极图形71、第二阳极图形72、第三阳极图形73)在所述基底上的正投影具有第五交叠区域，所述第四导电连接部964与所述阳极图形通过设置在所述第五交叠区域的第三过孔63电连。
在发光时段，所述第六晶体管T6将由所述驱动晶体管的第二极输出的驱动信号，依次经过所述第三导电连接部963和所述第四导电连接部964传输至发光元件的阳极。
上述实施例提供的显示基板中，设置所述第六晶体管T6的第二极，依次通过所述第三导电连接部963和所述第四导电连接部964与阳极图形电连，更好的保证了所述第六晶体管T6的第二极与所述阳极图形之间的电连性能。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在所述第五子像素M5中，所述第四导电连接部964包括实体部分9641和镂空部分9642；所述实体部分9641在所述基底上的正投影，以及所述镂空部分9642在所述基底上的正投影均与所述阳极图形在所述基底上的正投影至少部分交叠；所述阳极图形在所述基底上的正投影与所述第五数据线图形985在所述基底上的正投影至少部分交叠，所述阳极图形在所述基底上的正投影与沿所述第一方向相邻的第七数据线图形987在所述基底上的正投影至少部分交叠。
具体地，在所述第五子像素M5中，所述发光元件包括第五发光元件，所述第五发光元件包括沿远离所述基底的方向依次层叠设置的第五阳极图形75、第五发光功能层和阴极。示例性的，所述第五发光元件包括蓝色发光元件。
示例性的，在所述第五子像素M5中，所述实体部分9641在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有所述第四交叠区域；所述实体部分9641在所述基底上的正投影与所述第五阳极图形75在所述基底上的正投影具有所述第五交叠区域。
示例性的，所述第五阳极图形75的第一侧部在所述基底上的正投影，与其所属的子像素中的所述第五数据线图形985在所述基底上的正投影交叠，且与该第五数据线图形985沿第一方向相邻的第七数据线图形987在所述基底上的正投影交叠；所述第五阳极图形75的第二侧部在所述基底上的正投影与所述镂空部分9642在所述基底上的正投影交叠；所述第一侧部和所述第二侧部沿所述第一方向相对设置。
示例性的，所述镂空部分9642形成为口字型，所述第五阳极图形75的第二侧部在所述基底上的正投影，与所述镂空部分9642中沿所述第一方向相对的两边在所述基底上的正投影均交叠。示例性的，所述第五阳极图形75的第二侧部在所述基底上的正投影，与所述镂空部分9642中沿所述第二方向相对的两边在所述基底上的正投影均交叠。
示例性的，所述镂空部分9642中沿所述第一方向相对的两边之间具有第一距离L3，沿第一方向相邻的两个子像素中，相靠近的所述第五数据线图形 985与所述第七数据线图形987之间沿所述第一方向具有第二距离L4，所述第一距离L3与所述第二距离L4相等。
上述设置方式使得所述第四导电连接部964能够补偿所述第五数据线图形985和所述第七数据线图形987在所述第五阳极图形75下方产生的段差，使得所述第五阳极图形75能够形成在相对平坦的表面上，从而使得所述第五阳极图形75具有较高的平坦度，有效减小了显示基板在显示时产生的色偏现象。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在部分所述第一子像素M1中，所述发光元件包括第一发光元件，所述第一发光元件包括第一阳极图形71；所述第一阳极图形71在所述基底上的正投影与所述第一数据线图形981在所述基底上的正投影不交叠。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在所述第一子像素M1中，所述第四导电连接部964包括实体部分；所述实体部分在所述基底上的正投影，与所述阳极图形在所述基底上的正投影至少部分交叠；所述阳极图形在所述基底上的正投影与所述第一数据线图形981在所述基底上的正投影不交叠，所述阳极图形在所述基底上的正投影与所述第二数据线图形982在所述基底上的正投影至少部分交叠。
具体地，在所述第一子像素M1中，所述发光元件包括第一发光元件，所述第一发光元件包括沿远离所述基底的方向依次层叠设置的第一阳极图形71、第一发光功能层和阴极。示例性的，所述第一发光元件包括红色发光元件。
示例性的，在所述第一子像素M1中，所述实体部分在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有所述第四交叠区域；所述实体部分在所述基底上的正投影与所述第一阳极图形71在所述基底上的正投影具有所述第五交叠区域。
示例性的，所述第一阳极图形71在所述基底上的正投影，与所述第一数据线图形981在所述基底上的正投影不交叠，所述第一阳极图形71的在所述基底上的正投影与沿所述第一方向相邻的第三数据线图形983在所述基底上的正投影不交叠，所述第一阳极图形71的在所述基底上的正投影与沿第二方 向相邻的第二数据线图形982在所述基底上的正投影至少部分交叠。
示例性的，所述第一阳极图形71的第一侧部在所述基底上的正投影，与沿第二方向相邻的第二数据线图形982在所述基底上的正投影交叠；所述第一阳极图形71的第二侧部在所述基底上的正投影，与该第二数据线图形982沿第一方向相邻的第八数据线图形988在所述基底上的正投影交叠；所述第一侧部和所述第二侧部沿所述第一方向相对设置。
上述设置方式使得所述第二数据线图形982，以及所述第八数据线图形988，能够补偿彼此在所述第一阳极图形71下方产生的段差，使得所述第一阳极图形71能够形成在相对平坦的表面上，从而使得所述第一阳极图形71具有较高的平坦度，有效减小了显示基板在显示时产生的色偏现象。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在部分所述第二子像素中，所述发光元件包括第二发光元件，所述第二发光元件包括第二阳极图形72；所述第二阳极图形72在所述基底上的正投影，与所述第二数据线图形982在所述基底上的正投影交叠。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在所述第二子像素M2中，所述第四导电连接部964包括实体部分和镂空部分；
所述实体部分在所述基底上的正投影，以及所述镂空部分在所述基底上的正投影均与所述阳极图形在所述基底上的正投影至少部分交叠；
所述阳极图形在所述基底上的正投影与所述第二数据线图形982在所述基底上的正投影至少部分交叠。
具体地，在所述第二子像素M2中，所述发光元件包括第二发光元件，所述第二发光元件包括沿远离所述基底的方向依次层叠设置的第二阳极图形72、第二发光功能层和阴极。示例性的，所述第二发光元件包括蓝色发光元件。
示例性的，在所述第二子像素M2中，所述实体部分9641在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有所述第四交叠区域；所述实体部分9641在所述基底上的正投影与所述第二阳极图形72在所述基底上的正投影具有所述第五交叠区域。
示例性的，所述第二阳极图形72的第二侧部在所述基底上的正投影，与 其所属的子像素中的所述第二数据线图形982在所述基底上的正投影至少部分交叠，所述第二阳极图形72的第二侧部在所述基底上的正投影，与所述实体部分在所述基底上的正投影，以及所述镂空部分在所述基底上的正投影均交叠；所述第二阳极图形72的第一侧部在所述基底上的正投影，与沿第二方向相邻的第一数据线图形981在所述基底上的正投影交叠，且与该第一数据线图形981沿第二方向相邻的第三数据线图形983所述基底上的正投影交叠。所述第一侧部和所述第二侧部沿所述第一方向相对设置。
示例性的，所述镂空部分9642形成为口字型，所述第二阳极图形72的第二侧部在所述基底上的正投影，与所述镂空部分9642中沿所述第一方向相对的两边在所述基底上的正投影均交叠。示例性的，所述第二阳极图形72的第二侧部在所述基底上的正投影，与所述镂空部分9642中沿所述第二方向相对的两边在所述基底上的正投影均交叠。
上述设置方式使得所述第四导电连接部964和所述第二数据线图形982，能够补偿所述第一数据线图形981，以及所述第三数据线图形983的延长部分在所述第二阳极图形72下方产生的段差，使得所述第二阳极图形72能够形成在相对平坦的表面上，从而使得所述第二阳极图形72具有较高的平坦度，有效减小了显示基板在显示时产生的色偏现象。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在所述第六子像素M6中，所述第四导电连接部964包括实体部分；
所述实体部分在所述基底上的正投影，与所述阳极图形在所述基底上的正投影至少部分交叠；
所述阳极图形在所述基底上的正投影与所述第六数据线图形986在所述基底上的正投影至少部分交叠，所述阳极图形在所述基底上的正投影与沿所述第一方向相邻的第四数据线图形984在所述基底上的正投影至少部分交叠。
具体地，在所述第六子像素M6中，所述发光元件包括第六发光元件，所述第六发光元件包括沿远离所述基底的方向依次层叠设置的第六阳极图形76、第六发光功能层和阴极。示例性的，所述第六发光元件包括红色发光元件。
示例性的，在所述第六子像素M6中，所述实体部分在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有所述第四交叠区域；所述实体部分在所述基底上的正投影与所述第六阳极图形76在所述基底上的正投影具有所述第五交叠区域。
示例性的，所述第六阳极图形76的第一侧部在所述基底上的正投影与所述第六数据线图形986在所述基底上的正投影至少部分交叠，所述第六阳极图形76的第二侧部在所述基底上的正投影与沿所述第一方向相邻的第四数据线图形984在所述基底上的正投影至少部分交叠。所述第一侧部和所述第二侧部沿所述第一方向相对设置。
上述设置方式使得所述第六数据线图形986和所述第四数据线图形984，能够补偿彼此在所述第六阳极图形76下方产生的段差，使得所述第六阳极图形76能够形成在相对平坦的表面上，从而使得所述第六阳极图形76具有较高的平坦度，有效减小了显示基板在显示时产生的色偏现象。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在部分所述第三子像素M3中，所述发光元件包括第三发光元件，所述第三发光元件包括第三阳极图形73；所述第四导电连接部964包括实体部分9641和镂空部分9642；
所述第三阳极图形73在所述基底上的正投影与所述第三数据线图形983在所述基底上的正投影交叠，且与该第三数据线图形983沿第一方向相邻的数据线图形在所述基底上的正投影交叠；
所述第三阳极图形73在所述基底上的正投影与所述实体部分9641在所述基底上的正投影交叠；和/或，所述第三阳极图形73在所述基底上的正投影与所述镂空部分9642在所述基底上的正投影交叠。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在所述第三子像素M3中，所述第四导电连接部964包括实体部分9641和镂空部分9642；
所述实体部分9641在所述基底上的正投影，以及所述镂空部分9642在所述基底上的正投影均与所述阳极图形在所述基底上的正投影至少部分交叠；
所述阳极图形在所述基底上的正投影与所述第三数据线图形983在所述基底上的正投影至少部分交叠。
具体地，在所述第三子像素M3中，所述发光元件包括第三发光元件，所述第三发光元件包括沿远离所述基底的方向依次层叠设置的第三阳极图形73、第三发光功能层和阴极。示例性的，所述第三发光元件包括绿色发光元件。
示例性的，在部分所述第三子像素M3中，所述实体部分9641在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有所述第四交叠区域；所述实体部分9641在所述基底上的正投影与所述第三阳极图形73在所述基底上的正投影具有所述第五交叠区域。
示例性的，所述第三阳极图形73的第二侧部在所述基底上的正投影，与其所属的子像素中的所述第三数据线图形983在所述基底上的正投影至少部分交叠，所述第三阳极图形73的第二侧部在所述基底上的正投影，与沿所述第一方向相邻的第一数据线981在所述基底上的正投影至少部分交叠；所述第三阳极图形73的第一侧部在所述基底上的正投影，与所述实体部分在所述基底上的正投影，以及所述镂空部分在所述基底上的正投影均交叠；所述第一侧部和所述第二侧部沿所述第一方向相对设置。
示例性的，所述镂空部分9642形成为口字型，所述第三阳极图形73的第一侧部在所述基底上的正投影，与所述镂空部分9642中沿所述第一方向相对的两边在所述基底上的正投影均交叠。
上述设置方式使得所述第四导电连接部964能够补偿所述第一数据线图形981，以及所述第三数据线图形983在所述第三阳极图形73下方产生的段差，使得所述第三阳极图形73能够形成在相对平坦的表面上，从而使得所述第五阳极图形75具有较高的平坦度，有效减小了显示基板在显示时产生的色偏现象。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在所述第七子像素M7中，所述第四导电连接部包括实体部分和镂空部分；
所述实体部分在所述基底上的正投影，与所述阳极图形在所述基底上的正投影至少部分交叠，所述镂空部分在所述基底上的正投影，与所述阳极图 形在所述基底上的正投影不交叠；
所述阳极图形在所述基底上的正投影与所述第七数据线图形987在所述基底上的正投影至少部分交叠，所述阳极图形在所述基底上的正投影与沿所述第一方向相邻的第五数据线图形985在所述基底上的正投影至少部分交叠。
具体地，在所述第七子像素M7中，所述发光元件包括第七发光元件，所述第七发光元件包括沿远离所述基底的方向依次层叠设置的第七阳极图形77、第七发光功能层和阴极。示例性的，所述第七发光元件包括绿色发光元件。
示例性的，在所述第七子像素M7中，所述实体部分9641在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有所述第四交叠区域；所述实体部分9641在所述基底上的正投影与所述第七阳极图形77在所述基底上的正投影具有所述第五交叠区域。
示例性的，所述第七阳极图形77的第二侧部在所述基底上的正投影，与其所属的子像素中的所述第七数据线图形987在所述基底上的正投影至少部分交叠，所述第七阳极图形77的第二侧部在所述基底上的正投影，与沿所述第一方向相邻的第五数据线图形985在所述基底上的正投影至少部分交叠；所述第七阳极图形77的第一侧部在所述基底上的正投影，与所述实体部分在所述基底上的正投影交叠；所述第一侧部和所述第二侧部沿所述第一方向相对设置。
上述设置方式使得所述第四导电连接部964能够补偿所述第七数据线图形987，以及所述第五数据线图形985在所述第七阳极图形77下方产生的段差，使得所述第七阳极图形77能够形成在相对平坦的表面上，从而使得所述第七阳极图形77具有较高的平坦度，有效减小了显示基板在显示时产生的色偏现象。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在所述第八子像素M8中，所述第四导电连接部964包括实体部分9641和镂空部分9642；
所述实体部分9641在所述基底上的正投影，以及所述镂空部分9642在 所述基底上的正投影均与所述阳极图形在所述基底上的正投影至少部分交叠；
所述阳极图形在所述基底上的正投影与所述第八数据线图形988在所述基底上的正投影不交叠，与沿所述第一方向相邻的第六数据线图形986在所述基底上的正投影不交叠。
具体地，在所述第八子像素M8中，所述发光元件包括第八发光元件，所述第八发光元件包括沿远离所述基底的方向依次层叠设置的第八阳极图形78、第八发光功能层和阴极。示例性的，所述第八发光元件包括绿色发光元件。
示例性的，在部分所述第八子像素M8中，所述实体部分9641在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有所述第四交叠区域；所述实体部分9641在所述基底上的正投影与所述第八阳极图形78在所述基底上的正投影具有所述第五交叠区域。
示例性的，所述第八阳极图形78的第二侧部在所述基底上的正投影，与其沿第二方向相邻的第七数据线图形987在所述基底上的正投影至少部分交叠；所述第八阳极图形78的第二侧部在所述基底上的正投影，与该第七数据线图形987沿第一方向相邻的第五数据线图形985在所述基底上的正投影至少部分交叠；所述第八阳极图形78的第一侧部在所述基底上的正投影，与所述实体部分在所述基底上的正投影交叠，还与所述镂空部分在所述基底上的正投影交叠；所述第一侧部和所述第二侧部沿所述第一方向相对设置。
上述设置方式使得所述第四导电连接部964能够补偿所述第七数据线图形987，以及所述第五数据线图形985在所述第八阳极图形78下方产生的段差，使得所述第八阳极图形78能够形成在相对平坦的表面上，从而使得所述第八阳极图形78具有较高的平坦度，有效减小了显示基板在显示时产生的色偏现象。
如图11、图12、图13a、图14和图15所示，在一些实施例中，在所述第四子像素M4中，所述第四导电连接部964包括实体部分9641和镂空部分9642；
所述实体部分9641在所述基底上的正投影，与所述阳极图形在所述基底 上的正投影至少部分交叠，所述镂空部分9642在所述基底上的正投影，与所述阳极图形在所述基底上的正投影不交叠；
所述阳极图形在所述基底上的正投影与所述第四数据线图形984在所述基底上的正投影不交叠，所述阳极图形在所述基底上的正投影与沿所述第一方向相邻的第二数据线图形982在所述基底上的正投影不交叠。
具体地，在所述第四子像素M4中，所述发光元件包括第四发光元件，所述第四发光元件包括沿远离所述基底的方向依次层叠设置的第四阳极图形74、第四发光功能层和阴极。示例性的，所述第四发光元件包括绿色发光元件。
示例性的，在所述第四子像素M4中，所述实体部分9641在所述基底上的正投影与所述第三导电连接部963在所述基底上的正投影具有所述第四交叠区域；所述实体部分9641在所述基底上的正投影与所述第四阳极图形74在所述基底上的正投影具有所述第五交叠区域。
示例性的，所述第四阳极图形74的第二侧部在所述基底上的正投影，与其沿第二方向相邻的第三数据线图形983在所述基底上的正投影至少部分交叠；所述第四阳极图形74的第二侧部在所述基底上的正投影，与该第三数据线图形983沿第一方向相邻的第一数据线图形981在所述基底上的正投影至少部分交叠；所述第四阳极图形74的第一侧部在所述基底上的正投影，与所述实体部分在所述基底上的正投影交叠，且与所述镂空部分在所述基底上的正投影不交叠；所述第一侧部和所述第二侧部沿所述第一方向相对设置。
上述设置方式使得所述第四导电连接部964能够补偿所述第一数据线图形981，以及所述第三数据线图形983在所述第四阳极图形74下方产生的段差，使得所述第四阳极图形74能够形成在相对平坦的表面上，从而使得所述第四阳极图形74具有较高的平坦度，有效减小了显示基板在显示时产生的色偏现象。
值得注意，图16为图12中有源层的布局示意图；图17为图12中第一栅金属层的布局示意图；图18为图12中第二栅金属层的布局示意图；图19为图12中第一源漏金属层的布局示意图。所述有源层、所述第一栅金属层、所述第二栅金属层和所述第一源漏金属层沿远离所述基底的方向依次层叠设 置。
如图2、图5和图12所示，在一些实施例中，所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4均包括：发光元件、栅线图形92和发光控制信号线图形93；所述栅线图形92的至少部分和所述发光控制信号线图形93的至少部分均沿所述第一方向延伸；
在所述第一子像素M1、所述第二子像素M2、所述第三子像素M3和所述第四子像素M4中，所述子像素驱动电路还包括：第一晶体管T1、数据写入晶体管(即第四晶体管T4)、第五晶体管T5、第六晶体管T6、第二复位晶体管(即第七晶体管T7)和存储电容Cst；
所述驱动晶体管的栅极与所述第一晶体管T1的第二极电连，所述驱动晶体管的第一极与所述第五晶体管T5的第二极电连，所述驱动晶体管的第二极与所述第一晶体管T1的第一极电连；
所述第一晶体管T1的栅极与所述栅线图形92电连；
所述数据写入晶体管的栅极与所述栅线图形92电连，所述数据写入晶体管的第一极与其所属子像素中的数据线图形电连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连；
所述第五晶体管T5的栅极与所述发光控制信号线图形93电连，所述第五晶体管T5的第一极与所述电源信号线图形91电连；
所述第六晶体管T6的栅极与所述发光控制信号线图形93电连，所述第六晶体管T6的第一极与所述驱动晶体管的第二极电连，所述第六晶体管T6的第二极与所述发光元件包括的阳极图形电连；
第二复位晶体管的栅极与沿所述第二方向相邻的下一个子像素中的复位信号线图形95'电连，所述第二复位晶体管的第一极与沿所述第二方向相邻的下一个子像素中的所述初始化信号线图形94'电连，所述第二复位晶体管的第二极与所述阳极图形电连；
所述存储电容的第一极板复用为驱动晶体管的栅极，存储电容的第二极板与所述电源信号线图形91电连。
示例性的，显示基板中每个子像素均包括子像素驱动电路，每个子像素驱动电路均包括：第一晶体管T1、第二晶体管T2、驱动晶体管(如第三晶 体管)、数据写入晶体管(如第四晶体管)、第五晶体管T5、第六晶体管T6、第七晶体管T7、存储电容Cst、第一导电连接部961、第二导电连接部962、第三导电连接部963、第四导电连接部964和第五导电连接部965等。
具体地，所述多个子像素能够划分为沿所述第二方向依次排列的多行子像素，以及沿所述第一方向依次排列的多列子像素，位于同一行的子像素包括的所述初始化信号线图形94依次电连接，形成为一体结构；位于同一行的子像素包括的所述栅线图形92依次电连接，形成为一体结构；位于同一行的子像素包括的所述发光控制信号线图形93依次电连接，形成为一体结构；位于同一行的子像素包括的所述复位信号线图形95依次电连接，形成为一体结构；位于同一列的子像素包括的第一数据线图形981依次电连接，形成为一体结构；位于同一列的子像素包括的第二数据线图形982依次电连接，形成为一体结构；位于同一列的子像素包括的所述电源信号线图形91依次电连接，形成为一体结构。
如图2所示，以一个子像素驱动电路为例，该子像素驱动电路包括7个薄膜晶体管和1个电容。该子像素驱动电路包括的各晶体管均采用P型晶体管，每个晶体管的第一极包括源极，每个晶体管的第二极包括漏极。
第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与栅线图形92电连，第一晶体管T1的源极S1与第三晶体管T3(即驱动晶体管)的漏极D3电连，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g电连。
第二晶体管T2(即第一复位晶体管)为双栅结构，第二晶体管T2的栅极202g与所述复位信号线图形95电连，第二晶体管T2的源极S2与所述初始化信号线图形94电连，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g电连。
第四晶体管T4(即数据写入晶体管)的栅极204g与所述栅线图形92电连，第四晶体管T4的源极S4与第一数据线图形981或第二数据线图形982电连，第四晶体管T4的漏极D4与第三晶体管T3的源极S3电连。
第五晶体管T5的栅极205g与发光控制信号线图形93电连，第五晶体管T5的源极S5与电源信号线图形91电连，第五晶体管T5的漏极D5与第三晶体管T3的源极S3电连。
第六晶体管T6的栅极206g与发光控制信号线图形93电连，第六晶体管T6的源极S6与第三晶体管T3的漏极D3电连，第六晶体管T6的漏极D6与发光元件EL的阳极电连。
第七晶体管T7(即第二复位晶体管)的栅极207g与沿所述第二方向相邻的下一个子像素中的复位信号线图形95'电连，第七晶体管T7的漏极D7与对应的发光元件EL的阳极电连，第七晶体管T7的源极S7与沿所述第二方向相邻的下一个子像素中的所述初始化信号线图形94'电连。
存储电容Cst的第一极板Cst1复用为第三晶体管T3的栅极203g，存储电容Cst的第二极板Cst2与所述电源信号线图形91电连。
如图3所示，上述结构的子像素驱动电路在工作时，每个工作周期均包括复位时段P1、写入补偿时段P2和发光时段P3。图3中，E1代表当前子像素中的发光控制信号线图形93上传输的发光控制信号，R1代表当前子像素中的复位信号线图形95上传输的复位信号，D1代表当前子像素中的目标数据线图形上传输的数据信号，G1代表当前子像素中的栅线图形92上传输的栅极扫描信号，R1'代表当前子像素沿所述第二方向相邻的下一个子像素中的复位信号线图形95'上传输的复位信号。
在所述第一复位时段P1，所述复位信号线图形95输入的复位信号处于有效电平，第二晶体管T2导通，将由所述初始化信号线图形94传输的初始化信号输入至第三晶体管T3的栅极203g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位。
在写入补偿时段P2，所述复位信号线图形95输入的复位信号处于非有效电平，第二晶体管T2截止，栅线图形92输入的栅极扫描信号处于有效电平，控制第一晶体管T1和第四晶体管T4导通，目标数据线图形写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的源极S3，同时，第一晶体管T1和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在写入补偿时段P2，复位信号线图形95'输入的复位信号处于有效电平，控制第七晶体管T7导通，由所述初始化信号线图形94'传输的初始化信号输入至发光元件EL的阳极，控制发光元件EL不发光。
在发光时段P3，发光控制信号线图形93写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源信号线图形91传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极，驱动对应的发光元件EL发光。
如图6～8、图10～图13所示，在制作上述子像素时，子像素对应的各膜层的布局如下：
沿远离基底的方向上依次层叠设置的有源膜层、第一栅极绝缘层GI1、第一栅金属层、第二栅极绝缘层GI2、第二栅金属层、层间绝缘层ILD、第一源漏金属层、第一平坦层PLN1、第二源漏金属层、第二平坦层PLN2和阳极层。
如图6所示，有源膜层用于形成子像素驱动电路中各晶体管的沟道区(被各晶体管的栅极覆盖的部分)，源极(如：S1～S7)和漏极(如：D1～D7)，源极和漏极对应的有源膜层由于掺杂作用，导电性能会优于沟道区对应的有源膜层；有源膜层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极和漏极可掺杂有n型杂质或p型杂质。
如图6所示，第一栅金属层用于形成子像素驱动电路中各晶体管的栅极(如：201g～207g)，以及子像素包括的栅线图形92、发光控制信号线图形93、复位信号线图形95等结构，每个子像素驱动电路中的第三晶体管T3的栅极203g均复用为该子像素驱动电路中的第二存储电容Cst的第一极板Cst1。
如图7所示，第二栅金属层用于形成第二存储电容Cst的第二极板Cst2，子像素包括的初始化信号线图形94，以及屏蔽图形80。
如图8所示，第一源漏金属层用于形成子像素包括的电源信号线图形91，电源补偿图形和一些导电连接部。
如图11所示，第二源漏金属层用于形成子像素包括的第一数据线图形981、第二数据线图形982和一些导电连接部。
另外，如图5所示，本公开提供的显示基板中，在第二方向上，第四晶体管T4的栅极204g、第一晶体管T1的栅极201g和第二晶体管T2的栅极202g均位于驱动晶体管的栅极(即第三晶体管T3的栅极203g)的第一侧，第七晶体管T7的栅极、第六晶体管T6的栅极206g、第五晶体管T5的栅极均位于驱动晶体管的栅极的第二侧。示例性的，所述驱动晶体管的栅极的第一侧和第二侧为沿第二方向相对的两侧，进一步地，驱动晶体管的栅极的第一侧可以为驱动晶体管的栅极的上侧，驱动晶体管的栅极的第二侧可以为驱动晶体管的栅极的下侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管的栅极的下侧，为驱动晶体管的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管的栅极的更远离IC的一侧。
在第一方向上，第四晶体管T4的栅极204g和第五晶体管T5的栅极205g均位于驱动晶体管的栅极的第三侧，第一晶体管T1的栅极201g和第六晶体管T6的栅极206g均位于驱动晶体管的栅极的第四侧。示例性的，驱动晶体管的栅极的第三侧和第四侧为沿第一方向相对的两侧；进一步地，驱动晶体管的栅极的第三侧可以为驱动晶体管的栅极的右侧，驱动晶体管的栅极的第四侧可以为驱动晶体管的栅极的左侧。所述左侧和右侧，例如在同一子像素中，第二数据线图形982位于驱动晶体管的栅极右侧，第一数据线图形981位于驱动晶体管的栅极左侧。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
上述实施例提供的显示基板中，通过设置所述屏蔽图形80在所述基底上的正投影与所述第一复位晶体管的第一极在所述基底上的正投影交叠，使得所述屏蔽图形80屏蔽了由于数据信号跳变对第一复位晶体管的第一极产生的干扰，进而避免了由于数据信号跳变对初始化信号线图形94上传输的初始化信号产生影响，有效提升了显示基板的显示效果。另外，上述将所述屏蔽图形80与所述电源信号线图形91电连，使得所述屏蔽图形80具有与电源信号线图形91传输的电源信号相同的稳定电位，这样不仅有利于所述子像素驱 动电路处于稳定的工作状态，还更好的保证了所述屏蔽图形80的屏蔽效果。
因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，能够实现较高的画面显示质量。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，包括：在基底上制作阵列分布的多个子像素，制作所述子像素的步骤具体包括：
制作初始化信号线图形94，所述初始化信号线图形94的至少部分沿第一方向延伸；
制作复位信号线图形95，所述复位信号线图形95的至少部分沿所述第一方向延伸；
制作电源信号线图形91，所述电源信号线图形91的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
制作子像素驱动电路，所述子像素驱动电路包括驱动晶体管和第一复位晶体管，所述第一复位晶体管的栅极与所述复位信号线图形95电连，所述第一复位晶体管的第一极与所述初始化信号线图形94电连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连；
制作屏蔽图形80，所述屏蔽图形80与所述电源信号线图形91电连，所述屏蔽图形80在所述基底上的正投影与所述第一复位晶体管的第一极在所述基底上的正投影交叠。
需要说明，上述制作子像素的具体步骤的执行顺序可根据实际需要设置，并不是按照上述撰写顺序依次进行的。
采用本公开实施例提供的制作方法制作的显示基板中，通过设置所述屏蔽图形80在所述基底上的正投影与所述第一复位晶体管的第一极在所述基底上的正投影交叠，使得所述屏蔽图形80屏蔽了由于数据信号跳变对第一复位晶体管的第一极产生的干扰，进而避免了由于数据信号跳变对初始化信号线图形94上传输的初始化信号产生影响，有效提升了显示基板的显示效果。另外，上述将所述屏蔽图形80与所述电源信号线图形91电连，使得所述屏蔽图形80具有与电源信号线图形91传输的电源信号相同的稳定电位，这样 不仅有利于所述子像素驱动电路处于稳定的工作状态，还更好的保证了所述屏蔽图形80的屏蔽效果。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种显示基板，包括：基底和阵列分布在所述基底上的多个子像素，所述子像素包括：
    初始化信号线图形，所述初始化信号线图形的至少部分沿第一方向延伸；
    复位信号线图形，所述复位信号线图形的至少部分沿所述第一方向延伸；
    电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
    子像素驱动电路，所述子像素驱动电路包括驱动晶体管和第一复位晶体管，所述第一复位晶体管的栅极与所述复位信号线图形电连，所述第一复位晶体管的第一极与所述初始化信号线图形电连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连；
    屏蔽图形，所述屏蔽图形与所述电源信号线图形电连，所述屏蔽图形在所述基底上的正投影与所述第一复位晶体管的第一极在所述基底上的正投影交叠。
  2. 根据权利要求1所述的显示基板，其中，所述屏蔽图形在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影不交叠。
  3. 根据权利要求1所述的显示基板，其中，所述屏蔽图形在所述基底上的正投影与所述第一复位晶体管的第二极在所述基底上的正投影交叠。
  4. 根据权利要求1所述的显示基板，其中，所述多个子像素包括：
    沿第二方向设置的第一子像素和第二子像素，所述第一子像素包括第一数据线图形，所述第二子像素包括第二数据线图形，所述第一数据线图形的至少部分和所述第二数据线图形的至少部分均沿第二方向延伸，所述第一数据线图形位于沿所述第二方向延伸的同一列所述第一子像素的第一侧，所述第二数据线图形位于沿所述第二方向延伸的同一列所述第二子像素的第二侧，所述第一侧与所述第二侧沿第一方向相对，所述第一方向与所述第二方向相交；
    沿第二方向设置的第三子像素和第四子像素，沿所述第一方向，所述第 三子像素与所述第一子像素位于同一行，所述第四子像素与所述第二子像素位于同一行；所述第三子像素包括第三数据线图形，所述第四子像素包括第四数据线图形，所述第三数据线图形的至少部分和所述第四数据线图形的至少部分均沿第二方向延伸，所述第三数据线图形位于沿所述第二方向延伸的同一列第三子像素的第二侧，所述第四数据线图形位于沿所述第二方向延伸的同一列第四子像素的第一侧。
  5. 根据权利要求4所述的显示基板，其中，
    所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括第一导电连接部和第五导电连接部；
    在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中：
    所述子像素驱动电路均包括数据写入晶体管；
    所述第一导电连接部分别与对应的数据线图形和数据写入晶体管的第一极电连；所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连；
    所述第一复位晶体管的第二极通过所述第五导电连接部与所述驱动晶体管的栅极电连；
    所述屏蔽图形在所述基底上的正投影与所述第一导电连接部在所述基底上的正投影至少部分交叠。
  6. 根据权利要求5所述的显示基板，其中，所述屏蔽图形的至少部分在所述基底上的正投影，位于所述第一导电连接部在所述基底上的正投影与所述第五导电连接部在所述基底上的正投影之间。
  7. 根据权利要求4所述的显示基板，其中，在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中：
    所述子像素驱动电路均包括第一晶体管，所述第一晶体管的第一极与所述驱动晶体管的第二极电连，所述第一晶体管的第二极与所述驱动晶体管的栅极电连；
    所述第一晶体管的有源图形包括间隔设置的两个半导体部分，以及分别连接所述两个半导体部分的第一导体部分；
    所述屏蔽图形在所述基底上的投影还与所述第一导体部分在所述基底上 的正投影至少部分交叠。
  8. 根据权利要求5所述的显示基板，其中，沿垂直于所述基底的方向上，所述屏蔽图形位于所述第一复位晶体管的第一极与所述第一导电连接部之间。
  9. 根据权利要求4所述的显示基板，其中，在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述电源信号线图形均包括：相电连的电源主体部分和电源突出部分；
    在所述第一子像素中，所述电源突出部分在所述基底上的正投影与所述第一数据线图形在所述基底上的正投影交叠，所述电源主体部分在所述基底上的正投影与沿所述第一方向相邻的数据线图形在所述基底上的正投影至少部分交叠。
  10. 根据权利要求4所述的显示基板，其中，在所述第二子像素中，所述电源突出部分在所述基底上的正投影与所述第二数据线图形在所述基底上的正投影不交叠。
  11. 根据权利要求4所述的显示基板，其中，在所述第三子像素中，所述电源突出部分在所述基底上的正投影与所述第三数据线图形在所述基底上的正投影不交叠。
  12. 根据权利要求4所述的显示基板，其中，在所述第四子像素中，所述电源突出部分在所述基底上的正投影与所述第四数据线图形在所述基底上的正投影交叠，所述电源主体部分在所述基底上的正投影与沿所述第一方向相邻的数据线图形在所述基底上的正投影交叠。
  13. 根据权利要求4所述的显示基板，其中，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括：
    电源补偿图形，所述电源补偿图形的至少部分沿所述第一方向延伸，所述电源信号线图形和所述电源补偿图形均位于所述第一数据线图形、所述第二数据线图形、所述第三数据线图形和所述第四数据线图形靠近所述基底的一侧；
    所述电源补偿图形分别与其所属子像素中的电源信号线图形，以及沿所述第一方向相邻子像素中的电源信号线图形电连。
  14. 根据权利要求13所述的显示基板，其中，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括：沿第二方向分布的所述复位信号线图形、栅线图形和发光控制信号线图形；所述栅线图形的至少部分沿所述第一方向延伸，所述发光控制信号线图形的至少部分沿第一方向延伸；
    在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述电源补偿图形在所述基底上的正投影，位于所述栅线图形在所述基底上的正投影与所述发光控制信号线图形在所述基底上的正投影之间。
  15. 根据权利要求13所述的显示基板，其中，在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述电源信号线图形均包括：相电连的电源主体部分和电源突出部分，所述电源突出部分与所述电源主体部分之间具有间隙；
    所述电源补偿图形的第一端与其所属子像素中的所述电源突出部分电连；所述电源补偿图形的第二端与沿所述第一方向相邻子像素中的电源主体部分电连。
  16. 根据权利要求4所述的显示基板，其中，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括：第六晶体管，以及沿远离所述基底的方向层叠设置的第三导电连接部、第四导电连接部和发光元件；所述发光元件包括阳极图形；在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述第六晶体管的第一极与所述驱动晶体管的第二极连接；所述第六晶体管的第二极通过所述第三导电连接部、第四导电连接部和所述发光元件电连。
  17. 根据权利要求16所述的显示基板，其中，在部分所述第一子像素中，所述发光元件包括第一发光元件，所述第一发光元件包括第一阳极图形；
    所述第一阳极图形在所述基底上的正投影与所述第一数据线图形在所述基底上的正投影不交叠。
  18. 根据权利要求16所述的显示基板，其中，在部分所述第三子像素中，所述发光元件包括第三发光元件，所述第三发光元件包括第三阳极图形；
    所述第四导电连接部包括实体部分和镂空部分；
    所述第三阳极图形在所述基底上的正投影与所述第三数据线图形在所述基底上的正投影交叠，且与该第三数据线图形沿第一方向相邻的数据线图形在所述基底上的正投影交叠；
    所述第三阳极图形在所述基底上的正投影与所述实体部分在所述基底上的正投影交叠；和/或，所述第三阳极图形在所述基底上的正投影与所述镂空部分在所述基底上的正投影交叠。
  19. 根据权利要求16所述的显示基板，其中，在部分所述第二子像素中，所述发光元件包括第二发光元件，所述第二发光元件包括第二阳极图形；
    所述第二阳极图形在所述基底上的正投影，与所述第二数据线图形在所述基底上的正投影交叠。
  20. 根据权利要求4所述的显示基板，其中，所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素均包括：发光元件、栅线图形和发光控制信号线图形；所述栅线图形的至少部分和所述发光控制信号线图形的至少部分均沿所述第一方向延伸；
    在所述第一子像素、所述第二子像素、所述第三子像素和所述第四子像素中，所述子像素驱动电路还包括：第一晶体管、数据写入晶体管、第五晶体管、第六晶体管、第二复位晶体管和存储电容；
    所述驱动晶体管的栅极与所述第一晶体管的第二极电连，所述驱动晶体管的第一极与所述第五晶体管的第二极电连，所述驱动晶体管的第二极与所述第一晶体管的第一极电连；
    所述第一晶体管的栅极与所述栅线图形电连；
    所述数据写入晶体管的栅极与所述栅线图形电连，所述数据写入晶体管的第一极与其所属子像素中的数据线图形电连，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连；
    所述第五晶体管的栅极与所述发光控制信号线图形电连，所述第五晶体管的第一极与所述电源信号线图形电连；
    所述第六晶体管的栅极与所述发光控制信号线图形电连，所述第六晶体管的第一极与所述驱动晶体管的第二极电连，所述第六晶体管的第二极与所述发光元件包括的阳极图形电连；
    第二复位晶体管的栅极与沿所述第二方向相邻的下一个子像素中的复位信号线图形电连，所述第二复位晶体管的第一极与沿所述第二方向相邻的下一个子像素中的所述初始化信号线图形电连，所述第二复位晶体管的第二极与所述阳极图形电连；
    所述存储电容的第一极板复用为所述驱动晶体管的栅极，所述存储电容的第二极板与所述电源信号线图形电连。
  21. 一种显示装置，包括如权利要求1～20中任一项所述的显示基板。
  22. 一种显示基板的制作方法，包括：在基底上制作阵列分布的多个子像素，制作所述子像素的步骤具体包括：
    制作初始化信号线图形，所述初始化信号线图形的至少部分沿第一方向延伸；
    制作复位信号线图形，所述复位信号线图形的至少部分沿所述第一方向延伸；
    制作电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；
    制作子像素驱动电路，所述子像素驱动电路包括驱动晶体管和第一复位晶体管，所述第一复位晶体管的栅极与所述复位信号线图形电连，所述第一复位晶体管的第一极与所述初始化信号线图形电连，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连；
    制作屏蔽图形，所述屏蔽图形与所述电源信号线图形电连，所述屏蔽图形在所述基底上的正投影与所述第一复位晶体管的第一极在所述基底上的正投影交叠。
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