WO2021102905A9 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021102905A9
WO2021102905A9 PCT/CN2019/121950 CN2019121950W WO2021102905A9 WO 2021102905 A9 WO2021102905 A9 WO 2021102905A9 CN 2019121950 W CN2019121950 W CN 2019121950W WO 2021102905 A9 WO2021102905 A9 WO 2021102905A9
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WIPO (PCT)
Prior art keywords
transistor
line pattern
substrate
pattern
signal line
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PCT/CN2019/121950
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English (en)
French (fr)
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WO2021102905A1 (zh
Inventor
刁永富
陈祯祐
许标
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/121950 priority Critical patent/WO2021102905A1/zh
Priority to US17/254,168 priority patent/US20210335989A1/en
Priority to CN201980002673.1A priority patent/CN113853643B/zh
Priority to EP19950228.7A priority patent/EP4068259A4/en
Publication of WO2021102905A1 publication Critical patent/WO2021102905A1/zh
Publication of WO2021102905A9 publication Critical patent/WO2021102905A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • Organic Light-Emitting Diode (English: Organic Light-Emitting Diode, abbreviated as: OLED) display products are widely used in various fields due to their advantages of high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency.
  • the purpose of the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display substrate including: a substrate and a plurality of sub-pixels arranged in an array on the substrate; the sub-pixels include:
  • a data line pattern extending along the first direction
  • An initialization signal line pattern includes a portion extending in a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;
  • a sub-pixel driving circuit includes: a driving transistor, a first transistor coupled to the gate of the driving transistor, and a first shielding member coupled to the initialization signal line pattern, the first The orthographic projection of a shielding component on the substrate is located between the orthographic projection of the first transistor on the substrate and the orthographic projection of the target data line pattern on the substrate; The next sub-pixel adjacent to the sub-pixel includes the target data line pattern.
  • the plurality of sub-pixels includes a plurality of rows of sub-pixels, each row of sub-pixels includes a plurality of the sub-pixels arranged along the second direction, and the initialization signal line patterns in the same row of sub-pixels are sequentially Coupled to form an initialization signal line corresponding to the row of sub-pixels;
  • the first shielding member extends along the first direction and is coupled to at least one of the initialization signal lines.
  • the first shielding component is coupled to two adjacent initialization signal lines.
  • the first shielding component and the initialization signal line pattern are arranged in different layers, and the orthographic projection of the first shielding component on the substrate is opposite to the orthographic projection of the initialization signal line pattern on the substrate.
  • the first shielding component and the data line pattern are made of the same material.
  • the display substrate includes a first interlayer insulating layer, and the first shielding member and the data line pattern are both located on a surface of the first interlayer insulating layer facing away from the substrate.
  • the sub-pixel driving circuit further includes a second transistor coupled to the gate of the driving transistor, and the second transistor includes:
  • the orthographic projection of the third conductor pattern on the substrate, the orthographic projection of the first grid pattern on the substrate, and the orthographic projection of the second grid pattern on the substrate do not overlap ;
  • the orthographic projection of the third conductor pattern on the substrate at least partially overlaps the orthographic projection of the initialization signal line pattern on the substrate.
  • the sub-pixel driving circuit further includes a first extension portion extending from the first semiconductor pattern, and the conductivity of the first extension portion is better than that of the first semiconductor pattern;
  • the first extension portion includes a first part, a second part, and a third part, the first part and the third part all extend in the first direction, and the second part extends in the second direction, One end of the second part is coupled to the first part, and the other end of the second part is coupled to the third part;
  • An end of the third part away from the second part is coupled to the first transistor.
  • the first transistor includes:
  • the third grid pattern and the fourth grid pattern are coupled to each other, and the orthographic projection of the third grid pattern on the substrate partially overlaps the orthographic projection of the fourth semiconductor pattern on the substrate, so The orthographic projection of the fourth grid pattern on the substrate partially overlaps the orthographic projection of the fifth semiconductor pattern on the substrate;
  • the orthographic projection of the sixth conductor pattern on the substrate, the orthographic projection of the third grid pattern on the substrate, and the orthographic projection of the fourth grid pattern on the substrate do not overlap .
  • the orthographic projection of the first shielding component on the substrate at least partially overlaps the orthographic projection of the sixth conductor pattern on the substrate.
  • the sub-pixel driving circuit further includes:
  • the second shielding component coupled with the first shielding component, the orthographic projection of the second shielding component on the substrate, and the orthographic projection of the sixth conductor pattern on the substrate at least partially overlap.
  • the second shielding component and the first shielding component are arranged in different layers, and the orthographic projection of the second shielding component on the substrate and the orthographic projection of the first shielding component on the substrate There is a second overlapping area, and the second shielding member and the first shielding member are coupled through a second via provided in the second overlapping area.
  • the second shielding component and the initialization signal line pattern are made of the same material.
  • the display substrate further includes a second interlayer insulating layer, and the second shielding member and the initialization signal line pattern are both located on a surface of the second interlayer insulating layer facing away from the substrate.
  • the sub-pixel further includes a power signal line pattern
  • the power signal line pattern includes a portion extending along the first direction
  • the sub-pixel driving circuit further includes a storage capacitor, and the first in the storage capacitor One plate is multiplexed as the gate of the driving transistor, the second plate in the storage capacitor is coupled to the power signal line pattern, and the second plate in the storage capacitor is located in the second layer
  • the inter-insulating layer faces away from the surface of the substrate.
  • the sub-pixel further includes: a reset signal line pattern extending in a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:
  • a first conductive connection portion, the orthographic projection of the first conductive connection portion on the substrate covers at least part of the orthographic projection of the sixth conductor pattern on the substrate;
  • a second transistor the first electrode of the second transistor is coupled to the initialization signal line pattern through the first conductive connection portion, and the second electrode of the second transistor is coupled to the gate of the driving transistor , The gate of the second transistor is coupled to the reset signal line pattern.
  • the sub-pixel further includes: a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line The patterns all extend along the second direction, and the power signal line pattern includes a portion extending along the first direction;
  • the sub-pixel driving circuit further includes: a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to The first electrode of the first transistor is coupled;
  • the gate of the first transistor is coupled to the gate line pattern
  • the gate of the second transistor is coupled to the reset signal line pattern, the first electrode of the second transistor is coupled to the initialization signal line pattern, and the second electrode of the second transistor is coupled to the drive The gate of the transistor is coupled;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the The light-emitting element in the sub-pixel is coupled;
  • the gate of the seventh transistor is coupled to the reset signal line pattern included in the next sub-pixel adjacent along the first direction, and the first electrode of the seventh transistor is connected to the initialization signal included in the next sub-pixel
  • the line pattern is coupled, and the second electrode of the seventh transistor is coupled to the light-emitting element in the sub-pixel.
  • the sub-pixel further includes: a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line The patterns all extend in the second direction, the power signal line pattern includes a portion extending in the first direction; the orthographic projection of the first shielding member on the substrate is in line with the grid pattern The orthographic projection on the substrate and the orthographic projection of the light-emitting control signal line pattern on the substrate partially overlap.
  • a second aspect of the present disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels arranged in an array on the substrate; the sub-pixels include:
  • a data line pattern extending along the first direction
  • An initialization signal line pattern includes a portion extending in a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;
  • a sub-pixel driving circuit the sub-pixel driving circuit includes: a driving transistor, a first transistor coupled to the gate of the driving transistor, and a first shielding member coupled to the initialization signal line pattern, the first A shielding component is used to form a coupling capacitor with the first electrode of the first transistor.
  • the orthographic projection of the first shielding component on the substrate and the orthographic projection of the target data line pattern on the substrate do not overlap.
  • the next sub-pixel adjacent to the sub-pixel in two directions includes the target data line pattern.
  • the plurality of sub-pixels distributed in the array includes multiple rows of sub-pixels, each row of sub-pixels includes the sub-pixels arranged along the second direction, and the initialization signal line pattern located in the same row of sub-pixels Sequentially coupled to form an initialization signal line corresponding to the row of sub-pixels;
  • the first shielding member extends along the first direction and is coupled to at least one of the initialization signal lines.
  • the first shielding component is coupled to two adjacent initialization signal lines.
  • the first shielding component and the initialization signal line pattern are arranged in different layers, and the orthographic projection of the first shielding component on the substrate is opposite to the orthographic projection of the initialization signal line pattern on the substrate.
  • the first shielding component and the data line pattern are made of the same material.
  • the display substrate includes a first interlayer insulating layer, and the first shielding member and the data line pattern are both located on a surface of the first interlayer insulating layer facing away from the substrate.
  • the sub-pixel driving circuit further includes a second transistor coupled to the gate of the driving transistor, and the second transistor includes:
  • the first grid pattern and the second grid pattern, the orthographic projection of the first grid pattern on the substrate and the orthographic projection of the first semiconductor pattern on the substrate at least partially overlap, and the second The orthographic projection of the gate pattern on the substrate and the orthographic projection of the second semiconductor pattern on the substrate at least partially overlap;
  • the orthographic projection of the third conductor pattern on the substrate, the orthographic projection of the first grid pattern on the substrate, and the orthographic projection of the second grid pattern on the substrate do not overlap ;
  • the orthographic projection of the third conductor pattern on the substrate at least partially overlaps the orthographic projection of the initialization signal line pattern on the substrate.
  • the sub-pixel driving circuit further includes a first extension portion extending from the first semiconductor pattern, and the conductivity of the first extension portion is better than that of the first semiconductor pattern;
  • the first extension portion includes a first part, a second part, and a third part, the first part and the third part all extend in the first direction, and the second part extends in the second direction, One end of the second part is coupled to the first part, and the other end of the second part is coupled to the third part;
  • An end of the third part away from the second part is coupled to the first transistor.
  • the first transistor includes:
  • the third grid pattern and the fourth grid pattern are coupled to each other, and the orthographic projection of the third grid pattern on the substrate partially overlaps the orthographic projection of the fourth semiconductor pattern on the substrate, so The orthographic projection of the fourth grid pattern on the substrate partially overlaps the orthographic projection of the fifth semiconductor pattern on the substrate;
  • the orthographic projection of the sixth conductor pattern on the substrate, the orthographic projection of the third grid pattern on the substrate, and the orthographic projection of the fourth grid pattern on the substrate do not overlap .
  • the orthographic projection of the first shielding component on the substrate at least partially overlaps the orthographic projection of the sixth conductor pattern on the substrate.
  • the sub-pixel driving circuit further includes:
  • the second shielding component coupled with the first shielding component, the orthographic projection of the second shielding component on the substrate, and the orthographic projection of the sixth conductor pattern on the substrate at least partially overlap.
  • the second shielding component and the first shielding component are arranged in different layers, and the orthographic projection of the second shielding component on the substrate and the orthographic projection of the first shielding component on the substrate There is a second overlapping area, and the second shielding member and the first shielding member are coupled through a second via provided in the second overlapping area.
  • the second shielding component and the initialization signal line pattern are made of the same material.
  • the display substrate further includes a second interlayer insulating layer, and the second shielding member and the initialization signal line pattern are both located on a surface of the second interlayer insulating layer facing away from the substrate.
  • the sub-pixel further includes a power signal line pattern
  • the power signal line pattern includes a portion extending along the first direction
  • the sub-pixel driving circuit further includes a storage capacitor, and the first in the storage capacitor One plate is multiplexed as the gate of the driving transistor, the second plate in the storage capacitor is coupled to the power signal line pattern, and the second plate in the storage capacitor is located in the second layer
  • the inter-insulating layer faces away from the surface of the substrate.
  • the sub-pixel further includes: a reset signal line pattern extending in a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:
  • a first conductive connection portion, the orthographic projection of the first conductive connection portion on the substrate covers at least part of the orthographic projection of the sixth conductor pattern on the substrate;
  • a second transistor the first electrode of the second transistor is coupled to the initialization signal line pattern through the first conductive connection portion, and the second electrode of the second transistor is coupled to the gate of the driving transistor , The gate of the second transistor is coupled to the reset signal line pattern.
  • the sub-pixel further includes: a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line The patterns all extend along the second direction, and the power signal line pattern includes a portion extending along the first direction;
  • the sub-pixel driving circuit further includes: a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to The first electrode of the first transistor is coupled;
  • the gate of the first transistor is coupled to the gate line pattern
  • the gate of the second transistor is coupled to the reset signal line pattern, the first electrode of the second transistor is coupled to the initialization signal line pattern, and the second electrode of the second transistor is coupled to the drive The gate of the transistor is coupled;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the The light-emitting element in the sub-pixel is coupled;
  • the gate of the seventh transistor is coupled to the reset signal line pattern included in the next sub-pixel adjacent along the first direction, and the first electrode of the seventh transistor is connected to the initialization signal included in the next sub-pixel
  • the line pattern is coupled, and the second electrode of the seventh transistor is coupled to the light-emitting element in the sub-pixel.
  • the sub-pixel further includes: a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line The patterns all extend in the second direction, the power signal line pattern includes a portion extending in the first direction; the orthographic projection of the first shielding member on the substrate is in line with the grid pattern The orthographic projection on the substrate and the orthographic projection of the light-emitting control signal line pattern on the substrate partially overlap.
  • a third aspect of the present disclosure provides a display substrate including: a substrate and a plurality of sub-pixels arranged in an array on the substrate; the sub-pixels include:
  • a data line pattern extending along the first direction
  • a power signal line pattern including a portion extending along the first direction
  • a sub-pixel driving circuit includes: two switching transistors, a driving transistor, and a storage capacitor; the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the first plate of the storage capacitor is The two-electrode plate is coupled to the power signal line pattern; the second poles of the two switching transistors are both coupled to the first pole of the driving transistor, and the first pole of at least one of the two switching transistors is The orthographic projection of the diode on the substrate is at least partially overlapped with the orthographic projection of the power signal line pattern on the substrate, and is at least overlapped with the orthographic projection of the second plate of the storage capacitor on the substrate. Partially overlapped.
  • the second poles of the two switching transistors and the first pole of the driving transistor have an integrated structure, and the integrated structure includes a first conductive portion extending along the first direction, and the first conductive portion is located at the The orthographic projection on the substrate, the orthographic projection of the power signal line pattern on the substrate, and the orthographic projection of the second plate of the storage capacitor on the substrate have a first overlap area, and The first overlapping area does not overlap with the orthographic projection of the data line pattern on the substrate.
  • the orthographic projection of the first electrode of the driving transistor on the substrate is located inside the orthographic projection of the second electrode plate of the storage capacitor on the substrate.
  • the sub-pixels further include: gate line patterns and light emission control signal line patterns that both extend in a second direction, and the second direction intersects the first direction;
  • the sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switching transistors include a fourth transistor and a fifth transistor;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is coupled to the fifth transistor
  • the second electrode of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the first transistor is coupled to the gate line pattern
  • the second electrode of the first transistor is coupled to the gate of the driving transistor
  • the first electrode of the first transistor and the second electrode are coupled to the gate line pattern.
  • the first electrode of the six transistor and the second electrode of the driving transistor are formed as an integral structure, and the integral structure includes a second conductive portion extending along the first direction.
  • the gate of the sixth transistor is connected to the light emission control
  • the signal line pattern is coupled, and the second electrode of the sixth transistor is coupled to the light-emitting element in the sub-pixel;
  • the orthographic projection of the channel region of the driving transistor on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate; And along the second direction, the minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive portion on the substrate is smaller than that of the groove The minimum distance between the orthographic projection of the track area on the substrate and the orthographic projection of the second conductive portion on the substrate.
  • the sub-pixels further include: gate line patterns and light emission control signal line patterns that both extend in a second direction, and the second direction intersects the first direction;
  • the sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switching transistors include a fourth transistor and a fifth transistor;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is coupled to the fifth transistor
  • the second electrode of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the first transistor is coupled to the gate line pattern
  • the second electrode of the first transistor is coupled to the gate of the driving transistor
  • the first electrode of the first transistor and the second electrode are coupled to the gate line pattern.
  • the first electrode of the six transistor and the second electrode of the driving transistor are formed as an integral structure, and the integral structure includes a second conductive portion extending along the first direction.
  • the gate of the sixth transistor is connected to the light emission control
  • the signal line pattern is coupled, and the second electrode of the sixth transistor is coupled to the light-emitting element in the sub-pixel;
  • the orthographic projection of the channel region of the driving transistor on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate;
  • the first electrode and the second electrode of the driving transistor each include a first part extending in the second direction, and the length of the first part of the first electrode in the second direction is the same as the first part of the second electrode. The lengths extending in the second direction are different.
  • a fourth aspect of the present disclosure provides a display device including the above display substrate.
  • a fifth aspect of the present disclosure provides a manufacturing method of a display substrate, including:
  • a plurality of sub-pixels distributed in an array are fabricated on a substrate; the sub-pixels include:
  • a data line pattern extending along the first direction
  • An initialization signal line pattern includes a portion extending in a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;
  • a sub-pixel driving circuit includes: a driving transistor, a first transistor coupled to the gate of the driving transistor, and a first shielding member coupled to the initialization signal line pattern, the first The orthographic projection of a shielding component on the substrate is located between the orthographic projection of the first transistor on the substrate and the orthographic projection of the target data line pattern on the substrate; The next sub-pixel adjacent to the sub-pixel includes the target data line pattern.
  • FIG. 1 is a schematic structural diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 2 is a working timing diagram corresponding to the sub-pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of a first layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure
  • FIG. 4 is a schematic diagram of a first layout of an active film layer provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a first layout of a first gate metal layer provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a first layout of a second gate metal layer provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a first layout of a source and drain metal layer provided by an embodiment of the disclosure.
  • Figure 8 is a schematic cross-sectional view along the A1A2 direction in Figure 3;
  • FIG. 9 is a schematic diagram of a second layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a third layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of a fourth layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of a fifth layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • Fig. 13 is a schematic cross-sectional view taken along the direction B1B2 in Fig. 11;
  • FIG. 14 is a schematic diagram of a sixth layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • 15 is a schematic diagram of a first layout of a plurality of sub-pixels in a display substrate provided by an embodiment of the disclosure
  • 16 is a schematic diagram of a seventh layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • Fig. 17 is a schematic cross-sectional view taken along the direction C1C2 in Fig. 16;
  • FIG. 18 is a schematic diagram of a second layout of an active film layer provided by an embodiment of the disclosure.
  • FIG. 19 is a schematic diagram of an eighth layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • 20 is a schematic diagram of a ninth layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • FIG. 21 is a schematic diagram of a tenth layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • FIG. 22 is a schematic cross-sectional view along the direction D1D2 in FIG. 21;
  • FIG. 23 is a schematic diagram of the layout of the third metal layer
  • FIG. 24 is a schematic diagram of a second layout of a plurality of sub-pixels in a display substrate provided by an embodiment of the disclosure.
  • FIG. 25 is a schematic diagram of the crosstalk phenomenon that occurs at the gate of the driving transistor in the related art.
  • FIG. 26 is a schematic diagram of an eleventh layout of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure.
  • the causes of vertical crosstalk in OLED display products roughly include: vertical crosstalk caused by the voltage drop on the power signal line, and vertical crosstalk caused by changing data signals loaded on the data line; among them, the vertical crosstalk caused by the data line is the cause of OLED Display products are the main factors for the vertical crosstalk phenomenon. Therefore, how to solve the vertical crosstalk caused by the data line has become an urgent problem to be solved.
  • a shielding pattern can be provided between the data line and the part subject to the crosstalk of the data line, and the coupling effect between the data line and the part can be reduced through the shielding pattern. , Thereby reducing the problem of vertical crosstalk generated by the data line, so that the display product can achieve better display effects.
  • one or more embodiments described herein correspond to a display substrate having a 7TlC (ie, 7 thin film transistors and 1 capacitor) sub-pixel driving circuit.
  • the display substrate may include different sub-pixel driving circuits, for example, more than or less than 7 thin film transistors, and one or more capacitors.
  • the display substrate provided by the present disclosure includes a plurality of sub-pixels, and each sub-pixel may include: a gate line pattern GATE, a first reset signal line pattern RST1, a first initialization signal line pattern VINT1, a data line pattern DATA , The light emission control signal line pattern EM, the power supply signal line pattern VDD, the second reset signal line pattern RST2, and the second initialization signal line pattern VINT2.
  • the sub-pixel driving circuit in each sub-pixel may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.
  • FIG. 1 also includes a first capacitor C1, which is a parasitic capacitor.
  • each transistor included in the sub-pixel driving circuit adopts P-type transistors, wherein the first transistor T1 has a double-gate structure, and the gate 201g of the first transistor T1 is coupled to the gate line pattern GATE , The source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3, and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 has a double-gate structure.
  • the gate 202g of the second transistor T2 is coupled to the first reset signal line pattern RST1
  • the source S2 of the second transistor T2 is coupled to the first initialization signal line pattern VINT1
  • the second transistor The drain D2 of T2 is coupled to the gate 203g of the third transistor T3.
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the source S4 of the fourth transistor T4 is coupled to the data line pattern DATA, and the drain D4 of the fourth transistor T4 is coupled to the source of the third transistor T3 S3 is coupled.
  • the gate 205g of the fifth transistor T5 is coupled to the emission control signal line pattern EM, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source of the third transistor T3 ⁇ S3 is coupled.
  • the gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the light emitting element OLED The anode is coupled.
  • the gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the anode of the light-emitting element OLED, and the source S7 of the seventh transistor T7 is coupled to the second initialization
  • the signal line pattern VINT2 is coupled.
  • the first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.
  • each work cycle includes a first reset period P1, a write compensation period P2, a second reset period P3, and a light emitting period P4.
  • the first reset signal input by the first reset signal line pattern RST1 is at an active level
  • the second transistor T2 is turned on
  • the initialization signal transmitted by the first initialization signal line pattern VINT1 is input to the third
  • the gate 203g of the transistor T3 makes the gate-source voltage Vgs held on the third transistor T3 in the previous frame cleared to reset the gate 203g of the third transistor T3.
  • the first reset signal is at an inactive level
  • the second transistor T2 is turned off
  • the gate scanning signal input by the gate line pattern GATE is at an active level, controlling the first transistor T1 and the fourth transistor T4 Turned on
  • the data line pattern DATA writes a data signal and transmits it to the source S3 of the third transistor T3 through the fourth transistor T4.
  • the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 It is formed as a diode structure, so the first transistor T1, the third transistor T3, and the fourth transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the third transistor T3 can be controlled.
  • the potential of the gate 203g finally reaches Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the gate scan signal is at an inactive level
  • the first transistor T1 and the fourth transistor T4 are both turned off
  • the second reset signal input from the second reset signal line RST2 is at an active level, and controls the first
  • the seven transistor T7 is turned on, and the initialization signal transmitted by the second initialization signal line pattern VINT2 is input to the anode of the light-emitting element OLED, and the light-emitting element OLED is controlled to not emit light.
  • the light emission control signal written in the light emission control signal line pattern EM is at an effective level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line pattern VDD is input to the third The source S3 of the transistor T3, and the gate 203g of the third transistor T3 is kept at Vdata+Vth, so that the third transistor T3 is turned on.
  • the corresponding gate-source voltage of the third transistor T3 is Vdata+Vth-VDD, where VDD is The voltage value corresponding to the power signal, based on the leakage current generated by the gate-source voltage, flows to the anode of the corresponding light-emitting element OLED, and drives the corresponding light-emitting element OLED to emit light.
  • each film layer corresponding to the sub-pixel driving circuit is as follows:
  • the active film layer, the gate insulating layer, the first gate metal layer, the first interlayer insulating layer, the second gate metal layer, the second interlayer insulating layer, the first source and drain are stacked in sequence in the direction away from the substrate The metal layer and the third interlayer insulating layer.
  • the active film layer is used to form the channel region (e.g. 101pg ⁇ 107pg), source formation area (e.g. 101ps ⁇ 107ps) and drain formation area (e.g. :101pd ⁇ 107pd), the active film layer corresponding to the source electrode formation region and the drain electrode formation region will have better conductivity than the active film layer corresponding to the channel region due to the doping effect;
  • the active film layer can be made of amorphous silicon , Polysilicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active film layer corresponding to the source formation region and the drain formation region can be directly used as the corresponding source or drain, or metal materials can be used to make contact with the source formation region.
  • the source electrode is made of a metal material to make the drain electrode in contact with the drain electrode formation region.
  • the first gate metal layer is used to form the gate of each transistor in the sub-pixel driving circuit (e.g., 201g to 207g), and the gate line pattern GATE, the light emission control signal line pattern EM, and the first gate line pattern included in the display substrate.
  • a reset signal line pattern RST1 and a second reset signal line pattern RST2 and other structures, the gate 203g of the third transistor T3 in each sub-pixel drive circuit is multiplexed as the first pole of the storage capacitor Cst in the sub-pixel drive circuit Board Cst1.
  • the second gate metal layer is used to form the second plate Cst2 of the storage capacitor Cst, and the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 included in the display substrate.
  • the first source-drain metal layer is used to form the source (such as S1 to S7) and drain (such as D1 to D7) of each transistor in the sub-pixel driving circuit, and display
  • the substrate includes data line patterns (such as DATA1 and DATA2) and power signal line patterns VDD.
  • the gate 201g of the first transistor T1 covers the first channel region 101pg, and the source S1 of the first transistor T1 is located in the first source formation region 101ps, The drain D1 of the first transistor T1 is located in the first drain formation region 101pd.
  • the gate 202g of the second transistor T2 covers the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source formation region 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation region 102pd.
  • the gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.
  • the gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source S4 of the fourth transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain formation region 104pd.
  • the gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.
  • the gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.
  • the gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.
  • the gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.
  • the connecting lines 401, 402, and 403 in FIG. 1 are all formed by the first source-drain metal layer, and the specific layout is shown in FIGS. 3 and 7.
  • the first capacitor C1 in FIG. 1 is a parasitic capacitor.
  • the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate is downward from the fourth drain forming region 104pd corresponding to the fourth transistor T4.
  • the plurality of sub-pixels included may be distributed in an array, and the plurality of sub-pixels may be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, and each row of sub-pixels includes multiple rows arranged in the second direction.
  • each column of sub-pixels includes a plurality of sub-pixels arranged along a first direction, the first direction intersects the second direction; the gate line pattern GATE and the first reset signal line pattern RST1 included in the sub-pixel ,
  • the first initialization signal line pattern VINT1, the light emission control signal line pattern EM, the second reset signal line pattern RST2, and the second initialization signal line pattern VINT2 may all extend in the second direction;
  • the gate line patterns GATE located in the same row can be formed as a single gate line of an integrated structure
  • the first reset signal line patterns RST1 located in the same row can be formed as a first reset signal line of an integrated structure
  • the first initialization signal located in the same row
  • the line pattern VINT1 can be formed as a first initialization signal line in an integrated structure
  • the light emission control signal line pattern EM in the same row can be formed as a light emission control signal line in an integrated structure
  • the second reset signal line pattern RST2 in the same row can be formed
  • the second initialization signal line pattern VINT2 located in the same row can be formed as a second initialization signal line of an integrated structure.
  • the data line pattern DATA located in the same column can be formed as a data line of an integrated structure
  • the power signal line pattern VDD located in the same column can be formed as a power signal line of an integrated structure.
  • the second reset signal line corresponding to one row of sub-pixels can be multiplexed into the first reset signal line corresponding to the next adjacent row of sub-pixels; similarly, the second reset signal line corresponding to one row of sub-pixels can be multiplexed.
  • the initialization signal line is multiplexed into the first initialization signal line corresponding to the adjacent next row of sub-pixels.
  • the gate 204g of the fourth transistor T4 and the first transistor T1 The gate 201g of the second transistor T2 and the gate 202g of the second transistor T2 are both located on the first side of the gate of the driving transistor (that is, the gate 203g of the third transistor T3), the gate of the seventh transistor T7 and the gate of the sixth transistor T6
  • the pole 206g and the gate of the fifth transistor T5 are both located on the second side of the gate of the driving transistor.
  • the first side and the second side of the gate of the driving transistor are opposite sides of the gate of the driving transistor in the first direction.
  • the first side of the gate of the driving transistor may be It is the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor may be the lower side of the gate of the driving transistor T1.
  • the lower side for example, the side of the display substrate for bonding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC.
  • the upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor farther away from the IC.
  • the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located at the third of the gate of the driving transistor.
  • the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor are opposite sides of the gate of the driving transistor in the second direction X; further, the third side of the gate of the driving transistor may be The left side of the gate of the driving transistor and the fourth side of the gate of the driving transistor may be the right side of the gate of the driving transistor.
  • the first data line pattern DATA1 is located on the left side of the power signal line pattern VDD
  • the power signal line pattern VDD is located on the right side of the first data line pattern DATA1.
  • an embodiment of the present disclosure provides a display substrate, including: a substrate 50 and a plurality of sub-pixels arranged in an array on the substrate 50; the sub-pixels include:
  • a data line pattern extending along the first direction (DATA1 in Fig. 3);
  • the initialization signal line pattern (VINT1 in FIG. 3), the initialization signal line pattern includes a portion extending in a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used for transmission Initialization signal with fixed potential;
  • a sub-pixel driving circuit comprising: a driving transistor (T3 in FIG. 3), a first transistor T1 coupled to the gate of the driving transistor, and coupled to the initialization signal line pattern
  • the above-mentioned display substrate generally includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes: a data line pattern (DATA1 in FIG. 3) extending in a first direction, and an initialization signal at least partially extending in a second direction.
  • Line pattern VINT1 in FIG. 3
  • the data line pattern is used to transmit data signals
  • the initialization signal line pattern is used to transmit initialization signals with a fixed potential
  • the first direction includes the Y direction
  • the second direction includes the X direction.
  • the target data line pattern is: along the second direction, the data line pattern included in the next sub-pixel adjacent to the current sub-pixel.
  • Each sub-pixel also includes a sub-pixel drive circuit, and a light-emitting element corresponding to the sub-pixel drive circuit one-to-one.
  • the light-emitting element includes an anode, an organic light-emitting material layer, and a cathode that are stacked, wherein the anode of the light-emitting element is connected to the corresponding sub-pixel.
  • the driving circuit is coupled, and the light-emitting element realizes light emission under the driving of the driving signal provided by the sub-pixel driving circuit.
  • the gate 203g of the third transistor T3 (that is, the driving transistor) is connected to the first transistor through the connecting line 401
  • the drain D1 of the transistor T1 is coupled, and the drain D3 of the third transistor T3 is coupled to the source S1 of the first transistor T1.
  • the orthographic projection of the first channel region 101pg of the first transistor T1 on the substrate 50 is the same as the orthographic projection of the target data line pattern (DATA2 in FIG.
  • the minimum distance between projections is smaller than the minimum distance between the orthographic projection of the third channel region 103pg of the third transistor T3 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50.
  • the orthographic projection of the aforementioned channel regions (such as the first channel region 101pg and the third channel region 103pg) on the substrate 50 is in line with the target data line pattern (DATA2 in FIG. 3)
  • the minimum distance between the orthographic projections on the substrate 50 refers to: the channel region in the orthographic projection on the substrate 50 is closest to the boundary of the target data line pattern, and the target data line pattern (as shown in FIG. DATA2 in 3) The minimum distance between orthographic projections on the substrate 50.
  • a first shielding part 404 coupled to the initialization signal line pattern (VINT1 in FIG. 3) is provided in the sub-pixel driving circuit, so that the first shielding part 404 has the same signal as the initialization signal.
  • the first shielding part 404 can reduce the influence of the signal change transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the driving transistor
  • the influence of the coupling between the gate (ie 203g) and the target data line pattern reduces the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.
  • the above-mentioned coupling of the first shielding component 404 with the initialization signal line pattern not only makes the first shielding component 404 have a fixed potential, but also realizes that the voltage of the initialization signal line pattern is strengthened, so that the initialization signal line The voltage of the initialization signal transmitted on the pattern is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.
  • the first shielding component 404 may also be coupled with the power signal line pattern VDD included in the sub-pixels, so that the A shielding member 404 has the same fixed potential as the power signal transmitted by the power signal line pattern VDD.
  • the above method of coupling the first shielding member 404 and the power signal line pattern VDD can ensure that the first shielding member 404 has a fixed potential, but it will increase the parasitic capacitance generated by the power signal line pattern VDD. , Which makes the RC load of the power signal line pattern VDD larger, which is not conducive to reducing the vertical crosstalk phenomenon.
  • the gate 201g of the first transistor T1 and the gate line pattern GATE are an integral structure, and the gate 201g of the first transistor T1 is an integral structure. A portion that forms an overlapping area with the active film layer in a direction perpendicular to the substrate.
  • the plurality of sub-pixels include multiple rows of sub-pixels, and each row of sub-pixels includes a plurality of the sub-pixels arranged along the second direction, and are located in the same row of sub-pixels.
  • the initialization signal line patterns of are sequentially coupled to form the initialization signal line corresponding to the row of sub-pixels; the first shielding member 404 extends along the first direction and is coupled to at least one of the initialization signal lines.
  • the multiple sub-pixels may be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged in the second direction, and each column of sub-pixels includes multiple sub-pixels arranged in the first direction.
  • the first direction and the second direction intersect; the initialization signal line patterns located in the same row of sub-pixels are sequentially coupled to form an initialization signal line corresponding to the row of sub-pixels.
  • the above arrangement of the first shielding component 404 extending along the first direction and being coupled to at least one of the initialization signal lines not only enables the first shielding component 404 to reduce the effect of signal changes transmitted on the target data line pattern.
  • the impact of the performance of the first transistor T1 thereby reducing the impact of the coupling between the gate of the driving transistor (ie 203g) and the target data line pattern, reducing the problem of vertical crosstalk, so that the display substrate can be used for display.
  • the first shielding component 404 is coupled to the two adjacent initialization signal lines.
  • the coupling manner of the first shielding component 404 and the initialization signal line, and the specifics of the first shielding component 404 there are various structures and arrangements. Illustratively, as shown in FIG.
  • the first shielding member 404 can be set to be coupled to the two adjacent initialization signal lines respectively; this arrangement makes the The orthographic projection of the first shielding component 404 on the substrate 50 is not only located between the orthographic projection of the first transistor T1 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; It also enables the orthographic projection of the first shielding member 404 on the substrate 50 to be located between the orthographic projection of the connecting line 401 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50.
  • the orthographic projection of the first shielding member 404 on the substrate 50 to be located on the orthographic projection of the driving transistor (ie, the third transistor T3) on the substrate 50 and the target data line
  • the graphics are between the orthographic projections on the substrate 50.
  • the above-mentioned setting method greatly reduces the first crosstalk generated between the target signal line pattern and the first transistor T1, and the second crosstalk generated between the target signal line pattern and the connecting line 401, thereby reducing The indirect crosstalk to the driving transistor caused by the above-mentioned first crosstalk and second crosstalk is eliminated.
  • the above arrangement method also reduces the direct crosstalk generated between the target signal line pattern and the driving transistor, thereby better ensuring the working performance of the display substrate.
  • the first shielding component 404 and the initialization signal line pattern are arranged in different layers, and the first shielding component 404 is disposed on the substrate 50. There is a first overlap area with the orthographic projection of the initialization signal line pattern on the substrate, and the first shielding member 404 passes through the first via hole provided in the first overlap area and the Initialize the signal line pattern coupling.
  • the first shielding component 404 and the initialization signal line pattern can be arranged in the same layer or in different layers.
  • the first shielding component 404 and the initialization signal line pattern are arranged in different layers, the The orthographic projection of the first shielding member 404 on the substrate 50 and the orthographic projection of the initialization signal line pattern on the substrate 50 both have a first overlap area, so that the first overlap area is provided in the first overlap area. Via holes can realize the coupling between the first shielding component 404 and the initialization signal line.
  • the first shielding member 404 and the data line pattern (DATA1 in FIG. 3) can be made of the same material.
  • the display substrate includes a first interlayer insulating layer, and the first shielding member 404 and the data line pattern (DATA1 in FIG. 3) are both located in the first interlayer insulating layer. The layer faces away from the surface of the substrate.
  • the first shielding member 404 is arranged in the above-mentioned manner, so that the first shielding member 404 and the data line pattern can be simultaneously formed on the back of the first interlayer insulating layer through a patterning process.
  • the surface of the substrate avoids adding an additional patterning process for manufacturing the first shielding component 404, thereby simplifying the manufacturing process of the display substrate and saving the manufacturing cost.
  • the sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, and the second transistor T2 includes:
  • the first gate pattern and the second gate pattern are coupled to each other, and the orthographic projection of the first gate pattern on the substrate 50 partially overlaps the orthographic projection of the first semiconductor pattern on the substrate 50 , The orthographic projection of the second gate pattern on the substrate 50 partially overlaps the orthographic projection of the second semiconductor pattern on the substrate 50;
  • the orthographic projection of the third conductor pattern on the substrate 50 and the orthographic projection of the first grid pattern on the substrate 50, and the orthographic projection of the second grid pattern on the substrate 50 Do not overlap;
  • the orthographic projection of the third conductor pattern on the substrate 50 and the orthographic projection of the initialization signal line pattern (VINT1 in FIG. 3) on the substrate 50 at least partially overlap.
  • the above-mentioned second transistor T2 has a double gate structure, and the first semiconductor pattern and the second semiconductor pattern included in it are formed as the channel region of the second transistor T2 (corresponding to FIG. 7), the third conductor pattern 102px included in it is doped, and its conductivity is better than that of the first semiconductor pattern and the second semiconductor pattern.
  • the second transistor T2 includes The first gate pattern and the second gate pattern cover the first semiconductor pattern and the second semiconductor pattern in a one-to-one correspondence, and can be used together as the gate 202g of the second transistor T2.
  • the third conductor pattern 102px has good conductivity and is not covered by the gate pattern, it is easy to couple with other conductive patterns in the vicinity and cause crosstalk.
  • the technical solution provided by the foregoing embodiment by setting the orthographic projection of the third conductor pattern on the substrate 50, and the initialization signal line pattern (VINT1 in FIG. 3) on the substrate 50 The projections overlap at least partially, so that the initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the third conductor pattern is better reduced. The coupling effect between the conductive pattern 102px and other conductive patterns nearby makes the working performance of the display substrate more stable.
  • the sub-pixel driving circuit further includes a first extension part extending from the first semiconductor pattern, and the conductivity of the first extension part is better than that of the first extension part.
  • the first extension portion and the first semiconductor pattern can be fabricated in a single patterning process, and after the first semiconductor pattern is formed, the first extension portion is doped so that the first extension The conductivity of the part is better than that of the first semiconductor pattern.
  • the first extension portion is set to the above structure, so that when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor through the first extension portion, It is more conducive to reducing the impact of the signal change transmitted on the target data line pattern on the performance of the first transistor T1 and the performance of the second transistor T2, thereby reducing the gate of the driving transistor (ie 203g) and the target data line pattern
  • the influence of the coupling between them reduces the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.
  • the first transistor T1 includes:
  • the first transistor has a double-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included in it are formed as the channel region of the first transistor (corresponding to FIG. 4 101pg), the sixth conductor pattern 101px included in it is doped, and its conductivity is better than that of the fourth semiconductor pattern and the fifth semiconductor pattern, and the third gate of the first transistor
  • the electrode pattern and the fourth gate pattern cover the fourth semiconductor pattern and the fifth semiconductor pattern in a one-to-one correspondence, and can be used as the gate 201g of the first transistor T1.
  • the orthographic projection of the first shielding component 404 on the substrate 50 at least partially overlaps the orthographic projection of the sixth conductor pattern 101px on the substrate 50.
  • the orthographic projection of the first shielding member 404 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that The first shielding component 404 can cover the sixth conductor pattern 101px, and because the first shielding component 404 has a fixed potential, the sixth conductor pattern 101px and other nearby patterns are better reduced.
  • the coupling effect between the conductive patterns makes the working performance of the display substrate more stable.
  • the sub-pixel driving circuit further includes: a second shielding part 301 coupled to the first shielding part 404, and the second shielding part
  • the orthographic projection of 301 on the substrate 50 and the orthographic projection of the sixth conductor pattern 101px on the substrate 50 at least partially overlap.
  • the above-mentioned orthographic projection of the second shielding component 301 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px, and since the second shielding member 301 is coupled to the first shielding member 404, the second shielding member 301 has a fixed potential, thereby better reducing The coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns is reduced, so that the working performance of the display substrate is more stable.
  • the first shielding part 404 and the second shielding part 301 both have a fixed potential, it is better to prevent or reduce the first transistor T1 and the target data line pattern ( For example, parasitic capacitance is formed between DATA2), which effectively prevents or reduces vertical crosstalk defects.
  • the orthographic projection of the second shielding member 301 on the substrate 50 can be arranged to cover all of the orthographic projection of the sixth conductor pattern on the substrate 50.
  • the orthographic projection of the second shielding component 301 on the substrate 50 is arranged to cover all of the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can
  • the sixth conductor pattern 101px is completely covered, thereby minimizing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, and better improving the working stability of the display substrate.
  • the second shielding component 301 and the first shielding component 404 are arranged in different layers, and the orthographic projection of the second shielding component 301 on the substrate 50 is in the same position as the first shielding component 404.
  • the orthographic projection on the substrate 50 has a second overlapping area, and the second shielding member 301 and the first shielding member 404 are coupled through a second via provided in the second overlapping area.
  • the second shielding component 301 and the first shielding component 404 can be arranged in the same layer or in different layers.
  • the second shielding component 301 and the first shielding component 404 are arranged in different layers, it can be arranged There is a second overlapping area between the orthographic projection of the second shielding member 301 on the substrate 50 and the orthographic projection of the first shielding member 404 on the substrate 50. In this way, a second overlapping area is provided in the second overlapping area.
  • Two vias, so that the second shielding component 301 and the first shielding component 404 can be coupled through the second vias.
  • the second shielding member 301 and the initialization signal line pattern may be made of the same material.
  • the display substrate further includes a second interlayer insulating layer, and the second shielding member 301 and the initialization signal line pattern (VINT1 in FIG. 3) are both located on the second layer.
  • the inter-insulating layer faces away from the surface of the substrate.
  • the second shielding member 301 and the initialization signal line pattern are set with the same material, and the second shielding member 301 and the initialization signal line pattern (VINT1 in FIG. 3) are both located at the same material.
  • the second interlayer insulating layer faces away from the surface of the substrate, so that the second shielding member 301 and the initialization signal line pattern can be formed at the same time in the same patterning process, avoiding the addition of additional dedicated for manufacturing
  • the manufacturing process of the second shielding component 301 simplifies the manufacturing process of the display substrate and saves the production cost.
  • the sub-pixel further includes a power signal line pattern VDD
  • the power signal line pattern VDD includes a portion extending along the first direction
  • the sub-pixel driving circuit further includes A storage capacitor Cst, the first plate Cst1 in the storage capacitor Cst is multiplexed as the gate of the driving transistor, and the second plate Cst2 in the storage capacitor Cst is coupled to the power signal line pattern VDD,
  • the second electrode plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate.
  • the storage capacitor Cst included in the sub-pixel driving circuit has a first electrode plate Cst1 and a second electrode plate Cst2, the first electrode plate Cst1 and the second electrode plate Cst2 are disposed oppositely, and the first electrode plate Cst2 A plate Cst1 is coupled to the gate of the driving transistor, and the second plate Cst2 is coupled to the power signal line pattern VDD.
  • the first plate Cst1 can be directly multiplexed as the gate of the driving transistor, which not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor, but also reduces the number of components.
  • the space occupied by the pixel drive circuit is more conducive to improving the resolution of the display substrate.
  • the second electrode plate Cst2 in the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second electrode plate Cst2 in the storage capacitor Cst can be connected to the first electrode plate Cst2.
  • the two shielding components 301 and the initialization signal line pattern are formed at the same time in the same patterning process, which greatly simplifies the manufacturing process of the display substrate and saves the production cost.
  • the sub-pixel further includes: a reset signal line pattern (RST1 in FIG. 3) extending in a second direction intersecting the first direction, and the sub-pixel
  • the drive circuit also includes:
  • the second transistor T2 the first electrode (such as the source S2) of the second transistor T2 is coupled to the initialization signal line pattern (such as VINT1) through the first conductive connection portion 405, and the second transistor T2
  • the second electrode (such as the drain D2) of the second transistor is coupled to the gate of the driving transistor, and the gate 202g of the second transistor T2 is coupled to the reset signal line pattern (such as RST1).
  • the first conductive connecting portion 405 can be made of a metal material, and can be formed in the same patterning process as the data line pattern.
  • the orthographic projection of the first conductive connecting portion 405 on the substrate 50 as described above covers at least part of the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the first conductive connecting portion 405 can be aligned with The sixth conductor pattern 101px is covered, and because the first conductive connection portion 405 is coupled to the initialization signal line pattern, the first conductive connection portion 405 has a fixed potential, thereby better reducing The coupling effect between the sixth conductive pattern 101px and other conductive patterns nearby makes the working performance of the display substrate more stable.
  • the sub-pixel further includes: a gate line pattern GATE, a light emission control signal line pattern EM, a reset signal line pattern (RST1 in FIG. 3), and a power signal line pattern VDD;
  • the gate line pattern GATE, the light emission control signal line pattern EM, and the reset signal line pattern all extend along the second direction, and the power signal line pattern VDD includes a portion extending along the first direction;
  • the sub-pixel driving circuit further includes: a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7;
  • the gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second electrode of the first transistor T1, and the first electrode of the driving transistor is connected to the second electrode of the fifth transistor T5. Pole coupled, the second pole of the driving transistor is coupled to the first pole of the first transistor T1;
  • the gate 201g of the first transistor T1 is coupled to the gate line pattern GATE;
  • the gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first electrode of the second transistor T2 is coupled to the initialization signal line pattern, and the second electrode of the second transistor T2 is coupled to the reset signal line pattern. Coupled with the gate of the driving transistor;
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, and the first electrode of the fourth transistor T4 is coupled to the data line pattern (DATA1 in FIG. 3).
  • the second electrode of the four-transistor T4 is coupled to the first electrode of the driving transistor;
  • the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern VDD;
  • the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the sixth transistor T6 The second pole of is coupled to the light-emitting element in the sub-pixel;
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) included in the next sub-pixel adjacent in the first direction, and the first electrode of the seventh transistor T7 is connected to the bottom
  • the initialization signal line pattern (such as VINT2) included in one sub-pixel is coupled, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.
  • the plurality of sub-pixels included may be distributed in an array, and the plurality of sub-pixels may be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, and each row of sub-pixels includes a plurality of sub-pixels arranged in the second direction.
  • Each column of sub-pixels includes a plurality of sub-pixels arranged along a first direction, and the first direction intersects the second direction.
  • next sub-pixel adjacent in the first direction is the next adjacent sub-pixel located in the same column as the seventh transistor T7.
  • Setting the sub-pixel and the sub-pixel driving circuit included in the above-mentioned structure can effectively reduce the layout space occupied by the sub-pixel driving circuit while ensuring the working performance of the sub-pixel driving circuit, which is beneficial to improve the display The resolution of the substrate.
  • the gates of the transistors included in the sub-pixel driving circuit and the functional patterns coupled with them can be formed as an integral structure.
  • the gates of the first transistor and the gate of the fourth transistor are both corresponding to
  • the coupled gate line pattern is an integrated structure
  • the gate of the fifth transistor and the gate of the sixth transistor are both integrated with the correspondingly coupled light-emitting control signal line pattern
  • the gate of the second transistor and the gate of the seventh transistor are integrated.
  • the electrode and the correspondingly coupled reset signal line pattern form an integral structure.
  • the first transistor T1 is used for threshold compensation of the driving transistor (such as the third transistor T3)
  • the second transistor T2 is used for resetting the gate of the driving transistor
  • the fourth transistor T4 is used for writing the data signal transmitted by the data line pattern
  • the fifth transistor T5 is used for writing the power signal transmitted by the power signal line pattern to the first pole of the driving transistor
  • the sixth transistor T6 is used for In order to control whether the corresponding light-emitting element emits light
  • the seventh transistor T7 is used to reset the anode of the light-emitting element.
  • the sub-pixel further includes: a gate line pattern GATE, a light emission control signal line pattern EM, a reset signal line pattern RST, and a power signal line pattern VDD; the gate line pattern GATE, the light emission control signal line Both the pattern EM and the reset signal line pattern RST extend in the second direction, the power signal line pattern VDD includes a portion extending in the first direction; the first shielding member 404 is on the substrate 50
  • the orthographic projection of respectively overlaps the orthographic projection of the grid line pattern GATE on the substrate 50 and the orthographic projection of the light-emitting control signal line pattern EM on the substrate 50, respectively.
  • the first shielding component 404 is laid out in the above-mentioned manner, so that the first shielding component 404 can isolate the first transistor T1 and the driving transistor from the target data line pattern (such as DATA2) Therefore, it is more beneficial to reduce the crosstalk caused by the change of the data signal on the target data line pattern to the first transistor T1 and the driving transistor.
  • the target data line pattern such as DATA2
  • the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel in various ways.
  • the anode of the light-emitting element is on the positive side of the substrate.
  • the head shadow overlaps the orthographic projection of the second electrode of the seventh transistor T7 on the substrate, and the anode of the light-emitting element can pass through the via hole provided at the overlap with the seventh transistor T7.
  • the second pole is coupled; or, the frontal shadow of the anode of the light-emitting element on the substrate does not overlap with the orthographic projection of the second electrode of the seventh transistor T7 on the substrate, and the sub
  • the pixel driving circuit further includes a second conductive connection portion 406 and a third conductive connection portion 407.
  • the orthographic projection of the anode of the light-emitting element on the substrate and the first end of the third conductive connection portion 407 are on the substrate.
  • the orthographic projections on the top overlap, the anode of the light-emitting element is coupled to the first end of the third conductive connection portion 407 through the via hole at the overlap, and the second end of the third conductive connection portion 407 is coupled to the first end of the third conductive connection portion 407.
  • the via hole at the overlap is coupled to the second end of the second conductive connection portion 406, so that the anode of the light-emitting element can be connected to the second conductive connection portion 406 and the third conductive connection portion 407.
  • the second electrode of the seventh transistor T7 is coupled.
  • the second conductive connection portion 406 may include an edge
  • the anode of the light-emitting element may be located on the upper side of the light-emitting control signal line pattern in the corresponding sub-pixel
  • the second electrode of the seventh transistor T7 may be located in the corresponding sub-pixel In the lower side of the light-emitting control signal line pattern.
  • the light-emitting element in the first color sub-pixel includes a first anode 601, a first organic light-emitting material layer, and a first cathode that are sequentially stacked in a direction away from the substrate; the orthographic projection of the first anode 601 on the substrate corresponds to the The orthographic projection of the second electrode of the seventh transistor T7 on the substrate overlaps, and the first anode 601 passes through the via hole at the overlap to correspond to the second electrode of the seventh transistor T7. Coupling.
  • the light-emitting element in the second color sub-pixel includes a second anode 602, a second organic light-emitting material layer, and a second cathode that are sequentially stacked in a direction away from the substrate; the positive head shadow of the second anode 602 on the substrate, and Correspondingly, the orthographic projection of the second electrode of the seventh transistor T7 on the substrate does not overlap, and the sub-pixel driving circuit in the second color sub-pixel further includes a second conductive connection portion 406 and a third conductive connection Portion 407, the second anode 602 is coupled to the corresponding second electrode of the seventh transistor T7 through the second conductive connection portion 406 and the third conductive connection portion 407.
  • the light-emitting element in the third color sub-pixel includes a third anode 603, a third organic light-emitting material layer, and a third cathode that are sequentially stacked in a direction away from the substrate; the orthographic projection of the third anode 603 on the substrate corresponds to the The second electrode of the seventh transistor T7 overlaps the orthographic projection on the substrate, and the third anode 603 is connected to the second electrode of the seventh transistor T7 through the via hole at the overlap. Coupling.
  • the anode of the organic light-emitting element of each color sub-pixel includes a main body electrode and a connection electrode, and the shape of the main body electrode is hexagonal.
  • the first anode 601 of the first color sub-pixel includes a first body electrode 6011 and a first connection electrode 6012.
  • the first body electrode 6011 and the first connection electrode 6012 may be an integral structure, and the first connection electrode 6012 is connected to the second electrode of the seventh transistor T7 of the first color sub-pixel through the connection hole.
  • the second anode 602 of the second color sub-pixel includes a second main body electrode 6021 and a second connection electrode 6022.
  • the second main body electrode 6021 and the second connection electrode 6022 may be an integral structure, and the second connection electrode 6022 is connected by a second conductivity.
  • the portion 406 and the third conductive connection portion 407 are connected to the second electrode of the seventh transistor T7 of the second color sub-pixel.
  • the third anode 603 of the third color sub-pixel includes a third main body electrode 6031 and a third connection electrode 6032.
  • the third main body electrode 6031 and the third connection electrode 6032 may be an integral structure, and the third connection electrode 6032 is connected to the third body electrode 6032 through the connection hole.
  • the second electrode of the seventh transistor T7 of the three-color sub-pixel is connected.
  • the first connection electrode 6012 of the first color sub-pixel is located on the side of the first main body electrode 6011 away from the data line pattern of the sub-pixel pixel circuit in the X direction, and located at the center of the first main electrode 6011 in the Y direction It is far away from the side of the light emission control signal line of the sub-pixel pixel circuit.
  • the first connection electrode 6012 and the first body electrode 6011 of the first color sub-pixel are arranged in the Y direction, and the first connection electrode 6012 is located at the lower right corner of the first body electrode 6011.
  • the second connection electrode 6022 of the second color sub-pixel is located on the side of the second main body electrode 6021 away from the data line of the sub-pixel pixel circuit in the X direction, and is located close to the center of the second main electrode 6021 in the Y direction.
  • the sub-pixel pixel circuit emits light on one side of the control signal line.
  • the second connection electrode 6022 and the second body electrode 6021 of the second color sub-pixel are arranged in the Y direction, and the second connection electrode 6022 is located at the lower right corner of the first body electrode 1231.
  • the third connection electrode 6032 and the third main body electrode 6031 of the third color sub-pixel are arranged in the X direction, and the third connection electrode 6032 is located on the right side of the third main body electrode 6031, that is, close to the sub-pixel pixel circuit and close to the shielding line. On the side.
  • the first body electrode 6011 of the first anode 601 of the first color sub-pixel covers the driving transistor of the first color sub-pixel
  • the driving transistors of the two color sub-pixels basically do not overlap or partially overlap
  • the third body electrode 6031 of the third anode 603 of the third color sub-image does not overlap the driving transistors of the third color sub-pixel.
  • the first body electrode 6011 of the first color sub-pixel 601 overlaps the gate line pattern and the light-emitting control signal line pattern; the second color sub-pixel (for example, the red sub-pixel) The second body electrode 6021 overlaps the gate line pattern and the reset signal line pattern; the third body electrode 6031 of the third color sub-pixel (such as the green sub-pixel) and the light-emitting control signal line pattern, the next row of sub-pixel drive circuit
  • the reset signal line pattern and the initialization signal line pattern of the sub-pixel driving circuit in the next row overlap.
  • the third body electrode 6031 of the third color sub-pixel overlaps the pixel driving circuit area of the first color sub-pixel (for example, the blue sub-pixel) adjacent to it in the next row.
  • the first body electrode 6011 of the first color sub-pixel 601 overlaps with a portion of the driving transistor of the adjacent third color sub-pixel, and the first body electrode 6011 of the first color sub-pixel 601 is in its sub-pixel driving circuit.
  • the data line patterns of the first shielding member 404, and the data line patterns in the sub-pixel driving circuit of the adjacent second color sub-pixel are all overlapped.
  • the second body electrode 6021 of the second color sub-pixel does not overlap with the data line pattern in the sub-pixel drive circuit, and the power signal line pattern in the sub-pixel drive circuit and the adjacent sub-pixel drive of the third color sub-pixel are not overlapped.
  • the power signal line pattern and the data line pattern in the circuit overlap.
  • the third body electrode 6031 of the third color sub-pixel overlaps with the data line pattern and power signal line pattern in the sub-pixel driving circuit, and overlaps with the power signal line in the sub-pixel driving circuit of the adjacent second color sub-pixel.
  • the first body electrode 6011 of the first color sub-pixel 601 is provided with a first connection electrode 6012 connected to it on the side close to the reset signal line pattern of the next row; the second body of the second color sub-pixel The side of the electrode 6021 close to the reset signal line pattern of the next row is provided with a second connecting electrode 6022 connected to it; the third body electrode 6031 of the third color sub-pixel is provided with a third connected to the side close to its seventh transistor T7. Connect the electrode 6032.
  • the first connection electrode 6012 of the first color sub-pixel 601 overlaps with the second electrode of the seventh transistor T7 in the sub-pixel driving circuit.
  • the second connection electrode 6022 of the second color sub-pixel does not overlap with the second electrode of the seventh transistor T7 in the sub-pixel driving circuit, and the second electrode of the seventh transistor T7 of the second color sub-pixel is not overlapped with the second electrode of the third color sub-pixel.
  • the third body electrode 6031 of the pixel overlaps.
  • the third connection electrode 6032 of the third color sub-pixel overlaps with the second electrode of the seventh transistor T7 in the sub-pixel driving circuit.
  • an embodiment of the present disclosure also provides a display substrate, including: a substrate 50 and a plurality of sub-pixels arranged in an array on the substrate 50; the sub-pixels include:
  • a data line pattern (such as: DATA1) extending along the first direction;
  • An initialization signal line pattern (such as: VINT1), the initialization signal line pattern includes a portion extending in a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used for transmission with a fixed potential
  • a sub-pixel driving circuit comprising: a driving transistor (such as a third transistor T3), a first transistor T1 coupled to the gate of the driving transistor, and coupled to the initialization signal line pattern
  • the first shielding component 404 is used to form a coupling capacitor with the first electrode (ie source S1) of the first transistor T1, and the first shielding component 404 is orthographically projected on the substrate 50
  • the orthographic projection of the target data line pattern (such as DATA2) on the substrate 50 does not overlap, and the next sub-pixel adjacent to the sub-pixel along the second direction includes the target data line pattern.
  • the above-mentioned display substrate generally includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes: a data line pattern (DATA1 in FIG. 3) extending in a first direction, and an initialization signal at least partially extending in a second direction.
  • Line pattern VINT1 in FIG. 3
  • the data line pattern is used to transmit data signals
  • the initialization signal line pattern is used to transmit initialization signals with a fixed potential
  • the first direction includes the Y direction
  • the second direction includes the X direction.
  • the target data line pattern is: along the second direction, the data line pattern included in the next sub-pixel adjacent to the current sub-pixel.
  • Each sub-pixel also includes a sub-pixel drive circuit, and a light-emitting element corresponding to the sub-pixel drive circuit one-to-one.
  • the light-emitting element includes an anode, an organic light-emitting material layer, and a cathode that are stacked, wherein the anode of the light-emitting element is connected to the corresponding sub-pixel.
  • the driving circuit is coupled, and the light-emitting element realizes light emission under the driving of the driving signal provided by the sub-pixel driving circuit.
  • the gate 203g of the third transistor T3 (that is, the driving transistor) is connected to the first transistor through the connecting line 401
  • the drain D1 of the transistor T1 is coupled, and the drain D3 of the third transistor T3 is coupled to the source S1 of the first transistor T1.
  • the orthographic projection of the first channel region 101pg of the first transistor T1 on the substrate 50 is the same as the orthographic projection of the target data line pattern (DATA2 in FIG.
  • the minimum distance between projections is smaller than the minimum distance between the orthographic projection of the third channel region 103pg of the third transistor T3 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50.
  • the orthographic projection of the aforementioned channel regions (such as the first channel region 101pg and the third channel region 103pg) on the substrate 50 is in line with the target data line pattern (DATA2 in FIG. 3)
  • the minimum distance between the orthographic projections on the substrate 50 refers to: the channel region in the orthographic projection on the substrate 50 is closest to the boundary of the target data line pattern, and the target data line pattern (as shown in FIG. DATA2 in 3) The minimum distance between orthographic projections on the substrate 50.
  • a first shielding part 404 coupled to the initialization signal line pattern (VINT1 in FIG. 3) is provided in the sub-pixel driving circuit, so that the first shielding part 404 has the same signal as the initialization signal.
  • the same fixed potential, and setting the first shielding part 404 can form a coupling capacitance with the first electrode (ie source S1) of the first transistor T1, so that the first shielding part 404 can reduce the target data line pattern
  • the influence of the transmitted signal change on the performance of the first transistor T1, thereby reducing the influence of the coupling between the gate of the driving transistor (ie 203g) and the target data line pattern, reducing the problem of vertical crosstalk, and making the display substrate Better display effect can be obtained when used for display.
  • the above-mentioned coupling of the first shielding component 404 with the initialization signal line pattern not only makes the first shielding component 404 have a fixed potential, but also realizes that the voltage of the initialization signal line pattern is strengthened, so that the initialization signal line The voltage of the initialization signal transmitted on the pattern is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.
  • the first shielding component 404 may also be coupled with the power signal line pattern VDD included in the sub-pixels, so that the A shielding member 404 has the same fixed potential as the power signal transmitted by the power signal line pattern VDD.
  • the above method of coupling the first shielding member 404 and the power signal line pattern VDD can ensure that the first shielding member 404 has a fixed potential, but it will increase the parasitic capacitance generated by the power signal line pattern VDD. , Which makes the RC load of the power signal line pattern VDD larger, which is not conducive to reducing the vertical crosstalk phenomenon.
  • the gate 201g of the first transistor T1 and the gate line pattern GATE are an integral structure, and the gate 201g of the first transistor T1 is an integral structure. A portion that forms an overlapping area with the active film layer in a direction perpendicular to the substrate.
  • the plurality of sub-pixels include multiple rows of sub-pixels, and each row of sub-pixels includes a plurality of the sub-pixels arranged along the second direction, and are located in the same row of sub-pixels.
  • the initialization signal line patterns of are sequentially coupled to form the initialization signal line corresponding to the row of sub-pixels; the first shielding member 404 extends along the first direction and is coupled to at least one of the initialization signal lines.
  • the multiple sub-pixels may be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged in the second direction, and each column of sub-pixels includes multiple sub-pixels arranged in the first direction.
  • the first direction and the second direction intersect; the initialization signal line patterns located in the same row of sub-pixels are sequentially coupled to form an initialization signal line corresponding to the row of sub-pixels.
  • the above arrangement of the first shielding component 404 extending along the first direction and being coupled to at least one of the initialization signal lines not only enables the first shielding component 404 to reduce the effect of signal changes transmitted on the target data line pattern.
  • the impact of the performance of the first transistor T1 thereby reducing the impact of the coupling between the gate of the driving transistor (ie 203g) and the target data line pattern, reducing the problem of vertical crosstalk, so that the display substrate can be used for display.
  • the first shielding component 404 is coupled to the two adjacent initialization signal lines.
  • the coupling manner of the first shielding component 404 and the initialization signal line, and the specifics of the first shielding component 404 there are various structures and arrangements. Illustratively, as shown in FIG.
  • the first shielding member 404 can be set to be coupled to the two adjacent initialization signal lines respectively; this arrangement makes the The orthographic projection of the first shielding component 404 on the substrate 50 is not only located between the orthographic projection of the first transistor T1 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; It also enables the orthographic projection of the first shielding member 404 on the substrate 50 to be located between the orthographic projection of the connecting line 401 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50.
  • the orthographic projection of the first shielding member 404 on the substrate 50 to be located on the orthographic projection of the driving transistor (ie, the third transistor T3) on the substrate 50 and the target data line
  • the graphics are between the orthographic projections on the substrate 50.
  • the above-mentioned setting method greatly reduces the first crosstalk generated between the target signal line pattern and the first transistor T1, and the second crosstalk generated between the target signal line pattern and the connecting line 401, thereby reducing The indirect crosstalk to the driving transistor caused by the above-mentioned first crosstalk and second crosstalk is eliminated.
  • the above arrangement method also reduces the direct crosstalk generated between the target signal line pattern and the driving transistor, thereby better ensuring the working performance of the display substrate.
  • the first shielding component 404 and the initialization signal line pattern are arranged in different layers, and the first shielding component 404 is disposed on the substrate 50. There is a first overlap area with the orthographic projection of the initialization signal line pattern on the substrate, and the first shielding member 404 passes through the first via hole provided in the first overlap area and the Initialize the signal line pattern coupling.
  • the first shielding component 404 and the initialization signal line pattern can be arranged in the same layer or in different layers.
  • the first shielding component 404 and the initialization signal line pattern are arranged in different layers, the The orthographic projection of the first shielding member 404 on the substrate 50 and the orthographic projection of the initialization signal line pattern on the substrate 50 both have a first overlap area, so that the first overlap area is provided in the first overlap area. Via holes can realize the coupling between the first shielding component 404 and the initialization signal line.
  • the first shielding member 404 and the data line pattern (DATA1 in FIG. 3) can be made of the same material.
  • the display substrate includes a first interlayer insulating layer, and the first shielding member 404 and the data line pattern (DATA1 in FIG. 3) are both located in the first interlayer insulating layer. The layer faces away from the surface of the substrate.
  • the first shielding member 404 is arranged in the above-mentioned manner, so that the first shielding member 404 and the data line pattern can be simultaneously formed on the back of the first interlayer insulating layer through a patterning process.
  • the surface of the substrate avoids adding an additional patterning process for manufacturing the first shielding component 404, thereby simplifying the manufacturing process of the display substrate and saving the manufacturing cost.
  • the sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, and the second transistor T2 includes:
  • the first gate pattern and the second gate pattern are coupled to each other, and the orthographic projection of the first gate pattern on the substrate 50 partially overlaps the orthographic projection of the first semiconductor pattern on the substrate 50 , The orthographic projection of the second gate pattern on the substrate 50 partially overlaps the orthographic projection of the second semiconductor pattern on the substrate 50;
  • the orthographic projection of the third conductor pattern on the substrate 50 and the orthographic projection of the first grid pattern on the substrate 50, and the orthographic projection of the second grid pattern on the substrate 50 Do not overlap;
  • the orthographic projection of the third conductor pattern on the substrate 50 and the orthographic projection of the initialization signal line pattern (VINT1 in FIG. 3) on the substrate 50 at least partially overlap.
  • the above-mentioned second transistor T2 has a double gate structure, and the first semiconductor pattern and the second semiconductor pattern included in it are formed as the channel region of the second transistor T2 (corresponding to FIG. 7), the third conductor pattern 102px included in it is doped, and its conductivity is better than that of the first semiconductor pattern and the second semiconductor pattern.
  • the second transistor T2 includes The first gate pattern and the second gate pattern cover the first semiconductor pattern and the second semiconductor pattern in a one-to-one correspondence, and can be used together as the gate 202g of the second transistor T2.
  • the third conductor pattern 102px has good conductivity and is not covered by the gate pattern, it is easy to couple with other conductive patterns in the vicinity and cause crosstalk.
  • the technical solution provided by the foregoing embodiment by setting the orthographic projection of the third conductor pattern on the substrate 50, and the initialization signal line pattern (VINT1 in FIG. 3) on the substrate 50 The projections overlap at least partially, so that the initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the third conductor pattern is better reduced. The coupling effect between the conductive pattern 102px and other conductive patterns nearby makes the working performance of the display substrate more stable.
  • the sub-pixel driving circuit further includes a first extension part extending from the first semiconductor pattern, and the conductivity of the first extension part is better than that of the first extension part.
  • the first extension portion and the first semiconductor pattern can be fabricated in a single patterning process, and after the first semiconductor pattern is formed, the first extension portion is doped so that the first extension The conductivity of the part is better than that of the first semiconductor pattern.
  • the first extension portion is set to the above structure, so that when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor through the first extension portion, It is more conducive to reducing the impact of the signal change transmitted on the target data line pattern on the performance of the first transistor T1 and the performance of the second transistor T2, thereby reducing the gate of the driving transistor (ie 203g) and the target data line pattern
  • the influence of the coupling between them reduces the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.
  • the first transistor T1 includes:
  • the first transistor has a double-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included in it are formed as the channel region of the first transistor (corresponding to FIG. 4 101pg), the sixth conductor pattern 101px included in it is doped, and its conductivity is better than that of the fourth semiconductor pattern and the fifth semiconductor pattern, and the third gate of the first transistor
  • the electrode pattern and the fourth gate pattern cover the fourth semiconductor pattern and the fifth semiconductor pattern in a one-to-one correspondence, and can be used as the gate 201g of the first transistor T1.
  • the orthographic projection of the first shielding component 404 on the substrate 50 at least partially overlaps the orthographic projection of the sixth conductor pattern 101px on the substrate 50.
  • the orthographic projection of the first shielding member 404 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that The first shielding component 404 can cover the sixth conductor pattern 101px, and because the first shielding component 404 has a fixed potential, the sixth conductor pattern 101px and other nearby patterns are better reduced.
  • the coupling effect between the conductive patterns makes the working performance of the display substrate more stable.
  • the sub-pixel driving circuit further includes: a second shielding part 301 coupled to the first shielding part 404, and the second shielding part
  • the orthographic projection of 301 on the substrate 50 and the orthographic projection of the sixth conductor pattern 101px on the substrate 50 at least partially overlap.
  • the above-mentioned orthographic projection of the second shielding component 301 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px, and since the second shielding member 301 is coupled to the first shielding member 404, the second shielding member 301 has a fixed potential, thereby better reducing The coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns is reduced, so that the working performance of the display substrate is more stable.
  • the first shielding part 404 and the second shielding part 301 both have a fixed potential, it is better to prevent or reduce the first transistor T1 and the target data line pattern ( For example, parasitic capacitance is formed between DATA2), which effectively prevents or reduces vertical crosstalk defects.
  • the orthographic projection of the second shielding member 301 on the substrate 50 can be arranged to cover all of the orthographic projection of the sixth conductor pattern on the substrate 50.
  • the orthographic projection of the second shielding component 301 on the substrate 50 is arranged to cover all of the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can
  • the sixth conductor pattern 101px is completely covered, thereby minimizing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, and better improving the working stability of the display substrate.
  • the second shielding component 301 and the first shielding component 404 are arranged in different layers, and the orthographic projection of the second shielding component 301 on the substrate 50 is in the same position as the first shielding component 404.
  • the orthographic projection on the substrate 50 has a second overlapping area, and the second shielding member 301 and the first shielding member 404 are coupled through a second via provided in the second overlapping area.
  • the second shielding component 301 and the first shielding component 404 can be arranged in the same layer or in different layers.
  • the second shielding component 301 and the first shielding component 404 are arranged in different layers, it can be arranged There is a second overlapping area between the orthographic projection of the second shielding member 301 on the substrate 50 and the orthographic projection of the first shielding member 404 on the substrate 50. In this way, a second overlapping area is provided in the second overlapping area.
  • Two vias, so that the second shielding component 301 and the first shielding component 404 can be coupled through the second vias.
  • the second shielding member 301 and the initialization signal line pattern may be made of the same material.
  • the display substrate further includes a second interlayer insulating layer, and the second shielding member 301 and the initialization signal line pattern (VINT1 in FIG. 3) are both located on the second layer.
  • the inter-insulating layer faces away from the surface of the substrate.
  • the second shielding member 301 and the initialization signal line pattern are set with the same material, and the second shielding member 301 and the initialization signal line pattern (VINT1 in FIG. 3) are both located at the same material.
  • the second interlayer insulating layer faces away from the surface of the substrate, so that the second shielding member 301 and the initialization signal line pattern can be formed at the same time in the same patterning process, avoiding the addition of additional dedicated for manufacturing
  • the manufacturing process of the second shielding component 301 simplifies the manufacturing process of the display substrate and saves the production cost.
  • the sub-pixel further includes a power signal line pattern VDD
  • the power signal line pattern VDD includes a portion extending along the first direction
  • the sub-pixel driving circuit further includes A storage capacitor Cst, the first plate Cst1 in the storage capacitor Cst is multiplexed as the gate of the driving transistor, and the second plate Cst2 in the storage capacitor Cst is coupled to the power signal line pattern VDD,
  • the second electrode plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate.
  • the storage capacitor Cst included in the sub-pixel driving circuit has a first electrode plate Cst1 and a second electrode plate Cst2, the first electrode plate Cst1 and the second electrode plate Cst2 are disposed oppositely, and the first electrode plate Cst2 A plate Cst1 is coupled to the gate of the driving transistor, and the second plate Cst2 is coupled to the power signal line pattern VDD.
  • the first plate Cst1 can be directly multiplexed as the gate of the driving transistor, which not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor, but also reduces the number of components.
  • the space occupied by the pixel drive circuit is more conducive to improving the resolution of the display substrate.
  • the second electrode plate Cst2 in the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second electrode plate Cst2 in the storage capacitor Cst can be connected to the first electrode plate Cst2.
  • the two shielding components 301 and the initialization signal line pattern are formed at the same time in the same patterning process, which greatly simplifies the manufacturing process of the display substrate and saves the production cost.
  • the sub-pixel further includes: a reset signal line pattern (RST1 in FIG. 3) extending in a second direction intersecting the first direction, and the sub-pixel
  • the drive circuit also includes:
  • the second transistor T2 the first electrode (such as the source S2) of the second transistor T2 is coupled to the initialization signal line pattern (such as VINT1) through the first conductive connection portion 405, and the second transistor T2
  • the second electrode (such as the drain D2) of the second transistor is coupled to the gate of the driving transistor, and the gate 202g of the second transistor T2 is coupled to the reset signal line pattern (such as RST1).
  • the first conductive connection portion 405 can be made of a metal material, and can be formed in the same patterning process as the data line pattern.
  • the orthographic projection of the first conductive connecting portion 405 on the substrate 50 as described above covers at least part of the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the first conductive connecting portion 405 can be aligned with The sixth conductor pattern 101px is covered, and because the first conductive connection portion 405 is coupled to the initialization signal line pattern, the first conductive connection portion 405 has a fixed potential, thereby better reducing The coupling effect between the sixth conductive pattern 101px and other conductive patterns nearby makes the working performance of the display substrate more stable.
  • the sub-pixel further includes: a gate line pattern GATE, a light emission control signal line pattern EM, a reset signal line pattern (RST1 in FIG. 3), and a power signal line pattern VDD;
  • the gate line pattern GATE, the light emission control signal line pattern EM, and the reset signal line pattern all extend along the second direction, and the power signal line pattern VDD includes a portion extending along the first direction;
  • the sub-pixel driving circuit further includes: a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7;
  • the gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second electrode of the first transistor T1, and the first electrode of the driving transistor is connected to the second electrode of the fifth transistor T5. Pole coupled, the second pole of the driving transistor is coupled to the first pole of the first transistor T1;
  • the gate 201g of the first transistor T1 is coupled to the gate line pattern GATE;
  • the gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first electrode of the second transistor T2 is coupled to the initialization signal line pattern, and the second electrode of the second transistor T2 is coupled to the reset signal line pattern. Coupled with the gate of the driving transistor;
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, and the first electrode of the fourth transistor T4 is coupled to the data line pattern (DATA1 in FIG. 3).
  • the second electrode of the four-transistor T4 is coupled to the first electrode of the driving transistor;
  • the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern VDD;
  • the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the sixth transistor T6 The second pole of is coupled to the light-emitting element in the sub-pixel;
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) included in the next sub-pixel adjacent in the first direction, and the first electrode of the seventh transistor T7 is connected to the bottom
  • the initialization signal line pattern (such as VINT2) included in one sub-pixel is coupled, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.
  • the plurality of sub-pixels included may be distributed in an array, and the plurality of sub-pixels may be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, and each row of sub-pixels includes a plurality of sub-pixels arranged in the second direction.
  • Each column of sub-pixels includes a plurality of sub-pixels arranged along a first direction, and the first direction intersects the second direction.
  • next sub-pixel adjacent in the first direction is the next adjacent sub-pixel located in the same column as the seventh transistor T7.
  • Setting the sub-pixel and the sub-pixel driving circuit included in the above-mentioned structure can effectively reduce the layout space occupied by the sub-pixel driving circuit while ensuring the working performance of the sub-pixel driving circuit, which is beneficial to improve the display The resolution of the substrate.
  • the gates of the transistors included in the sub-pixel driving circuit and the functional patterns coupled with them can be formed as an integral structure.
  • the gates of the first transistor and the gate of the fourth transistor are both corresponding to
  • the coupled gate line pattern is an integrated structure
  • the gate of the fifth transistor and the gate of the sixth transistor are both integrated with the correspondingly coupled light-emitting control signal line pattern
  • the gate of the second transistor and the gate of the seventh transistor are integrated.
  • the electrode and the correspondingly coupled reset signal line pattern form an integral structure.
  • the first transistor T1 is used for threshold compensation of the driving transistor (such as the third transistor T3)
  • the second transistor T2 is used for resetting the gate of the driving transistor
  • the fourth transistor T4 is used for writing the data signal transmitted by the data line pattern
  • the fifth transistor T5 is used for writing the power signal transmitted by the power signal line pattern to the first pole of the driving transistor
  • the sixth transistor T6 is used for In order to control whether the corresponding light-emitting element emits light
  • the seventh transistor T7 is used to reset the anode of the light-emitting element.
  • the sub-pixel further includes: a gate line pattern GATE, a light emission control signal line pattern EM, a reset signal line pattern RST, and a power signal line pattern VDD; the gate line pattern GATE, the light emission control signal line Both the pattern EM and the reset signal line pattern RST extend in the second direction, the power signal line pattern VDD includes a portion extending in the first direction; the first shielding member 404 is on the substrate 50
  • the orthographic projection of respectively overlaps with the orthographic projection of the grid line pattern GATE on the substrate 50 and the orthographic projection of the light-emitting control signal line pattern EM on the substrate 50, respectively.
  • the first shielding component 404 is laid out in the above-mentioned manner, so that the first shielding component 404 can isolate the first transistor T1 and the driving transistor from the target data line pattern (such as DATA2) Therefore, it is more beneficial to reduce the crosstalk caused by the change of the data signal on the target data line pattern to the first transistor T1 and the driving transistor.
  • the target data line pattern such as DATA2
  • the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel in various ways.
  • the anode of the light-emitting element is on the positive side of the substrate.
  • the head shadow overlaps the orthographic projection of the second electrode of the seventh transistor T7 on the substrate, and the anode of the light-emitting element can pass through the via hole provided at the overlap with the seventh transistor T7.
  • the second pole is coupled; or, the frontal shadow of the anode of the light-emitting element on the substrate does not overlap with the orthographic projection of the second electrode of the seventh transistor T7 on the substrate, and the sub
  • the pixel driving circuit further includes a second conductive connection portion 406 and a third conductive connection portion 407.
  • the orthographic projection of the anode of the light-emitting element on the substrate and the first end of the third conductive connection portion 407 are on the substrate.
  • the orthographic projections on the top overlap, the anode of the light-emitting element is coupled to the first end of the third conductive connection portion 407 through the via hole at the overlap, and the second end of the third conductive connection portion 407 is coupled to the first end of the third conductive connection portion 407.
  • the via hole at the overlap is coupled to the second end of the second conductive connection portion 406, so that the anode of the light-emitting element can be connected to the second conductive connection portion 406 and the third conductive connection portion 407.
  • the second electrode of the seventh transistor T7 is coupled.
  • the second conductive connection portion 406 may include an edge
  • the anode of the light-emitting element may be located on the upper side of the light-emitting control signal line pattern in the corresponding sub-pixel
  • the second electrode of the seventh transistor T7 may be located in the corresponding sub-pixel In the lower side of the light-emitting control signal line pattern.
  • the light-emitting element in the first color sub-pixel includes a first anode 601, a first organic light-emitting material layer, and a first cathode that are sequentially stacked in a direction away from the substrate; the orthographic projection of the first anode 601 on the substrate corresponds to the The orthographic projection of the second electrode of the seventh transistor T7 on the substrate overlaps, and the first anode 601 passes through the via hole at the overlap to correspond to the second electrode of the seventh transistor T7. Coupling.
  • the light-emitting element in the second color sub-pixel includes a second anode 602, a second organic light-emitting material layer, and a second cathode that are sequentially stacked in a direction away from the substrate; the positive head shadow of the second anode 602 on the substrate, and Correspondingly, the orthographic projection of the second electrode of the seventh transistor T7 on the substrate does not overlap, and the sub-pixel driving circuit in the second color sub-pixel further includes a second conductive connection portion 406 and a third conductive connection Portion 407, the second anode 602 is coupled to the corresponding second electrode of the seventh transistor T7 through the second conductive connection portion 406 and the third conductive connection portion 407.
  • the light-emitting element in the third color sub-pixel includes a third anode 603, a third organic light-emitting material layer, and a third cathode that are sequentially stacked in a direction away from the substrate; the orthographic projection of the third anode 603 on the substrate corresponds to the The second electrode of the seventh transistor T7 overlaps the orthographic projection on the substrate, and the third anode 603 is connected to the second electrode of the seventh transistor T7 through the via hole at the overlap. Coupling.
  • the anode of the organic light-emitting element of each color sub-pixel includes a main body electrode and a connection electrode, and the shape of the main body electrode is hexagonal.
  • the first anode 601 of the first color sub-pixel includes a first body electrode 6011 and a first connection electrode 6012.
  • the first body electrode 6011 and the first connection electrode 6012 may be an integral structure, and the first connection electrode 6012 is connected to the second electrode of the seventh transistor T7 of the first color sub-pixel through the connection hole.
  • the second anode 602 of the second color sub-pixel includes a second main body electrode 6021 and a second connection electrode 6022.
  • the second main body electrode 6021 and the second connection electrode 6022 may be an integral structure, and the second connection electrode 6022 is connected by a second conductivity.
  • the portion 406 and the third conductive connection portion 407 are connected to the second electrode of the seventh transistor T7 of the second color sub-pixel.
  • the third anode 603 of the third color sub-pixel includes a third main body electrode 6031 and a third connection electrode 6032.
  • the third main body electrode 6031 and the third connection electrode 6032 may be an integral structure, and the third connection electrode 6032 is connected to the third body electrode 6032 through the connection hole.
  • the second electrode of the seventh transistor T7 of the three-color sub-pixel is connected.
  • the first connection electrode 6012 of the first color sub-pixel is located on the side of the first main body electrode 6011 away from the data line pattern of the sub-pixel pixel circuit in the X direction, and located at the center of the first main electrode 6011 in the Y direction It is far away from the side of the light emission control signal line of the sub-pixel pixel circuit.
  • the first connection electrode 6012 and the first body electrode 6011 of the first color sub-pixel are arranged in the Y direction, and the first connection electrode 6012 is located at the lower right corner of the first body electrode 6011.
  • the second connection electrode 6022 of the second color sub-pixel is located on the side of the second main body electrode 6021 away from the data line of the sub-pixel pixel circuit in the X direction, and is located close to the center of the second main electrode 6021 in the Y direction.
  • the sub-pixel pixel circuit emits light on one side of the control signal line.
  • the second connection electrode 6022 and the second body electrode 6021 of the second color sub-pixel are arranged in the Y direction, and the second connection electrode 6022 is located at the lower right corner of the first body electrode 1231.
  • the third connection electrode 6032 and the third main body electrode 6031 of the third color sub-pixel are arranged in the X direction, and the third connection electrode 6032 is located on the right side of the third main body electrode 6031, that is, close to the sub-pixel pixel circuit and close to the shielding line. On the side.
  • the first body electrode 6011 of the first anode 601 of the first color sub-pixel covers the driving transistor of the first color sub-pixel
  • the driving transistors of the two color sub-pixels basically do not overlap or partially overlap
  • the third body electrode 6031 of the third anode 603 of the third color sub-image does not overlap the driving transistors of the third color sub-pixel.
  • the first body electrode 6011 of the first color sub-pixel 601 overlaps the gate line pattern and the light-emitting control signal line pattern; the second color sub-pixel (for example, the red sub-pixel) The second body electrode 6021 overlaps the gate line pattern and the reset signal line pattern; the third body electrode 6031 of the third color sub-pixel (such as the green sub-pixel) and the light-emitting control signal line pattern, the next row of sub-pixel drive circuit
  • the reset signal line pattern and the initialization signal line pattern of the sub-pixel driving circuit in the next row overlap.
  • the third body electrode 6031 of the third color sub-pixel overlaps the pixel driving circuit area of the first color sub-pixel (for example, the blue sub-pixel) adjacent to it in the next row.
  • the first body electrode 6011 of the first color sub-pixel 601 overlaps with a portion of the driving transistor of the adjacent third color sub-pixel, and the first body electrode 6011 of the first color sub-pixel 601 is in its sub-pixel driving circuit.
  • the data line patterns of the first shielding member 404, and the data line patterns in the sub-pixel driving circuit of the adjacent second color sub-pixel are all overlapped.
  • the second body electrode 6021 of the second color sub-pixel does not overlap with the data line pattern in the sub-pixel drive circuit, and the power signal line pattern in the sub-pixel drive circuit and the adjacent sub-pixel drive of the third color sub-pixel are not overlapped.
  • the power signal line pattern and the data line pattern in the circuit overlap.
  • the third body electrode 6031 of the third color sub-pixel overlaps with the data line pattern and power signal line pattern in the sub-pixel driving circuit, and overlaps with the power signal line in the sub-pixel driving circuit of the adjacent second color sub-pixel.
  • the first body electrode 6011 of the first color sub-pixel 601 is provided with a first connection electrode 6012 connected to it on the side close to the reset signal line pattern of the next row; the second body of the second color sub-pixel The side of the electrode 6021 close to the reset signal line pattern of the next row is provided with a second connecting electrode 6022 connected to it; the third body electrode 6031 of the third color sub-pixel is provided with a third connected to the side close to its seventh transistor T7. Connect the electrode 6032.
  • the first connection electrode 6012 of the first color sub-pixel 601 overlaps with the second electrode of the seventh transistor T7 in the sub-pixel driving circuit.
  • the second connection electrode 6022 of the second color sub-pixel does not overlap with the second electrode of the seventh transistor T7 in the sub-pixel driving circuit, and the second electrode of the seventh transistor T7 of the second color sub-pixel is not overlapped with the second electrode of the third color sub-pixel.
  • the third body electrode 6031 of the pixel overlaps.
  • the third connection electrode 6032 of the third color sub-pixel overlaps with the second electrode of the seventh transistor T7 in the sub-pixel driving circuit.
  • An embodiment of the present disclosure also provides a display device, which includes the display substrate provided in the foregoing embodiment.
  • the first shielding member 404 can reduce the influence of the signal change transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the gate of the driving transistor ( That is, the influence of the coupling between 203g) and the target data line pattern reduces the problem of vertical crosstalk, so that a better display effect can be obtained when the display substrate is used for display.
  • the first shielding member 404 is coupled to the initialization signal line pattern.
  • the initialization signal line is also strengthened. The voltage of the pattern makes the voltage of the initialization signal transmitted on the initialization signal line pattern more stable, which is more conducive to the working performance of the sub-pixel driving circuit.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • the embodiments of the present disclosure also provide a manufacturing method of a display substrate, which is used to manufacture the display substrate provided in the above-mentioned embodiments, and the manufacturing method includes:
  • a plurality of sub-pixels distributed in an array are fabricated on the substrate 50; the sub-pixels include:
  • a data line pattern extending along the first direction (DATA1 in Fig. 3);
  • the initialization signal line pattern (VINT1 in FIG. 3), the initialization signal line pattern includes a portion extending in a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used for transmission Initialization signal with fixed potential;
  • a sub-pixel driving circuit comprising: a driving transistor (T3 in FIG. 3), a first transistor T1 coupled to the gate of the driving transistor, and coupled to the initialization signal line pattern
  • a first shielding member 404 coupled to the initialization signal line pattern (VINT1 in FIG. 3) is provided in the sub-pixel driving circuit, so that The first shielding member 404 has the same fixed potential as the initialization signal, and is provided with an orthographic projection of the first shielding member 404 on the substrate 50, which is located on the front of the first transistor T1 on the substrate 50.
  • the projection and the target data line pattern (DATA2 in FIG. 3) are between the orthographic projection on the substrate 50, so that the first shielding member 404 can reduce the impact on the first transistor T1 due to the signal change transmitted on the target data line pattern.
  • the first shielding member 404 is coupled to the initialization signal line pattern, in addition to making the first shielding member 404 have a fixed potential, it also realizes The voltage of the initialization signal line pattern is strengthened, so that the voltage of the initialization signal transmitted on the initialization signal line pattern is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.
  • an embodiment of the present disclosure also provides a display substrate, including: a substrate 50 and a plurality of sub-pixels arranged in an array on the substrate 50; the sub-pixels include:
  • a data line pattern (such as DATA1) extending along the first direction;
  • the sub-pixel driving circuit includes: two switching transistors (such as the fourth transistor T4 and the fifth transistor T5), a driving transistor (such as the third transistor T3) and a storage capacitor Cst; the storage capacitor Cst
  • the first plate Cst1 is coupled to the gate of the driving transistor (such as the gate 203g of the third transistor T3), and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD;
  • the second poles of the two switching transistors (such as the drain D4 of the fourth transistor T4 and the drain D5 of the fifth transistor T5) are connected to the first pole of the driving transistor (such as the source S3 of the third transistor T3) Coupled, the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate 50 at least partially overlaps the orthographic projection of the power signal line pattern VDD on the substrate 50, And at least partially overlap with the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50.
  • the above-mentioned display substrate generally includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes: a data line pattern (such as DATA1) extending in a first direction, and a power signal line pattern VDD extending at least partially in the first direction;
  • a data line pattern such as DATA1
  • VDD power signal line pattern
  • the first direction includes the Y direction
  • the second direction includes the X direction.
  • the specific structure of the power signal line pattern VDD is various.
  • the power signal line pattern VDD is a grid-like structure, and the power signal line pattern VDD of the grid-like structure includes an edge along the first The part that extends in one direction.
  • Each sub-pixel also includes a sub-pixel drive circuit, and a light-emitting element corresponding to the sub-pixel drive circuit one-to-one.
  • the light-emitting element includes an anode, an organic light-emitting material layer, and a cathode that are stacked, wherein the anode of the light-emitting element is connected to the corresponding sub-pixel.
  • the driving circuit is coupled, and the light-emitting element realizes light emission under the driving of the driving signal provided by the sub-pixel driving circuit.
  • the gate 203g of the third transistor T3 (that is, the driving transistor) is multiplexed as the first plate of the storage capacitor Cst Cst1, the second plate Cst2 of the storage capacitor Cst is located on the side of the first plate Cst1 facing away from the substrate, and the orthographic projection of the first plate Cst1 on the substrate is the same as the first plate Cst1 on the substrate.
  • the orthographic projection of the diode Cst2 on the substrate at least partially overlaps, and the orthographic projection of the second electrode Cst2 on the substrate is switched with at least one of the fourth transistor T4 and the fifth transistor T5.
  • the orthographic projection of the second electrode of the transistor on the substrate 50 and the orthographic projection of the power signal line pattern VDD on the substrate 50 at least partially overlap.
  • the second electrode plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, so that the second electrode of the storage capacitor Cst
  • the board Cst2 has the same fixed potential as the power signal transmitted on the power signal line pattern VDD; at the same time, the second poles of the two switching transistors are both coupled to the first pole of the driving transistor, and the two The orthographic projection of the second electrode of at least one of the switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and overlaps with the storage capacitor Cst.
  • the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 at least partially overlaps, so that the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both be used for at least one of the two switching transistors.
  • the second pole of the switching transistor is shielded, thereby reducing the signal on other conductive patterns (such as signal line patterns) located around at least one of the two switching transistors.
  • the crosstalk phenomenon generated by the second pole of at least one switching transistor further reduces the crosstalk phenomenon generated on the first pole of the driving transistor.
  • the second pole of the two switching transistors (such as the fourth transistor T4 and the fifth transistor T5) and the first pole of the driving transistor (such as the third transistor T3)
  • the one-piece structure includes a first conductive portion 108 extending along the first direction, the orthographic projection of the first conductive portion 108 on the substrate, and the power signal line pattern VDD on the substrate
  • the orthographic projection, and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 there is a first overlap area, and the first overlap area and the data line pattern (such as DATA1) are in the The orthographic projections on the substrate 50 do not overlap.
  • the second poles of the two switching transistors and the first pole of the driving transistor are formed into an integrated structure, so that the second poles of the two switching transistors and the first pole of the driving transistor can pass through Formed by a patterning process.
  • the integrated structure is provided with a first conductive portion 108 extending along the first direction, and the orthographic projection of the data line pattern on the substrate is located on the first conductive portion 108
  • the orthographic projection on the substrate is far from the side of the orthographic projection of the driving transistor on the substrate, and the orthographic projection of the first conductive portion 108 on the substrate is consistent with the power signal line pattern
  • the orthographic projection of VDD on the substrate and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 have a first overlapping area, so that the second plate Cst2 of the storage capacitor Cst and the
  • the power signal line pattern VDD can all shield the first conductive portion 108, reduce the signal transmitted on the data line pattern, and cause crosstalk to the first conductive portion 108, thereby reducing the impact on the driving transistor.
  • the first pole of the crosstalk phenomenon is provided with a first conductive portion 108 extending along the first direction, and the orthographic projection of the data line pattern on the substrate is located
  • an orthographic projection of the first electrode of the driving transistor on the substrate 50 can be set, and the second electrode plate Cst2 of the storage capacitor Cst is located on the substrate. The interior of the orthographic projection.
  • the above arrangement allows the second electrode plate Cst2 of the storage capacitor Cst to completely cover the first electrode of the driving transistor, thereby more effectively reducing the signal transmitted on the data line pattern, which has a negative effect on the driving transistor.
  • the first pole of the crosstalk phenomenon is the second electrode plate Cst2 of the storage capacitor Cst.
  • the sub-pixel further includes: a gate line pattern GATE and a light-emission control signal line pattern EM that both extend in a second direction, and the second direction is the same as the first Intersect in one direction;
  • the sub-pixel driving circuit further includes: a first transistor T1 and a sixth transistor T6; the two switching transistors include a fourth transistor T4 and a fifth transistor T5;
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the first electrode of the fourth transistor T4 is coupled to the data line pattern (such as DATA1), and the fourth transistor T4
  • the second electrode is coupled to the second electrode of the fifth transistor T5, the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to The power signal line pattern VDD is coupled;
  • the gate 201g of the first transistor T1 is coupled to the gate line pattern GATE, the second electrode of the first transistor T1 is coupled to the gate of the driving transistor, and the first transistor T1 is The first electrode of the sixth transistor T6 and the second electrode of the driving transistor form an integral structure, and the integral structure includes a second conductive portion 109 extending along the first direction.
  • the sixth transistor T6 The gate 206g of T6 is coupled to the light-emitting control signal line pattern EM, and the second pole of the sixth transistor T6 is coupled to the light-emitting element in the sub-pixel;
  • the minimum distance between the orthographic projections of the channel region is smaller than the minimum distance between the orthographic projection of the channel region on the substrate 50 and the orthographic projection of the second conductive portion 109 on the substrate.
  • the plurality of sub-pixels included may be distributed in an array, and the plurality of sub-pixels may be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, and each row of sub-pixels includes a plurality of sub-pixels arranged in the second direction.
  • Each column of sub-pixels includes a plurality of sub-pixels arranged along a first direction, and the first direction intersects the second direction.
  • the sub-pixel driving circuit included in each column of sub-pixels is located between the data line patterns included in the column of sub-pixels and the data line patterns included in the next column of sub-pixels adjacent to the column of sub-pixels.
  • the minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive portion 108 on the substrate is Refers to: along the second direction, in the orthographic projection of the channel region of the driving transistor on the substrate, the boundary closest to the orthographic projection of the first conductive portion 108 on the substrate, and the The distance between the orthographic projection of the first conductive portion 108 on the substrate; in the second direction described above, the orthographic projection of the channel region on the substrate 50 is in line with the second conductive portion 109
  • the minimum distance between the orthographic projections on the substrate refers to: in the orthographic projection of the drive transistor on the substrate along the second direction, the channel region of the driving transistor is closest to the second conductive portion 109 in the orthographic projection. The distance between the boundary of the orthographic projection on the substrate and the orthographic projection of the second conductive portion 109 on the substrate.
  • the sub-pixel driving circuit included in each sub-pixel is located between two adjacent data line patterns (such as: DATA1 and DATA2). Because the data transmitted on the two data line patterns will change, And when the data changes, it is easy to cause crosstalk to the gate of the driving transistor in the sub-pixel driving circuit, as shown in FIG. 25, which further affects the working stability of the driving transistor.
  • the fourth transistor T4, the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all arranged in the peripheral area of the driving transistor, and arranged
  • One of the two data line patterns (such as DATA1) is located on the side of the fourth transistor T4 and the fifth transistor T5 away from the driving transistor, and the other of the two data line patterns ( Such as DATA2) is located on the side of the first transistor T1 and the sixth transistor T6 away from the driving transistor; at the same time, by setting the channel region of the driving transistor (103pg in FIG.
  • the channel region of the drive transistor The minimum distance between the orthographic projection on the substrate and the orthographic projection of the first conductive portion 108 on the substrate is smaller than the orthographic projection of the channel region on the substrate, and the first The minimum distance between the orthographic projections of the two conductive portions 109 on the substrate; the channel region of the driving transistor can be increased to the greatest extent while ensuring a proper distance from DATA1. The distance between the track area and DATA2, thereby better reducing the crosstalk generated by the DATA2 to the driving transistor.
  • the crosstalk caused by DATA1 to the channel region of the driving transistor can be effectively reduced. Therefore, the above In the technical solution provided by the embodiment, even if the channel region of the driving transistor is close to the DATA, the crosstalk influence is small.
  • the orthographic projection of the first conductive portion 108 on the substrate is similar to the The orthographic projection of the power signal line pattern VDD on the substrate and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 have a first overlap area, so that the second overlap area of the storage capacitor Cst Both the electrode plate Cst2 and the power signal line pattern VDD can shield the first conductive portion 108, reduce the signal transmitted on DATA1, generate crosstalk to the first conductive portion 108, and reduce the impact on the driving Crosstalk between the first pole of the transistor and the channel region.
  • the sub-pixel further includes: a gate line pattern GATE and a light emission control signal line pattern EM that both extend in a second direction, the second direction intersects the first direction ;
  • the sub-pixel driving circuit further includes: a first transistor T1 and a sixth transistor T6; the two switching transistors include a fourth transistor T4 and a fifth transistor T5;
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the first electrode of the fourth transistor T4 is coupled to the data line pattern (such as DATA1), and the fourth transistor T4
  • the second electrode is coupled to the second electrode of the fifth transistor T5, the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to The power signal line pattern VDD is coupled;
  • the gate 201g of the first transistor T1 is coupled to the gate line pattern GATE, the second electrode of the first transistor T1 is coupled to the gate of the driving transistor, and the first transistor T1 is
  • the first electrode of the sixth transistor T6 and the second electrode of the driving transistor form an integral structure, and the integral structure includes a second conductive portion 109 extending along the first direction.
  • the sixth transistor T6 The gate 206g of the transistor is coupled to the light-emitting control signal line pattern EM, and the second electrode of the sixth transistor T6 is coupled to the light-emitting element in the sub-pixel;
  • the orthographic projection of the channel region of the driving transistor (103pg in FIG. 18) on the substrate, and the orthographic projection of the first conductive portion 108 on the substrate is in the same direction as the second conductive portion 109
  • the first pole and the second pole of the drive transistor each include a first portion extending along the second direction, and the first portion of the first pole extends along the second direction The length is different from the length of the first part of the second pole extending in the second direction.
  • the first pole and the second pole of the driving transistor described above each include a first portion extending in the second direction, and the length of the first portion of the first pole in the second direction is the same as the length of the first pole in the second direction.
  • the lengths of the first part of the two poles that extend along the second direction are different, which specifically include the following two situations:
  • the length H1 of the first part of the first pole along the second direction is smaller than the length H2 of the first part of the second pole extending along the second direction, so that the channel of the driving transistor
  • the area (103pg in FIG. 18) is close to the data line pattern (such as DATA1) included in the sub-pixel where it is located, and far away from the data line pattern (such as DATA1) included in the next sub-pixel adjacent to the sub-pixel where it is located in the second direction DATA2), which enables the channel region of the driving transistor to meet the proper distance from DATA1 while maximizing the distance between the channel region of the driving transistor and DATA2, thereby better reducing the distance between the channel region of the driving transistor and DATA2
  • the crosstalk caused by the DATA2 to the drive transistor is also accounted for.
  • the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both shield the first conductive portion 108, the signal transmitted on DATA1 is reduced, and crosstalk is generated to the first conductive portion 108, In turn, the crosstalk phenomenon generated to the first electrode and the channel region of the driving transistor is reduced.
  • the length of the first portion of the first pole along the second direction is greater than the length of the first portion of the second pole extending along the second direction, so that the channel region of the drive transistor ( 103pg in Figure 18) is far away from the data line pattern (such as DATA1) included in the sub-pixel where it is located, and is close to the data line pattern (such as DATA2) included in the next sub-pixel adjacent to the sub-pixel where it is located in the second direction , Can make the channel region of the driving transistor meet the appropriate distance from DATA2, maximally increase the distance between the channel region of the driving transistor and DATA1, thereby better reducing the total distance.
  • the crosstalk caused by DATA1 to the driving transistor is far away from the data line pattern (such as DATA1) included in the sub-pixel where it is located, and is close to the data line pattern (such as DATA2) included in the next sub-pixel adjacent to the sub-pixel where it is located in the second direction .
  • the display substrate includes a first shielding member
  • the first shielding member can completely block DATA2 from the second conductive portion 109
  • the signal transmitted on DATA2 can be reduced, and crosstalk to the second conductive portion 109 can be generated. , Thereby reducing the crosstalk phenomenon generated to the second electrode and the channel region of the driving transistor.
  • the sub-pixel further includes an initialization signal line pattern (such as VINT1), and the initialization signal line pattern includes a portion extending in a second direction.
  • the first direction intersects, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;
  • the sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, and the second transistor T2 includes:
  • the orthographic projection of the third conductor pattern on the substrate, the orthographic projection of the first grid pattern on the substrate, and the orthographic projection of the second grid pattern on the substrate do not overlap ;
  • the orthographic projection of the third conductor pattern on the substrate at least partially overlaps the orthographic projection of the initialization signal line pattern on the substrate.
  • the above-mentioned second transistor T2 has a double-gate structure, and the first semiconductor pattern and the second semiconductor pattern included in it are formed as the channel region of the second transistor T2 (corresponding to FIG. 18), the third conductor pattern 102px included in it is doped, and the conductivity is better than that of the first semiconductor pattern and the second semiconductor pattern.
  • the second transistor T2 includes The first gate pattern and the second gate pattern cover the first semiconductor pattern and the second semiconductor pattern in a one-to-one correspondence, and can be used together as the gate 202g of the second transistor T2.
  • the orthographic projection of the third conductor pattern on the substrate 50 is set to at least partially overlap with the orthographic projection of the initialization signal line pattern on the substrate 50, so that the The initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the third conductor pattern 102px and other nearby conductive patterns are better reduced. The coupling effect between the graphics makes the working performance of the display substrate more stable.
  • the sub-pixel driving circuit further includes a first extension part extending from the first semiconductor pattern, and the conductivity of the first extension part is better than that of the first extension part.
  • the first semiconductor pattern; the first extension includes a first portion 61, a second portion 62 and a third portion 63, the first portion 61 and the third portion 63 extend along the first direction, the The second portion 62 extends along the second direction, one end of the second portion 62 is coupled to the first portion 61, and the other end of the second portion 62 is coupled to the third portion 63; An end of the third portion 63 away from the second portion 62 is coupled to the first transistor T1.
  • the first extension portion and the first semiconductor pattern can be fabricated in a single patterning process, and after the first semiconductor pattern is formed, the first extension portion is doped so that the first extension The conductivity of the part is better than that of the first semiconductor pattern.
  • the first extension portion is set to the above structure, so that when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor through the first extension portion, It is more conducive to reducing the impact of the signal change transmitted on the target data line pattern on the performance of the first transistor T1 and the performance of the second transistor T2, thereby reducing the gate of the driving transistor (ie 203g) and the target data line pattern
  • the influence of the coupling between them reduces the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.
  • the first transistor includes:
  • the third grid pattern and the fourth grid pattern are coupled to each other, and the orthographic projection of the third grid pattern on the substrate partially overlaps the orthographic projection of the fourth semiconductor pattern on the substrate, so The orthographic projection of the fourth grid pattern on the substrate partially overlaps the orthographic projection of the fifth semiconductor pattern on the substrate;
  • the orthographic projection of the sixth conductor pattern on the substrate, the orthographic projection of the third grid pattern on the substrate, and the orthographic projection of the fourth grid pattern on the substrate do not overlap .
  • the first transistor has a double gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included in it are formed as the channel region of the first transistor (corresponding to FIG. 18 101pg), the sixth conductor pattern 101px included in it is doped, and its conductivity is better than that of the fourth semiconductor pattern and the fifth semiconductor pattern, and the third gate of the first transistor
  • the electrode pattern and the fourth gate pattern cover the fourth semiconductor pattern and the fifth semiconductor pattern in a one-to-one correspondence, and can be used as the gate 201g of the first transistor T1.
  • the sub-pixel further includes an initialization signal line pattern (such as VINT1), and the initialization signal line pattern includes a portion extending in a second direction.
  • the first direction intersects, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;
  • the sub-pixel driving circuit further includes: a first shielding part 404 coupled to the initialization signal line pattern, and the orthographic projection of the first shielding part 404 on the substrate 50 is identical to the sixth conductor pattern 101px The orthographic projections on the substrate 50 at least partially overlap.
  • the orthographic projection of the first shielding member 404 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that The first shielding component 404 can cover the sixth conductor pattern 101px, and because the first shielding component 404 has a fixed potential, the sixth conductor pattern 101px and other nearby patterns are better reduced.
  • the coupling effect between the conductive patterns makes the working performance of the display substrate more stable.
  • the sub-pixel further includes an initialization signal line pattern (such as VINT1), and the initialization signal line pattern includes a portion extending in a second direction.
  • the first direction intersects, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;
  • the sub-pixel driving circuit further includes: a first shielding part 404 coupled to the initialization signal line pattern, and a second shielding part 301 coupled to the first shielding part 404, the second shielding part 301
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the sixth conductor pattern on the substrate.
  • the above-mentioned orthographic projection of the second shielding component 301 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px, and since the second shielding member 301 is coupled to the first shielding member 404, the second shielding member 301 has a fixed potential, thereby better reducing The coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns is reduced, so that the working performance of the display substrate is more stable.
  • the first shielding part 404 and the second shielding part 301 both have a fixed potential, it is better to prevent or reduce the first transistor T1 and the target data line pattern ( For example, parasitic capacitance is formed between DATA2), which effectively prevents or reduces vertical crosstalk defects.
  • the plurality of sub-pixels include multiple rows of sub-pixels, and each row of sub-pixels includes a plurality of the sub-pixels arranged along the second direction, and are located in the same row.
  • the initialization signal line patterns in the sub-pixels are sequentially coupled to form the initialization signal line corresponding to the row of sub-pixels; the first shielding part 404 extends along the first direction, and the first shielding part 404 is adjacent to it The two initialization signal lines are coupled.
  • the shape of the power signal line pattern can be laid out according to actual needs. For example, along the second direction, the width of the power signal line pattern near the channel region of the driving transistor, It is smaller than the width of the vicinity of the channel region away from the driving transistor, so that the influence of the power signal line pattern on the gate of the driving transistor can be reduced in the vicinity of the channel region of the driving transistor.
  • a compensation pattern 408 may be provided in the display substrate, and the compensation pattern 408 may be connected in parallel with the power signal line pattern to improve the transmission performance of the power signal line pattern.
  • the compensation pattern 408 and the third conductive connection portion 407 can be formed in the same layer and the same material, so that the compensation pattern 408 and the third conductive connection portion 407 can be formed in the same patterning process.
  • the orthographic projection of the power signal line pattern VDD on the substrate completely covers the orthographic projection of the first conductive portion 108 on the substrate.
  • the orthographic projection of the power signal line pattern VDD on the substrate covers the first semiconductor pattern, the second semiconductor pattern, and the third conductor pattern of the second transistor T2
  • the orthographic projection on the substrate also covers at least part of the orthographic projection of the first electrode of the second transistor T2 on the substrate, and the second electrode of the second transistor T2 is on the substrate At least part of the orthographic projection.
  • the first shielding member 404 is an extension structure extending from the initialization signal line pattern.
  • the first shielding part 404 is set as an extension structure extending from the initialization signal line pattern, so that the first shielding part 404 and the initialization signal line pattern can be formed in the same patterning process, thereby Better simplifies the manufacturing process flow of the display substrate.
  • the first shielding component 404 and the initialization signal line pattern are arranged in different layers, and the orthographic projection of the first shielding component 404 on the substrate 50 is different from the The orthographic projection of the initialization signal line pattern on the substrate 50 has a first overlap area, and the first shielding member is coupled to the initialization signal line pattern through a first via provided in the first overlap area;
  • the second shielding component 301 and the first shielding component 404 are arranged in different layers, and the orthographic projection of the second shielding component 301 on the substrate 50 is the same as that of the first shielding component 404 on the substrate 50. There is a second overlapping area in the orthographic projection, and the second shielding member 301 and the first shielding member 404 are coupled through a second via provided in the second overlapping area.
  • the first shielding component 404 and the initialization signal line pattern can be arranged in the same layer or in different layers.
  • the first shielding component 404 and the initialization signal line pattern are arranged in different layers, the The orthographic projection of the first shielding member 404 on the substrate 50 and the orthographic projection of the initialization signal line pattern on the substrate 50 both have a first overlap area, so that the first overlap area is provided in the first overlap area. Via holes can realize the coupling between the first shielding component 404 and the initialization signal line.
  • the second shielding component 301 and the first shielding component 404 can be provided in the same layer or in different layers.
  • the second shielding component 301 and the first shielding component 404 are provided in different layers, it can be provided There is a second overlapping area between the orthographic projection of the second shielding member 301 on the substrate 50 and the orthographic projection of the first shielding member 404 on the substrate 50. In this way, a second overlapping area is provided in the second overlapping area. Two vias, so that the second shielding component 301 and the first shielding component 404 can be coupled through the second vias.
  • the first shielding component 404 and the data line pattern are made of the same material.
  • the display substrate includes a first interlayer insulating layer, and both the first shielding member 404 and the data line pattern are located on a surface of the first interlayer insulating layer facing away from the substrate.
  • the first shielding member 404 is arranged in the above-mentioned manner, so that the first shielding member 404 and the data line pattern can be simultaneously formed on the back of the first interlayer insulating layer through a patterning process.
  • the surface of the substrate avoids adding an additional patterning process for manufacturing the first shielding component 404, thereby simplifying the manufacturing process of the display substrate and saving the manufacturing cost.
  • the second shielding component 301 and the initialization signal line pattern are made of the same material.
  • the display substrate further includes a second interlayer insulating layer, and the second shielding member 301 and the initialization signal line pattern are both located on the surface of the second interlayer insulating layer facing away from the substrate. .
  • the second shielding member 301 and the initialization signal line pattern are set with the same material, and the second shielding member 301 and the initialization signal line pattern (VINT1 in FIG. 3) are both located at the same material.
  • the second interlayer insulating layer faces away from the surface of the substrate, so that the second shielding member 301 and the initialization signal line pattern can be formed at the same time in the same patterning process, avoiding the addition of additional dedicated for manufacturing
  • the manufacturing process of the second shielding component 301 simplifies the manufacturing process of the display substrate and saves the production cost.
  • the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the driving transistor, and the second plate Cst2 of the storage capacitor Cst is the same as the second shielding member 301.
  • the material is set, and the second electrode plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate 50.
  • the storage capacitor Cst included in the sub-pixel driving circuit has a first electrode plate Cst1 and a second electrode plate Cst2, the first electrode plate Cst1 and the second electrode plate Cst2 are disposed oppositely, and the first electrode plate Cst2 A plate Cst1 is coupled to the gate of the driving transistor, and the second plate Cst2 is coupled to the power signal line pattern VDD.
  • the first plate Cst1 can be directly multiplexed as the gate of the driving transistor, which not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor, but also reduces the number of components.
  • the space occupied by the pixel drive circuit is more conducive to improving the resolution of the display substrate.
  • the second electrode plate Cst2 in the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second electrode plate Cst2 in the storage capacitor Cst can be connected to the first electrode plate Cst2.
  • the two shielding components 301 and the initialization signal line pattern are formed at the same time in the same patterning process, which greatly simplifies the manufacturing process of the display substrate and saves the production cost.
  • the sub-pixel further includes: a reset signal line pattern (such as RST1) extending in a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:
  • the second transistor T2 the first electrode (such as the source S2) of the second transistor T2 is coupled to the initialization signal line pattern (such as VINT1) through the first conductive connection portion 405, and the second transistor T2
  • the second electrode (such as the drain D2) of the second transistor is coupled to the gate of the driving transistor, and the gate 202g of the second transistor T2 is coupled to the reset signal line pattern (such as RST1).
  • the first conductive connection portion 405 can be made of a metal material, and can be formed in the same patterning process as the data line pattern.
  • the orthographic projection of the first conductive connecting portion 405 on the substrate 50 as described above covers at least part of the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the first conductive connecting portion 405 can be aligned with The sixth conductor pattern 101px is covered, and because the first conductive connection portion 405 is coupled to the initialization signal line pattern, the first conductive connection portion 405 has a fixed potential, thereby better reducing The coupling effect between the sixth conductive pattern 101px and other conductive patterns nearby makes the working performance of the display substrate more stable.
  • the sub-pixel further includes: a gate line pattern GATE, a light emission control signal line pattern EM, a reset signal line pattern (such as RST1), and an initialization signal line pattern (such as VINT1);
  • the gate line pattern GATE, the light emission control signal line pattern EM, the reset signal line pattern, and the initialization signal line pattern all extend in a second direction, and the second direction intersects the first direction;
  • the two switching transistors include a fourth transistor T4 and a fifth transistor T5;
  • the sub-pixel driving circuit further includes: a first transistor T1, a second transistor T2, a sixth transistor T6, and a seventh transistor T7;
  • the gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second electrode of the first transistor T1, and the first electrode of the driving transistor is connected to the second electrode of the fifth transistor T5. Pole coupled, the second pole of the driving transistor is coupled to the first pole of the first transistor T1;
  • the gate 201g of the first transistor T1 is coupled to the gate line pattern GATE;
  • the gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first electrode of the second transistor T2 is coupled to the initialization signal line pattern, and the second electrode of the second transistor T2 is coupled to the reset signal line pattern. Coupled with the gate of the driving transistor;
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the first electrode of the fourth transistor T4 is coupled to the data line pattern (DATA1 in Figure ()), the The second electrode of the fourth transistor T4 is coupled to the first electrode of the driving transistor;
  • the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern VDD;
  • the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the sixth transistor T6 The second pole of is coupled to the light-emitting element in the sub-pixel;
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) included in the next sub-pixel adjacent in the first direction, and the first electrode of the seventh transistor T7 is connected to the bottom
  • the initialization signal line pattern (such as VINT2) included in one sub-pixel is coupled, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.
  • the plurality of sub-pixels included may be distributed in an array, and the plurality of sub-pixels may be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, and each row of sub-pixels includes a plurality of sub-pixels arranged in the second direction.
  • Each column of sub-pixels includes a plurality of sub-pixels arranged along a first direction, and the first direction intersects the second direction.
  • next sub-pixel adjacent in the first direction is the next adjacent sub-pixel located in the same column as the seventh transistor T7.
  • Setting the sub-pixel and the sub-pixel driving circuit included in the above-mentioned structure can effectively reduce the layout space occupied by the sub-pixel driving circuit while ensuring the working performance of the sub-pixel driving circuit, which is beneficial to improve the display The resolution of the substrate.
  • An embodiment of the present disclosure also provides a display device, which includes the display substrate provided in the foregoing embodiment.
  • the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, the second plate Cst2 of the storage capacitor Cst is connected to the power signal line.
  • the power signal transmitted on the pattern VDD has the same fixed potential; at the same time, it is set that the second poles of the two switching transistors are coupled to the first pole of the driving transistor, and at least one of the two switching transistors is
  • the orthographic projection of the second electrode on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and overlaps with the second electrode plate Cst2 of the storage capacitor Cst in the
  • the orthographic projections on the substrate 50 at least partially overlap, so that the second electrode plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both shield the second electrode of at least one of the two switching transistors, Therefore, the signal on other conductive patterns (such as signal line patterns) located around at least one of the two switching transistors
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the embodiment of the present disclosure also provides a manufacturing method of a display substrate, the manufacturing method includes: manufacturing a plurality of sub-pixels distributed in an array on a substrate; the sub-pixels include: a data line pattern extending in a first direction; a power signal A line pattern, the power signal line pattern includes a portion extending along the first direction; a sub-pixel drive circuit, the sub-pixel drive circuit includes: two switching transistors, a drive transistor and a storage capacitor; the second of the storage capacitor One plate is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the power signal line pattern; the second electrodes of the two switching transistors are both connected to the gate of the driving transistor.
  • the first pole is coupled, the orthographic projection of the second pole of at least one of the two switching transistors on the substrate at least partially overlaps with the orthographic projection of the power signal line pattern on the substrate, And at least partially overlap with the orthographic projection of the second plate of the storage capacitor on the substrate.
  • the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, so that the second plate Cst2 of the storage capacitor Cst has the same
  • the power signal transmitted on the power signal line pattern VDD has the same fixed potential; at the same time, it is set that the second poles of the two switching transistors are both coupled to the first pole of the driving transistor, and the two switching transistors are
  • the orthographic projection of the second electrode of at least one switching transistor on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and overlaps with the second electrode of the storage capacitor Cst.
  • the orthographic projection of the plate Cst2 on the substrate 50 at least partially overlaps, so that the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both be used for the first switching transistor of at least one of the two switching transistors.
  • the two poles are shielded, thereby reducing the signal on other conductive patterns (such as signal line patterns) located around at least one of the two switching transistors.
  • the crosstalk phenomenon generated by the second pole of the drive transistor further reduces the crosstalk phenomenon generated on the first pole of the driving transistor.

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Abstract

一种显示基板及其制作方法、显示装置。所述显示基板包括：基底（50）和在基底（50）上阵列分布的多个子像素；子像素包括：沿第一方向延伸的数据线图形（DATA1）；初始化信号线图形（VINT1），初始化信号线图形（VINT1）包括沿第二方向延伸的部分，第二方向与第一方向相交，初始化信号线图形（VINT1）用于传输具有固定电位的初始化信号；子像素驱动电路，子像素驱动电路包括：驱动晶体管（T3），与驱动晶体管（T3）的栅极（203g）耦接的第一晶体管（T1），以及与初始化信号线图形（VINT1）耦接的第一屏蔽部件（404），第一屏蔽部件（404）在基底（50）上的正投影，位于第一晶体管（T1）在基底（50）上的正投影与目标数据线图形（DATA2）在基底（50）上的正投影之间；沿第二方向与该子像素相邻的下一个子像素中包括目标数据线图形（DATA2）。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示产品，以其亮度高、功耗低、响应快、清晰度高、柔性好、发光效率高等优点被广泛的应用在各个领域。
而随着OLED显示产品的应用范围越来越广泛，对OLED显示产品的显示质量要求越来越高，影响显示产品显示质量的因素多种多样，其中显示产品中包括的像素电路结构产生的垂直串扰现象作为重要因素受到人们的广泛关注，导致该垂直串扰现象的原因大致有两种，分别是显示产品中电源信号线上的压降造成的垂直串扰和数据线传输变化的数据信号造成的垂直串扰。
发明内容
本公开的目的在于提供一种显示基板及其制作方法、显示装置。
本公开的第一方面提供一种显示基板，包括：基底和在所述基底上阵列分布的多个子像素；所述子像素包括：
沿第一方向延伸的数据线图形；
初始化信号线图形，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
子像素驱动电路，所述子像素驱动电路包括：驱动晶体管，与所述驱动晶体管的栅极耦接的第一晶体管，以及与所述初始化信号线图形耦接的第一屏蔽部件，所述第一屏蔽部件在所述基底上的正投影，位于所述第一晶体管在所述基底上的正投影与目标数据线图形在所述基底上的正投影之间；沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
可选的，所述多个子像素包括多行子像素，每行子像素均包括沿所述第二方向排列的多个所述子像素，位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的初始化信号线；
所述第一屏蔽部件沿所述第一方向延伸，与至少一条所述初始化信号线耦接。
可选的，所述第一屏蔽部件与其相邻的两条所述初始化信号线耦接。
可选的，所述第一屏蔽部件与所述初始化信号线图形异层设置，所述第一屏蔽部件在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影存在第一重叠区域，所述第一屏蔽部件通过设置在所述第一重叠区域的第一过孔与所述初始化信号线图形耦接。
可选的，所述第一屏蔽部件与所述数据线图形同材料设置。
可选的，所述显示基板包括第一层间绝缘层，所述第一屏蔽部件与所述数据线图形均位于所述第一层间绝缘层背向所述基底的表面。
可选的，所述子像素驱动电路还包括与所述驱动晶体管的栅极耦接的第二晶体管，所述第二晶体管包括：
第一半导体图形、第二半导体图形和分别与所述第一半导体图形和所述第二半导体图形耦接的第三导体图形，所述第三导体图形的导电性能优于所述第一半导体图形的导电性能和所述第二半导体图形的导电性能；
相耦接的第一栅极图形和第二栅极图形，所述第一栅极图形在所述基底上的正投影与所述第一半导体图形在所述基底上的正投影至少部分重叠，所述第二栅极图形在所述基底上的正投影与所述第二半导体图形在所述基底上的正投影至少部分重叠；
所述第三导体图形在所述基底上的正投影与所述第一栅极图形在所述基底上的正投影，以及所述第二栅极图形在所述基底上的正投影均不重叠；
所述第三导体图形在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影至少部分重叠。
可选的，所述子像素驱动电路还包括由所述第一半导体图形延伸出的第一延伸部，所述第一延伸部的导电性能优于所述第一半导体图形；
所述第一延伸部包括第一部分、第二部分和第三部分，所述第一部分和 所述第三部分均沿所述第一方向延伸，所述第二部分沿所述第二方向延伸，所述第二部分的一端与所述第一部分耦接，所述第二部分的另一端与所述第三部分耦接；
所述第三部分远离所述第二部分的一端与所述第一晶体管耦接。
可选的，所述第一晶体管包括：
第四半导体图形、第五半导体图形和分别与所述第四半导体图形和所述第五半导体图形耦接的第六导体图形，所述第六导体图形的导电性能优于所述第四半导体图形的导电性能和所述第五半导体图形的导电性能；
相耦接的第三栅极图形和第四栅极图形，所述第三栅极图形在所述基底上的正投影与所述第四半导体图形在所述基底上的正投影部分重叠，所述第四栅极图形在所述基底上的正投影与所述第五半导体图形在所述基底上的正投影部分重叠；
所述第六导体图形在所述基底上的正投影与所述第三栅极图形在所述基底上的正投影，以及所述第四栅极图形在所述基底上的正投影均不重叠。
可选的，所述第一屏蔽部件在所述基底上的正投影，与所述第六导体图形在所述基底上的正投影至少部分重叠。
可选的，所述子像素驱动电路还包括：
与所述第一屏蔽部件耦接的第二屏蔽部件，所述第二屏蔽部件在所述基底上的正投影，与所述第六导体图形在所述基底上的正投影至少部分重叠。
可选的，所述第二屏蔽部件与所述第一屏蔽部件异层设置，所述第二屏蔽部件在所述基底上的正投影与所述第一屏蔽部件在所述基底上的正投影存在第二重叠区域，所述第二屏蔽部件与所述第一屏蔽部件之间通过设置在所述第二重叠区域的第二过孔耦接。
可选的，所述第二屏蔽部件与所述初始化信号线图形同材料设置。
可选的，所述显示基板还包括第二层间绝缘层，所述第二屏蔽部件与所述初始化信号线图形均位于所述第二层间绝缘层背向所述基底的表面。
可选的，所述子像素还包括电源信号线图形，所述电源信号线图形包括沿所述第一方向延伸的部分，所述子像素驱动电路还包括存储电容，所述存储电容中的第一极板复用为所述驱动晶体管的栅极，所述存储电容中的第二 极板与所述电源信号线图形耦接，所述存储电容中的第二极板位于所述第二层间绝缘层背向所述基底的表面。
可选的，所述子像素还包括：沿与所述第一方向相交的第二方向延伸的复位信号线图形，所述子像素驱动电路还包括：
第一导电连接部，所述第一导电连接部在所述基底上的正投影覆盖至少部分所述第六导体图形在所述基底上的正投影；
第二晶体管，所述第二晶体管的第一极通过所述第一导电连接部与所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接，所述第二晶体管的栅极与所述复位信号线图形耦接。
可选的，所述子像素还包括：栅线图形、发光控制信号线图形、复位信号线图形和电源信号线图形；所述栅线图形、所述发光控制信号线图形和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形包括沿所述第一方向延伸的部分；
所述子像素驱动电路还包括：第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述栅线图形耦接；
所述第二晶体管的栅极与所述复位信号线图形耦接，所述第二晶体管的第一极与所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所 述子像素中的发光元件耦接；
所述第七晶体管的栅极与沿所述第一方向相邻的下一个子像素包括的复位信号线图形耦接，所述第七晶体管的第一极与该下一个子像素包括的初始化信号线图形耦接，所述第七晶体管的第二极与所述子像素中的发光元件耦接。
可选的，所述子像素还包括：栅线图形、发光控制信号线图形、复位信号线图形和电源信号线图形；所述栅线图形、所述发光控制信号线图形和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形包括沿所述第一方向延伸的部分；所述第一屏蔽部件在所述基底上的正投影，分别与所述栅线图形在所述基底上的正投影，以及所述发光控制信号线图形在所述基底上的正投影部分交叠。
本公开的第二方面提供一种显示基板，包括：基底和在所述基底上阵列分布的多个子像素；所述子像素包括：
沿第一方向延伸的数据线图形；
初始化信号线图形，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
子像素驱动电路，所述子像素驱动电路包括：驱动晶体管，与所述驱动晶体管的栅极耦接的第一晶体管，以及与所述初始化信号线图形耦接的第一屏蔽部件，所述第一屏蔽部件用于与所述第一晶体管的第一极形成耦合电容，所述第一屏蔽部件在基底上正投影与目标数据线图形在所述基底上正投影不交叠，沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
可选的，所述阵列分布的多个子像素包括多行子像素，每行子像素均包括沿所述第二方向排列的所述子像素，位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的初始化信号线；
所述第一屏蔽部件沿所述第一方向延伸，与至少一条所述初始化信号线耦接。
可选的，所述第一屏蔽部件与其相邻的两条所述初始化信号线耦接。
可选的，所述第一屏蔽部件与所述初始化信号线图形异层设置，所述第一屏蔽部件在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影存在第一重叠区域，所述第一屏蔽部件通过设置在所述第一重叠区域的第一过孔与所述初始化信号线图形耦接。
可选的，所述第一屏蔽部件与所述数据线图形同材料设置。
可选的，所述显示基板包括第一层间绝缘层，所述第一屏蔽部件与所述数据线图形均位于所述第一层间绝缘层背向所述基底的表面。
可选的，所述子像素驱动电路还包括与所述驱动晶体管的栅极耦接的第二晶体管，所述第二晶体管包括：
第一半导体图形、第二半导体图形和分别与所述第一半导体图形和所述第二半导体图形耦接的第三导体图形，所述第三导体图形的导电性能优于所述第一半导体图形的导电性能和所述第二半导体图形的导电性能；
第一栅极图形和第二栅极图形，所述第一栅极图形在所述基底上的正投影与所述第一半导体图形在所述基底上的正投影至少部分重叠，所述第二栅极图形在所述基底上的正投影与所述第二半导体图形在所述基底上的正投影至少部分重叠；
所述第三导体图形在所述基底上的正投影与所述第一栅极图形在所述基底上的正投影，以及所述第二栅极图形在所述基底上的正投影均不重叠；
所述第三导体图形在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影至少部分重叠。
可选的，所述子像素驱动电路还包括由所述第一半导体图形延伸出的第一延伸部，所述第一延伸部的导电性能优于所述第一半导体图形；
所述第一延伸部包括第一部分、第二部分和第三部分，所述第一部分和所述第三部分均沿所述第一方向延伸，所述第二部分沿所述第二方向延伸，所述第二部分的一端与所述第一部分耦接，所述第二部分的另一端与所述第三部分耦接；
所述第三部分远离所述第二部分的一端与所述第一晶体管耦接。
可选的，所述第一晶体管包括：
第四半导体图形、第五半导体图形和分别与所述第四半导体图形和所述 第五半导体图形耦接的第六导体图形，所述第六导体图形的导电性能优于所述第四半导体图形的导电性能和所述第五半导体图形的导电性能；
相耦接的第三栅极图形和第四栅极图形，所述第三栅极图形在所述基底上的正投影与所述第四半导体图形在所述基底上的正投影部分重叠，所述第四栅极图形在所述基底上的正投影与所述第五半导体图形在所述基底上的正投影部分重叠；
所述第六导体图形在所述基底上的正投影与所述第三栅极图形在所述基底上的正投影，以及所述第四栅极图形在所述基底上的正投影均不重叠。
可选的，所述第一屏蔽部件在所述基底上的正投影，与所述第六导体图形在所述基底上的正投影至少部分重叠。
可选的，所述子像素驱动电路还包括：
与所述第一屏蔽部件耦接的第二屏蔽部件，所述第二屏蔽部件在所述基底上的正投影，与所述第六导体图形在所述基底上的正投影至少部分重叠。
可选的，所述第二屏蔽部件与所述第一屏蔽部件异层设置，所述第二屏蔽部件在所述基底上的正投影与所述第一屏蔽部件在所述基底上的正投影存在第二重叠区域，所述第二屏蔽部件与所述第一屏蔽部件之间通过设置在所述第二重叠区域的第二过孔耦接。
可选的，所述第二屏蔽部件与所述初始化信号线图形同材料设置。
可选的，所述显示基板还包括第二层间绝缘层，所述第二屏蔽部件与所述初始化信号线图形均位于所述第二层间绝缘层背向所述基底的表面。
可选的，所述子像素还包括电源信号线图形，所述电源信号线图形包括沿所述第一方向延伸的部分，所述子像素驱动电路还包括存储电容，所述存储电容中的第一极板复用为所述驱动晶体管的栅极，所述存储电容中的第二极板与所述电源信号线图形耦接，所述存储电容中的第二极板位于所述第二层间绝缘层背向所述基底的表面。
可选的，所述子像素还包括：沿与所述第一方向相交的第二方向延伸的复位信号线图形，所述子像素驱动电路还包括：
第一导电连接部，所述第一导电连接部在所述基底上的正投影覆盖至少部分所述第六导体图形在所述基底上的正投影；
第二晶体管，所述第二晶体管的第一极通过所述第一导电连接部与所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接，所述第二晶体管的栅极与所述复位信号线图形耦接。
可选的，所述子像素还包括：栅线图形、发光控制信号线图形、复位信号线图形和电源信号线图形；所述栅线图形、所述发光控制信号线图形和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形包括沿所述第一方向延伸的部分；
所述子像素驱动电路还包括：第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述栅线图形耦接；
所述第二晶体管的栅极与所述复位信号线图形耦接，所述第二晶体管的第一极与所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述子像素中的发光元件耦接；
所述第七晶体管的栅极与沿所述第一方向相邻的下一个子像素包括的复位信号线图形耦接，所述第七晶体管的第一极与该下一个子像素包括的初始化信号线图形耦接，所述第七晶体管的第二极与所述子像素中的发光元件耦接。
可选的，所述子像素还包括：栅线图形、发光控制信号线图形、复位信 号线图形和电源信号线图形；所述栅线图形、所述发光控制信号线图形和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形包括沿所述第一方向延伸的部分；所述第一屏蔽部件在所述基底上的正投影，分别与所述栅线图形在所述基底上的正投影，以及所述发光控制信号线图形在所述基底上的正投影部分交叠。
本公开的第三方面提供一种显示基板，包括：基底和在所述基底上阵列分布的多个子像素；所述子像素包括：
沿第一方向延伸的数据线图形；
电源信号线图形，所述电源信号线图形包括沿所述第一方向延伸的部分；
子像素驱动电路，所述子像素驱动电路包括：两个开关晶体管、驱动晶体管和存储电容；所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与所述电源信号线图形耦接；所述两个开关晶体管的第二极均与所述驱动晶体管的第一极耦接，所述两个开关晶体管中的至少一个开关晶体管的第二极在所述基底上的正投影，与所述电源信号线图形在所述基底上的正投影至少部分重叠，且与所述存储电容的第二极板在所述基底上的正投影至少部分重叠。
可选的，所述两个开关晶体管的第二极与所述驱动晶体管的第一极为一体结构，该一体结构包括沿所述第一方向延伸的第一导电部，该第一导电部在所述基底上的正投影，与所述电源信号线图形在所述基底上的正投影，以及所述存储电容的第二极板在所述基底上的正投影存在第一交叠区域，所述第一交叠区域与所述数据线图形在所述基底上的正投影不交叠。
可选的，所述驱动晶体管的第一极在所述基底上的正投影，位于所述存储电容的第二极板在所述基底上的正投影的内部。
可选的，所述子像素还包括：均沿第二方向延伸的栅线图形和发光控制信号线图形，所述第二方向与所述第一方向相交；
所述子像素驱动电路还包括：第一晶体管和第六晶体管；所述两个开关晶体管包括第四晶体管和第五晶体管；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述第五晶体管的第二 极耦接，所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第一晶体管的栅极与所述栅线图形耦接，所述第一晶体管的第二极与所述驱动晶体管的栅极耦接，所述第一晶体管的第一极、所述第六晶体管的第一极与所述驱动晶体管的第二极形成为一体结构，该一体结构包括沿所述第一方向延伸的第二导电部，所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第二极与所述子像素中的发光元件耦接；
所述驱动晶体管的沟道区在所述基底上的正投影，位于所述第一导电部在所述基底上的正投影与所述第二导电部在所述基底上的正投影之间；且沿所述第二方向，所述驱动晶体管的沟道区在所述基底上的正投影，与所述第一导电部在所述基底上的正投影之间的最小距离，小于所述沟道区在所述基底上的正投影，与所述第二导电部在所述基底上的正投影之间的最小距离。
可选的，所述子像素还包括：均沿第二方向延伸的栅线图形和发光控制信号线图形，所述第二方向与所述第一方向相交；
所述子像素驱动电路还包括：第一晶体管和第六晶体管；所述两个开关晶体管包括第四晶体管和第五晶体管；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述第五晶体管的第二极耦接，所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第一晶体管的栅极与所述栅线图形耦接，所述第一晶体管的第二极与所述驱动晶体管的栅极耦接，所述第一晶体管的第一极、所述第六晶体管的第一极与所述驱动晶体管的第二极形成为一体结构，该一体结构包括沿所述第一方向延伸的第二导电部，所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第二极与所述子像素中的发光元件耦接；
所述驱动晶体管的沟道区在所述基底上的正投影，位于所述第一导电部在所述基底上的正投影与所述第二导电部在所述基底上的正投影之间；所述驱动晶体管的第一极和第二极均包括沿所述第二方向延伸的第一部分，所述第一极的第一部分沿所述第二方向的长度与所述第二极的第一部分沿所述第 二方向延伸的长度不同。
基于上述显示基板的技术方案，本公开的第四方面提供一种显示装置，包括上述显示基板。
基于上述显示基板的技术方案，本公开的第五方面提供一种显示基板的制作方法，包括：
在基底上制作阵列分布的多个子像素；所述子像素包括：
沿第一方向延伸的数据线图形；
初始化信号线图形，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
子像素驱动电路，所述子像素驱动电路包括：驱动晶体管，与所述驱动晶体管的栅极耦接的第一晶体管，以及与所述初始化信号线图形耦接的第一屏蔽部件，所述第一屏蔽部件在所述基底上的正投影，位于所述第一晶体管在所述基底上的正投影与目标数据线图形在所述基底上的正投影之间；沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的子像素驱动电路的结构示意图；
图2为本公开实施例提供的子像素驱动电路对应的工作时序图；
图3为本公开实施例提供的显示基板中子像素驱动电路的第一布局示意图；
图4为本公开实施例提供的有源膜层的第一布局示意图；
图5为本公开实施例提供的第一栅金属层的第一布局示意图；
图6为本公开实施例提供的第二栅金属层的第一布局示意图；
图7为本公开实施例提供的源漏金属层的第一布局示意图。
图8为图3中沿A1A2方向的截面示意图；
图9为本公开实施例提供的显示基板中子像素驱动电路的第二布局示意图；
图10为本公开实施例提供的显示基板中子像素驱动电路的第三布局示意图；
图11为本公开实施例提供的显示基板中子像素驱动电路的第四布局示意图；
图12为本公开实施例提供的显示基板中子像素驱动电路的第五布局示意图；
图13为图11中沿B1B2方向的截面示意图；
图14为本公开实施例提供的显示基板中子像素驱动电路的第六布局示意图；
图15为本公开实施例提供的显示基板中多个子像素的第一布局示意图；
图16为本公开实施例提供的显示基板中子像素驱动电路的第七布局示意图；
图17为图16中沿C1C2方向的截面示意图；
图18为本公开实施例提供的有源膜层的第二布局示意图；
图19为本公开实施例提供的显示基板中子像素驱动电路的第八布局示意图；
图20为本公开实施例提供的显示基板中子像素驱动电路的第九布局示意图；
图21为本公开实施例提供的显示基板中子像素驱动电路的第十布局示意图；
图22为图21中沿D1D2方向的截面示意图；
图23为第三金属层的布局示意图；
图24为本公开实施例提供的显示基板中多个子像素的第二布局示意图；
图25为相关技术中驱动晶体管的栅极出现的串扰现象示意图；
图26本公开实施例提供的显示基板中子像素驱动电路的第十一布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
OLED显示产品中产生垂直串扰的原因大致包括：电源信号线上的压降造成的垂直串扰，以及数据线上加载变化的数据信号造成的垂直串扰；其中，由数据线造成的垂直串扰是导致OLED显示产品出现垂直串扰现象的主要因素，因此，如何解决由数据线造成的垂直串扰成为亟待解决的问题。
基于上述问题的存在，本公开的发明人经研究发现，可在数据线和受到该数据线串扰的部分之间设置屏蔽图形，通过该屏蔽图形减小数据线和所述部分之间的耦合影响，从而减弱由数据线产生的垂直串扰的问题，使显示产品实现更好的显示效果。
需要说明，本文描述的一个或多个实施方式对应于具有7TlC(即7个薄膜晶体管和1个电容)子像素驱动电路的显示基板。在另一实施方式中，所述显示基板可包括不同的子像素驱动电路，例如，大于或小于7个薄膜晶体管，以及包括一个或多个电容器。
如图1所示，本公开提供的显示基板中包括多个子像素，各子像素可均包括：栅线图形GATE、第一复位信号线图形RST1、第一初始化信号线图形VINT1、数据线图形DATA、发光控制信号线图形EM、电源信号线图形VDD、第二复位信号线图形RST2和第二初始化信号线图形VINT2。
各子像素中的子像素驱动电路可均包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和存储电容Cst。另外，图1中还包括了第一电容C1，该第一电容C1是寄生电容。
以一个子像素驱动电路为例，该子像素驱动电路包括的各晶体管均采用P型晶体管，其中，第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与栅线图形GATE耦接，第一晶体管T1的源极S1与第三晶体管T3的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。
第二晶体管T2为双栅结构，第二晶体管T2的栅极202g与第一复位信号线图形RST1耦接，第二晶体管T2的源极S2与第一初始化信号线图形VINT1耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
第四晶体管T4的栅极204g与所述栅线图形GATE耦接，第四晶体管T4的源极S4与数据线图形DATA耦接，第四晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。
第五晶体管T5的栅极205g与发光控制信号线图形EM耦接，第五晶体管T5的源极S5与电源信号线图形VDD耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与发光控制信号线图形EM耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6与发光元件OLED的阳极耦接。
第七晶体管T7的栅极207g与第二复位信号线图形RST2耦接，第七晶体管T7的漏极D7与所述发光元件OLED的阳极耦接，第七晶体管T7的源极S7与第二初始化信号线图形VINT2耦接。
存储电容Cst的第一极板Cst1与第三晶体管T3的栅极203g耦接，存储电容Cst的第二极板Cst2与所述电源信号线图形VDD耦接。
如图2所示，上述结构的子像素驱动电路在工作时，每个工作周期均包括第一复位时段P1、写入补偿时段P2、第二复位时段P3和发光时段P4。
在所述第一复位时段P1，第一复位信号线图形RST1输入的第一复位信号处于有效电平，第二晶体管T2导通，由第一初始化信号线图形VINT1传输的初始化信号输入至第三晶体管T3的栅极203g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位。
在写入补偿时段P2，所述第一复位信号处于非有效电平，第二晶体管T2截止，栅线图形GATE输入的栅极扫描信号处于有效电平，控制第一晶体管T1和第四晶体管T4导通，数据线图形DATA写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的源极S3，同时，第一晶体管T1和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管 T1、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在第二复位时段P3，所述栅极扫描信号处于非有效电平，第一晶体管T1和第四晶体管T4均截止，第二复位信号线RST2输入的第二复位信号处于有效电平，控制第七晶体管T7导通，由第二初始化信号线图形VINT2传输的初始化信号输入至发光元件OLED的阳极，控制发光元件OLED不发光。
在发光时段P4，发光控制信号线图形EM写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源信号线图形VDD传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件OLED的阳极，驱动对应的发光元件OLED发光。
如图3所示，在制作上述子像素驱动电路时，子像素驱动电路对应的各膜层的布局如下：
沿远离基底的方向上依次层叠设置的有源膜层、栅极绝缘层、第一栅金属层、第一层间绝缘层、第二栅金属层、第二层间绝缘层、第一源漏金属层和第三层间绝缘层。
如图4所示，有源膜层用于形成子像素驱动电路中各晶体管的沟道区(如：101pg～107pg)，源极形成区(如：101ps～107ps)和漏极形成区(如：101pd～107pd)，源极形成区和漏极形成区对应的有源膜层由于掺杂作用，导电性能会优于沟道区对应的有源膜层；有源膜层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
另外，值得注意，所述源极形成区和漏极形成区对应的有源膜层可直接作为对应的源极或漏极，或者，也可以采用金属材料制作与所述源极形成区接触的源极，采用金属材料制作与所述漏极形成区接触的漏极。
如图5所示，第一栅金属层用于形成子像素驱动电路中各晶体管的栅极(如：201g～207g)，以及显示基板包括的栅线图形GATE、发光控制信号线图形EM、第一复位信号线图形RST1和第二复位信号线图形RST2等结构，每个子像素驱动电路中的第三晶体管T3的栅极203g均复用为该子像素驱动电路中的存储电容Cst的第一极板Cst1。
如图6所示，第二栅金属层用于形成存储电容Cst的第二极板Cst2，以及显示基板包括的第一初始化信号线图形VINT1和第二初始化信号线图形VINT2。
如图1、图3和7所示，第一源漏金属层用于形成子像素驱动电路中各晶体管的源极(如：S1～S7)和漏极(如：D1～D7)，以及显示基板包括的数据线图形(如DATA1和DATA2)和电源信号线图形VDD。
更详细地说，请继续参阅图3、图7～图10，第一晶体管T1的栅极201g覆盖第一沟道区101pg，第一晶体管T1的源极S1位于第一源极形成区101ps，第一晶体管T1的漏极D1位于第一漏极形成区101pd。
第二晶体管T2的栅极202g覆盖第二沟道区102pg，第二晶体管T2的源极S2位于第二源极形成区102ps，第二晶体管T2的漏极D2位于第二漏极形成区102pd。
第三晶体管T3的栅极203g覆盖第三沟道区103pg，第三晶体管T3的源极S3位于第三源极形成区103ps，第三晶体管T3的漏极D3位于第三漏极形成区103pd。
第四晶体管T4的栅极204g覆盖第四沟道区104pg，第四晶体管T4的源极S4位于第四源极形成区104ps，第四晶体管T4的漏极D4位于第四漏极形成区104pd。
第五晶体管T5的栅极205g覆盖第五沟道区105pg，第五晶体管T5的源极S5位于第五源极形成区105ps，第五晶体管T5的漏极D5位于第五漏极形成区105pd。
第六晶体管T6的栅极206g覆盖第六沟道区106pg，第六晶体管T6的源极S6位于第六源极形成区106ps，第六晶体管T6的漏极D6位于第六漏极形成区106pd。
第七晶体管T7的栅极207g覆盖第七沟道区107pg，第七晶体管T7的源极S7位于第七源极形成区107ps，第七晶体管T7的漏极D7位于第七漏极形成区107pd。
第三晶体管T3的栅极203g复用为存储电容Cst的第一极板Cst1，存储电容Cst的第二极板Cst2与电源信号线图形VDD耦接。
需要说明，图1中的连接线401、402和403，均是由第一源漏金属层形成，具体布局如图3和图7所示。图1中的第一电容C1为寄生电容，如图3所示，存储电容Cst的第二极板Cst2在基底上的正投影与第四晶体管T4对应的第四漏极形成区104pd的向下延长部分在基底上的正投影存在重叠区域，该重叠区域即形成为所示第一电容C1。
另外，本公开提供的显示基板中，包括的多个子像素可呈阵列分布，所述多个子像素可划分为多行子像素和多列子像素，每行子像素均包括沿第二方向排列的多个子像素，每列子像素均包括沿第一方向排列的多个子像素，所述第一方向与所述第二方向相交；所述子像素中包括的栅线图形GATE、第一复位信号线图形RST1、第一初始化信号线图形VINT1、发光控制信号线图形EM、第二复位信号线图形RST2和第二初始化信号线图形VINT2可均沿第二方向延伸；所述子像素中包括的数据线图形DATA和电源信号线图形VDD均沿第一方向延伸。
位于同一行的栅线图形GATE可形成为一体结构的一条栅线，位于同一行的第一复位信号线图形RST1可形成为一体结构的一条第一复位信号线，位于同一行的第一初始化信号线图形VINT1可形成为一体结构的一条第一初始化信号线，位于同一行的发光控制信号线图形EM可形成为一体结构的一条发光控制信号线，位于同一行的第二复位信号线图形RST2可形成为一体结构的一条第二复位信号线，位于同一行的第二初始化信号线图形VINT2可形成为一体结构的一条第二初始化信号线。位于同一列的数据线图形DATA可形成为一体结构的一条数据线，位于同一列的电源信号线图形VDD可形成为一体结构的一条电源信号线。
为了简化子像素的布局空间，可将一行子像素对应的第二复位信号线复用为相邻的下一行子像素对应的第一复位信号线；同样的，可将一行子像素 对应的第二初始化信号线复用为相邻的下一行子像素对应的第一初始化信号线。
如图3所示，在一些实施例中，以一个子像素中包括的子像素驱动电路为例，在第一方向(如Y方向)上，第四晶体管T4的栅极204g、第一晶体管T1的栅极201g和第二晶体管T2的栅极202g均位于驱动晶体管的栅极(即第三晶体管T3的栅极203g)的第一侧，第七晶体管T7的栅极、第六晶体管T6的栅极206g、第五晶体管T5的栅极均位于驱动晶体管的栅极的第二侧。示例性的，所述驱动晶体管的栅极的第一侧和第二侧为在第一方向上驱动晶体管的栅极的彼此相对的两侧，进一步地，驱动晶体管的栅极的第一侧可以为驱动晶体管的栅极的上侧，驱动晶体管的栅极的第二侧可以为驱动晶体管T1的栅极的下侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管的栅极的下侧，为驱动晶体管的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管的栅极的更远离IC的一侧。
在一些实施例中，如图3所示，在第二方向(如X方向)上，第四晶体管T4的栅极204g和第五晶体管T5的栅极205g均位于驱动晶体管的栅极的第三侧，第一晶体管T1的栅极201g和第六晶体管T6的栅极206g均位于驱动晶体管T1的栅极的第四侧。示例性的，驱动晶体管的栅极的第三侧和第四侧为在第二方向X上驱动晶体管的栅极的彼此相对的两侧；进一步地，驱动晶体管的栅极的第三侧可以为驱动晶体管的栅极的左侧，驱动晶体管的栅极的第四侧可以为驱动晶体管的栅极的右侧。所述左侧和右侧，例如在同一子像素中，第一数据线图形DATA1位于电源信号线图形VDD左侧，电源信号线图形VDD在第一数据线图形DATA1右侧。
请参阅图3和图8，本公开实施例提供了一种显示基板，包括：基底50和在所述基底50上阵列分布的多个子像素；所述子像素包括：
沿第一方向延伸的数据线图形(如图3中的DATA1)；
初始化信号线图形(如图3中的VINT1)，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
子像素驱动电路，所述子像素驱动电路包括：驱动晶体管(如图3中的 T3)，与所述驱动晶体管的栅极耦接的第一晶体管T1，以及与所述初始化信号线图形耦接的第一屏蔽部件404，所述第一屏蔽部件404在所述基底50上的正投影，位于所述第一晶体管T1在所述基底50上的正投影与目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间；沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
具体地，上述显示基板一般包括阵列分布的多个子像素，每个子像素均包括：沿第一方向延伸的数据线图形(如图3中的DATA1)，以及至少部分沿第二方向延伸的初始化信号线图形(如图3中的VINT1)；所述数据线图形用于传输数据信号，所述初始化信号线图形用于传输具有固定电位的初始化信号；示例性的，所述第一方向包括Y方向，所述第二方向包括X方向。
所述目标数据线图形为：沿所述第二方向，与当前子像素相邻的下一个子像素中包括的数据线图形。
每个子像素还包括子像素驱动电路，以及与所述子像素驱动电路一一对应的发光元件，发光元件包括层叠设置的阳极、有机发光材料层和阴极，其中发光元件的阳极与对应的子像素驱动电路耦接，在子像素驱动电路提供的驱动信号的驱动下，发光元件实现发光。
更详细地说，如图1、图3和图4所示，以子像素驱动电路包括上述7T1C为例，第三晶体管T3(即所述驱动晶体管)的栅极203g通过连接线401与第一晶体管T1的漏极D1耦接，第三晶体管T3的漏极D3与第一晶体管T1的源极S1耦接。沿X方向，所述第一晶体管T1的第一沟道区101pg在所述基底50上的正投影，与所述目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间最小距离，小于第三晶体管T3的第三沟道区103pg在所述基底50上的正投影，与所述目标数据线图形在所述基底50上的正投影之间最小距离。值得注意，上述沟道区(如：第一沟道区101pg和第三沟道区103pg)在所述基底50上的正投影，与所述目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间最小距离是指：该沟道区在所述基底50上的正投影中最靠近所述目标数据线图形的边界，与所述目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间的最小距离。
上述结构的子像素驱动电路中，当目标数据线图形传输的数据信号发生 变化时，会对第一晶体管T1的性能产生影响，由于第一晶体管T1通过连接线401与第三晶体管T3耦接，进而对第三晶体管T3的工作性能产生影响。
本公开实施例在所述子像素驱动电路中设置了与所述初始化信号线图形(如图3中的VINT1)耦接的第一屏蔽部件404，使第一屏蔽部件404具有与所述初始化信号相同的固定电位，并设置所述第一屏蔽部件404在所述基底50上的正投影，位于所述第一晶体管T1在所述基底50上的正投影与目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间，使得第一屏蔽部件404能够减小由于目标数据线图形上传输的信号变化对第一晶体管T1的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。
另外，上述将所述第一屏蔽部件404与所述初始化信号线图形耦接，除了使得第一屏蔽部件404具有固定电位之外，还实现了加强了初始化信号线图形的电压，使得初始化信号线图形上传输的初始化信号的电压更稳定，从而更有利于子像素驱动电路的工作性能。
值得注意，除了将所述第一屏蔽部件404与所述初始化信号线图形耦接外，还可以将第一屏蔽部件404与所述子像素包括的电源信号线图形VDD耦接，使得所述第一屏蔽部件404具有与电源信号线图形VDD传输的电源信号相同的固定电位。
上述将所述第一屏蔽部件404与所述电源信号线图形VDD耦接的方式，虽然能够保证所述第一屏蔽部件404具有固定的电位，但是会增大电源信号线图形VDD产生的寄生电容，使得电源信号线图形VDD的RC负载更大，不利于减弱垂直串扰现象。
如图3所示，在一些实施例中，所述第一晶体管T1的栅极201g和所述栅线图形GATE为一体结构，所述第一晶体管T1的栅极201g为该一体结构中能够在垂直于所述基底的方向上与有源膜层形成交叠区域的部分。
如图3所示，在一些实施例中，所述多个子像素包括多行子像素，每行子像素均包括沿所述第二方向排列的多个所述子像素，位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的初始化信号线； 所述第一屏蔽部件404沿所述第一方向延伸，与至少一条所述初始化信号线耦接。
具体地，所述多个子像素可划分为多行子像素和多列子像素，每行子像素均包括沿第二方向排列的多个子像素，每列子像素均包括沿第一方向排列的多个子像素，所述第一方向与所述第二方向相交；位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的一条初始化信号线。
上述设置所述第一屏蔽部件404沿所述第一方向延伸，并与至少一条所述初始化信号线耦接，不仅使得第一屏蔽部件404能够减小由于目标数据线图形上传输的信号变化对第一晶体管T1的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果；而且，还实现了加强了初始化信号线的电压，使得初始化信号线上传输的初始化信号的电压更稳定，从而更有利于子像素驱动电路的工作性能。
如图9所示，在一些实施例中，所述第一屏蔽部件404与其相邻的两条所述初始化信号线耦接。
具体地，当设置所述第一屏蔽部件404与所述初始化信号线耦接时，所述第一屏蔽部件404与所述初始化信号线的耦接方式，以及所述第一屏蔽部件404的具体结构和设置方式均多种多样，示例性的，如图3所示，可设置所述第一屏蔽部件404分别与其相邻的两条所述初始化信号线耦接；这种设置方式，使得所述第一屏蔽部件404在所述基底50上的正投影，不仅位于所述第一晶体管T1在所述基底50的正投影与所述目标数据线图形在所述基底50的正投影之间；还使得所述第一屏蔽部件404在所述基底50上的正投影，能够位于连接线401在所述基底50上的正投影与所述目标数据线图形在所述基底50上的正投影之间；同时还使得所述第一屏蔽部件404在所述基底50上的正投影，能够位于所述驱动晶体管(即第三晶体管T3)在所述基底50上的正投影与所述目标数据线图形在所述基底50上的正投影之间。
上述设置方式很好的降低了所述目标信号线图形与所述第一晶体管T1之间产生的第一串扰，以及所述目标信号线图形与连接线401之间产生的第二串扰，从而降低了由于上述第一串扰和第二串扰导致的对驱动晶体管产生 的间接串扰。另外，上述设置方式还降低了所述目标信号线图形与所述驱动晶体管之间产生的直接串扰，从而更好的保证了显示基板的工作性能。
请继续参阅图3，在一些实施例中，所述第一屏蔽部件404与所述初始化信号线图形(如图3中的VINT1)异层设置，所述第一屏蔽部件404在所述基底50上的正投影，与所述初始化信号线图形在所述基底上的正投影存在第一重叠区域，所述第一屏蔽部件404通过设置在所述第一重叠区域的第一过孔与所述初始化信号线图形耦接。
具体地，所述第一屏蔽部件404可与所述初始化信号线图形同层设置或异层设置，当所述第一屏蔽部件404与所述初始化信号线图形异层设置时，可设置所述第一屏蔽部件404在所述基底50上的正投影，与所述初始化信号线图形在所述基底50上的正投影均存在第一重叠区域，这样通过在所述第一重叠区域设置第一过孔，即可实现所述第一屏蔽部件404与所述初始化信号线之间的耦接。
需要说明，上述“所述第一屏蔽部件404可与所述初始化信号线图形同层设置”包括：所述第一屏蔽部件404与所述初始化信号线图形位于同一水平面上；所述第一屏蔽部件404与所述初始化信号线图形位于同一层膜层；所述第一屏蔽部件404与所述初始化信号线图形均设置在同一层绝缘层背向基底的表面；以及所述第一屏蔽部件404与所述初始化信号线图形采用一次构图工艺形成等多种情况中的至少一种。
上述“所述第一屏蔽部件404可与所述初始化信号线图形异层设置”包括：所述第一屏蔽部件404与所述初始化信号线图形不位于同一层膜层；所述第一屏蔽部件404与所述初始化信号线图形无法采用一次构图工艺形成等多种情况中的至少一种。
在一些实施例中，可设置所述第一屏蔽部件404与所述数据线图形(如图3中的DATA1)同材料设置。
在一些实施例中，可设置所述显示基板包括第一层间绝缘层，所述第一屏蔽部件404与所述数据线图形(如图3中的DATA1)均位于所述第一层间绝缘层背向所述基底的表面。
具体地，按照上述方式设置所述第一屏蔽部件404，使得能够通过一次 构图工艺，将所述第一屏蔽部件404与所述数据线图形同时形成在所述第一层间绝缘层背向所述基底的表面，避免为了制作所述第一屏蔽部件404而增加额外的构图工艺，从而很好的简化了显示基板的制作流程，节约了制作成本。
如图3所示，在一些实施例中，所述子像素驱动电路还包括与所述驱动晶体管的栅极耦接的第二晶体管T2，所述第二晶体管T2包括：
第一半导体图形、第二半导体图形和分别与所述第一半导体图形和所述第二半导体图形耦接的第三导体图形，所述第三导体图形的导电性能优于所述第一半导体图形的导电性能和所述第二半导体图形的导电性能；
相耦接的第一栅极图形和第二栅极图形，所述第一栅极图形在所述基底50上的正投影与所述第一半导体图形在所述基底50上的正投影部分重叠，所述第二栅极图形在所述基底50上的正投影与所述第二半导体图形在所述基底50上的正投影部分重叠；
所述第三导体图形在所述基底50上的正投影与所述第一栅极图形在所述基底50上的正投影，以及所述第二栅极图形在所述基底50上的正投影均不重叠；
所述第三导体图形在所述基底50上的正投影，与所述初始化信号线图形(如图3中的VINT1)在所述基底50上的正投影至少部分重叠。
具体地，如图7所示，上述第二晶体管T2为双栅结构，其包括的所述第一半导体图形和所述第二半导体图形形成为所述第二晶体管T2的沟道区(对应图7中的标记102pg位置)，其包括的所述第三导体图形102px由于进行了掺杂，导电性能优于所述第一半导体图形和所述第二半导体图形，所述第二晶体管T2包括的第一栅极图形和第二栅极图形一一对应覆盖所述第一半导体图形和所述第二半导体图形，可共同作为所述第二晶体管T2的栅极202g。
上述结构的第二晶体管T2中，由于所述第三导体图形102px具有良好的导电性能，且未被栅极图形覆盖，因此，容易与其附近的其他导电图形之间耦合，产生串扰现象。上述实施例提供的技术方案中，通过设置所述第三导体图形在所述基底50上的正投影，与所述初始化信号线图形(如图3中的VINT1)在所述基底50上的正投影至少部分重叠，使得所述初始化信号线图 形能够对所述第三导体图形102px进行遮盖，由于所述初始化信号线图形上传输具有固定电位的初始化信号，更好的减小了所述第三导体图形102px与其附近的其他导电图形之间的耦合作用，从而使得显示基板的工作性能更稳定。
如图4所示，在一些实施例中，所述子像素驱动电路还包括由所述第一半导体图形延伸出的第一延伸部，所述第一延伸部的导电性能优于所述第一半导体图形；所述第一延伸部包括第一部分61、第二部分62和第三部分63，所述第一部分61和所述第三部分63均沿所述第一方向延伸，所述第二部分62沿所述第二方向延伸，所述第二部分62的一端与所述第一部分61耦接，所述第二部分62的另一端与所述第三部分63耦接；所述第三部分63远离所述第二部分62的一端与所述第一晶体管T1耦接。
具体地，所述第一延伸部可与所述第一半导体图形在一次构图工艺中制作，并在形成所述第一半导体图形后，对该第一延伸部进行掺杂，使得该第一延伸部的导电性能优于所述第一半导体图形。
在增加第一屏蔽部件404之后，将所述第一延伸部设置为上述结构，使得第二晶体管T2在通过所述第一延伸部分别与第一晶体管T1和驱动晶体管的栅极耦接时，更有利于降低由于目标数据线图形上传输的信号变化对第一晶体管T1的性能，以及第二晶体管T2的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。
如图3和图4所示，在一些实施例中，所述第一晶体管T1包括：
第四半导体图形、第五半导体图形和分别与所述第四半导体图形和所述第五半导体图形耦接的第六导体图形，所述第六导体图形的导电性能优于所述第四半导体图形的导电性能和所述第五半导体图形的导电性能；
相耦接的第三栅极图形和第四栅极图形，所述第三栅极图形在所述基底50上的正投影与所述第四半导体图形在所述基底50上的正投影部分重叠，所述第四栅极图形在所述基底50上的正投影与所述第五半导体图形在所述基底50上的正投影部分重叠；
所述第六导体图形在所述基底50上的正投影与所述第三栅极图形在所 述基底50上的正投影，以及所述第四栅极图形在所述基底50上的正投影均不重叠。
具体地，如图4所示，所述第一晶体管为双栅结构，其包括的所述第四半导体图形和所述第五半导体图形形成为所述第一晶体管的沟道区(对应图4中的标记101pg)，其包括的所述第六导体图形101px由于进行了掺杂，导电性能优于所述第四半导体图形和所述第五半导体图形，所述第一晶体管包括的第三栅极图形和第四栅极图形一一对应覆盖所述第四半导体图形和所述第五半导体图形，可共同作为所述第一晶体管T1的栅极201g。
如图10所示，在一些实施例中，所述第一屏蔽部件404在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠。
具体地，上述结构的第一晶体管T1中，由于所述第六导体图形101px具有良好的导电性能，且未被栅极图形覆盖，因此，容易与其附近的其他导电图形之间耦合，产生串扰现象。上述实施例提供的技术方案中，通过设置所述第一屏蔽部件404在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠，使得所述第一屏蔽部件404能够对所述第六导体图形101px进行遮盖，且由于所述第一屏蔽部件404具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
如图11、图12和图13所示，在一些实施例中，所述子像素驱动电路还包括：与所述第一屏蔽部件404耦接的第二屏蔽部件301，所述第二屏蔽部件301在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠。
具体地，上述设置所述第二屏蔽部件301在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠，使得所述第二屏蔽部件301能够对所述第六导体图形101px进行遮盖，且由于所述第二屏蔽部件301与所述第一屏蔽部件404耦接，使所述第二屏蔽部件301具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
因此，上述实施例提供的显示基板中，由于所述第一屏蔽部件404和所述第二屏蔽部件301均具有固定电位，从而更好的防止或减少了第一晶体管T1与目标数据线图形(如DATA2)之间形成寄生电容，有效防止或减少了垂直串扰缺陷。
进一步地，可设置所述第二屏蔽部件301在所述基底50上的正投影覆盖所述第六导体图形在所述基底50上的正投影的全部。
具体地，设置所述第二屏蔽部件301在所述基底50上的正投影覆盖所述第六导体图形101px在所述基底50上的正投影的全部，使得所述第二屏蔽部件301能够将所述第六导体图形101px完全遮盖，从而最大限度的减小所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，更好的提升显示基板的工作稳定性。
在一些实施例中，所述第二屏蔽部件301与所述第一屏蔽部件404异层设置，所述第二屏蔽部件301在所述基底50上的正投影与所述第一屏蔽部件404在所述基底50上的正投影存在第二重叠区域，所述第二屏蔽部件301与所述第一屏蔽部件404之间通过设置在所述第二重叠区域的第二过孔耦接。
具体地，所述第二屏蔽部件301可与所述第一屏蔽部件404同层设置或异层设置，当所述第二屏蔽部件301与所述第一屏蔽部件404异层设置时，可设置所述第二屏蔽部件301在所述基底50上的正投影与所述第一屏蔽部件404在所述基底50上的正投影存在第二重叠区域，这样通过在所述第二重叠区域设置第二过孔，使得所述第二屏蔽部件301与所述第一屏蔽部件404之间能够通过所述第二过孔实现耦接。
在一些实施例中，可设置所述第二屏蔽部件301与所述初始化信号线图形同材料设置。
在一些实施例中，可设置所述显示基板还包括第二层间绝缘层，所述第二屏蔽部件301与所述初始化信号线图形(如图3中的VINT1)均位于所述第二层间绝缘层背向所述基底的表面。
具体地，上述将所述第二屏蔽部件301与所述初始化信号线图形同材料设置，并将所述第二屏蔽部件301与所述初始化信号线图形(如图3中的VINT1)均位于所述第二层间绝缘层背向所述基底的表面，使得所述第二屏 蔽部件301能够与所述初始化信号线图形在同一次构图工艺中同时形成，避免了增加额外的专门用于制作所述第二屏蔽部件301的制作工艺，从而很好的简化了显示基板的制作流程，节约了生产成本。
如图3所示，在一些实施例中，所述子像素还包括电源信号线图形VDD，所述电源信号线图形VDD包括沿所述第一方向延伸的部分，所述子像素驱动电路还包括存储电容Cst，所述存储电容Cst中的第一极板Cst1复用为所述驱动晶体管的栅极，所述存储电容Cst中的第二极板Cst2与所述电源信号线图形VDD耦接，所述存储电容Cst中的第二极板Cst2位于所述第二层间绝缘层背向所述基底的表面。
具体地，所述子像素驱动电路中包括的存储电容Cst具有第一极板Cst1和第二极板Cst2，所述第一极板Cst1和所述第二极板Cst2相对设置，且所述第一极板Cst1与所述驱动晶体管的栅极耦接，所述第二极板Cst2与所述电源信号线图形VDD耦接。在布局该存储电容Cst时，可将所述第一极板Cst1直接复用为所述驱动晶体管的栅极，这样不仅保证了存储电容Cst与驱动晶体管的栅极实现耦接，还缩小了子像素驱动电路占用的空间，更有利于提升显示基板的分辨率。另外，设置所述存储电容Cst中的第二极板Cst2位于所述第二层间绝缘层背向所述基底的表面，使得所述存储电容Cst中的第二极板Cst2能够与所述第二屏蔽部件301和所述初始化信号线图形在同一次构图工艺中同时形成，从而很好的简化了显示基板的制作流程，节约了生产成本。
如图14所示，在一些实施例中，所述子像素还包括：沿与所述第一方向相交的第二方向延伸的复位信号线图形(如图3中的RST1)，所述子像素驱动电路还包括：
第一导电连接部405，所述第一导电连接部405在所述基底50上的正投影覆盖至少部分所述第六导体图形101px在所述基底50上的正投影；
第二晶体管T2，所述第二晶体管T2的第一极(如源极S2)通过所述第一导电连接部405与所述初始化信号线图形(如VINT1)耦接，所述第二晶体管T2的第二极(如漏极D2)与所述驱动晶体管的栅极耦接，所述第二晶体管T2的栅极202g与所述复位信号线图形(如RST1)耦接。
具体地，所述第一导电连接部405可采用金属材料制作，并可与数据线 图形在同一次构图工艺中形成。
上述设置所述第一导电连接部405在所述基底50上的正投影覆盖至少部分所述第六导体图形101px在所述基底50上的正投影，使得所述第一导电连接部405能够对所述第六导体图形101px进行遮盖，且由于所述第一导电连接部405与所述初始化信号线图形耦接，使所述第一导电连接部405具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
如图3所示，在一些实施例中，所述子像素还包括：栅线图形GATE、发光控制信号线图形EM、复位信号线图形(如图3中的RST1)和电源信号线图形VDD；所述栅线图形GATE、所述发光控制信号线图形EM和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形VDD包括沿所述第一方向延伸的部分；
所述子像素驱动电路还包括：第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7；
所述驱动晶体管的栅极(如第三晶体管T3的栅极203g)与所述第一晶体管T1的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管T5的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管T1的第一极耦接；
所述第一晶体管T1的栅极201g与所述栅线图形GATE耦接；
所述第二晶体管T2的栅极202g与所述复位信号线图形耦接，所述第二晶体管T2的第一极与所述初始化信号线图形耦接，所述第二晶体管T2的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管T4的栅极204g与所述栅线图形GATE耦接，所述第四晶体管T4的第一极与所述数据线图形(如图3中的DATA1)耦接，所述第四晶体管T4的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管T5的栅极205g与所述发光控制信号线图形EM耦接，所述第五晶体管T5的第一极与所述电源信号线图形VDD耦接；
所述第六晶体管T6的栅极206g与所述发光控制信号线图形EM耦接，所述第六晶体管T6的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管T6的第二极与所述子像素中的发光元件耦接；
所述第七晶体管T7的栅极207g与沿所述第一方向相邻的下一个子像素包括的复位信号线图形(如RST2)耦接，所述第七晶体管T7的第一极与该下一个子像素包括的初始化信号线图形(如VINT2)耦接，所述第七晶体管T7的第二极与所述子像素中的发光元件耦接。
具体地，上述显示基板中，包括的多个子像素可呈阵列分布，所述多个子像素可划分为多行子像素和多列子像素，每行子像素均包括沿第二方向排列的多个子像素，每列子像素均包括沿第一方向排列的多个子像素，所述第一方向与所述第二方向相交。
需要说明，上述沿所述第一方向相邻的下一个子像素，即与该第七晶体管T7位于同一列的相邻的下一个子像素。
将所述子像素和其包括的子像素驱动电路设置为上述结构，能够在保证子像素驱动电路的工作性能的情况下，有效减小所述子像素驱动电路占用的布局空间，有利于提升显示基板的分辨率。
需要说明，所述子像素驱动电路中包括的各晶体管的栅极，与其耦接的功能图形可形成为一体结构，示例性的，第一晶体管的栅极和第四晶体管的栅极均与对应耦接的栅线图形为一体结构，第五晶体管的栅极和第六晶体管的栅极均与对应耦接的发光控制信号线图形为一体结构，第二晶体管的栅极和第七晶体管的栅极与对应耦接的复位信号线图形为一体结构。
另外，所述第一晶体管T1用于对所述驱动晶体管(如第三晶体管T3)进行阈值补偿，所述第二晶体管T2用于对所述驱动晶体管的栅极进行复位，所述第四晶体管T4用于写入所述数据线图形传输的数据信号，所述第五晶体管T5用于向所述驱动晶体管的第一极写入电源信号线图形传输的电源信号，所述第六晶体管T6用于控制对应的发光元件是否发光，所述第七晶体管T7用于对所述发光元件的阳极进行复位。
在一些实施例中，所述子像素还包括：栅线图形GATE、发光控制信号线图形EM、复位信号线图形RST和电源信号线图形VDD；所述栅线图形GATE、所述发光控制信号线图形EM和所述复位信号线图形RST均沿所述第二方向延伸，所述电源信号线图形VDD包括沿所述第一方向延伸的部分；所述第一屏蔽部件404在所述基底50上的正投影，分别与所述栅线图形GATE 在所述基底50上的正投影，以及所述发光控制信号线图形EM在所述基底50上的正投影部分交叠。
具体地，将所述第一屏蔽部件404按照上述方式布局，使得所述第一屏蔽部件404能够将所述第一晶体管T1、所述驱动晶体管均与所述目标数据线图形(如DATA2)隔离，从而更有利于减小所述目标数据线图形上数据信号变化，对所述第一晶体管T1和所述驱动晶体管引起的串扰。
在一些实施例中，所述第七晶体管T7的第二极与所述子像素中的发光元件耦接的方式多种多样，示例性的，所述发光元件的阳极在所述基底上的正头影，与所述第七晶体管T7的第二极在所述基底上的正投影交叠，所述发光元件的阳极能够通过设置在该交叠处的过孔与所述第七晶体管T7的第二极耦接；或者，所述发光元件的阳极在所述基底上的正头影，与所述第七晶体管T7的第二极在所述基底上的正投影不交叠，所述子像素驱动电路还包括第二导电连接部406和第三导电连接部407，所述发光元件的阳极在所述基底上的正投影与所述第三导电连接部407的第一端在所述基底上的正投影交叠，所述发光元件的阳极通过在该交叠处的过孔与所述第三导电连接部407的第一端耦接，第三导电连接部407的第二端与第二导电连接部406的第一端交叠，第三导电连接部407的第二端与第二导电连接部406的第一端通过在该交叠处的过孔实现耦接，所述第七晶体管T7的第二极在所述基底上的正投影与所述第二导电连接部406的第二端在所述基底上的正投影交叠，所述第七晶体管T7的第二极通过在该交叠处的过孔与所述第二导电连接部406的第二端耦接，从而实现所述发光元件的阳极能够通过所述第二导电连接部406和第三导电连接部407与所述第七晶体管T7的第二极耦接。
当设置所述发光元件的阳极通过所述第二导电连接部406和第三导电连接部407与所述第七晶体管T7的第二极耦接时，所述第二导电连接部406可包括沿所述第一方向延伸的部分，所述发光元件的阳极可位于其对应的子像素中的发光控制信号线图形的上侧，所述第七晶体管T7的第二极可位于其对应的子像素中的发光控制信号线图形的下侧。
如图15和图24所示，以图中示出的三种颜色的子像素为例，对该三种颜色的子像素的结构进行说明。
第一颜色子像素中的发光元件包括沿远离基底的方向依次层叠设置的第一阳极601、第一有机发光材料层和第一阴极；第一阳极601在所述基底上的正投影与对应的所述第七晶体管T7的第二极在所述基底上的正投影部分交叠，所述第一阳极601通过在该交叠处的过孔与对应的所述第七晶体管T7的第二极耦接。
第二颜色子像素中的发光元件包括沿远离基底的方向依次层叠设置的第二阳极602、第二有机发光材料层和第二阴极；第二阳极602在所述基底上的正头影，与对应的所述第七晶体管T7的第二极在所述基底上的正投影不交叠，所述第二颜色子像素中的子像素驱动电路还包括第二导电连接部406和第三导电连接部407，所述第二阳极602通过第二导电连接部406和第三导电连接部407与对应的所述第七晶体管T7的第二极耦接。
第三颜色子像素中的发光元件包括沿远离基底的方向依次层叠设置的第三阳极603、第三有机发光材料层和第三阴极；第三阳极603在所述基底上的正投影与对应的所述第七晶体管T7的第二极在所述基底上的正投影部分交叠，所述第三阳极603通过在该交叠处的过孔与对应的所述第七晶体管T7的第二极耦接。
例如，如图15所示，各颜色子像素的有机发光元件的阳极均包括主体电极和连接电极，且主体电极的形状均为六边形。
如图15所示，第一颜色子像素的第一阳极601包括第一主体电极6011和第一连接电极6012，第一主体电极6011和第一连接电极6012可以为一体结构，且第一连接电极6012通过连接孔实现与第一颜色子像素的第七晶体管T7的第二极相连。第二颜色子像素的第二阳极602包括第二主体电极6021和第二连接电极6022，第二主体电极6021和第二连接电极6022可以为一体结构，且第二连接电极6022通过第二导电连接部406和第三导电连接部407与第二颜色子像素的第七晶体管T7的第二极相连。第三颜色子像素的第三阳极603包括第三主体电极6031和第三连接电极6032，第三主体电极6031和第三连接电极6032可以为一体结构，且第三连接电极6032通过连接孔与第三颜色子像素的第七晶体管T7的第二极相连。
例如第一颜色子像素的第一连接电极6012，在X方向上位于第一主体电 极6011中心远离该子像素像素电路的数据线图形的一侧，且在Y方向上位于第一主体电极6011中心远离该子像素像素电路的发光控制信号线的一侧。例如第一颜色子像素的第一连接电极6012和第一主体电极6011在Y方向排布，第一连接电极6012位于第一主体电极6011的右下角。例如，第二颜色子像素的第二连接电极6022，在X方向上位于第二主体电极6021中心远离该子像素像素电路数据线的一侧，且在Y方向上位于第二主体电极6021中心靠近该子像素像素电路发光控制信号线的一侧。例如，第二颜色子像素的第二连接电极6022和第二主体电极6021在Y方向排布，第二连接电极6022位于第一主体电极1231的右下角。例如，第三颜色子像素的第三连接电极6032与第三主体电极6031在X方向排布，第三连接电极6032位于第三主体电极6031的右侧，即靠近该子像素像素电路靠近屏蔽线的一侧。
如图15所示，第一颜色子像素的第一阳极601的第一主体电极6011覆盖第一颜色子像素的驱动晶体管，第二颜色子像素的第二阳极602的第二主体电极6021与第二颜色子像素的驱动晶体管基本没有交叠或者有部分交叠，第三颜色子像的第三阳极603的第三主体电极6031与第三颜色子像素的驱动晶体管没有交叠。
如图15所示，第一颜色子像素601(例如蓝色子像素)的第一主体电极6011与栅线图形和发光控制信号线图形有交叠；第二颜色子像素(例如红色子像素)的第二主体电极6021与栅线图形和复位信号线图形有交叠；第三颜色子像素(例如绿色子像素)的第三主体电极6031与发光控制信号线图形、下一行子像素驱动电路的复位信号线图形以及下一行子像素驱动电路的初始化信号线图形有交叠。例如第三颜色子像素(例如绿色子像素)的第三主体电极6031与下一行与其相邻的第一颜色子像素(例如蓝色子像素)的像素驱动电路区域有交叠。
例如，第一颜色子像素601的第一主体电极6011与相邻的第三颜色子像素的驱动晶体管的部分交叠，且第一颜色子像素601的第一主体电极6011与其子像素驱动电路中的数据线图形、第一屏蔽部件404以及相邻第二颜色子像素的子像素驱动电路中的数据线图形均有交叠。第二颜色子像素的第二主体电极6021与其子像素驱动电路中的数据线图形没有交叠，且与其子像素驱 动电路中的电源信号线图形和相邻的第三颜色子像素的子像素驱动电路中的电源信号线图形以及数据线图形均有交叠。第三颜色子像素的第三主体电极6031与其子像素驱动电路中的数据线图形和电源信号线图形均有交叠，且与相邻第二颜色子像素的子像素驱动电路中的电源信号线图形有交叠。
例如，如图15所示，第一颜色子像素601的第一主体电极6011靠近下一行复位信号线图形的一侧设置有与其连接的第一连接电极6012；第二颜色子像素的第二主体电极6021靠近下一行复位信号线图形的一侧设置有与其连接的第二连接电极6022；第三颜色子像素的第三主体电极6031靠近其第七晶体管T7的一侧设置有与其连接的第三连接电极6032。
例如，如图15所示，第一颜色子像素601的第一连接电极6012与其子像素驱动电路中的第七晶体管T7的第二极有交叠。第二颜色子像素的第二连接电极6022与其子像素驱动电路中的第七晶体管T7的第二极没有交叠，而第二颜色子像素的第七晶体管T7的第二极与第三颜色子像素的第三主体电极6031有交叠。第三颜色子像素的第三连接电极6032与其子像素驱动电路中的第七晶体管T7的第二极有交叠。
如图26所示，本公开实施例还提供了一种显示基板，包括：基底50和在所述基底50上阵列分布的多个子像素；所述子像素包括：
沿第一方向延伸的数据线图形(如：DATA1)；
初始化信号线图形(如：VINT1)，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
子像素驱动电路，所述子像素驱动电路包括：驱动晶体管(如：第三晶体管T3)，与所述驱动晶体管的栅极耦接的第一晶体管T1，以及与所述初始化信号线图形耦接的第一屏蔽部件404，所述第一屏蔽部件404用于与所述第一晶体管T1的第一极(即源极S1)形成耦合电容，所述第一屏蔽部件404在基底50上正投影与目标数据线图形(如DATA2)在所述基底50上正投影不交叠，沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
具体地，上述显示基板一般包括阵列分布的多个子像素，每个子像素均 包括：沿第一方向延伸的数据线图形(如图3中的DATA1)，以及至少部分沿第二方向延伸的初始化信号线图形(如图3中的VINT1)；所述数据线图形用于传输数据信号，所述初始化信号线图形用于传输具有固定电位的初始化信号；示例性的，所述第一方向包括Y方向，所述第二方向包括X方向。
所述目标数据线图形为：沿所述第二方向，与当前子像素相邻的下一个子像素中包括的数据线图形。
每个子像素还包括子像素驱动电路，以及与所述子像素驱动电路一一对应的发光元件，发光元件包括层叠设置的阳极、有机发光材料层和阴极，其中发光元件的阳极与对应的子像素驱动电路耦接，在子像素驱动电路提供的驱动信号的驱动下，发光元件实现发光。
更详细地说，如图1、图3和图4所示，以子像素驱动电路包括上述7T1C为例，第三晶体管T3(即所述驱动晶体管)的栅极203g通过连接线401与第一晶体管T1的漏极D1耦接，第三晶体管T3的漏极D3与第一晶体管T1的源极S1耦接。沿X方向，所述第一晶体管T1的第一沟道区101pg在所述基底50上的正投影，与所述目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间最小距离，小于第三晶体管T3的第三沟道区103pg在所述基底50上的正投影，与所述目标数据线图形在所述基底50上的正投影之间最小距离。值得注意，上述沟道区(如：第一沟道区101pg和第三沟道区103pg)在所述基底50上的正投影，与所述目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间最小距离是指：该沟道区在所述基底50上的正投影中最靠近所述目标数据线图形的边界，与所述目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间的最小距离。
上述结构的子像素驱动电路中，当目标数据线图形传输的数据信号发生变化时，会对第一晶体管T1的性能产生影响，由于第一晶体管T1通过连接线401与第三晶体管T3耦接，进而对第三晶体管T3的工作性能产生影响。
本公开实施例在所述子像素驱动电路中设置了与所述初始化信号线图形(如图3中的VINT1)耦接的第一屏蔽部件404，使第一屏蔽部件404具有与所述初始化信号相同的固定电位，并设置所述第一屏蔽部件404能够与所述第一晶体管T1的第一极(即源极S1)形成耦合电容，使得第一屏蔽部件 404能够减小由于目标数据线图形上传输的信号变化对第一晶体管T1的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。
另外，上述将所述第一屏蔽部件404与所述初始化信号线图形耦接，除了使得第一屏蔽部件404具有固定电位之外，还实现了加强了初始化信号线图形的电压，使得初始化信号线图形上传输的初始化信号的电压更稳定，从而更有利于子像素驱动电路的工作性能。
值得注意，除了将所述第一屏蔽部件404与所述初始化信号线图形耦接外，还可以将第一屏蔽部件404与所述子像素包括的电源信号线图形VDD耦接，使得所述第一屏蔽部件404具有与电源信号线图形VDD传输的电源信号相同的固定电位。
上述将所述第一屏蔽部件404与所述电源信号线图形VDD耦接的方式，虽然能够保证所述第一屏蔽部件404具有固定的电位，但是会增大电源信号线图形VDD产生的寄生电容，使得电源信号线图形VDD的RC负载更大，不利于减弱垂直串扰现象。
如图3所示，在一些实施例中，所述第一晶体管T1的栅极201g和所述栅线图形GATE为一体结构，所述第一晶体管T1的栅极201g为该一体结构中能够在垂直于所述基底的方向上与有源膜层形成交叠区域的部分。
如图3所示，在一些实施例中，所述多个子像素包括多行子像素，每行子像素均包括沿所述第二方向排列的多个所述子像素，位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的初始化信号线；所述第一屏蔽部件404沿所述第一方向延伸，与至少一条所述初始化信号线耦接。
具体地，所述多个子像素可划分为多行子像素和多列子像素，每行子像素均包括沿第二方向排列的多个子像素，每列子像素均包括沿第一方向排列的多个子像素，所述第一方向与所述第二方向相交；位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的一条初始化信号线。
上述设置所述第一屏蔽部件404沿所述第一方向延伸，并与至少一条所 述初始化信号线耦接，不仅使得第一屏蔽部件404能够减小由于目标数据线图形上传输的信号变化对第一晶体管T1的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果；而且，还实现了加强了初始化信号线的电压，使得初始化信号线上传输的初始化信号的电压更稳定，从而更有利于子像素驱动电路的工作性能。
如图9所示，在一些实施例中，所述第一屏蔽部件404与其相邻的两条所述初始化信号线耦接。
具体地，当设置所述第一屏蔽部件404与所述初始化信号线耦接时，所述第一屏蔽部件404与所述初始化信号线的耦接方式，以及所述第一屏蔽部件404的具体结构和设置方式均多种多样，示例性的，如图3所示，可设置所述第一屏蔽部件404分别与其相邻的两条所述初始化信号线耦接；这种设置方式，使得所述第一屏蔽部件404在所述基底50上的正投影，不仅位于所述第一晶体管T1在所述基底50的正投影与所述目标数据线图形在所述基底50的正投影之间；还使得所述第一屏蔽部件404在所述基底50上的正投影，能够位于连接线401在所述基底50上的正投影与所述目标数据线图形在所述基底50上的正投影之间；同时还使得所述第一屏蔽部件404在所述基底50上的正投影，能够位于所述驱动晶体管(即第三晶体管T3)在所述基底50上的正投影与所述目标数据线图形在所述基底50上的正投影之间。
上述设置方式很好的降低了所述目标信号线图形与所述第一晶体管T1之间产生的第一串扰，以及所述目标信号线图形与连接线401之间产生的第二串扰，从而降低了由于上述第一串扰和第二串扰导致的对驱动晶体管产生的间接串扰。另外，上述设置方式还降低了所述目标信号线图形与所述驱动晶体管之间产生的直接串扰，从而更好的保证了显示基板的工作性能。
请继续参阅图3，在一些实施例中，所述第一屏蔽部件404与所述初始化信号线图形(如图3中的VINT1)异层设置，所述第一屏蔽部件404在所述基底50上的正投影，与所述初始化信号线图形在所述基底上的正投影存在第一重叠区域，所述第一屏蔽部件404通过设置在所述第一重叠区域的第一过孔与所述初始化信号线图形耦接。
具体地，所述第一屏蔽部件404可与所述初始化信号线图形同层设置或异层设置，当所述第一屏蔽部件404与所述初始化信号线图形异层设置时，可设置所述第一屏蔽部件404在所述基底50上的正投影，与所述初始化信号线图形在所述基底50上的正投影均存在第一重叠区域，这样通过在所述第一重叠区域设置第一过孔，即可实现所述第一屏蔽部件404与所述初始化信号线之间的耦接。
需要说明，上述“所述第一屏蔽部件404可与所述初始化信号线图形同层设置”包括：所述第一屏蔽部件404与所述初始化信号线图形位于同一水平面上；所述第一屏蔽部件404与所述初始化信号线图形位于同一层膜层；所述第一屏蔽部件404与所述初始化信号线图形均设置在同一层绝缘层背向基底的表面；以及所述第一屏蔽部件404与所述初始化信号线图形采用一次构图工艺形成等多种情况中的至少一种。
上述“所述第一屏蔽部件404可与所述初始化信号线图形异层设置”包括：所述第一屏蔽部件404与所述初始化信号线图形不位于同一层膜层；所述第一屏蔽部件404与所述初始化信号线图形无法采用一次构图工艺形成等多种情况中的至少一种。
在一些实施例中，可设置所述第一屏蔽部件404与所述数据线图形(如图3中的DATA1)同材料设置。
在一些实施例中，可设置所述显示基板包括第一层间绝缘层，所述第一屏蔽部件404与所述数据线图形(如图3中的DATA1)均位于所述第一层间绝缘层背向所述基底的表面。
具体地，按照上述方式设置所述第一屏蔽部件404，使得能够通过一次构图工艺，将所述第一屏蔽部件404与所述数据线图形同时形成在所述第一层间绝缘层背向所述基底的表面，避免为了制作所述第一屏蔽部件404而增加额外的构图工艺，从而很好的简化了显示基板的制作流程，节约了制作成本。
如图3所示，在一些实施例中，所述子像素驱动电路还包括与所述驱动晶体管的栅极耦接的第二晶体管T2，所述第二晶体管T2包括：
第一半导体图形、第二半导体图形和分别与所述第一半导体图形和所述 第二半导体图形耦接的第三导体图形，所述第三导体图形的导电性能优于所述第一半导体图形的导电性能和所述第二半导体图形的导电性能；
相耦接的第一栅极图形和第二栅极图形，所述第一栅极图形在所述基底50上的正投影与所述第一半导体图形在所述基底50上的正投影部分重叠，所述第二栅极图形在所述基底50上的正投影与所述第二半导体图形在所述基底50上的正投影部分重叠；
所述第三导体图形在所述基底50上的正投影与所述第一栅极图形在所述基底50上的正投影，以及所述第二栅极图形在所述基底50上的正投影均不重叠；
所述第三导体图形在所述基底50上的正投影，与所述初始化信号线图形(如图3中的VINT1)在所述基底50上的正投影至少部分重叠。
具体地，如图7所示，上述第二晶体管T2为双栅结构，其包括的所述第一半导体图形和所述第二半导体图形形成为所述第二晶体管T2的沟道区(对应图7中的标记102pg位置)，其包括的所述第三导体图形102px由于进行了掺杂，导电性能优于所述第一半导体图形和所述第二半导体图形，所述第二晶体管T2包括的第一栅极图形和第二栅极图形一一对应覆盖所述第一半导体图形和所述第二半导体图形，可共同作为所述第二晶体管T2的栅极202g。
上述结构的第二晶体管T2中，由于所述第三导体图形102px具有良好的导电性能，且未被栅极图形覆盖，因此，容易与其附近的其他导电图形之间耦合，产生串扰现象。上述实施例提供的技术方案中，通过设置所述第三导体图形在所述基底50上的正投影，与所述初始化信号线图形(如图3中的VINT1)在所述基底50上的正投影至少部分重叠，使得所述初始化信号线图形能够对所述第三导体图形102px进行遮盖，由于所述初始化信号线图形上传输具有固定电位的初始化信号，更好的减小了所述第三导体图形102px与其附近的其他导电图形之间的耦合作用，从而使得显示基板的工作性能更稳定。
如图4所示，在一些实施例中，所述子像素驱动电路还包括由所述第一半导体图形延伸出的第一延伸部，所述第一延伸部的导电性能优于所述第一半导体图形；所述第一延伸部包括第一部分61、第二部分62和第三部分63， 所述第一部分61和所述第三部分63均沿所述第一方向延伸，所述第二部分62沿所述第二方向延伸，所述第二部分62的一端与所述第一部分61耦接，所述第二部分62的另一端与所述第三部分63耦接；所述第三部分63远离所述第二部分62的一端与所述第一晶体管T1耦接。
具体地，所述第一延伸部可与所述第一半导体图形在一次构图工艺中制作，并在形成所述第一半导体图形后，对该第一延伸部进行掺杂，使得该第一延伸部的导电性能优于所述第一半导体图形。
在增加第一屏蔽部件404之后，将所述第一延伸部设置为上述结构，使得第二晶体管T2在通过所述第一延伸部分别与第一晶体管T1和驱动晶体管的栅极耦接时，更有利于降低由于目标数据线图形上传输的信号变化对第一晶体管T1的性能，以及第二晶体管T2的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。
如图3和图4所示，在一些实施例中，所述第一晶体管T1包括：
第四半导体图形、第五半导体图形和分别与所述第四半导体图形和所述第五半导体图形耦接的第六导体图形，所述第六导体图形的导电性能优于所述第四半导体图形的导电性能和所述第五半导体图形的导电性能；
相耦接的第三栅极图形和第四栅极图形，所述第三栅极图形在所述基底50上的正投影与所述第四半导体图形在所述基底50上的正投影部分重叠，所述第四栅极图形在所述基底50上的正投影与所述第五半导体图形在所述基底50上的正投影部分重叠；
所述第六导体图形在所述基底50上的正投影与所述第三栅极图形在所述基底50上的正投影，以及所述第四栅极图形在所述基底50上的正投影均不重叠。
具体地，如图4所示，所述第一晶体管为双栅结构，其包括的所述第四半导体图形和所述第五半导体图形形成为所述第一晶体管的沟道区(对应图4中的标记101pg)，其包括的所述第六导体图形101px由于进行了掺杂，导电性能优于所述第四半导体图形和所述第五半导体图形，所述第一晶体管包括的第三栅极图形和第四栅极图形一一对应覆盖所述第四半导体图形和所述 第五半导体图形，可共同作为所述第一晶体管T1的栅极201g。
如图10所示，在一些实施例中，所述第一屏蔽部件404在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠。
具体地，上述结构的第一晶体管T1中，由于所述第六导体图形101px具有良好的导电性能，且未被栅极图形覆盖，因此，容易与其附近的其他导电图形之间耦合，产生串扰现象。上述实施例提供的技术方案中，通过设置所述第一屏蔽部件404在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠，使得所述第一屏蔽部件404能够对所述第六导体图形101px进行遮盖，且由于所述第一屏蔽部件404具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
如图11、图12和图13所示，在一些实施例中，所述子像素驱动电路还包括：与所述第一屏蔽部件404耦接的第二屏蔽部件301，所述第二屏蔽部件301在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠。
具体地，上述设置所述第二屏蔽部件301在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠，使得所述第二屏蔽部件301能够对所述第六导体图形101px进行遮盖，且由于所述第二屏蔽部件301与所述第一屏蔽部件404耦接，使所述第二屏蔽部件301具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
因此，上述实施例提供的显示基板中，由于所述第一屏蔽部件404和所述第二屏蔽部件301均具有固定电位，从而更好的防止或减少了第一晶体管T1与目标数据线图形(如DATA2)之间形成寄生电容，有效防止或减少了垂直串扰缺陷。
进一步地，可设置所述第二屏蔽部件301在所述基底50上的正投影覆盖所述第六导体图形在所述基底50上的正投影的全部。
具体地，设置所述第二屏蔽部件301在所述基底50上的正投影覆盖所述 第六导体图形101px在所述基底50上的正投影的全部，使得所述第二屏蔽部件301能够将所述第六导体图形101px完全遮盖，从而最大限度的减小所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，更好的提升显示基板的工作稳定性。
在一些实施例中，所述第二屏蔽部件301与所述第一屏蔽部件404异层设置，所述第二屏蔽部件301在所述基底50上的正投影与所述第一屏蔽部件404在所述基底50上的正投影存在第二重叠区域，所述第二屏蔽部件301与所述第一屏蔽部件404之间通过设置在所述第二重叠区域的第二过孔耦接。
具体地，所述第二屏蔽部件301可与所述第一屏蔽部件404同层设置或异层设置，当所述第二屏蔽部件301与所述第一屏蔽部件404异层设置时，可设置所述第二屏蔽部件301在所述基底50上的正投影与所述第一屏蔽部件404在所述基底50上的正投影存在第二重叠区域，这样通过在所述第二重叠区域设置第二过孔，使得所述第二屏蔽部件301与所述第一屏蔽部件404之间能够通过所述第二过孔实现耦接。
在一些实施例中，可设置所述第二屏蔽部件301与所述初始化信号线图形同材料设置。
在一些实施例中，可设置所述显示基板还包括第二层间绝缘层，所述第二屏蔽部件301与所述初始化信号线图形(如图3中的VINT1)均位于所述第二层间绝缘层背向所述基底的表面。
具体地，上述将所述第二屏蔽部件301与所述初始化信号线图形同材料设置，并将所述第二屏蔽部件301与所述初始化信号线图形(如图3中的VINT1)均位于所述第二层间绝缘层背向所述基底的表面，使得所述第二屏蔽部件301能够与所述初始化信号线图形在同一次构图工艺中同时形成，避免了增加额外的专门用于制作所述第二屏蔽部件301的制作工艺，从而很好的简化了显示基板的制作流程，节约了生产成本。
如图3所示，在一些实施例中，所述子像素还包括电源信号线图形VDD，所述电源信号线图形VDD包括沿所述第一方向延伸的部分，所述子像素驱动电路还包括存储电容Cst，所述存储电容Cst中的第一极板Cst1复用为所述驱动晶体管的栅极，所述存储电容Cst中的第二极板Cst2与所述电源信号线 图形VDD耦接，所述存储电容Cst中的第二极板Cst2位于所述第二层间绝缘层背向所述基底的表面。
具体地，所述子像素驱动电路中包括的存储电容Cst具有第一极板Cst1和第二极板Cst2，所述第一极板Cst1和所述第二极板Cst2相对设置，且所述第一极板Cst1与所述驱动晶体管的栅极耦接，所述第二极板Cst2与所述电源信号线图形VDD耦接。在布局该存储电容Cst时，可将所述第一极板Cst1直接复用为所述驱动晶体管的栅极，这样不仅保证了存储电容Cst与驱动晶体管的栅极实现耦接，还缩小了子像素驱动电路占用的空间，更有利于提升显示基板的分辨率。另外，设置所述存储电容Cst中的第二极板Cst2位于所述第二层间绝缘层背向所述基底的表面，使得所述存储电容Cst中的第二极板Cst2能够与所述第二屏蔽部件301和所述初始化信号线图形在同一次构图工艺中同时形成，从而很好的简化了显示基板的制作流程，节约了生产成本。
如图14所示，在一些实施例中，所述子像素还包括：沿与所述第一方向相交的第二方向延伸的复位信号线图形(如图3中的RST1)，所述子像素驱动电路还包括：
第一导电连接部405，所述第一导电连接部405在所述基底50上的正投影覆盖至少部分所述第六导体图形101px在所述基底50上的正投影；
第二晶体管T2，所述第二晶体管T2的第一极(如源极S2)通过所述第一导电连接部405与所述初始化信号线图形(如VINT1)耦接，所述第二晶体管T2的第二极(如漏极D2)与所述驱动晶体管的栅极耦接，所述第二晶体管T2的栅极202g与所述复位信号线图形(如RST1)耦接。
具体地，所述第一导电连接部405可采用金属材料制作，并可与数据线图形在同一次构图工艺中形成。
上述设置所述第一导电连接部405在所述基底50上的正投影覆盖至少部分所述第六导体图形101px在所述基底50上的正投影，使得所述第一导电连接部405能够对所述第六导体图形101px进行遮盖，且由于所述第一导电连接部405与所述初始化信号线图形耦接，使所述第一导电连接部405具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
如图3所示，在一些实施例中，所述子像素还包括：栅线图形GATE、发光控制信号线图形EM、复位信号线图形(如图3中的RST1)和电源信号线图形VDD；所述栅线图形GATE、所述发光控制信号线图形EM和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形VDD包括沿所述第一方向延伸的部分；
所述子像素驱动电路还包括：第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7；
所述驱动晶体管的栅极(如第三晶体管T3的栅极203g)与所述第一晶体管T1的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管T5的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管T1的第一极耦接；
所述第一晶体管T1的栅极201g与所述栅线图形GATE耦接；
所述第二晶体管T2的栅极202g与所述复位信号线图形耦接，所述第二晶体管T2的第一极与所述初始化信号线图形耦接，所述第二晶体管T2的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管T4的栅极204g与所述栅线图形GATE耦接，所述第四晶体管T4的第一极与所述数据线图形(如图3中的DATA1)耦接，所述第四晶体管T4的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管T5的栅极205g与所述发光控制信号线图形EM耦接，所述第五晶体管T5的第一极与所述电源信号线图形VDD耦接；
所述第六晶体管T6的栅极206g与所述发光控制信号线图形EM耦接，所述第六晶体管T6的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管T6的第二极与所述子像素中的发光元件耦接；
所述第七晶体管T7的栅极207g与沿所述第一方向相邻的下一个子像素包括的复位信号线图形(如RST2)耦接，所述第七晶体管T7的第一极与该下一个子像素包括的初始化信号线图形(如VINT2)耦接，所述第七晶体管T7的第二极与所述子像素中的发光元件耦接。
具体地，上述显示基板中，包括的多个子像素可呈阵列分布，所述多个子像素可划分为多行子像素和多列子像素，每行子像素均包括沿第二方向排列的多个子像素，每列子像素均包括沿第一方向排列的多个子像素，所述第 一方向与所述第二方向相交。
需要说明，上述沿所述第一方向相邻的下一个子像素，即与该第七晶体管T7位于同一列的相邻的下一个子像素。
将所述子像素和其包括的子像素驱动电路设置为上述结构，能够在保证子像素驱动电路的工作性能的情况下，有效减小所述子像素驱动电路占用的布局空间，有利于提升显示基板的分辨率。
需要说明，所述子像素驱动电路中包括的各晶体管的栅极，与其耦接的功能图形可形成为一体结构，示例性的，第一晶体管的栅极和第四晶体管的栅极均与对应耦接的栅线图形为一体结构，第五晶体管的栅极和第六晶体管的栅极均与对应耦接的发光控制信号线图形为一体结构，第二晶体管的栅极和第七晶体管的栅极与对应耦接的复位信号线图形为一体结构。
另外，所述第一晶体管T1用于对所述驱动晶体管(如第三晶体管T3)进行阈值补偿，所述第二晶体管T2用于对所述驱动晶体管的栅极进行复位，所述第四晶体管T4用于写入所述数据线图形传输的数据信号，所述第五晶体管T5用于向所述驱动晶体管的第一极写入电源信号线图形传输的电源信号，所述第六晶体管T6用于控制对应的发光元件是否发光，所述第七晶体管T7用于对所述发光元件的阳极进行复位。
在一些实施例中，所述子像素还包括：栅线图形GATE、发光控制信号线图形EM、复位信号线图形RST和电源信号线图形VDD；所述栅线图形GATE、所述发光控制信号线图形EM和所述复位信号线图形RST均沿所述第二方向延伸，所述电源信号线图形VDD包括沿所述第一方向延伸的部分；所述第一屏蔽部件404在所述基底50上的正投影，分别与所述栅线图形GATE在所述基底50上的正投影，以及所述发光控制信号线图形EM在所述基底50上的正投影部分交叠。
具体地，将所述第一屏蔽部件404按照上述方式布局，使得所述第一屏蔽部件404能够将所述第一晶体管T1、所述驱动晶体管均与所述目标数据线图形(如DATA2)隔离，从而更有利于减小所述目标数据线图形上数据信号变化，对所述第一晶体管T1和所述驱动晶体管引起的串扰。
在一些实施例中，所述第七晶体管T7的第二极与所述子像素中的发光元 件耦接的方式多种多样，示例性的，所述发光元件的阳极在所述基底上的正头影，与所述第七晶体管T7的第二极在所述基底上的正投影交叠，所述发光元件的阳极能够通过设置在该交叠处的过孔与所述第七晶体管T7的第二极耦接；或者，所述发光元件的阳极在所述基底上的正头影，与所述第七晶体管T7的第二极在所述基底上的正投影不交叠，所述子像素驱动电路还包括第二导电连接部406和第三导电连接部407，所述发光元件的阳极在所述基底上的正投影与所述第三导电连接部407的第一端在所述基底上的正投影交叠，所述发光元件的阳极通过在该交叠处的过孔与所述第三导电连接部407的第一端耦接，第三导电连接部407的第二端与第二导电连接部406的第一端交叠，第三导电连接部407的第二端与第二导电连接部406的第一端通过在该交叠处的过孔实现耦接，所述第七晶体管T7的第二极在所述基底上的正投影与所述第二导电连接部406的第二端在所述基底上的正投影交叠，所述第七晶体管T7的第二极通过在该交叠处的过孔与所述第二导电连接部406的第二端耦接，从而实现所述发光元件的阳极能够通过所述第二导电连接部406和第三导电连接部407与所述第七晶体管T7的第二极耦接。
当设置所述发光元件的阳极通过所述第二导电连接部406和第三导电连接部407与所述第七晶体管T7的第二极耦接时，所述第二导电连接部406可包括沿所述第一方向延伸的部分，所述发光元件的阳极可位于其对应的子像素中的发光控制信号线图形的上侧，所述第七晶体管T7的第二极可位于其对应的子像素中的发光控制信号线图形的下侧。
如图15所示，以图中示出的三种颜色的子像素为例，对该三种颜色的子像素的结构进行说明。
第一颜色子像素中的发光元件包括沿远离基底的方向依次层叠设置的第一阳极601、第一有机发光材料层和第一阴极；第一阳极601在所述基底上的正投影与对应的所述第七晶体管T7的第二极在所述基底上的正投影部分交叠，所述第一阳极601通过在该交叠处的过孔与对应的所述第七晶体管T7的第二极耦接。
第二颜色子像素中的发光元件包括沿远离基底的方向依次层叠设置的第二阳极602、第二有机发光材料层和第二阴极；第二阳极602在所述基底上 的正头影，与对应的所述第七晶体管T7的第二极在所述基底上的正投影不交叠，所述第二颜色子像素中的子像素驱动电路还包括第二导电连接部406和第三导电连接部407，所述第二阳极602通过第二导电连接部406和第三导电连接部407与对应的所述第七晶体管T7的第二极耦接。
第三颜色子像素中的发光元件包括沿远离基底的方向依次层叠设置的第三阳极603、第三有机发光材料层和第三阴极；第三阳极603在所述基底上的正投影与对应的所述第七晶体管T7的第二极在所述基底上的正投影部分交叠，所述第三阳极603通过在该交叠处的过孔与对应的所述第七晶体管T7的第二极耦接。
例如，如图15所示，各颜色子像素的有机发光元件的阳极均包括主体电极和连接电极，且主体电极的形状均为六边形。
如图15所示，第一颜色子像素的第一阳极601包括第一主体电极6011和第一连接电极6012，第一主体电极6011和第一连接电极6012可以为一体结构，且第一连接电极6012通过连接孔实现与第一颜色子像素的第七晶体管T7的第二极相连。第二颜色子像素的第二阳极602包括第二主体电极6021和第二连接电极6022，第二主体电极6021和第二连接电极6022可以为一体结构，且第二连接电极6022通过第二导电连接部406和第三导电连接部407与第二颜色子像素的第七晶体管T7的第二极相连。第三颜色子像素的第三阳极603包括第三主体电极6031和第三连接电极6032，第三主体电极6031和第三连接电极6032可以为一体结构，且第三连接电极6032通过连接孔与第三颜色子像素的第七晶体管T7的第二极相连。
例如第一颜色子像素的第一连接电极6012，在X方向上位于第一主体电极6011中心远离该子像素像素电路的数据线图形的一侧，且在Y方向上位于第一主体电极6011中心远离该子像素像素电路的发光控制信号线的一侧。例如第一颜色子像素的第一连接电极6012和第一主体电极6011在Y方向排布，第一连接电极6012位于第一主体电极6011的右下角。例如，第二颜色子像素的第二连接电极6022，在X方向上位于第二主体电极6021中心远离该子像素像素电路数据线的一侧，且在Y方向上位于第二主体电极6021中心靠近该子像素像素电路发光控制信号线的一侧。例如，第二颜色子像素的第二 连接电极6022和第二主体电极6021在Y方向排布，第二连接电极6022位于第一主体电极1231的右下角。例如，第三颜色子像素的第三连接电极6032与第三主体电极6031在X方向排布，第三连接电极6032位于第三主体电极6031的右侧，即靠近该子像素像素电路靠近屏蔽线的一侧。
如图15所示，第一颜色子像素的第一阳极601的第一主体电极6011覆盖第一颜色子像素的驱动晶体管，第二颜色子像素的第二阳极602的第二主体电极6021与第二颜色子像素的驱动晶体管基本没有交叠或者有部分交叠，第三颜色子像的第三阳极603的第三主体电极6031与第三颜色子像素的驱动晶体管没有交叠。
如图15所示，第一颜色子像素601(例如蓝色子像素)的第一主体电极6011与栅线图形和发光控制信号线图形有交叠；第二颜色子像素(例如红色子像素)的第二主体电极6021与栅线图形和复位信号线图形有交叠；第三颜色子像素(例如绿色子像素)的第三主体电极6031与发光控制信号线图形、下一行子像素驱动电路的复位信号线图形以及下一行子像素驱动电路的初始化信号线图形有交叠。例如第三颜色子像素(例如绿色子像素)的第三主体电极6031与下一行与其相邻的第一颜色子像素(例如蓝色子像素)的像素驱动电路区域有交叠。
例如，第一颜色子像素601的第一主体电极6011与相邻的第三颜色子像素的驱动晶体管的部分交叠，且第一颜色子像素601的第一主体电极6011与其子像素驱动电路中的数据线图形、第一屏蔽部件404以及相邻第二颜色子像素的子像素驱动电路中的数据线图形均有交叠。第二颜色子像素的第二主体电极6021与其子像素驱动电路中的数据线图形没有交叠，且与其子像素驱动电路中的电源信号线图形和相邻的第三颜色子像素的子像素驱动电路中的电源信号线图形以及数据线图形均有交叠。第三颜色子像素的第三主体电极6031与其子像素驱动电路中的数据线图形和电源信号线图形均有交叠，且与相邻第二颜色子像素的子像素驱动电路中的电源信号线图形有交叠。
例如，如图15所示，第一颜色子像素601的第一主体电极6011靠近下一行复位信号线图形的一侧设置有与其连接的第一连接电极6012；第二颜色子像素的第二主体电极6021靠近下一行复位信号线图形的一侧设置有与其 连接的第二连接电极6022；第三颜色子像素的第三主体电极6031靠近其第七晶体管T7的一侧设置有与其连接的第三连接电极6032。
例如，如图15所示，第一颜色子像素601的第一连接电极6012与其子像素驱动电路中的第七晶体管T7的第二极有交叠。第二颜色子像素的第二连接电极6022与其子像素驱动电路中的第七晶体管T7的第二极没有交叠，而第二颜色子像素的第七晶体管T7的第二极与第三颜色子像素的第三主体电极6031有交叠。第三颜色子像素的第三连接电极6032与其子像素驱动电路中的第七晶体管T7的第二极有交叠。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
由于上述实施例提供的显示基板中，通过设置第一屏蔽部件404能够减小由于目标数据线图形上传输的信号变化对第一晶体管T1的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。另外，上述实施例提供的显示基板中，将所述第一屏蔽部件404与所述初始化信号线图形耦接，除了使得第一屏蔽部件404具有固定电位之外，还实现了加强了初始化信号线图形的电压，使得初始化信号线图形上传输的初始化信号的电压更稳定，从而更有利于子像素驱动电路的工作性能。
因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，用于制作上述实施例提供的显示基板，所述制作方法包括：
在基底50上制作阵列分布的多个子像素；所述子像素包括：
沿第一方向延伸的数据线图形(如图3中的DATA1)；
初始化信号线图形(如图3中的VINT1)，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
子像素驱动电路，所述子像素驱动电路包括：驱动晶体管(如图3中的 T3)，与所述驱动晶体管的栅极耦接的第一晶体管T1，以及与所述初始化信号线图形耦接的第一屏蔽部件404，所述第一屏蔽部件404在所述基底50上的正投影，位于所述第一晶体管T1在所述基底50上的正投影与目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间；沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
采用本公开实施例提供的制作方法制作上述显示基板时，在所述子像素驱动电路中设置了与所述初始化信号线图形(如图3中的VINT1)耦接的第一屏蔽部件404，使第一屏蔽部件404具有与所述初始化信号相同的固定电位，并设置所述第一屏蔽部件404在所述基底50上的正投影，位于所述第一晶体管T1在所述基底50上的正投影与目标数据线图形(如图3中的DATA2)在所述基底50上的正投影之间，使得第一屏蔽部件404能够减小由于目标数据线图形上传输的信号变化对第一晶体管T1的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。
另外，采用本公开实施例提供的制作方法制作上述显示基板时，将所述第一屏蔽部件404与所述初始化信号线图形耦接，除了使得第一屏蔽部件404具有固定电位之外，还实现了加强了初始化信号线图形的电压，使得初始化信号线图形上传输的初始化信号的电压更稳定，从而更有利于子像素驱动电路的工作性能。
如图16所示，本公开实施例还提供了一种显示基板，包括：基底50和在所述基底50上阵列分布的多个子像素；所述子像素包括：
沿第一方向延伸的数据线图形(如DATA1)；
电源信号线图形VDD，所述电源信号线图形VDD包括沿所述第一方向延伸的部分；
子像素驱动电路，所述子像素驱动电路包括：两个开关晶体管(如第四晶体管T4和第五晶体管T5)、驱动晶体管(如第三晶体管T3)和存储电容Cst；所述存储电容Cst的第一极板Cst1与所述驱动晶体管的栅极(如第三晶体管T3的栅极203g)耦接，所述存储电容Cst的第二极板Cst2与所述电源信号线图形VDD耦接；所述两个开关晶体管的第二极(如第四晶体管T4的 漏极D4和第五晶体管T5的漏极D5)均与所述驱动晶体管的第一极(如第三晶体管T3的源极S3)耦接，所述两个开关晶体管中的至少一个开关晶体管的第二极在所述基底50上的正投影，与所述电源信号线图形VDD在所述基底50上的正投影至少部分重叠，且与所述存储电容Cst的第二极板Cst2在所述基底50上的正投影至少部分重叠。
具体地，上述显示基板一般包括阵列分布的多个子像素，每个子像素均包括：沿第一方向延伸的数据线图形(如DATA1)，以及至少部分沿第一方向延伸的电源信号线图形VDD；示例性的，所述第一方向包括Y方向，所述第二方向包括X方向。
值得注意，所述电源信号线图形VDD的具体结构多种多样，示例性的，所述电源信号线图形VDD为网格状结构，网格状结构的电源信号线图形VDD中包括沿所述第一方向延伸的部分。
每个子像素还包括子像素驱动电路，以及与所述子像素驱动电路一一对应的发光元件，发光元件包括层叠设置的阳极、有机发光材料层和阴极，其中发光元件的阳极与对应的子像素驱动电路耦接，在子像素驱动电路提供的驱动信号的驱动下，发光元件实现发光。
更详细地说，如图16所示，以子像素驱动电路包括上述7T1C为例，第三晶体管T3(即所述驱动晶体管)的栅极203g复用为所述存储电容Cst的第一极板Cst1，所述存储电容Cst的第二极板Cst2位于所述第一极板Cst1背向所述基底的一侧，所述第一极板Cst1在所述基底上的正投影，与所述第二极板Cst2在所述基底上的正投影至少部分重叠，且所述第二极板Cst2在所述基底上的正投影，与所述第四晶体管T4和第五晶体管T5中的至少一个开关晶体管的第二极在所述基底50上的正投影，以及与所述电源信号线图形VDD在所述基底50上的正投影均至少部分重叠。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，设置所述存储电容Cst的第二极板Cst2与所述电源信号线图形VDD耦接，使得存储电容Cst的第二极板Cst2具有与所述电源信号线图形VDD上传输的电源信号相同的固定电位；同时设置所述两个开关晶体管的第二极均与所述驱动晶体管的第一极耦接，所述两个开关晶体管中的至少一个开关晶体管 的第二极在所述基底50上的正投影，与所述电源信号线图形VDD在所述基底50上的正投影至少部分重叠，且与所述存储电容Cst的第二极板Cst2在所述基底50上的正投影至少部分重叠，使得存储电容Cst的第二极板Cst2和所述电源信号线图形VDD均能够对所述两个开关晶体管中的至少一个开关晶体管的第二极进行遮挡，从而减小了位于所述两个开关晶体管中的至少一个开关晶体管周边的其它导电图形(如信号线图形)上的信号，对所述两个开关晶体管中的至少一个开关晶体管的第二极产生的串扰现象，进而减小了对所述驱动晶体管的第一极产生的串扰现象。
如图16所示，在一些实施例中，所述两个开关晶体管(如第四晶体管T4和第五晶体管T5)的第二极与所述驱动晶体管(如第三晶体管T3)的第一极为一体结构，该一体结构包括沿所述第一方向延伸的第一导电部108，该第一导电部108在所述基底上的正投影，与所述电源信号线图形VDD在所述基底上的正投影，以及所述存储电容Cst的第二极板Cst2在所述基底50上的正投影存在第一交叠区域，所述第一交叠区域与所述数据线图形(如DATA1)在所述基底50上的正投影不交叠。
具体地，将所述两个开关晶体管的第二极与所述驱动晶体管的第一极形成为一体结构，使得所述两个开关晶体管的第二极与所述驱动晶体管的第一极能够通过一次构图工艺形成。
上述实施例提供的显示基板中，设置所述一体结构包括沿所述第一方向延伸的第一导电部108，所述数据线图形在所述基底上的正投影位于所述第一导电部108在所述基底上的正投影远离与所述驱动晶体管在所述基底上的正投影的一侧，以及所述第一导电部108在所述基底上的正投影，与所述电源信号线图形VDD在所述基底上的正投影，以及所述存储电容Cst的第二极板Cst2在所述基底50上的正投影存在第一交叠区域，使得存储电容Cst的第二极板Cst2和所述电源信号线图形VDD均能够对所述第一导电部108进行遮挡，减小了所述数据线图形上传输的信号，对第一导电部108产生串扰，进而减小了对所述驱动晶体管的第一极产生的串扰现象。
如图16所示，在一些实施例中，可设置所述驱动晶体管的第一极在所述基底50上的正投影，位于所述存储电容Cst的第二极板Cst2在所述基底上的 正投影的内部。
上述设置方式使得所述存储电容Cst的第二极板Cst2能够将所述驱动晶体管的第一极完全覆盖，从而更有效的减小了所述数据线图形上传输的信号，对所述驱动晶体管的第一极产生的串扰现象。
如图16和图17所示，在一些实施例中，所述子像素还包括：均沿第二方向延伸的栅线图形GATE和发光控制信号线图形EM，所述第二方向与所述第一方向相交；
所述子像素驱动电路还包括：第一晶体管T1和第六晶体管T6；所述两个开关晶体管包括第四晶体管T4和第五晶体管T5；
所述第四晶体管T4的栅极204g与所述栅线图形GATE耦接，所述第四晶体管T4的第一极与所述数据线图形(如DATA1)耦接，所述第四晶体管T4的第二极与所述第五晶体管T5的第二极耦接，所述第五晶体管T5的栅极205g与所述发光控制信号线图形EM耦接，所述第五晶体管T5的第一极与所述电源信号线图形VDD耦接；
所述第一晶体管T1的栅极201g与所述栅线图形GATE耦接，所述第一晶体管T1的第二极与所述驱动晶体管的栅极耦接，所述第一晶体管T1的第一极、所述第六晶体管T6的第一极与所述驱动晶体管的第二极形成为一体结构，该一体结构包括沿所述第一方向延伸的第二导电部109，所述第六晶体管T6的栅极206g与所述发光控制信号线图形EM耦接，所述第六晶体管T6的第二极与所述子像素中的发光元件耦接；
所述驱动晶体管的沟道区(如图18中的103pg)在所述基底上的正投影，位于所述第一导电部108在所述基底50上的正投影与所述第二导电部109在所述基底50上的正投影之间；且沿所述第二方向，所述驱动晶体管的沟道区在所述基底上的正投影，与所述第一导电部108在所述基底上的正投影之间的最小距离，小于所述沟道区在所述基底50上的正投影，与所述第二导电部109在所述基底上的正投影之间的最小距离。
具体地，上述显示基板中，包括的多个子像素可呈阵列分布，所述多个子像素可划分为多行子像素和多列子像素，每行子像素均包括沿第二方向排列的多个子像素，每列子像素均包括沿第一方向排列的多个子像素，所述第 一方向与所述第二方向相交。每列子像素中包括的子像素驱动电路均位于该列子像素包括的数据线图形，与该列子像素相邻的下一列子像素包括的数据线图形之间。
需要说明，上述沿所述第二方向，所述驱动晶体管的沟道区在所述基底上的正投影，与所述第一导电部108在所述基底上的正投影之间的最小距离是指：沿所述第二方向，所述驱动晶体管的沟道区在所述基底上的正投影中，最靠近所述第一导电部108在所述基底上的正投影的边界，与所述第一导电部108在所述基底上的正投影之间的距离；上述沿所述第二方向，所述沟道区在所述基底50上的正投影，与所述第二导电部109在所述基底上的正投影之间的最小距离是指：沿所述第二方向，所述驱动晶体管的沟道区在所述基底上的正投影中，最靠近所述第二导电部109在所述基底上的正投影的边界，与所述第二导电部109在所述基底上的正投影之间的距离。
更详细地说，每个子像素包括的子像素驱动电路均位于相邻的两个数据线图形(如：DATA1和DATA2)之间，由于该两个数据线图形上传输的数据均会发生变化，且当该数据发生变化时，容易对所述子像素驱动电路中的驱动晶体管的栅极产生串扰，具体如图25所示，进而影响所述驱动晶体管的工作稳定性。
上述实施例提供的技术方案中，将所述第四晶体管T4、所述第五晶体管T5、所述第一晶体管T1和所述第六晶体管T6均设置在所述驱动晶体管的周边区域，并设置所述两个数据线图形中的一个(如DATA1)位于所述第四晶体管T4、所述第五晶体管T5远离所述驱动晶体管的一侧，设置所述两个数据线图形中的另一个(如DATA2)位于所述第一晶体管T1和所述第六晶体管T6远离所述驱动晶体管的一侧；同时通过设置所述驱动晶体管的沟道区(如图18中的103pg)在所述基底上的正投影，位于所述第一导电部108在所述基底50上的正投影与所述第二导电部109在所述基底50上的正投影之间，且所述驱动晶体管的沟道区在所述基底上的正投影，与所述第一导电部108在所述基底上的正投影之间的最小距离，小于所述沟道区在所述基底上的正投影，与所述第二导电部109在所述基底上的正投影之间的最小距离；能够使得所述驱动晶体管的沟道区在保证与DATA1满足合适距离的情况下， 最大限度的增加了所述驱动晶体管的沟道区域与DATA2之间的距离，从而更好的减小了所述DATA2对所述驱动晶体管产生的串扰。
而且，由于所述驱动晶体管的沟道区靠近DATA1的部分，能够被所述电源信号线图形VDD覆盖，因此，能够有效减小DATA1对所述驱动晶体管的沟道区产生的串扰，因此，上述实施例提供的技术方案中，即使所述驱动晶体管的沟道区与DATA相距较近，受到的串扰影响也较小。
另外，由于存储电容Cst的第二极板Cst2具有与所述电源信号线图形VDD上传输的电源信号相同的固定电位，且所述第一导电部108在所述基底上的正投影，与所述电源信号线图形VDD在所述基底上的正投影，以及所述存储电容Cst的第二极板Cst2在所述基底50上的正投影存在第一交叠区域，使得存储电容Cst的第二极板Cst2和所述电源信号线图形VDD均能够对所述第一导电部108进行遮挡，减小了DATA1上传输的信号，对第一导电部108产生串扰，进而减小了对所述驱动晶体管的第一极和沟道区产生的串扰现象。
如图16所示，在一些实施例中，所述子像素还包括：均沿第二方向延伸的栅线图形GATE和发光控制信号线图形EM，所述第二方向与所述第一方向相交；
所述子像素驱动电路还包括：第一晶体管T1和第六晶体管T6；所述两个开关晶体管包括第四晶体管T4和第五晶体管T5；
所述第四晶体管T4的栅极204g与所述栅线图形GATE耦接，所述第四晶体管T4的第一极与所述数据线图形(如DATA1)耦接，所述第四晶体管T4的第二极与所述第五晶体管T5的第二极耦接，所述第五晶体管T5的栅极205g与所述发光控制信号线图形EM耦接，所述第五晶体管T5的第一极与所述电源信号线图形VDD耦接；
所述第一晶体管T1的栅极201g与所述栅线图形GATE耦接，所述第一晶体管T1的第二极与所述驱动晶体管的栅极耦接，所述第一晶体管T1的第一极、所述第六晶体管T6的第一极与所述驱动晶体管的第二极形成为一体结构，该一体结构包括沿所述第一方向延伸的第二导电部109，所述第六晶体管T6的栅极206g与所述发光控制信号线图形EM耦接，所述第六晶体管T6 的第二极与所述子像素中的发光元件耦接；
所述驱动晶体管的沟道区(如图18中的103pg)在所述基底上的正投影，位于所述第一导电部108在所述基底上的正投影与所述第二导电部109在所述基底上的正投影之间；所述驱动晶体管的第一极和第二极均包括沿所述第二方向延伸的第一部分，所述第一极的第一部分沿所述第二方向的长度与所述第二极的第一部分沿所述第二方向延伸的长度不同。
具体地，上述设置所述驱动晶体管的第一极和第二极均包括沿所述第二方向延伸的第一部分，所述第一极的第一部分沿所述第二方向的长度与所述第二极的第一部分沿所述第二方向延伸的长度不同，具体包括：如下两种情况：
第一种情况，所述第一极的第一部分沿所述第二方向的长度H1小于所述第二极的第一部分沿所述第二方向延伸的长度H2，这样所述驱动晶体管的沟道区(如图18中的103pg)靠近其所在的子像素包括的数据线图形(如DATA1)，且远离沿第二方向其所在的子像素相邻的下一个子像素包括的数据线图形(如DATA2)，能够使得所述驱动晶体管的沟道区在保证与DATA1满足合适距离的情况下，最大限度的增加了所述驱动晶体管的沟道区域与DATA2之间的距离，从而更好的减小了所述DATA2对所述驱动晶体管产生的串扰。同时由于存储电容Cst的第二极板Cst2和所述电源信号线图形VDD均能够对所述第一导电部108进行遮挡，减小了DATA1上传输的信号，对第一导电部108产生串扰，进而减小了对所述驱动晶体管的第一极和沟道区产生的串扰现象。
第二种情况，所述第一极的第一部分沿所述第二方向的长度大于所述第二极的第一部分沿所述第二方向延伸的长度，这样所述驱动晶体管的沟道区(如图18中的103pg)远离其所在的子像素包括的数据线图形(如DATA1)，且靠近沿第二方向其所在的子像素相邻的下一个子像素包括的数据线图形(如DATA2)，能够使得所述驱动晶体管的沟道区在保证与DATA2满足合适距离的情况下，最大限度的增加了所述驱动晶体管的沟道区域与DATA1之间的距离，从而更好的减小了所述DATA1对所述驱动晶体管产生的串扰。而且，当所述显示基板中包括第一屏蔽部件，且该第一屏蔽部件能够将DATA2与第 二导电部109完全阻隔时，能够减小DATA2上传输的信号，对第二导电部109产生串扰，进而减小了对所述驱动晶体管的第二极和沟道区产生的串扰现象。
如图16所示，在一些实施例中，所述子像素还包括初始化信号线图形(如VINT1)，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
所述子像素驱动电路还包括与所述驱动晶体管的栅极耦接的第二晶体管T2，所述第二晶体管T2包括：
第一半导体图形、第二半导体图形和分别与所述第一半导体图形和所述第二半导体图形耦接的第三导体图形，所述第三导体图形的导电性能优于所述第一半导体图形的导电性能和所述第二半导体图形的导电性能；
相耦接的第一栅极图形和第二栅极图形，所述第一栅极图形在所述基底上的正投影与所述第一半导体图形在所述基底上的正投影至少部分重叠，所述第二栅极图形在所述基底上的正投影与所述第二半导体图形在所述基底上的正投影至少部分重叠；
所述第三导体图形在所述基底上的正投影与所述第一栅极图形在所述基底上的正投影，以及所述第二栅极图形在所述基底上的正投影均不重叠；
所述第三导体图形在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影至少部分重叠。
具体地，如图16所示，上述第二晶体管T2为双栅结构，其包括的所述第一半导体图形和所述第二半导体图形形成为所述第二晶体管T2的沟道区(对应图18中的标记102pg位置)，其包括的所述第三导体图形102px由于进行了掺杂，导电性能优于所述第一半导体图形和所述第二半导体图形，所述第二晶体管T2包括的第一栅极图形和第二栅极图形一一对应覆盖所述第一半导体图形和所述第二半导体图形，可共同作为所述第二晶体管T2的栅极202g。
上述结构的第二晶体管T2中，由于所述第三导体图形102px具有良好的导电性能，且未被栅极图形覆盖，因此，容易与其附近的其他导电图形之间 耦合，产生串扰现象。上述实施例提供的技术方案中，通过设置所述第三导体图形在所述基底50上的正投影，与所述初始化信号线图形在所述基底50上的正投影至少部分重叠，使得所述初始化信号线图形能够对所述第三导体图形102px进行遮盖，由于所述初始化信号线图形上传输具有固定电位的初始化信号，更好的减小了所述第三导体图形102px与其附近的其他导电图形之间的耦合作用，从而使得显示基板的工作性能更稳定。
如图16和图18所示，在一些实施例中，所述子像素驱动电路还包括由所述第一半导体图形延伸出的第一延伸部，所述第一延伸部的导电性能优于所述第一半导体图形；所述第一延伸部包括第一部分61、第二部分62和第三部分63，所述第一部分61和所述第三部分63均沿所述第一方向延伸，所述第二部分62沿所述第二方向延伸，所述第二部分62的一端与所述第一部分61耦接，所述第二部分62的另一端与所述第三部分63耦接；所述第三部分63远离所述第二部分62的一端与所述第一晶体管T1耦接。
具体地，所述第一延伸部可与所述第一半导体图形在一次构图工艺中制作，并在形成所述第一半导体图形后，对该第一延伸部进行掺杂，使得该第一延伸部的导电性能优于所述第一半导体图形。
在增加第一屏蔽部件404之后，将所述第一延伸部设置为上述结构，使得第二晶体管T2在通过所述第一延伸部分别与第一晶体管T1和驱动晶体管的栅极耦接时，更有利于降低由于目标数据线图形上传输的信号变化对第一晶体管T1的性能，以及第二晶体管T2的性能产生的影响，进而减小驱动晶体管的栅极(即203g)和目标数据线图形之间的耦合的影响，减弱垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。
在一些实施例中，所述第一晶体管包括：
第四半导体图形、第五半导体图形和分别与所述第四半导体图形和所述第五半导体图形耦接的第六导体图形，所述第六导体图形的导电性能优于所述第四半导体图形的导电性能和所述第五半导体图形的导电性能；
相耦接的第三栅极图形和第四栅极图形，所述第三栅极图形在所述基底上的正投影与所述第四半导体图形在所述基底上的正投影部分重叠，所述第四栅极图形在所述基底上的正投影与所述第五半导体图形在所述基底上的正 投影部分重叠；
所述第六导体图形在所述基底上的正投影与所述第三栅极图形在所述基底上的正投影，以及所述第四栅极图形在所述基底上的正投影均不重叠。
具体地，如图16所示，所述第一晶体管为双栅结构，其包括的所述第四半导体图形和所述第五半导体图形形成为所述第一晶体管的沟道区(对应图18中的标记101pg)，其包括的所述第六导体图形101px由于进行了掺杂，导电性能优于所述第四半导体图形和所述第五半导体图形，所述第一晶体管包括的第三栅极图形和第四栅极图形一一对应覆盖所述第四半导体图形和所述第五半导体图形，可共同作为所述第一晶体管T1的栅极201g。
如图19所示，在一些实施例中，所述子像素还包括初始化信号线图形(如VINT1)，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
所述子像素驱动电路还包括：与所述初始化信号线图形耦接的第一屏蔽部件404，所述第一屏蔽部件404在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠。
上述实施例提供的技术方案中，通过设置所述第一屏蔽部件404在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠，使得所述第一屏蔽部件404能够对所述第六导体图形101px进行遮盖，且由于所述第一屏蔽部件404具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
如图20所示，在一些实施例中，所述子像素还包括初始化信号线图形(如VINT1)，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
所述子像素驱动电路还包括：与所述初始化信号线图形耦接的第一屏蔽部件404，以及与所述第一屏蔽部件404耦接的第二屏蔽部件301，所述第二屏蔽部件301在所述基底上的正投影，与所述第六导体图形在所述基底上的 正投影至少部分重叠。
具体地，上述设置所述第二屏蔽部件301在所述基底50上的正投影，与所述第六导体图形101px在所述基底50上的正投影至少部分重叠，使得所述第二屏蔽部件301能够对所述第六导体图形101px进行遮盖，且由于所述第二屏蔽部件301与所述第一屏蔽部件404耦接，使所述第二屏蔽部件301具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
因此，上述实施例提供的显示基板中，由于所述第一屏蔽部件404和所述第二屏蔽部件301均具有固定电位，从而更好的防止或减少了第一晶体管T1与目标数据线图形(如DATA2)之间形成寄生电容，有效防止或减少了垂直串扰缺陷。
如图21和图22所示，在一些实施例中，所述多个子像素包括多行子像素，每行子像素均包括沿所述第二方向排列的多个所述子像素，位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的初始化信号线；所述第一屏蔽部件404沿所述第一方向延伸，所述第一屏蔽部件404与其相邻的两条所述初始化信号线耦接。
在一些实施例中，电源信号线图形的形状可根据实际需要布局，示例性的，沿所述第二方向，所述电源信号线图形在靠近所述驱动晶体管的沟道区的附近的宽度，要小于其远离所述驱动晶体管的沟道区的附近的宽度，使得在所述驱动晶体管的沟道区的附近，能够降低所述电源信号线图形对所述驱动晶体管的栅极的影响。
在一些实施例中，如图23所示，可在所述显示基板中设置补偿图形408，并将该补偿图形408与所述电源信号线图形并联，以提升所述电源信号线图形的传输性能。值得注意，所述补偿图形408可与所述第三导电连接部407同层同材料设置，以使所述补偿图形408可与所述第三导电连接部407在同一次构图工艺中形成。
在一些实施例中，在一个子像素中，所述电源信号线图形VDD在所述基底上的正投影，完全覆盖所述第一导电部108在所述基底上的正投影。
在一些实施例中，在一个子像素中，所述电源信号线图形VDD在所述基 底上的正投影，覆盖所述第二晶体管T2的第一半导体图形、第二半导体图形和第三导体图形在所述基底上的正投影，同时还覆盖所述第二晶体管T2的第一极在所述基底上的正投影的至少部分，以及所述第二晶体管T2的第二极在所述基底上的正投影的至少部分。
在一些实施例中，所述第一屏蔽部件404为由所述初始化信号线图形延伸出的延伸结构。
具体地，设置所述第一屏蔽部件404为由所述初始化信号线图形延伸出的延伸结构，使得所述第一屏蔽部件404和所述初始化信号线图形能够在同一次构图工艺中形成，从而更好的简化了显示基板的制作工艺流程。
如图20所示，在一些实施例中，所述第一屏蔽部件404与所述初始化信号线图形异层设置，所述第一屏蔽部件404在所述基底50上的正投影，与所述初始化信号线图形在所述基底50上的正投影存在第一重叠区域，所述第一屏蔽部件通过设置在所述第一重叠区域的第一过孔与所述初始化信号线图形耦接；
所述第二屏蔽部件301与所述第一屏蔽部件404异层设置，所述第二屏蔽部件301在所述基底50上的正投影与所述第一屏蔽部件404在所述基底50上的正投影存在第二重叠区域，所述第二屏蔽部件301与所述第一屏蔽部件404之间通过设置在所述第二重叠区域的第二过孔耦接。
具体地，所述第一屏蔽部件404可与所述初始化信号线图形同层设置或异层设置，当所述第一屏蔽部件404与所述初始化信号线图形异层设置时，可设置所述第一屏蔽部件404在所述基底50上的正投影，与所述初始化信号线图形在所述基底50上的正投影均存在第一重叠区域，这样通过在所述第一重叠区域设置第一过孔，即可实现所述第一屏蔽部件404与所述初始化信号线之间的耦接。同样的，所述第二屏蔽部件301可与所述第一屏蔽部件404同层设置或异层设置，当所述第二屏蔽部件301与所述第一屏蔽部件404异层设置时，可设置所述第二屏蔽部件301在所述基底50上的正投影与所述第一屏蔽部件404在所述基底50上的正投影存在第二重叠区域，这样通过在所述第二重叠区域设置第二过孔，使得所述第二屏蔽部件301与所述第一屏蔽部件404之间能够通过所述第二过孔实现耦接。
在一些实施例中，所述第一屏蔽部件404与所述数据线图形同材料设置。
在一些实施例中，所述显示基板包括第一层间绝缘层，所述第一屏蔽部件404与所述数据线图形均位于所述第一层间绝缘层背向所述基底的表面。
具体地，按照上述方式设置所述第一屏蔽部件404，使得能够通过一次构图工艺，将所述第一屏蔽部件404与所述数据线图形同时形成在所述第一层间绝缘层背向所述基底的表面，避免为了制作所述第一屏蔽部件404而增加额外的构图工艺，从而很好的简化了显示基板的制作流程，节约了制作成本。
在一些实施例中，所述第二屏蔽部件301与所述初始化信号线图形同材料设置。
在一些实施例中，所述显示基板还包括第二层间绝缘层，所述第二屏蔽部件301与所述初始化信号线图形均位于所述第二层间绝缘层背向所述基底的表面。
具体地，上述将所述第二屏蔽部件301与所述初始化信号线图形同材料设置，并将所述第二屏蔽部件301与所述初始化信号线图形(如图3中的VINT1)均位于所述第二层间绝缘层背向所述基底的表面，使得所述第二屏蔽部件301能够与所述初始化信号线图形在同一次构图工艺中同时形成，避免了增加额外的专门用于制作所述第二屏蔽部件301的制作工艺，从而很好的简化了显示基板的制作流程，节约了生产成本。
在一些实施例中，所述存储电容中Cst的第一极板Cst1复用为所述驱动晶体管的栅极，所述存储电容Cst中的第二极板Cst2与所述第二屏蔽部件301同材料设置，且所述存储电容Cst中的第二极板Cst2位于所述第二层间绝缘层背向所述基底50的表面。
具体地，所述子像素驱动电路中包括的存储电容Cst具有第一极板Cst1和第二极板Cst2，所述第一极板Cst1和所述第二极板Cst2相对设置，且所述第一极板Cst1与所述驱动晶体管的栅极耦接，所述第二极板Cst2与所述电源信号线图形VDD耦接。在布局该存储电容Cst时，可将所述第一极板Cst1直接复用为所述驱动晶体管的栅极，这样不仅保证了存储电容Cst与驱动晶体管的栅极实现耦接，还缩小了子像素驱动电路占用的空间，更有利于提升 显示基板的分辨率。另外，设置所述存储电容Cst中的第二极板Cst2位于所述第二层间绝缘层背向所述基底的表面，使得所述存储电容Cst中的第二极板Cst2能够与所述第二屏蔽部件301和所述初始化信号线图形在同一次构图工艺中同时形成，从而很好的简化了显示基板的制作流程，节约了生产成本。
在一些实施例中，所述子像素还包括：沿与所述第一方向相交的第二方向延伸的复位信号线图形(如RST1)，所述子像素驱动电路还包括：
第一导电连接部405，所述第一导电连接部405在所述基底50上的正投影覆盖至少部分所述第六导体图形101px在所述基底50上的正投影；
第二晶体管T2，所述第二晶体管T2的第一极(如源极S2)通过所述第一导电连接部405与所述初始化信号线图形(如VINT1)耦接，所述第二晶体管T2的第二极(如漏极D2)与所述驱动晶体管的栅极耦接，所述第二晶体管T2的栅极202g与所述复位信号线图形(如RST1)耦接。
具体地，所述第一导电连接部405可采用金属材料制作，并可与数据线图形在同一次构图工艺中形成。
上述设置所述第一导电连接部405在所述基底50上的正投影覆盖至少部分所述第六导体图形101px在所述基底50上的正投影，使得所述第一导电连接部405能够对所述第六导体图形101px进行遮盖，且由于所述第一导电连接部405与所述初始化信号线图形耦接，使所述第一导电连接部405具有固定电位，从而更好的减小了所述第六导体图形101px与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
如图16所示，在一些实施例中，所述子像素还包括：栅线图形GATE、发光控制信号线图形EM、复位信号线图形(如RST1)和初始化信号线图形(如VINT1)；所述栅线图形GATE、所述发光控制信号线图形EM、所述复位信号线图形和所述初始化信号线图形均沿第二方向延伸，所述第二方向与所述第一方向相交；
所述两个开关晶体管包括第四晶体管T4和第五晶体管T5；
所述子像素驱动电路还包括：第一晶体管T1、第二晶体管T2、第六晶体管T6和第七晶体管T7；
所述驱动晶体管的栅极(如第三晶体管T3的栅极203g)与所述第一晶 体管T1的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管T5的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管T1的第一极耦接；
所述第一晶体管T1的栅极201g与所述栅线图形GATE耦接；
所述第二晶体管T2的栅极202g与所述复位信号线图形耦接，所述第二晶体管T2的第一极与所述初始化信号线图形耦接，所述第二晶体管T2的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管T4的栅极204g与所述栅线图形GATE耦接，所述第四晶体管T4的第一极与所述数据线图形(如图()中的DATA1)耦接，所述第四晶体管T4的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管T5的栅极205g与所述发光控制信号线图形EM耦接，所述第五晶体管T5的第一极与所述电源信号线图形VDD耦接；
所述第六晶体管T6的栅极206g与所述发光控制信号线图形EM耦接，所述第六晶体管T6的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管T6的第二极与所述子像素中的发光元件耦接；
所述第七晶体管T7的栅极207g与沿所述第一方向相邻的下一个子像素包括的复位信号线图形(如RST2)耦接，所述第七晶体管T7的第一极与该下一个子像素包括的初始化信号线图形(如VINT2)耦接，所述第七晶体管T7的第二极与所述子像素中的发光元件耦接。
具体地，上述显示基板中，包括的多个子像素可呈阵列分布，所述多个子像素可划分为多行子像素和多列子像素，每行子像素均包括沿第二方向排列的多个子像素，每列子像素均包括沿第一方向排列的多个子像素，所述第一方向与所述第二方向相交。
需要说明，上述沿所述第一方向相邻的下一个子像素，即与该第七晶体管T7位于同一列的相邻的下一个子像素。
将所述子像素和其包括的子像素驱动电路设置为上述结构，能够在保证子像素驱动电路的工作性能的情况下，有效减小所述子像素驱动电路占用的布局空间，有利于提升显示基板的分辨率。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
由于上述实施例提供的显示基板中，设置所述存储电容Cst的第二极板 Cst2与所述电源信号线图形VDD耦接，使得存储电容Cst的第二极板Cst2具有与所述电源信号线图形VDD上传输的电源信号相同的固定电位；同时设置所述两个开关晶体管的第二极均与所述驱动晶体管的第一极耦接，所述两个开关晶体管中的至少一个开关晶体管的第二极在所述基底50上的正投影，与所述电源信号线图形VDD在所述基底50上的正投影至少部分重叠，且与所述存储电容Cst的第二极板Cst2在所述基底50上的正投影至少部分重叠，使得存储电容Cst的第二极板Cst2和所述电源信号线图形VDD均能够对所述两个开关晶体管中的至少一个开关晶体管的第二极进行遮挡，从而减小了位于所述两个开关晶体管中的至少一个开关晶体管周边的其它导电图形(如信号线图形)上的信号，对所述两个开关晶体管中的至少一个开关晶体管的第二极产生的串扰现象，进而减小了对所述驱动晶体管的第一极产生的串扰现象。
因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
本公开实施例还提供了一种显示基板的制作方法，所述制作方法包括：在基底上制作阵列分布的多个子像素；所述子像素包括：沿第一方向延伸的数据线图形；电源信号线图形，所述电源信号线图形包括沿所述第一方向延伸的部分；子像素驱动电路，所述子像素驱动电路包括：两个开关晶体管、驱动晶体管和存储电容；所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与所述电源信号线图形耦接；所述两个开关晶体管的第二极均与所述驱动晶体管的第一极耦接，所述两个开关晶体管中的至少一个开关晶体管的第二极在所述基底上的正投影，与所述电源信号线图形在所述基底上的正投影至少部分重叠，且与所述存储电容的第二极板在所述基底上的正投影至少部分重叠。
采用本公开实施例提供的制作方法制作的显示基板中，设置所述存储电容Cst的第二极板Cst2与所述电源信号线图形VDD耦接，使得存储电容Cst的第二极板Cst2具有与所述电源信号线图形VDD上传输的电源信号相同的固定电位；同时设置所述两个开关晶体管的第二极均与所述驱动晶体管的第一极耦接，所述两个开关晶体管中的至少一个开关晶体管的第二极在所述基 底50上的正投影，与所述电源信号线图形VDD在所述基底50上的正投影至少部分重叠，且与所述存储电容Cst的第二极板Cst2在所述基底50上的正投影至少部分重叠，使得存储电容Cst的第二极板Cst2和所述电源信号线图形VDD均能够对所述两个开关晶体管中的至少一个开关晶体管的第二极进行遮挡，从而减小了位于所述两个开关晶体管中的至少一个开关晶体管周边的其它导电图形(如信号线图形)上的信号，对所述两个开关晶体管中的至少一个开关晶体管的第二极产生的串扰现象，进而减小了对所述驱动晶体管的第一极产生的串扰现象。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护 范围应以所述权利要求的保护范围为准。

Claims (38)

  1. 一种显示基板，包括：基底和在所述基底上阵列分布的多个子像素；所述子像素包括：
    沿第一方向延伸的数据线图形；
    初始化信号线图形，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
    子像素驱动电路，所述子像素驱动电路包括：驱动晶体管，与所述驱动晶体管的栅极耦接的第一晶体管，以及与所述初始化信号线图形耦接的第一屏蔽部件，所述第一屏蔽部件在所述基底上的正投影，位于所述第一晶体管在所述基底上的正投影与目标数据线图形在所述基底上的正投影之间；沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
  2. 根据权利要求1所述的显示基板，其中，所述阵列分布的多个子像素包括多行子像素，每行子像素均包括沿所述第二方向排列的所述子像素，位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的初始化信号线；
    所述第一屏蔽部件沿所述第一方向延伸，与至少一条所述初始化信号线耦接。
  3. 根据权利要求2所述的显示基板，其中，
    所述第一屏蔽部件与其相邻的两条所述初始化信号线耦接。
  4. 根据权利要求1所述的显示基板，其中，所述第一屏蔽部件与所述初始化信号线图形异层设置，所述第一屏蔽部件在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影存在第一重叠区域，所述第一屏蔽部件通过设置在所述第一重叠区域的第一过孔与所述初始化信号线图形耦接。
  5. 根据权利要求1所述的显示基板，其中，所述第一屏蔽部件与所述数据线图形同材料设置。
  6. 根据权利要求1所述的显示基板，其中，所述显示基板包括第一层间 绝缘层，所述第一屏蔽部件与所述数据线图形均位于所述第一层间绝缘层背向所述基底的表面。
  7. 根据权利要求1所述的显示基板，其中，所述子像素驱动电路还包括与所述驱动晶体管的栅极耦接的第二晶体管，所述第二晶体管包括：
    第一半导体图形、第二半导体图形和分别与所述第一半导体图形和所述第二半导体图形耦接的第三导体图形，所述第三导体图形的导电性能优于所述第一半导体图形的导电性能和所述第二半导体图形的导电性能；
    第一栅极图形和第二栅极图形，所述第一栅极图形在所述基底上的正投影与所述第一半导体图形在所述基底上的正投影至少部分重叠，所述第二栅极图形在所述基底上的正投影与所述第二半导体图形在所述基底上的正投影至少部分重叠；
    所述第三导体图形在所述基底上的正投影与所述第一栅极图形在所述基底上的正投影，以及所述第二栅极图形在所述基底上的正投影均不重叠；
    所述第三导体图形在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影至少部分重叠。
  8. 根据权利要求7所述的显示基板，其中，所述子像素驱动电路还包括由所述第一半导体图形延伸出的第一延伸部，所述第一延伸部的导电性能优于所述第一半导体图形；
    所述第一延伸部包括第一部分、第二部分和第三部分，所述第一部分和所述第三部分均沿所述第一方向延伸，所述第二部分沿所述第二方向延伸，所述第二部分的一端与所述第一部分耦接，所述第二部分的另一端与所述第三部分耦接；
    所述第三部分远离所述第二部分的一端与所述第一晶体管耦接。
  9. 根据权利要求1所述的显示基板，其中，所述第一晶体管包括：
    第四半导体图形、第五半导体图形和分别与所述第四半导体图形和所述第五半导体图形耦接的第六导体图形，所述第六导体图形的导电性能优于所述第四半导体图形的导电性能和所述第五半导体图形的导电性能；
    相耦接的第三栅极图形和第四栅极图形，所述第三栅极图形在所述基底上的正投影与所述第四半导体图形在所述基底上的正投影部分重叠，所述第 四栅极图形在所述基底上的正投影与所述第五半导体图形在所述基底上的正投影部分重叠；
    所述第六导体图形在所述基底上的正投影与所述第三栅极图形在所述基底上的正投影，以及所述第四栅极图形在所述基底上的正投影均不重叠。
  10. 根据权利要求9所述的显示基板，其中，所述第一屏蔽部件在所述基底上的正投影，与所述第六导体图形在所述基底上的正投影至少部分重叠。
  11. 根据权利要求9所述的显示基板，其中，所述子像素驱动电路还包括：
    与所述第一屏蔽部件耦接的第二屏蔽部件，所述第二屏蔽部件在所述基底上的正投影，与所述第六导体图形在所述基底上的正投影至少部分重叠。
  12. 根据权利要求11所述的显示基板，其中，所述第二屏蔽部件与所述第一屏蔽部件异层设置，所述第二屏蔽部件在所述基底上的正投影与所述第一屏蔽部件在所述基底上的正投影存在第二重叠区域，所述第二屏蔽部件与所述第一屏蔽部件之间通过设置在所述第二重叠区域的第二过孔耦接。
  13. 根据权利要求11所述的显示基板，其中，所述第二屏蔽部件与所述初始化信号线图形同材料设置。
  14. 根据权利要求11所述的显示基板，其中，所述显示基板还包括第二层间绝缘层，所述第二屏蔽部件与所述初始化信号线图形均位于所述第二层间绝缘层背向所述基底的表面。
  15. 根据权利要求14所述的显示基板，其中，所述子像素还包括电源信号线图形，所述电源信号线图形包括沿所述第一方向延伸的部分，所述子像素驱动电路还包括存储电容，所述存储电容中的第一极板复用为所述驱动晶体管的栅极，所述存储电容中的第二极板与所述电源信号线图形耦接，所述存储电容中的第二极板位于所述第二层间绝缘层背向所述基底的表面。
  16. 根据权利要求9所述的显示基板，其中，所述子像素还包括：沿与所述第一方向相交的第二方向延伸的复位信号线图形，所述子像素驱动电路还包括：
    第一导电连接部，所述第一导电连接部在所述基底上的正投影覆盖至少部分所述第六导体图形在所述基底上的正投影；
    第二晶体管，所述第二晶体管的第一极通过所述第一导电连接部与所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接，所述第二晶体管的栅极与所述复位信号线图形耦接。
  17. 根据权利要求1所述的显示基板，其中，所述子像素还包括：栅线图形、发光控制信号线图形、复位信号线图形和电源信号线图形；所述栅线图形、所述发光控制信号线图形和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形包括沿所述第一方向延伸的部分；
    所述子像素驱动电路还包括：第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
    所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
    所述第一晶体管的栅极与所述栅线图形耦接；
    所述第二晶体管的栅极与所述复位信号线图形耦接，所述第二晶体管的第一极与所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
    所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述子像素中的发光元件耦接；
    所述第七晶体管的栅极与沿所述第一方向相邻的下一个子像素包括的复位信号线图形耦接，所述第七晶体管的第一极与该下一个子像素包括的初始化信号线图形耦接，所述第七晶体管的第二极与所述子像素中的发光元件耦接。
  18. 根据权利要求1所述的显示基板，其中，所述子像素还包括：栅线 图形、发光控制信号线图形、复位信号线图形和电源信号线图形；所述栅线图形、所述发光控制信号线图形和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形包括沿所述第一方向延伸的部分；所述第一屏蔽部件在所述基底上的正投影，分别与所述栅线图形在所述基底上的正投影，以及所述发光控制信号线图形在所述基底上的正投影部分交叠。
  19. 一种显示基板，包括：基底和在所述基底上阵列分布的多个子像素；所述子像素包括：
    沿第一方向延伸的数据线图形；
    初始化信号线图形，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
    子像素驱动电路，所述子像素驱动电路包括：驱动晶体管，与所述驱动晶体管的栅极耦接的第一晶体管，以及与所述初始化信号线图形耦接的第一屏蔽部件，所述第一屏蔽部件用于与所述第一晶体管的第一极形成耦合电容，所述第一屏蔽部件在基底上正投影与目标数据线图形在所述基底上正投影不交叠，沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
  20. 根据权利要求19所述的显示基板，其中，所述阵列分布的多个子像素包括多行子像素，每行子像素均包括沿所述第二方向排列的所述子像素，位于同一行子像素中的所述初始化信号线图形依次耦接，形成该行子像素对应的初始化信号线；
    所述第一屏蔽部件沿所述第一方向延伸，与至少一条所述初始化信号线耦接。
  21. 根据权利要求20所述的显示基板，其中，
    所述第一屏蔽部件与其相邻的两条所述初始化信号线耦接。
  22. 根据权利要求19所述的显示基板，其中，所述第一屏蔽部件与所述初始化信号线图形异层设置，所述第一屏蔽部件在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影存在第一重叠区域，所述第一 屏蔽部件通过设置在所述第一重叠区域的第一过孔与所述初始化信号线图形耦接。
  23. 根据权利要求19所述的显示基板，其中，所述第一屏蔽部件与所述数据线图形同材料设置。
  24. 根据权利要求19所述的显示基板，其中，所述显示基板包括第一层间绝缘层，所述第一屏蔽部件与所述数据线图形均位于所述第一层间绝缘层背向所述基底的表面。
  25. 根据权利要求19所述的显示基板，其中，所述子像素驱动电路还包括与所述驱动晶体管的栅极耦接的第二晶体管，所述第二晶体管包括：
    第一半导体图形、第二半导体图形和分别与所述第一半导体图形和所述第二半导体图形耦接的第三导体图形，所述第三导体图形的导电性能优于所述第一半导体图形的导电性能和所述第二半导体图形的导电性能；
    第一栅极图形和第二栅极图形，所述第一栅极图形在所述基底上的正投影与所述第一半导体图形在所述基底上的正投影至少部分重叠，所述第二栅极图形在所述基底上的正投影与所述第二半导体图形在所述基底上的正投影至少部分重叠；
    所述第三导体图形在所述基底上的正投影与所述第一栅极图形在所述基底上的正投影，以及所述第二栅极图形在所述基底上的正投影均不重叠；
    所述第三导体图形在所述基底上的正投影，与所述初始化信号线图形在所述基底上的正投影至少部分重叠。
  26. 根据权利要求25所述的显示基板，其中，所述子像素驱动电路还包括由所述第一半导体图形延伸出的第一延伸部，所述第一延伸部的导电性能优于所述第一半导体图形；
    所述第一延伸部包括第一部分、第二部分和第三部分，所述第一部分和所述第三部分均沿所述第一方向延伸，所述第二部分沿所述第二方向延伸，所述第二部分的一端与所述第一部分耦接，所述第二部分的另一端与所述第三部分耦接；
    所述第三部分远离所述第二部分的一端与所述第一晶体管耦接。
  27. 根据权利要求19所述的显示基板，其中，所述第一晶体管包括：
    第四半导体图形、第五半导体图形和分别与所述第四半导体图形和所述第五半导体图形耦接的第六导体图形，所述第六导体图形的导电性能优于所述第四半导体图形的导电性能和所述第五半导体图形的导电性能；
    相耦接的第三栅极图形和第四栅极图形，所述第三栅极图形在所述基底上的正投影与所述第四半导体图形在所述基底上的正投影部分重叠，所述第四栅极图形在所述基底上的正投影与所述第五半导体图形在所述基底上的正投影部分重叠；
    所述第六导体图形在所述基底上的正投影与所述第三栅极图形在所述基底上的正投影，以及所述第四栅极图形在所述基底上的正投影均不重叠。
  28. 根据权利要求27所述的显示基板，其中，所述第一屏蔽部件在所述基底上的正投影，与所述第六导体图形在所述基底上的正投影至少部分重叠。
  29. 根据权利要求27所述的显示基板，其中，所述子像素驱动电路还包括：
    与所述第一屏蔽部件耦接的第二屏蔽部件，所述第二屏蔽部件在所述基底上的正投影，与所述第六导体图形在所述基底上的正投影至少部分重叠。
  30. 根据权利要求29所述的显示基板，其中，所述第二屏蔽部件与所述第一屏蔽部件异层设置，所述第二屏蔽部件在所述基底上的正投影与所述第一屏蔽部件在所述基底上的正投影存在第二重叠区域，所述第二屏蔽部件与所述第一屏蔽部件之间通过设置在所述第二重叠区域的第二过孔耦接。
  31. 根据权利要求29所述的显示基板，其中，所述第二屏蔽部件与所述初始化信号线图形同材料设置。
  32. 根据权利要求29所述的显示基板，其中，所述显示基板还包括第二层间绝缘层，所述第二屏蔽部件与所述初始化信号线图形均位于所述第二层间绝缘层背向所述基底的表面。
  33. 根据权利要求32所述的显示基板，其中，所述子像素还包括电源信号线图形，所述电源信号线图形包括沿所述第一方向延伸的部分，所述子像素驱动电路还包括存储电容，所述存储电容中的第一极板复用为所述驱动晶体管的栅极，所述存储电容中的第二极板与所述电源信号线图形耦接，所述存储电容中的第二极板位于所述第二层间绝缘层背向所述基底的表面。
  34. 根据权利要求27所述的显示基板，其中，所述子像素还包括：沿与所述第一方向相交的第二方向延伸的复位信号线图形，所述子像素驱动电路还包括：
    第一导电连接部，所述第一导电连接部在所述基底上的正投影覆盖至少部分所述第六导体图形在所述基底上的正投影；
    第二晶体管，所述第二晶体管的第一极通过所述第一导电连接部与所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接，所述第二晶体管的栅极与所述复位信号线图形耦接。
  35. 根据权利要求19所述的显示基板，其中，所述子像素还包括：栅线图形、发光控制信号线图形、复位信号线图形和电源信号线图形；所述栅线图形、所述发光控制信号线图形和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形包括沿所述第一方向延伸的部分；
    所述子像素驱动电路还包括：第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
    所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
    所述第一晶体管的栅极与所述栅线图形耦接；
    所述第二晶体管的栅极与所述复位信号线图形耦接，所述第二晶体管的第一极与所述初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
    所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与所述子像素中的发光元件耦接；
    所述第七晶体管的栅极与沿所述第一方向相邻的下一个子像素包括的复位信号线图形耦接，所述第七晶体管的第一极与该下一个子像素包括的初始化信号线图形耦接，所述第七晶体管的第二极与所述子像素中的发光元件耦接。
  36. 根据权利要求19所述的显示基板，其中，所述子像素还包括：栅线图形、发光控制信号线图形、复位信号线图形和电源信号线图形；所述栅线图形、所述发光控制信号线图形和所述复位信号线图形均沿所述第二方向延伸，所述电源信号线图形包括沿所述第一方向延伸的部分；所述第一屏蔽部件在所述基底上的正投影，分别与所述栅线图形在所述基底上的正投影，以及所述发光控制信号线图形在所述基底上的正投影部分交叠。
  37. 一种显示装置，包括如权利要求1～36中任一项所述的显示基板。
  38. 一种显示基板的制作方法，包括：
    在基底上制作阵列分布的多个子像素；所述子像素包括：
    沿第一方向延伸的数据线图形；
    初始化信号线图形，所述初始化信号线图形包括沿第二方向延伸的部分，所述第二方向与所述第一方向相交，所述初始化信号线图形用于传输具有固定电位的初始化信号；
    子像素驱动电路，所述子像素驱动电路包括：驱动晶体管，与所述驱动晶体管的栅极耦接的第一晶体管，以及与所述初始化信号线图形耦接的第一屏蔽部件，所述第一屏蔽部件在所述基底上的正投影，位于所述第一晶体管在所述基底上的正投影与目标数据线图形在所述基底上的正投影之间；沿所述第二方向与该子像素相邻的下一个子像素中包括所述目标数据线图形。
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