WO2023092607A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023092607A1
WO2023092607A1 PCT/CN2021/134167 CN2021134167W WO2023092607A1 WO 2023092607 A1 WO2023092607 A1 WO 2023092607A1 CN 2021134167 W CN2021134167 W CN 2021134167W WO 2023092607 A1 WO2023092607 A1 WO 2023092607A1
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Prior art keywords
transistor
sub
coupled
pixels
active layer
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PCT/CN2021/134167
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English (en)
French (fr)
Inventor
袁志东
李永谦
袁粲
刘军
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/926,747 priority Critical patent/US20240138211A1/en
Priority to PCT/CN2021/134167 priority patent/WO2023092607A1/zh
Priority to CN202180003679.8A priority patent/CN116601768A/zh
Publication of WO2023092607A1 publication Critical patent/WO2023092607A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • OLED Organic Light-Emitting Diode
  • OLED display products use the direct recombination of electrons and holes to excite spectra of various wavelengths to form images.
  • OLED display products have the advantages of fast response speed and maximum contrast ratio, and are expected to become the mainstream display products of the next generation.
  • OLED display products include: display panel, gate driver, data driver and timing controller.
  • the display panel includes: data lines, grid lines and pixels.
  • the working mode is as follows: the gate driving device provides the gate driving signal to the gate line, and when the gate driving signal is supplied to the gate line, the corresponding row of pixels is written with the data voltage transmitted by the data line.
  • the pixels emit light with different brightness according to the magnitude of the data voltage to realize the display function.
  • the purpose of the present disclosure is to provide a display substrate and a display device.
  • a first aspect of the present disclosure provides a display substrate, including: a substrate, a plurality of sub-pixels disposed on the substrate, the plurality of sub-pixels are arranged in an array; the sub-pixels include:
  • a sub-pixel driving circuit includes a driving transistor and a second transistor, the gate of the second transistor is coupled to the second scanning line, the first electrode of the second transistor is connected to the reference
  • the signal line is formed as an integral structure, and the second pole of the second transistor is coupled to the gate of the driving transistor.
  • the second transistor includes a second active layer, the second active layer forms the first pole and the second pole of the second transistor, at least part of the reference signal line is along the first direction extending; at least part of the second active layer extends along the first direction; at least part of the second scan line extends along the first direction; the second active layer on the substrate At least part of the orthographic projection is located between the orthographic projection of the reference signal line on the substrate and the orthographic projection of the second scan line on the substrate.
  • the sub-pixel also includes a first scan line, a data line and a first connection pattern;
  • the sub-pixel driving circuit also includes a first transistor;
  • the gate of the first transistor is coupled to the first scan line, the first pole of the first transistor is coupled to the data line, the second pole of the first transistor is coupled to the driving transistor gate coupling;
  • the first connection pattern is respectively coupled to the second pole of the first transistor and the second pole of the second transistor, and the orthographic projection of the first connection pattern on the substrate is respectively connected to the second pole of the first transistor.
  • the orthographic projection of a scan line on the substrate partially overlaps the orthographic projection of the second scan line on the substrate.
  • the multiple sub-pixels are divided into multiple repeating units, and the multiple repeating units are divided into multiple columns of repeating unit columns;
  • the display substrate further includes multiple power lines, and the power lines are connected to the repeating units columns are arranged alternately along said first direction;
  • the reference signal lines in the sub-pixels located in the same row along the first direction form an integrated structure;
  • the orthographic projections on the above bases do not overlap.
  • the sub-pixel further includes a third scan line and an initialization signal line;
  • the sub-pixel driving circuit further includes a third transistor, the gate of the third transistor is coupled to the third scanning line, and the first electrode of the third transistor is formed into an integral structure with the initialization signal line, so The second pole of the third transistor is coupled to the first pole of the driving transistor.
  • the initialization signal lines in the sub-pixels located in the same row along the first direction form an integrated structure; the orthographic projection of the initialization signal lines on the substrate is the same as the The orthographic projections of the power lines on the substrate do not overlap.
  • the repeating unit includes an initialization signal bus, at least part of the initialization signal bus extends along a second direction, and the second direction intersects the first direction; the initialization signal bus and the initialization signal line coupling.
  • the third transistor includes a double-gate structure, the third transistor includes a third active layer, the third active layer includes two third channel portions, and the two third conductor portions to which the channel portions are respectively coupled;
  • the repeating unit includes a plurality of second connection patterns, and in the repeating unit, along the first direction, the first poles of adjacent third transistors are coupled through the second connection patterns, or The conductor parts of the adjacent third transistors are coupled through the second connection pattern; the orthographic projection of the second connection pattern on the substrate is located at the two adjacent third transistors that are coupled between the orthographic projections of a portion of the grid on said substrate;
  • the repeating unit further includes an initialization signal bus extending along a second direction intersecting the first direction, and the initialization signal bus is coupled to the second connection pattern.
  • the first pole of the third transistor or the conductor part to which the second connection pattern is coupled is formed as an integral structure.
  • the third active layer includes a U-shaped structure, and the orthographic projection of the third active layer on the substrate has two intersections with the orthographic projection of the third scan line on the substrate. stack area; the two ends of the third active layer located at the U-shaped opening are respectively coupled to the initialization signal line; the part of the third active layer located at the bottom of the U-shaped opening is coupled to the first pole of the drive transistor .
  • the sub-pixel also includes a light emission control line
  • the sub-pixel driving circuit further includes a fourth transistor, the gate of the fourth transistor is coupled to the light emission control line, the first electrode of the fourth transistor is coupled to the power supply line, and the fourth transistor the second pole of the transistor is coupled to the second pole of the driving transistor;
  • adjacent sub-pixel driving circuits along the second direction multiplex the same fourth transistor, and multiplex the same light emission control signal line.
  • the sub-pixel includes an anode pattern
  • the fourth transistor includes a fourth active layer, and the orthographic projection of the fourth active layer on the substrate is located at the orthographic projection of two adjacent anode patterns along the second direction on the substrate between.
  • the driving transistor includes a driving active layer
  • the two driving active layers included in the two driving transistors are arranged axisymmetrically with respect to a first axis of symmetry, and the first axis of symmetry extends along the second direction,
  • the orthographic projection of the first axis of symmetry on the substrate is located between the orthographic projections of the two anode patterns included in the two adjacent sub-pixels along the first direction on the substrate;
  • the two driving active layers included in the two driving transistors are arranged axisymmetrically with respect to a second axis of symmetry, and the second axis of symmetry extends along the first direction,
  • the orthographic projection of the second axis of symmetry on the substrate is located between the orthographic projections of the two anode patterns included in the two adjacent sub-pixels along the second direction on the substrate.
  • the second transistor includes a second active layer
  • the two second active layers included in the two second transistors are arranged axisymmetrically with respect to the first axis of symmetry;
  • the two second active layers included in the two second transistors are arranged axisymmetrically with respect to the second axis of symmetry.
  • the sub-pixel driving circuit further includes a first transistor, and the first transistor includes a first active layer;
  • the two first active layers included in the two first transistors are arranged axisymmetrically with respect to the first axis of symmetry;
  • the two first active layers included in the two first transistors are arranged axisymmetrically with respect to the second axis of symmetry.
  • the sub-pixel driving circuit further includes a third transistor, and the third transistor includes a third active layer;
  • the two third active layers included in the two third transistors are arranged axisymmetrically with respect to the first axis of symmetry;
  • the two third active layers included in the two third transistors are arranged axisymmetrically with respect to the second axis of symmetry.
  • the sub-pixel driving circuit further includes a fourth transistor, and the fourth transistor includes a fourth active layer;
  • the two fourth active layers included in the two fourth transistors are arranged axisymmetrically with respect to the first axis of symmetry.
  • a second aspect of the present disclosure provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a circuit diagram corresponding to the smallest repeating unit in a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a driving timing diagram of two adjacent sub-pixel driving circuits along the second direction provided by an embodiment of the present disclosure
  • Fig. 3 is a schematic diagram of a first layout corresponding to the circuit diagram in Fig. 1;
  • FIG. 4 is a schematic diagram of the active layer in FIG. 3;
  • FIG. 5 is a schematic layout diagram of the first gate metal layer in FIG. 3;
  • FIG. 6 is a schematic layout diagram of a second gate metal layer in FIG. 3;
  • FIG. 7 is a schematic layout diagram of the first source-drain metal layer in FIG. 3;
  • FIG. 8 is a schematic layout diagram of a second source-drain metal layer in FIG. 3;
  • FIG. 9 is a schematic layout diagram of openings formed by the pixel defining layer in FIG. 3;
  • FIG. 10 is a schematic layout diagram of the active layer and the first gate metal layer in FIG. 3;
  • FIG. 11 is a schematic layout diagram of the active layer, the second gate metal layer, and the first source-drain metal layer in FIG. 3;
  • FIG. 12 is a schematic layout diagram of the first source-drain metal layer and the second source-drain metal layer in FIG. 3;
  • FIG. 13 is a schematic layout diagram of an anode layer and a second source-drain metal layer provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic layout diagram of adding a second gate metal layer and a first source-drain metal layer in FIG. 10;
  • FIG. 15 is a schematic layout diagram of adding a second source-drain metal layer and an anode layer in FIG. 14;
  • FIG. 16 is a schematic diagram of a second layout corresponding to the circuit diagram in FIG. 1;
  • Figure 17 is a schematic diagram of the active layer in Figure 16.
  • FIG. 18 is a schematic layout diagram of the second gate metal layer in FIG. 16;
  • FIG. 19 is a schematic layout diagram of the first source-drain metal layer in FIG. 16;
  • FIG. 20 is a schematic layout diagram of the active layer and the first gate metal layer in FIG. 16;
  • FIG. 21 is a schematic layout diagram of the active layer, the second gate metal layer, and the first source-drain metal layer in FIG. 16;
  • FIG. 22 is a schematic layout diagram of the first source-drain metal layer and the second source-drain metal layer in FIG. 16;
  • FIG. 23 is a schematic diagram of a third layout corresponding to the circuit diagram in FIG. 1;
  • Figure 24 is a schematic diagram of the active layer in Figure 23;
  • FIG. 25 is a schematic layout diagram of the active layer and the first gate metal layer in FIG. 23;
  • FIG. 26 is a schematic diagram of a fourth layout corresponding to the circuit diagram in FIG. 1;
  • Figure 27 is a schematic diagram of the active layer in Figure 26;
  • FIG. 28 is a schematic layout diagram of the first gate metal layer in FIG. 26;
  • FIG. 29 is a partial cross-sectional schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display substrate, including: a base, a plurality of sub-pixels arranged on the base, The multiple sub-pixels are distributed in an array; the sub-pixels include:
  • a sub-pixel driving circuit includes a driving transistor T5 and a second transistor T2, the gate of the second transistor T2 is coupled to the second scanning line 42, and the first transistor T2 of the second transistor T2
  • the pole is formed as an integral structure with the reference signal line 36, and the second pole of the second transistor T2 is coupled to the gate of the driving transistor T5.
  • the display substrate includes a display area and a peripheral area surrounding the display area.
  • the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels are distributed in the display area in an array.
  • the sub-pixel includes a sub-pixel driving circuit and a light-emitting element, and the sub-pixel driving circuit is coupled to the light-emitting element for providing a driving signal to the light-emitting element, so as to drive the light-emitting element to emit light.
  • the sub-pixel driving circuit includes a 5T1C circuit structure, that is, includes 5 thin film transistors and a storage capacitor.
  • the light-emitting element includes an anode pattern, a light-emitting functional layer and a cathode layer sequentially stacked along a direction away from the substrate;
  • the light-emitting functional layer includes a stacked electron injection layer, an electron transport layer, and an organic light-emitting material layer, hole transport layer and hole injection layer.
  • the cathode layer receives a negative power supply signal VSS.
  • the electron injection layer included in each sub-pixel is formed into an integrated structure, capable of covering the entire display area; similarly, the electron transport layer included in each sub-pixel, the hole Both the transport layer and the hole injection layer can also be formed as an integral structure, which can cover the entire display area.
  • the cathode layer included in each sub-pixel is formed as an integral structure, which can cover the entire display area.
  • At least part of the reference signal line 36 extends along the first direction. At least part of the second scan line 42 extends along the first direction.
  • the second scan lines 42 in the same row of sub-pixels along the first direction are coupled in sequence to form an integrated structure.
  • the gate of the driving transistor T5 is coupled to the second pole of the second transistor T2, and the first pole of the driving transistor T5 is coupled to the light emitting element.
  • the second transistor T2 includes a double-gate transistor, and the two gates of the second transistor T2 are integrally formed with the second scan line 42 .
  • the two gates are arranged along the first direction.
  • the first pole of the second transistor T2 is integrated with the reference signal line 36 .
  • the first pole of the second transistor T2 and the reference signal line 36 are formed into an integrated structure, which can reduce the size of the second transistor T2.
  • the distance between the first electrode and the reference signal line 36 reduces the layout space occupied by the sub-pixels and reduces the layout difficulty of the sub-pixels.
  • there is no need to arrange other transfer patterns to connect the electrical connection between the first pole of the second transistor T2 and the reference signal line 36 which further reduces the layout difficulty of the display substrate.
  • the first electrode of the second transistor T2 is set to form an integral structure with the reference signal line 36, so that the first electrode of the second transistor T2 and the reference signal line
  • the signal line 36 can be formed and coupled in the same process at the same time, which not only simplifies the manufacturing process flow of the display substrate, reduces the manufacturing cost, but also better ensures that the first electrode of the second transistor T2 and all
  • the above connection performance of the reference signal line 36 improves the production yield of the display substrate.
  • the second transistor T2 is set to include a second active layer 32, and the second active layer
  • the source layer 32 forms the first pole and the second pole of the second transistor T2, at least part of the reference signal line 36 extends along the first direction; at least part of the second active layer 32 extends along the first direction. direction; at least part of the second scanning line 42 extends along the first direction; at least part of the orthographic projection of the second active layer 32 on the substrate is located at the reference signal line 36 at the Between the orthographic projection on the substrate and the orthographic projection of the second scan line 42 on the substrate.
  • the second transistor T2 is set to include a second active layer 32, and the second active layer
  • the source layer 32 forms the first pole and the second pole of the second transistor T2
  • the second active layer 32 and the reference signal line 36 form an integral structure.
  • the second active layer 32 includes at least a portion extending along the first direction.
  • the second active layer 32 is used to form the first pole, the second pole of the second transistor T2, and the channel portion of the second transistor T2.
  • the reference signal line 36 and the second active layer 32 are made of the same layer and material, and can be formed into an integrated structure in the same patterning process.
  • the second active layer 32 and the reference signal line 36 are arranged along a second direction, and the second direction intersects the first direction.
  • the first direction includes the horizontal direction
  • the second direction includes the longitudinal direction.
  • the above arrangement can reduce the distance between the second active layer 32 and the reference signal line 36 , reduce the layout space occupied by the sub-pixels, and reduce the layout difficulty of the sub-pixels. Moreover, there is no need to arrange other transfer patterns to realize the electrical connection between the first pole of the second transistor T2 and the reference signal line 36 , which further reduces the layout difficulty of the display substrate.
  • the reference signal line 36 and the second active layer 32 can be simultaneously formed into an integrated structure in the same patterning process, which not only simplifies the manufacturing process of the display substrate, reduces the manufacturing cost, but also better ensures
  • the connection between the first electrode of the second transistor T2 and the reference signal line 36 improves the manufacturing yield of the display substrate.
  • the reference signal line 36 and the second active layer 32 are formed into an integral structure, so that the reference signal line 36 and the second scanning line 42 are arranged in different layers, which reduces the The probability of short circuit with the second scanning line 42 effectively improves the yield of the display substrate.
  • At least part of the reference signal line 36 is set to extend along the first direction; At least part of the active layer 32 extends along the first direction; at least part of the second scan line 42 extends along the first direction; the orthographic projection of the second active layer 32 on the substrate At least partly, it is located between the orthographic projection of the reference signal line 36 on the substrate and the orthographic projection of the second scanning line 42 on the substrate.
  • the orthographic projection of the two gates of the second transistor T2 on the substrate is located at the orthographic projection of the reference signal line 36 on the substrate and the second scanning line 42 on the substrate. Between orthographic projections on the base.
  • the above arrangement makes the gate of the second transistor T2 close to the second scanning line 42, and the second active layer 32 is close to the reference signal line 36, which is beneficial to the gate of the second transistor T2 and
  • the second scanning line 42 is formed into an integrated structure, which is beneficial to the formation of the second active layer 32 and the reference signal line 36 into an integrated structure.
  • the above arrangement can minimize the layout space occupied by the second transistor T2, the reference signal line 36 and the second scan line 42, which is beneficial to reduce the layout difficulty of the display substrate.
  • the sub-pixels further include a first scanning line 41, a data line 62 and a second A connection pattern 61; the sub-pixel driving circuit further includes a first transistor T1;
  • the gate of the first transistor T1 is coupled to the first scanning line 41, the first pole of the first transistor T1 is coupled to the data line 62, and the second pole of the first transistor T1 is coupled to the data line 62.
  • the gate of the driving transistor T5 is coupled;
  • the first connection pattern 61 is respectively coupled to the second pole of the first transistor T1 and the second pole of the second transistor T2, and the orthographic projection of the first connection pattern 61 on the substrate is respectively Partially overlap with the orthographic projection of the first scan line 41 on the substrate and the orthographic projection of the second scan line 42 on the substrate.
  • the first scan line 41 includes at least a portion extending along the first direction.
  • the first scan lines 41 in the sub-pixels located in the same row along the first direction are sequentially coupled to form an integrated structure.
  • the data line 62 includes at least a portion extending along the second direction, and the data lines 62 in the sub-pixels in the same column along the second direction are sequentially coupled to form an integrated structure.
  • each repeating unit includes four pixel units, and each pixel unit includes a first sub-pixel arranged along the first direction, a second sub-pixel and a second sub-pixel Three sub-pixels.
  • the first sub-pixel is coupled to the first data line 621
  • the second sub-pixel is coupled to the second data line 622
  • the third sub-pixel is coupled to the third data line 623 .
  • the first sub-pixel, the second sub-pixel and the third sub-pixel have different colors.
  • the first sub-pixel includes a red sub-pixel
  • the second sub-pixel includes a green sub-pixel
  • the third sub-pixel includes a blue sub-pixel.
  • FIG. 1 shows the red data signals DATAR1 and DATAR2 received by the red sub-pixel, the green data signals DATAG1 and DATAG2 received by the green sub-pixel, and the blue data signals DATAB1 and DATAB2 received by the blue sub-pixel.
  • the first transistor T1 includes a double-gate structure, the two gates of the first transistor T1 are arranged along the first direction, and the two gates and the first scanning line 41 are formed as One structure.
  • the first transistor T1 includes a first active layer 31 including at least a portion extending along the first direction.
  • the orthographic projection of the first active layer 31 on the substrate at least partially overlaps the orthographic projections of the two gates on the substrate.
  • the first active layer 31 forms the first pole and the second pole of the first transistor T1, and the channel portion of the first transistor T1.
  • the orthographic projection of the reference signal line 36 on the substrate, the orthographic projection of the second active layer 32 on the substrate, the second scanning line 42 The orthographic projection on the substrate, the orthographic projection of the first scan line 41 on the substrate, and the orthographic projection of the first active layer 31 on the substrate are arranged in sequence.
  • the first connection pattern 61 includes at least a portion extending along the second direction.
  • the first connection pattern 61 is coupled to the second pole of the first transistor T1 through a via hole, and the first connection pattern 61 is coupled to the second pole of the second transistor T2 through a via hole.
  • the first connection pattern 61 is coupled to the gate of the driving transistor T5 through a via hole.
  • the first connection pattern 61 is made by using the first source-drain metal layer in the display substrate.
  • Layout of the first transistor T1, the second transistor T2, the first scan line 41 and the second scan line 42 according to the above-mentioned method is beneficial to reduce the layout space occupied by the sub-pixels and reduce the The layout of pixels is difficult, and at the same time, it is beneficial to improve the yield rate of the display substrate.
  • the plurality of sub-pixels are divided into a plurality of repeating units, and the plurality of repeating units are divided into Multiple columns of repeating unit columns;
  • the display substrate further includes multiple power supply lines VDD, and the power supply lines VDD and the repeating unit columns are arranged alternately along the first direction;
  • the reference signal lines 36 in the sub-pixels located in the same row along the first direction form an integrated structure;
  • the orthographic projections of line VDD on the substrate do not overlap.
  • the multiple repeating units are distributed in an array, the multiple repeating units are divided into multiple repeating unit columns, and each repeating unit column includes multiple repeating units arranged along the second direction.
  • the power line VDD includes at least a portion extending along the second direction.
  • the orthographic projection of the repeating unit array on the substrate is located between the orthographic projections of adjacent power lines VDD on the substrate.
  • the repeating unit further includes a reference signal bus 63, and the reference signal bus 63 includes at least a portion extending along the second direction.
  • the reference signal bus 63 is coupled to the reference signal line 36 in the repeating unit.
  • the repeating unit includes two rows and six columns of sub-pixels distributed in an array.
  • the reference signal line 36 in each row of sub-pixels is formed as an integral structure, and is coupled with the reference signal bus 63 through a via hole.
  • the six columns of sub-pixels are divided into two groups of sub-pixels, each group of sub-pixels includes three columns of sub-pixels, and the orthographic projection of the reference signal bus 63 on the substrate is located between the orthographic projections of the two groups of sub-pixels on the substrate .
  • the reference signal buses 63 included in the repeating unit column of the same column are sequentially coupled to form an integrated structure.
  • the reference signal lines 36 arranged in the sub-pixels in the same row along the first direction are formed as an integral structure, and are coupled with the reference signal bus 63, so that the reference signal bus 63 can serve as the reference signal line 36.
  • the signal line 36 provides a reference signal to ensure the normal operation of the display substrate.
  • the above setting of the orthographic projection of the reference signal line 36 on the substrate does not overlap with the orthographic projection of the power supply line VDD on the substrate, which reduces the occurrence of the reference signal line 36 and the power supply line VDD. risk of short circuit.
  • the sub-pixel further includes a third scan line 43 and an initialization signal line 51;
  • the sub-pixel driving circuit further includes a third transistor T3, the gate of the third transistor T3 is coupled to the third scanning line 43 , the first electrode of the third transistor T3 is connected to the initialization signal line 51 Formed as an integral structure, the second pole of the third transistor T3 is coupled to the first pole of the driving transistor T5.
  • the third scan line 43 includes at least a portion extending along the first direction.
  • the third scan lines 43 in the same row of sub-pixels are sequentially coupled to form an integrated structure.
  • the initialization signal line 51 includes at least a portion extending along the first direction.
  • the initialization signal lines 51 in the same row of sub-pixels are sequentially coupled to form an integrated structure.
  • the third transistor T3 includes a double gate structure.
  • the orthographic projection of the first electrode of the third transistor T3 on the substrate and the orthographic projection of the initialization signal line 51 on the substrate are located at the position of the third scanning line 43 on the substrate. The same side of the orthographic projection.
  • the first electrode of the third transistor T3 and the initialization signal line 51 are set to form an integral structure, which can reduce the size of the first electrode of the third transistor T3 and the initialization signal line.
  • the distance between 51 reduces the layout space occupied by the sub-pixels and reduces the layout difficulty of the sub-pixels.
  • the first pole of the third transistor T3 is set to form an integral structure with the initialization signal line 51, so that the first pole of the third transistor T3 and the initialization signal line
  • the wires 51 can be formed simultaneously in the same process and realize coupling, which not only simplifies the manufacturing process flow of the display substrate, reduces the manufacturing cost, but also better ensures that the first electrode of the third transistor T3 and the The connection performance of the initialization signal line 51 improves the manufacturing yield of the display substrate.
  • the third transistor T3 includes a third active layer 33, and the third active layer 33 forms the third transistor T3
  • the third active layer 33 and the initialization signal line 51 form an integral structure.
  • the third active layer 33 includes an L-shaped structure.
  • the third active layer 33 is used to form the first pole, the second pole and the channel part of the third transistor T3.
  • the part of the third active layer 33 used to form the first pole of the third transistor T3 is formed into an integral structure with the initialization signal line 51 .
  • the above arrangement of the third active layer 33 and the initialization signal line 51 forms an integrated structure, which can reduce the distance between the third active layer 33 and the initialization signal line 51 and reduce the occupation of the sub-pixels.
  • the layout space reduces the difficulty of sub-pixel layout.
  • the initialization signal line 51 and the third active layer 33 can be simultaneously formed into an integrated structure in the same patterning process, which not only simplifies the manufacturing process of the display substrate, reduces the manufacturing cost, but also better ensures
  • the connection performance between the first electrode of the third transistor T3 and the initialization signal line 51 improves the manufacturing yield of the display substrate.
  • the initialization signal line 51 and the third active layer 33 are formed into an integral structure, so that the initialization signal line 51 and the third scanning line 43 are arranged in different layers, reducing the initialization signal line 51 The probability of short circuit with the third scan line 43 effectively improves the yield of the display substrate.
  • the initialization signal lines 51 in the sub-pixels located in the same row along the first direction are integrated Structure: the orthographic projection of the initialization signal line 51 on the substrate does not overlap with the orthographic projection of the power supply line VDD on the substrate.
  • the initialization signal lines 51 in the sub-pixels in the same row along the first direction are sequentially coupled to form an integrated structure.
  • the above setting of the orthographic projection of the initialization signal line 51 on the substrate does not overlap with the orthographic projection of the power supply line VDD on the substrate can reduce the occurrence of the initialization signal line 51 and the power supply line VDD. risk of short circuit.
  • the repeating unit includes an initialization signal bus 50, the initialization signal bus 50 At least partially extending along a second direction, the second direction intersects with the first direction; the initialization signal bus 50 is coupled to the initialization signal line 51 .
  • the repeating unit includes two rows and six columns of sub-pixels distributed in an array.
  • the initialization signal line 51 in each row of sub-pixels is formed as an integral structure, and is coupled with the initialization signal bus 50 through a via hole.
  • the six columns of sub-pixels are divided into two groups of sub-pixels, each group of sub-pixels includes three columns of sub-pixels, and the orthographic projection of the initialization signal bus 50 on the substrate is located between the orthographic projections of the two groups of sub-pixels on the substrate .
  • the initialization signal buses 50 included in the repeating unit column of the same column are sequentially coupled to form an integrated structure.
  • the initialization signal lines 51 arranged in the sub-pixels in the same row along the first direction are formed as an integral structure, and are coupled with the initialization signal bus 50, so as to achieve the initialization through the initialization signal bus 50.
  • the signal line 51 provides an initialization signal to ensure the normal operation of the display substrate.
  • the third transistor T3 includes a double-gate structure, the third transistor T3 includes a third active layer 33, and the third active layer 33 includes two a third channel portion 331, and a conductor portion 332 respectively coupled to the two third channel portions 331;
  • the repeating unit includes a plurality of second connection patterns 67, and in the repeating unit, along the first direction, the first poles of adjacent third transistors T3 are coupled through the second connection patterns 67 , or the conductor portion 332 of the adjacent third transistor T3 is coupled through the second connection pattern 67; the orthographic projection of the second connection pattern 67 on the substrate is located at the two coupled Part of the gates of adjacent third transistors T3 are between the orthographic projections on the substrate;
  • the repeating unit also includes an initialization signal bus 50, the initialization signal bus 50 extends along a second direction, the second direction intersects the first direction, the initialization signal bus 50 is connected to the second connection pattern 67 coupling.
  • the first poles of some adjacent third transistors T3 are coupled through the second connection pattern 67, and the other The conductor portions 332 of some adjacent third transistors T3 are coupled through the second connection pattern 67 .
  • the repeating unit includes two rows and six columns of sub-pixels distributed in an array. Take the first row of sub-pixels in the repeating unit as an example.
  • the first electrode of the third transistor T3 in the first sub-pixel is coupled to the first electrode of the third transistor T3 in the second sub-pixel through the second connection pattern 67 .
  • the conductor portion 332 of the third transistor T3 in the second sub-pixel is coupled to the conductor portion 332 of the third transistor T3 in the third sub-pixel through the second connection pattern 67 .
  • the first pole of the third transistor T3 in the third sub-pixel is coupled to the first pole of the third transistor T3 in the fourth sub-pixel through the second connection pattern 67 .
  • the conductor portion 332 of the third transistor T3 in the fourth sub-pixel is coupled to the conductor portion 332 of the third transistor T3 in the fifth sub-pixel through the second connection pattern 67 .
  • the first electrode of the third transistor T3 in the fifth sub-pixel is coupled to the first electrode of the third transistor T3 in the sixth sub-pixel through the second connection pattern 67 .
  • the initialization signal bus 50 is coupled to the second connection pattern 67 through a via hole.
  • the second connection pattern 67 between the third transistor T3 in the third sub-pixel and the third transistor T3 in the fourth sub-pixel is coupled to the initialization signal bus 50 through a via hole. catch.
  • the first poles of the adjacent third transistors T3 are coupled through the second connection pattern 67, or the adjacent third transistors T3
  • the conductor part 332 is coupled through the second connection pattern 67; so that in the repeating unit, the third transistors T3 located in the same row along the first direction are connected in series, and the third transistor T3 on the third scanning line 43 can be connected in series. All are turned on when a valid scanning signal is provided, and the initialization signal provided by the initialization signal bus 50 is transmitted to the corresponding sub-pixel.
  • the third active layer 33 includes an L-shaped structure
  • the gate of the third transistor T3 includes a first gate pattern and a second gate pattern
  • a part of the third scanning line 43 is multiplexed is the first gate pattern
  • the second gate pattern and the third scanning line 43 form an integral structure
  • the second gate pattern is located on the third scanning pattern along the second direction side.
  • the orthographic projection of the first grid pattern on the substrate and the orthographic projection of the second grid pattern on the substrate are respectively the same as the orthographic projection of the third active layer 33 on the substrate overlap at least partially.
  • the orthographic projection of the second connection pattern 67 on the substrate is located between the orthographic projections of the second gate patterns of the two adjacent third transistors T3 coupled to it on the substrate .
  • the above setting of the orthographic projection of the second connection pattern 67 on the substrate is located between the orthographic projections of the partial gates of the two adjacent third transistors T3 coupled to it on the substrate, which is conducive to reducing the
  • the layout space occupied by the sub-pixels reduces the layout difficulty of the display substrate, which is beneficial to the realization of high resolution of the display substrate.
  • the first pole of the third transistor T3 or the conductor portion 332 to which the second connection pattern 67 is coupled is formed as an integral structure.
  • the above arrangement enables the second connection pattern 67 and the first electrode of the third transistor T3 to be formed in the same patterning process, which not only simplifies the manufacturing process of the display substrate, but also reduces the manufacturing cost of the display substrate. Moreover, the above arrangement also improves the performance of the electrical connection between the second connection pattern 67 and the first electrode of the third transistor T3, ensuring the yield of the display substrate.
  • the third active layer 33 is set to include a U-shaped structure, and the orthographic projection of the third active layer 33 on the substrate is the same as that of the third active layer 33.
  • the orthographic projection of the scanning line 43 on the substrate has two overlapping regions; the two ends of the third active layer 33 located at the U-shaped opening are respectively coupled to the initialization signal line 51; A portion of the source layer 33 at the bottom of the U-shape is coupled to the first pole of the driving transistor T5.
  • the opening of the U-shaped structure faces the initialization signal line 51 coupled thereto.
  • the U-shaped structure and the initialization signal line 51 form an integral structure.
  • the third scanning lines 43 in the sub-pixels in the same row along the first direction are sequentially coupled to form an integrated strip structure extending along the first direction .
  • the above arrangement makes the third transistor T3 form a double-gate structure, and the third scan line 43 is multiplexed as the gate of the third transistor T3.
  • the above arrangement method is beneficial to reduce the layout space occupied by the sub-pixels, and is beneficial to realize high resolution of the display substrate.
  • the sub-pixel further includes an emission control line 44;
  • the sub-pixel driving circuit further includes a fourth transistor T4, the gate of the fourth transistor T4 is coupled to the light emission control line 44, and the first electrode of the fourth transistor T4 is coupled to the power supply line VDD. , the second pole of the fourth transistor T4 is coupled to the second pole of the driving transistor T5;
  • adjacent sub-pixel driving circuits along the second direction multiplex the same fourth transistor T4 and multiplex the same light emission control signal line.
  • the light emission control line 44 includes at least a portion extending along the first direction.
  • the fourth transistor T4 is used to control the driving transistor T5 to write a driving signal to the anode pattern 80, so as to control the light emitting condition of the light emitting element.
  • adjacent sub-pixel driving circuits along the second direction multiplex the same fourth transistor T4, and the multiplexed fourth transistor T4 is respectively driven by two of the adjacent sub-pixel driving circuits.
  • the transistors T5 are respectively coupled, and the multiplexed fourth transistor T4 respectively controls the two driving transistors T5 to write a driving signal to the corresponding anode pattern 80 .
  • the display substrate provided by the above embodiment by being arranged in the same repeating unit, adjacent sub-pixel driving circuits along the second direction multiplex the same fourth transistor T4 and multiplex the same light emission control signal line; The number of the fourth transistor T4 and the number of light-emitting control signal lines in the display substrate are reduced, and the layout space occupied by the repeating unit is effectively reduced. Therefore, the display substrate provided by the above embodiment optimizes the layout of multiple sub-pixels, not only It ensures that the display substrate can achieve high-resolution display, and is also better compatible with GOA (English: Gate On Array) logic resources.
  • GOA Gate On Array
  • the sub-pixel is set to include an anode pattern 80;
  • the fourth transistor T4 includes a fourth active layer 34, and the orthographic projection of the fourth active layer 34 on the substrate is located on the substrate where two adjacent anode patterns 80 along the second direction are located. between the orthographic projections on .
  • the fourth active layer 34 includes at least a portion extending along the first direction.
  • the orthographic projection of the light emission control signal line on the substrate is located between the orthographic projections of two adjacent anode patterns 80 along the second direction on the substrate.
  • the sub-pixel further includes a power connection part 45, which is arranged in a different layer from the fourth active layer 34, and the power connection part 45 is arranged in a different layer from the power line VDD.
  • the power supply connection part 45 is coupled to the first pole of the fourth transistor T4 through the second conductive pattern 65, and the power supply connection part 45 is coupled to the power supply line VDD through a via hole that runs through the power supply line VDD.
  • the above arrangement makes the fourth transistor T4 and the light emission control signal line roughly located between the two multiplexed sub-pixels, which not only ensures that the fourth transistor T4 and the light emission control signal line, but also the two
  • the good connection performance of the first driving transistor T5 also effectively reduces the layout difficulty of the light emission control signal line and the fourth transistor T4.
  • the driving transistor T5 includes a driving active layer 35;
  • the two driving active layers 35 included in the two driving transistors T5 are arranged axisymmetrically with respect to a first axis of symmetry, and the first axis of symmetry is along the second direction Extending, the orthographic projection of the first axis of symmetry on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two adjacent sub-pixels along the first direction on the substrate;
  • the two driving active layers 35 included in the two driving transistors T5 are arranged axisymmetrically with respect to the second symmetry axis X2, and the second symmetry axis X2 is arranged along the second axis of symmetry.
  • the orthographic projection of the second symmetry axis X2 on the substrate is located between the orthographic projections of the two anode patterns 80 included in the two adjacent sub-pixels along the second direction on the substrate .
  • the second pole of the driving transistor T5 is coupled to the second pole of the fourth transistor T4 through the first conductive pattern 64
  • the first electrode of the driving transistor T5 is coupled to the second plate Cst2 of the storage capacitor Cst, and is coupled to the anode pattern 80 through the second plate Cst2.
  • the first pole of the driving transistor T5 is arranged in a different layer from the second plate Cst2 of the storage capacitor Cst, and the first pole of the driving transistor T5 is connected to the second pole through the third conductive pattern 66 Board Cst2 is coupled.
  • the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the driving transistor T5.
  • the second pole plate Cst2 is also coupled to the second pole of the third transistor T3 through the first conductive connection portion 60 .
  • the first electrode of the third transistor T3 is coupled to the initialization signal line 51 through the fifth conductive pattern 68 .
  • the driving active layer 35 includes a U-shaped portion, and two end portions respectively extending from the two ends of the U-shaped portion.
  • the U-shaped portion is used to form a channel portion of the driving transistor T5, and the two ends serve as the first pole and the second pole of the driving transistor T5 respectively.
  • the gates included in the two driving transistors T5 are arranged symmetrically with respect to the first axis of symmetry.
  • the gates included in the two driving transistors T5 are arranged symmetrically with respect to the second symmetry axis X2.
  • the above-mentioned symmetrical setting method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • the second transistor T2 is set to include a second active layer 32;
  • the two second active layers 32 included in the two second transistors T2 are arranged axisymmetrically with respect to the first axis of symmetry;
  • the two second active layers 32 included in the two second transistors T2 are arranged axisymmetrically with respect to the second symmetry axis X2.
  • the second active layer 32 includes a portion extending along the first direction.
  • the width of the two ends of the second active layer 32 in the second direction is larger than the middle portion of the second active layer 32 between the two ends in the second direction.
  • the orthographic projection of the middle part of the second active layer 32 on the substrate at least partially overlaps the orthographic projection of the gate of the second transistor T2 on the substrate, and the second The middle part of the active layer 32 is used to form the channel region of the second transistor T2.
  • the above arrangement method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • the sub-pixel driving circuit is set to further include a first transistor T1, and the first transistor T1 includes a first active layer 31;
  • the two first active layers 31 included in the two first transistors T1 are arranged axisymmetrically with respect to the first axis of symmetry;
  • the two first active layers 31 included in the two first transistors T1 are arranged axisymmetrically with respect to the second symmetry axis X2.
  • the first active layer 31 includes a portion extending along the first direction.
  • the width of the two ends of the first active layer 31 in the second direction is larger than the width of the middle part of the first active layer 31 between the two ends in the second direction.
  • the orthographic projection of the middle part of the first active layer 31 on the substrate at least partially overlaps the orthographic projection of the gate of the first transistor T1 on the substrate, and the first The middle part of the active layer 31 is used to form the channel region of the first transistor T1.
  • the above arrangement method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • the sub-pixel driving circuit further includes a third transistor T3, and the third transistor T3 includes a third active layer 33;
  • the two third active layers 33 included in the two third transistors T3 are arranged axisymmetrically with respect to the first axis of symmetry;
  • the two third active layers 33 included in the two third transistors T3 are arranged axisymmetrically with respect to the second symmetry axis X2.
  • the sub-pixel driving circuit further includes a fourth transistor T4, and the fourth transistor T4 includes a fourth active layer 34;
  • the two fourth active layers 34 included in the two fourth transistors T4 are arranged axisymmetrically with respect to the first axis of symmetry.
  • the above arrangement method effectively reduces the layout space occupied by the sub-pixels, which is beneficial for the display substrate to achieve high display resolution.
  • FIG. 5 for the schematic diagram of the first gate metal layer
  • FIG. 8 for the schematic diagram of the second source-drain metal layer
  • FIG. 9 for the schematic diagram of the layout of the openings formed by the pixel defining layer.
  • FIG. 13 for a schematic layout of the anode layer and the second source-drain metal layer.
  • FIG. 5 for the schematic diagram of the first gate metal layer
  • Fig. 18 for the schematic diagram of the second gate metal layer
  • Fig. 19 for the layout diagram of the first source-drain metal layer
  • FIG. 8 for a schematic diagram of the metal layer
  • FIG. 9 for a schematic layout of the openings formed by the pixel defining layer
  • FIG. 13 for a schematic layout of the anode layer and the second source-drain metal layer.
  • FIG. 18 for the schematic diagram of the second gate metal layer
  • Fig. 19 for the schematic diagram of the layout of the first source-drain metal layer
  • Fig. 8 for the schematic diagram of the second source-drain metal layer
  • pixel defining layer Refer to FIG. 9 for a schematic layout of the formed openings
  • FIG. 13 for a schematic layout of the anode layer and the second source-drain metal layer.
  • the display substrate includes a buffer layer Buf, an active layer Poly, a first gate insulating layer GI1, a first gate metal layer Gat1, and The second gate insulating layer GI2, the second gate metal layer Gat2, the interlayer insulating layer ILD, the first source-drain metal layer SD1, the first passivation layer PVX1, the first planar layer PLN1, the second source-drain metal layer SD2, The second passivation layer PVX2, the second planar layer PLN2, the anode layer (including the anode pattern 80), the pixel definition layer PDL, the light emitting function layer, the cathode layer, and the packaging structure.
  • the display substrate may not include the first passivation layer PVX1 and/or the second passivation layer PVX2.
  • the display substrate is formed through 12 patterning processes (Mask process), specifically including: patterning process of the active layer, patterning process of the first gate metal layer, patterning process of the second gate metal layer, interlayer insulation Layer patterning process, patterning process of the first source-drain metal layer, patterning process of the first flat layer, patterning process of the first passivation layer, patterning process of the second source-drain metal layer, patterning process of the second flat layer, The patterning process of the second passivation layer, the patterning process of the anode layer and the patterning process of the pixel defining layer.
  • Mask process patterning processes
  • the pixel defining layer forms a pixel opening 81 .
  • the pixel opening 81 is designed for equal-pitch arc printing, which can increase the printing rate for making organic light-emitting materials, and can improve the device performance of the display substrate.
  • the two first conductive connecting parts 60 are symmetrical about the second symmetry axis X2, and the two The first conductive pattern 64 is symmetrical about the second axis of symmetry X2, the two third conductive patterns 66 are symmetrical about the second axis of symmetry X2, and the two fifth conductive patterns 68 are symmetrical about the second axis of symmetry.
  • the axis X2 is symmetrical, the two anode patterns are symmetrical about the second symmetrical axis X2, and the two pixel openings 81 are symmetrical about the second symmetrical axis X2.
  • the two first connection figures 61 are symmetrical about the second axis of symmetry X2.
  • the two first pole plates Cst1 are symmetrical about the second axis of symmetry X2
  • the two second pole plates Cst2 are symmetrical about the second axis of symmetry X2
  • the two first active layers 31 are symmetrical about the second axis of symmetry X2.
  • the second symmetry axis X2 is symmetrical, the two second active layers 32 are symmetrical about the second symmetry axis X2, the two third active layers 33 are symmetrical about the second symmetry axis X2, and the two The fourth active layer 34 is symmetrical about the second axis of symmetry X2, and the two driving active layers 35 are symmetrical about the second axis of symmetry X2.
  • the two first conductive connecting parts 60 are symmetrical about the first axis of symmetry, and the two first The conductive pattern 64 is symmetrical about the first axis of symmetry, the two second conductive patterns 65 are symmetrical about the first axis of symmetry, the two third conductive patterns 66 are symmetrical about the first axis of symmetry, and the two conductive patterns 65 are symmetrical about the first axis of symmetry.
  • the fifth conductive pattern 68 is symmetrical about the first axis of symmetry, the two anode patterns are symmetrical about the first axis of symmetry, the two pixel openings 81 are symmetrical about the first axis of symmetry, and the two anode patterns are symmetrical about the first axis of symmetry.
  • the first pole plate Cst1 is symmetrical about the first axis of symmetry, the two second pole plates Cst2 are symmetrical about the first axis of symmetry, and the two first active layers 31 are symmetrical about the first axis of symmetry.
  • the two first connecting figures 61 are symmetrical about the first axis of symmetry.
  • the sub-pixel further includes a first conductive connection portion 60 and a second conductive connection portion 70 arranged in different layers, and the first conductive connection portion
  • the connection part 60 is located between the base and the second conductive connection part 70, and the anode pattern 80 is located on the side of the second conductive connection part 70 facing away from the base;
  • the second pole plate Cst2 is coupled to the first conductive connection part 60;
  • the second conductive connection part 70 is coupled to the first conductive connection part 60 through a first via hole, and the orthographic projection of the first via hole on the substrate 10 is located in the first overlapping region;
  • the second conductive connection portion 70 is coupled to the anode pattern 80 through a second via hole, and the orthographic projection of the second via hole on the substrate 10 is located in the second overlapping region.
  • the sub-pixel driving circuit includes a driving transistor T5, a fourth transistor T4, a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst .
  • the working processes of the sub-pixels in the first row and the sub-pixels in the second row of the two adjacent sub-pixels along the second direction include: a reset period P1, a compensation period P2, a data writing period P3 and a light-emitting period P4.
  • the reset periods of the first row of subpixels and the second row of subpixels are staggered, the compensation periods of the first row of subpixels and the second row of subpixels are partially staggered, and the data writing periods of the first row of subpixels and the second row of subpixels are completely stagger.
  • the light emission control signal EM is at an inactive level, which can prevent the first row of The first pole of the driving transistor T5 of the sub-pixel continuously receives the power signal Vd, which prevents the gate-source voltage drop of the driving transistor T5 of the sub-pixel in the first row, which affects the compensation effect of the sub-pixel driving circuit in the first sub-pixel.
  • FIG. 1 schematically shows the light emitting element EL, the negative power supply signal VSS provided by the cathode layer, and the reference signal Vref provided by the reference signal line 63 .
  • the initialization signal Vinit provided by the initialization signal bus 50 .
  • the power signal Vd provided by the power line VDD.
  • the light emission control signal EM provided by the light emission control line 44 .
  • FIG. 2 shows the first scan signal G11 input from the first scan line 41, the second scan signal G21 input from the second scan line 42, and the third scan signal input from the third scan line 43 in the first row of sub-pixels.
  • FIG. 2 also shows the first scan signal G12 input from the first scan line 41, the second scan signal G22 input from the second scan line 42, and the third scan signal G22 input from the third scan line 43 in the second row of sub-pixels.
  • Signal G32 is the first scan signal G11 input from the first scan line 41, the second scan signal G21 input from the second scan line 42, and the third scan signal input from the third scan line 43 in the first row of sub-pixels.
  • Embodiments of the present disclosure also provide a display device, including the display substrate provided in the above embodiments.
  • the first electrode of the second transistor T2 and the reference signal line 36 are set to form an integral structure, which can reduce the size of the first electrode of the second transistor T2 and the reference signal line. 36, reducing the layout space occupied by the sub-pixels and reducing the difficulty of sub-pixel layout. Moreover, there is no need to arrange other transfer patterns to connect the electrical connection between the first pole of the second transistor T2 and the reference signal line 36 , which further reduces the layout difficulty of the display substrate.
  • the first pole of the second transistor T2 is set to form an integral structure with the reference signal line 36, so that the first pole of the second transistor T2 and the reference signal line
  • the lines 36 can be formed simultaneously in the same process and realize the coupling, which not only simplifies the manufacturing process flow of the display substrate and reduces the manufacturing cost, but also better ensures that the first electrode of the second transistor T2 and the The connection performance of the reference signal line 36 improves the manufacturing yield of the display substrate.
  • the display device provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a back panel. board etc.
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

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Abstract

一种显示基板和显示装置。显示基板包括基底，设置于基底上的多个子像素，多个子像素呈阵列分布。子像素包括：基准信号线（36）和第二扫描线（42）；以及，子像素驱动电路，子像素驱动电路包括驱动晶体管（T5）和第二晶体管（T2），第二晶体管（T2）的栅极与第二扫描线（42）耦接，第二晶体管（T2）的第一极与基准信号线（36）形成为一体结构，第二晶体管（T2）的第二极与驱动晶体管（T5）的栅极耦接，从而能够降低子像素占用的布局空间，减低了子像素的布局难度。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示产品是通过借助电子与空穴直接的复合，激发出各种波长的光谱，从而形成图像。OLED显示产品具有响应速度快，对比度最大化等优点，有望成为下一代显示主流产品。
OLED显示产品包括：显示面板、栅极驱动装置、数据驱动器和时序控制器。显示面板包括：数据线、栅线和像素。通常工作方式为：栅极驱动装置向栅线提供栅极驱动信号，当栅极驱动信号被提供至栅线时，对应的一行像素则被写入数据线传输的数据电压。像素根据数据电压的大小发出不同亮度的光，实现显示功能。
发明内容
本公开的目的在于提供一种显示基板和显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：基底，设置于所述基底上的多个子像素，所述多个子像素呈阵列分布；所述子像素包括：
基准信号线和第二扫描线；以及，
子像素驱动电路，所述子像素驱动电路包括驱动晶体管和第二晶体管，所述第二晶体管的栅极与所述第二扫描线耦接，所述第二晶体管的第一极与所述基准信号线形成为一体结构，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接。
可选的，所述第二晶体管包括第二有源层，所述第二有源层形成所述第二晶体管的第一极和第二极，所述基准信号线的至少部分沿第一方向延伸； 所述第二有源层的至少部分沿所述第一方向延伸；所述第二扫描线的至少部分沿所述第一方向延伸；所述第二有源层在所述基底上的正投影的至少部分，位于所述基准信号线在所述基底上的正投影和所述第二扫描线在所述基底上的正投影之间。
可选的，所述子像素还包括第一扫描线，数据线和第一连接图形；所述子像素驱动电路还包括第一晶体管；
所述第一晶体管的栅极与所述第一扫描线耦接，所述第一晶体管的第一极与所述数据线耦接，所述第一晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第一连接图形分别与所述第一晶体管的第二极和所述第二晶体管的第二极耦接，所述第一连接图形在所述基底上的正投影，分别与所述第一扫描线在所述基底上的正投影和所述第二扫描线在所述基底上的正投影部分交叠。
可选的，所述多个子像素划分为多个重复单元，所述多个重复单元划分为多列重复单元列；所述显示基板还包括多条电源线，所述电源线与所述重复单元列沿所述第一方向交替设置；
在每个重复单元中，沿所述第一方向位于同一行的各子像素中的基准信号线形成为一体结构；所述基准信号线在所述基底上的正投影，与所述电源线在所述基底上的正投影不交叠。
可选的，所述子像素还包括第三扫描线和初始化信号线；
所述子像素驱动电路还包括第三晶体管，所述第三晶体管的栅极与所述第三扫描线耦接，所述第三晶体管的第一极与所述初始化信号线形成为一体结构，所述第三晶体管的第二极与所述驱动晶体管的第一极耦接。
可选的，在每个重复单元中，沿所述第一方向位于同一行的各子像素中的初始化信号线形成为一体结构；所述初始化信号线在所述基底上的正投影，与所述电源线在所述基底上的正投影不交叠。
可选的，所述重复单元包括初始化信号总线，所述初始化信号总线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；所述初始化信号总线与所述初始化信号线耦接。
可选的，所述第三晶体管包括双栅结构，所述第三晶体管包括第三有源层，所述第三有源层包括两个第三沟道部分，以及与所述两个第三沟道部分分别耦接的导体部分；
所述重复单元中包括多个第二连接图形，在所述重复单元中，沿所述第一方向，相邻的第三晶体管的第一极通过所述第二连接图形相耦接，或者相邻的第三晶体管的所述导体部分通过所述第二连接图形相耦接；所述第二连接图形在所述基底上的正投影，位于其耦接的两个相邻的第三晶体管的部分栅极在所述基底上的正投影之间；
所述重复单元还包括初始化信号总线，所述初始化信号总线沿第二方向延伸，所述第二方向与所述第一方向相交，所述初始化信号总线与所述第二连接图形耦接。
可选的，所述第二连接图形与其耦接的所述第三晶体管的第一极或者所述导体部分形成为一体结构。
可选的，所述第三有源层包括U型结构，所述第三有源层在所述基底上的正投影与所述第三扫描线在所述基底上的正投影具有两个交叠区；所述第三有源层位于U型开口处的两端与所述初始化信号线分别耦接；所述第三有源层位于U型底部的部分与驱动晶体管的第一极耦接。
可选的，所述子像素还包括发光控制线；
所述子像素驱动电路还包括第四晶体管，所述第四晶体管的栅极与所述发光控制线耦接，所述第四晶体管的第一极与所述电源线耦接，所述第四晶体管的第二极与所述驱动晶体管的第二极耦接；
在同一个重复单元中，沿第二方向相邻的子像素驱动电路复用同一个所述第四晶体管，且复用同一条发光控制信号线。
可选的，所述子像素包括阳极图形；
所述第四晶体管包括第四有源层，所述第四有源层在所述基底上的正投影，位于沿所述第二方向相邻的两个阳极图形在所述基底上的正投影之间。
可选的，所述驱动晶体管包括驱动有源层；
沿第一方向相邻的两个子像素中，两个所述驱动晶体管包括的两个所述驱动有源层关于第一对称轴呈轴对称设置，所述第一对称轴沿第二方向延伸， 所述第一对称轴在所述基底上的正投影，位于所述沿第一方向相邻的两个子像素包括的两个阳极图形在所述基底上的正投影之间；
沿第二方向相邻的两个子像素中，两个所述驱动晶体管包括的两个所述驱动有源层关于第二对称轴呈轴对称设置，所述第二对称轴沿第一方向延伸，所述第二对称轴在所述基底上的正投影，位于所述沿第二方向相邻的两个子像素包括的两个阳极图形在所述基底上的正投影之间。
可选的，所述第二晶体管包括第二有源层；
沿第一方向相邻的两个子像素中，两个所述第二晶体管包括的两个所述第二有源层关于所述第一对称轴呈轴对称设置；
沿第二方向相邻的两个子像素中，两个所述第二晶体管包括的两个所述第二有源层关于所述第二对称轴呈轴对称设置。
可选的，所述子像素驱动电路还包括第一晶体管，所述第一晶体管包括第一有源层；
沿第一方向相邻的两个子像素中，两个所述第一晶体管包括的两个所述第一有源层关于所述第一对称轴呈轴对称设置；
沿第二方向相邻的两个子像素中，两个所述第一晶体管包括的两个所述第一有源层关于所述第二对称轴呈轴对称设置。
可选的，所述子像素驱动电路还包括第三晶体管，所述第三晶体管包括第三有源层；
沿第一方向相邻的两个子像素中，两个所述第三晶体管包括的两个所述第三有源层关于所述第一对称轴呈轴对称设置；
沿第二方向相邻的两个子像素中，两个所述第三晶体管包括的两个所述第三有源层关于所述第二对称轴呈轴对称设置。
可选的，所述子像素驱动电路还包括第四晶体管，所述第四晶体管包括第四有源层；
沿第一方向相邻的两个子像素中，两个所述第四晶体管包括的两个所述第四有源层关于所述第一对称轴呈轴对称设置。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的显示基板中最小重复单元对应的电路图；
图2为本公开实施例提供的沿第二方向相邻两个子像素驱动电路的驱动时序图；
图3为图1中电路图对应的第一布局示意图；
图4为图3中有源层的示意图；
图5为图3中第一栅金属层的布局示意图；
图6为图3中第二栅金属层的布局示意图；
图7为图3中第一源漏金属层的布局示意图；
图8为图3中第二源漏金属层的布局示意图；
图9为图3中像素界定层形成的开口的布局示意图；
图10为图3中有源层和第一栅金属层的布局示意图；
图11为图3中有源层和第二栅金属层和第一源漏金属层的布局示意图；
图12为图3中第一源漏金属层和第二源漏金属层的布局示意图；
图13为本公开实施例提供的阳极层和第二源漏金属层的布局示意图；
图14为在图10中增加第二栅金属层和第一源漏金属层的布局示意图；
图15为在图14中增加第二源漏金属层和阳极层的布局示意图；
图16为图1中电路图对应的第二布局示意图；
图17为图16中有源层的示意图；
图18为图16中第二栅金属层的布局示意图；
图19为图16中第一源漏金属层的布局示意图；
图20为图16中有源层和第一栅金属层的布局示意图；
图21为图16中有源层和第二栅金属层和第一源漏金属层的布局示意图；
图22为图16中第一源漏金属层和第二源漏金属层的布局示意图；
图23为图1中电路图对应的第三布局示意图；
图24为图23中有源层的示意图；
图25为图23中有源层和第一栅金属层的布局示意图；
图26为图1中电路图对应的第四布局示意图；
图27为图26中有源层的示意图；
图28为图26中第一栅金属层的布局示意图；
图29为本公开实施例提供的显示基板的部分截面示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板和显示装置，下面结合说明书附图进行详细描述。
随着显示技术的不断发展，人们对显示产品的显示质量要求不断提升。为了实现高质量显示，高分辨率显示产品越来越受到人们关注。而显示产品的布局空间有限，实现高分辨率会增加子像素的布局难度，不利于显示产品的制作良率。
如图3，图4，图5，图10，图11，图14至图28所示，本公开实施例提供了一种显示基板，包括：基底，设置于所述基底上的多个子像素，所述多个子像素呈阵列分布；所述子像素包括：
基准信号线36和第二扫描线42；以及，
子像素驱动电路，所述子像素驱动电路包括驱动晶体管T5和第二晶体管T2，所述第二晶体管T2的栅极与所述第二扫描线42耦接，所述第二晶体管T2的第一极与所述基准信号线36形成为一体结构，所述第二晶体管T2的第二极与所述驱动晶体管T5的栅极耦接。
示例性的，所述显示基板包括显示区域和包围所述显示区域的周边区域。所述显示基板包括多个子像素，所述多个子像素呈阵列分布在所述显示区域。
示例性的，所述子像素包括子像素驱动电路和发光元件，所述子像素驱动电路与所述发光元件耦接，用于为所述发光元件提供驱动信号，以实现驱动发光元件发光。示例性的，所述子像素驱动电路包括5T1C电路结构，即包括5个薄膜晶体管和一个存储电容。示例性的，所述发光元件包括沿远离所述基底的方向依次层叠设置的阳极图形，发光功能层和阴极层；所述发光功 能层包括层叠设置的电子注入层，电子传输层，有机发光材料层，空穴传输层和空穴注入层。示例性的，所述阴极层接收负电源信号VSS。
示例性的，所述多个子像素中，各子像素包括的电子注入层形成为一体结构，能够覆盖整个所述显示区域；同样的，各子像素包括的所述电子传输层，所述空穴传输层和所述空穴注入层也均可以形成为一体结构，能够覆盖整个所述显示区域。示例性的，所述多个子像素中，各子像素包括的阴极层形成为一体结构，能够覆盖整个所述显示区域。
示例性的，所述基准信号线36的至少部分沿第一方向延伸。所述第二扫描线42的至少部分沿所述第一方向延伸。
示例性的，沿所述第一方向位于同一行的子像素中的第二扫描线42依次耦接，形成为一体结构。
示例性的，所述驱动晶体管T5的栅极与所述第二晶体管T2的第二极耦接，所述驱动晶体管T5的第一极与发光元件耦接。
示例性的，所述第二晶体管T2包括双栅晶体管，所述第二晶体管T2的两个栅极与所述第二扫描线42形成为一体结构。所述两个栅极沿所述第一方向排列。所述第二晶体管T2的第一极与所述基准信号线36形成为一体结构。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，设置所述第二晶体管T2的第一极与所述基准信号线36形成为一体结构，可以缩小所述第二晶体管T2的第一极与所述基准信号线36之间的距离，降低所述子像素占用的布局空间，降低了子像素的布局难度。而且无需设置其他转接图形来连接所述第二晶体管T2的第一极和所述基准信号线36之间的电连接，进一步降低了显示基板的布局难度。
另外，本公开实施例提供的显示基板中，设置所述第二晶体管T2的第一极与所述基准信号线36形成为一体结构，使得所述第二晶体管T2的第一极和所述基准信号线36能够在同一次工艺中同时形成，且实现耦接，这样不仅简化了显示基板的制作工艺流程，降低制作成本，还更好的保证了所述第二晶体管T2的第一极和所述基准信号线36的连接性能，提升了显示基板的制作良率。
如图3，图4，图5，图10，图11，图14至图28所示，在一些实施例 中，设置所述第二晶体管T2包括第二有源层32，所述第二有源层32形成所述第二晶体管T2的第一极和第二极，所述基准信号线36的至少部分沿第一方向延伸；所述第二有源层32的至少部分沿所述第一方向延伸；所述第二扫描线42的至少部分沿所述第一方向延伸；所述第二有源层32在所述基底上的正投影的至少部分，位于所述基准信号线36在所述基底上的正投影和所述第二扫描线42在所述基底上的正投影之间。
如图3，图4，图5，图10，图11，图14至图28所示，在一些实施例中，设置所述第二晶体管T2包括第二有源层32，所述第二有源层32形成所述第二晶体管T2的第一极和第二极，所述第二有源层32与所述基准信号线36形成为一体结构。
示例性的，所述第二有源层32包括沿所述第一方向延伸的至少部分。
示例性的，所述第二有源层32用于形成所述第二晶体管T2的第一极，第二极，以及所述第二晶体管T2的沟道部分。
示例性的，所述基准信号线36与所述第二有源层32同层同材料制作，能够在同一次构图工艺中同时形成为一体结构。
示例性的，所述第二有源层32与所述基准信号线36沿第二方向排列，所述第二方向与所述第一方向相交。示例性的，所述第一方向包括横向，所述第二方向包括纵向。
上述设置方式可以缩小所述第二有源层32与所述基准信号线36之间的距离，降低所述子像素占用的布局空间，降低了子像素的布局难度。而且无需设置其他转接图形来实现所述第二晶体管T2的第一极和所述基准信号线36之间的电连接，进一步降低了显示基板的布局难度。
另外，所述基准信号线36与所述第二有源层32能够在同一次构图工艺中同时形成为一体结构，不仅简化了显示基板的制作工艺流程，降低制作成本，还更好的保证了所述第二晶体管T2的第一极和所述基准信号线36的连接性能，提升了显示基板的制作良率。
此外，将所述基准信号线36与所述第二有源层32形成为一体结构，使得所述基准信号线36与所述第二扫描线42异层设置，降低了所述基准信号线36与所述第二扫描线42发生短路的概率，有效提升了显示基板的良率。
如图3，图4，图5，图10，图11，图14至图28所示，在一些实施例中，设置所述基准信号线36的至少部分沿第一方向延伸；所述第二有源层32的至少部分沿所述第一方向延伸；所述第二扫描线42的至少部分沿所述第一方向延伸；所述第二有源层32在所述基底上的正投影的至少部分，位于所述基准信号线36在所述基底上的正投影和所述第二扫描线42在所述基底上的正投影之间。
示例性的，所述第二晶体管T2的两个栅极在所述基底上的正投影，位于所述基准信号线36在所述基底上的正投影和所述第二扫描线42在所述基底上的正投影之间。
上述设置方式使得所述第二晶体管T2的栅极靠近所述第二扫描线42，所述第二有源层32靠近所述基准信号线36，有利于所述第二晶体管T2的栅极与所述第二扫描线42形成为一体结构，同时有利于所述第二有源层32与所述基准信号线36形成为一体结构。而且，上述设置方式能够将所述第二晶体管T2，所述基准信号线36和所述第二扫描线42占用的布局空间最小化，有利于降低显示基板的布局难度。
如图3，图4，图5，图7，图10，图11，图14至图28所示，在一些实施例中，所述子像素还包括第一扫描线41，数据线62和第一连接图形61；所述子像素驱动电路还包括第一晶体管T1；
所述第一晶体管T1的栅极与所述第一扫描线41耦接，所述第一晶体管T1的第一极与所述数据线62耦接，所述第一晶体管T1的第二极与所述驱动晶体管T5的栅极耦接；
所述第一连接图形61分别与所述第一晶体管T1的第二极和所述第二晶体管T2的第二极耦接，所述第一连接图形61在所述基底上的正投影，分别与所述第一扫描线41在所述基底上的正投影和所述第二扫描线42在所述基底上的正投影部分交叠。
示例性的，所述第一扫描线41包括沿所述第一方向延伸的至少部分。沿所述第一方向位于同一行的子像素中的第一扫描线41依次耦接，形成为一体结构。
示例性的，所述数据线62包括沿所述第二方向延伸的至少部分，沿所述 第二方向位于同一列的子像素中的数据线62依次耦接，形成为一体结构。
如图7，图14和图15所示，示例性的，每个重复单元包括四个像素单元，每个像素单元包括沿所述第一方向排列的第一子像素，第二子像素和第三子像素。第一子像素耦接第一数据线621，第二子像素耦接第二数据线622，第三子像素耦接第三数据线623。
示例性的，所述第一子像素，所述第二子像素和所述第三子像素的颜色各不相同。示例性的，所述第一子像素包括红色子像素，所述第二子像素包括绿色子像素，所述第三子像素包括蓝色子像素。需要说明，图1中示意了红色子像素接收的红色数据信号DATAR1和DATAR2，绿色子像素接收的绿色数据信号DATAG1和DATAG2，蓝色子像素接收的蓝色数据信号DATAB1和DATAB2。
示例性的，所述第一晶体管T1包括双栅结构，所述第一晶体管T1的两个栅极沿所述第一方向排列，所述两个栅极与所述第一扫描线41形成为一体结构。所述第一晶体管T1包括第一有源层31，所述第一有源层31包括沿所述第一方向延伸的至少部分。所述第一有源层31在所述基底上的正投影，与所述两个栅极在所述基底上的正投影至少部分交叠。所述第一有源层31形成所述第一晶体管T1的第一极和第二极，以及所述第一晶体管T1的沟道部分。
示例性的，沿所述第二方向，所述基准信号线36在所述基底上的正投影，所述第二有源层32在所述基底上的正投影，所述第二扫描线42在所述基底上的正投影，所述第一扫描线41在所述基底上的正投影，以及所述第一有源层31在所述基底上的正投影依次排列。
示例性的，所述第一连接图形61包括沿所述第二方向延伸的至少部分。所述第一连接图形61与所述第一晶体管T1的第二极通过过孔耦接，所述第一连接图形61与所述第二晶体管T2的第二极通过过孔耦接，所述第一连接图形61与所述驱动晶体管T5的栅极通过过孔耦接。
示例性的，所述第一连接图形61采用显示基板中的第一源漏金属层制作。
按照上述方式布局所述第一晶体管T1，所述第二晶体管T2，所述第一扫描线41和所述第二扫描线42，有利于缩小所述子像素占用的布局空间，降 低所述子像素的布局难度，同时有利于提升所述显示基板的良率。
如图3，图4，图7，图10，图11，图14至图28所示，在一些实施例中，所述多个子像素划分为多个重复单元，所述多个重复单元划分为多列重复单元列；所述显示基板还包括多条电源线VDD，所述电源线VDD与所述重复单元列沿所述第一方向交替设置；
在每个重复单元中，沿所述第一方向位于同一行的各子像素中的基准信号线36形成为一体结构；所述基准信号线36在所述基底上的正投影，与所述电源线VDD在所述基底上的正投影不交叠。
示例性的，所述多个重复单元呈阵列分布，所述多个重复单元划分为多列重复单元列，每列重复单元列包括沿所述第二方向排列的多个重复单元。
示例性的，所述电源线VDD包括沿所述第二方向延伸的至少部分。示例性的，所述重复单元列在所述基底上的正投影，位于相邻的电源线VDD在所述基底上的正投影之间。
示例性的，所述重复单元还包括基准信号总线63，所述基准信号总线63包括沿所述第二方向延伸的至少部分。所述基准信号总线63与所述重复单元中的基准信号线36耦接。
示例性的，所述重复单元包括呈阵列分布的两行六列子像素。该两行子像素中，每行子像素中的基准信号线36均形成为一体结构，且与所述基准信号总线63通过过孔耦接。该六列子像素划分为两组子像素，每组子像素包括三列子像素，所述基准信号总线63在所述基底上的正投影，位于两组子像素在所述基底上的正投影之间。
示例性的，同一列重复单元列中包括的各基准信号总线63依次耦接，形成为一体结构。
上述设置沿所述第一方向位于同一行的各子像素中的基准信号线36形成为一体结构，且与所述基准信号总线63耦接，实现了通过所述基准信号总线63为所述基准信号线36提供基准信号，保证了显示基板的正常工作。
上述设置所述基准信号线36在所述基底上的正投影，与所述电源线VDD在所述基底上的正投影不交叠，降低了所述基准信号线36与所述电源线VDD发生短路的风险。
如图16至图22，图26至图28所示，在一些实施例中，所述子像素还包括第三扫描线43和初始化信号线51；
所述子像素驱动电路还包括第三晶体管T3，所述第三晶体管T3的栅极与所述第三扫描线43耦接，所述第三晶体管T3的第一极与所述初始化信号线51形成为一体结构，所述第三晶体管T3的第二极与所述驱动晶体管T5的第一极耦接。
示例性的，所述第三扫描线43包括沿所述第一方向延伸的至少部分。同一行子像素中的各第三扫描线43依次耦接，形成为一体结构。
示例性的，所述初始化信号线51包括沿所述第一方向延伸的至少部分。同一行子像素中的各初始化信号线51依次耦接，形成为一体结构。
示例性的，所述第三晶体管T3包括双栅结构。所述第三晶体管T3的第一极在所述基底上的正投影，以及所述初始化信号线51在所述基底上的正投影，均位于所述第三扫描线43在所述基底上的正投影的同一侧。
上述实施例提供的显示基板中，设置所述第三晶体管T3的第一极与所述初始化信号线51形成为一体结构，可以缩小所述第三晶体管T3的第一极与所述初始化信号线51之间的距离，降低所述子像素占用的布局空间，降低了子像素的布局难度。而且无需设置其他转接图形来连接所述第三晶体管T3的第一极和所述初始化信号线51之间的电连接，进一步降低了显示基板的布局难度。
另外，上述实施例提供的显示基板中，设置所述第三晶体管T3的第一极与所述初始化信号线51形成为一体结构，使得所述第三晶体管T3的第一极和所述初始化信号线51能够在同一次工艺中同时形成，且实现耦接，这样不仅简化了显示基板的制作工艺流程，降低制作成本，还更好的保证了所述第三晶体管T3的第一极和所述初始化信号线51的连接性能，提升了显示基板的制作良率。
如图16至图28，图26至图28所示，在一些实施例中，所述第三晶体管T3包括第三有源层33，所述第三有源层33形成所述第三晶体管T3的第一极和第二极，所述第三有源层33与所述初始化信号线51形成为一体结构。
示例性的，所述第三有源层33包括L型结构。所述第三有源层33用于 形成所述第三晶体管T3的第一极，第二极和沟道部分。所述第三有源层33用于形成所述第三晶体管T3的第一极的部分与所述初始化信号线51形成为一体结构。
上述设置所述第三有源层33与所述初始化信号线51形成为一体结构，可以缩小所述第三有源层33与所述初始化信号线51之间的距离，降低所述子像素占用的布局空间，降低了子像素的布局难度。而且无需设置其他转接图形来实现所述第三晶体管T3的第一极和所述初始化信号线51之间的电连接，进一步降低了显示基板的布局难度。
另外，所述初始化信号线51与所述第三有源层33能够在同一次构图工艺中同时形成为一体结构，不仅简化了显示基板的制作工艺流程，降低制作成本，还更好的保证了所述第三晶体管T3的第一极和所述初始化信号线51的连接性能，提升了显示基板的制作良率。
此外，将所述初始化信号线51与所述第三有源层33形成为一体结构，使得所述初始化信号线51与所述第三扫描线43异层设置，降低了所述初始化信号线51与所述第三扫描线43发生短路的概率，有效提升了显示基板的良率。
如图16至图28，图26至图28所示，在一些实施例中，在每个重复单元中，沿所述第一方向位于同一行的各子像素中的初始化信号线51形成为一体结构；所述初始化信号线51在所述基底上的正投影，与所述电源线VDD在所述基底上的正投影不交叠。
示例性的，沿所述第一方向位于同一行的各子像素中的初始化信号线51依次耦接，形成为一体结构。
上述设置所述初始化信号线51在所述基底上的正投影，与所述电源线VDD在所述基底上的正投影不交叠，能够降低所述初始化信号线51与所述电源线VDD发生短路的风险。
如图3，图6，图7，图11，图14，图15，图16和图26所示，在一些实施例中，所述重复单元包括初始化信号总线50，所述初始化信号总线50的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；所述初始化信号总线50与所述初始化信号线51耦接。
示例性的，所述重复单元包括呈阵列分布的两行六列子像素。该两行子像素中，每行子像素中的初始化信号线51均形成为一体结构，且与所述初始化信号总线50通过过孔耦接。该六列子像素划分为两组子像素，每组子像素包括三列子像素，所述初始化信号总线50在所述基底上的正投影，位于两组子像素在所述基底上的正投影之间。
示例性的，同一列重复单元列中包括的各初始化信号总线50依次耦接，形成为一体结构。
上述设置沿所述第一方向位于同一行的各子像素中的初始化信号线51形成为一体结构，且与所述初始化信号总线50耦接，实现了通过所述初始化信号总线50为所述初始化信号线51提供初始化信号，保证了显示基板的正常工作。
如图23至图25所示，在一些实施例中，所述第三晶体管T3包括双栅结构，所述第三晶体管T3包括第三有源层33，所述第三有源层33包括两个第三沟道部分331，以及与所述两个第三沟道部分331分别耦接的导体部分332；
所述重复单元中包括多个第二连接图形67，在所述重复单元中，沿所述第一方向，相邻的第三晶体管T3的第一极通过所述第二连接图形67相耦接，或者相邻的第三晶体管T3的所述导体部分332通过所述第二连接图形67相耦接；所述第二连接图形67在所述基底上的正投影，位于其耦接的两个相邻的第三晶体管T3的部分栅极在所述基底上的正投影之间；
所述重复单元还包括初始化信号总线50，所述初始化信号总线50沿第二方向延伸，所述第二方向与所述第一方向相交，所述初始化信号总线50与所述第二连接图形67耦接。
示例性的，在所述重复单元中，沿所述第一方向位于同一行的子像素中，一部分相邻的第三晶体管T3的第一极通过所述第二连接图形67相耦接，另一部分相邻的第三晶体管T3的所述导体部分332通过所述第二连接图形67相耦接。
示例性的，所述重复单元包括呈阵列分布的两行六列子像素。以该重复单元中的第一行子像素为例。第一个子像素中的第三晶体管T3的第一极与第二个子像素中的第三晶体管T3的第一极通过第二连接图形67耦接。第二个 子像素中的第三晶体管T3的导体部分332与第三个子像素中的第三晶体管T3的导体部分332通过第二连接图形67耦接。第三个子像素中的第三晶体管T3的第一极与第四个子像素中的第三晶体管T3的第一极通过第二连接图形67耦接。第四个子像素中的第三晶体管T3的导体部分332与第五个子像素中的第三晶体管T3的导体部分332通过第二连接图形67耦接。第五个子像素中的第三晶体管T3的第一极与第六个子像素中的第三晶体管T3的第一极通过第二连接图形67耦接。
示例性的，所述初始化信号总线50与所述第二连接图形67通过过孔耦接。
示例性的，位于所述第三个子像素中的第三晶体管T3和所述第四个子像素中的第三晶体管T3之间的第二连接图形67，与所述初始化信号总线50通过过孔耦接。
上述设置在所述重复单元中，沿所述第一方向，相邻的第三晶体管T3的第一极通过所述第二连接图形67相耦接，或者相邻的第三晶体管T3的所述导体部分332通过所述第二连接图形67相耦接；使得在所述重复单元中，沿所述第一方向位于同一行的第三晶体管T3串联在一起，能够在所述第三扫描线43提供有效的扫描信号的情况下均开启，将所述初始化信号总线50提供的初始化信号传输至相应的子像素中。
示例性的，所述第三有源层33包括L型结构，所述第三晶体管T3的栅极包括第一栅极图形和第二栅极图形，所述第三扫描线43的一部分复用为所述第一栅极图形，所述第二栅极图形与所述第三扫描线43形成为一体结构，所述第二栅极图形沿所述第二方向位于所述第三扫描图形的一侧。所述第一栅极图形在所述基底上的正投影和所述第二栅极图形在所述基底上的正投影，分别与所述第三有源层33在所述基底上的正投影至少部分交叠。
示例性的，所述第二连接图形67在所述基底上的正投影，位于其耦接的两个相邻的第三晶体管T3的第二栅极图形在所述基底上的正投影之间。
上述设置所述第二连接图形67在所述基底上的正投影，位于其耦接的两个相邻的第三晶体管T3的部分栅极在所述基底上的正投影之间，有利于缩小子像素占用的布局空间，降低显示基板的布局难度，有利于显示基板实现高 分辨率。
如图23至图25所示，在一些实施例中，设置所述第二连接图形67与其耦接的所述第三晶体管T3的第一极或者所述导体部分332形成为一体结构。
上述设置方式使得所述第二连接图形67与所述第三晶体管T3的第一极能够在同一次构图工艺中形成，不仅简化了显示基板的制作工艺流程，还降低了显示基板的制作成本。而且，上述设置方式还提升了所述第二连接图形67与所述第三晶体管T3的第一极之间的电连接性能，保证了显示基板的良率。
如图26至图28所示，在一些实施例中，设置所述第三有源层33包括U型结构，所述第三有源层33在所述基底上的正投影与所述第三扫描线43在所述基底上的正投影具有两个交叠区；所述第三有源层33位于U型开口处的两端与所述初始化信号线51分别耦接；所述第三有源层33位于U型底部的部分与驱动晶体管T5的第一极耦接。
示例性的，所述U型结构的开口朝向其耦接的初始化信号线51。所述U型结构与所述初始化信号线51形成为一体结构。
示例性的，在一个重复单元中，沿所述第一方向位于同一行的各子像素中的第三扫描线43依次耦接，形成为一体的，沿所述第一方向延伸的条形结构。
上述设置方式使得所述第三晶体管T3形成为双栅结构，所述第三扫描线43复用为所述第三晶体管T3的栅极。
上述设置方式有利于降低所述子像素占用的布局空间，有利于显示基板实现高分辨率。
如图10，图14和图15所示，在一些实施例中，所述子像素还包括发光控制线44；
所述子像素驱动电路还包括第四晶体管T4，所述第四晶体管T4的栅极与所述发光控制线44耦接，所述第四晶体管T4的第一极与所述电源线VDD耦接，所述第四晶体管T4的第二极与所述驱动晶体管T5的第二极耦接；
在同一个重复单元中，沿第二方向相邻的子像素驱动电路复用同一个所述第四晶体管T4，且复用同一条发光控制信号线。
示例性的，所述发光控制线44包括沿所述第一方向延伸的至少部分。
示例性的，所述第四晶体管T4用于控制所述驱动晶体管T5向所述阳极图形80写入驱动信号，从而实现控制所述发光元件的发光情况。
示例性的，沿第二方向相邻的子像素驱动电路复用同一个所述第四晶体管T4，复用的所述第四晶体管T4分别与该相邻的子像素驱动电路中的两个驱动晶体管T5分别耦接，复用的所述第四晶体管T4分别控制所述两个驱动晶体管T5向相应的阳极图形80写入驱动信号。
上述实施例提供的显示基板中，通过设置在同一个重复单元中，沿第二方向相邻的子像素驱动电路复用同一个所述第四晶体管T4，且复用同一条发光控制信号线；减少了显示基板中第四晶体管T4的数量和发光控制信号线的数量，有效缩小了重复单元占用的布局空间，因此，上述实施例提供的显示基板对多个子像素的布局进行了优化设计，不仅保证了显示基板能够实现高分辨率的显示，还较好的兼容了GOA(英文：Gate On Array)逻辑资源。
如图10，图13至图15，在一些实施例中，设置所述子像素包括阳极图形80；
所述第四晶体管T4包括第四有源层34，所述第四有源层34在所述基底上的正投影，位于沿所述第二方向相邻的两个阳极图形80在所述基底上的正投影之间。
示例性的，所述第四有源层34包括沿所述第一方向延伸的至少部分。
示例性的，所述发光控制信号线在所述基底上的正投影，位于沿所述第二方向相邻的两个阳极图形80在所述基底上的正投影之间。
示例性的，子像素还包括电源连接部45，所述电源连接部45与所述第四有源层34异层设置，所述电源连接部45与所述电源线VDD异层设置，所述电源连接部45通过第二导电图形65与所述第四晶体管T4的第一极耦接，所述电源连接部45通过过孔与所述电源线VDD耦接，该过孔贯穿位于所述电源连接部45与所述电源线VDD之间的绝缘层。
上述设置方式使得所述第四晶体管T4和所述发光控制信号线大致位于复用的两个子像素之间的位置，这样不仅保证了所述第四晶体管T4与所述发光控制信号线，以及两个驱动晶体管T5的良好连接性能，还有效降低了所述 发光控制信号线和所述第四晶体管T4的布局难度。
如图4至图7，图10至图15所示，在一些实施例中，所述驱动晶体管T5包括驱动有源层35；
沿第一方向相邻的两个子像素中，两个所述驱动晶体管T5包括的两个所述驱动有源层35关于第一对称轴呈轴对称设置，所述第一对称轴沿第二方向延伸，所述第一对称轴在所述基底上的正投影，位于所述沿第一方向相邻的两个子像素包括的两个阳极图形80在所述基底上的正投影之间；
沿第二方向相邻的两个子像素中，两个所述驱动晶体管T5包括的两个所述驱动有源层35关于第二对称轴X2呈轴对称设置，所述第二对称轴X2沿第一方向延伸，所述第二对称轴X2在所述基底上的正投影，位于所述沿第二方向相邻的两个子像素包括的两个阳极图形80在所述基底上的正投影之间。
如图4至图7，图10至图15所示，示例性的，所述驱动晶体管T5的第二极通过所述第一导电图形64与所述第四晶体管T4的第二极耦接，所述驱动晶体管T5的第一极与存储电容Cst的第二极板Cst2耦接，通过所述第二极板Cst2实现与阳极图形80耦接。示例性的，所述驱动晶体管T5的第一极与存储电容Cst的第二极板Cst2异层设置，所述驱动晶体管T5的第一极通过所述第三导电图形66与所述第二极板Cst2耦接。存储电容Cst的第一极板Cst1复用为所述驱动晶体管T5的栅极。
示例性的，所述第二极板Cst2还通过第一导电连接部60与所述第三晶体管T3的第二极耦接。所述第三晶体管T3的第一极通过第五导电图形68与所述初始化信号线51耦接。
示例性的，所述驱动有源层35包括U形部，和由所述U形部的两端分别延伸出的两个端部。示例性的，所述U形部用于形成所述驱动晶体管T5的沟道部分，所述两个端部分别作为所述驱动晶体管T5的第一极和第二极。
示例性的，沿第一方向相邻的两个子像素中，两个所述驱动晶体管T5包括的栅极关于所述第一对称轴对称设置。
示例性的，沿第二方向相邻的两个子像素中，两个所述驱动晶体管T5包括的栅极关于所述第二对称轴X2对称设置。
上述对称的设置方式有效缩小了子像素占用的布局空间，有利于显示基 板实现高显示分辨率。
如图4至图7，图10至图15所示，在一些实施例中，设置所述第二晶体管T2包括第二有源层32；
沿第一方向相邻的两个子像素中，两个所述第二晶体管T2包括的两个所述第二有源层32关于所述第一对称轴呈轴对称设置；
沿第二方向相邻的两个子像素中，两个所述第二晶体管T2包括的两个所述第二有源层32关于所述第二对称轴X2呈轴对称设置。
示例性的，所述第二有源层32包括沿所述第一方向延伸的部分。示例性的，所述第二有源层32的两个端部在所述第二方向的宽度，大于所述第二有源层32位于两个端部之间的中间部分在所述第二方向的宽度。示例性的，所述第二有源层32的中间部分在所述基底上的正投影与所述第二晶体管T2的栅极在所述基底上的正投影至少部分交叠，所述第二有源层32的中间部分用于形成所述第二晶体管T2的沟道区。
上述设置方式有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图4至图7，图10至图15所示，在一些实施例中，设置所述子像素驱动电路还包括第一晶体管T1，所述第一晶体管T1包括第一有源层31；
沿第一方向相邻的两个子像素中，两个所述第一晶体管T1包括的两个所述第一有源层31关于所述第一对称轴呈轴对称设置；
沿第二方向相邻的两个子像素中，两个所述第一晶体管T1包括的两个所述第一有源层31关于所述第二对称轴X2呈轴对称设置。
示例性的，所述第一有源层31包括沿所述第一方向延伸的部分。示例性的，所述第一有源层31的两个端部在所述第二方向的宽度，大于所述第一有源层31位于两个端部之间的中间部分在所述第二方向的宽度。示例性的，所述第一有源层31的中间部分在所述基底上的正投影与所述第一晶体管T1的栅极在所述基底上的正投影至少部分交叠，所述第一有源层31的中间部分用于形成所述第一晶体管T1的沟道区。
上述设置方式有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
如图4至图7，图10至图15所示，在一些实施例中，所述子像素驱动电路还包括第三晶体管T3，所述第三晶体管T3包括第三有源层33；
沿第一方向相邻的两个子像素中，两个所述第三晶体管T3包括的两个所述第三有源层33关于所述第一对称轴呈轴对称设置；
沿第二方向相邻的两个子像素中，两个所述第三晶体管T3包括的两个所述第三有源层33关于所述第二对称轴X2呈轴对称设置。
如图4至图7，图10至图15所示，在一些实施例中，所述子像素驱动电路还包括第四晶体管T4，所述第四晶体管T4包括第四有源层34；
沿第一方向相邻的两个子像素中，两个所述第四晶体管T4包括的两个所述第四有源层34关于所述第一对称轴呈轴对称设置。
上述设置方式有效缩小子像素占用的布局空间，有利于显示基板实现高显示分辨率。
需要说明，图16至图22对应的实施例中，第一栅金属层的示意图参见图5，第二源漏金属层的示意图参见图8，像素界定层形成的开口的布局示意图参见图9，阳极层和第二源漏金属层的布局示意图参见图13。
图23至图25对应的实施例中，第一栅金属层的示意图参见图5，第二栅金属层的示意图参见图18，第一源漏金属层的布局示意图参见图19，第二源漏金属层的示意图参见图8，像素界定层形成的开口的布局示意图参见图9，阳极层和第二源漏金属层的布局示意图参见图13。
图26至图28对应的实施例中，第二栅金属层的示意图参见图18，第一源漏金属层的布局示意图参见图19，第二源漏金属层的示意图参见图8，像素界定层形成的开口的布局示意图参见图9，阳极层和第二源漏金属层的布局示意图参见图13。
如图29所示，示例性的，所述显示基板包括沿远离所述基底的方向依次层叠设置的缓冲层Buf，有源层Poly，第一栅极绝缘层GI1，第一栅金属层Gat1，第二栅极绝缘层GI2，第二栅金属层Gat2，层间绝缘层ILD，第一源漏金属层SD1，第一钝化层PVX1，第一平坦层PLN1，第二源漏金属层SD2，第二钝化层PVX2，第二平坦层PLN2，阳极层(包括阳极图形80)，像素界定层PDL，发光功能层，阴极层，封装结构。示例性的，所述显示基板也可以 不包括所述第一钝化层PVX1和/或所述第二钝化层PVX2。
示例性的，所述显示基板经历12道构图工艺(Mask工艺)形成，具体包括：有源层的构图工艺，第一栅金属层的构图工艺，第二栅金属层的构图工艺，层间绝缘层的构图工艺，第一源漏金属层的构图工艺，第一平坦层的构图工艺，第一钝化层的构图工艺，第二源漏金属层的构图工艺，第二平坦层的构图工艺，第二钝化层的构图工艺，阳极层的构图工艺和像素界定层的构图工艺。
如图9所示，示例性的，所述像素界定层形成像素开口81。示例性的，像素开口81为等Pitch圆弧打印设计，能够提升制作有机发光材料的打印速率，并能够提升显示基板的器件性能。
如图7和图9所示，示例性的，沿所述第二方向相邻的两个子像素中，两个所述第一导电连接部60关于所述第二对称轴X2对称，两个所述第一导电图形64关于所述第二对称轴X2对称，两个所述第三导电图形66关于所述第二对称轴X2对称，两个所述第五导电图形68关于所述第二对称轴X2对称，两个所述阳极图形关于所述第二对称轴X2对称，两个所述像素开口81关于所述第二对称轴X2对称。两个所述第一连接图形61关于所述第二对称轴X2对称。两个所述第一极板Cst1关于所述第二对称轴X2对称，两个所述第二极板Cst2关于所述第二对称轴X2对称，两个所述第一有源层31关于所述第二对称轴X2对称，两个所述第二有源层32关于所述第二对称轴X2对称，两个所述第三有源层33关于所述第二对称轴X2对称，两个所述第四有源层34关于所述第二对称轴X2对称，两个所述驱动有源层35关于所述第二对称轴X2对称。
如图7和图9所示，示例性的，沿所述第一方向相邻的两个子像素中，两个所述第一导电连接部60关于第一对称轴对称，两个所述第一导电图形64关于所述第一对称轴对称，两个所述第二导电图形65关于所述第一对称轴对称，两个所述第三导电图形66关于所述第一对称轴对称，两个所述第五导电图形68关于所述第一对称轴对称，两个所述阳极图形关于所述第一对称轴对称，两个所述像素开口81关于所述第一对称轴对称，两个所述第一极板Cst1关于所述第一对称轴对称，两个所述第二极板Cst2关于所述第一对称 轴对称，两个所述第一有源层31关于所述第一对称轴对称，两个所述第二有源层32关于所述第一对称轴对称，两个所述第三有源层33关于所述第一对称轴对称，两个所述第四有源层34关于所述第一对称轴对称，两个所述驱动有源层35关于所述第一对称轴对称。两个所述第一连接图形61关于所述第一对称轴对称。
如图7，图8，图12和图13所示，在一些实施例中，所述子像素还包括异层设置的第一导电连接部60和第二导电连接部70，所述第一导电连接部60位于所述基底和所述第二导电连接部70之间，所述阳极图形80位于所述第二导电连接部70背向所述基底的一侧；
所述第二极板Cst2与所述第一导电连接部60耦接；
所述第二导电连接部70在所述基底10上的正投影，与所述第一导电连接部60在所述基底10上的正投影之间具有第一交叠区域，所述第二导电连接部70在所述基底10上的正投影，与所述阳极图形80在所述基底10上的正投影之间具有第二交叠区域；
所述第二导电连接部70通过第一过孔与所述第一导电连接部60耦接，所述第一过孔在所述基底10上的正投影位于所述第一交叠区域；所述第二导电连接部70通过第二过孔与所述阳极图形80耦接，所述第二过孔在所述基底10上的正投影位于所述第二交叠区域。
如图1和图2所示，上述实施例提供的显示基板中，子像素驱动电路包括驱动晶体管T5，第四晶体管T4，第一晶体管T1，第二晶体管T2，第三晶体管T3和存储电容Cst。
沿第二方向相邻的两个子像素中位于第一行的子像素和位于第二行的子像素的工作过程均包括：复位时段P1，补偿时段P2，数据写入时段P3和发光时段P4。
第一行子像素和第二行子像素的复位时段错开，第一行子像素和第二行子像素的补偿时段部分错开，第一行子像素和第二行子像素的数据写入时段完全错开。
需要说明，在第一行子像素和第二子像素的数据写入时段中，发光控制信号EM处于非有效电平，这样能够避免在第二子像素写入数据信号的过程 中，第一行子像素的驱动晶体管T5的第一极持续接收电源信号Vd，避免了第一行子像素的驱动晶体管T5的栅源电压下降，影响对第一子像素中子像素驱动电路的补偿效果。
图1中示意了发光元件EL，阴极层提供的负电源信号VSS，所述基准信号线63提供的基准信号Vref。所述初始化信号总线50提供的初始化信号Vinit。电源线VDD提供的电源信号Vd。发光控制线44提供的发光控制信号EM。
图2中示意了第一行子像素中，第一扫描线41输入的第一扫描信号G11，第二扫描线42输入的第二扫描信号G21，以及第三扫描线43输入的第三扫描信号G31。图2中还示意了第二行子像素中，第一扫描线41输入的第一扫描信号G12，第二扫描线42输入的第二扫描信号G22，以及第三扫描线43输入的第三扫描信号G32。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
上述实施例提供的显示基板中，设置所述第二晶体管T2的第一极与所述基准信号线36形成为一体结构，可以缩小所述第二晶体管T2的第一极与所述基准信号线36之间的距离，降低所述子像素占用的布局空间，降低了子像素的布局难度。而且无需设置其他转接图形来连接所述第二晶体管T2的第一极和所述基准信号线36之间的电连接，进一步降低了显示基板的布局难度。
另外，上述实施例提供的显示基板中，设置所述第二晶体管T2的第一极与所述基准信号线36形成为一体结构，使得所述第二晶体管T2的第一极和所述基准信号线36能够在同一次工艺中同时形成，且实现耦接，这样不仅简化了显示基板的制作工艺流程，降低制作成本，还更好的保证了所述第二晶体管T2的第一极和所述基准信号线36的连接性能，提升了显示基板的制作良率。
本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易 想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种显示基板，包括：基底，设置于所述基底上的多个子像素，所述多个子像素呈阵列分布；所述子像素包括：
    基准信号线和第二扫描线；以及，
    子像素驱动电路，所述子像素驱动电路包括驱动晶体管和第二晶体管，所述第二晶体管的栅极与所述第二扫描线耦接，所述第二晶体管的第一极与所述基准信号线形成为一体结构，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接。
  2. 根据权利要求1所述的显示基板，其中，所述第二晶体管包括第二有源层，所述第二有源层形成所述第二晶体管的第一极和第二极，所述基准信号线的至少部分沿第一方向延伸；所述第二有源层的至少部分沿所述第一方向延伸；所述第二扫描线的至少部分沿所述第一方向延伸；所述第二有源层在所述基底上的正投影的至少部分，位于所述基准信号线在所述基底上的正投影和所述第二扫描线在所述基底上的正投影之间。
  3. 根据权利要求2所述的显示基板，其中，所述子像素还包括第一扫描线，数据线和第一连接图形；所述子像素驱动电路还包括第一晶体管；
    所述第一晶体管的栅极与所述第一扫描线耦接，所述第一晶体管的第一极与所述数据线耦接，所述第一晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第一连接图形分别与所述第一晶体管的第二极和所述第二晶体管的第二极耦接，所述第一连接图形在所述基底上的正投影，分别与所述第一扫描线在所述基底上的正投影和所述第二扫描线在所述基底上的正投影部分交叠。
  4. 根据权利要求2所述的显示基板，其中，所述多个子像素划分为多个重复单元，所述多个重复单元划分为多列重复单元列；所述显示基板还包括多条电源线，所述电源线与所述重复单元列沿所述第一方向交替设置；
    在每个重复单元中，沿所述第一方向位于同一行的各子像素中的基准信号线形成为一体结构；所述基准信号线在所述基底上的正投影，与所述电源 线在所述基底上的正投影不交叠。
  5. 根据权利要求4所述的显示基板，其中，所述子像素还包括第三扫描线和初始化信号线；
    所述子像素驱动电路还包括第三晶体管，所述第三晶体管的栅极与所述第三扫描线耦接，所述第三晶体管的第一极与所述初始化信号线形成为一体结构，所述第三晶体管的第二极与所述驱动晶体管的第一极耦接。
  6. 根据权利要求5所述的显示基板，其中，在每个重复单元中，沿所述第一方向位于同一行的各子像素中的初始化信号线形成为一体结构；所述初始化信号线在所述基底上的正投影，与所述电源线在所述基底上的正投影不交叠。
  7. 根据权利要求6所述的显示基板，其中，所述重复单元包括初始化信号总线，所述初始化信号总线的至少部分沿第二方向延伸，所述第二方向与所述第一方向相交；所述初始化信号总线与所述初始化信号线耦接。
  8. 根据权利要求5所述的显示基板，其中，所述第三晶体管包括双栅结构，所述第三晶体管包括第三有源层，所述第三有源层包括两个第三沟道部分，以及与所述两个第三沟道部分分别耦接的导体部分；
    所述重复单元中包括多个第二连接图形，在所述重复单元中，沿所述第一方向，相邻的第三晶体管的第一极通过所述第二连接图形相耦接，或者相邻的第三晶体管的所述导体部分通过所述第二连接图形相耦接；所述第二连接图形在所述基底上的正投影，位于其耦接的两个相邻的第三晶体管的部分栅极在所述基底上的正投影之间；
    所述重复单元还包括初始化信号总线，所述初始化信号总线沿第二方向延伸，所述第二方向与所述第一方向相交，所述初始化信号总线与所述第二连接图形耦接。
  9. 根据权利要求8所述的显示基板，其中，所述第二连接图形与其耦接的所述第三晶体管的第一极或者所述导体部分形成为一体结构。
  10. 根据权利要求5所述的显示基板，其中，所述第三有源层包括U型结构，所述第三有源层在所述基底上的正投影与所述第三扫描线在所述基底上的正投影具有两个交叠区；所述第三有源层位于U型开口处的两端与所述 初始化信号线分别耦接；所述第三有源层位于U型底部的部分与驱动晶体管的第一极耦接。
  11. 根据权利要求4所述的显示基板，其中，所述子像素还包括发光控制线；
    所述子像素驱动电路还包括第四晶体管，所述第四晶体管的栅极与所述发光控制线耦接，所述第四晶体管的第一极与所述电源线耦接，所述第四晶体管的第二极与所述驱动晶体管的第二极耦接；
    在同一个重复单元中，沿第二方向相邻的子像素驱动电路复用同一个所述第四晶体管，且复用同一条发光控制信号线。
  12. 根据权利要求11所述的显示基板，其中，所述子像素包括阳极图形；
    所述第四晶体管包括第四有源层，所述第四有源层在所述基底上的正投影，位于沿所述第二方向相邻的两个阳极图形在所述基底上的正投影之间。
  13. 根据权利要求1～12中任一项所述的显示基板，其中，所述驱动晶体管包括驱动有源层；
    沿第一方向相邻的两个子像素中，两个所述驱动晶体管包括的两个所述驱动有源层关于第一对称轴呈轴对称设置，所述第一对称轴沿第二方向延伸，所述第一对称轴在所述基底上的正投影，位于所述沿第一方向相邻的两个子像素包括的两个阳极图形在所述基底上的正投影之间；
    沿第二方向相邻的两个子像素中，两个所述驱动晶体管包括的两个所述驱动有源层关于第二对称轴呈轴对称设置，所述第二对称轴沿第一方向延伸，所述第二对称轴在所述基底上的正投影，位于所述沿第二方向相邻的两个子像素包括的两个阳极图形在所述基底上的正投影之间。
  14. 根据权利要求13所述的显示基板，其中，所述第二晶体管包括第二有源层；
    沿第一方向相邻的两个子像素中，两个所述第二晶体管包括的两个所述第二有源层关于所述第一对称轴呈轴对称设置；
    沿第二方向相邻的两个子像素中，两个所述第二晶体管包括的两个所述第二有源层关于所述第二对称轴呈轴对称设置。
  15. 根据权利要求13所述的显示基板，其中，所述子像素驱动电路还包 括第一晶体管，所述第一晶体管包括第一有源层；
    沿第一方向相邻的两个子像素中，两个所述第一晶体管包括的两个所述第一有源层关于所述第一对称轴呈轴对称设置；
    沿第二方向相邻的两个子像素中，两个所述第一晶体管包括的两个所述第一有源层关于所述第二对称轴呈轴对称设置。
  16. 根据权利要求13所述的显示基板，其中，所述子像素驱动电路还包括第三晶体管，所述第三晶体管包括第三有源层；
    沿第一方向相邻的两个子像素中，两个所述第三晶体管包括的两个所述第三有源层关于所述第一对称轴呈轴对称设置；
    沿第二方向相邻的两个子像素中，两个所述第三晶体管包括的两个所述第三有源层关于所述第二对称轴呈轴对称设置。
  17. 根据权利要求13所述的显示基板，其中，所述子像素驱动电路还包括第四晶体管，所述第四晶体管包括第四有源层；
    沿第一方向相邻的两个子像素中，两个所述第四晶体管包括的两个所述第四有源层关于所述第一对称轴呈轴对称设置。
  18. 一种显示装置，包括如权利要求1～17中任一项所述的显示基板。
PCT/CN2021/134167 2021-11-29 2021-11-29 显示基板和显示装置 WO2023092607A1 (zh)

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