WO2022170547A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022170547A1
WO2022170547A1 PCT/CN2021/076457 CN2021076457W WO2022170547A1 WO 2022170547 A1 WO2022170547 A1 WO 2022170547A1 CN 2021076457 W CN2021076457 W CN 2021076457W WO 2022170547 A1 WO2022170547 A1 WO 2022170547A1
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Prior art keywords
line
electrode
area
connection line
transistor
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Application number
PCT/CN2021/076457
Other languages
English (en)
French (fr)
Inventor
杜丽丽
王本莲
龙跃
黄炜赟
王彬艳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to GB2215878.6A priority Critical patent/GB2610947A/en
Priority to CN202180000212.8A priority patent/CN115668346A/zh
Priority to US17/608,747 priority patent/US20230255067A1/en
Priority to PCT/CN2021/076457 priority patent/WO2022170547A1/zh
Publication of WO2022170547A1 publication Critical patent/WO2022170547A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers

Definitions

  • This article relates to, but is not limited to, the field of display technology, especially a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFTs thin film transistors
  • At least one embodiment of the present disclosure provides a display substrate, a method for manufacturing the same, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a display area and a peripheral area located at the periphery of the display area.
  • the display area is provided with at least a plurality of sub-pixels, and at least one sub-pixel includes: a pixel driving circuit arranged on the base substrate and a light-emitting element connected to the pixel driving circuit; the pixel driving circuit is connected to the first initial signal line connected, the first initial signal line is configured to provide a first initial voltage to the light-emitting element under the control of the pixel driving circuit.
  • the peripheral area is provided with a first power supply line and a signal connection line, and the first initial signal line is connected to the first power supply line through the signal connection line in the peripheral area.
  • the peripheral area includes: a first border area, a second border area and a binding pin area, the binding pin area is located on one side of the display area, the first The frame area is located between the binding pin area and the display area; the second frame area communicates with the first frame area and surrounds the display area.
  • the signal connection line includes: a first connection line; the first connection line is connected to the first initial signal line and the first power supply line in the second frame area. The first connection line is located on a side of the first power line close to the display area.
  • the first connection wire is located on a side of the first power wire away from the base substrate.
  • the signal connection line further includes: a second connection line, the second connection line is connected with the first initial signal line, and the second connection line passes through the first connection line connected to the first power cord.
  • the second connection line is located on a side of the first connection line close to the display area.
  • the second connection line is located on a side of the first connection line close to the base substrate, and is located on a side of the first initial signal line away from the base substrate.
  • the second connection line and the first power supply line are of the same layer structure.
  • an extension direction of the first connection line in the peripheral region intersects with an extension direction of the first initial signal line in the display region.
  • the display area includes: a driving structure layer and a light-emitting element disposed on the base substrate, the light-emitting element includes: a first electrode, a second electrode and a light-emitting element disposed on the first an organic light-emitting layer between an electrode and a second electrode; the first electrode is located on the side of the second electrode close to the base substrate.
  • the first connection line and the first electrode of the light-emitting element are of the same layer structure.
  • the driving structure layer includes: a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source-drain metal layer disposed on the base substrate.
  • the first initial signal line and the second gate metal layer have a same-layer structure, and the first power line and the source-drain metal layer have a same-layer structure.
  • the peripheral area includes: a first border area, a second border area and a binding pin area, the binding pin area is located on one side of the display area, the first The frame area is located between the binding pin area and the display area; the second frame area communicates with the first frame area and surrounds the display area.
  • the signal connection line includes: a third connection line, the third connection line is connected to the first initial signal line in the second frame area, and the third connection wire is connected to the first initial frame area in the first frame area. the first power line connection.
  • the third connection wire and the first power wire are integrally formed.
  • the signal connection line further includes: a fourth connection line; the third connection line is connected with the fourth connection line, and the fourth connection line is connected to the first frame area with the fourth connection line.
  • the first power line is connected; the fourth connection line is located on the side of the first power line close to the base substrate.
  • the pixel driving circuit includes: first to seventh transistors.
  • the control electrode of the first transistor is connected to the second scan line, the first electrode of the first transistor is connected to the second initial signal line, the second electrode of the first transistor is connected to the first node; the control electrode of the second transistor is connected to the first
  • the scan line is connected, the first pole of the second transistor is connected to the first node, the second pole of the second transistor is connected to the third node; the control pole of the third transistor is connected to the first node, and the first pole of the third transistor is connected to the third node.
  • the second node is connected to the second node, the second electrode of the third transistor is connected to the third node; the control electrode of the fourth transistor is connected to the first scan signal line, the first electrode of the fourth transistor is connected to the data signal line, and the first electrode of the fourth transistor is connected to the data signal line.
  • the diode is connected to the second node; the control electrode of the fifth transistor is connected to the light-emitting signal line, the first electrode of the fifth transistor is connected to the second power line, and the second electrode of the fifth transistor is connected to the second node; the sixth transistor The control electrode of the sixth transistor is connected to the light-emitting signal line, the first electrode of the sixth transistor is connected to the third node, the second electrode of the sixth transistor is connected to the fourth node; the control electrode of the seventh transistor is connected to the first scanning signal line, and the sixth transistor is connected to the first scanning signal line.
  • the first electrode of the seven transistors is connected to the first initial signal line, the second electrode of the seventh transistor is connected to the fourth node; the first electrode of the light-emitting element is connected to the fourth node, and the second electrode of the light-emitting element is connected to the fourth node.
  • the first power cord is connected.
  • an embodiment of the present disclosure also provides a display device including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a method for manufacturing a display substrate, which is used to prepare the above-mentioned display substrate.
  • the manufacturing method includes: forming a plurality of sub-pixels in a display area, and forming a plurality of sub-pixels in a peripheral area of the periphery of the display area A first power line and a signal connection line are formed.
  • at least one sub-pixel includes: a pixel driving circuit disposed on the base substrate and a light-emitting element connected to the pixel driving circuit; the pixel driving circuit is connected to a first initial signal line, and the first initial signal line It is configured to provide a first initial voltage to the light-emitting element under the control of the pixel driving circuit.
  • the first initial signal line is connected to the first power line through the signal connection line in the peripheral region.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a driving structure of a display substrate according to at least one embodiment of the disclosure
  • FIG. 3 is a schematic plan view of a display area of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area of a display substrate according to at least one embodiment of the disclosure
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to at least one embodiment of the disclosure.
  • FIG. 6 is an operation timing diagram of a pixel driving circuit according to at least one embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of wirings in a peripheral region of a display substrate according to at least one embodiment of the present disclosure.
  • Fig. 10 is a partial cross-sectional schematic diagram along the P-P direction in Fig. 8;
  • FIG. 11 is a partial schematic view of the upper left corner of the display substrate shown in FIG. 7;
  • FIG. 12 is a partial schematic view of the position of the lower left corner of the display substrate shown in FIG. 7;
  • FIG. 13 is a schematic diagram of another wiring diagram of the peripheral region of the display substrate according to at least one embodiment of the disclosure.
  • FIG. 14 is a schematic diagram of another wiring diagram of the peripheral region of the display substrate according to at least one embodiment of the disclosure.
  • 15 and 16 are partially enlarged schematic views of the area S2 in FIG. 14;
  • FIG. 17 is a schematic partial cross-sectional view along the R-R direction in FIG. 15;
  • Figure 20 is a schematic partial cross-sectional view along the Y-Y direction in Figure 18;
  • 21 is a schematic diagram of another wiring diagram of a peripheral region of a display substrate according to at least one embodiment of the disclosure.
  • Fig. 22 is a partial enlarged schematic view of region S3 in Fig. 21;
  • FIG. 23 is another schematic diagram of a peripheral region of a display substrate according to at least one embodiment of the disclosure.
  • Fig. 24 is a partial enlarged schematic view of region S4 in Fig. 23;
  • Figure 25 is a schematic partial cross-sectional view along the Q-Q direction in Figure 24;
  • FIG. 26 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • ordinal numbers such as “first”, “second”, and “third” are set to avoid confusion of constituent elements, rather than to limit the quantity.
  • a “plurality” in this disclosure means a quantity of two or more.
  • the terms “installed”, “connected” and “connected” should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • the “electrical connection” includes the case where the constituent elements are connected together by an element having a certain electrical effect.
  • the “element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements. Examples of “elements having some electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode in order to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode.
  • the first electrode may be the source electrode or the drain electrode
  • the second electrode may be It is a drain electrode or a source electrode
  • the gate electrode of the transistor is called a control electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in the present disclosure, “source electrode” and “drain electrode” may be interchanged with each other.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • At least one embodiment of the present disclosure provides a display substrate, including: a display area and a peripheral area located at the periphery of the display area.
  • the display area is provided with at least a plurality of sub-pixels, and at least one sub-pixel includes: a pixel driving circuit provided on the base substrate and a light-emitting element connected to the pixel driving circuit.
  • the pixel driving circuit is connected to the first initial signal line, and the first initial signal line is configured to provide a first initial voltage to the light-emitting element under the control of the pixel driving circuit.
  • the peripheral area is provided with a first power line and a signal connection line. The first initial signal line is connected to the first power line through the signal connection line in the peripheral area.
  • the electrical connection between the first power line and the first initial signal line is realized by using signal connection lines in the peripheral area, so that the first initial voltage provided by the first initial signal line is the first power supply voltage provided by the first power line , using the first power supply voltage provided by the first power supply line to initialize the light-emitting element, which can improve the uniformity of the display substrate under high and low gray scales, and can avoid increasing the space for pins and traces that introduce the first initial voltage in the peripheral area .
  • the peripheral area includes: a first frame area, a second frame area, and a binding pin area.
  • the binding pin area is located on one side of the display area
  • the first frame area is located between the binding pin area and the display area
  • the second frame area is connected to the first frame area and surrounds the display area.
  • the signal connection line includes: a first connection line.
  • the first connection line is connected to the first initial signal line and the first power line in the second frame area.
  • the first connection line is located on one side of the first power line close to the display area.
  • the first connection line in a plane perpendicular to the display substrate, is located on a side of the first power line away from the base substrate.
  • the display area includes: a driving structure layer and a light-emitting element disposed on the base substrate, and the light-emitting element includes: a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode , the first electrode is located on the side of the second electrode close to the base substrate.
  • the first connection line may be in the same layer structure as the first electrode of the light-emitting element.
  • the driving structure layer includes: a semiconductor layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer arranged on the base substrate.
  • the first initial signal line and the second gate metal layer may have the same layer structure, and the first power line and the source and drain metal layer may have the same layer structure.
  • this embodiment does not limit this.
  • the driving structure layer may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the base substrate.
  • the first initial signal line and the second gate metal layer may be of the same layer structure
  • the first power line may be of the same layer structure as the first source/drain metal layer
  • the first connection line may be of the same layer structure as the second source/drain metal layer
  • the first power line and the second source-drain metal layer may be of the same layer structure
  • the first connection line may be of the same layer structure as the first electrode of the light-emitting element.
  • the signal connection line may include: a first connection line and a second connection line.
  • the second connection line is connected to the first initial signal line, and the second connection line is connected to the first power line through the first connection line.
  • the second connection line is located on one side of the first connection line close to the display area.
  • the second connection line is connected with the first connection line in the second frame area, and the first connection line is connected with the first power line in the second frame area.
  • the second connection line in a plane perpendicular to the display substrate, is located on a side of the first connection line close to the base substrate, and is located on a side of the first initial signal line away from the base substrate.
  • the first initial signal line may be of the same layer structure as the second gate metal layer of the display area
  • the second connection line may be of the same layer structure as the source/drain metal layer of the display area
  • the first connection line may be of the same layer structure as the second gate metal layer of the light-emitting element.
  • One electrode is of the same layer structure. However, this embodiment does not limit this.
  • the second connection line and the first power supply line are of the same layer structure.
  • both the second connection line and the first power supply line are of the same layer structure as the source-drain metal layer of the display area.
  • this embodiment does not limit this.
  • the second connection line and the first power supply line may be of a heterogeneous structure.
  • the second connection line and the first source-drain metal layer in the display area may be in the same layer structure, and the first power line may be in the same layer structure as the second source-drain metal layer in the display area.
  • the extension direction of the first connection line in the peripheral area intersects with the extension direction of the first initial signal line in the display area.
  • the first initial signal line extends in the horizontal direction in the display area
  • the first connection line extends in the vertical direction in the peripheral area.
  • the first initial signal line extends in the vertical direction in the display area
  • the first connection line extends in the horizontal direction in the peripheral area.
  • this embodiment does not limit this.
  • the peripheral area includes: a first border area, a second border area, and a binding pin area, the binding pin area is located on one side of the display area, and the first border area is located in the binding pin area and the display area; the second frame area communicates with the first frame area and surrounds the display area.
  • the signal connection line includes: a third connection line. The third connection line is connected to the first initial signal line in the second frame area, and the third connection line is connected to the first power line in the first frame area.
  • the connection between the third connection line and the first power supply line is realized in the first frame area, so as to avoid adding pins for introducing the first initial voltage in the binding pin area.
  • the third connection wire and the first power wire are integrally formed.
  • the wiring in the first frame area can be optimized.
  • the signal connection line includes: a third connection line and a fourth connection line.
  • the third connection line is connected with the fourth connection line.
  • the fourth connection line is connected to the first power line in the first frame area.
  • the fourth connection line is located on the side of the first power line close to the base substrate.
  • the third connection line may be connected with the fourth connection line in the first bezel area, or may be connected with the fourth connection line in the second bezel area.
  • the third connection line may be of the same layer structure as the first power supply line, for example, the same layer structure as the source-drain metal layer of the display area; the fourth connection line may be of the same layer structure as the second gate metal layer of the display area layer structure.
  • this embodiment does not limit this.
  • the pixel driving circuit includes: first to seventh transistors.
  • the control electrode of the first transistor is connected to the second scan line, the first electrode of the first transistor is connected to the second initial signal line, and the second electrode of the first transistor is connected to the first node.
  • the control electrode of the second transistor is connected to the first scan line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node.
  • the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node.
  • the control electrode of the fourth transistor is connected to the first scan signal line, the first electrode of the fourth transistor is connected to the data signal line, and the second electrode of the fourth transistor is connected to the second node.
  • the control electrode of the fifth transistor is connected to the light-emitting signal line, the first electrode of the fifth transistor is connected to the second power line, and the second electrode of the fifth transistor is connected to the second node.
  • the control electrode of the sixth transistor is connected to the light-emitting signal line, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node.
  • the control electrode of the seventh transistor is connected to the first scan signal line, the first electrode of the seventh transistor is connected to the first initial signal line, and the second electrode of the seventh transistor is connected to the fourth node.
  • the first electrode of the light-emitting element is connected to the fourth node, and the second electrode of the light-emitting element is connected to the first power supply line.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the disclosure.
  • the display substrate in a plane parallel to the display substrate, the display substrate includes: a display area 100 and a peripheral area located at the periphery of the display area 100 .
  • the peripheral area includes: the first frame area 200, the second frame area 300 and the binding pin area 400.
  • the binding pin area 400 is located on one side of the display area 100
  • the first border area 200 is located between the display area 100 and the binding pin area 400 .
  • the second frame area 300 is located on the other side of the display area 100 .
  • the second frame area 300 communicates with the first frame area 200 and surrounds the display area 100 .
  • the first frame area 200 is a lower frame of the display substrate
  • the second frame area 300 includes an upper frame, a left frame and a right frame of the display substrate.
  • this embodiment does not limit this.
  • the display substrate may include a pair of long sides parallel to each other in the first direction F1 and a pair of short sides parallel to each other in the second direction F2.
  • the first direction F1 and the second direction F2 are perpendicular to each other.
  • the present embodiment does not limit the shape of the display substrate.
  • the display substrate may be a closed polygon including linear sides, a circular or elliptical shape including curved sides, or a semi-circular or semi-elliptical shape including linear and curved sides, and the like.
  • at least some corners of the display substrate may be curved.
  • the curvature can be set according to the position of the curve. For example, the curvature can be changed depending on where the curve starts, the length of the curve, etc.
  • the first frame area 200 is located on one side of the display area 100 , and along a direction away from the display area 100 (ie, along the second direction F2 ), the first frame area 200 It may include a first fan-out area 201 , a bending area 202 , a second fan-out area 203 , an anti-static area 204 and a driving chip area 205 arranged in sequence.
  • the bonding pin area 400 is located on the side of the driver chip area 205 away from the display area 100 .
  • the first fan-out area 201 can be provided with signal transmission lines of the display substrate, and the signal transmission lines of the display substrate at least include a first power supply line (VSS), a second power supply line (VDD) and a plurality of data transmission lines, and the plurality of data transmission lines are configured to be fan-shaped.
  • the fanout is connected to the data line of the display substrate, and the first power supply line VSS and the second power supply line VDD are configured to be connected to the low-level power supply line and the high-level power supply line of the display substrate, respectively.
  • the bending area 202 may be provided with a groove, and the groove is configured to bend the second fan-out area 203 , the anti-static area 204 , the driving chip area 205 and the bonding pin area 400 to the back of the display area 100 .
  • the second fan-out area 203 may be provided with a first power supply line VSS, a second power supply line VDD, a gate signal transmission line, and a plurality of data transmission lines drawn out in a fan-out wiring manner.
  • the anti-static area 204 may be provided with an anti-static circuit, and the anti-static circuit is configured to eliminate static electricity.
  • the driver chip area 205 may be provided with a source driver circuit (Driver IC), and the source driver circuit is configured to be connected with a plurality of data transmission lines of the second fan-out area 203.
  • the binding pin area 400 can be provided with a plurality of pins (PINs), and the plurality of pins are respectively connected to the first power supply line VSS, the second power supply line VDD, the signal line of the anti-static area 204 and the signal line of the driving chip area 205 .
  • Multiple pins are connected to external control devices by binding a flexible circuit board (FPC, Flexible Printed Circuit).
  • FIG. 2 is a schematic diagram of a driving structure of a display substrate according to at least one embodiment of the disclosure.
  • the display area of the display substrate is provided with a pixel array, and the peripheral area can be provided with a timing controller, a data driver, a scan driver and a light-emitting driver.
  • the pixel array may include a plurality of scan signal lines (eg, S(1) to S(m)), a plurality of data signal lines (eg, D(1) to D(n)), a plurality of light emission signal lines (eg, E(1) to E(o)) and a plurality of sub-pixels Pxij.
  • the timing controller may provide grayscale values and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the data driver
  • the scan driver can supply the light-emitting driver with a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver.
  • the data driver may generate data voltages to be supplied to the data signal lines D( 1 ) to D(n) using the grayscale values and control signals received from the timing controller.
  • the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D(1) to D(n) in sub-pixel row units, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S( 1 ) to S(m) by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S( 1 ) to S(m).
  • the scan driver may be constructed in the form of a shift register, and may generate the scan signal in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal , m can be a natural number.
  • the light emission driver may generate light emission signals to be supplied to the light emission signal lines E( 1 ) to E(o) by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the light-emitting driver may sequentially supply light-emitting signals having off-level pulses to the light-emitting signal lines E(1) to E(o).
  • the light-emitting driver may be constructed in the form of a shift register, and may generate the light-emitting signal in such a manner that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, o Can be a natural number.
  • the pixel array may include a plurality of sub-pixels PXij. Each sub-pixel PXij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light-emitting signal line, and i and j may be natural numbers.
  • the sub-pixel PXij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.
  • FIG. 3 is a schematic plan view of a display area of a display substrate according to at least one embodiment of the disclosure.
  • the display area of the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color and emits light of a second color
  • the second sub-pixel P2 for light and the third sub-pixel P3 for emitting light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting element.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line and the light-emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light-emitting signal line. Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting element.
  • the light-emitting elements in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting element is configured to emit corresponding current in response to the current output by the pixel driving circuit of the sub-pixel. Brightness of light.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels and blue (B) sub-pixels, or may include red sub-pixels, green sub-pixels, blue sub-pixels
  • the pixel and the white sub-pixel are not limited in this disclosure.
  • the shape of the sub-pixels in the pixel unit may be rectangular, diamond, pentagon or hexagonal.
  • the three sub-pixels can be arranged horizontally, vertically, or in a zigzag manner; when the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square manner. arrangement.
  • the present disclosure is not limited herein.
  • the display area may include: a driving structure layer 102 disposed on the base substrate 101 , and a light emitting element 103 disposed on the side of the driving structure layer 102 away from the base substrate 101 . and the encapsulation layer 104 disposed on the side of the light-emitting element 103 away from the base substrate 101 .
  • the display area may include other film layers, such as spacer columns, etc., which are not limited in this disclosure.
  • the base substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving structure layer 102 of each sub-pixel may include a plurality of thin film transistors and storage capacitors constituting a pixel driving circuit.
  • FIG. 4 takes one thin film transistor 210 and one storage capacitor 211 included in each sub-pixel as an example for illustration.
  • the driving structure layer 102 includes a semiconductor layer, a first gate metal layer, a second gate metal layer and a source-drain metal layer which are sequentially arranged on the base substrate 101 .
  • the semiconductor layer at least includes: the active layer of the thin film transistor 210; the first gate metal layer at least includes: the gate of the thin film transistor and the first capacitor electrode of the storage capacitor; the second gate metal layer at least includes: the second capacitor electrode of the storage capacitor ;
  • the source-drain metal layer at least includes: the source electrode and the drain electrode of the thin film transistor.
  • a first insulating layer 11 is arranged between the base substrate and the semiconductor layer, a second insulating layer 12 is arranged between the semiconductor layer and the first gate metal layer, and a third insulating layer is arranged between the first gate metal layer and the second gate metal layer 13.
  • a fourth insulating layer 14 is arranged between the second gate metal layer and the source-drain metal layer, and a fifth insulating layer 15 is arranged between the source-drain metal layer and the light-emitting element 103 .
  • the first insulating layer 11 may also be called a buffer layer
  • the second insulating layer 12 and the third insulating layer 13 may also be called a gate insulating layer
  • the fourth insulating layer 14 may also be called an interlayer insulating layer
  • the fifth insulating layer 15 It can also be called a flat layer.
  • the light emitting element 103 may include: a first electrode 301 , a pixel definition layer 302 , an organic light emitting layer 303 and a second electrode 304 .
  • the first electrode 301 is connected to the drain electrode of the thin film transistor 210 through a via hole
  • the organic light-emitting layer 303 is connected to the first electrode 301
  • the second electrode 304 is connected to the organic light-emitting layer 303
  • the organic light-emitting layer 303 is between the first electrode 301 and the second electrode 301.
  • the electrodes 304 are driven to emit light of corresponding colors.
  • the first electrode 301 is an anode and the second electrode 304 is a cathode.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the external water vapor cannot enter the light-emitting element 103 .
  • the organic light emitting layer 303 may include a stacked hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), an electron blocking layer (EBL, Electron Block Layer) ), light emitting layer (EML, Emitting Layer), hole blocking layer (HBL, Hole Block Layer), electron transport layer (ETL, Electron Transport Layer) and electron injection layer (EIL, Electron Injection Layer).
  • HIL Hole Injection Layer
  • HTL Hole Injection Layer
  • EBL Electron Block Layer
  • EML Emitting Layer
  • hole blocking layer HBL, Hole Block Layer
  • ETL Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and electron injection layer of all subpixels may be a common layer connected together
  • the hole transport layer and electron transport layer of all subpixels may be a common layer connected together
  • all subpixels may be a common layer connected together.
  • the hole blocking layer may be a common layer connected together, and the light emitting layer and the
  • the pixel driving circuit may be a 7T1C structure.
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to at least one embodiment of the present disclosure.
  • the pixel driving circuit may include 7 thin film transistors (first transistor T1 to seventh transistor T7 ), 1 storage capacitor Cst and 8 signal lines (data signal line D, first scan signal line S1 , The second scanning signal line S2, the light emitting signal line E, the first initial signal line INIT1, the second initial signal line INIT2, the first power supply line VSS and the second power supply line VDD).
  • the first end of the storage capacitor Cst is connected to the second power line VDD, the second end of the storage capacitor Cst is connected to the first node N1, that is, the second end of the storage capacitor Cst is connected to the third transistor T3 control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the second initial signal line INIT2, and the second electrode of the first transistor is connected to the first node N1.
  • the first transistor T1 transmits the second initialization voltage to the gate of the third transistor T3 to initialize the charge amount of the gate of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scan signal line S1
  • the first electrode of the second transistor T2 is connected to the first node N1
  • the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the first node N1, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor Cst, the first electrode of the third transistor T3 is connected to the second node N2, and the third transistor T3 is connected to the second node N2.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the second power supply line VDD and the first power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and enables the data voltage of the data signal line D to be input to the pixel driving circuit when an on-level scan signal is applied to the first scan signal line S1.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the second power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When an on-level light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 make the light emitting element emit light by forming a driving current path between the second power supply line VDD and the first power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the first initial signal line INIT1, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element.
  • the seventh transistor T7 transmits the first initialization voltage to the first electrode of the light emitting element to initialize the amount of charge accumulated in the first electrode of the light emitting element or The amount of charge accumulated in the first electrode of the light-emitting element is released.
  • the second electrode of the light-emitting element is connected to the first power supply line VSS, the signal of the first power supply line VSS is a low-level signal, and the signal of the second power supply line VDD is a high-level signal continuously provided.
  • the first scan signal line S1 is the scan signal line in the pixel driving circuit of the display row
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scan signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display line is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display line
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, the first initial signal line INIT1 and the second initial signal line INT2 may be along the first direction F1 extension.
  • the second power supply line VDD and the data signal line D may extend in the second direction F2.
  • FIG. 6 is an operation timing diagram of a pixel driving circuit according to at least one embodiment of the present disclosure. Exemplary embodiments of the present disclosure will be described below through the operation process of the pixel driving circuit illustrated in FIG. 5 .
  • the pixel driving circuit in FIG. 5 includes 7 transistors (the first transistor T1 to the seventh transistor T7 ), 1 storage capacitors Cst and 8 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, first initial signal line INIT1, second initial signal line INIT2, first power supply line VSS and second power supply line VDD), all 7 transistors are P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are a high-level signal.
  • the signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1, and the signal of the second initial signal line INIT2 is supplied to the first node N1 to initialize the storage capacitor Cst and clear the original storage capacitor Cst. data voltage.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the light is emitted at this stage. Components do not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are a high-level signal
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scan signal line S1 is a low-level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage output from the data signal line D is provided to the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 to the first A node N1, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst, and the voltage of the second end (the first node N1) of the storage capacitor Cst is Vd-
  • , Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3.
  • the seventh transistor T7 is turned on, so that the first initial voltage of the first initial signal line INIT1 is supplied to the first electrode of the light-emitting element, the first electrode of the light-emitting element is initialized (reset), the internal pre-stored voltage is cleared, and the initialization is completed , to ensure that the light-emitting element does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, so that the first transistor T1 is turned off.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are a high-level signal.
  • the signal of the light-emitting signal line E is a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the second power supply line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 supplies a driving voltage to the first electrode of the light-emitting element to drive the light-emitting element to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the second power line VDD.
  • the voltages of the first node N1 and the fourth node N4 are controlled by the second initial signal line INIT2 and the first initial signal line INIT1, respectively.
  • the first initial voltage provided by the first initial signal line INIT1 is different from the second initial voltage provided by the second initial signal line INIT2.
  • the first initial signal line INIT1 is connected to the first power line VSS, that is, the first initial voltage provided by the first initial signal line INIT1 is equal to the first power voltage provided by the first power line VSS.
  • the first node N1 and the fourth node N4 are respectively provided with different initial voltages by adopting a double initial signal line, so as to avoid the problems caused when the first node and the fourth node are controlled by the same initial signal line.
  • a double initial signal line so as to avoid the problems caused when the first node and the fourth node are controlled by the same initial signal line.
  • the problem of low grayscale image quality is affected by the pressure drop existing in the area and the opening area near the first frame area.
  • the first power supply line VSS can be used to provide the first initial voltage, thereby avoiding the introduction of the first initial voltage in the binding pin area.
  • the second border area 300 includes a first edge area 300 a located on the right side of the display area 100 , a second edge area 300 b located on the upper side of the display area 100 , and a second edge area 300 b located on the upper side of the display area 100 .
  • the third edge area 300c on the left side of the display area 100 is displayed.
  • the first edge area 300 a , the second edge area 300 b , the third edge area 300 c and the first frame area 200 are connected and surround the periphery of the display area 100 .
  • the first edge area 300a may be the right frame of the display substrate
  • the second edge area 300b may be the upper frame of the display substrate
  • the third edge area 300c may be the left frame of the display substrate.
  • the display area 100 is provided with a plurality of first initial signal lines INIT1 parallel to each other.
  • Each of the first initial signal lines INIT1 is configured to provide a first initial voltage to the pixel driving circuit of each row of sub-pixels.
  • the plurality of first initial signal lines INIT1 in the display area 100 may extend along the first direction F1 and be sequentially arranged along the second direction F2. In some examples, taking the pixel driving circuit shown in FIG.
  • the first scan signal line S1 , the second scan signal line S2 , the first initial signal line INIT1 , and the second initial signal line INIT2 and the light emitting signal line E extend along the first direction F1
  • the data signal line D and the second power supply line VDD extend along the second direction F2
  • the first scanning signal line S1, the light emitting signal line E, the second initial signal line INIT2 may be sequentially arranged along the second direction F2.
  • this embodiment does not limit this.
  • the first initial signal line INIT1 may extend from the display area 100 to the first and third edge areas 300 a and 300 c of the second bezel area 300 .
  • the first initial signal line INIT1 has a first extension end extending to the first edge region 300a, and a second extension end extending to the third edge region 300c.
  • this embodiment does not limit this.
  • the first initial signal line INIT1 may extend to one side edge region to receive the first initial voltage.
  • the second frame region 300 is provided with a first power supply line VSS, a first connection line 501 and a second connection line 502 .
  • the first power line VSS may be disposed in the first edge region 300a, the second edge region 300b and the third edge region 300c, and the first connection line 501 and the second connection line 502 may be disposed in the first edge region 300a and the third edge region 300c.
  • the first connection line 501 is connected to a plurality of first initial signal lines INIT1 of the display area 100 through the second connection line 502 , and the first connection line 501 is connected to the first power supply line VSS, so as to realize the first power supply line VSS and the display area 100 electrical connection between the first initial signal line INIT1 within.
  • the first connection line 501 is located on the side of the second connection line 502 away from the display area 100
  • the first power supply line VSS is located at the side of the first connection line 501 away from the display area 100
  • the second connection line 502 and the first power supply line VSS may be of the same layer structure, and the first connection line 501 is located on a side of the first power supply line VSS away from the base substrate.
  • this embodiment does not limit this.
  • the first power supply line VSS is connected to the pins in the binding pin area 400 to obtain the first power supply voltage provided externally.
  • the first power supply line VSS is disposed at the periphery of the display area 100 in the first edge region 300a, the second edge region 300b and the third edge region 300c.
  • both the first edge region 300a and the third edge region 300c are provided with a first connection line 501 and a second connection line 502 .
  • the first edge region 300a the first extension ends of the plurality of first initial signal lines INIT1 are connected to the first power line VSS through the second connection line 502 and the first connection line 501.
  • the second extension ends of the plurality of first initial signal lines INIT1 are connected to the first power line VSS through the second connection line 502 and the first connection line 501.
  • the first connection line and the second connection line may be provided only in the first edge region 300a or the third edge region 300c to realize the connection between the first initial signal line INIT1 and the first power supply line VSS.
  • the first connection line 501 and the second connection line 502 in the second frame area 300 may extend along the edge of the display area 100 .
  • the first connection line 501 and the second connection line 502 within the first edge region 300a and the third edge region 300c may extend along the second direction F2.
  • the first connection line 501 is directly connected to the first power supply line VSS, and the orthographic projection of the first connection line 501 on the base substrate partially overlaps the first power supply line VSS.
  • the second connection line 502 is connected to the first connection line 501 and the plurality of first initial signal lines INIT1.
  • the first connection line 501 and the first electrode of the light-emitting element of the display area 100 may be of the same layer structure.
  • the first power line VSS and the source-drain metal layer of the display area 100 may be of the same layer structure.
  • the second connection line 502 and the first power supply line VSS are of the same layer structure.
  • the first initial signal line INIT2 and the second gate metal layer of the display area 100 are of the same layer structure. However, this embodiment does not limit this.
  • the connection between the first power line VSS and the first initial signal line INIT1 is realized through the first connection line 501 and the second connection line 502 in the second frame area 300 , and there is no need to bind the pin area 400 increases the pins for introducing the first initial voltage, without increasing the wiring space for introducing the first initial voltage in the first frame area 200 , which can avoid increasing the area of the first frame area 200 and the binding pin area 400 .
  • FIGS. 8 and 9 are partially enlarged schematic views of the area S1 in FIG. 7 .
  • 8 is a partial schematic diagram of a third edge region after forming the first connection line according to at least one embodiment of the present disclosure.
  • FIG. 9 is a partial schematic diagram of a third edge region after forming a second connection line according to at least one embodiment of the present disclosure.
  • FIGS. 8 and 9 only the positions of the light-emitting driving circuit and the scanning driving circuit are shown, and the detailed circuit structures are omitted.
  • first power lines are sequentially arranged in the third edge area 300 c
  • the initial signal lead 600 is connected to the extension ends of the plurality of second initial signal lines INIT2 in the third edge region 300c.
  • the initial signal lead 600 is connected to the bonding pin in the bonding pin area 400 to obtain the second initial voltage provided externally.
  • the extending direction of the second connection line 502 and the initial signal lead 600 is the same, for example, extending along the second direction F2.
  • the second connection line 502 is located on the side of the initial signal line 600 away from the display area 100 .
  • this embodiment does not limit this.
  • the second connection line 502 may be located on a side of the initial signal line 600 close to the display area 100 .
  • the trace width of the second connection line 502 may be approximately the same as the trace width of the initial signal lead 600 .
  • the trace width of the first power supply line VSS may be larger than the trace width of the second connection line 502 and larger than the trace width of the initial signal lead 600 .
  • the trace width of the second connection line 502 is about 3um to 30um, for example, it may be about 13um.
  • the trace width of the initial signal lead 600 is about 3um to 30um, for example, about 13um.
  • the distance between the second connection line 502 and the initial signal lead 600 is about 1 um to 15 um, for example, 4 um.
  • the trace width of the first power line VSS in the third edge region 300c is about 20um to 500um, for example, about 270um.
  • the trace width refers to the characteristic size of the trace in the vertical direction of the extending direction.
  • the scan driver may include scan driving circuits 61 arranged in the first edge region 300a and the third edge region 300c, respectively.
  • the light-emitting driver may include light-emitting driving circuits 62 arranged in the first edge region 300a and the third edge region 300c, respectively.
  • the scan driving circuit 61 may include a plurality of cascaded scan GOA units. The plurality of scan GOA units may provide scan signals (e.g., including a first scan signal and a second scan signal) to the pixel array of the display area 100.
  • each scan GOA unit may be connected to a first scan signal line of a row of sub-pixels in the display area 100 through a scan wire 601, configured to provide a first scan signal to a row of sub-pixels, and be connected to a row of sub-pixels with a first scan signal.
  • the second scan signal line is connected and configured to provide the second scan signal to the sub-pixels in the upper row.
  • the light-emitting driving circuit may include a plurality of cascaded light-emitting GOA units, and the plurality of light-emitting GOA units may provide light-emitting signals to the display area 100 .
  • Each light-emitting GOA unit is connected to a light-emitting signal line of a row of sub-pixels in the display area 100 through a light-emitting lead 602, and is configured to provide a light-emitting signal to a row of sub-pixels.
  • the second connection line 502 , the initial signal lead 600 and the first power supply line VSS may be of the same layer structure, for example, the same layer structure as the source-drain metal layer of the display area 100 .
  • the plurality of first initial signal lines INIT1 connected to the second connection line 502 , the plurality of second initial signal lines INIT2 connected to the initial signal lead 600 , the scanning lead 601 and the light emitting lead 602 may be of the same layer structure, such as those of the display area 100 .
  • the second gate metal layer is of the same layer structure.
  • the first scan signal line and the second scan signal line connected by the scan lead 601 and the light emitting signal line connected by the light emitting lead 602 are of the same layer structure, for example, the same layer structure as the first gate metal layer of the display area 100 .
  • the scan lead 601 can be connected to the first scan signal line and the second scan signal line through the via hole on the second insulating layer, and the light emitting lead 602 can be connected to the light emitting signal line through the via hole on the second insulating layer.
  • this embodiment does not limit this.
  • the first connection wire 501 may have a plurality of hollow parts, so that the first connection wire 501 is formed with slits.
  • the bulging phenomenon caused by the first connecting wire covering a large area of the fifth insulating layer made of an organic insulating material
  • the positions of the plurality of hollow portions of the first connection line 501 correspond to the positions of the first isolation dams.
  • the overlapping area of the first connection line 501 and the first power supply line VSS covers the location of the first isolation dam, which can increase the contact area between the first connection line 501 and the first power supply line VSS, and through the
  • the first connecting line is provided with a hollow portion, which can realize the effective connection between the first connecting line 501 and the first power line VSS.
  • the first connection line 501 and the first electrode of the light emitting element of the display area 100 are of the same layer structure, and the first power supply line VSS and the source-drain metal layer of the display area 100 are of the same layer structure.
  • a flat layer (that is, the above-mentioned fifth insulating layer) is provided between the first power supply line VSS and the first connection line 501, and the first power supply line VSS and the first connection can be realized through the first groove opened on the flat layer.
  • a valid connection between lines 501 is provided between the first power supply line VSS and the first connection line 501, and the first power supply line VSS and the first connection can be realized through the first groove opened on the flat layer.
  • FIG. 10 is a schematic partial cross-sectional view along the P-P direction in FIG. 8 .
  • the first initial signal line INIT1 is provided on the third insulating layer 13
  • the second connection line 502 is connected to the third insulating layer 14 through the first via K1 provided on the fourth insulating layer 14 .
  • An initial signal line INIT1 is connected.
  • the first connection line 501 is connected to the second connection line 502 through the second groove K2 provided on the fifth insulating layer 15 .
  • the fifth insulating layer 15 in the peripheral region is provided with a first groove and a second groove
  • the first connection line 501 can be connected to the first power line VSS through the first groove
  • the second groove connected to the second connection line 502 .
  • FIG. 11 is a partial schematic view of the upper left corner of the display substrate shown in FIG. 7 .
  • FIG. 11 is a partial schematic diagram of the boundary position of the second edge region 300b and the third edge region 300c shown in FIG. 7 .
  • the first connection line 51 and the second connection line 52 are not provided in the second edge region 300b.
  • the first initial signal line INIT1 extends from the left and right sides of the display area 100 and is connected to the first power line VSS.
  • the second connection line 502 in the third edge area 300c may extend along the upper left corner edge of the display area 100, for example, the extension direction of the second connection line 502 at the upper left corner and the extension direction of the second connection line 502 of the third edge area 300c The direction of extension is crossed.
  • the first connection line 501 may not need to extend to the upper left corner position. Since the second connection line 502 is connected to the first connection line 501 in the third edge region 300c, the second connection line 502 only needs to extend to the upper left corner to be connected to the first initial signal line INIT1.
  • the wiring structure at the boundary position between the second edge region and the first edge region (ie, the upper right corner position) can be referred to as shown in FIG. 11 , so it will not be repeated here.
  • FIG. 12 is a partial schematic view of the lower left corner of the display substrate shown in FIG. 7 .
  • FIG. 12 is a partial schematic diagram of the boundary position between the third edge area and the first frame area shown in FIG. 7 .
  • the second connection line 502 may extend from the first frame area 200 into the third edge area 300c.
  • the pin connected to the second connection line 502 does not need to be set in the binding pin area.
  • a side of the second connection line 502 close to the display area 100 is provided with an initial signal lead 600 and a second power supply line VDD.
  • the initial signal leads 600 may extend from the bonding pin area 400 through the first frame area 200 to the third edge area 300c.
  • the first connection line 501 may extend to the lower left corner and be connected with the second connection line 502 .
  • the wiring structure of the boundary position between the first edge area and the first frame area (ie, the lower right corner position) can be referred to as shown in FIG. 12 , so it will not be repeated here.
  • the structure of the display substrate of the present disclosure will be described below with reference to FIGS. 4 , 8 to 12 through an example of a manufacturing process of the display substrate.
  • the "patterning process” referred to in the present disclosure includes processes such as depositing film layers, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • Deposition can be selected from any one or more of sputtering, evaporation and chemical vapor deposition
  • coating can be selected from any one or more of spray coating and spin coating
  • etching can be selected from dry etching. and any one or more of wet engraving.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
  • the "film” can also be referred to as a "layer”.
  • the "film” needs a patterning process during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • a and B are of the same layer structure
  • a and B are simultaneously formed through the same patterning process.
  • the same layer does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.
  • the preparation process of the display substrate of this embodiment may include the following steps (1) to (8).
  • the base substrate 101 is a rigid substrate, such as a glass substrate, or a flexible substrate.
  • this embodiment does not limit this.
  • a first insulating film and a semiconductor film are sequentially deposited on the base substrate 101, the semiconductor film is patterned through a patterning process to form the first insulating layer 11 covering the entire base substrate 10, and the first insulating layer 11 is formed on the base substrate 10.
  • the semiconductor layer pattern on the first insulating layer 11 As shown in FIG. 4 , the semiconductor layer pattern is formed in the display area 100 and includes at least the first active layer.
  • a second insulating film and a first metal film are sequentially deposited on the base substrate 101 on which the above structure is formed, and the first metal film is patterned through a patterning process to form a second layer covering the semiconductor layer pattern.
  • the insulating layer 12 and the first gate metal layer disposed on the second insulating layer 12 are shown in FIG. 4 .
  • the first gate metal layer pattern is formed in the display area 100 and includes at least a first gate electrode and a first capacitor electrode. In this step, the first scan signal line, the second scan signal line, and the light-emitting signal line may be formed in the display area 100 synchronously.
  • a third insulating film and a second metal film are sequentially deposited on the base substrate 101 on which the above structure is formed, the second metal film is patterned through a patterning process to form the third insulating layer 13 , and The second gate metal layer, the first initial signal line, and the second initial signal line pattern are disposed on the third insulating layer 13 .
  • the second gate metal layer pattern is formed in the display area 100 and includes at least a second capacitor electrode.
  • the first and second initial signal lines INIT1 and INIT2 may extend from the display area 100 to the first and third edge areas 300a and 300c.
  • a fourth insulating film is deposited on the base substrate 101 on which the above structure is formed, and the fourth insulating film is patterned through a patterning process to form a layer covering the second gate metal, the first initial signal line and the The fourth insulating layer 14 pattern of the second initial signal line pattern.
  • at least a plurality of first via holes and a plurality of second via holes are opened on the fourth insulating layer 14 .
  • a plurality of second via holes are located in the display area 100, exposing the surface of the first active layer.
  • a plurality of first via holes K1 are located in the first edge region 300a and the third edge region 300c, exposing the surfaces of the first initial signal line INIT1 and the second initial signal line INIT2.
  • a third metal thin film is deposited on the base substrate 101 forming the above structure, the third metal thin film is patterned through a patterning process, and a source-drain metal layer, a third metal thin film are formed on the fourth insulating layer 14 A power supply line VSS and a second connection line 502 and an initial signal lead 600 pattern.
  • a source-drain metal layer pattern is formed in the display area 100 and includes at least a first source electrode, a first drain electrode, and a plurality of patterns of data lines (not shown). The first source electrode and the first drain electrode are respectively connected with the source region and the drain region of the first active layer through the second via hole. As shown in FIG. 8 to FIG.
  • the second connection line 502 can be connected to the first initial signal line INIT1 through the first via K1.
  • the initial signal lead 600 It can be connected to the second initial signal line INIT2 through the first via hole K1.
  • the driving structure layer of the display area 100 is prepared on the base substrate 101 , as shown in FIG. 4 .
  • the first active layer, the first gate electrode, the first source electrode and the first drain electrode form a thin film transistor 210
  • the first capacitor electrode and the second capacitor electrode form a storage capacitor 211 .
  • the first to fourth insulating films are all made of inorganic materials, for example, any one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) or More, can be single layer, multi-layer or composite layer.
  • a flat thin film is coated, and a fifth insulating layer is formed through a patterning process.
  • the fifth insulating layer is provided with a plurality of third via holes, first grooves and second grooves. As shown in FIG. 4 , the third via hole is formed in the display area 100 to expose the surface of the first drain electrode of the thin film transistor 210 . As shown in FIG. 8 and FIG.
  • the first groove and the second groove K2 are formed in the peripheral area, and the fifth insulating layer 15 in the first groove is etched away, exposing the surface of the first power supply line VSS, The fifth insulating layer in the second groove K2 is etched away, exposing the surface of the second connection line 502 .
  • a first conductive film is deposited, and the first conductive film is patterned through a patterning process to form a pattern of a first electrode and a first connection line 501 of the light-emitting element.
  • the first electrode 301 of the light-emitting element is formed in the display area 100 , and the first electrode 301 is connected to the first drain electrode of the thin film transistor 210 through the third via hole on the fifth insulating layer 15 .
  • the first connection line 501 is formed in the peripheral area, connected to the first power supply line VSS through the first groove, and connected to the second connection line 502 through the second groove K2.
  • a pixel-defining film is coated, and a pattern of the pixel-defining layer 302 is formed by masking, exposing, and developing processes. As shown in FIG. 4 , the pixel definition layer 302 is formed in the display area 100 . Pixel openings are formed on the pixel defining layer 302 of the display area 100 , and the pixel defining film in the pixel opening is developed to expose the surface of the first electrode 301 .
  • an organic light-emitting layer 303 and a second electrode 304 are sequentially formed on the base substrate 101 on which the aforementioned pattern is formed.
  • the organic light-emitting layer 303 includes a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer, and is formed in the pixel opening of the display area 100 to realize the organic light-emitting layer 303 and the first electrode. 301 connect. Since the first electrode 301 is connected to the first drain electrode of the thin film transistor 210, the light emission control of the organic light emitting layer 303 is realized. A portion of the second electrode 304 is formed on the organic light emitting layer 303 .
  • an encapsulation layer 104 is formed on the base substrate 101 on which the aforementioned patterns are formed.
  • the encapsulation layer 104 may adopt a laminated structure of inorganic material/organic material/inorganic material.
  • the organic material layer is disposed between the two inorganic material layers.
  • the fifth insulating layer 15 and the pixel defining layer 302 may be organic materials such as polyimide, acrylic, or polyethylene terephthalate.
  • the preparation process of the scan driving circuit and the light-emitting driving circuit is similar to the preparation process of the driving structure layer of the display area, so it is not repeated here.
  • the preparation process of this exemplary embodiment can be realized by using the existing mature preparation equipment, and can be well compatible with the existing preparation process.
  • the process is simple to realize, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the structure of the display substrate of the present exemplary embodiment and the manufacturing process thereof are merely an exemplary illustration.
  • corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs.
  • the display area may be provided with a first source-drain metal layer and a second source-drain metal layer
  • the first source-drain metal layer may include the first source electrode and the first drain electrode of the thin film transistor
  • the second source-drain metal layer may include light-emitting A connection electrode between the element and the first drain electrode.
  • the first connection line and the second source-drain metal layer may be of the same layer structure
  • the first power supply line and the second connection line may be of the same layer structure as the first source-drain metal layer.
  • this embodiment does not limit this.
  • connection between the first initial signal line and the first power supply line is realized by arranging the first connection line and the second connection line in the first edge region and the third edge region on opposite sides of the display area.
  • This embodiment can greatly improve the uniformity of the display substrate under high and low gray scales without increasing the wiring space in the first frame area and the pins in the pin binding area, thereby improving the picture quality.
  • FIG. 13 is another schematic diagram of wirings in the peripheral region of the display substrate according to at least one embodiment of the disclosure.
  • the first initial signal line INIT1 disposed in the display area 100 may extend along the second direction F2, and the plurality of first initial signal lines INIT1 may be arranged along the first direction F1 .
  • this embodiment does not limit this.
  • the extending direction of the second initial signal line INIT2 provided in the display area 100 may be the same as the extending direction of the first initial signal line INIT1, for example, extending along the second direction F2;
  • the extending directions of the initial signal lines INIT1 intersect, for example, the second initial signal lines INIT2 extend in the first direction F1, and the first initial signal lines INIT1 extend in the second direction F2.
  • the first initial signal line INIT1 may extend from the display area 100 to the second edge area 300b of the second frame area (eg, the upper frame of the display substrate).
  • the first initial signal line INIT1 has a first extension end extending to the second edge region 300b.
  • the second frame area is provided with a first power line VSS and a first connection line 501 . Since the first edge region 300a, the second edge region 200b and the third edge region 300c are all provided with the first power supply lines VSS, the plurality of first initial signal lines INIT1 can be connected to the second edge region 300b through the first connection lines 501 and the first power line VSS.
  • the first extension end of the first initial signal line INIT1 is connected to the first end of the first connection line 501
  • the second end of the first connection line 501 is connected to the first power supply line VSS.
  • the first power line VSS is located on the side of the first connection line 501 away from the display area 100
  • the first connection line 501 is located at the side of the first initial signal line INIT1 away from the display area 100 .
  • the orthographic projection of the first connection line 501 on the base substrate overlaps with the first power supply line and the plurality of first initial signal lines INIT1 of the VSS.
  • this embodiment does not limit this.
  • the second edge region 300b may further be provided with a second connection line, the extension direction of the second connection line is consistent with the extension direction of the first connection line, and the second connection line is connected to the first power line through the first connection line, The second connection line is connected to the first initial signal line.
  • the second connection line and the first power line may be of the same layer structure.
  • the driving structure layer of the display area 100 includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first gate metal layer, a first gate metal layer, a first a source-drain metal layer and a second source-drain metal layer.
  • the first source-drain metal layer may include a first source electrode and a first drain electrode of the thin film transistor
  • the second source-drain metal layer may include a connection electrode between the light-emitting element and the first drain electrode.
  • the first connection line 501 located in the second edge region 300b may be in the same layer structure as the first electrode of the light-emitting element.
  • the first initial signal line INIT1 and the first source-drain metal layer may have the same layer structure, and the extension direction of the first initial signal line INIT1 may be parallel to the extension direction of the data signal line.
  • the first initial signal line INIT1 and the second source-drain metal layer may be in the same layer structure, or may be provided in the same layer as the semiconductor layer.
  • this embodiment does not limit this.
  • the first initial signal lines are disposed on other conductive film layers that do not overlap with the scan signal lines.
  • connection between the first initial signal line and the first power line in the second edge region (ie, the upper frame) of the display substrate it is possible to avoid the first edge region and the second edge region ( That is, the left and right borders of the display area) design the connection structure to achieve a narrow border.
  • FIG. 14 is another schematic diagram of wiring in the peripheral region of the display substrate according to at least one embodiment of the disclosure.
  • 15 and 16 are partially enlarged schematic views of the area S2 in FIG. 14 .
  • FIG. 17 is a schematic partial cross-sectional view along the R-R direction in FIG. 15 .
  • 15 is a partial schematic diagram of a third edge region after forming the first connection line according to at least one embodiment of the disclosure.
  • 16 is a partial schematic diagram of a third edge region after forming a first power line according to at least one embodiment of the present disclosure.
  • the second frame area 300 is provided with a first connection line 501 .
  • the first connection line 501 connects the first power supply line VSS and the plurality of first initial signal lines INIT1.
  • the first connection line 501 may not be provided in the second edge region 300b.
  • the first connection line 501 is connected to the first power supply line VSS through the first groove provided on the fifth insulating layer 15 , and is connected to the first power supply line VSS through the fifth insulating layer 15 and The second groove of the fourth insulating layer 14 is connected to the first initial signal line INIT1.
  • the material of the first connection line 501 may be the same material as the anode of the organic light-emitting layer, for example, may be indium tin oxide (ITO), or a stack of Ag/ITO/Ag.
  • ITO indium tin oxide
  • the first connection line 501 may be fabricated in the same layer as the anode of the organic light-emitting layer.
  • connection between the first initial signal line and the first power line is realized by arranging the first connection lines in the first edge region and the third edge region on opposite sides of the display area.
  • This embodiment can greatly improve the uniformity of the display substrate under high and low gray scales without increasing the wiring space in the first frame area and the pins in the pin binding area, thereby improving the picture quality.
  • the first initial signal line INIT1 in the present exemplary embodiment may extend along the second direction F2, and is connected to the first power supply line VSS through the first connection line 501 in the second edge region 300b.
  • FIG. 18 and 19 are another partial enlarged schematic diagram of the area S2 in FIG. 14 .
  • FIG. 20 is a schematic partial cross-sectional view along the Y-Y direction in FIG. 18 .
  • 18 is a partial schematic diagram of a third edge region after forming the first connecting sub-line according to at least one embodiment of the disclosure.
  • FIG. 19 is a partial schematic diagram of a third edge region after forming a second connecting sub-line according to at least one embodiment of the present disclosure.
  • the second frame area 300 is provided with a first connection line.
  • the first connection line is a multi-layer structure.
  • the first connection line includes a first connection sub-line 501a and a second connection sub-line 501b.
  • the first connection lines are disposed in the first edge region 300a and the third edge region 300c.
  • the second connection sub-line 501b is connected to the first power supply line VSS and the plurality of first initial signal lines INIT1, and the first connection sub-line 501a is connected to the second connection sub-line 501b.
  • the driving structure layer of the display area 100 includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially arranged on the base substrate.
  • the first connection sub-wire 501a and the first electrode of the light-emitting element are in the same layer structure
  • the second connection sub-wire 501b and the second source-drain metal layer are in the same layer structure
  • the first power supply line VSS and the first source-drain metal layer are in the same layer structure.
  • Layer structure, the first initial signal line INIT1 and the second gate metal layer are of the same layer structure. As shown in FIGS.
  • the first connection sub-wire 501a is connected to the second connection sub-wire 501b through the groove on the sixth insulating layer 16.
  • the second connection sub-line 501b is connected to the first initial signal line INIT1 through a via hole penetrating the fifth insulating layer 15 and the fourth insulating layer 14 .
  • the fifth insulating layer 15 and the sixth insulating layer 16 may be flat layers prepared using organic materials.
  • the second connection sub-line 501b may cover the area where the light-emitting driving circuit 62 and the scanning driving circuit 61 are located, and extend above the first initial signal line INIT1, and connect to a plurality of first initial signals through via holes Line INIT1 is connected.
  • the second connection sub-line 501b also extends above the first power supply line VSS, and is connected to the first power supply line VSS through the groove on the fifth insulating layer.
  • the second connection sub-line 501b may connect the first power supply line VSS and the first initial signal line INIT1.
  • this embodiment does not limit this.
  • the second connection sub-line may only be connected to the first power supply line VSS, and the first initial signal line INIT1 and the second connection sub-line are connected by the first connection sub-line to realize the connection between the first power supply line VSS and the first initial signal line INIT1
  • the second connection sub-line can only be connected to the first initial signal line INIT1
  • the first connection sub-line connects the second connection sub-line and the first power line to realize the first power line VSS and the first initial signal line Electrical connection for INIT1.
  • the use of the second connection sub-line in the same layer structure as the second source-drain metal layer can facilitate the overlap between different lines.
  • Multi-layer bonding can reduce resistance and provide signal transmission performance.
  • the first connecting sub-wire 501a may be made of the same material as the anode of the organic light-emitting layer, for example, may be ITO, or a stack of Ag/ITO/Ag.
  • the first connecting sub-wire 501a can be fabricated in the same layer as the anode of the organic light-emitting layer.
  • the material of the second connection sub-wire 501b may include a metal material, for example, may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or a laminate, etc., or Can be a titanium/aluminum/titanium stack.
  • a metal material for example, may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or a laminate, etc., or Can be a titanium/aluminum/titanium stack.
  • the material of the first power supply line VSS may include a metal material, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or a laminate, etc., or it may be It is a titanium/aluminum/titanium stack.
  • the material of the second connection sub-line 501b can also be the same material as other metal film layers in the pixel driving circuit, or made in the same layer, for example, can be the same layer as the gate metal layer, or the same material can be used .
  • the material of the second connection sub-wire 501b can be made of the same material and/or the same layer as the gate electrode of the oxide transistor, for example, the material can be molybdenum , aluminum, copper, titanium, niobium, one of them or alloys, or molybdenum/titanium alloys or laminates, etc.
  • the structures (or methods) shown in this embodiment mode can be appropriately combined with the structures (or methods) shown in other embodiments.
  • the first initial signal line INIT1 in the present exemplary embodiment may extend along the second direction F2, and the first connection sub-line and the second connection sub-line may be disposed in the second edge region 300b to realize the first power supply line VSS Electrical connection to the first initial signal line INIT1.
  • a second connection line may also be provided in the second frame area, and the second connection line may be the same as the first source-drain metal layer.
  • FIG. 21 is another schematic diagram of wirings in the peripheral region of the display substrate according to at least one embodiment of the disclosure.
  • FIG. 22 is a partial enlarged schematic view of the area S3 in FIG. 21 .
  • the first frame area 200 is located between the binding pin area 400 and the display area 100 .
  • the first frame area 200 may include: a first fan-out area, a bending area, a second fan-out area, an anti-static area and a driving chip area.
  • a third connection line 503 is provided in the first frame area 200 and the second frame area.
  • the third connection line 503 is connected to the first initial signal line INIT1 in the first edge region 300 a and the third edge region 300 c of the second frame region, and is connected to the first power line VSS in the first frame region 200 .
  • the third connection line 503 and the first power supply line VSS have an integral structure, and the connection position of the third connection line 503 and the first power supply line VSS may be located in the first frame area 200 .
  • the extending direction of the third connection line 503 in the first edge region 300 a and the third edge 300 c crosses the extending direction of the first initial signal line INIT1 in the display area 100 .
  • FIG. 22 is a schematic diagram showing the wiring at the lower left corner of the display substrate.
  • the third connection line 503 is located on the side of the initial signal lead 600 away from the display area 100
  • the initial signal lead 600 is located on the side of the second power line VDD away from the display area 100 . side.
  • the first power supply line VSS is divided into two paths, one of which forms a third connection line 503 connected to the first initial signal line INIT1 at the second extension end of the third edge region 300c, The other line still enters the third edge region 300c as the first power line VSS.
  • signal lines provided to the scan driving circuit and the light emitting driving circuit are provided.
  • a third power supply line VGH, a fourth power supply line VGL, a first signal line group provided to the light-emitting GOA unit, and a first signal line group provided to the scanning GOA unit are sequentially arranged on the side of the first power supply line VSS close to the display area 100
  • the first signal line group may include: a first start signal line ESTV and clock signal lines ECB and ECK.
  • the second signal line group includes: a second start signal line GSTV and clock signal lines GCB and GCK.
  • the third power line VGH, the fourth power line VGL, the clock signal lines GCB and GCK may be in the same layer structure as the second gate metal layer of the display area; the first start signal line ESTV and the clock signal lines ECB and The ECK and the first gate metal layer in the display area may be of the same layer structure; the second start signal line GSTV may be of the same layer structure as the first gate metal layer, and connected to the wiring of the same layer as the second gate metal layer, so as to Receive a scan start signal.
  • the first initial signal line may extend along the second direction
  • the third connection line may be disposed in the first edge region, the second edge region and the third edge region
  • the first initial signal line may be located in the first edge region, the second edge region and the third edge region.
  • the second edge region is connected to the third connection line.
  • the first initial signal line may be connected to the first power line at the second edge region.
  • FIG. 23 is another schematic diagram of wiring in the peripheral region of the display substrate according to at least one embodiment of the disclosure.
  • FIG. 24 is a partial enlarged schematic view of the area S4 in FIG. 23 .
  • FIG. 25 is a schematic cross-sectional view along the Q-Q direction in FIG. 24 . In some exemplary embodiments, as shown in FIG.
  • the third connection line 503 is connected to the first initial signal line INIT1 in the first edge region 300 a and the third edge region 300 c of the second frame region 300 , and in the first edge region 300 a and the third edge region 300 c of the second frame region 300
  • the border region 200 , the boundary position of the first border region 200 and the third edge region 300 c , or the third edge region 300 c is connected to one end of the fourth connection line 504 .
  • the other end of the fourth connection line 504 is connected to the first power line VSS in the first frame area 200 .
  • connection position of the fourth connection line 504 and the first power line VSS may be located on a side of the bending region 202 away from the display region 100 .
  • the extension direction of the fourth connection line 504 in the first frame region 200 may be consistent with the extension direction of the clock signal line and the start signal line provided to the scan driving circuit and the light emitting driving circuit.
  • the fourth connection line 504 may be in the same layer structure as the second gate metal layer of the display area 100 , and the first power supply line VSS may be in the same layer structure as the source-drain metal layer of the display area 100 . for the same layer structure.
  • the first power line VSS may be connected to the fourth connection line 504 through a via hole provided on the fourth insulating layer 14 .
  • the fourth connection line 504 can be connected to the third connection line 503 through a via hole provided on the fourth insulating layer.
  • this embodiment does not limit this.
  • the remaining traces on the same layer as the fourth connection wire 504 are omitted.
  • the electrical connection between the fourth connection line and the first power supply line is realized in the first frame area, and the connection between the first power supply line and the first initial signal line through the third connection line and the fourth connection line is realized.
  • the electrical connection can greatly improve the uniformity of the display substrate under high and low gray scales without increasing the wiring space in the first frame area and the pins in the pin binding area, thereby improving the picture quality.
  • the structures (or methods) shown in this embodiment mode can be appropriately combined with the structures (or methods) shown in other embodiments.
  • the first initial signal line may extend along the second direction
  • the third connection line may be disposed in the first edge region, the second edge region and the third edge region
  • the first initial signal line may be located in the first edge region, the second edge region and the third edge region.
  • the second edge region is connected to the third connection line.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, which is used to prepare the display substrate described in the above embodiments.
  • the manufacturing method of the display substrate in this embodiment includes: forming a plurality of sub-pixels in a display area, and forming a first power supply line and a signal connection line in a peripheral area of the periphery of the display area.
  • at least one sub-pixel includes: a pixel driving circuit disposed on the base substrate and a light-emitting element connected to the pixel driving circuit; the pixel driving circuit is connected to a first initial signal line, and the first initial signal line It is configured to provide a first initial voltage to the light-emitting element under the control of the pixel driving circuit.
  • the first initial signal line is connected to the first power line through the signal connection line in the peripheral region.
  • FIG. 26 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • this embodiment provides a display device 91 including: a display substrate 910 .
  • the display substrate 910 is the display substrate provided in the foregoing embodiments.
  • the display substrate 910 may be an OLED display substrate.
  • the display device 91 may be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. However, this embodiment does not limit this.

Abstract

一种显示基板，包括：显示区域（100）和位于显示区域（100）外围的周边区域。显示区域（100）至少设置有多个子像素。至少一个子像素包括：设置在衬底基板上的像素驱动电路和与像素驱动电路连接的发光元件（103）。像素驱动电路与第一初始信号线（INIT1）连接，第一初始信号线（INIT1）配置为在像素驱动电路的控制下，给发光元件（103）提供第一初始电压。周边区域设置有第一电源线（VSS）和信号连接线，第一初始信号线（INIT1）在周边区域通过信号连接线与第一电源线（VSS）连接。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光元件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开至少一实施例提供一种显示基板及其制备方法、显示装置。
一方面，本公开实施例提供一种显示基板，包括：显示区域和位于所述显示区域外围的周边区域。所述显示区域至少设置有多个子像素，至少一个子像素包括：设置在衬底基板上的像素驱动电路和与所述像素驱动电路连接的发光元件；所述像素驱动电路与第一初始信号线连接，所述第一初始信号线配置为在所述像素驱动电路的控制下，给所述发光元件提供第一初始电压。所述周边区域设置有第一电源线和信号连接线，所述第一初始信号线在所述周边区域通过所述信号连接线与所述第一电源线连接。
在一些示例性实施方式中，所述周边区域包括：第一边框区域、第二边框区域和绑定引脚区域，所述绑定引脚区域位于所述显示区域的一侧，所述第一边框区域位于所述绑定引脚区域和所述显示区域之间；所述第二边框区域与第一边框区域连通并围绕所述显示区域。所述信号连接线包括：第一连 接线；所述第一连接线在所述第二边框区域与所述第一初始信号线和所述第一电源线连接。所述第一连接线位于所述第一电源线靠近所述显示区域的一侧。
在一些示例性实施方式中，所述第一连接线位于所述第一电源线远离所述衬底基板的一侧。
在一些示例性实施方式中，所述信号连接线还包括：第二连接线，所述第二连接线与所述第一初始信号线连接，所述第二连接线通过所述第一连接线与所述第一电源线连接。所述第二连接线位于所述第一连接线靠近所述显示区域的一侧。
在一些示例性实施方式中，所述第二连接线位于所述第一连接线靠近所述衬底基板的一侧，且位于所述第一初始信号线远离所述衬底基板的一侧。
在一些示例性实施方式中，所述第二连接线与所述第一电源线为同层结构。
在一些示例性实施方式中，所述第一连接线在所述周边区域内的延伸方向与所述第一初始信号线在所述显示区域内的延伸方向交叉。
在一些示例性实施方式中，所述显示区域包括：设置在所述衬底基板上的驱动结构层和发光元件，所述发光元件包括：第一电极、第二电极和设置在所述第一电极和第二电极之间的有机发光层；所述第一电极位于所述第二电极靠近所述衬底基板的一侧。所述第一连接线与所述发光元件的所述第一电极为同层结构。
在一些示例性实施方式中，所述驱动结构层包括：设置在所述衬底基板上的半导体层、第一栅金属层、第二栅金属层和源漏金属层。所述第一初始信号线与所述第二栅金属层为同层结构，所述第一电源线与所述源漏金属层为同层结构。
在一些示例性实施方式中，所述周边区域包括：第一边框区域、第二边框区域和绑定引脚区域，所述绑定引脚区域位于所述显示区域的一侧，所述第一边框区域位于所述绑定引脚区域和所述显示区域之间；所述第二边框区域与第一边框区域连通并围绕所述显示区域。所述信号连接线包括：第三连 接线，所述第三连接线在所述第二边框区域与所述第一初始信号线连接，所述第三连接线在所述第一边框区域与所述第一电源线连接。
在一些示例性实施方式中，所述第三连接线与所述第一电源线为一体结构。
在一些示例性实施方式中，所述信号连接线还包括：第四连接线；所述第三连接线与所述第四连接线连接，所述第四连接线在所述第一边框区域与所述第一电源线连接；所述第四连接线位于所述第一电源线靠近所述衬底基板的一侧。
在一些示例性实施方式中，所述像素驱动电路包括：第一晶体管至第七晶体管。第一晶体管的控制极与第二扫描线连接，第一晶体管的第一极与第二初始信号线连接，第一晶体管的第二极与第一节点连接；第二晶体管的控制极与第一扫描线连接，第二晶体管的第一极与第一节点连接，第二晶体管的第二极与第三节点连接；第三晶体管的控制极与第一节点连接，第三晶体管的第一极与第二节点连接，第三晶体管的第二极与第三节点连接；第四晶体管的控制极与第一扫描信号线连接，第四晶体管的第一极与数据信号线连接，第四晶体管的第二极与第二节点连接；第五晶体管的控制极与发光信号线连接，第五晶体管的第一极与第二电源线连接，第五晶体管的第二极与第二节点连接；第六晶体管的控制极与发光信号线连接，第六晶体管的第一极与第三节点连接，第六晶体管的第二极与第四节点连接；第七晶体管的控制极与第一扫描信号线连接，第七晶体管的第一极与第一初始信号线连接，第七晶体管的第二极与第四节点连接；所述发光元件的第一电极与第四节点连接，所述发光元件的第二电极与第一电源线连接。
另一方面，本公开实施例还提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示基板的制备方法，用于制备如上所述的显示基板，所述制备方法包括：在显示区域形成多个子像素，在所述显示区域外围的周边区域形成第一电源线和信号连接线。其中，至少一个子像素包括：设置在衬底基板上的像素驱动电路和与所述像素驱动电路连接的发光元件；所述像素驱动电路与第一初始信号线连接，所述第一初始信号线 配置为在所述像素驱动电路的控制下，给所述发光元件提供第一初始电压。所述第一初始信号线在在所述周边区域通过所述信号连接线与所述第一电源线连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的一种显示基板的示意图；
图2为本公开至少一实施例的显示基板的驱动结构示意图；
图3为本公开至少一实施例的显示基板的显示区域的平面结构示意图；
图4为本公开至少一实施例的显示基板的显示区域的剖面结构示意图；
图5为本公开至少一实施例的像素驱动电路的等效电路示意图；
图6为本公开至少一实施例的像素驱动电路的工作时序图；
图7为本公开至少一实施例的显示基板的周边区域的走线示意图；
图8和图9为图7中区域S1的局部放大示意图；
图10为图8中沿P-P方向的局部剖面示意图；
图11为图7所示的显示基板的左上拐角位置的局部示意图；
图12为图7所示的显示基板的左下拐角位置的局部示意图；
图13为本公开至少一实施例的显示基板的周边区域的另一走线示意图；
图14为本公开至少一实施例的显示基板的周边区域的另一走线示意图；
图15和图16为图14中区域S2的局部放大示意图；
图17为图15中沿R-R方向的局部剖面示意图；
图18和图19为图14中区域S2的另一局部放大示意图；
图20为图18中沿Y-Y方向的局部剖面示意图；
图21为本公开至少一实施例的显示基板的周边区域的另一走线示意图；
图22为图21中区域S3的局部放大示意图；
图23为本公开至少一实施例的显示基板的周边区域的另一示意图；
图24为图23中区域S4的局部放大示意图；
图25为图24中沿Q-Q方向的局部剖面示意图；
图26为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说 明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。其中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极，另外，将晶体管的栅极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。
本公开至少一实施例提供一种显示基板，包括：显示区域和位于显示区 域外围的周边区域。显示区域至少设置有多个子像素，至少一个子像素包括：设置在衬底基板上的像素驱动电路和与像素驱动电路连接的发光元件。像素驱动电路与第一初始信号线连接，第一初始信号线配置为在像素驱动电路的控制下，给发光元件提供第一初始电压。周边区域设置有第一电源线和信号连接线。第一初始信号线在周边区域通过信号连接线与第一电源线连接。
本实施例通过在周边区域利用信号连接线实现第一电源线和第一初始信号线的电连接，使得第一初始信号线提供的第一初始电压即为第一电源线提供的第一电源电压，利用第一电源线提供的第一电源电压对发光元件进行初始化，可以提升显示基板在高低灰阶下的均一性，而且可以避免在周边区域增加引入第一初始电压的引脚和走线空间。
在一些示例性实施方式中，周边区域包括：第一边框区域、第二边框区域和绑定引脚区域。绑定引脚区域位于显示区域的一侧，第一边框区域位于绑定引脚区域和显示区域之间，第二边框区域与第一边框区域连通并围绕显示区域。信号连接线包括：第一连接线。第一连接线在第二边框区域与第一初始信号线和第一电源线连接。第一连接线位于第一电源线靠近显示区域的一侧。在本示例性实施方式中，通过在第二边框区域利用第一连接线实现第一初始信号线与第一电源线的电连接，可以避免在绑定引脚区域增加引入第一初始电压的引脚以及避免在第一边框区域增加引入第一初始电压的走线空间。
在一些示例性实施方式中，在垂直于显示基板的平面内，第一连接线位于第一电源线远离衬底基板的一侧。在一些示例中，显示区域包括：设置在衬底基板上的驱动结构层和发光元件，发光元件包括：第一电极、第二电极和设置在第一电极和第二电极之间的有机发光层，第一电极位于第二电极靠近衬底基板的一侧。第一连接线可以与发光元件的第一电极为同层结构。驱动结构层包括：设置在衬底基板上的半导体层、第一栅金属层、第二栅金属层和源漏金属层。第一初始信号线可以与第二栅金属层为同层结构，第一电源线可以与源漏金属层为同层结构。然而，本实施例对此并不限定。在一些示例中，驱动结构层可以包括：设置在衬底基板上的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层。第一初始信号线可 以与第二栅金属层为同层结构，第一电源线可以与第一源漏金属层为同层结构，第一连接线可以与第二源漏金属层为同层结构。或者，第一电源线可以与第二源漏金属层为同层结构，第一连接线可以与发光元件的第一电极为同层结构。
在一些示例性实施方式中，信号连接线可以包括：第一连接线和第二连接线。第二连接线与第一初始信号线连接，第二连接线通过第一连接线与第一电源线连接。第二连接线位于第一连接线靠近显示区域的一侧。其中，第二连接线在第二边框区域与第一连接线连接，第一连接线在第二边框区域与第一电源线。在一些示例中，在垂直于显示基板的平面内，第二连接线位于第一连接线靠近衬底基板的一侧，且位于第一初始信号线远离衬底基板的一侧。例如，第一初始信号线可以与显示区域的第二栅金属层为同层结构，第二连接线可以与显示区域的源漏金属层为同层结构，第一连接线可以与发光元件的第一电极为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，第二连接线与第一电源线为同层结构。例如，第二连接线和第一电源线均与显示区域的源漏金属层为同层结构。然而，本实施例对此并不限定。在一些示例中，第二连接线和第一电源线可以为异层结构。例如，第二连接线可以与显示区域的第一源漏金属层为同层结构，第一电源线可以与显示区域的第二源漏金属层为同层结构。
在一些示例性实施方式中，第一连接线在周边区域内的延伸方向与第一初始信号线在显示区域内的延伸方向交叉。例如，第一初始信号线在显示区域内沿水平方向延伸，第一连接线在周边区域内沿竖直方向延伸。或者，例如，第一初始信号线在显示区域内沿竖直方向延伸，第一连接线在周边区域内沿水平方向延伸。然而，本实施例对此并不限定。
在一些示例性实施方式中，周边区域包括：第一边框区域、第二边框区域和绑定引脚区域，绑定引脚区域位于显示区域的一侧，第一边框区域位于绑定引脚区域和显示区域之间；第二边框区域与第一边框区域连通并围绕显示区域。信号连接线包括：第三连接线。第三连接线在第二边框区域与第一初始信号线连接，第三连接线在第一边框区域与第一电源线连接。在本示例性实施方式中，在第一边框区域内实现第三连接线和第一电源线的连接，可 以避免在绑定引脚区域增加引入第一初始电压的引脚。
在一些示例性实施方式中，第三连接线与第一电源线为一体结构。本示例性实施方式中，通过将第三连接线与第一电源线设置为一体结构，可以优化第一边框区域内的走线。
在一些示例性实施方式中，信号连接线包括：第三连接线和第四连接线。第三连接线与第四连接线连接。第四连接线在第一边框区域与第一电源线连接。第四连接线位于第一电源线靠近衬底基板的一侧。在一些示例中，第三连接线可以在第一边框区域与第四连接线连接，或者，可以在第二边框区域与第四连接线连接。在一些示例中，第三连接线可以与第一电源线为同层结构，例如与显示区域的源漏金属层为同层结构；第四连接线可以与显示区域的第二栅金属层为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，像素驱动电路包括：第一晶体管至第七晶体管。第一晶体管的控制极与第二扫描线连接，第一晶体管的第一极与第二初始信号线连接，第一晶体管的第二极与第一节点连接。第二晶体管的控制极与第一扫描线连接，第二晶体管的第一极与第一节点连接，第二晶体管的第二极与第三节点连接。第三晶体管的控制极与第一节点连接，第三晶体管的第一极与第二节点连接，第三晶体管的第二极与第三节点连接。第四晶体管的控制极与第一扫描信号线连接，第四晶体管的第一极与数据信号线连接，第四晶体管的第二极与第二节点连接。第五晶体管的控制极与发光信号线连接，第五晶体管的第一极与第二电源线连接，第五晶体管的第二极与第二节点连接。第六晶体管的控制极与发光信号线连接，第六晶体管的第一极与第三节点连接，第六晶体管的第二极与第四节点连接。第七晶体管的控制极与第一扫描信号线连接，第七晶体管的第一极与第一初始信号线连接，第七晶体管的第二极与第四节点连接。发光元件的第一电极与第四节点连接，发光元件的第二电极与第一电源线连接。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的一种显示基板的示意图。如图1所示，在平行于显示基板的平面内，显示基板包括：显示区域100、位于显示区域100外围的周边区域。周边区域包括：第一边框区域200、第二边框区域300以 及绑定引脚区域400。绑定引脚区域400位于显示区域100一侧，第一边框区域200位于显示区域100和绑定引脚区域400之间。第二边框区域300位于显示区域100的其它侧。第二边框区域300与第一边框区域200连通并围绕显示区域100。在一些示例中，第一边框区域200为显示基板的下边框，第二边框区域300包括显示基板的上边框、左边框和右边框。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1所示，显示基板可以包括在第一方向F1上彼此平行的一对长边和在第二方向F2上彼此平行的一对短边。第一方向F1与第二方向F2相互垂直。然而，本实施例对于显示基板的形状并不限定。在一些示例中，显示基板可以为包括线性边的闭合多边形、包括弯曲边的圆形或椭圆形、或者包括线性边和弯曲边的半圆形或半椭圆形等。在一些示例中，当显示基板具有线性边时，显示基板的至少一些拐角可以为曲线。当显示基板具有矩形形状时，在相邻的线性边彼此交汇处的部分可以采用具有预定曲率的曲线代替。其中，可以根据曲线的位置不同来设定曲率。例如，可以根据曲线开始的位置、曲线的长度等来改变曲率。
在一些示例性实施方式中，如图1所示，第一边框区域200位于显示区域100的一侧，沿着远离显示区域100的方向(即沿着第二方向F2)，第一边框区域200可以包括依次设置的第一扇出区201、弯折区202、第二扇出区203、防静电区204和驱动芯片区205。绑定引脚区400位于驱动芯片区205远离显示区域100的一侧。第一扇出区201可以设置显示基板的信号传输线，显示基板的信号传输线至少包括第一电源线(VSS)、第二电源线(VDD)和多条数据传输线，多条数据传输线配置为以扇出(Fanout)走线方式连接显示基板的数据线(Data Line)，第一电源线VSS和第二电源线VDD配置为分别连接显示基板的低电平电源线和高电平电源线。弯折区202可以设置凹槽，凹槽配置为使第二扇出区203、防静电区204、驱动芯片区205和绑定引脚区400弯折到显示区域100的背面。第二扇出区203可以设置有第一电源线VSS、第二电源线VDD、栅极信号传输线以及以扇出走线方式引出的多条数据传输线。防静电区204可以设置防静电电路，防静电电路配置为消除静电。驱动芯片区205可以设置源驱动电路(Driver IC)，源驱动电路配置 为与第二扇出区203的多条数据传输线连接。绑定引脚区400可以设置多个引脚(PIN)，多个引脚分别与第一电源线VSS、第二电源线VDD、防静电区204的信号线以及驱动芯片区205的信号线连接。多个引脚通过绑定柔性电路板(FPC，Flexible Printed Circuit)连接外部控制装置。
图2为本公开至少一实施例的显示基板的驱动结构示意图。如图1和图2所示，显示基板的显示区域设置有像素阵列，周边区域可以设置时序控制器、数据驱动器、扫描驱动器和发光驱动器。像素阵列可以包括多个扫描信号线(例如，S(1)到S(m))、多个数据信号线(例如，D(1)到D(n))、多个发光信号线(例如，E(1)到E(o))和多个子像素Pxij。
在一些示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D(1)至D(n)的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据信号线D(1)至D(n)，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S(1)至S(m)的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S(1)至S(m)。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E(1)至E(o)的发光信号。例如，发光驱动器可以将具有截止电平脉冲的发光信号顺序地提供到发光信号线E(1)至E(o)。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素PXij。每个子像素PXij可以连接到对应的数据信号线、对应的扫描信号线和对应的发光信号线，i和j可以是自 然数。子像素PXij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图3为本公开至少一实施例的显示基板的显示区域的平面结构示意图。如图3所示，显示基板的显示区域可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光元件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光元件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光元件分别与所在子像素的像素驱动电路连接，发光元件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在一些示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。在一些示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列。然而，本公开在此不做限定。
图4为本公开至少一实施例的显示基板的显示区域的剖面结构示意图。图4中示意了显示基板的三个子像素的结构。如图4所示，在垂直于显示基板的平面内，显示区域可以包括：设置在衬底基板101上的驱动结构层102、设置在驱动结构层102远离衬底基板101一侧的发光元件103以及设置在发光元件103远离衬底基板101一侧的封装层104。在一些可能的实现方式中，显示区域可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在一些示例性实施方式中，衬底基板101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动结构层102可以包括构成像素驱动电路的多个薄膜晶体管和存储电容，图4中以每个子像素中包括的一个薄膜晶体管210 和一个存储电容211为例进行示意。驱动结构层102包括依次设置在衬底基板101上的半导体层、第一栅金属层、第二栅金属层和源漏金属层。半导体层至少包括：薄膜晶体管210的有源层；第一栅金属层至少包括：薄膜晶体管的栅极和存储电容的第一电容电极；第二栅金属层至少包括：存储电容的第二电容电极；源漏金属层至少包括：薄膜晶体管的源电极和漏电极。衬底基板和半导体层之间设置第一绝缘层11，半导体层和第一栅金属层之间设置第二绝缘层12，第一栅金属层和第二栅金属层之间设置第三绝缘层13，第二栅金属层和源漏金属层之间设置第四绝缘层14，源漏金属层和发光元件103之间设置第五绝缘层15。第一绝缘层11还可以称为缓冲层，第二绝缘层12和第三绝缘层13还可以称为栅绝缘层，第四绝缘层14还可以称为层间绝缘层，第五绝缘层15还可以称为平坦层。
在一些示例性实施方式中，发光元件103可以包括：第一电极301、像素定义层302、有机发光层303和第二电极304。第一电极301通过过孔与薄膜晶体管210的漏电极连接，有机发光层303与第一电极301连接，第二电极304与有机发光层303连接，有机发光层303在第一电极301和第二电极304驱动下出射相应颜色的光线。在一些示例中，第一电极301为阳极，第二电极304为阴极。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光元件103。
在一些示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、电子阻挡层(EBL，Electron Block Layer)、发光层(EML，Emitting Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子传输层(ETL，Electron Transport Layer)和电子注入层(EIL，Electron Injection Layer)。在一些示例中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。然而，本实施例对此并不限定。
在一些示例性实施例中，像素驱动电路可以是7T1C结构。图5为本公开至少一实施例的像素驱动电路的等效电路示意图。如图5所示，像素驱动电路可以包括7个薄膜晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容Cst和8个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VSS和第二电源线VDD)。
在一些示例性实施方式中，存储电容Cst的第一端与第二电源线VDD连接，存储电容Cst的第二端与第一节点N1连接，即存储电容Cst的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第二初始信号线INIT2连接，第一晶体管的第二极与第一节点N1连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第二初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第一节点N1连接，即第三晶体管T3的控制极与存储电容Cst的第二端连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第二电源线VDD与第一电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第二节点N2连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极 与第二电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光元件的第一电极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第二电源线VDD与第一电源线VSS之间形成驱动电流路径而使发光元件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与第一初始信号线INIT1连接，第七晶体管T7的第二极与发光元件的第一电极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将第一初始化电压传输到发光元件的第一电极，以使发光元件的第一电极中累积的电荷量初始化或释放发光元件的第一电极中累积的电荷量。
在一些示例性实施方式中，发光元件的第二电极与第一电源线VSS连接，第一电源线VSS的信号为低电平信号，第二电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在一些示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，在显示区域内，第一扫描信号线S1、第二扫描信号线S2、发光信号线E、第一初始信号线INIT1和第二初始信号线INT2可以沿第一方向F1延伸。第二电源线VDD和数据信号线D可以沿第二方向F2延伸。
图6为本公开至少一实施例的像素驱动电路的工作时序图。下面通过图 5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容Cst和8个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VSS和第二电源线VDD)，7个晶体管均为P型晶体管。
在一些示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1、称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，第二初始信号线INIT2的信号提供至第一节点N1，对存储电容Cst进行初始化，清除存储电容Cst中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段发光元件不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容Cst的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号，使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通，使得数据信号线D输出的数据电压经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第二端(第一节点N1)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通，使得第一初始信号线INIT1的第一初始电压提供至发光元件的第一电极，对发光元件的第一电极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第 一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第二电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件的第一电极提供驱动电压，驱动发光元件发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光元件的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第二电源线VDD输出的电源电压。
在本示例性实施方式中，第一节点N1和第四节点N4的电压分别由第二初始信号线INIT2和第一初始信号线INIT1控制。第一初始信号线INIT1提供的第一初始电压不同于第二初始信号线INIT2提供的第二初始电压。第一初始信号线INIT1与第一电源线VSS连接，即第一初始信号线INIT1提供的第一初始电压等于第一电源线VSS提供的第一电源电压。
本实施例通过采用双初始信号线的方式，分别给第一节点N1和第四节点N4提供不同的初始电压，可以避免由同一初始信号线控制第一节点和第四节点时产生的问题，例如，由于同一初始信号线在靠近第一边框区域和远离第一边框区域所存在的压降(drop)而导致显示区域存在亮度差异，或者当显示区域存在开口区域时，由于同一初始信号线在开口区域和开口区域靠近第一边框区域一侧所存在的压降而影响低灰阶画质的问题。本示例性实施方式中，通过设置第一初始信号走线INIT1与第一电源线VSS连接，可以利用第一电源线VSS来提供第一初始电压，从而避免在绑定引脚区域增加引入第一初始电压的引脚，以及避免在第一边框区域增加引入第一初始电压的走线空间而导致增加第一边框区域的面积。
图7为本公开至少一实施例的显示基板的周边区域的走线示意图。在一些示例性实施方式中，如图1和图7所示，第二边框区域300包括位于显示 区域100右侧的第一边缘区域300a、位于显示区域100上侧的第二边缘区域300b以及位于显示区域100左侧的第三边缘区域300c。第一边缘区域300a、第二边缘区域300b、第三边缘区域300c和第一边框区域200连通后围绕在显示区域100的四周。例如，第一边缘区域300a可以为显示基板的右边框，第二边缘区域300b可以为显示基板的上边框，第三边缘区域300c可以为显示基板的左边框。
在一些示例性实施方式中，显示区域100设置有多条相互平行的第一初始信号线INIT1。每条第一初始信号线INIT1配置为给每一行子像素的像素驱动电路提供第一初始电压。例如，显示区域100内的多条第一初始信号线INIT1可以沿第一方向F1延伸，并沿着第二方向F2依次排布。在一些示例中，以图5所示的像素驱动电路为例，在每个子像素中，第一扫描信号线S1、第二扫描信号线S2、第一初始信号线INIT1、第二初始信号线INIT2和发光信号线E均沿第一方向F1延伸，数据信号线D和第二电源线VDD沿第二方向F2延伸，且第一扫描信号线S1、发光信号线E、第二初始信号线INIT2、第一初始信号线INIT1和第二扫描信号线S2可以沿第二方向F2依次排布。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一初始信号线INIT1可以从显示区域100延伸至第二边框区域300的第一边缘区域300a和第三边缘区域300c。例如，第一初始信号线INIT1具有延伸至第一边缘区域300a的第一延伸端，以及延伸至第三边缘区域300c的第二延伸端。然而，本实施例对此并不限定。例如，第一初始信号线INIT1可以向一侧边缘区域延伸以接收第一初始电压。
在一些示例性实施方式中，第二边框区域300设置有第一电源线VSS、第一连接线501和第二连接线502。在一些示例中，第一电源线VSS可以设置在第一边缘区域300a、第二边缘区域300b和第三边缘区域300c，第一连接线501和第二连接线502可以设置在第一边缘区域300a和第三边缘区域300c。第一连接线501通过第二连接线502与显示区域100的多条第一初始信号线INIT1连接，第一连接线501与第一电源线VSS连接，从而实现第一电源线VSS和显示区域100内的第一初始信号线INIT1之间的电连接。第一连接线501位于第二连接线502远离显示区域100的一侧，第一电源线VSS 位于第一连接线501远离显示区域100的一侧。在一些示例中，第二连接线502和第一电源线VSS可以为同层结构，第一连接线501位于第一电源线VSS远离衬底基板的一侧。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一电源线VSS与绑定引脚区域400内的引脚连接，以获取外部提供的第一电源电压。第一电源线VSS在第一边缘区域300a、第二边缘区域300b和第三边缘区域300c均设置在显示区域100的外围。
在一些示例性实施方式中，第一边缘区域300a和第三边缘区域300c均设置有第一连接线501和第二连接线502。在第一边缘区域300a内，多条第一初始信号线INIT1的第一延伸端通过第二连接线502和第一连接线501与第一电源线VSS连接。在第三边缘区域300c内，多条第一初始信号线INIT1的第二延伸端通过第二连接线502和第一连接线501与第一电源线VSS连接。然而，本实施例对此并不限定。例如，可以仅在第一边缘区域300a或第三边缘区域300c设置第一连接线和第二连接线，实现第一初始信号线INIT1与第一电源线VSS的连接。
在一些示例性实施方式中，第二边框区域300内的第一连接线501和第二连接线502可以沿显示区域100的边缘延伸。例如，第一边缘区域300a和第三边缘区域300c内的第一连接线501和第二连接线502可以沿第二方向F2延伸。第一连接线501与第一电源线VSS直接连接，第一连接线501在衬底基板上的正投影与第一电源线VSS部分交叠。第二连接线502与第一连接线501和多条第一初始信号线INIT1连接。在一些示例中，第一连接线501与显示区域100的发光元件的第一电极可以为同层结构。第一电源线VSS与显示区域100的源漏金属层可以为同层结构。第二连接线502与第一电源线VSS为同层结构。第一初始信号线INIT2与显示区域100的第二栅金属层为同层结构。然而，本实施例对此并不限定。
在本示例性实施方式中，在第二边框区域300内通过第一连接线501和第二连接线502实现第一电源线VSS和第一初始信号线INIT1的连接，无需在绑定引脚区域400增加引入第一初始电压的引脚，无需在第一边框区域200增加引入第一初始电压的走线空间，可以避免增加第一边框区域200和绑定 引脚区域400的面积。
图8和图9为图7中区域S1的局部放大示意图。图8为本公开至少一实施例的形成第一连接线后的第三边缘区域的局部示意图。图9为本公开至少一实施例的形成第二连接线后的第三边缘区域的局部示意图。图8和图9中仅示意发光驱动电路和扫描驱动电路的位置，省略示意了详细电路结构。
在一些示例性实施方式中，如图8和图9所示，在平行于显示基板的平面内，沿着靠近显示区域100的方向上，第三边缘区域300c内依次排布有第一电源线VSS、发光驱动电路62、扫描驱动电路61、第二连接线502和初始信号引线600。初始信号引线600与多条第二初始信号线INIT2在第三边缘区域300c内的延伸端连接。初始信号引线600与绑定引脚区域400内的绑定引脚连接，以获取外部提供的第二初始电压。在第三边缘区域300c内，第二连接线502与初始信号引线600的延伸方向相同，例如沿着第二方向F2延伸。第二连接线502位于初始信号引线600远离显示区域100的一侧。然而，本实施例对此并不限定。例如，第二连接线502可以位于初始信号线600靠近显示区域100的一侧。
在一些示例性实施方式中，第二连接线502的走线宽度可以与初始信号引线600的走线宽度大致相同。第一电源线VSS的走线宽度可以大于第二连接线502的走线宽度，且大于初始信号引线600的走线宽度。
在一些示例性实施方式中，第二连接线502的走线宽度约为3um至30um，例如可以约为13um。初始信号引线600的走线宽度约为3um至30um，例如可以约为13um。第二连接线502与初始信号引线600之间的间距约为1um至15um，例如可以为4um。第三边缘区域300c内的第一电源线VSS的走线宽度约为20um至500um，例如可以约为270um。
在本公开中，走线宽度表示走线在延伸方向的垂直方向上的特征尺寸。
在一些示例性实施方式中，扫描驱动器可以包括分别排布在第一边缘区域300a和第三边缘区域300c的扫描驱动电路61。发光驱动器可以包括分别排布在第一边缘区域300a和第三边缘区域300c的发光驱动电路62。扫描驱动电路61可以包括多个级联的扫描GOA单元。多个扫描GOA单元可以给显示区域100的像素阵列提供扫描信号(例如，包括第一扫描信号和第二扫 描信号)。在一些示例中，每个扫描GOA单元可以通过扫描引线601与显示区域100的一行子像素的第一扫描信号线连接，配置为给一行子像素提供第一扫描信号，并与上一行子像素的第二扫描信号线连接，配置为给上一行子像素提供第二扫描信号。发光驱动电路可以包括多个级联的发光GOA单元，多个发光GOA单元可以给显示区域100提供发光信号。每个发光GOA单元通过发光引线602与显示区域100的一行子像素的发光信号线连接，配置为给一行子像素提供发光信号。
在一些示例性实施方式中，第二连接线502、初始信号引线600和第一电源线VSS可以为同层结构，例如与显示区域100的源漏金属层为同层结构。第二连接线502连接的多条第一初始信号线INIT1、初始信号引线600连接的多条第二初始信号线INIT2、扫描引线601和发光引线602可以为同层结构，例如与显示区域100的第二栅金属层为同层结构。扫描引线601连接的第一扫描信号线和第二扫描信号线、发光引线602连接的发光信号线为同层结构，例如与显示区域100的第一栅金属层为同层结构。扫描引线601可以通过第二绝缘层上的过孔与第一扫描信号线和第二扫描信号线连接，发光引线602可以通过第二绝缘层上的过孔与发光信号线连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图8所示，第一连接线501可以具有多个镂空部，使得第一连接线501形成有缝隙。本示例中通过在第一连接线501上设置多个镂空部，可以避免第一连接线覆盖大面积的第五绝缘层(采用有机绝缘材料制备)而导致的鼓包现象。第一连接线501和第一电源线VSS在衬底基板上的正投影的交叠区域内，第一连接线501的多个镂空部的位置与第一隔离坝的位置对应。第一连接线501与第一电源线VSS的交叠区域覆盖第一隔离坝所在位置，可以增加第一连接线501和第一电源线VSS的接触面积，而且通过在第一隔离坝对应位置的第一连接线设置镂空部，可以实现第一连接线501与第一电源线VSS的有效连接。
在一些示例性实施方式中，第一连接线501与显示区域100的发光元件的第一电极为同层结构，第一电源线VSS与显示区域100的源漏金属层为同层结构。第一电源线VSS和第一连接线501之间设置有平坦层(即上述的第 五绝缘层)，通过在平坦层上开设的第一凹槽，可以实现第一电源线VSS和第一连接线501之间的有效连接。
图10为图8中沿P-P方向的局部剖面示意图。在一些示例性实施方式中，如图10所示，第一初始信号线INIT1设置在第三绝缘层13上，第二连接线502通过第四绝缘层14上设置的第一过孔K1与第一初始信号线INIT1连接。第一连接线501通过第五绝缘层15上设置的第二凹槽K2与第二连接线502连接。
在一些示例中，周边区域的第五绝缘层15上开设有第一凹槽和第二凹槽，第一连接线501可以通过第一凹槽与第一电源线VSS连接，通过第二凹槽与第二连接线502连接。通过在第五绝缘层15上开设第一凹槽和第二凹槽，可以增加第一连接线501与第一电源线VSS和第二连接线502的接触面积，实现第一连接线501的两端分别与第一电源线VSS和第二连接线502的有效电连接。
图11为图7所示的显示基板的左上拐角位置的局部示意图。图11为图7所示的第二边缘区域300b和第三边缘区域300c的交界位置的局部示意图。如图7和图11所示，第二边缘区域300b不设置第一连接线51和第二连接线52。第一初始信号线INIT1从显示区域100的左右两侧延伸后与第一电源线VSS连接。第三边缘区域300c内的第二连接线502可以沿着显示区域100的左上拐角边缘延伸，例如左上拐角处的第二连接线502的延伸方向与第三边缘区域300c的第二连接线502的延伸方向交叉。在一些示例中，第一连接线501可以无需延伸至左上拐角位置。由于第二连接线502在第三边缘区域300c与第一连接线501连接，仅第二连接线502延伸至左上拐角位置与第一初始信号线INIT1连接即可。
关于第二边缘区域和第一边缘区域的交界位置(即右上拐角位置)的走线结构可以参照图11所示，故于此不再赘述。
图12为图7所示的显示基板的左下拐角位置的局部示意图。图12为图7所示的第三边缘区域和第一边框区域的交界位置的局部示意图。如图7和图12所示，第二连接线502可以从第一边框区域200延伸进入第三边缘区域300c。绑定引脚区域内无需设置与第二连接线502连接的引脚。第二连接线 502靠近显示区域100一侧设置有初始信号引线600和第二电源线VDD。初始信号引线600可以从绑定引脚区域400，经过第一边框区域200延伸至第三边缘区域300c。第一连接线501可以延伸到左下拐角位置，并与第二连接线502连接。
关于第一边缘区域和第一边框区域的交界位置(即右下拐角位置)的走线结构可以参照图12所示，故于此不再赘述。
下面参照图4、图8至图12通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
本公开中所说的“A和B为同层结构”是指，A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
在一些示例性实施方式中，本实施例的显示基板的制备过程可以包括以下步骤(1)至步骤(8)。
(1)、提供衬底基板。
在一些示例性实施方式中，衬底基板101为刚性基板，例如玻璃基板，或者，柔性基底。然而，本实施例对此并不限定。
(2)、在衬底基板上制备半导体层图案。
在一些示例性实施方式中，在衬底基板101上依次沉积第一绝缘薄膜和半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成覆盖整个衬底基板10的第一绝缘层11，以及设置在第一绝缘层11上的半导体层图案。如图4 所示，半导体层图案形成在显示区域100，至少包括第一有源层。
(3)、在衬底基板上制备第一栅金属层图案。
在一些示例性实施方式中，在形成上述结构的衬底基板101上，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖半导体层图案的第二绝缘层12，以及设置在第二绝缘层12上的第一栅金属层，如图4所示。第一栅金属层图案形成在显示区域100，至少包括第一栅电极和第一电容电极。在本步骤中，可以在显示区域100同步形成第一扫描信号线、第二扫描信号线以及发光信号线。
(4)、在衬底基板上制备第二栅金属层、第一初始信号线和第二初始信号线图案。
在一些示例性实施方式中，在形成上述结构的衬底基板101上，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成第三绝缘层13，以及设置在第三绝缘层13上的第二栅金属层、第一初始信号线和第二初始信号线图案。如图4所示，第二栅金属层图案形成在显示区域100，至少包括第二电容电极。第一初始信号线INIT1和第二初始信号线INIT2可以从显示区域100延伸至第一边缘区域300a和第三边缘区域300c。
(5)、在衬底基板上制备第四绝缘层图案。
在一些示例性实施方式中，在形成上述结构的衬底基板101上，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖第二栅金属层、第一初始信号线和第二初始信号线图案的第四绝缘层14图案。如图4和图10所示，第四绝缘层14上至少开设有多个第一过孔和多个第二过孔。多个第二过孔位于显示区域100，暴露出第一有源层的表面。多个第一过孔K1位于第一边缘区域300a和第三边缘区域300c，暴露出第一初始信号线INIT1和第二初始信号线INIT2的表面。
(6)、在衬底基板上制备源漏金属层、第一电源线、第二连接线和初始信号引线图案。
在一些示例性实施方式中，在形成上述结构的衬底基板101上，沉积第 三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第四绝缘层14上形成源漏金属层、第一电源线VSS和第二连接线502和初始信号引线600图案。如图4所示，源漏金属层图案形成在显示区域100，至少包括第一源电极、第一漏电极、多条数据线(未示出)图案。第一源电极和第一漏电极分别通过第二过孔与第一有源层的源极区和漏极区连接。如图8至图10所示，第一电源线VSS和第二连接线502形成在周边区域，第二连接线502可以通过第一过孔K1与第一初始信号线INIT1连接，初始信号引线600可以通过第一过孔K1与第二初始信号线INIT2连接。
至此，在衬底基板101上制备完成显示区域100的驱动结构层，如图4所示。显示区域100的驱动结构层中，第一有源层、第一栅电极、第一源电极和第一漏电极组成薄膜晶体管210，第一电容电极和第二电容电极组成存储电容211。
在一些示例性实施方式中，第一绝缘薄膜至第四绝缘薄膜均采用无机材料，例如，硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。
(7)、在衬底基板上依次制备第五绝缘层、发光元件和封装层。
在一些示例性实施方式中，在形成前述结构的衬底基板101上，涂覆平坦薄膜，通过构图工艺形成第五绝缘层。第五绝缘层上设置有多个第三过孔、第一凹槽和第二凹槽。如图4所示，第三过孔形成在显示区域100，暴露出薄膜晶体管210的第一漏电极的表面。如图8和图10所示，第一凹槽和第二凹槽K2形成在周边区域，第一凹槽内的第五绝缘层15被刻蚀掉，暴露出第一电源线VSS的表面，第二凹槽K2内的第五绝缘层被刻蚀掉，暴露出第二连接线502的表面。
随后，沉积第一导电薄膜，通过构图工艺对第一导电薄膜进行构图，形成发光元件的第一电极和第一连接线501图案。如图4所示，发光元件的第一电极301形成在显示区域100，第一电极301通过第五绝缘层15上的第三过孔与薄膜晶体管210的第一漏电极连接。如图8和图10所示，第一连接线501形成在周边区域，通过第一凹槽与第一电源线VSS连接，通过第二凹槽K2与第二连接线502连接。
随后，涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义层302图案。如图4所示，像素定义层302形成在显示区域100。显示区域100的像素定义层302上开设有像素开口，像素开口内的像素定义薄膜被显影掉，暴露出第一电极301的表面。
随后，在形成前述图案的衬底基板101上依次形成有机发光层303和第二电极304。例如，有机发光层303包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，形成在显示区域100的像素开口内，实现有机发光层303与第一电极301连接。由于第一电极301与薄膜晶体管210的第一漏电极连接，实现有机发光层303的发光控制。第二电极304的一部分形成在有机发光层303上。
在一些示例性实施方式中，在形成前述图案的衬底基板101上，形成封装层104。如图4所示，封装层104可以采用无机材料/有机材料/无机材料的叠层结构。有机材料层设置在两个无机材料层之间。
在一些示例性实施方式中，第五绝缘层15和像素定义层302可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。
在上述制备过程中，扫描驱动电路和发光驱动电路的制备过程类似于显示区域的驱动结构层的制备过程，故于此不再赘述。
本示例性实施例的制备工艺利用现有成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本示例性实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示区域可以设置第一源漏金属层和第二源漏金属层，第一源漏金属层可以包括薄膜晶体管的第一源电极和第一漏电极，第二源漏金属层可以包括发光元件和第一漏电极之间的连接电极。第一连接线与第二源漏金属层可以为同层结构，第一电源线和第二连接线可以与第一源漏金属层为同层结构。然而，本实施例对此并不限定。
在本示例性实施方式中，通过在显示区域相对两侧的第一边缘区域和第三边缘区域设置第一连接线和第二连接线，实现第一初始信号线与第一电源 线的连接。本实施例可以在不增加第一边框区域的走线空间和绑定引脚区域的引脚的情况下，大幅度提升显示基板在高低灰阶下的均一性，从而提升画面品质。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图13为本公开至少一实施例的显示基板的周边区域的另一走线示意图。在一些示例性实施方式中，如图13所示，显示区域100内设置的第一初始信号线INIT1可以沿第二方向F2延伸，多条第一初始信号线INIT1可以沿第一方向F1排布。然而，本实施例对此并不限定。例如，显示区域100内设置的第二初始信号线INIT2的延伸方向可以与第一初始信号线INIT1的延伸方向相同，例如沿第二方向F2延伸；或者，第二初始信号线INIT2可以与第一初始信号线INIT1的延伸方向交叉，例如第二初始信号线INIT2沿第一方向F1延伸，第一初始信号线INIT1沿第二方向F2延伸。
在一些示例性实施方式中，如图13所示，第一初始信号线INIT1可以从显示区域100延伸至第二边框区域的第二边缘区域300b(例如，显示基板的上边框)。例如，第一初始信号线INIT1具有延伸至第二边缘区域300b的第一延伸端。第二边框区域设置有第一电源线VSS和第一连接线501。由于第一边缘区域300a、第二边缘区域200b和第三边缘区域300c均设置有第一电源线VSS，多个第一初始信号线INIT1可以在第二边缘区域300b通过第一连接线501与第一电源线VSS连接。例如，第一初始信号线INIT1的第一延伸端与第一连接线501的第一端连接，第一连接线501的第二端与第一电源线VSS连接。第一电源线VSS位于第一连接线501远离显示区域100的一侧，第一连接线501位于第一初始信号线INIT1远离显示区域100的一侧。第一连接线501在衬底基板上的正投影与第一电源线和VSS多条第一初始信号线INIT1均存在交叠。然而，本实施例对此并不限定。在一些示例中，第二边缘区域300b还可以设置第二连接线，第二连接线的延伸方向与第一连接线的延伸方向一致，第二连接线通过第一连接线连接第一电源线，第二连接线与第一初始信号线连接。其中，第二连接线可以与第一电源线为同层结构。
在一些示例性实施方式中，在垂直于显示基板的平面内，显示区域100 的驱动结构层包括依次设置在衬底基板上的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层。第一源漏金属层可以包括薄膜晶体管的第一源电极和第一漏电极，第二源漏金属层可以包括发光元件和第一漏电极之间的连接电极。位于第二边缘区域300b的第一连接线501可以与发光元件的第一电极为同层结构。在一些示例中，第一初始信号线INIT1可以与第一源漏金属层为同层结构，且第一初始信号线INIT1的延伸方向可以与数据信号线的延伸方向平行。或者，在一些示例中，第一初始信号线INIT1可以与第二源漏金属层为同层结构，或者，与半导体层同层设置。然而，本实施例对此并不限定。第一初始信号线设置在不与扫描信号线交叠的其他导电膜层。
本示例性实施方式中，通过在显示基板的第二边缘区域(即上边框)实现第一初始信号线和第一电源线之间的连接，可以避免在第一边缘区域和第二边缘区域(即显示区域的左右边框)设计连接结构，从而实现窄边框。
关于本实施例提供的显示基板的其他结构可以参照前述实施例的说明，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图14为本公开至少一实施例的显示基板的周边区域的另一走线示意图。图15和图16为图14中区域S2的局部放大示意图。图17为图15中沿R-R方向的局部剖面示意图。图15为本公开至少一实施例的形成第一连接线后的第三边缘区域的局部示意图。图16为本公开至少一实施例的形成第一电源线后的第三边缘区域的局部示意图。
在一些示例性实施方式中，如图14至图16所示，第二边框区域300设置有第一连接线501。在第一边缘区域300a和第三边缘区域300c，第一连接线501连接第一电源线VSS和多条第一初始信号线INIT1。第二边缘区域300b内可以不设置第一连接线501。在本示例中，如图15和图17所示，第一连接线501通过设置在第五绝缘层15上的第一凹槽与第一电源线VSS连接，并通过贯穿第五绝缘层15和第四绝缘层14的第二凹槽与第一初始信号线INIT1连接。
本示例性实施方式中，第一连接线501的材料可以与有机发光层的阳极为相同材料，例如可以是氧化铟锡(ITO)，或者Ag/ITO/Ag的叠层。
本示例性实施方式中，第一连接线501可以与有机发光层的阳极同层制作。
在本示例性实施方式中，通过在显示区域相对两侧的第一边缘区域和第三边缘区域设置第一连接线，实现第一初始信号线与第一电源线的连接。本实施例可以在不增加第一边框区域的走线空间和绑定引脚区域的引脚的情况下，大幅度提升显示基板在高低灰阶下的均一性，从而提升画面品质。
关于本实施例的显示区域和周边区域的相关结构可以参照上述实施例的描述，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。例如，本示例性实施方式中的第一初始信号线INIT1可以沿第二方向F2延伸，在第二边缘区域300b通过第一连接线501与第一电源线VSS连接。
图18和图19为图14中区域S2的另一局部放大示意图。图20为图18中沿Y-Y方向的局部剖面示意图。图18为本公开至少一实施例的形成第一连接子线后的第三边缘区域的局部示意图。图19为本公开至少一实施例的形成第二连接子线后的第三边缘区域的局部示意图。
在一些示例性实施方式中，如图14、图18和图19所示，第二边框区域300设置有第一连接线。在本示例中，第一连接线为多层结构。例如，第一连接线包括第一连接子线501a和第二连接子线501b。第一连接线设置在第一边缘区域300a和第三边缘区域300c。第二连接子线501b连接第一电源线VSS和多条第一初始信号线INIT1，第一连接子线501a与第二连接子线501b连接。在本示例中，显示区域100的驱动结构层包括依次设置在衬底基板上的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层。第一连接子线501a与发光元件的第一电极为同层结构，第二连接子线501b与第二源漏金属层为同层结构，第一电源线VSS与第一源漏金属层为同层结构，第一初始信号线INIT1与第二栅金属层为同层结构。如图18和图20所示，第一连接子线501a通过第六绝缘层16上的凹槽与第二连接子线 501b连接。第二连接子线501b通过贯穿第五绝缘层15和第四绝缘层14的过孔与第一初始信号线INIT1连接。第五绝缘层15和第六绝缘层16可以为采用有机材料制备的平坦层。
在一些示例性实施方式中，第二连接子线501b可以覆盖发光驱动电路62和扫描驱动电路61所在区域，并延伸到第一初始信号线INIT1的上方，通过过孔与多条第一初始信号线INIT1连接。第二连接子线501b还延伸到第一电源线VSS的上方，通过第五绝缘层上的凹槽与第一电源线VSS连接。在本示例中，第二连接子线501b可以连接第一电源线VSS和第一初始信号线INIT1。然而，本实施例对此并不限定。例如，第二连接子线可以仅连接第一电源线VSS，由第一连接子线连接第一初始信号线INIT1和第二连接子线，实现第一电源线VSS和第一初始信号线INIT1的电连接；或者，第二连接子线可以仅连接第一初始信号线INIT1，由第一连接子线连接第二连接子线和第一电源线，实现第一电源线VSS和第一初始信号线INIT1的电连接。
本示例性实施方式中，通过将第一连接线设置为双层结构，利用与第二源漏金属层为同层结构的第二连接子线可以有利于不同走线之间的搭接，通过多层搭接可以降低电阻，提供信号传输性能。
本示例性实施方式中，第一连接子线501a可以与有机发光层的阳极为相同材料，例如可以是ITO，或者Ag/ITO/Ag的叠层。例如，第一连接子线501a可以与有机发光层的阳极同层制作。
本示例性实施方式中，第二连接子线501b的材料可以包括金属材料，例如可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。
本示例性实施方式中，第一电源线VSS的材料可以包括金属材料，例如可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。
本示例性实施方式中，第二连接子线501b的材料也可以是与像素驱动电路中的其他金属膜层相同材料，或者同层制作，例如可以与栅极金属层同层，或者采用相同材料。例如，对于LTPO背板(氧化物与低温多晶硅结合的背板)，第二连接子线501b的材料可以与氧化物晶体管的栅极采用相同材料， 和/或同层制作，例如材料可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等。
关于本实施例的显示基板的其余结构可以参照上述实施例的描述，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。例如，本示例性实施方式中的第一初始信号线INIT1可以沿第二方向F2延伸，第一连接子线和第二连接子线可以设置在第二边缘区域300b，以实现第一电源线VSS与第一初始信号线INIT1的电连接。或者，例如，在本示例性实施方式提供的双层结构的第一连接线的基础上，还可以在第二边框区域设置第二连接线，第二连接线可以与第一源漏金属层为同层结构，并与第一初始信号线连接，第二连接线与第二连接子线连接，第二连接子线与第一连接子线连接，由第一连接子线或第二连接子线与第一电源线连接，从而实现第一初始信号线与第一电源线的电连接。图21为本公开至少一实施例的显示基板的周边区域的另一走线示意图。图22为图21中区域S3的局部放大示意图。在一些示例性实施方式中，如图21所示，第一边框区域200位于绑定引脚区域400和显示区域100之间。例如，沿着远离显示区域100的方向上，第一边框区域200可以包括：第一扇出区域、弯折区域、第二扇出区域、防静电区域和驱动芯片区域。在本示例中，第一边框区域200和第二边框区域内设置有第三连接线503。第三连接线503在第二边框区域的第一边缘区域300a和第三边缘区域300c内与第一初始信号线INIT1连接，在第一边框区域200内与第一电源线VSS连接。在本示例中，第三连接线503与第一电源线VSS为一体结构，且第三连接线503和第一电源线VSS的连接位置可以位于第一边框区域200。
在一些示例性实施方式中，第三连接线503在第一边缘区域300a和第三边缘300c内的延伸方向与第一初始信号线INIT1在显示区域100内的延伸方向交叉。
图22所示为显示基板的左下角位置的走线示意图。在一些示例性实施方式中，如图21和图22所示，第三连接线503位于初始信号引线600远离显示区域100的一侧，初始信号引线600位于第二电源线VDD远离显示区域 100的一侧。第一电源线VSS从第一边框区域200向第三边缘区域300c延伸时分成两路，一路形成第三连接线503与第一初始信号线INIT1在第三边缘区域300c的第二延伸端连接，另一路仍作为第一电源线VSS进入第三边缘区域300c。
在一些示例性实施方式中，如图22所示，在第三连接线503和第一电源线VSS的连接位置的附近，设置有提供给扫描驱动电路和发光驱动电路的信号线。例如，在第一电源线VSS靠近显示区域100的一侧依次排布有第三电源线VGH、第四电源线VGL、提供给发光GOA单元的第一信号线组、提供给扫描GOA单元的第二信号线组。第一信号线组可以包括：第一起始信号线ESTV以及时钟信号线ECB和ECK。第二信号线组包括：第二起始信号线GSTV以及时钟信号线GCB和GCK。在一些示例中，第三电源线VGH、第四电源线VGL、时钟信号线GCB和GCK可以与显示区域的第二栅金属层为同层结构；第一起始信号线ESTV以及时钟信号线ECB和ECK可以与显示区域的第一栅金属层为同层结构；第二起始信号线GSTV可以与第一栅金属层为同层结构，并连接与第二栅金属层同层的走线，以接收扫描起始信号。
在本示例性实施方式中，通过在第一边框区域实现第三连接线和第一电源线的一体连接，以实现第一电源线与第一初始信号线的电连接，可以在不增加第一边框区域的走线空间和绑定引脚区域的引脚的情况下，大幅度提升显示基板在高低灰阶下的均一性，从而提升画面品质。
关于本实施例的显示区域和周边区域的相关结构可以参照上述实施例的描述，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。例如，本示例性实施方式中的第一初始信号线可以沿第二方向延伸，第三连接线可以设置在第一边缘区域、第二边缘区域和第三边缘区域，第一初始信号线可以在第二边缘区域与第三连接线连接。或者，第一初始信号线可以在第二边缘区域与第一电源线连接。
图23为本公开至少一实施例的显示基板的周边区域的另一走线示意图。图24为图23中区域S4的局部放大示意图。图25为图24中沿Q-Q方向的剖面示意图。在一些示例性实施方式中，如图23所示，第三连接线503在第 二边框区域300的第一边缘区域300a和第三边缘区域300c内与第一初始信号线INIT1连接，在第一边框区域200、第一边框区域200和第三边缘区域300c的交界位置、或者第三边缘区域300c，与第四连接线504的一端连接。第四连接线504的另一端在第一边框区域200内与第一电源线VSS连接。
在一些示例性实施方式中，如图24所示，第四连接线504与第一电源线VSS的连接位置可以位于弯折区域202远离显示区域100的一侧。第四连接线504在第一边框区域200内的延伸方向可以与提供给扫描驱动电路和发光驱动电路的时钟信号线和起始信号线的延伸方向一致。
在一些示例性实施方式中，如图25所示，第四连接线504可以与显示区域100的第二栅金属层为同层结构，第一电源线VSS可以与显示区域100的源漏金属层为同层结构。第一电源线VSS可以通过第四绝缘层14上设置的过孔与第四连接线504连接。当第三连接线503与第一电源线VSS为同层结构，第四连接线504可以通过第四绝缘层上设置的过孔与第三连接线503连接。然而，本实施例对此并不限定。图25中省略示意了与第四连接线504同层的其余走线。
在本示例性实施方式中，通过在第一边框区域实现第四连接线和第一电源线的电连接，实现第一电源线通过第三连接线和第四连接线与第一初始信号线的电连接，可以在不增加第一边框区域的走线空间和绑定引脚区域的引脚的情况下，大幅度提升显示基板在高低灰阶下的均一性，从而提升画面品质。
关于本实施例的显示区域和周边区域的相关结构可以参照上述实施例的描述，故于此不再赘述。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。例如，本示例性实施方式中的第一初始信号线可以沿第二方向延伸，第三连接线可以设置在第一边缘区域、第二边缘区域和第三边缘区域，第一初始信号线可以在第二边缘区域与第三连接线连接。
本公开至少一实施例还提供一种显示基板的制备方法，用于制备如上实施例所述的显示基板。本实施例的显示基板的制备方法，包括：在显示区域形成多个子像素，在显示区域外围的周边区域形成第一电源线和信号连接线。 其中，至少一个子像素包括：设置在衬底基板上的像素驱动电路和与所述像素驱动电路连接的发光元件；所述像素驱动电路与第一初始信号线连接，所述第一初始信号线配置为在所述像素驱动电路的控制下，给所述发光元件提供第一初始电压。所述第一初始信号线在在所述周边区域通过所述信号连接线与所述第一电源线连接。
关于本实施例的显示基板的制备方法可以参照前述实施例的描述，故于此不再赘述。
图26为本公开至少一实施例的显示装置的示意图。如图26所示，本实施例提供一种显示装置91，包括：显示基板910。显示基板910为前述实施例提供的显示基板。其中，显示基板910可以为OLED显示基板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (15)

  1. 一种显示基板，包括：
    显示区域和位于所述显示区域外围的周边区域；
    所述显示区域至少设置有多个子像素，至少一个子像素包括：设置在衬底基板上的像素驱动电路和与所述像素驱动电路连接的发光元件；所述像素驱动电路与第一初始信号线连接，所述第一初始信号线配置为在所述像素驱动电路的控制下，给所述发光元件提供第一初始电压；
    所述周边区域设置有第一电源线和信号连接线，所述第一初始信号线在所述周边区域通过所述信号连接线与所述第一电源线连接。
  2. 根据权利要求1所述的显示基板，其中，所述周边区域包括：第一边框区域、第二边框区域和绑定引脚区域，所述绑定引脚区域位于所述显示区域的一侧，所述第一边框区域位于所述绑定引脚区域和所述显示区域之间；所述第二边框区域与第一边框区域连通并围绕所述显示区域；
    所述信号连接线包括：第一连接线；所述第一连接线在所述第二边框区域与所述第一初始信号线和所述第一电源线连接；
    所述第一连接线位于所述第一电源线靠近所述显示区域的一侧。
  3. 根据权利要求2所述的显示基板，其中，所述第一连接线位于所述第一电源线远离所述衬底基板的一侧。
  4. 根据权利要求2或3所述的显示基板，其中，所述信号连接线还包括：第二连接线，所述第二连接线与所述第一初始信号线连接，所述第二连接线通过所述第一连接线与所述第一电源线连接；
    所述第二连接线位于所述第一连接线靠近所述显示区域的一侧。
  5. 根据权利要求4所述的显示基板，其中，所述第二连接线位于所述第一连接线靠近所述衬底基板的一侧，且位于所述第一初始信号线远离所述衬底基板的一侧。
  6. 根据权利要求4或5所述的显示基板，其中，所述第二连接线与所述第一电源线为同层结构。
  7. 根据权利要求2至6中任一项所述的显示基板，其中，所述第一连接线在所述周边区域内的延伸方向与所述第一初始信号线在所述显示区域内的延伸方向交叉。
  8. 根据权利要求2至7中任一项所述的显示基板，其中，所述显示区域包括：设置在所述衬底基板上的驱动结构层和发光元件，所述发光元件包括：第一电极、第二电极和设置在所述第一电极和第二电极之间的有机发光层；所述第一电极位于所述第二电极靠近所述衬底基板的一侧；
    所述第一连接线与所述发光元件的所述第一电极为同层结构。
  9. 根据权利要求8所述的显示基板，其中，所述驱动结构层包括：设置在所述衬底基板上的半导体层、第一栅金属层、第二栅金属层和源漏金属层；
    所述第一初始信号线与所述第二栅金属层为同层结构，所述第一电源线与所述源漏金属层为同层结构。
  10. 根据权利要求1所述的显示基板，其中，所述周边区域包括：第一边框区域、第二边框区域和绑定引脚区域，所述绑定引脚区域位于所述显示区域的一侧，所述第一边框区域位于所述绑定引脚区域和所述显示区域之间；所述第二边框区域与第一边框区域连通并围绕所述显示区域；
    所述信号连接线包括：第三连接线，所述第三连接线在所述第二边框区域与所述第一初始信号线连接，所述第三连接线在所述第一边框区域与所述第一电源线连接。
  11. 根据权利要求10所述的显示基板，其中，所述第三连接线与所述第一电源线为一体结构。
  12. 根据权利要求10所述的显示基板，其中，所述信号连接线还包括：第四连接线；所述第三连接线与所述第四连接线连接，所述第四连接线在所述第一边框区域与所述第一电源线连接；所述第四连接线位于所述第一电源线靠近所述衬底基板的一侧。
  13. 根据权利要求1至12中任一项所述的显示基板，其中，所述像素驱动电路包括：第一晶体管至第七晶体管；
    第一晶体管的控制极与第二扫描线连接，第一晶体管的第一极与第二初 始信号线连接，第一晶体管的第二极与第一节点连接；
    第二晶体管的控制极与第一扫描线连接，第二晶体管的第一极与第一节点连接，第二晶体管的第二极与第三节点连接；
    第三晶体管的控制极与第一节点连接，第三晶体管的第一极与第二节点连接，第三晶体管的第二极与第三节点连接；
    第四晶体管的控制极与第一扫描信号线连接，第四晶体管的第一极与数据信号线连接，第四晶体管的第二极与第二节点连接；
    第五晶体管的控制极与发光信号线连接，第五晶体管的第一极与第二电源线连接，第五晶体管的第二极与第二节点连接；
    第六晶体管的控制极与发光信号线连接，第六晶体管的第一极与第三节点连接，第六晶体管的第二极与第四节点连接；
    第七晶体管的控制极与第一扫描信号线连接，第七晶体管的第一极与第一初始信号线连接，第七晶体管的第二极与第四节点连接；
    所述发光元件的第一电极与第四节点连接，所述发光元件的第二电极与第一电源线连接。
  14. 一种显示装置，包括如权利要求1至13中任一项所述的显示基板。
  15. 一种显示基板的制备方法，用于制备如权利要求1至13中任一项所述的显示基板，所述制备方法包括：
    在显示区域形成多个子像素，在所述显示区域外围的周边区域形成第一电源线和信号连接线；
    其中，至少一个子像素包括：设置在衬底基板上的像素驱动电路和与所述像素驱动电路连接的发光元件；所述像素驱动电路与第一初始信号线连接，所述第一初始信号线配置为在所述像素驱动电路的控制下，给所述发光元件提供第一初始电压；所述第一初始信号线在在所述周边区域通过所述信号连接线与所述第一电源线连接。
PCT/CN2021/076457 2021-02-10 2021-02-10 显示基板及其制备方法、显示装置 WO2022170547A1 (zh)

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