WO2022007571A1 - 显示装置及其制作方法 - Google Patents
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- WO2022007571A1 WO2022007571A1 PCT/CN2021/098814 CN2021098814W WO2022007571A1 WO 2022007571 A1 WO2022007571 A1 WO 2022007571A1 CN 2021098814 W CN2021098814 W CN 2021098814W WO 2022007571 A1 WO2022007571 A1 WO 2022007571A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
- H10K77/10—Substrates, e.g. flexible substrates
- H10K77/111—Flexible substrates
Definitions
- the present disclosure relates to the field of display technology, and in particular, to a display device and a manufacturing method thereof.
- OLED display panels are being used more and more in conference rooms, home theaters, outdoor advertising and other fields. Therefore, the demand for large-size displays is increasing day by day. The requirements for high-quality technology for similar displays are also higher.
- Embodiments of the present disclosure provide a display device and a manufacturing method thereof, and the specific solutions are as follows:
- an embodiment of the present disclosure provides a display device, including:
- one side of the drive circuit board has a plurality of first connection electrodes
- a display module located on one side of the driving circuit board, the display module comprising a flexible substrate, a plurality of signal lines on the side of the flexible substrate away from the driving circuit board, and a plurality of signal lines on the flexible substrate
- the bottom faces a plurality of bottom electrodes on one side of the driving circuit board; wherein, the flexible substrate is provided with a plurality of first via holes in the display area of the display module, and the signal lines pass through the first via holes.
- the hole is electrically connected to the bottom electrode, and the bottom electrode is electrically connected to the first connection electrode.
- the plurality of signal lines include a plurality of scan signal lines, a plurality of data signal lines, and a plurality of high-level signal lines;
- the display module includes a pixel circuit located on the side of the flexible substrate away from the driving circuit board;
- the pixel circuit includes a first metal layer and a second metal layer, the second metal layer is located on a side of the first metal layer away from the flexible substrate;
- the first metal layer includes the plurality of scan signal lines and the plurality of high-level signal lines
- the second metal layer includes the plurality of data signal lines.
- the plurality of signal lines further include a plurality of low-level signal lines, and the low-level signal lines include a first metal layer located in the first metal layer. Low level signal line.
- the low-level signal line further includes a second sub-low-level signal line located in the second metal layer.
- At least one of the first sub-low-level signal lines and at least one of the second sub-low-level signal lines are electrically connected.
- the plurality of signal lines further include a plurality of sensing signal lines located in the second metal layer.
- the data signal line includes a plurality of first data signal lines and a plurality of second data signal lines, and at least one of the sensing signal lines is in the flexible
- the orthographic projection on the substrate is located between the orthographic projections of the two adjacent first data signal lines on the flexible substrate;
- the orthographic projections of at least one row of the bottom electrodes on the flexible substrate are located between the orthographic projections of two adjacent second data signal lines on the flexible substrate.
- the two first data signal lines and the one second data signal line located on the same side of the two first data signal lines are divided into A data signal line group;
- two adjacent first data signal lines have a first distance
- adjacent first data signal lines and second data signal lines have a second distance
- the first distance is less than the second distance
- the plurality of scan signal lines, the first sub-low-level signal lines, and the plurality of high-level signal lines extend along a first direction
- the plurality of data signal lines, the plurality of sensing signal lines and the second sub-low level signal lines extend along a second direction; the first direction and the second direction are arranged to intersect.
- the display module further includes an insulating layer located between the first metal layer and the second metal layer, and the insulating layer is located between the first metal layer and the second metal layer.
- the display area is provided with a plurality of second vias;
- the first metal layer further includes a plurality of first transfer electrodes, at least one of the data signal lines, and at least one of the sensing signal lines, respectively passing through the second via holes and the first transfer electrodes .
- the first via hole is electrically connected to the corresponding bottom electrode.
- the pixel circuit includes a capacitor
- the first metal layer further includes a first electrode plate of the capacitor
- the second metal layer further includes the capacitor The second electrode plate of the capacitor.
- the pixel circuit includes an oxide active layer, and the oxide active layer is located on a side of the first metal layer away from the flexible substrate .
- the display module further includes a flat layer and a light-emitting device located on a side of the pixel circuit away from the flexible substrate;
- the light-emitting device includes a light-emitting functional layer, a first electrode on the side of the light-emitting functional layer facing the flexible substrate, and a second electrode on the side of the light-emitting functional layer away from the flexible substrate;
- the flat layer includes a plurality of third via holes and a plurality of fourth via holes arranged in the display area, and the first electrode is electrically connected to the driving transistor of the pixel circuit through the third via holes, so the The second electrode is electrically connected to the second sub-low level signal line through the fourth via hole.
- the display module further includes a plurality of second transfer electrodes located on a side of the layer where the pixel circuit is located away from the flexible substrate, and the insulating
- the layer further includes a plurality of fifth via holes; the second electrode passes through the second transfer electrode, the fourth via hole, the second sub-low level signal line, the fifth via hole and all the The first sub-low level signal line is electrically connected.
- the plurality of second transition electrodes are provided in the same layer as the first electrodes.
- the pixel circuit further includes: a third metal layer located on a side of the second metal layer away from the flexible substrate, the third metal layer The plurality of second transition electrodes are included.
- the display module further includes: a pixel defining layer located between the layer where the first electrode is located and the light-emitting functional layer;
- the pixel defining layer includes a pixel opening exposing at least a portion of the first electrode, and a sixth via exposing the second via electrode.
- the display module further includes a thin film encapsulation layer on a side of the light-emitting device away from the flexible substrate.
- connection structure is further included, and the connection structure is electrically connected between the first connection electrode and the bottom electrode.
- connection structure includes at least one of anisotropic conductive adhesive, conductive silver paste, or an alloy formed by eutectic bonding.
- the driving circuit board further includes: a substrate having a plurality of seventh via holes, and a substrate located on a side of the substrate away from the plurality of first connection electrodes A plurality of second connection electrodes, at least part of the first connection electrodes are electrically connected to the second connection electrodes in a one-to-one correspondence through the seventh via holes.
- the extension direction of the first connection electrode and the extension direction of the second connection electrode are both substantially parallel to the extension direction of the plurality of scan signal lines .
- the driving circuit board further includes a protective film on a side of the plurality of second connection electrodes away from the substrate.
- a plurality of the display modules are spliced and arranged in a direction of one side of the driving circuit board having the plurality of first connection electrodes.
- the adjacent signal lines are electrically connected to the same second connection electrode through the first connection electrode.
- the ratio between the distance between the two adjacent pixel openings and the width of the seam between two adjacent display modules is 0.8-1.2.
- the display device further includes: a general encapsulation layer, a touch module and a protective cover plate which are sequentially located on the side of the display module away from the driving circuit board.
- a method for fabricating the above-mentioned display device provided by an embodiment of the present disclosure includes:
- a plurality of mutually independent display modules are formed on the peeling layer, and each of the display modules includes a flexible substrate, a plurality of signal lines on the flexible substrate, and a plurality of signal lines on the flexible substrate away from the flexible substrate. a plurality of bottom electrodes on one side of the plurality of signal lines; wherein, the flexible substrate is provided with a plurality of first via holes in the display area of the display module, and the signal lines are connected with the first via holes through the first via holes. the bottom electrode is electrically connected;
- a driving circuit board is provided, and one side of the driving circuit board has a plurality of first connection electrodes;
- At least one of the display modules is arranged on one side of the driving circuit board, so that the bottom electrode is electrically connected to the first connection electrode.
- FIG. 1 is a schematic structural diagram of a display module provided by an embodiment of the present disclosure
- FIG. 2 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure
- FIG. 3 is a layout of a pixel circuit provided by an embodiment of the present disclosure.
- FIG. 4 is a layout of a bottom electrode provided by an embodiment of the present disclosure.
- FIG. 5 is a layout of a via hole of a flexible substrate provided by an embodiment of the present disclosure.
- FIG. 6 is another via layout of the flexible substrate provided by the embodiment of the present disclosure.
- FIG. 7 is a layout of a first metal layer according to an embodiment of the present disclosure.
- FIG. 8 is a layout of a second metal layer according to an embodiment of the present disclosure.
- FIG. 9 is a schematic structural diagram of the pixel circuit shown in FIG. 3;
- FIG. 10 is a layout of a gate insulating layer provided by an embodiment of the present disclosure.
- FIG. 11 is a layout of an interlayer dielectric layer provided by an embodiment of the present disclosure.
- FIG. 12 is a layout of an oxide active layer provided by an embodiment of the present disclosure.
- FIG. 13 is a layout of a planarization layer provided by an embodiment of the present disclosure.
- FIG. 14 is a layout of a layer where the first electrode is provided according to an embodiment of the present disclosure.
- FIG. 15 is a layout of an inorganic insulating layer provided by an embodiment of the present disclosure.
- 16 is a layout of a pixel definition layer provided by an embodiment of the present disclosure.
- FIG. 17 is a layout of a first connection electrode provided by an embodiment of the present disclosure.
- FIG. 18 is a layout of a substrate provided by an embodiment of the present disclosure.
- FIG. 19 is a layout of a second connection electrode provided by an embodiment of the present disclosure.
- FIG. 20 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
- FIG. 21 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
- FIG. 22 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
- FIG. 23 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
- 24 to 32 are schematic structural diagrams of a display device in a manufacturing process according to an embodiment of the present disclosure.
- the signal lines included in the display module are generally electrically connected to the binding electrodes through the frame wiring, and the binding electrodes are electrically connected to the connecting electrodes of the driving circuit board, and the driving chip passes through the wiring of the driving circuit board.
- Load the connection electrodes with a drive signal Due to the existence of the frame traces, the path of the driving signal is long, so the large voltage drop of the driving signal affects the uniformity of the display.
- an embodiment of the present disclosure provides a display device, as shown in FIG. 1 to FIG. 6 , which may include:
- a drive circuit board 001 one side of the drive circuit board 001 has a plurality of first connection electrodes 101;
- the display module 002 is located on one side of the driving circuit board 001 , and the display module 002 may include a flexible substrate 201 , a plurality of signal lines 202 located on the side of the flexible substrate 201 away from the driving circuit board 001 , and the flexible substrate 201 A plurality of bottom electrodes 203 facing the side of the driving circuit board 001; wherein, the flexible substrate 201 is provided with a plurality of first via holes O 1 in the display area (Active Area, AA) of the display module 002, and the signal lines 202 pass through the first via holes O 1 .
- O 1 a via electrode 203 is electrically connected to the bottom, the bottom electrode 203 is electrically connected to the first electrode 101 is connected.
- the driving circuit board 001 is disposed on the side of the display module 002 away from the display area AA, and the first connection electrode 101 is electrically connected to the bottom electrode 203 of the display area AA, so as to provide a signal Line 202 provides the drive signal.
- the driving signal provided by the driving circuit board 001 is sequentially transmitted to the signal line 202 through the first connection electrode 101 and the bottom electrode 203, which avoids the transmission of the driving signal on the frame wiring in the related art, thus shortening the driving time.
- the propagation path of the signal can effectively reduce the voltage drop, which is beneficial to improve the display uniformity.
- the signal line 202 and the bottom electrode 203 are located within the display region AA, when the signal line 202 through the first hole on the flexible substrate 201 O 1 and the bottom electrode 203 is electrically connected via a corresponding bottom electrode 203 and the corresponding signal line 202 The electrical connection in the direction perpendicular to the display module 002 is realized, which prevents the bottom electrode 203 from occupying a part of the pixel area alone, thereby improving the pixel aperture ratio.
- the plurality of signal lines 102 may include a plurality of scanning signal lines G, a plurality of data signals Line D and multiple high-level signal lines VDD;
- the display module 002 may include a pixel circuit 204 located on the side of the flexible substrate 201 away from the driving circuit board 001;
- the pixel circuit 204 may include a first metal layer 2041 and a second metal layer 2042, and the second metal layer 2042 is located on a side of the first metal layer 2041 away from the flexible substrate 201;
- the first metal layer 2041 may include a plurality of scan signal lines G and a plurality of high-level signal lines VDD, and the second metal layer 2042 may include a plurality of data signal lines D.
- the plurality of signal lines 102 may further include a plurality of low-level signal lines VSS.
- the level signal line VSS may include a first sub-low level signal line V1 located at the first metal layer 2041 .
- the low-level signal line VSS may further include a second sub-low-level signal line V2 located in the second metal layer 2042, the second sub-low-level signal line V2 and the first sub-low-level signal line V2
- the line V1 is electrically connected, so that the signal on the low-level signal line VSS can be transmitted along the direction perpendicular to the display module 002, thereby reducing the transmission path of the signal on the low-level signal line VSS. It should be understood that, since a fixed potential is loaded on the low-level signal line VSS, in order to facilitate the loading of signals, at least one first sub-low-level signal line V1 and at least one second sub-low-level signal line V2 are connected. electrical connection.
- the plurality of signal lines 102 may further include a plurality of sensing lines located on the second metal layer 2042 Signal line S. That is, the plurality of sensing signal lines S and the plurality of data signal lines D are disposed in the same layer, and both are located in the second metal layer 2042 . This avoids adding a plurality of film layers for the sensing signal lines S, saves a mask process, and has fewer film layers, which is in line with the development trend of light and thin products.
- the plurality of data signal lines D may include a plurality of first data signal lines D1 and a plurality of second data signal lines D1
- the orthographic projection of at least one sensing signal line S on the flexible substrate 201 is located between the orthographic projections of the two adjacent first data signal lines D1 on the flexible substrate 201; specifically, as shown in FIG.
- the orthographic projection of at least one row of bottom electrodes 203 on the flexible substrate 201 can be set between the orthographic projections of two adjacent second data signal lines D2 on the flexible substrate 201, so as to utilize the second data signal lines D2 reasonably. space between.
- two first data signal lines D1 and one second data signal line D2 located on the same side of the two first data signal lines D1 are divided into one data signal line group D12;
- a first distance d1 exists between two adjacent first data signal lines D1, a second distance d2 exists between adjacent first data signal lines D1 and second data signal lines D2, and the first The distance d1 is smaller than the second distance d2;
- FIG. 8 shows that the two data signal line groups D12 are symmetrical about the Z axis.
- the smaller first distance d1 can satisfy the routing space of the sensing signal lines S.
- the larger second distance d2 is beneficial for arranging the bottom electrodes 203 within the range of the second distance d2, so that the orthographic projection of the bottom electrodes 203 of at least one row on the flexible substrate 201 can be located in two adjacent second data signals Line D2 is between the orthographic projections on the flexible substrate 201 .
- the electrical connection between the sensing signal line S and the bottom bottom electrode 203 is realized by punching through holes.
- the pattern of the sensing signal line S at the position of the via hole needs to be covered.
- Via holes In the case of large via holes, the width of the sensing signal line S at the via hole position needs to be increased.
- the first data signal line D1 adjacent to the sensing signal line S needs to set a corner f to avoid the sensing signal line S at the position of the via hole and prevent the sensing signal line S and the first data signal line D1. short-circuit.
- the shape of the second data signal line D2 and the first data signal line D1 can be set to be the same, that is, the second data signal line D2 also has a corner f.
- the plurality of scan signal lines G, the first sub-low-level signal lines V1 and the plurality of high-level signal lines VDD may extend along the first direction Y
- the plurality of data signal lines D, the plurality of sensing signal lines S and the second sub-low level signal lines V2 may extend along the second direction X; the first direction Y and the second direction X are arranged to intersect.
- the plurality of scan signal lines G include a plurality of first scan signal lines G1 and a plurality of second scan signal lines G2.
- the pixel circuit 204 may include a driving transistor M1, a first transistor M2, a second transistor M3, a capacitor C1 and a light-emitting element EL (eg, OLED or QLED); wherein, the first transistor M2
- the gate of the first transistor M2 is electrically connected to the first scanning signal line G1, the first pole of the first transistor M2 is electrically connected to the data signal line D, and the second pole of the first transistor M2 is electrically connected to the gate of the driving transistor M1;
- the second transistor M2 is electrically connected to the gate of the driving transistor M1;
- the gate of M3 is electrically connected to the second scanning signal line G2, the first pole of the second transistor M3 is electrically connected to the sensing signal line S, and the second pole of the second transistor M3 is electrically connected to the second pole of the driving transistor M1;
- the capacitor C1 is connected between the gate of the driving transistor M1 and the second electrode of the driving transistor M1; the first electrode of the driving transistor M1 is
- the sensing signal line S can realize threshold voltage compensation of the driving transistor M1 through the second transistor M3, and the data signal line D can write data to the gate of the driving transistor M1 through the first transistor M2
- the storage capacitor C1 can store the gate voltage of the driving transistor M1 and the second pole voltage of the driving transistor M1, and the driving transistor M1 can provide the light-emitting element EL with the operating current after threshold compensation.
- the display module 002 may further include a The insulating layer 205, the insulating layer 205 is provided with a plurality of second via holes O 2 in the display area AA;
- the first metal layer 2041 also includes a plurality of first transfer electrodes P1; at least one data signal line D, and at least one sensing signal line S, which pass through the second via hole O 2 , the first transfer electrode P1, the first The via hole O 1 (specifically, O 1 ′ shown in FIG. 2 ) is electrically connected to the corresponding bottom electrode 203 , so that the data signal line D and the sensing signal line S can be loaded with corresponding driving signals.
- the insulating layer 205 may include an interlayer dielectric layer 2051 and a gate insulating layer 2052
- FIG. 10 specifically shows that the interlayer dielectric layer 2051 and the gate insulating layer 2052 are penetrated and electrically connected The sensing signal line S and the second via hole O 2 of the first via electrode P1 .
- FIG. 11 shows the via hole penetrating the interlayer dielectric layer 2051 and connecting the source and drain of the transistor with the active layer. It should be noted that, in FIG.
- O 2 ′ is a through hole passing through the interlayer dielectric layer 2051 and the gate insulating layer 2052 and electrically connecting the first electrode of the driving transistor M1 and the high-level signal line VDD
- O 2 ′′ is a through hole passing through The interlayer dielectric layer 2051 and the gate insulating layer 2052 are electrically connected to the gate of the driving transistor M1, the first electrode plate C11 of the capacitor C1, and the through hole of the second electrode of the first transistor M2.
- the first metal layer 2041 may further include the first electrode plate C11 of the capacitor C1 , and the second metal layer 2042 The second electrode plate C12 of the capacitor C1 may also be included. In this way, there is no need to add two conductive layers to manufacture the first electrode plate C11 and the second electrode plate C12 of the capacitor C1, which reduces the process flow.
- the pixel circuit 204 may include an oxide active layer, and the oxide active layer is located on the first metal layer 2041 The side facing away from the flexible substrate 201 .
- Oxide active layer transistors are suitable for realizing large-scale video wall display products.
- each of the included transistors may be bottom-gate transistors, that is, the first metal layer 2041 may include gates of the respective transistors, so as to facilitate connection to the bottom electrode 203 .
- the first metal layer 2041 has the function of voltage stabilization and shielding, which can prevent interference to the signal of the oxide active layer.
- the display module 002 may further include a pixel circuit 204 on the side away from the flexible substrate 201 .
- the light-emitting device 207 may include a light-emitting functional layer 2071, a first electrode 2072 on the side of the light-emitting functional layer 2071 facing the flexible substrate 201, and a second electrode 2073 on the side of the light-emitting functional layer 2071 facing away from the flexible substrate 201;
- the flat layer 206 includes a plurality of third via holes O 3 and a plurality of fourth via holes O 4 arranged in the display area AA, and the first electrode 2072 is electrically connected to the driving transistor M1 of the pixel circuit 204 through the third via hole O 3 , the second electrode 2073 via a fourth O 4 connected to the second sub-power line V2 through the low-level signal.
- an inorganic insulating layer (PVX) 208 is provided between the planarization layer 206 and the second metal layer 2042 .
- the inorganic insulating layer 208 is provided with corresponding through holes at the third via hole O 3 and the fourth via hole O 4 of the flat layer 206 .
- the light emitting functional layer 2071 may include, but is not limited to, a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer.
- the display module 002 may further include a flexible lining located at the layer where the pixel circuit 204 is located away from A plurality of second transfer electrodes P2 on one side of the bottom 201, the second metal layer 2042 may further include a plurality of third transfer electrodes P3, and the insulating layer 205 may further include a plurality of fifth via holes O 5 ; the second electrode 2073 passes through second switching electrode P2, the fourth via O 4, the second sub-line low-level signal V2, and the fifth O 5 via a first sub-signal line V1 is electrically connected to a low level.
- the display module 002 may further include: located between the layer where the first electrode 2072 is located and the light-emitting functional layer 2071 The pixel definition layer 209;
- the pixel defining layer 209 includes a pixel opening K exposing at least a part of the first electrode 2072, and a sixth via hole O 6 exposing the second via electrode P2.
- O sixth through hole 6 is provided, so that the signal can provide a low level signal line VSS in the display region AA of the flexible substrate 201 from the second electrode to the transfer direction departing from the driving circuit board 001 of 2073, compared to the related art
- the solution of providing the second electrode 2073 with a low-level signal through the frame wiring in the middle scheme greatly reduces the transmission path of the low-level signal, which is beneficial to reduce the voltage drop of the low-level signal.
- a plurality of second via electrodes P2 can be disposed in the same layer as the first electrodes 2072 to save mask process and reduce product thickness.
- a third metal layer may also be disposed between the planarization layer 206 and the layer where the pixel circuit 204 is located, and the third metal layer may include a plurality of second transfer electrodes P2.
- the display module 002 may further include a thin film encapsulation layer 210 on the side of the light emitting device 207 away from the flexible substrate 201 .
- the thin film encapsulation layer 210 may include two inorganic encapsulation layers, and an organic encapsulation layer between the two inorganic encapsulation layers.
- the packaging may also be performed by means of lamination or the like.
- connection structure 003 connected between the first connection electrode 101 and the bottom electrode 203 may be used to realize the connection between the first connection electrode 101 and the bottom electrode 203 .
- the connection structure 003 may be at least one of anisotropic conductive paste, conductive silver paste, or an alloy formed by eutectic bonding.
- the anisotropic conductive adhesive is conductive in the Z direction, but not in the X direction and the Y direction, the electrical connection between the first connection electrode 101 and the corresponding bottom electrode 201 can be realized by the anisotropic conductive adhesive.
- the anisotropic conductive adhesive itself is viscous, so the display module 002 can also be fixed on the driving circuit board 001 while conducting the signal, which simplifies the manufacturing process.
- the binding method of eutectic bonding or the binding method of conductive silver paste can also fix the display module 002 on the driving circuit board 001 while realizing signal conduction, which simplifies the manufacturing process.
- the driving circuit 001 may further include: a substrate 102 having a plurality of seventh via holes O 7 and a plurality of the substrate 102 facing away from the side of the first connection electrode 101 connecting the plurality of second electrode 103, at least a portion of the first electrode 101 is connected through a seventh via hole O 7 and the second connection electrode 103 is electrically connected to one correspondence.
- each of the first connection electrodes 101 is electrically connected to the second connection electrodes 103 through the seventh via hole O 7 .
- the driving circuit 001 may only include a driver that provides driving signals for the second connection electrodes 101 .
- Chip (IC) in some embodiments, part of the first connection electrodes 101 are electrically connected to the second connection electrodes 103 through the seventh via hole O 7 , and the rest of the first connection electrodes 101 are separately disposed on the driving circuit board 001 .
- the driving circuit 001 may include a first driving chip (IC1) providing driving signals for the second connecting electrodes 101, and a second driving chip (IC2) providing driving signals for the remaining first connecting electrodes 101 directly.
- the driver chip may include, but is not limited to, a gate driver circuit (Gate GOA), a source driver circuit (Source IC), an emissive control circuit (EM GOA), and the like.
- the gate driving circuit, source driving circuit and light-emitting control circuit in the related art are generally arranged in the frame area of the large-size display device.
- On the driving circuit board 001 it is avoided to set the gate driving circuit, the source driving circuit and the light-emitting control circuit in the frame area of each display module 002, so that the frame area of each display module 002 is very narrow and can even be eliminated. Therefore, when a large-size display device is formed by splicing a plurality of display modules 002, the non-display area between adjacent display modules 002 is mainly seam A, which enhances the overall display uniformity.
- the extension direction of the first connection electrode 101 and the extension direction of the second connection electrode 103 are both It is substantially parallel to the extending direction of the plurality of scanning signal lines G, so as to transfer driving signals to the second metal layer 2042 and the light emitting device 207 through the first metal layer 2041 where the plurality of scanning signal lines G are located.
- the driving circuit board 001 may further include a protective film 104 on the side of the plurality of second connection electrodes 103 away from the substrate 102 , so as to realize the driving Protection of components on circuit board 001.
- the length of the signal lines included in the large-size OLED display is relatively large, which makes the path of the driving signal long, and also causes a large voltage drop in the driving signal, which affects the uniformity of the display.
- a plurality of display modules 002 are spliced and arranged on one side of the driving circuit board 001 having the plurality of first connection electrodes 101 .
- the driving signal path provided by the driving circuit board 001 is the first connection electrode 101 of the driving circuit board 001 ⁇ the bottom electrode 203 of the small-size display module 002 ⁇ the small-size display
- the signal line 202 of the module 002; while the driving signal path of the large-size display device in the related art is the first connection electrode 101 of the driving circuit board 002 ⁇ the binding terminal of the large-size display module frame area ⁇ the large-size display module frame
- the connecting line of the area ⁇ the signal line of the large-size display module, the comparison shows that the path of the driving circuit in the present disclosure is shorter, and the length of the signal line 202 of the small-size display module 002 is shorter than that of the large-size display module. Therefore, the present disclosure can effectively reduce the pressure drop and improve the display uniformity.
- the first connection electrodes 101 of the driving circuit board 001, the signal lines 202 of the display area AA included in the display module 02 and the connection lines of the frame area are all copper wires, and the first connection electrodes 101 of the driving circuit board 001 are larger than
- the signal lines 202 and the frame traces of the display module 002 are much thicker, so in the present disclosure, the voltage drop of the driving signal mainly depends on the voltage drop on the signal lines 202 included in the display module 02 with a smaller size, that is to say , the voltage drop of the large-size splicing display device provided by the present disclosure is equivalent to the voltage drop level of the smaller-size display module 02 .
- the pressure drop level is reduced to 1/2 of the pressure drop level of a large-size display device in the related art.
- the power supply voltage is generally increased, thereby increasing the power consumption of the display device.
- the effect of voltage drop is well improved, so the power consumption of a large-size display device can be reduced, for example, the power consumption can be reduced by 1/2.
- the size and resolution specifications of medium and large size display devices are very limited, but there are different requirements for some details such as camera opening, frame, AA arc chamfer, etc., product development costs are high, and the manufacturing process is complicated.
- different display modules 002 can be manufactured and assembled to obtain products with different shapes and details corresponding to different requirements, thereby saving mask development time and verification time, and improving product development speed.
- wiring of various components and chips can be performed on the driving circuit board 001 as the base substrate, so that a variety of optical, radio frequency and acoustic devices can be placed in the display device, which helps to improve the integration degree of end products and increase the Layout flexibility.
- the adjacent signal line 202 may be electrically connected to the same second connection electrode 103 through the first connection electrode 101 .
- the two end points of the signal line 202 may be electrically connected to one first connection electrode 101 correspondingly, and the two first connection electrodes 101 that are electrically connected to the adjacent end points of the two signal lines 202 are substantially located on the same line, so
- the corresponding two second connection electrodes 103 have an integrated structure, which facilitates signal transmission on adjacent display modules 002 .
- the ratio between the spacing between the adjacent two pixel openings K and the width of the seam A of the adjacent two display modules 002 may be: 0.8-1.2, preferably 1.
- the visual uniformity at the seam A is consistent with that in the display area AA of each display module 02 .
- FIG. 22 exemplarily shows the red light emitting device R, the green light emitting device G and the blue light emitting device B, wherein the red light emitting device R, the green light emitting device G and the blue light emitting device B are one cycle in the row direction
- the light-emitting devices in the column direction have the same color; of course, the light-emitting devices at the pixel opening K may also be arranged using various HDR algorithms during specific implementation.
- the display device may further include: a general encapsulation layer 004 and a touch module 005 which are sequentially located on the side of the display module 002 away from the driving circuit board 001 . and protective cover 006.
- the total encapsulation layer 004 can prevent water and oxygen from invading into the display module 002 through the seams between adjacent display modules 002, thereby improving the use of the product life.
- the touch module 005 may be a single-piece glass touch (OGS) touch module, an external single-layer touch module or an external double-layer touch module, etc., which are not limited herein.
- the protective cover plate 006 may be a hard glass cover plate or a soft glass cover plate, which is not limited herein.
- an embodiment of the present disclosure provides a method for manufacturing the above-mentioned display device. Since the principle of solving the problem of the manufacturing method is similar to the principle of solving the problem of the above-mentioned display device, the manufacturing method provided by the embodiment of the present disclosure has the advantages of For the implementation, reference may be made to the implementation of the above-mentioned display device provided by the embodiments of the present disclosure, and repeated details will not be repeated.
- the manufacturing method of the above-mentioned display device further provided by the embodiment of the present disclosure includes the following steps:
- a plurality of independent display modules are formed on the peeling layer, and each display module includes a flexible substrate, a plurality of signal lines on the flexible substrate, and a plurality of signal lines on the side of the flexible substrate away from the plurality of signal lines a bottom electrode; wherein the flexible substrate is provided with a plurality of first via holes in the display area of the display module, and the signal line is electrically connected to the bottom electrode through the first via holes;
- a driving circuit board is provided, and one side of the driving circuit board has a plurality of first connection electrodes;
- At least one display module is arranged on one side of the driving circuit board, so that the bottom electrode is electrically connected with the first connection electrode.
- Step 1 As shown in Figure 24, a motherboard 007 is provided.
- the second step as shown in FIG. 25 , a peeling layer 008 is formed on the mother board 007 .
- the third step forming a plurality of independent display modules 002 on the peeling layer 008.
- this step may specifically include:
- a plurality of bottom electrodes 203 in the display area AA are formed on the peeling layer 008;
- a flexible substrate 201 is formed on the layer where the plurality of bottom electrodes 203 are located, wherein the flexible substrate 201 has a first via O 1 in a region corresponding to each bottom electrode 203 , and the region H having an opening; alternatively, may be realized via making a first flexible substrate 201 O 1 contained by a dry etching process or a laser drilling and the like.
- the flexible substrate 201 made of polyimide (PI) is thicker, the hardness is higher.
- a first metal layer 2041 , a gate insulating layer 2052 , an oxide active layer 2043 , an interlayer dielectric layer 2051 , a second metal layer 2042 , and an inorganic insulating layer are sequentially formed on the flexible substrate 201 layer 208 , flat layer 206 , first electrode 2072 , pixel defining layer 209 , light-emitting functional layer 2071 , second electrode 2073 and thin film encapsulation layer 210 . Since the specific structure of each film layer has been introduced above, it will not be repeated here.
- the performance test can be performed on each display module 002 after this step is completed, the display modules 002 with poor manufacturing are screened out at this stage, and the display modules 002 with normal performance are subsequently spliced in the It is sufficient to form a large-sized display device on the driving circuit board 001 .
- the present disclosure greatly reduces the cost and glass loss.
- the fourth step cutting the motherboard 007 to obtain a plurality of display modules 002; specifically, the plurality of display modules 002 can be obtained by means of laser cutting or mask etching.
- Step 5 As shown in FIG. 31 , separate the display module 002 from the peeling layer 008 .
- Step 6 As shown in FIG. 32 , a driver circuit board 001 is provided, the driver circuit board 001 includes a substrate 102 , a plurality of first connection electrodes 101 , a plurality of second connection electrodes 103 , a driver chip IC and a protective film 104 .
- the seventh step is to perform splicing of at least one display module 002 on the driving circuit board 001, and make each first connection electrode 101 pass through a connection structure formed by anisotropic conductive glue, conductive silver paste or eutectic bonded alloy. 003 is electrically connected to the corresponding bottom electrode 203 .
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Abstract
Description
Claims (28)
- 一种显示装置,其中,包括:驱动电路板,所述驱动电路板的一侧具有多个第一连接电极;显示模组,位于所述驱动电路板的一侧,所述显示模组包括柔性衬底、位于所述柔性衬底背离所述驱动电路板一侧的多条信号线、以及位于所述柔性衬底面向所述驱动电路板一侧的多个底电极;其中,所述柔性衬底在所述显示模组的显示区设置有多个第一过孔,所述信号线通过所述第一过孔与所述底电极电连接,所述底电极与所述第一连接电极电连接。
- 如权利要求1所述的显示装置,其中,所述多条信号线包括多条扫描信号线、多条数据信号线和多条高电平信号线;所述显示模组包括位于所述柔性衬底背离所述驱动电路板一侧的像素电路;所述像素电路包括第一金属层和第二金属层,所述第二金属层位于所述第一金属层背离所述柔性衬底的一侧;所述第一金属层包括所述多条扫描信号线和所述多条高电平信号线,所述第二金属层包括所述多条数据信号线。
- 如权利要求2所述的显示装置,其中,所述多条信号线还包括多条低电平信号线,所述低电平信号线包括位于所述第一金属层的第一低电平信号线。
- 如权利要求3所述的显示装置,其中,所述低电平信号线还包括位于所述第二金属层的第二子低电平信号线。
- 如权利要求4所述的显示装置,其中,至少一条所述第一子低电平信号线同至少一条所述第二子低电平信号线之间电连接。
- 如权利要求5所述的显示装置,其中,所述多条信号线还包括位于所述第二金属层的多条感测信号线。
- 如权利要求6所述的显示装置,其中,所述数据信号线包括多条第一 数据信号线和多条第二数据信号线,至少一条所述感测信号线在所述柔性衬底上的正投影位于相邻两条所述第一数据信号线在所述柔性衬底上的正投影之间;至少一行所述底电极在所述柔性衬底上的正投影位于相邻两条所述第二数据信号线在所述柔性衬底上的正投影之间。
- 如权利要求7所述的显示装置,其中,两条所述第一数据信号线和位于两条所述第一数据信号线同一侧的一条所述第二数据信号线被划分为一个数据信号线组;在至少一个所述数据信号线组中,相邻两个所述第一数据信号线存在第一距离,相邻的所述第一数据信号线和所述第二数据信号线存在第二距离,所述第一距离小于所述第二距离;存在至少两个相邻所述数据信号线组轴对称设置。
- 如权利要求6所述的显示装置,其中,所述多条扫描信号线、所述第一子低电平信号线和所述多条高电平信号线沿第一方向延伸,所述多条数据信号线、所述多条感测信号线和所述第二子低电平信号线沿第二方向延伸;所述第一方向与所述第二方向交叉设置。
- 如权利要求6所述的显示装置,其中,所述显示模组还包括位于所述第一金属层与所述第二金属层之间的绝缘层,所述绝缘层在所述显示区设置有多个第二过孔;所述第一金属层还包括多个第一转接电极,至少一条所述数据信号线、以及至少一条所述感测信号线,分别通过所述第二过孔、所述第一转接电极、所述第一过孔与对应的所述底电极电连接。
- 如权利要求2所述的显示装置,其中,所述像素电路包括电容,所述第一金属层还包括所述电容的第一电极板,所述第二金属层还包括所述电容的第二电极板。
- 如权利要求2所述的显示装置,其中,所述像素电路包括氧化物有源层,所述氧化物有源层位于所述第一金属层背离所述柔性衬底的一侧。
- 如权利要求4所述的显示装置,其中,所述显示模组还包括位于所述像素电路背离所述柔性衬底一侧的平坦层和发光器件;所述发光器件包括发光功能层,位于所述发光功能层面向所述柔性衬底一侧的第一电极,以及位于所述发光功能层背离所述柔性衬底一侧的第二电极;所述平坦层包括在所述显示区设置的多个第三过孔和多个第四过孔,所述第一电极通过所述第三过孔与所述像素电路的驱动晶体管电连接,所述第二电极通过所述第四过孔与所述第二子低电平信号线电连接。
- 如权利要求13所述的显示装置,其中,所述显示模组还包括位于所述像素电路所在层背离所述柔性衬底一侧的多个第二转接电极,所述绝缘层还包括多个第五过孔;所述第二电极通过所述第二转接电极、所述第四过孔、所述第二子低电平信号线、所述第五过孔与所述第一子低电平信号线电连接。
- 如权利要求14所述的显示装置,其中,所述多个第二转接电极与所述第一电极同层设置。
- 如权利要求14所述的显示装置,其中,所述像素电路还包括:位于所述第二金属层背离所述柔性衬底一侧的第三金属层,所述第三金属层包括所述多个第二转接电极。
- 如权利要求13所述的显示装置,其中,所述显示模组还包括:位于所述第一电极所在层与所述发光功能层之间的像素界定层;所述像素界定层包括暴露出至少部分所述第一电极的像素开口,以及暴露出所述第二转接电极的第六过孔。
- 如权利要求13所述的显示装置,其中,所述显示模组还包括位于所述发光器件背离所述柔性衬底一侧的薄膜封装层。
- 如权利要求1-18任一项所述的显示装置,其中,还包括连接结构,所述连接结构电连接于所述第一连接电极和所述底电极之间。
- 如权利要求19所述的显示装置,其中,所述连接结构包括异方性导电胶、导电银浆或通过共晶键合的方式形成的合金中的至少一种。
- 如权利要求2-18任一项所述的显示装置,其中,所述驱动电路板还包括:具有多个第七过孔的基板、以及位于所述基板背离所述多个第一连接电极一侧的多个第二连接电极,至少部分所述第一连接电极通过所述第七过孔与所述第二连接电极一一对应电连接。
- 如权利要求21所述的显示装置,其中,所述第一连接电极的延伸方向、以及所述第二连接电极的延伸方向均与所述多条扫描信号线的延伸方向大致平行。
- 如权利要求22所述的显示装置,其中,所述驱动电路板还包括位于所述多个第二连接电极背离所述基板一侧的保护膜。
- 如权利要求21所述的显示装置,其中,在所述驱动电路板具有所述多个第一连接电极的一侧方向上,拼接设置有多个所述显示模组。
- 如权利要求24所述的显示装置,其中,相邻所述信号线通过所述第一连接电极与同一个所述第二连接电极电连接。
- 如权利要求24所述的显示装置,其中,相邻两个所述像素开口的间距与相邻两个所述显示模组的拼缝宽度之比为0.8-1.2。
- 如权利要求24所述的显示装置,其中,还包括:依次位于所述显示模组背离所述驱动电路板一侧的总封装层、触控模组和保护盖板。
- 一种如权利要求1-27任一项所述显示装置的制作方法,其中,包括:提供一母板;在所述母板上形成剥离层;在所述剥离层上形成相互独立的多个显示模组,每个所述显示模组包括柔性衬底、位于所述柔性衬底上的多条信号线、以及位于所述柔性衬底背离所述多条信号线一侧的多个底电极;其中,所述柔性衬底在所述显示模组的显示区设置有多个第一过孔,所述信号线通过所述第一过孔与所述底电极电连接;切割母板,获得多个所述显示模组;将所述显示模组与所述剥离层进行分离;提供一个驱动电路板,所述驱动电路板的一侧具有多个第一连接电极;将至少一个所述显示模组设置在所述驱动电路板的一侧,使得所述底电极与所述第一连接电极电连接。
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US17/922,411 US20230320146A1 (en) | 2020-07-07 | 2021-06-08 | Display device and method for manufacturing the same |
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CN202010645247.4A CN111681610A (zh) | 2020-07-07 | 2020-07-07 | 一种显示装置及其制作方法 |
CN202110436352.1A CN113920943B (zh) | 2020-07-07 | 2021-04-22 | 显示装置及其制作方法 |
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CN114864624A (zh) * | 2022-05-12 | 2022-08-05 | 滁州惠科光电科技有限公司 | 显示面板及显示器 |
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CN113745303A (zh) * | 2021-09-06 | 2021-12-03 | 武汉华星光电半导体显示技术有限公司 | 显示面板及显示装置 |
CN116072010A (zh) * | 2021-11-02 | 2023-05-05 | 武汉华星光电半导体显示技术有限公司 | 拼接显示面板和显示装置 |
CN116071992A (zh) * | 2021-11-02 | 2023-05-05 | 武汉华星光电半导体显示技术有限公司 | 显示面板和显示装置 |
CN116096168A (zh) * | 2021-11-02 | 2023-05-09 | 武汉华星光电半导体显示技术有限公司 | 显示面板和显示装置 |
CN114973983B (zh) * | 2022-05-31 | 2024-04-30 | 武汉华星光电半导体显示技术有限公司 | 一种拼接显示面板 |
CN115019677B (zh) * | 2022-07-01 | 2023-12-22 | 昆山国显光电有限公司 | 显示面板及其制备方法、显示装置的制备方法 |
CN117769733A (zh) * | 2022-07-25 | 2024-03-26 | 厦门市芯颖显示科技有限公司 | 拼接显示面板和显示装置 |
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CN114864624B (zh) * | 2022-05-12 | 2023-08-08 | 滁州惠科光电科技有限公司 | 显示面板及显示器 |
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CN111681610A (zh) | 2020-09-18 |
US20230320146A1 (en) | 2023-10-05 |
CN113920943A (zh) | 2022-01-11 |
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