WO2024001256A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024001256A1
WO2024001256A1 PCT/CN2023/078659 CN2023078659W WO2024001256A1 WO 2024001256 A1 WO2024001256 A1 WO 2024001256A1 CN 2023078659 W CN2023078659 W CN 2023078659W WO 2024001256 A1 WO2024001256 A1 WO 2024001256A1
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WIPO (PCT)
Prior art keywords
driving unit
signal line
layer
gate driving
display area
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Application number
PCT/CN2023/078659
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English (en)
French (fr)
Inventor
胡俊艳
戴超
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2024001256A1 publication Critical patent/WO2024001256A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • level transmission signal lines are used to connect gate drive units of different levels so that signals can be transmitted.
  • the level transmission signal line overlaps with other metals, which will lead to a large parasitic capacitance, the level transmission signal line cannot be set in the area corresponding to the gate drive unit. A separate area needs to be set up for the level transmission signal line, resulting in a larger frame of the display panel. .
  • Embodiments of the present application provide a display panel and a display device to alleviate the technical problem of existing display devices that require a separate area for tiered signal lines, resulting in a larger frame.
  • An embodiment of the present application provides a display panel, which includes: a display area and a non-display area provided on at least one side of the display area; the display panel further includes:
  • a driving circuit layer is provided on one side of the substrate, and the driving circuit layer includes: a multi-level gate driving unit arranged in the non-display area, and a stage conductor connecting the gate driving units of different levels. signal line;
  • the driving circuit layer includes: a first semiconductor layer provided on one side of the substrate, the first semiconductor layer includes a plurality of first semiconductors provided in a non-display area, and the gate driving unit includes The first semiconductor;
  • the level transmission signal line is disposed between the first semiconductor layer and the substrate, and overlaps with at least part of the gate driving unit in the non-display area.
  • the driving circuit layer further includes: a first metal layer disposed on a side of the first semiconductor layer away from the substrate, and the first metal layer includes a first metal layer disposed in the non-display area. a gate, the gate driving unit includes the gate;
  • the cascade signal line overlaps at least part of the gate electrode in the non-display area.
  • the driving circuit layer further includes: a second metal layer disposed on a side of the first metal layer away from the substrate, and the second metal layer includes a second metal layer disposed on the non-display area.
  • Metal wiring, the gate driving unit includes the metal wiring;
  • the level transmission signal line overlaps with at least part of the metal wiring in the non-display area.
  • the driving circuit layer further includes: a source and drain layer disposed on a side of the second metal layer away from the first metal layer, and the gate driving unit includes a transistor, and the transistor It includes a first electrode and a second electrode disposed on the source and drain layer, and the first electrode is connected to the level transmission signal line through a first via hole.
  • the first electrode is connected to the first semiconductor through a second via hole, and the width of the first via hole is greater than the width of the second via hole.
  • the driving circuit layer further includes: a source and drain layer disposed on a side of the second metal layer away from the first metal layer, and the gate driving unit includes a transistor, and the transistor Including a first electrode and a second electrode provided on the source and drain layer, the display panel also includes a connecting metal, the first electrode is connected to the level transmission signal line through the connecting metal, and the connecting metal passes through The vias connect to the stage signal lines.
  • the display panel further includes a light-emitting layer disposed on a side of the driving circuit layer away from the substrate, and the light-emitting layer includes: a pixel light-emitting unit disposed in the display area,
  • the driving circuit layer further includes a pixel driving unit disposed in the display area and driving the pixel light-emitting unit, and a light-shielding layer disposed between the pixel driving unit and the substrate,
  • the light-shielding layer includes: a light-shielding portion provided in the display area and overlapped with the pixel driving unit, and the level transmission signal line provided in the non-display area.
  • the first semiconductor layer further includes a plurality of second semiconductors disposed in the display area, and the pixel driving unit includes the second semiconductors;
  • the first semiconductor includes a first channel region, and the level transmission signal line is not overlapped with the first channel region;
  • the second semiconductor includes a second channel region, and the light shielding portion overlaps with the second channel region.
  • the driving circuit layer further includes: a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate,
  • the second semiconductor layer includes a plurality of third semiconductors disposed in the display area, the pixel driving unit further includes the third semiconductor, and the third semiconductor includes a metal oxide material;
  • the light shielding portion and the third semiconductor are not overlapped.
  • the pixel driving unit includes:
  • the first initialization transistor is connected to the first initialization signal line.
  • the gate of the first initialization transistor is connected to the first scan signal line of the first gate driving unit.
  • the first initialization transistor is used to activate the first scan signal when the first scan signal line is connected to the first scan signal line. Under the control of, input the first initialization signal to the first node;
  • a switching transistor used to input a data signal to the second node under the control of the second scan signal
  • a driving transistor used to drive the pixel light-emitting unit to emit light under the control of the first node and the second node potential
  • a compensation transistor is connected to the driving transistor through the first node and the third node, the gate of the compensation transistor is connected to the second scanning signal line of the second gate driving unit, and the compensation transistor is used to Under the control of three scan signals, compensate the threshold voltage of the driving transistor;
  • the gate driving unit includes: the first gate driving unit and the second gate driving unit of different stages, and one end of the stage transmission signal line is connected to the first gate driving unit, so The other end of the stage transmission signal line is connected to the second gate driving unit along the gate driving circuit area.
  • the gate driving unit further includes a third gate driving unit, the gate driving circuit area includes a first wiring area and a second wiring area, the first gate driving unit and The second gate driving unit is provided in the first wiring area, the third gate driving unit is provided in the second wiring area, and at least part of the stage transmission signal line is provided in the second wiring area. wiring area.
  • the first gate driving unit is connected to the stage transmission signal line through a via at the junction of the first wiring area and the second wiring area
  • the second The gate driving unit is connected to the stage transmission signal line through a via hole at the junction of the first wiring area and the second wiring area.
  • the display panel further includes a connection wiring area disposed between the gate driving circuit area and the display area, and the second wiring area is disposed in the first wiring area. and the connection wiring area, the level transmission signal line extends from the second wiring area to the connection wiring area.
  • a display device which includes a display panel and a driver chip.
  • the display panel includes a display area and a non-display area provided on at least one side of the display area; the display panel further includes:
  • a driving circuit layer is provided on one side of the substrate, and the driving circuit layer includes: a multi-level gate driving unit arranged in the non-display area, and a stage conductor connecting the gate driving units of different levels. signal line;
  • the driving circuit layer includes: a first semiconductor layer provided on one side of the substrate, the first semiconductor layer includes a plurality of first semiconductors provided in a non-display area, and the gate driving unit includes The first semiconductor;
  • the level transmission signal line is disposed between the first semiconductor layer and the substrate, and overlaps with at least part of the gate driving unit in the non-display area.
  • the driving circuit layer further includes: a first metal layer disposed on a side of the first semiconductor layer away from the substrate, and the first metal layer includes a first metal layer disposed in the non-display area. a gate, the gate driving unit includes the gate;
  • the cascade signal line overlaps at least part of the gate electrode in the non-display area.
  • the driving circuit layer further includes: a second metal layer disposed on a side of the first metal layer away from the substrate, and the second metal layer includes a second metal layer disposed on the non-display area.
  • Metal wiring, the gate driving unit includes the metal wiring;
  • the level transmission signal line overlaps with at least part of the metal wiring in the non-display area.
  • the driving circuit layer further includes: a source and drain layer disposed on a side of the second metal layer away from the first metal layer, and the gate driving unit includes a transistor, and the transistor It includes a first electrode and a second electrode disposed on the source and drain layer, and the first electrode is connected to the level transmission signal line through a first via hole.
  • the first electrode is connected to the first semiconductor through a second via hole, and the width of the first via hole is greater than the width of the second via hole.
  • the driving circuit layer further includes: a source and drain layer disposed on a side of the second metal layer away from the first metal layer, and the gate driving unit includes a transistor, and the transistor Including a first electrode and a second electrode provided on the source and drain layer, the display panel also includes a connecting metal, the first electrode is connected to the level transmission signal line through the connecting metal, and the connecting metal passes through The vias connect to the stage signal lines.
  • the display panel further includes a light-emitting layer disposed on a side of the driving circuit layer away from the substrate, and the light-emitting layer includes: a pixel light-emitting unit disposed in the display area,
  • the driving circuit layer further includes a pixel driving unit disposed in the display area and driving the pixel light-emitting unit, and a light-shielding layer disposed between the pixel driving unit and the substrate,
  • the light-shielding layer includes: a light-shielding portion provided in the display area and overlapped with the pixel driving unit, and the level transmission signal line provided in the non-display area.
  • the present application provides a display panel and a display device; the display panel includes a display area and a non-display area arranged on at least one side of the display area; the display panel includes a substrate and a driving circuit layer; the driving circuit layer is arranged on one side of the substrate , the driving circuit layer includes a multi-level gate driving unit arranged in the non-display area, and a level transmission signal line connecting the gate driving units of different levels, wherein the driving circuit layer includes: a first semiconductor arranged on one side of the substrate layer, the first semiconductor layer includes a plurality of first semiconductors disposed in the non-display area, the gate driving unit includes the first semiconductor, the level transmission signal line is disposed between the first semiconductor layer and the substrate, and between the non-display area and At least part of the gate driving units are arranged overlappingly.
  • the level transmission signal line between the first semiconductor layer and the substrate, the parasitic capacitance between the level transmission signal line and the metal trace of the gate driving unit located on the first semiconductor layer is avoided, so that the level transmission signal line can be prevented from being generated.
  • the signal lines can be overlapped with at least part of the gate drive units in the non-display area. This eliminates the need to set up corresponding wiring areas for the level transmission signal lines, thus reducing the space in the frame occupied by the level transmission signal lines and shortening the display panel. frame.
  • FIG. 1 is a first schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a circuit diagram of a display panel provided by an embodiment of the present application.
  • Figure 3 is a perspective view of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a comparison diagram of the installation areas of various components of the current display device provided by the embodiment of the present application and the display panel of the present application.
  • embodiments of the present application provide a display panel and a display device to alleviate the above technical problem.
  • an embodiment of the present application provides a display panel.
  • the display panel 1 includes: a display area 181 and a non-display area 182 provided on at least one side of the display area 181; the display panel 1 also includes:
  • a driving circuit layer is provided on one side of the substrate 11 .
  • the driving circuit layer includes: a multi-level gate driving unit 22 provided in the non-display area 182 (a first-level gate driving unit is shown in FIG. 3 ). , and the stage transmission signal lines 122 connecting the gate driving units 22 of different stages;
  • the driving circuit layer includes: a first semiconductor layer 141 provided on one side of the substrate 11, the first semiconductor layer 141 including a plurality of first semiconductors 141a provided in a non-display area, the gate electrode
  • the driving unit 22 includes the first semiconductor 141a;
  • the cascade signal line 122 is disposed between the first semiconductor layer 141 and the substrate 11 , and overlaps with at least part of the gate driving unit 22 in the non-display area 182 .
  • Embodiments of the present application provide a display panel that disposes a cascade signal line between a first semiconductor layer and a substrate to avoid cascading signal lines and gate driving units from being placed on the metal layer above the first semiconductor layer. Parasitic capacitance is generated between the traces, so that the level transmission signal line can be overlapped with at least part of the gate drive unit in the non-display area. This eliminates the need to set up a corresponding wiring area for the level transmission signal line, thus reducing the number of level transmission signal lines. The space occupied by the frame shortens the frame of the display panel.
  • Figure 1 is a cross-sectional view of the display panel. Therefore, Figure 1 does not show all the components of a single sub-pixel. Only some transistors, wiring and capacitors are shown. Therefore, it can be understood that Figure 1
  • the pixel driving unit in Figure 1 not only includes two transistors, but also includes other components; similarly, the gate driving unit shown in Figure 1 includes not only a single transistor, but also other components. Specifically, the pixel driving unit includes components.
  • the device may be a plurality of components as shown in the circuit in Figure 2.
  • the pixel light-emitting unit is labeled with LED, but this application does not limit the pixel light-emitting unit to a light-emitting diode.
  • the pixel light-emitting unit may be an organic light-emitting diode.
  • the first semiconductor layer 141 also includes a second semiconductor, and the second semiconductor is provided in the pixel driving unit 21 and is not labeled in FIG. 1 .
  • the driving circuit layer further includes: a first metal layer 143 disposed on the side of the first semiconductor layer 141 away from the substrate 11 .
  • the layer 143 includes a gate electrode 143a disposed in the non-display area 182, and the gate driving unit 22 includes the gate electrode 143a;
  • the cascade signal line overlaps at least part of the gate electrode in the non-display area.
  • the level transmission signal line can reuse the area where the gate is located in the non-display area, thereby avoiding the need to set up an additional separate wiring area for the level transmission signal line.
  • the corresponding frame area can be shortened to achieve a narrower frame; at the same time, the distance between the cascade signal line and the gate is relatively large, and the thickness of the insulating layer between the cascade signal line and the gate is large, which avoids the need for cascading signal lines.
  • a parasitic capacitance is formed between the gate and the gate.
  • the driving circuit layer further includes: a second metal layer 145 disposed on the side of the first metal layer 143 away from the substrate 11 .
  • the layer 145 includes a metal trace 145a disposed in the non-display area 182, and the gate driving unit 22 includes the metal trace 145a;
  • the cascade signal line 122 overlaps at least part of the metal wiring 145a in the non-display area 182.
  • the metal wiring 145a may include the first plate of the capacitor in the gate driving unit and the wiring on the same layer.
  • the first metal layer 143 is provided with the second plate of the capacitor at a position corresponding to the first plate.
  • the first plate and the second plate constitute a capacitor in the gate driving unit.
  • the level transmission signal line can reuse the area where the metal wiring is located in the non-display area, thereby avoiding additional separate Setting the wiring area for the cascade signal lines can shorten the corresponding frame area and achieve a narrower frame.
  • the distance between the cascade signal lines and the metal traces is relatively large, and the insulation layer between the cascade signal lines and the metal traces is The larger thickness avoids the formation of parasitic capacitance between the level transmission signal lines and metal traces.
  • the driving circuit layer further includes: a source and drain layer 151 disposed on a side of the second metal layer 145 away from the first metal layer 143 .
  • the gate driving unit 22 includes a transistor.
  • the transistor includes a first electrode 151a and a second electrode 151b provided on the source and drain layer 151.
  • the first electrode 151a is connected to the stage transmission through a first via hole.
  • Signal line 122. This application connects the level transmission signal line to the first electrode of the transistor, so that the signal of the level transmission signal line can be transmitted.
  • the level transmission signal line only occupies a space as wide as the width of the via hole connecting the wiring area, and
  • the cascade signal line can be arranged in the gate drive circuit area to reduce the space occupied by the cascade signal line and reduce the frame of the display panel.
  • the first electrode is a source electrode and the second electrode is a drain electrode; or the first electrode is a drain electrode and the second electrode is a source electrode.
  • the first electrode 151a is connected to the first semiconductor 141a through a second via hole, and the width of the first via hole is greater than the width of the second via hole. width.
  • the light-shielding layer is disposed under the first semiconductor layer, causing the depth of the first via hole to be greater than the depth of the second via hole. Therefore, when the first electrode passes through the via hole and is connected to the graded transmission signal line of the light-shielding layer, The aperture of the first via hole can be made larger than the aperture of the second via hole to prevent the first electrode from breaking when passing through the first via hole and causing poor signal transmission.
  • the display panel further includes a buffer layer 13, a first insulating layer 142, a second insulating layer 144, a third insulating layer 146, a fourth insulating layer 148, a fifth insulating layer 150 and a third metal Layer 149
  • the buffer layer 13 is provided between the light shielding layer 12 and the first semiconductor layer 141
  • the first insulating layer 142 is provided between the first semiconductor layer 141 and the first metal layer 143
  • the second insulating layer 144 is disposed between the first metal layer 143 and the second metal layer 145
  • the third insulating layer 146 is disposed between the second metal layer 145 and the second semiconductor layer 145 .
  • the fourth insulating layer 148 is disposed between the second semiconductor layer 147 and the third metal layer 149
  • the fifth insulating layer 150 is disposed between the third metal layer 149 and the source between drain layers 151;
  • the first via hole includes a part located in the buffer layer, a part located in the first insulating layer, a part located in the second insulating layer, a part located in the third insulating layer, a part located in the Parts of the fourth insulating layer and parts of the fifth insulating layer, and the first via holes are respectively located in the buffer layer, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the third insulating layer.
  • the projections of parts of the five insulating layers on the substrate overlap each other.
  • the driving circuit layer further includes: a source and drain layer disposed on a side of the second metal layer away from the first metal layer, the gate driving unit includes a transistor, and the The transistor includes a first electrode and a second electrode provided on the source and drain layers.
  • the display panel is formed with a connecting metal.
  • the first electrode is connected to the level transmission signal line through the connecting metal.
  • the connecting metal passes through Vias connect to the stage signal lines.
  • the above embodiments respectively describe in detail the setting area of the stage transmission signal lines and the connection method of the stage transmission signal lines.
  • the setting area of the stage transmission signal lines and the connection method of the stage transmission signal lines can be combined.
  • the first gate driving unit is connected to the stage transmission signal line through a via hole at the junction of the first wiring area and the second wiring area, and the second gate driving unit A via hole is passed at the junction of the first wiring area and the second wiring area to connect to the level transmission signal line.
  • the level transmission signal line is provided on the light shielding layer, and the gate electrode
  • the output end of the driving unit is connected to the level transmission signal line through a via hole, so that the level transmission signal line is arranged on the light-shielding layer to avoid increasing the thickness of the display panel, and the level transmission signal line is connected to the first gate driving unit and the third gate driving unit.
  • the two-gate driving unit is connected through a via hole at the junction of the first wiring area and the second wiring area to avoid occupying the frame of the display panel, thereby reducing the frame of the display panel without increasing the thickness of the display panel. Therefore, the setting areas of other level transmission signal lines and the connection methods of the level transmission signal lines can also be combined to achieve better results, which will not be described again here.
  • the display panel further includes a luminescent layer disposed on a side of the driving circuit layer away from the substrate.
  • the luminescent layer includes: a luminescent layer disposed on the display area.
  • the driving circuit layer also includes a pixel driving unit disposed in the display area and driving the pixel light-emitting unit, and a light-shielding layer 12 disposed between the pixel driving unit and the substrate,
  • the light-shielding layer 12 includes: a light-shielding portion 121 provided in the display area and overlapped with the pixel driving unit, and the cascade signal line 122 provided in the non-display area.
  • the level transmission signal line 122 and the light-shielding part 121 of the display area can be prepared together in the same process, reusing the preparation process of the light-shielding part 121 , and reducing the preparation time of the level transmission signal line 122 The process is difficult, saves the process flow, and reduces the preparation cost.
  • the cascade signal line can be extended to the gate drive circuit area. The cascade signal line will only occupy the space connected by the via hole. The extended part of the cascade signal line can be set in the gate drive circuit area.
  • the space occupied by the cascade signal line is reduced, and due to the large thickness of the insulating layer between the light-shielding layer and the first metal layer and the second metal layer, the distance between the light-shielding layer and the first metal layer and the second metal layer is reduced.
  • the parasitic capacitance is small or even nonexistent, which avoids increasing the parasitic capacitance of the display panel. Since the display panel has a light-shielding layer, there is no need to add a metal film layer, which reduces the thickness of the display panel. Compared with using other film layers to form cascade signal lines, The thickness and parasitic capacitance of the display panel are reduced.
  • the first semiconductor layer further includes a plurality of second semiconductors disposed in the display area, and the pixel driving unit includes the second semiconductors;
  • the first semiconductor includes a first channel region, and the level transmission signal line is not overlapped with the first channel region;
  • the second semiconductor includes a second channel region, and the light shielding portion overlaps with the second channel region.
  • the light-shielding portion 121 overlaps with the second channel region of the second semiconductor, which can shield the adverse effects of the charges below the second channel region on it and enhance the working performance of the corresponding transistor in the pixel driving unit;
  • the level transmission signal line 122 is not overlapped with the first channel region of the first semiconductor, which can prevent the level transmission signal line from adversely affecting the transistor in the gate driving unit and preventing its normal operation.
  • the light-shielding part 121 can be grounded or connected to a constant potential to shield charges.
  • the cascade signal line 122 will conduct changing potentials and generate an electric field that adversely affects the transistor. It needs to be avoided.
  • a first channel region of a semiconductor is provided.
  • the driving circuit layer further includes: a second semiconductor layer 147 disposed on the side of the first semiconductor layer 141 away from the substrate,
  • the second semiconductor layer 147 includes a plurality of third semiconductors disposed in the display area.
  • the pixel driving unit also includes the third semiconductor.
  • the third semiconductor includes a metal oxide material (such as IGZO, full name "indium gallium”). zinc oxide", indium gallium zinc oxide, etc.);
  • the light shielding portion and the third semiconductor are not overlapped.
  • the gate driving unit can be prepared using transistors of different material types.
  • T1, T2, T5, T6, and T7 in Figure 2 can use low-temperature polysilicon to prepare their semiconductors
  • T3 and T4 can use Metal oxides are used to prepare their semiconductors.
  • the semiconductor layers of low-temperature polysilicon transistors and metal oxide transistors are generally arranged in different layers, that is, the stacking relationship between the first semiconductor layer and the second semiconductor layer.
  • the light-shielding portion is mainly provided for low-temperature polysilicon transistors, such as T1, and the metal oxide transistor can be arranged in a double-gate structure (such as 145 and 149 in Figure 1) without using a light shielding part to additionally shield it.
  • the display panel further includes a graded conduction metal layer.
  • the graded conduction metal layer is disposed on a side of the light-shielding layer away from the first semiconductor layer.
  • the graded conduction metal layer includes a graded conduction metal layer.
  • the signal line is provided with a graded transmission metal layer on the side of the light-shielding layer away from the first semiconductor layer, so that the graded transmission metal layer forms a graded transmission signal layer, so that the graded transmission signal line is set in the gate drive circuit area, reducing the cost of the display panel. frame.
  • the pixel driving unit 21 includes:
  • the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the gate of the first initialization transistor T4 is connected to the first scan signal line N Scan (n-5) of the first gate driving unit, so The first initialization transistor T4 is used to input the first initialization signal to the first node under the control of the first scan signal;
  • the switching transistor T2 is used to input a data signal to the second node under the control of the second scan signal;
  • the driving transistor T1 is used to drive the pixel light-emitting unit LED to emit light under the control of the first node and the second node potential;
  • the compensation transistor T3 is connected to the driving transistor T1 through the first node and the third node, and the gate of the compensation transistor T3 is connected to the second scanning signal line N Scan(n) of the second gate driving unit, The compensation transistor T3 is used to compensate the threshold voltage of the driving transistor T1 under the control of the third scan signal;
  • the gate driving unit 22 includes: the first gate driving unit and the second gate driving unit of different stages, and one end of the stage transmission signal line 122 is connected to the first gate driving unit. , the other end of the stage transmission signal line 122 is connected to the second gate driving unit along the gate driving circuit area 183 .
  • the first initialization transistor and the compensation transistor By connecting the first initialization transistor and the compensation transistor to the first scanning signal line and the second scanning signal line of the first gate driving unit and the second gate driving unit respectively, the first initialization transistor and the compensation transistor can be turned on at different stages. , thereby resetting and compensating the threshold voltage of the driving transistor respectively, to avoid signal crosstalk caused by turning on the first initialization transistor and the compensation transistor at the same time.
  • the driving time of the first initialization transistor and the compensation transistor is separated, so that the added 5-level gate driving unit can turn on the first initialization transistor in the first 10 rows of pixel driving units, such as
  • the 6-level gate driving unit drives the compensation transistors in the pixel driving units of the 1st and 2nd rows, and at the same time drives the first initialization transistors in the pixel driving units of the 11th and 12th rows, so that the first initialization transistor and the first initialization transistor can be driven separately. Compensation transistor.
  • the first gate driving unit and the second gate driving unit need to use a level transmission signal line for signal level transmission.
  • the third metal layer cannot be connected to the first level transmission signal line.
  • the metal layer and the second metal layer overlap, so the level transmission signal line will occupy a larger space and increase the frame; in this application, the level transmission signal line connects the first gate drive unit and the second gate drive unit from the gate drive circuit area.
  • the gate drive unit avoids the space occupied by cascading signal lines and reduces the frame of the display panel.
  • the first initialization transistor and the compensation transistor are oxide semiconductor transistors.
  • the gate driving unit further includes a third gate driving unit
  • the gate driving circuit area includes a first wiring area 183a and a second wiring area.
  • Region 183b, the first gate driving unit and the second gate driving unit are disposed in the first wiring region 183a
  • the third gate driving unit is disposed in the second wiring region, at least Part of the level transmission signal lines are provided in the second wiring area 183b.
  • at least part of the level transmission signal lines are arranged in the second wiring area to avoid signal crosstalk when the level transmission signal lines connect the first gate driving unit and the second gate driving unit.
  • the level transmission signal lines are arranged In the second routing area, it is possible to avoid space occupied by cascading signal lines and reduce the width of the frame of the display panel.
  • the gate driving unit uses the scanning signal line P Scan(n) to control the P-type transistor and the scanning signal line N Scan(n) to control the N-type transistor to control the transistor. , therefore, it is necessary to set up the first routing area and the second routing area to respectively set up the gate driving unit corresponding to the scanning signal line N Scan (n) and the gate driving unit corresponding to the scanning signal line P Scan (n).
  • Figure 3 shows the gate driving unit corresponding to N Scan (n) in a certain level of gate driving unit and the gate driving unit corresponding to the scanning signal line P Scan (n) and the connection to the display
  • the embodiment of the present application arranges the level transmission signal line in the second wiring area 183b, that is, the level transmission signal line setting area 185 in Figure 3 is located in the second wiring area 183b, reducing the level transmission area.
  • the frame occupied by the signal line reduces the frame of the display panel.
  • the first gate driving unit is connected to the stage transmission signal line through a via at the junction of the first wiring area and the second wiring area
  • the third The two-gate driving unit is connected to the stage transmission signal line through a via hole at the junction of the first wiring area and the second wiring area.
  • the gate drive unit corresponding to N Scan (n) will be connected to the stage transmission signal line at the first connection 311, so that the upper-level gate drive unit can transmit the signal to the lower-level gate through the stage transmission signal line.
  • the gate driving unit corresponding to N Scan (n) will be connected to the transistor in the pixel driving unit in the display area through the second connection 312 to drive the transistor. Since the gate driving unit is connected to the stage The signal line is connected at the junction of the first wiring area and the second wiring area to avoid signal interference between the gate driving unit corresponding to N Scan (n) and the gate driving unit corresponding to P Scan (n). Or defects may occur due to metal overlap and short circuit.
  • the display panel 1 further includes a connection wiring area 184 disposed between the gate driving circuit area 183 and the display area 181 .
  • the second wiring area 183b is disposed between the first wiring area 183a and the connection wiring area 184, and the stage transmission signal line 122 extends from the second wiring area 183b to the connection wiring area District 184.
  • the level transmission signal line is extended from the second wiring area to the connection wiring area, so that the level transmission signal line can be connected to the signal line to realize signal transmission.
  • the level transmission signal line only needs to occupy the connection wiring area at the connection point. In some areas, the space occupied by the level transmission signal line is reduced, and the frame of the display panel is reduced.
  • the pixel driving unit further includes a second initialization transistor T7, the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and is used in the fourth scan. Under the control of the signal, input a second initialization signal to the LED anode of the light-emitting device;
  • the first light-emitting control transistor T5 is connected to the driving transistor T1 through the second node, and is used to conduct the current of the power high-potential signal line ELVDD to the driving transistor T1 under the control of the light-emitting control signal;
  • the second light-emitting control transistor T6 is connected to the driving transistor T1 through a third node, and is used to conduct the current flowing from the driving transistor T1 to the anode of the light-emitting device LED under the control of the light-emitting control signal.
  • the pixel driving unit further includes a storage capacitor Cst and a boost capacitor Cboost.
  • One end of the storage capacitor Cst is connected to the power high potential signal line VDD.
  • the storage capacitor The other end of Cst is connected to the first node, one end of the boost capacitor is connected to the first initialization transistor T4, and the other end of the boost capacitor is connected to the gate of the switching transistor T2.
  • the data line Data transmits data signals
  • the first initialization signal line VI-G transmits the first initialization signal
  • the second initialization signal line VI-ANO transmits the second Initialization signal
  • the first scan signal line N Scan (n-5) transmits the first scan signal
  • the second scan signal line N Scan (n) transmits the second scan signal
  • the third scan signal line P Scan (n) transmits the third scan signal.
  • Scan signal, the fourth scan signal line P Scan (n-1) transmits the fourth scan signal
  • the luminescence control signal line EM transmits the luminescence control signal
  • the power low potential signal line ELVSS transmits low potential.
  • P Scan (n) represents the current level scan line
  • P Scan (n-1) represents the previous level scan line
  • the above scan line is used to control the P-type transistor.
  • the working principle of the circuit is as follows: in the first stage, the first initialization transistor T4 and the second initialization transistor T7 are turned on, and the gate of the driving transistor T1 is reset through the initialization signal output by the first initialization signal line VI-G.
  • the initialization signal output by the signal line VI-ANO resets the pixel light-emitting unit LED; in the second stage, the switching transistor T2 and the compensation transistor T3 are turned on, and the data signal input by the data line Data is written into the gate of the driving transistor T1; in the third stage , the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on to drive the pixel light-emitting unit LED to emit light.
  • FIG. 4 (a) in FIG. 4 is a schematic diagram of the installation area of each component of the current display device, and (b) in FIG. 4 is a schematic diagram of the installation area of each part of the display panel of the present application.
  • a gate drive circuit setting area 212 and a stage signal line setting area 213 need to be respectively provided, resulting in a larger frame of the display device.
  • the stage transmission signal line is set in the gate drive circuit area, as shown in (b) of Figure 4. It can be seen that the stage transmission signal line setting area 185 and the gate drive circuit area 183 overlap.
  • the signal line setting area 185 is located in the gate driving circuit area 183, thereby reducing the frame of the display panel.
  • a display panel using a 7T1C (seven transistors and one capacitor) circuit can also adopt the design of the present application.
  • the substrate 11 in order to improve the flexibility of the display panel and its ability to block water and oxygen, as shown in FIG. 1 , the substrate 11 includes a first flexible layer 111 , a barrier layer 112 and a second flexible layer 113 .
  • the display panel further includes a planarization layer 152 .
  • the material of the first semiconductor layer is low-temperature polysilicon
  • the material of the active layer is an oxide, specifically indium gallium zinc oxide.
  • the embodiment of the present application takes LTPO technology as an example to illustrate the structure of the display panel.
  • the embodiment of the present application is not limited thereto.
  • the display panel may adopt LTPS (Low Temperature Poly-silicon, low-temperature polysilicon) technology.
  • embodiments of the present application provide a display device, which includes the display panel and driver chip described in any of the above embodiments.
  • Embodiments of the present application provide a display panel and a display device; the display panel includes a display area and a non-display area disposed on at least one side of the display area; the display panel includes a substrate and a drive circuit layer, and the drive circuit layer is disposed on the substrate On one side, the driving circuit layer includes a multi-level gate driving unit arranged in the non-display area and a level transmission signal line connecting the gate driving units of different levels, wherein the driving circuit layer includes: a third gate driving unit arranged on one side of the substrate.
  • a semiconductor layer the first semiconductor layer includes a plurality of first semiconductors arranged in the non-display area
  • the gate driving unit includes the first semiconductor
  • the level transmission signal line is arranged between the first semiconductor layer and the substrate, and in the non-display area
  • the region overlaps at least part of the gate driving unit.
  • the signal lines can be overlapped with at least part of the gate drive units in the non-display area. This eliminates the need to set up corresponding wiring areas for the level transmission signal lines, thus reducing the space in the frame occupied by the level transmission signal lines and shortening the display panel. frame.

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Abstract

本申请提供一种显示面板和显示装置；该显示面板通过将级传信号线设置在第一半导体层和衬底之间，避免级传信号线与栅极驱动单元处于第一半导体层之上的金属走线之间产生寄生电容，使级传信号线可以在非显示区与至少部分栅极驱动单元重叠设置，减少了级传信号线占用的边框的空间，缩短了显示面板的边框。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其是涉及一种显示面板和显示装置。
 背景技术
现有显示器件为了实现窄边框，会采用栅极驱动电路对像素驱动电路进行控制。在栅极驱动电路中，为了实现信号的传递，会采用级传信号线连接不同级的栅极驱动单元，使得信号可以进行传递。但由于级传信号线与其他金属重叠会导致寄生电容较大，使得级传信号线无法设置在栅极驱动单元对应的区域，需要为级传信号线单独设置区域，导致显示面板的边框较大。
所以，现有显示器件存在需要为级传信号线单独设置区域导致边框较大的技术问题。
 技术问题
本申请实施例提供一种显示面板和显示装置，用以缓解现有显示器件存在需要为级传信号线单独设置区域导致边框较大的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，该显示面板包括：显示区和设置在所述显示区至少一侧的非显示区；所述显示面板还包括：
衬底；
驱动电路层，设置在所述衬底的一侧，所述驱动电路层包括：设置在所述非显示区的多级栅极驱动单元、以及连接不同级的所述栅极驱动单元的级传信号线；
其中，所述驱动电路层包括：设置在所述衬底一侧的第一半导体层，所述第一半导体层包括设置在非显示区的多个第一半导体，所述栅极驱动单元包括所述第一半导体；
所述级传信号线设置在所述第一半导体层和所述衬底之间，且在所述非显示区与至少部分所述栅极驱动单元重叠设置。
在一些实施例中，所述驱动电路层还包括：设置在所述第一半导体层远离所述衬底一侧的第一金属层，所述第一金属层包括设置在所述非显示区的栅极，所述栅极驱动单元包括所述栅极；
所述级传信号线在所述非显示区与至少部分所述栅极重叠设置。
在一些实施例中，所述驱动电路层还包括：设置在所述第一金属层远离所述衬底一侧的第二金属层，所述第二金属层包括设置在所述非显示区的金属走线，所述栅极驱动单元包括所述金属走线；
所述级传信号线在所述非显示区与至少部分所述金属走线重叠设置。
在一些实施例中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述第一电极穿过第一过孔连接至所述级传信号线。
在一些实施例中，所述第一电极穿过第二过孔连接至所述第一半导体，所述第一过孔的宽度大于所述第二过孔的宽度。
在一些实施例中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述显示面板还包括连接金属，所述第一电极通过连接金属与所述级传信号线连接，所述连接金属穿过过孔连接至级传信号线。
在一些实施例中，所述显示面板还包括设置在所述驱动电路层远离所述衬底一侧的发光层，所述发光层包括：设置于所述显示区的像素发光单元，
所述驱动电路层还包括设置在所述显示区且驱动所述像素发光单元的像素驱动单元，以及设置在所述像素驱动单元和所述衬底之间的遮光层，
其中，所述遮光层包括：设置在所述显示区且与所述像素驱动单元重叠设置的遮光部，和设置在所述非显示区的所述级传信号线。
在一些实施例中，所述第一半导体层还包括设置在显示区的多个第二半导体，所述像素驱动单元包括所述第二半导体；
所述第一半导体包括第一沟道区，所述级传信号线不与所述第一沟道区重叠设置；
所述第二半导体包括第二沟道区，所述遮光部与所述第二沟道区重叠设置。
在一些实施例中，所述驱动电路层还包括：设置在所述第一半导体层远离所述衬底一侧的第二半导体层，
所述第二半导体层包括设置在显示区的多个第三半导体，所述像素驱动单元还包括所述第三半导体，所述第三半导体包括金属氧化物材料；
所述遮光部与所述第三半导体不重叠设置。
在一些实施例中，所述像素驱动单元包括：
第一初始化晶体管，与第一初始化信号线连接，所述第一初始化晶体管的栅极连接至第一栅极驱动单元的第一扫描信号线，所述第一初始化晶体管用于在第一扫描信号的控制下，向第一节点输入第一初始化信号；
开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
驱动晶体管，用于在第一节点和第二节点电位的控制下，驱动所述像素发光单元发光；
补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，所述补偿晶体管的栅极连接至第二栅极驱动单元的第二扫描信号线，所述补偿晶体管用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
其中，所述栅极驱动单元包括：不同级的所述第一栅极驱动单元和所述第二栅极驱动单元，所述级传信号线一端连接至所述第一栅极驱动单元，所述级传信号线另一端沿所述栅极驱动电路区连接至第二栅极驱动单元。
在一些实施例中，所述栅极驱动单元还包括第三栅极驱动单元，所述栅极驱动电路区包括第一走线区和第二走线区，所述第一栅极驱动单元和所述第二栅极驱动单元设置于所述第一走线区，所述第三栅极驱动单元设置于所述第二走线区，至少部分所述级传信号线设置于所述第二走线区。
在一些实施例中，所述第一栅极驱动单元在所述第一走线区与所述第二走线区的交界处穿过过孔连接至所述级传信号线，所述第二栅极驱动单元在所述第一走线区与所述第二走线区的交界处穿过过孔连接至所述级传信号线。
在一些实施例中，所述显示面板还包括设置于所述栅极驱动电路区和所述显示区之间的连接走线区，所述第二走线区设置于所述第一走线区和所述连接走线区之间，所述级传信号线从所述第二走线区延伸至所述连接走线区。
同时，本申请实施例提供一种显示装置，该显示装置包括显示面板和驱动芯片，显示面板包括显示区和设置在所述显示区至少一侧的非显示区；所述显示面板还包括：
衬底；
驱动电路层，设置在所述衬底的一侧，所述驱动电路层包括：设置在所述非显示区的多级栅极驱动单元、以及连接不同级的所述栅极驱动单元的级传信号线；
其中，所述驱动电路层包括：设置在所述衬底一侧的第一半导体层，所述第一半导体层包括设置在非显示区的多个第一半导体，所述栅极驱动单元包括所述第一半导体；
所述级传信号线设置在所述第一半导体层和所述衬底之间，且在所述非显示区与至少部分所述栅极驱动单元重叠设置。
在一些实施例中，所述驱动电路层还包括：设置在所述第一半导体层远离所述衬底一侧的第一金属层，所述第一金属层包括设置在所述非显示区的栅极，所述栅极驱动单元包括所述栅极；
所述级传信号线在所述非显示区与至少部分所述栅极重叠设置。
在一些实施例中，所述驱动电路层还包括：设置在所述第一金属层远离所述衬底一侧的第二金属层，所述第二金属层包括设置在所述非显示区的金属走线，所述栅极驱动单元包括所述金属走线；
所述级传信号线在所述非显示区与至少部分所述金属走线重叠设置。
在一些实施例中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述第一电极穿过第一过孔连接至所述级传信号线。
在一些实施例中，所述第一电极穿过第二过孔连接至所述第一半导体，所述第一过孔的宽度大于所述第二过孔的宽度。
在一些实施例中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述显示面板还包括连接金属，所述第一电极通过连接金属与所述级传信号线连接，所述连接金属穿过过孔连接至级传信号线。
在一些实施例中，所述显示面板还包括设置在所述驱动电路层远离所述衬底一侧的发光层，所述发光层包括：设置于所述显示区的像素发光单元，
所述驱动电路层还包括设置在所述显示区且驱动所述像素发光单元的像素驱动单元，以及设置在所述像素驱动单元和所述衬底之间的遮光层，
其中，所述遮光层包括：设置在所述显示区且与所述像素驱动单元重叠设置的遮光部，和设置在所述非显示区的所述级传信号线。
 有益效果
本申请提供一种显示面板和显示装置；该显示面板包括显示区和设置于显示区至少一侧的非显示区，显示面板包括衬底和驱动电路层，驱动电路层设置在衬底的一侧，驱动电路层包括设置在非显示区的多级栅极驱动单元、以及连接不同级的栅极驱动单元的级传信号线，其中，驱动电路层包括：设置在衬底一侧的第一半导体层，第一半导体层包括设置在非显示区的多个第一半导体，栅极驱动单元包括第一半导体，级传信号线设置在第一半导体层和衬底之间，且在非显示区与至少部分栅极驱动单元重叠设置。本申请通过将级传信号线设置在第一半导体层和衬底之间，避免级传信号线与栅极驱动单元处于第一半导体层之上的金属走线之间产生寄生电容，使级传信号线可以在非显示区与至少部分栅极驱动单元重叠设置，这样可以无需额外为级传信号线设置对应的布线区域，进而减少了级传信号线占用的边框的空间，缩短了显示面板的边框。
 附图说明
图1为本申请实施例提供的显示面板的第一种示意图。
图2为本申请实施例提供的显示面板的电路图。
图3为本申请实施例提供的显示面板的透视图。
图4为本申请实施例提供的当前显示器件和本申请的显示面板的各部件的设置区域的对比图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例针对现有显示器件存在将发光单元设置在栅极驱动电路上会导致显示器件的良率较低的技术问题，提供一种显示面板和显示装置，用以缓解上述技术问题。
如图1至图3所示，本申请实施例提供一种显示面板，该显示面板1包括：显示区181和设置在所述显示区181至少一侧的非显示区182；所述显示面板1还包括：
衬底11；
驱动电路层，设置在所述衬底11一侧，所述驱动电路层包括：设置在所述非显示区182的多级栅极驱动单元22（图3中示出一级栅极驱动单元）、以及连接不同级的所述栅极驱动单元22的级传信号线122；
其中，所述驱动电路层包括：设置在所述衬底11一侧的第一半导体层141，所述第一半导体层141包括设置在非显示区的多个第一半导体141a，所述栅极驱动单元22包括所述第一半导体141a；
所述级传信号线122设置在所述第一半导体层141和所述衬底11之间，且在所述非显示区182与至少部分所述栅极驱动单元22重叠设置。
本申请实施例提供一种显示面板，该显示面板通过将级传信号线设置在第一半导体层和衬底之间，避免级传信号线与栅极驱动单元处于第一半导体层之上的金属走线之间产生寄生电容，使级传信号线可以在非显示区与至少部分栅极驱动单元重叠设置，这样可以无需额外为级传信号线设置对应的布线区域，进而减少了级传信号线占用的边框的空间，缩短了显示面板的边框。
需要说明的是，图1为显示面板的截面图，因此，图1中未示出单个子像素的所有元器件，仅示出了部分晶体管、走线以及电容，因此，可以理解的是，图1中的像素驱动单元不仅包括两个晶体管，还包括其他元器件；同理，图1示出的栅极驱动单元不仅包括单个晶体管，还包括其他元器件，具体的，像素驱动单元包括的元器件可以为图2中的电路示出的多个元器件。
需要说明的是，以LED标示像素发光单元，但本申请并不限定像素发光单元为发光二极管，像素发光单元可以为有机发光二极管。
具体的，如图1所示，第一半导体层141还包括第二半导体，第二半导体设置于像素驱动单元21中，在图1中未标示。
在一种实施例中，如图1所示，所述驱动电路层还包括：设置在所述第一半导体层141远离所述衬底11一侧的第一金属层143，所述第一金属层143包括设置在所述非显示区182的栅极143a，所述栅极驱动单元22包括所述栅极143a；
所述级传信号线在所述非显示区与至少部分所述栅极重叠设置。通过使级传信号线在非显示区与至少部分栅极重叠设置，使得级传信号线在非显示区可以复用栅极所处区域，进而可以避免额外单独为级传信号线设置布线区域，进而可以缩短对应的边框区域，实现更窄边框；同时，级传信号线与栅极的间距较大，级传信号线与栅极之间的绝缘层的厚度较大，避免了级传信号线与栅极之间形成寄生电容。
在一种实施例中，如图1所示，所述驱动电路层还包括：设置在所述第一金属层143远离所述衬底11一侧的第二金属层145，所述第二金属层145包括设置在所述非显示区182的金属走线145a，所述栅极驱动单元22包括所述金属走线145a；
所述级传信号线122在所述非显示区182与至少部分所述金属走线145a重叠设置。具体的，金属走线145a可以包括栅极驱动单元中电容的第一极板及与其同层的走线，同时第一金属层143在第一极板对应位置设置有电容的第二极板，第一极板和第二极板构成栅极驱动单元中的电容。
在本实施例中，通过使级传信号线在非显示区与至少部分金属走线重叠设置，使得级传信号线在非显示区可以复用金属走线所处区域，进而可以避免额外单独为级传信号线设置布线区域，进而可以缩短对应的边框区域，实现更窄边框；同时，级传信号线与金属走线的间距较大，级传信号线与金属走线之间的绝缘层的厚度较大，避免了级传信号线与金属走线之间形成寄生电容。
在一种实施例中，如图1所示，所述驱动电路层还包括：设置于所述第二金属层145远离所述第一金属层143的一侧的源漏极层151，所述栅极驱动单元22包括晶体管，所述晶体管包括设置于所述源漏极层151的第一电极151a和第二电极151b，所述第一电极151a穿过第一过孔连接至所述级传信号线122。本申请通过将级传信号线与晶体管的第一电极进行连接，使得可以通过将级传信号线的信号进行传输，级传信号线仅占用连接走线区的过孔的宽度大小的空间，而级传信号线可以设置在栅极驱动电路区，减小级传信号线占用的空间，减小显示面板的边框。
在一种实施例中，第一电极为源极、第二电极为漏极；或者第一电极为漏极，第二电极为源极。
在一种实施例中，如图1所示，所述第一电极151a穿过第二过孔连接至所述第一半导体141a，所述第一过孔的宽度大于所述第二过孔的宽度。通过使第一过孔的宽度大于第二过孔的宽度，使得第一电极穿过第一过孔连接级传信号线时，由于第一过孔的孔径较大，避免第一电极的部分在第一过孔内出现断裂，导致显示不良。
具体的，遮光层设置在第一半导体层下，导致第一过孔的深度大于第二过孔的深度，因此，在第一电极穿过过孔连接至遮光层的级传信号线上时，可以使得第一过孔的孔径大于第二过孔的孔径，避免第一电极在穿过第一过孔时出现断裂导致信号传输不良。
在一种实施例中，所述显示面板还包括缓冲层13、第一绝缘层142、第二绝缘层144、第三绝缘层146、第四绝缘层148、第五绝缘层150和第三金属层149，所述缓冲层13设置于所述遮光层12和所述第一半导体层141之间，所述第一绝缘层142设置于所述第一半导体层141和所述第一金属层143之间，所述第二绝缘层144设置于所述第一金属层143和所述第二金属层145之间，所述第三绝缘层146设置于所述第二金属层145和第二半导体层147之间，所述第四绝缘层148设置于第二半导体层147和所述第三金属层149之间，所述第五绝缘层150设置于所述第三金属层149和所述源漏极层151之间；
其中，所述第一过孔包括位于所述缓冲层的部分、位于所述第一绝缘层的部分、位于所述第二绝缘层的部分、位于所述第三绝缘层的部分、位于所述第四绝缘层的部分、位于所述第五绝缘层的部分，且所述第一过孔分别位于缓冲层、第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层的部分在衬底上的投影两两存在重合。
在一种实施例中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述显示面板形成有连接金属，所述第一电极通过连接金属与所述级传信号线连接，所述连接金属穿过过孔连接至级传信号线。通过在过孔内设置连接金属，使连接金属穿过过孔连接至级传信号线，则可以使第一电极通过连接金属连接至级传信号线，避免第一电极在过孔内出现断裂，提高第一电极与连接金属的连接效果。
需要说明的是，上述实施例分别对级传信号线的设置区域以及级传信号线的连接方式进行了详细描述，但对于级传信号线的设置区域和级传信号线的连接方式，可以结合以实现更好的技术效果。例如，所述第一栅极驱动单元在所述第一走线区与所述第二走线区的交界处穿过过孔连接至所述级传信号线，所述第二栅极驱动单元在所述第一走线区与所述第二走线区的交界处穿过过孔连接至所述级传信号线，所述级传信号线设置于所述遮光层，且所述栅极驱动单元的输出端穿过过孔连接至所述级传信号线，以使得级传信号线设置在遮光层，避免增加显示面板的厚度，将级传信号线与第一栅极驱动单元和第二栅极驱动单元在第一走线区和第二走线的交界处穿过过孔进行连接，避免占用显示面板的边框，从而减小显示面板的边框且不增加显示面板的厚度。因此，对于其他级传信号线的设置区域以及级传信号线的连接方式，也可以结合以达到更好的效果，在此不再赘述。
在一种实施例中，如图1所示，所述显示面板还包括设置在所述驱动电路层远离所述衬底一侧的发光层，所述发光层包括：设置于所述显示区的像素发光单元，
所述驱动电路层还包括设置在所述显示区且驱动所述像素发光单元的像素驱动单元，以及设置在所述像素驱动单元和所述衬底之间的遮光层12，
其中，所述遮光层12包括：设置在所述显示区且与所述像素驱动单元重叠设置的遮光部121，和设置在所述非显示区的所述级传信号线122。
通过将级传信号线设置在遮光层12，可以将级传信号线122与显示区的遮光部121同一工艺一起制备，复用了遮光部121的制备工艺，降低了级传信号线122的制备工艺难度，节省了工艺流程，降低了制备成本。同时，级传信号线可以延伸至栅极驱动电路区，级传信号线仅会占用过孔连接的部分的空间，而对于级传信号线的延伸部分，均可以设置在栅极驱动电路区，减小级传信号线占用的空间，且由于遮光层与第一金属层和第二金属层之间的绝缘层的厚度较大，使得遮光层与第一金属层和第二金属层之间的寄生电容较小甚至没有，避免增加显示面板的寄生电容，且由于显示面板存在遮光层，无需增加金属膜层，减小了显示面板的厚度，相较于采用其他膜层形成级传信号线，减小了显示面板的厚度和寄生电容。
在一种实施例中，所述第一半导体层还包括设置在显示区的多个第二半导体，所述像素驱动单元包括所述第二半导体；
所述第一半导体包括第一沟道区，所述级传信号线不与所述第一沟道区重叠设置；
所述第二半导体包括第二沟道区，所述遮光部与所述第二沟道区重叠设置。
在本实施例中，遮光部121与第二半导体的第二沟道区重叠设置，可以屏蔽第二沟道区下方的电荷对其产生的不良影响，增强像素驱动单元中相应晶体管的工作性能；同时，级传信号线122不与第一半导体的第一沟道区重叠设置，可以避免级传信号线对栅极驱动单元中的晶体管产生不良影响，避免妨碍其正常工作。在实际应用中遮光部121可以接地，也可以连接到恒定电位，起到屏蔽电荷的作用，而级传信号线122会导通变化的电位，会产生对晶体管不良影响的电场，需要避开第一半导体的第一沟道区设置。
在一种实施例中，如图1所示，所述驱动电路层还包括：设置在所述第一半导体层141远离所述衬底一侧的第二半导体层147，
所述第二半导体层147包括设置在显示区的多个第三半导体，所述像素驱动单元还包括所述第三半导体，所述第三半导体包括金属氧化物材料（例如IGZO，全称“indium gallium zinc oxide”，铟镓锌氧化物等）；
所述遮光部与所述第三半导体不重叠设置。
在本实施例中，栅极驱动单元可以采用不同材料类型的晶体管来制备，例如图2中的T1、T2、T5、T6、T7，它们可以采用低温多晶硅来制备其半导体，而T3、T4可以采用金属氧化物来制备其半导体。如图1所示，低温多晶硅晶体管和金属氧化物晶体管的半导体层一般是非同层设置，即第一半导体层和第二半导体层的层叠关系，而遮光部主要是针对低温多晶硅晶体管设置的，例如T1，而金属氧化物晶体管可以设置成双栅结构（例如图1中的145和149），并不用遮光部来额外为其进行屏蔽。
在一种实施例中，所述显示面板还包括级传金属层，所述级传金属层设置于所述遮光层远离所述第一半导体层的一侧，所述级传金属层包括级传信号线，通过在遮光层远离第一半导体层的一侧设置级传金属层，使级传金属层形成级传信号层，使得级传信号线设置在栅极驱动电路区，减小显示面板的边框。
在一种实施例中，如图1、图2所示，所述像素驱动单元21包括：
第一初始化晶体管T4，与第一初始化信号线VI-G连接，所述第一初始化晶体管T4的栅极连接至第一栅极驱动单元的第一扫描信号线N Scan（n-5），所述第一初始化晶体管T4用于在第一扫描信号的控制下，向第一节点输入第一初始化信号；
开关晶体管T2，用于在第二扫描信号的控制下，向第二节点输入数据信号；
驱动晶体管T1，用于在第一节点和第二节点电位的控制下，驱动所述像素发光单元LED发光；
补偿晶体管T3，通过所述第一节点和第三节点与所述驱动晶体管T1相连，所述补偿晶体管T3的栅极连接至第二栅极驱动单元的第二扫描信号线N Scan（n），所述补偿晶体管T3用于在第三扫描信号的控制下，补偿所述驱动晶体管T1的阈值电压；
其中，所述栅极驱动单元22包括：不同级的所述第一栅极驱动单元和所述第二栅极驱动单元，所述级传信号线122一端连接至所述第一栅极驱动单元，所述级传信号线122另一端沿所述栅极驱动电路区183连接至第二栅极驱动单元。
通过将第一初始化晶体管与补偿晶体管分别连接第一栅极驱动单元和第二栅极驱动单元的第一扫描信号线和第二扫描信号线，使得第一初始化晶体管和补偿晶体管能够在不同阶段开启，从而分别对驱动晶体管的阈值电压进行复位和补偿，避免同时开启第一初始化晶体管和补偿晶体管导致信号串扰。而通过增加5级栅极驱动单元将第一初始化晶体管和补偿晶体管的驱动时间分开，使增加的5级栅极驱动单元能够对前10行像素驱动单元中的第一初始化晶体管进行开启，例如第6级栅极驱动单元驱动第1和第2行的像素驱动单元中的补偿晶体管，同时会驱动第11和第12行像素驱动单元中的第一初始化晶体管，从而可以分开驱动第一初始化晶体管和补偿晶体管。
因此，第一栅极驱动单元和第二栅极驱动单元需要采用级传信号线进行信号的级传，相较于当前采用第三金属层形成级传信号线，第三金属层不能与第一金属层和第二金属层重叠，因此，级传信号线会占用较大的空间，增大边框；本申请通过使级传信号线从栅极驱动电路区连接第一栅极驱动单元和第二栅极驱动单元，避免了级传信号线占用空间，减少了显示面板的边框。
在一种实施例中，所述第一初始化晶体管和所述补偿晶体管为氧化物半导体晶体管。
在一种实施例中，如图2、图3所示，所述栅极驱动单元还包括第三栅极驱动单元，所述栅极驱动电路区包括第一走线区183a和第二走线区183b，所述第一栅极驱动单元和所述第二栅极驱动单元设置于所述第一走线区183a，所述第三栅极驱动单元设置于所述第二走线区，至少部分所述级传信号线设置于所述第二走线区183b。本申请通过将至少部分级传信号线设置在第二走线区，避免级传信号线在连接第一栅极驱动单元与第二栅极驱动单元时出现信号串扰，同时，级传信号线设置于第二走线区，可以避免级传信号线占用空间，减少显示面板的边框的宽度。
具体的，如图2所示，可以看到栅极驱动单元会分别采用控制P型晶体管的扫描信号线P Scan（n）和控制N型晶体管的扫描信号线N Scan（n）对晶体管进行控制，因此，需要设置第一走线区和第二走线区分别设置扫描信号线N Scan（n）对应的栅极驱动单元和扫描信号线P Scan（n）对应的栅极驱动单元。如图3所示，图3示出了某一级栅极驱动单元中的N Scan（n）对应的栅极驱动单元和扫描信号线P Scan（n）对应的栅极驱动单元以及连接至显示区的走线设置，本申请实施例将级传信号线设置于第二走线区183b中，即图3中的级传信号线设置区185位于第二走线区183b中，减小级传信号线占用的边框，减小显示面板的边框。
在一种实施例中，所述第一栅极驱动单元在所述第一走线区与所述第二走线区的交界处穿过过孔连接至所述级传信号线，所述第二栅极驱动单元在所述第一走线区与所述第二走线区的交界处穿过过孔连接至所述级传信号线。通过使第一栅极驱动单元和第二栅极驱动单元在第一走线区和第二走线区的交接处穿过过孔连接至级传信号线，可以通过级传信号线进行信号传递，且级传信号线与栅极驱动单元的连接处位于栅极驱动电路区，避免级传信号线占用空间，且栅极驱动单元无需延伸，避免栅极驱动单元中的金属发生重叠或者短路导致串扰。
从图3可以看到，N Scan（n）对应的栅极驱动单元会在第一连接处311连接至级传信号线，使得上级栅极驱动单元可以通过级传信号线将信号传递至下级栅极驱动单元，同时，N Scan（n）对应的栅极驱动单元会通过第二连接处312连接至显示区内的像素驱动单元中的晶体管，从而对晶体管进行驱动，由于栅极驱动单元与级传信号线在第一走线区和第二走线区的交界处连接，避免N Scan（n）对应的栅极驱动单元和P Scan（n）对应的栅极驱动单元之间的信号出现干扰或者由于金属重叠和短路产生不良。
在一种实施例中，如图1、图3所示，所述显示面板1还包括设置于所述栅极驱动电路区183和所述显示区181之间的连接走线区184，所述第二走线区183b设置于所述第一走线区183a和所述连接走线区184之间，所述级传信号线122从所述第二走线区183b延伸至所述连接走线区184。本申请通过将级传信号线从第二走线区延伸至连接走线区，使得级传信号线可以与信号线连接，实现信号传输，级传信号线仅需要在连接处占用连接走线区的部分区域，减少了级传信号线的占用空间，减小了显示面板的边框。
在一种实施例中，如图2所示，所述像素驱动单元还包括第二初始化晶体管T7，所述第二初始化晶体管T7与第二初始化信号线VI-ANO连接，用于在第四扫描信号的控制下，向所述发光器件LED阳极输入第二初始化信号；
第一发光控制晶体管T5，通过第二节点与所述驱动晶体管T1相连，用于在发光控制信号的控制下，导通电源高电位信号线ELVDD向所述驱动晶体管T1的电流；
第二发光控制晶体管T6，通过第三节点与所述驱动晶体管T1相连，用于在发光控制信号的控制下，导通所述驱动晶体管T1流向所述发光器件LED阳极的电流。
在一种实施例中，如图2所示，所述像素驱动单元还包括存储电容Cst和升压电容Cboost，所述存储电容Cst一端与所述电源高电位信号线VDD连接，所述存储电容Cst另一端与所述第一节点连接，所述升压电容一端与第一初始化晶体管T4连接，所述升压电容另一端与开关晶体管T2的栅极连接。
可以理解的是，在本申请实施例中，如图2所示，数据线Data传输数据信号，第一初始化信号线VI-G传输第一初始化信号、第二初始化信号线VI-ANO传输第二初始化信号，第一扫描信号线N Scan（n-5）传输第一扫描信号，第二扫描信号线N Scan（n）传输第二扫描信号，第三扫描信号线P Scan（n）传输第三扫描信号，第四扫描信号线P Scan（n-1）传输第四扫描信号，发光控制信号线EM传输发光控制信号，电源低电位信号线ELVSS传输低电位。
其中，P Scan（n）表示本级扫描线，P Scan（n-1）表示上一级扫描线，且上述扫描线用于控制P型晶体管。
电路的工作原理如下：在第一阶段，第一初始化晶体管T4和第二初始化晶体管T7打开，通过第一初始化信号线VI-G输出的初始化信号对驱动晶体管T1的栅极复位，通过第二初始化信号线VI-ANO输出的初始化信号对像素发光单元LED复位；在第二阶段，开关晶体管T2和补偿晶体管T3打开，将数据线Data输入的数据信号写入驱动晶体管T1栅极；在第三阶段，第一发光控制晶体管T5和第二发光控制晶体管T6打开，驱动像素发光单元LED发光。
如图4所示，图4中的（a）为当前显示器件的各部件的设置区域的示意图，图4中的（b）为本申请显示面板的各部分的设置区域的示意图。从图4中的（a）可以看到，在显示区211外，需要分别设置栅极驱动电路设置区212、和级传信号线设置区213，导致显示器件的边框较大。而本申请通过将级传信号线设置在栅极驱动电路区，如图4中的（b）所示，可以看到级传信号线设置区185和栅极驱动电路区183存在重叠，级传信号线设置区185位于栅极驱动电路区183内，减小了显示面板的边框。
本申请实施例以图2中的电路图为例进行了详细说明，但本申请实施例不限于此，例如采用7T1C（7个晶体管一个电容）电路的显示面板也可以采用本申请的设计。
在一种实施例中，为了提高显示面板的柔性和阻隔水氧的能力，如图1所示，衬底11包括第一柔性层111、阻挡层112和第二柔性层113。
在一种实施例中，如图1所示，所述显示面板还包括平坦化层152。
在一种实施例中，所述第一半导体层的材料为低温多晶硅，所述有源层的材料为氧化物，具体为氧化铟镓锌。
如图1所示，本申请实施例以LTPO技术为例说明了显示面板的结构，但本申请实施例不限于此，例如显示面板可以采用LTPS（Low Temperature Poly-silicon，低温多晶硅）技术。
同时，本申请实施例提供一种显示装置，该显示装置包括上述实施例任一所述的显示面板和驱动芯片。
根据上述实施例可知：
本申请实施例提供一种显示面板和显示装置；该显示面板包括显示区和设置于显示区至少一侧的非显示区，显示面板包括衬底和驱动电路层，驱动电路层设置在衬底的一侧，驱动电路层包括设置在非显示区的多级栅极驱动单元、以及连接不同级的栅极驱动单元的级传信号线，其中，驱动电路层包括：设置在衬底一侧的第一半导体层，第一半导体层包括设置在非显示区的多个第一半导体，栅极驱动单元包括第一半导体，级传信号线设置在第一半导体层和衬底之间，且在非显示区与至少部分栅极驱动单元重叠设置。本申请通过将级传信号线设置在第一半导体层和衬底之间，避免级传信号线与栅极驱动单元处于第一半导体层之上的金属走线之间产生寄生电容，使级传信号线可以在非显示区与至少部分栅极驱动单元重叠设置，这样可以无需额外为级传信号线设置对应的布线区域，进而减少了级传信号线占用的边框的空间，缩短了显示面板的边框。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括：显示区和设置在所述显示区至少一侧的非显示区；所述显示面板还包括：
    衬底；
    驱动电路层，设置在所述衬底的一侧，所述驱动电路层包括：设置在所述非显示区的多级栅极驱动单元、以及连接不同级的所述栅极驱动单元的级传信号线；
    其中，所述驱动电路层包括：设置在所述衬底一侧的第一半导体层，所述第一半导体层包括设置在非显示区的多个第一半导体，所述栅极驱动单元包括所述第一半导体；
    所述级传信号线设置在所述第一半导体层和所述衬底之间，且在所述非显示区与至少部分所述栅极驱动单元重叠设置。
  2. 如权利要求1所述的显示面板，其中，所述驱动电路层还包括：设置在所述第一半导体层远离所述衬底一侧的第一金属层，所述第一金属层包括设置在所述非显示区的栅极，所述栅极驱动单元包括所述栅极；
    所述级传信号线在所述非显示区与至少部分所述栅极重叠设置。
  3. 如权利要求2所述的显示面板，其中，所述驱动电路层还包括：设置在所述第一金属层远离所述衬底一侧的第二金属层，所述第二金属层包括设置在所述非显示区的金属走线，所述栅极驱动单元包括所述金属走线；
    所述级传信号线在所述非显示区与至少部分所述金属走线重叠设置。
  4. 如权利要求3所述的显示面板，其中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述第一电极穿过第一过孔连接至所述级传信号线。
  5. 如权利要求4所述的显示面板，其中，所述第一电极穿过第二过孔连接至所述第一半导体，所述第一过孔的宽度大于所述第二过孔的宽度。
  6. 如权利要求3所述的显示面板，其中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述显示面板还包括连接金属，所述第一电极通过连接金属与所述级传信号线连接，所述连接金属穿过过孔连接至级传信号线。
  7. 如权利要求1所述的显示面板，其中，所述显示面板还包括设置在所述驱动电路层远离所述衬底一侧的发光层，所述发光层包括：设置于所述显示区的像素发光单元，
    所述驱动电路层还包括设置在所述显示区且驱动所述像素发光单元的像素驱动单元，以及设置在所述像素驱动单元和所述衬底之间的遮光层，
    其中，所述遮光层包括：设置在所述显示区且与所述像素驱动单元重叠设置的遮光部，和设置在所述非显示区的所述级传信号线。
  8. 如权利要求7所述的显示面板，其中，所述第一半导体层还包括设置在显示区的多个第二半导体，所述像素驱动单元包括所述第二半导体；
    所述第一半导体包括第一沟道区，所述级传信号线不与所述第一沟道区重叠设置；
    所述第二半导体包括第二沟道区，所述遮光部与所述第二沟道区重叠设置。
  9. 如权利要求8所述的显示面板，其中，所述驱动电路层还包括：设置在所述第一半导体层远离所述衬底一侧的第二半导体层，
    所述第二半导体层包括设置在显示区的多个第三半导体，所述像素驱动单元还包括所述第三半导体，所述第三半导体包括金属氧化物材料；
    所述遮光部与所述第三半导体不重叠设置。
  10. 如权利要求7所述的显示面板，其中，所述像素驱动单元包括：
    第一初始化晶体管，与第一初始化信号线连接，所述第一初始化晶体管的栅极连接至第一栅极驱动单元的第一扫描信号线，所述第一初始化晶体管用于在第一扫描信号的控制下，向第一节点输入第一初始化信号；
    开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
    驱动晶体管，用于在第一节点和第二节点电位的控制下，驱动所述像素发光单元发光；
    补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，所述补偿晶体管的栅极连接至第二栅极驱动单元的第二扫描信号线，所述补偿晶体管用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
    其中，所述栅极驱动单元包括：不同级的所述第一栅极驱动单元和所述第二栅极驱动单元，所述级传信号线一端连接至所述第一栅极驱动单元，所述级传信号线另一端沿所述栅极驱动电路区连接至第二栅极驱动单元。
  11. 如权利要求10所述的显示面板，其中，所述栅极驱动单元还包括第三栅极驱动单元，所述栅极驱动电路区包括第一走线区和第二走线区，所述第一栅极驱动单元和所述第二栅极驱动单元设置于所述第一走线区，所述第三栅极驱动单元设置于所述第二走线区，至少部分所述级传信号线设置于所述第二走线区。
  12. 如权利要求11所述的显示面板，其中，所述第一栅极驱动单元在所述第一走线区与所述第二走线区的交界处穿过过孔连接至所述级传信号线，所述第二栅极驱动单元在所述第一走线区与所述第二走线区的交界处穿过过孔连接至所述级传信号线。
  13. 如权利要求11所述的显示面板，其中，所述显示面板还包括设置于所述栅极驱动电路区和所述显示区之间的连接走线区，所述第二走线区设置于所述第一走线区和所述连接走线区之间，所述级传信号线从所述第二走线区延伸至所述连接走线区。
  14. 一种显示装置，其包括显示面板和驱动芯片，显示面板包括显示区和设置在所述显示区至少一侧的非显示区；所述显示面板还包括：
    衬底；
    驱动电路层，设置在所述衬底的一侧，所述驱动电路层包括：设置在所述非显示区的多级栅极驱动单元、以及连接不同级的所述栅极驱动单元的级传信号线；
    其中，所述驱动电路层包括：设置在所述衬底一侧的第一半导体层，所述第一半导体层包括设置在非显示区的多个第一半导体，所述栅极驱动单元包括所述第一半导体；
    所述级传信号线设置在所述第一半导体层和所述衬底之间，且在所述非显示区与至少部分所述栅极驱动单元重叠设置。
  15. 如权利要求14所述的显示装置，其中，所述驱动电路层还包括：设置在所述第一半导体层远离所述衬底一侧的第一金属层，所述第一金属层包括设置在所述非显示区的栅极，所述栅极驱动单元包括所述栅极；
    所述级传信号线在所述非显示区与至少部分所述栅极重叠设置。
  16. 如权利要求15所述的显示装置，其中，所述驱动电路层还包括：设置在所述第一金属层远离所述衬底一侧的第二金属层，所述第二金属层包括设置在所述非显示区的金属走线，所述栅极驱动单元包括所述金属走线；
    所述级传信号线在所述非显示区与至少部分所述金属走线重叠设置。
  17. 如权利要求16所述的显示装置，其中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述第一电极穿过第一过孔连接至所述级传信号线。
  18. 如权利要求17所述的显示装置，其中，所述第一电极穿过第二过孔连接至所述第一半导体，所述第一过孔的宽度大于所述第二过孔的宽度。
  19. 如权利要求16所述的显示装置，其中，所述驱动电路层还包括：设置于所述第二金属层远离所述第一金属层的一侧的源漏极层，所述栅极驱动单元包括晶体管，所述晶体管包括设置于所述源漏极层的第一电极和第二电极，所述显示面板还包括连接金属，所述第一电极通过连接金属与所述级传信号线连接，所述连接金属穿过过孔连接至级传信号线。
  20. 如权利要求14所述的显示装置，其中，所述显示面板还包括设置在所述驱动电路层远离所述衬底一侧的发光层，所述发光层包括：设置于所述显示区的像素发光单元，
    所述驱动电路层还包括设置在所述显示区且驱动所述像素发光单元的像素驱动单元，以及设置在所述像素驱动单元和所述衬底之间的遮光层，
    其中，所述遮光层包括：设置在所述显示区且与所述像素驱动单元重叠设置的遮光部，和设置在所述非显示区的所述级传信号线。
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CN115206997A (zh) * 2022-07-01 2022-10-18 武汉华星光电半导体显示技术有限公司 显示面板和显示装置

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