WO2022111086A1 - 栅极驱动电路及其制造方法、阵列基板、显示装置 - Google Patents

栅极驱动电路及其制造方法、阵列基板、显示装置 Download PDF

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Publication number
WO2022111086A1
WO2022111086A1 PCT/CN2021/123296 CN2021123296W WO2022111086A1 WO 2022111086 A1 WO2022111086 A1 WO 2022111086A1 CN 2021123296 W CN2021123296 W CN 2021123296W WO 2022111086 A1 WO2022111086 A1 WO 2022111086A1
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Prior art keywords
pull
transistor
layer
gate
interlayer
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PCT/CN2021/123296
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English (en)
French (fr)
Inventor
苏同上
成军
周斌
赵策
王庆贺
汪军
闫梁臣
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority claimed from CN202011356542.4A external-priority patent/CN112466948B/zh
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/801,003 priority Critical patent/US20230086999A1/en
Publication of WO2022111086A1 publication Critical patent/WO2022111086A1/zh

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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a gate driving circuit and a manufacturing method thereof, an array substrate, and a display device.
  • the gate driver circuit is one of the necessary circuits for driving the normal display of the display panel, and in order to achieve a narrow border, the gate driver on array (GOA) technology is generally used to integrate the gate driver circuit in the array. on the substrate. Therefore, the gate drive circuit can also be called a GOA circuit.
  • GOA gate driver on array
  • a GOA circuit generally includes a plurality of transistors capable of realizing different functions, for example, an input transistor that realizes an input function and an output transistor that realizes an output function. Also, each transistor included in the GOA circuit includes a gate metal layer and a source-drain metal layer.
  • the present disclosure provides a gate driving circuit and a manufacturing method thereof, an array substrate, and a display device.
  • the technical solution is as follows:
  • a gate drive circuit includes: a plurality of first transistors; at least one first target transistor in the plurality of first transistors includes:
  • the first light-shielding layer is made of conductive material
  • the first light shielding layer is connected to the first gate metal layer.
  • the conductive material is a metal material.
  • the thickness of the first light shielding layer is greater than a thickness threshold.
  • the plurality of first transistors include: an input transistor, a reset transistor, a first output transistor, a second output transistor, a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, and a fourth pull-down control transistor.
  • the gate and first pole of the input transistor are connected to the input terminal, and the second pole is connected to the pull-up node;
  • the gate of the first output transistor is connected to the pull-up node, the first pole is connected to the first clock signal terminal, and the second pole is connected to the shift output terminal;
  • the gate of the second output transistor is connected to the pull-up node, the first pole is connected to the second clock signal terminal, and the second pole is connected to the driving output terminal;
  • the gate of the reset transistor is connected to the reset signal terminal, the first pole is connected to the first pull-down power supply terminal, and the second pole is connected to the pull-up node;
  • the gate and first electrode of the first pull-down control transistor are both connected to the pull-down control power supply terminal, and the second electrode is connected to the gate of the second pull-down control transistor;
  • the first pole of the second pull-down control transistor is connected to the pull-down control power supply terminal, and the second pole is connected to the pull-down node;
  • the gates of the third pull-down control transistor and the fourth pull-down control transistor are both connected to the pull-up node, and the first electrodes of the third pull-down control transistor and the fourth pull-down control transistor are both connected to the pull-up node.
  • a first pull-down power supply terminal is connected, a second pole of the third pull-down control transistor is connected to a gate of the second pull-down control transistor, and a second pole of the fourth pull-down control transistor is connected to the pull-down node;
  • the gate of the fifth pull-down control transistor is connected to the shift output terminal of another cascaded gate driving circuit, the first pole is connected to the first pull-down power supply terminal, and the second pole is connected to the pull-down node ;
  • the gates of the first pull-down transistor, the second pull-down transistor and the third pull-down transistor are all connected to the pull-down node, and the first electrodes of the first pull-down transistor and the second pull-down transistor are connected to the pull-down node. are connected to the first pull-down power supply terminal, the first pole of the third pull-down transistor is connected to the second pull-down power supply terminal, and the second pole of the first pull-down transistor is connected to the pull-up node, so The second pole of the second pull-down transistor is connected to the shift output terminal, and the second pole of the third pull-down transistor is connected to the drive output terminal;
  • the gate of the fourth pull-down transistor is connected to the shift output terminal of another gate driving circuit, the first pole is connected to the first pull-down power supply terminal, and the second pole is connected to the pull-up node.
  • the at least one first target transistor includes: the second output transistor, the second pull-down transistor and/or the third pull-down transistor.
  • the at least one first target transistor further includes: an active layer and a gate insulating layer;
  • the active layer, the gate insulating layer, the first gate metal layer and the first source/drain metal layer are sequentially stacked along a direction away from the first light shielding layer.
  • the orthographic projection of the first light shielding layer on the base substrate covers the orthographic projection of the active layer on the base substrate.
  • the at least one first target transistor further includes: a buffer layer, an interlayer intervening layer and a passivation layer;
  • the buffer layer is located between the first light shielding layer and the active layer
  • the interlayer interlayer is located between the first source and drain metal layer and the first gate metal layer;
  • the passivation layer is located on a side of the first source-drain metal layer away from the interlayer interlayer.
  • the passivation layer, the buffer layer and the interlayer intervening layer have first via holes, and the passivation layer and the interlayer intervening layer also have second via holes;
  • the at least one first target transistor further includes: a first connection portion;
  • the first connection portion is connected to the first light shielding layer through the first via hole, and is connected to the first gate metal layer through the second via hole.
  • the active layer includes a first conductive region and a second conductive region;
  • the interlayer intervening layer has a third via hole and a fourth via hole;
  • the first source-drain metal layer including a first source pattern and a first drain pattern;
  • the at least one first target transistor further includes: a second connection part and a third connection part;
  • one end of the second connection portion is connected to the first source pattern, and the other end is connected to the first conductive region through the third via hole;
  • One end of the third connection portion is connected to the first drain pattern, and the other end is connected to the second conductive region through the fourth via hole.
  • a method for manufacturing a gate drive circuit comprising:
  • a first light shielding layer is formed on one side of the base substrate by using a conductive material
  • the first light shielding layer is connected to the first gate metal layer.
  • the method further includes:
  • a buffer layer, an active layer and a buffer layer are sequentially formed on the side of the first light shielding layer away from the base substrate gate insulating layer;
  • passivation is formed on the side of the first source-drain metal layer away from the interlayer interlayer Floor;
  • a first connection portion is formed on the side of the passivation layer away from the base substrate, the first connection portion is connected to the first light shielding layer through the first via hole, and is connected to the first light shielding layer through the second via hole.
  • a hole is connected to the first gate metal layer.
  • an array substrate comprising:
  • a base substrate having a display area, and a non-display area surrounding the display area;
  • the gate drive circuit is the gate drive circuit according to the above aspect
  • each of the pixel circuits includes a plurality of second transistors, and at least one second target transistor in the plurality of second transistors includes: a second light-shielding layer located on one side of the base substrate and stacked in sequence, a second target transistor There are two gate metal layers and second source and drain metal layers, the second light shielding layer is made of conductive material, and the second source and drain metal layers include second source electrode patterns and second drain electrode patterns, so The second light shielding layer is connected to the second source pattern.
  • the plurality of second transistors include: a switching transistor and a driving transistor;
  • the at least one second target transistor includes the drive transistor.
  • a display device comprising: a source driving circuit, and the array substrate according to the above aspect;
  • the source driving circuit is connected to the data lines in the array substrate, and the source driving circuit is used for providing data signals to the data lines.
  • FIG. 1 is a schematic structural diagram of a first target transistor in a gate driving circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a first target transistor in a gate driving circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a relationship between a threshold voltage and an on-state current of a first target transistor according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a first target transistor in another gate driving circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a method for manufacturing a gate driving circuit provided by an embodiment of the present disclosure
  • FIG. 7 is a flowchart of another method for manufacturing a gate driving circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a base substrate provided with a first light shielding layer provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a base substrate provided with a buffer layer provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a base substrate formed with an active layer according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a base substrate with a gate insulating layer formed thereon provided by an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of a substrate substrate formed with a conductive region provided by an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of a base substrate with a first gate metal layer formed thereon provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of a substrate substrate formed with an interlayer interposition layer provided by an embodiment of the present disclosure
  • FIG. 15 is a schematic structural diagram of a base substrate with a first source-drain metal layer formed thereon provided by an embodiment of the present disclosure
  • FIG. 16 is a schematic structural diagram of a substrate substrate formed with a passivation layer according to an embodiment of the present disclosure
  • FIG. 17 is a schematic structural diagram of a substrate substrate formed with via holes according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a base substrate provided with a connecting portion according to an embodiment of the present disclosure
  • FIG. 19 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 20 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • a display panel generally includes a plurality of pixels arranged in an array, and each pixel may include a pixel circuit and a light-emitting element.
  • the electrode drive signal and the data signal from the data line drive the light-emitting element to emit light.
  • the GOA circuit can be connected with the gate lines in the display panel and used to provide gate driving signals for the gate lines.
  • the threshold voltage Vth of each transistor in the GOA circuit will undergo a severe negative drift (abbreviated as negative drift).
  • the on-state current Ion of each transistor in the GOA circuit is generally required to be relatively large. Therefore, the size of each transistor in the GOA circuit, such as the aspect ratio (W/L), needs to be set larger. , usually the aspect ratio W/L is 2000/6, which is not conducive to the realization of the narrow frame of the display device.
  • an embodiment of the present disclosure provides a new gate driving circuit, the gate driving circuit includes a plurality of first transistors, wherein at least one first target transistor includes a gate metal layer connected to the first gate metal layer.
  • the first shading layer is provided.
  • FIG. 1 shows a schematic structural diagram of a first target transistor provided by an embodiment of the present disclosure.
  • the first target transistor may include:
  • the first light shielding layer 10 can be made of conductive material, and the first light shielding layer 10 and the first gate metal layer 20 can be connected.
  • the first target transistor has a double-gate structure, and two conductive channels are formed in total, so that the threshold voltage Vth of the first target transistor can be shifted positively, that is, the negative shift of the first target transistor can be effectively suppressed Phenomenon.
  • Vth is drifting positively, the on-state current Ion of the first target transistor will also increase accordingly.
  • the calculation formula of the known on-state current Ion is:
  • Ion W* ⁇ n* Cox(Vgs-Vth) 2 /L, where W is the channel width, L is the channel length, ⁇ n is the carrier mobility of the first target transistor, and Cox is the first target The capacitance of the gate insulating layer of the transistor.
  • the size of the first target transistor can be correspondingly reduced on the premise that Ion is increased by connecting the first light shielding layer 10 to the first gate metal layer 20 .
  • the channel width W and/or the channel length L of the first target transistor may be reduced.
  • the width-to-length ratio W/L of the first target transistor needs to be set to 2000/6. Then after the first light shielding layer 10 is provided, the channel length L can be reduced, for example, the aspect ratio W/L can be changed from 2000/6 to 2000/5; or, the channel width W can be reduced, so that the aspect ratio W/L can be reduced. While W/L is changed from 2000/6 to 1500/5, the above target on-state current Ion is still achieved. In this way, a foundation is laid for the realization of the narrow frame, that is, the realization of the narrow frame of the display device is facilitated.
  • the embodiments of the present disclosure provide a gate driving circuit. Since at least one transistor in the gate driving circuit includes a first light shielding layer made of conductive material, and the first light shielding layer is connected to the first gate metal layer of the transistor, two conductive channels are formed, The on-state current is increased, thereby effectively suppressing the negative drift of the threshold voltage.
  • the first source-drain metal layer 30 may include a first source (source) pattern 301 and a first drain (drain) pattern 302 .
  • FIG. 3 shows the three In this case, a schematic diagram showing the relationship between the threshold voltage Vth and the on-state current Ion of the first target transistor.
  • the threshold voltage Vth of the first target transistor in which the first light shielding layer 10 is connected to the first source pattern 301 is set to be 0.03 volts (V), and the corresponding on-state current Ion is about 30 amperes ( A).
  • the threshold voltage Vth of the first target transistor without the first light shielding layer 10 is 0.59V, and the corresponding on-state current Ion is about 32A.
  • the threshold voltage Vth of the first target transistor connected to the first light shielding layer 10 and the first gate metal layer 20 is set to be 0.08V, and the corresponding on-state current Ion is about 42A.
  • the negative drift degree of the threshold voltage Vth of the first target transistor is negative compared to that the first light shielding layer 10 is not provided, or that the first light shielding layer 10 is connected to the first source pattern 301 . smaller, and the on-state current Ion is larger.
  • the conductive material for making the first light shielding layer 10 may be a metal material.
  • the first light shielding layer may also be referred to as the first metal light shielding layer.
  • the conductive material can also be other materials with conductive properties, such as organic conductive materials. This embodiment of the present disclosure does not limit the conductive material.
  • the thickness of the first light shielding layer 10 may be greater than a thickness threshold. That is, the thickness of the first light shielding layer 10 can be relatively large. In this way, the effective blocking of light can be further ensured.
  • FIG. 4 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present disclosure.
  • the first target transistor may further include an active (active, ACT) layer 40 and a gate insulator (GI) layer 50 .
  • active, ACT active
  • GI gate insulator
  • the active layer 40 , the gate insulating layer 50 , the first gate metal layer 20 and the first source-drain metal layer 30 may be stacked in sequence along the direction away from the first light shielding layer 10 . That is, the first target transistor described in the embodiment of the present disclosure may be a transistor with a top-gate structure.
  • the first target crystal is not limited to be a top gate structure.
  • it can also be a transistor with a bottom gate structure.
  • another metal layer may be provided on the side of the first source-drain metal layer 30 away from the base substrate 00 , and the first light shielding layer 10 may be provided to connect with the additional metal layer.
  • the orthographic projection of the first light shielding layer 10 on the base substrate 00 may cover the orthographic projection of the active layer 40 on the base substrate 00 . In this way, a better shading effect can be further ensured.
  • the first target transistor may further include: a buffer layer 60 , an interlayer dielectric (ILD) layer 70 and a passivation layer (PVX) 80 .
  • the interlayer interlayer 70 may also be referred to as an interlayer insulating layer.
  • the buffer layer 60 may be located between the first light shielding layer 10 and the active layer 40, the interlayer interlayer 70 may be located between the first source/drain metal layer 30 and the first gate metal layer 20, and the passivation layer 80 may be located on a side of the first source-drain metal layer 30 away from the interlayer interlayer 70 .
  • the passivation layer 80 , the buffer layer 60 and the interlayer interlayer 70 may have a first via K1 , and the passivation layer 80 and the interlayer interlayer 70 may also have a first via hole K1 .
  • the first target transistor may further include: a first connection part B1.
  • the first connection portion B1 may be connected to the first light shielding layer 10 through a first via hole K1, and may be connected to the first gate metal layer 20 through a second via hole K2.
  • the first via K1 and the second via K2 may also be referred to as connecting (connective, CNT) vias.
  • the first connection part B1 may include three parts B11 , B12 and B13 , the first part B11 may be located in the first via hole K1 and connected to the first light shielding layer 10 , and the second part B12 may be located in the second Inside the via hole K2 and connected to the first gate metal layer 20, the third part B13 may be located in the passivation layer 80 and connect the first part B11 and the second part B12.
  • the active layer 40 may include a first conductive region Q1 and a second conductive region Q2.
  • the interlayer interlayer 70 may further have third via holes K3 and fourth via holes K4.
  • the first source-drain metal layer 30 may include first source patterns 301 and first drain patterns 302 .
  • the first target transistor may further include: a second connection part B2 and a third connection part B3.
  • the third via K3 and the fourth via K4 may also be referred to as ILD vias.
  • connection portion B2 may be connected to the first source pattern 301, and the other end may be connected to the first conductive region Q1 through the third via hole K3.
  • One end of the third connection part B3 may be connected to the first drain pattern 302, and the other end may be connected to the second conductive region Q2 through the fourth via hole K4.
  • FIG. 5 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present disclosure.
  • the plurality of first transistors in the gate driving circuit may include: an input transistor M1, a reset transistor M2, a first output transistor M3, a second output transistor M4, a first pull-down control transistor M5, a Two pull-down control transistors M6, third pull-down control transistors M7, fourth pull-down control transistors M8, fifth pull-down control transistors M9, first pull-down transistors M10, second pull-down transistors M11, third pull-down transistors M12, and fourth pull-down transistors M13.
  • the gate and first pole of the input transistor M1 may be connected to the input terminal IN1, and the second pole may be connected to the pull-up node P1.
  • the input transistor M1 can be used to transmit the input signal to the pull-up node P1 under the control of the input signal provided by the input terminal IN1 to charge the pull-up node P1.
  • the gate of the first output transistor M3 may be connected to the pull-up node P1, the first pole may be connected to the first clock signal terminal CLK1, and the second pole may be connected to the shift output terminal CR1.
  • the shift output terminal CR1 can be connected to the input terminal IN of the cascaded gate driving circuit of the next stage, and is used for driving the gate driving circuit of the subsequent stage to work to realize the shift function.
  • the potential of the input signal may be an effective potential.
  • the first output transistor M3 can transmit the first clock signal provided by the first clock signal terminal CLK1 to the shift output terminal CR1 under the potential control of the pull-up node P1.
  • the gate of the second output transistor M4 may be connected to the pull-up node P1, the first pole may be connected to the second clock signal terminal CLK2, and the second pole may be connected to the driving output terminal OUT1.
  • the output terminal OUT1 can be connected to a gate line in the display panel, and is used to provide a gate driving signal for the gate line.
  • the second output transistor M4 may transmit the second clock signal provided by the second clock signal terminal CLK2 to the driving output terminal OUT1 under the potential control of the pull-up node P1.
  • the gate of the reset transistor M2 may be connected to the reset signal terminal RST, the first pole may be connected to the first pull-down power supply terminal VGL1, and the second pole may be connected to the pull-up node P1.
  • the reset transistor M2 can transmit the first pull-down power signal provided by the first pull-down power terminal VGL1 to the pull-up node P1 under the control of the reset signal provided by the reset signal terminal RST, so as to reset the noise reduction for the pull-up node P1.
  • the potential of the first pull-down power signal may be an inactive potential.
  • the inactive potential when the transistor is an N-type transistor, the inactive potential may be a low potential relative to the active potential.
  • the inactive potential when the transistor is a P-type transistor, the inactive potential may be higher than the active potential. This embodiment of the present disclosure does not limit this.
  • Both the gate and the first electrode of the first pull-down control transistor M5 may be connected to the pull-down control power supply terminal VDD, and the second electrode may be connected to the gate of the second pull-down control transistor M6.
  • the first pull-down control transistor M5 may transmit the pull-down control power signal to the gate of the second pull-down control transistor M6 under the control of the pull-down control power signal provided by the pull-down control power terminal VDD.
  • the potential of the pull-down control power signal may be an effective potential.
  • the first pole of the second pull-down control transistor M6 may be connected to the pull-down control power supply terminal VDD, and the second pole may be connected to the pull-down node P2.
  • the second pull-down control transistor M6 may transmit the pull-down control power signal to the pull-down node P2 under the control of the pull-down control power signal, so as to control the pull-down node P2.
  • the gates of the third pull-down control transistor M7 and the fourth pull-down control transistor M8 may both be connected to the pull-up node P1, and the first electrodes of the third pull-down control transistor M7 and the fourth pull-down control transistor M8 may both be connected to the first pull-down control transistor M8.
  • the power supply terminal VGL1 is connected, the second pole of the third pull-down control transistor M7 may be connected to the gate of the second pull-down control transistor M6, and the second pole of the fourth pull-down control transistor M8 may be connected to the pull-down node P2.
  • the third pull-down control transistor M7 may transmit the first pull-down power signal to the gate of the second pull-down control transistor M6 under the potential control of the pull-up node P1.
  • the fourth pull-down control transistor M8 can transmit the first pull-down power signal to the pull-down node P2 under the potential control of the pull-up node P1, so as to control the pull-down node P2.
  • the gate of the fifth pull-down control transistor M9 may be connected to the shift output terminal of another gate driving circuit in cascade connection, the first pole may be connected to the first pull-down power supply terminal VGL1, and the second pole may be connected to the pull-down node P2 .
  • the gate of the fifth pull-down control transistor M9 shown in FIG. 5 is connected to the shift output terminal CR1 (N-1) of the cascaded previous gate driving circuit, where N represents that the current stage is the Nth stage, And N is an integer greater than 1.
  • the fifth pull-down control transistor M9 can transmit the first pull-down power supply signal to the pull-down node P2 under the control of the signal provided by the shift output terminal of another cascaded gate driving circuit, so as to realize the control of the pull-down node P2. control.
  • the gates of the first pull-down transistor M10, the second pull-down transistor M11 and the third pull-down transistor M12 may all be connected to the pull-down node P2, and the first poles of the first pull-down transistor M10 and the second pull-down transistor M11 may be connected to the first pull-down transistor M10 and the second pull-down transistor M11.
  • the pull-down power supply terminal VGL1 is connected, the first pole of the third pull-down transistor M12 can be connected with the second pull-down power supply terminal VGL2, the second pole of the first pull-down transistor M10 can be connected with the pull-up node P1, and the second pull-down transistor M11
  • the second pole may be connected to the shift output terminal CR1, and the second pole of the third pull-down transistor M12 may be connected to the driving output terminal OUT1.
  • the first pull-down transistor M10 may transmit a first pull-down power supply signal to the pull-up node P1 under the potential control of the pull-down node P2, so as to realize the pull-down noise reduction of the pull-up node P1.
  • the second pull-down transistor M11 can transmit a first pull-down power signal to the shift output terminal CR1 under the potential control of the pull-down node P2, so as to realize the pull-down noise reduction of the shift output terminal CR1.
  • the third pull-down transistor M12 can transmit the second pull-down power signal provided by the second pull-down power terminal VGL2 to the driving output terminal OUT1 under the potential control of the pull-down node P2, so as to realize the pull-down noise reduction of the driving output terminal OUT1.
  • the potential of the second pull-down power supply signal may also be an inactive potential.
  • the gate of the fourth pull-down transistor M13 may be connected to the shift output terminal of another gate driving circuit, the first pole may be connected to the first pull-down power supply terminal VGL1, and the second pole may be connected to the pull-up node P1.
  • the gate of the fourth pull-down transistor M13 shown in FIG. 5 is connected to the shift output terminal CR1(N+1) of the next gate driving circuit in cascade connection.
  • the fourth pull-down transistor M13 can transmit the first pull-down power supply signal to the pull-up node P1 under the control of a signal provided by the shift output terminal of another gate driving circuit, so as to realize the pull-down noise reduction of the pull-up node P1 .
  • the gate driving circuit may further include a storage capacitor C1.
  • One end of the storage capacitor C1 can be connected to the pull-up node P1, and the other end can be connected to the driving output end OUT1.
  • the at least one first target transistor described in the embodiment of the present disclosure may include: a second output transistor M4, a second pull-down transistor M11 and/or a third pull-down transistor M12.
  • the second output transistor M4 is used to provide the gate driving signal to the gate line
  • the second pull-down transistor M11 is used to pull down the noise reduction for the shift output terminal CR1
  • the third pull-down transistor M12 is used to drive the output terminal OUT. Pull-down noise reduction, so the on-state current Ion required by the second output transistor M4, the second pull-down transistor M11 and the third pull-down transistor M12 is relatively large.
  • the at least one first target transistor shown is a second output transistor M4 , a second pull-down transistor M11 and a third pull-down transistor M12 . It can be seen from FIG. 5 that the first light shielding layer 10 is connected to the gate of the second output transistor M4, the gate of the second pull-down transistor M11 and the gate of the third pull-down transistor M12.
  • the gate driving circuit is not limited to the structure of 13T1C (ie, 13 transistors and one capacitor) shown in FIG. 5 , but may also be other structures such as 7T1C, which are not limited in the embodiments of the present disclosure.
  • the first light shielding layer 10 may also be made of an insulating material, and when it is made of an insulating material, the first light shielding layer 10 is not connected to any hierarchical structure. By arranging the first light shielding layer 10 made of insulating material, the stability of light can be improved, and the problem of negative drift caused by light can be solved.
  • the embodiments of the present disclosure provide a gate driving circuit. Since at least one transistor in the gate driving circuit includes a first light shielding layer made of conductive material, and the first light shielding layer is connected to the first gate metal layer of the transistor, two conductive channels are formed, The on-state current is increased, thereby effectively suppressing the negative drift of the threshold voltage.
  • FIG. 6 is a flowchart of a method for manufacturing a gate driving circuit provided by an embodiment of the present disclosure, which can be used to manufacture the gate driving circuit shown in any of FIG. 1 , FIG. 2 , FIG. 4 or FIG. 5 .
  • the method may include:
  • Step 601 using a conductive material to form a first light shielding layer on one side of the base substrate.
  • the conductive material may be a metal material, and a patterning process may be used to form the first light shielding layer on the provided base substrate.
  • Step 602 forming a first gate metal layer and a first source and drain metal layer on the side of the first light shielding layer away from the base substrate.
  • the first gate metal layer and the first source and drain metal layers may be formed on the base substrate on which the first light shielding layer is formed by using a patterning process. And the first light shielding layer is arranged to be connected with the first gate metal layer.
  • the embodiments of the present disclosure provide a method for manufacturing a gate driving circuit.
  • arranging the first light-shielding layer and connecting the first light-shielding layer to the first gate metal layer two conductive channels can be formed, the on-state current can be increased, and the negative voltage of the transistor threshold voltage in the gate driving circuit can be effectively suppressed. drift.
  • FIG. 7 is a flowchart of a method for manufacturing a gate driving circuit provided by an embodiment of the present disclosure, which can be used to manufacture the gate driving circuit shown in any of FIG. 1 , FIG. 2 , FIG. 4 or FIG. 5 .
  • the method may include:
  • Step 701 using a conductive material to form a first light shielding layer on one side of the base substrate.
  • a base substrate may be provided first as a carrier, and then a patterning process is used to form the first light shielding layer on one side of the base substrate.
  • the patterning process may include: gluing, exposing, developing and etching.
  • the base substrate may be a glass substrate or a flexible substrate.
  • the base substrate 00 on which the first light shielding layer 10 is formed may refer to the structure shown in FIG. 8 .
  • Step 702 forming a buffer layer, an active layer and a gate insulating layer in sequence on the side of the first light shielding layer away from the base substrate.
  • a buffer layer may be deposited on the side of the first light shielding layer away from the base substrate by a deposition process.
  • an active layer pattern is deposited on the side of the buffer layer away from the first light shielding layer by a deposition process, and the active layer pattern is processed by a patterning process to obtain an active layer.
  • a gate insulating layer pattern is deposited on the side of the active layer away from the buffer layer by a deposition process, and the gate insulating layer pattern is processed by a patterning process (eg, dry patterning process) to obtain a gate insulating layer.
  • a patterning process eg, dry patterning process
  • the active layer may be conductively treated by plasma doped with helium (He).
  • the base substrate 00 with the buffer layer 70 formed thereon may refer to the structure shown in FIG. 9 .
  • the base substrate 00 on which the active layer 40 is formed may refer to the structure shown in FIG. 10 .
  • the base substrate 00 on which the gate insulating layer 50 is formed may refer to the structure shown in FIG. 11 .
  • Referring to the structure shown in FIG. 12 the base substrate 00 after conducting the conducting treatment on the active layer 40 can be seen from FIG. 12 , the active layer 40 has a first conducting region Q1 and a second conducting region Q2 .
  • Step 703 forming a first gate metal layer on the side of the gate insulating layer away from the active layer.
  • a gate metal pattern may be deposited on the side of the gate insulating layer away from the active layer by a deposition process, and the gate is processed by a patterning process (eg, a wet patterning process).
  • the metal pattern results in a first gate metal layer.
  • this structure may also be referred to as a top gate structure.
  • the base substrate 00 on which the first gate metal layer 20 is formed may refer to the structure shown in FIG. 13 .
  • Step 704 forming an interlayer interlayer on the side of the first gate metal layer away from the base substrate.
  • a deposition process may be continued to form an interlayer interlayer on the side of the first gate metal layer away from the base substrate.
  • the base substrate 00 with the interlayer interposition layer 70 formed thereon may refer to the structure shown in FIG. 14 .
  • Step 705 forming a first source pattern and a first drain pattern on the side of the interlayer interlayer far away from the first gate metal layer.
  • a first source-drain metal layer may be deposited on the side of the interlayer interlayer away from the first gate metal layer by a deposition process, and a patterning process is used to process the layer.
  • the first source-drain metal layer obtains a first source pattern and a first drain pattern.
  • the base substrate 00 formed with the first source pattern 301 and the first drain pattern 302 may refer to the structure shown in FIG. 15 .
  • Step 706 forming a passivation layer on the side of the first source pattern and the first drain pattern away from the interlayer interlayer.
  • a passivation layer may be deposited on the side of the first source pattern and the first drain pattern away from the interlayer interlayer by a deposition process.
  • the base substrate 00 formed with the passivation layer 80 may refer to the structure shown in FIG. 16 .
  • Step 707 forming a first via hole exposing the first light shielding layer in the passivation layer, the interlayer intervening layer and the buffer layer.
  • a photoresist may be coated, and a first via hole exposing the first light shielding layer may be formed through an exposure process.
  • Step 708 forming a second via hole in the passivation layer and the interlayer interlayer to expose the first gate metal layer.
  • step 707 for the method of forming the second via hole, which is not repeated here.
  • step 707 may continue to form a third via hole exposing the first conductive region Q1 and a fourth via hole exposing the second conductive region Q2 in the interlayer interlayer.
  • the base substrate 00 formed with the first via hole K1 , the second via hole K2 , the third via hole K3 and the fourth via hole K4 reference may be made to the structure shown in FIG. 17 .
  • Step 709 forming a first connection part on the side of the passivation layer away from the base substrate, the first connection part is connected to the first light shielding layer through a first via hole, and is connected to the first gate metal layer through a second via hole .
  • a first connection part may be formed to connect the first light shielding layer and the first gate metal layer through the first via hole and the second via hole.
  • a second connection portion may be formed, connecting the first source pattern and the first conductive region through a third via hole, and a third connection portion may be formed, connecting the first drain pattern and the second conductor through a fourth via hole ization area.
  • each connection part may be made of conductive material, such as metal.
  • the base substrate 00 formed with the first connection portion B1 , the second connection portion B2 and the third connection portion B3 may refer to the structure shown in FIG. 18 .
  • the sequence of steps of the manufacturing method provided by the embodiments of the present disclosure can be adjusted appropriately, and the steps can also be correspondingly increased or decreased according to the situation.
  • the above-mentioned via holes can be formed first, then the source and drain patterns can be formed, and finally the passivation layer can be formed.
  • the embodiments of the present disclosure provide a method for manufacturing a gate driving circuit.
  • arranging the first light-shielding layer and connecting the first light-shielding layer to the first gate metal layer two conductive channels can be formed, the on-state current can be increased, and the negative voltage of the transistor threshold voltage in the gate driving circuit can be effectively suppressed. drift.
  • FIG. 19 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate may include: a base substrate 00 having a display area A1 and a non-display area A2 surrounding the display area A1.
  • the gate driving circuit 100 located in the non-display area A2 may be the gate driving circuit 100 shown in any of FIG. 1 , FIG. 2 , FIG. 4 or FIG. 5 . and a plurality of pixel circuits 200 located in the display area A1.
  • each pixel circuit 200 may include a plurality of second transistors.
  • At least one second target transistor in the plurality of second transistors may include:
  • the second light-shielding layer 01, the second gate metal layer 02 and the second source-drain metal layer 03 are located on one side of the base substrate 00 and stacked in sequence, and the second light-shielding layer 01 is made of conductive material (eg, metal material) , and the second source-drain metal layer 03 includes a second source pattern 031 and a second drain pattern 032 , and the second light shielding layer 01 can be connected to the second source pattern 031 .
  • conductive material eg, metal material
  • the pixel circuit 200 shown includes a switching transistor SW and a driving transistor DR, and the second target transistor including the second light shielding layer 01 is the driving transistor DR.
  • FIG. 19 only shows the structure of one first target transistor in the gate driving circuit 100, and does not show other transistor structures.
  • FIG. 20 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 20 , the display device may include: a source driving circuit 300 and an array substrate 000 as shown in FIG. 19 .
  • the source driving circuit 300 can be connected to the data lines in the array substrate 000, and the source driving circuit 300 is used for providing data signals to the data lines. In this way, under the driving of the gate driving circuit 100 and the source driving circuit 300, the pixels in the array substrate 000 can reliably emit light.
  • the display device can be: an organic light-emitting diode display device, a liquid crystal display device, a mobile phone, a computer, a TV, a monitor, electronic paper, a digital photo frame, or a navigator, and any other product or component with a display function.

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Abstract

提供了一种栅极驱动电路及其制造方法、阵列基板、显示装置，属于显示技术领域。由于该栅极驱动电路中的至少一个晶体管包括由导电材料制成的第一遮光层，且该第一遮光层与该晶体管的第一栅极金属层连接，因此形成了两个导电沟道，增大了开态电流，进而有效抑制了阈值电压的负漂。

Description

栅极驱动电路及其制造方法、阵列基板、显示装置
本公开要求于2020年11月27日提交的申请号为202011356542.4、发明名称为“栅极驱动电路及其制造方法、阵列基板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种栅极驱动电路及其制造方法、阵列基板、显示装置。
背景技术
栅极驱动电路是用于驱动显示面板正常显示必不可少的电路之一，且为了实现窄边框，目前一般采用阵列基板行驱动(gate driver on array，GOA)技术将栅极驱动电路集成于阵列基板上。故，栅极驱动电路也可以称为GOA电路。
相关技术中，GOA电路一般包括能够实现不同功能的多个晶体管，如，实现输入功能的输入晶体管和实现输出功能的输出晶体管。并且，GOA电路包括的每个晶体管均包括栅极金属层和源漏极金属层。
但是，相关技术中GOA电路所包括的晶体管的阈值电压负漂较为严重。
发明内容
本公开提供了一种栅极驱动电路及其制造方法、阵列基板、显示装置。所述技术方案如下：
一方面，提供了一种栅极驱动电路，所述栅极驱动电路包括：多个第一晶体管；所述多个第一晶体管中的至少一个第一目标晶体管包括：
位于衬底基板一侧的第一遮光层，所述第一遮光层由导电材料制成；
位于所述第一遮光层远离所述衬底基板一侧的第一栅极金属层和第一源漏极金属层；
其中，所述第一遮光层与所述第一栅极金属层连接。
可选的，所述导电材料为金属材料。
可选的，所述第一遮光层的厚度大于厚度阈值。
可选的，所述多个第一晶体管包括：输入晶体管、复位晶体管、第一输出晶体管、第二输出晶体管、第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管、第五下拉控制晶体管、第一下拉晶体管、第二下拉晶体管、第三下拉晶体管和第四下拉晶体管；
所述输入晶体管的栅极和第一极与输入端连接，第二极与上拉节点连接；
所述第一输出晶体管的栅极与所述上拉节点连接，第一极与第一时钟信号端连接，第二极与移位输出端连接；
所述第二输出晶体管的栅极与所述上拉节点连接，第一极与第二时钟信号端连接，第二极与驱动输出端连接；
所述复位晶体管的栅极与复位信号端连接，第一极与第一下拉电源端连接，第二极与所述上拉节点连接；
所述第一下拉控制晶体管的栅极和第一极均与下拉控制电源端连接，第二极与所述第二下拉控制晶体管的栅极连接；
所述第二下拉控制晶体管的第一极与所述下拉控制电源端连接，第二极与下拉节点连接；
所述第三下拉控制晶体管和所述第四下拉控制晶体管的栅极均与所述上拉节点连接，所述第三下拉控制晶体管和所述第四下拉控制晶体管的第一极均与所述第一下拉电源端连接，所述第三下拉控制晶体管的第二极与所述第二下拉控制晶体管的栅极连接，所述第四下拉控制晶体管的第二极与所述下拉节点连接；
所述第五下拉控制晶体管的栅极与级联的另一个栅极驱动电路的移位输出端连接，第一极与所述第一下拉电源端连接，第二极与所述下拉节点连接；
所述第一下拉晶体管、所述第二下拉晶体管和所述第三下拉晶体管的栅极均与所述下拉节点连接，所述第一下拉晶体管和所述第二下拉晶体管的第一极均与所述第一下拉电源端连接，所述第三下拉晶体管的第一极与第二下拉电源端连接，所述第一下拉晶体管的第二极与所述上拉节点连接，所述第二下拉晶体管的第二极与所述移位输出端连接，所述第三下拉晶体管的第二极与所述驱动输出端连接；
所述第四下拉晶体管的栅极与另一个栅极驱动电路的移位输出端连接，第 一极与所述第一下拉电源端连接，第二极与所述上拉节点连接。
可选的，所述至少一个第一目标晶体管包括：所述第二输出晶体管、所述第二下拉晶体管和/或所述第三下拉晶体管。
可选的，所述至少一个第一目标晶体管还包括：有源层和栅绝缘层；
所述有源层、所述栅绝缘层、所述第一栅极金属层和所述第一源漏极金属层沿远离所述第一遮光层的方向依次层叠。
可选的，所述第一遮光层在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
可选的，所述至少一个第一目标晶体管还包括：缓冲层、层间介定层和钝化层；
所述缓冲层位于所述第一遮光层和所述有源层之间；
所述层间介定层位于所述第一源漏极金属层和所述第一栅极金属层之间；
所述钝化层位于所述第一源漏极金属层远离所述层间介定层的一侧。
可选的，所述钝化层、所述缓冲层和所述层间介定层中具有第一过孔，所述钝化层和所述层间介定层中还具有第二过孔；所述至少一个第一目标晶体管还包括：第一连接部；
其中，所述第一连接部通过所述第一过孔与所述第一遮光层连接，并通过所述第二过孔与所述第一栅极金属层连接。
可选的，所述有源层包括第一导体化区域和第二导体化区域；所述层间介定层中具有第三过孔和第四过孔；所述第一源漏极金属层包括第一源极图案和第一漏极图案；所述至少一个第一目标晶体管还包括：第二连接部和第三连接部；
其中，所述第二连接部的一端与所述第一源极图案连接，另一端通过所述第三过孔连接至所述第一导体化区域；
所述第三连接部的一端与所述第一漏极图案连接，另一端通过所述第四过孔连接至所述第二导体化区域。
另一方面，提供了一种栅极驱动电路的制造方法，所述方法包括：
采用导电材料在衬底基板的一侧形成第一遮光层；
在所述第一遮光层远离所述衬底基板的一侧形成第一栅极金属层和第一源漏极金属层；
其中，所述第一遮光层与所述第一栅极金属层连接。
可选的，所述方法还包括：
在所述第一遮光层远离所述衬底基板的一侧形成第一栅极金属层之前，在所述第一遮光层远离所述衬底基板的一侧依次形成缓冲层、有源层和栅绝缘层；
在所述第一遮光层远离所述衬底基板的一侧形成第一栅极金属层之后，在所述第一栅极金属层远离所述衬底基板的一侧形成层间介定层；
在所述第一遮光层远离所述衬底基板的一侧形成第一源漏极金属层之后，在所述第一源漏极金属层远离所述层间介定层的一侧形成钝化层；
在所述钝化层、所述层间介定层和所述缓冲层中形成暴露所述第一遮光层的第一过孔；
在所述钝化层和所述层间介定层中形成暴露所述第一栅极金属层的第二过孔；
在所述钝化层远离所述衬底基板的一侧形成第一连接部，所述第一连接部通过所述第一过孔与所述第一遮光层连接，并通过所述第二过孔与所述第一栅极金属层连接。
又一方面，提供了一种阵列基板，所述阵列基板包括：
具有显示区，以及围绕所述显示区的非显示区的衬底基板；
位于所述非显示区的栅极驱动电路，所述栅极驱动电路为如上述方面所述的栅极驱动电路；
位于所述显示区的多个像素电路；
其中，每个所述像素电路包括多个第二晶体管，所述多个第二晶体管中的至少一个第二目标晶体管包括：位于所述衬底基板一侧且依次层叠的第二遮光层、第二栅极金属层和第二源漏极金属层，所述第二遮光层由导电材料制成，且所述第二源漏极金属层包括第二源极图案和第二漏极图案，所述第二遮光层与所述第二源极图案连接。
可选的，所述多个第二晶体管包括：开关晶体管和驱动晶体管；
其中，所述至少一个第二目标晶体管包括所述驱动晶体管。
再一方面，提供了一种显示装置，所述显示装置包括：源极驱动电路，以及如上述方面所述的阵列基板；
所述源极驱动电路与所述阵列基板中的数据线连接，所述源极驱动电路用 于向所述数据线提供数据信号。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种栅极驱动电路中第一目标晶体管的结构示意图；
图2是本公开实施例提供的一种栅极驱动电路中第一目标晶体管的结构示意图；
图3是本公开实施例提供的一种第一目标晶体管的阈值电压和开态电流关系示意图；
图4是本公开实施例提供的另一种栅极驱动电路中第一目标晶体管的结构示意图；
图5是本公开实施例提供的一种栅极驱动电路的结构示意图；
图6是本公开实施例提供的一种栅极驱动电路的制造方法流程图；
图7是本公开实施例提供的另一种栅极驱动电路的制造方法流程图；
图8是本公开实施例提供的一种形成有第一遮光层的衬底基板结构示意图；
图9是本公开实施例提供的一种形成有缓冲层的衬底基板结构示意图；
图10是本公开实施例提供的一种形成有有源层的衬底基板的结构示意图；
图11是本公开实施例提供的一种形成有栅绝缘层的衬底基板结构示意图；
图12是本公开实施例提供的一种形成有导体化区域的衬底基板结构示意图；
图13是本公开实施例提供的一种形成有第一栅极金属层的衬底基板结构示意图；
图14是本公开实施例提供的一种形成有层间介定层的衬底基板结构示意图；
图15是本公开实施例提供的一种形成有第一源漏极金属层的衬底基板结构示意图；
图16是本公开实施例提供的一种形成有钝化层的衬底基板结构示意图；
图17是本公开实施例提供的一种形成有过孔的衬底基板结构示意图；
图18是本公开实施例提供的一种形成有连接部的衬底基板结构示意图；
图19是本公开实施例提供的一种阵列基板的结构示意图；
图20是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的发明构思的目的、技术方案和优点更加清楚，下面将结合附图和一些实施例对本公开实施例保护的发明构思做详细描述。
显示面板中一般包括阵列排布的多个像素，每个像素均可以包括一个像素电路和一个发光元件，该像素电路分别与栅线、数据线以及发光元件连接，并用于基于来自栅线的栅极驱动信号和来自数据线的数据信号，驱动发光元件发光。GOA电路可以与显示面板中的栅线连接，并用于为栅线提供栅极驱动信号。
但是，因短沟道效应的存在，GOA电路中各个晶体管的阈值电压Vth会发生严重负向漂移(简称，负漂)。并且，为可靠驱动发光元件发光，一般要求GOA电路中各个晶体管的开态电流Ion较大，如此，GOA电路中每个晶体管的尺寸，如，宽长比(W/L)需要设置的较大，通常宽长比W/L为2000/6，不利于显示装置窄边框的实现。
为解决上述技术问题，本公开实施例提供了一种新的栅极驱动电路，该栅极驱动电路包括多个第一晶体管，其中至少一个第一目标晶体管包括与第一栅极金属层连接的第一遮光层。通过该设置方式，有效解决了第一目标晶体管的负漂问题，且该栅极驱动电路的设计有利于显示装置窄边框的实现。
以一个第一目标晶体管为例，图1示出了本公开实施例提供的一种第一目标晶体管的结构示意图。如图1所示，该第一目标晶体管可以包括：
位于衬底基板(base)00一侧的第一遮光层(light shield，LS)10，以及位于该第一遮光层10远离衬底基板00一侧的第一栅极(gate)金属层20和第一源漏极金属层30。
其中，该第一遮光层10可以由导电材料制成，且该第一遮光层10与第一 栅极金属层20可以连接。如此，可以看作该第一目标晶体管为双栅结构，且共形成上下两个导电沟道，使得该第一目标晶体管的阈值电压Vth可以正漂，即可以有效抑制第一目标晶体管的负漂现象。在Vth正漂的前提下，第一目标晶体管的开态电流Ion也会相应的增加。已知开态电流Ion的计算公式为：
Ion＝W*μ n*Cox(Vgs-Vth) 2/L，其中，W为沟道宽度，L为沟道长度，μ n为第一目标晶体管的载流子迁移率，Cox为第一目标晶体管的栅极绝缘层的电容。
基于开态电流Ion的计算公式可知，在通过设置第一遮光层10与第一栅极金属层20连接的方式增大Ion的前提下，可以相应的减小第一目标晶体管的尺寸。例如，可以减小第一目标晶体管的沟道宽度W和/或减小沟道长度L。
例如，假设未设置第一遮光层10时，为达到目标开态电流Ion，第一目标晶体管的宽长比W/L需要设置为2000/6。则在设置第一遮光层10后，可以在减小沟道长度L，如使得宽长比W/L由2000/6变为2000/5；或，减小沟道宽度W，使得宽长比W/L由2000/6变为1500/5的同时，依然达到上述目标开态电流Ion。如此，为窄边框的实现奠定了基础，即有利于显示装置窄边框的实现。
综上所述，本公开实施例提供了一种栅极驱动电路。由于该栅极驱动电路中的至少一个晶体管包括由导电材料制成的第一遮光层，且该第一遮光层与该晶体管的第一栅极金属层连接，因此形成了两个导电沟道，增大了开态电流，进而有效抑制了阈值电压的负漂。
可选的，结合图2，在本公开实施例中，第一源漏极金属层30可以包括第一源极(source)图案301和第一漏极(drain)图案302。
以未设置第一遮光层10，设置第一遮光层10与第一源极图案301连接，以及设置第一遮光层10与第一栅极金属层20连接为例，图3示出了该三种情况下，第一目标晶体管的阈值电压Vth和开态电流Ion的变化关系示意图。
其中，参考图3可以看出，设置第一遮光层10与第一源极图案301连接的第一目标晶体管的阈值电压Vth为0.03伏特(V)，对应的开态电流Ion约为30安培(A)。未设置第一遮光层10的第一目标晶体管的阈值电压Vth为0.59V，对应的开态电流Ion约为32A。设置第一遮光层10与第一栅极金属层20连接的第一目标晶体管的阈值电压Vth为0.08V，对应的开态电流Ion约为42A。如此可以进一步确定：采用本公开实施例的设置，相对于不设置第一遮光层10，或 设置第一遮光层10与第一源极图案301连接，第一目标晶体管的阈值电压Vth负漂程度更小，且开态电流Ion更大。
可选的，制作第一遮光层10的导电材料可以为金属材料。如此，第一遮光层也可以称为第一金属遮光层。通过设置金属材料作为导电材料，既可以可靠确保导电效果，且还可以实现对光线的有效遮挡，解决光照造成的负漂问题。
当然，该导电材料也可以为其他具有导电性能的材料，如，有机导电材料。本公开实施例对该导电材料不做限定。
可选的，该第一遮光层10的厚度可以大于厚度阈值。即，该第一遮光层10的厚度可以较大。如此，可以进一步确保对光线的有效遮挡。
可选的，图4是本公开实施例提供的另一种栅极驱动电路的结构示意图。如图4所示，第一目标晶体管还可以包括：有源(active，ACT)层40和栅绝缘(gate insulator，GI)层50。
其中，该有源层40、栅绝缘层50、第一栅极金属层20和第一源漏极金属层30可以沿远离第一遮光层10的方向依次层叠。即，本公开实施例记载的第一目标晶体管可以为顶栅结构的晶体管。
当然，第一目标晶体也不限于为顶栅结构。如，还可以为底栅结构的晶体管。在为底栅结构的晶体管时，可以在第一源漏极金属层30远离衬底基板00的一侧再设置一层金属层，并设置第一遮光层10与该增的金属层连接。
可选的，参考图4，在本公开实施例中，第一遮光层10在衬底基板00上的正投影可以覆盖有源层40在衬底基板00上的正投影。如此，可以进一步保证遮光效果较好。
可选的，继续参考图4，该第一目标晶体管还可以包括：缓冲(buffer)层60、层间介定(interlayer dielectric，ILD)层70和钝化层(Passivation，PVX)80。该层间介定层70也可以称为层间绝缘层。
其中，缓冲层60可以位于第一遮光层10和有源层40之间，层间介定层70可以位于第一源漏极金属层30和第一栅极金属层20之间，钝化层80可以位于第一源漏极金属层30远离层间介定层70的一侧。
可选的，继续参考图4，该钝化层80、缓冲层60和层间介定层70中可以具有第一过孔K1，钝化层80和层间介定层70中还可以具有第二过孔K2。第一目标晶体管还可以包括：第一连接部B1。
其中，第一连接部B1可以通过第一过孔(hole)K1与第一遮光层10连接，并可以通过第二过孔K2与第一栅极金属层20连接。该第一过孔K1和第二过孔K2也可以称为连接(connective，CNT)过孔。
例如，参考图4，第一连接部B1可以包括三部分B11、B12和B13，第一部分B11可以位于第一过孔K1内，并与第一遮光层10连接，第二部分B12可以位于第二过孔K2内，并与第一栅极金属层20连接，第三部分B13可以位于钝化层80中，并连接第一部分B11和第二部分B12。
可选的，结合图2和图4，有源层40可以包括第一导体化区域Q1和第二导体化区域Q2。层间介定层70中还可以具有第三过孔K3和第四过孔K4。第一源漏极金属层30可以包括第一源极图案301和第一漏极图案302。第一目标晶体管还可以包括：第二连接部B2和第三连接部B3。该第三过孔K3和第四过孔K4也可以称为ILD过孔。
其中，第二连接部B2的一端可以与第一源极图案301连接，另一端可以通过第三过孔K3连接至第一导体化区域Q1。第三连接部B3的一端可以与第一漏极图案302连接，另一端可以通过第四过孔K4连接至第二导体化区域Q2。
可选的，图5是本公开实施例提供的又一种栅极驱动电路的结构示意图。如图5所示，该栅极驱动电路中的多个第一晶体管可以包括：输入晶体管M1、复位晶体管M2、第一输出晶体管M3、第二输出晶体管M4、第一下拉控制晶体管M5、第二下拉控制晶体管M6、第三下拉控制晶体管M7、第四下拉控制晶体管M8、第五下拉控制晶体管M9、第一下拉晶体管M10、第二下拉晶体管M11、第三下拉晶体管M12和第四下拉晶体管M13。
其中，输入晶体管M1的栅极和第一极可以与输入端IN1连接，第二极可以与上拉节点P1连接。
例如，该输入晶体管M1可以用于在输入端IN1提供的输入信号控制下，向上拉节点P1传输输入信号，以为上拉节点P1充电。
第一输出晶体管M3的栅极可以与上拉节点P1连接，第一极可以与第一时钟信号端CLK1连接，第二极可以与移位输出端CR1连接。可选的，该移位输出端CR1可以与级联的后一级栅极驱动电路的输入端IN连接，用于驱动后一级栅极驱动电路工作，实现移位功能。该输入信号的电位可以为有效电位。
例如，该第一输出晶体管M3可以在上拉节点P1的电位控制下，向移位输 出端CR1传输第一时钟信号端CLK1提供的第一时钟信号。
第二输出晶体管M4的栅极可以与上拉节点P1连接，第一极可以与第二时钟信号端CLK2连接，第二极可以与驱动输出端OUT1连接。可选的，该输出端OUT1可以与显示面板中的栅线连接，并用于为栅线提供栅极驱动信号。
例如，该第二输出晶体管M4可以在上拉节点P1的电位控制下，向驱动输出端OUT1传输第二时钟信号端CLK2提供的第二时钟信号。
复位晶体管M2的栅极可以与复位信号端RST连接，第一极可以与第一下拉电源端VGL1连接，第二极可以与上拉节点P1连接。
例如，该复位晶体管M2可以在复位信号端RST提供的复位信号控制下，向上拉节点P1传输第一下拉电源端VGL1提供的第一下拉电源信号，以为上拉节点P1复位降噪。该第一下拉电源信号的电位可以为无效电位。
可选的，在晶体管为N型晶体管时，无效电位相对于有效电位可以为低电位。在晶体管为P型晶体管时，无效电位相对于有效电位可以为高电位。本公开实施例对此不作限定。
第一下拉控制晶体管M5的栅极和第一极均可以与下拉控制电源端VDD连接，第二极可以与第二下拉控制晶体管M6的栅极连接。
例如，该第一下拉控制晶体管M5可以在下拉控制电源端VDD提供的下拉控制电源信号控制下，向第二下拉控制晶体管M6的栅极传输该下拉控制电源信号。该下拉控制电源信号的电位可以为有效电位。
第二下拉控制晶体管M6的第一极可以与下拉控制电源端VDD连接，第二极可以与下拉节点P2连接。
例如，该第二下拉控制晶体管M6可以在下拉控制电源信号控制下，向下拉节点P2传输该下拉控制电源信号，以实现对下拉节点P2的控制。
第三下拉控制晶体管M7和第四下拉控制晶体管M8的栅极均可以与上拉节点P1连接，第三下拉控制晶体管M7和第四下拉控制晶体管M8的第一极可以均可以与第一下拉电源端VGL1连接，第三下拉控制晶体管M7的第二极可以与第二下拉控制晶体管M6的栅极连接，第四下拉控制晶体管M8的第二极可以与下拉节点P2连接。
例如，该第三下拉控制晶体管M7可以在上拉节点P1的电位控制下，向第二下拉控制晶体管M6的栅极传输第一下拉电源信号。该第四下拉控制晶体管 M8可以在上拉节点P1的电位控制下，向下拉节点P2传输第一下拉电源信号，以实现对下拉节点P2的控制。
第五下拉控制晶体管M9的栅极可以与级联的另一个栅极驱动电路的移位输出端连接，第一极可以与第一下拉电源端VGL1连接，第二极可以与下拉节点P2连接。可选的，图5示出的第五下拉控制晶体管M9的栅极与级联的前一个栅极驱动电路的移位输出端CR1(N-1)连接，N代表本级为第N级，且N为大于1的整数。
例如，该第五下拉控制晶体管M9可以在级联的另一个栅极驱动电路的移位输出端提供的信号控制下，向下拉节点P2传输第一下拉电源信号，以实现对下拉节点P2的控制。
第一下拉晶体管M10、第二下拉晶体管M11和第三下拉晶体管M12的栅极均可以与下拉节点P2连接，第一下拉晶体管M10和第二下拉晶体管M11的第一极均可以与第一下拉电源端VGL1连接，第三下拉晶体管M12的第一极可以与第二下拉电源端VGL2连接，第一下拉晶体管M10的第二极可以与上拉节点P1连接，第二下拉晶体管M11的第二极可以与移位输出端CR1连接，第三下拉晶体管M12的第二极可以与驱动输出端OUT1连接。
例如，该第一下拉晶体管M10可以在下拉节点P2的电位控制下，向上拉节点P1传输第一下拉电源信号，以实现对上拉节点P1的下拉降噪。该第二下拉晶体管M11可以在下拉节点P2的电位控制下，向移位输出端CR1传输第一下拉电源信号，以实现对移位输出端CR1的下拉降噪。该第三下拉晶体管M12可以在下拉节点P2的电位控制下，向驱动输出端OUT1传输第二下拉电源端VGL2提供的第二下拉电源信号，以实现对驱动输出端OUT1的下拉降噪。该第二下拉电源信号的电位也可以为无效电位。
第四下拉晶体管M13的栅极可以与另一个栅极驱动电路的移位输出端连接，第一极可以与第一下拉电源端VGL1连接，第二极可以与上拉节点P1连接。可选的，图5示出的第四下拉晶体管M13的栅极与级联的后一个栅极驱动电路的移位输出端CR1(N+1)连接。
例如，该第四下拉晶体管M13可以在另一个栅极驱动电路的移位输出端提供的信号控制下，向上拉节点P1传输第一下拉电源信号，以实现对上拉节点P1的下拉降噪。
再者，参考图5，该栅极驱动电路还可以包括存储电容C1。该存储电容C1的一端可以与上拉节点P1连接，另一端可以与驱动输出端OUT1连接。
可选的，本公开实施例记载的至少一个第一目标晶体管可以包括：第二输出晶体管M4、第二下拉晶体管M11和/或第三下拉晶体管M12。
因该第二输出晶体管M4是用于向栅线提供栅极驱动信号，第二下拉晶体管M11是用于为移位输出端CR1下拉降噪，第三下拉晶体管M12是用于为驱动输出端OUT下拉降噪，故该第二输出晶体管M4、第二下拉晶体管M11和第三下拉晶体管M12所需开态电流Ion相对较大，如此，通过设置该三者至少一个包括第一遮光层10，可以有效避免栅极驱动电路中晶体管的负漂现象。
例如，参考图5，其示出的至少一个第一目标晶体管为第二输出晶体管M4、第二下拉晶体管M11和第三下拉晶体管M12。从图5可以看出，第一遮光层10与第二输出晶体管M4的栅极、第二下拉晶体管M11的栅极以及第三下拉晶体管M12的栅极连接。
需要说明的是，栅极驱动电路不限于为图5示出的13T1C(即，13个晶体管和1个电容器)的结构，也可以为7T1C等其他结构，本公开实施例对此不做限定。此外，第一遮光层10也可以由绝缘材料制成，且在由绝缘材料制成时，该第一遮光层10不与任何层级结构连接。通过设置由绝缘材料制成的第一遮光层10，可以提高光照稳定性，且可以解决光照导致的负漂问题。
综上所述，本公开实施例提供了一种栅极驱动电路。由于该栅极驱动电路中的至少一个晶体管包括由导电材料制成的第一遮光层，且该第一遮光层与该晶体管的第一栅极金属层连接，因此形成了两个导电沟道，增大了开态电流，进而有效抑制了阈值电压的负漂。
图6是本公开实施例提供的一种栅极驱动电路的制造方法流程图，可以用于制造如图1、图2、图4或图5任一所示的栅极驱动电路。如图6所示，该方法可以包括：
步骤601、采用导电材料在衬底基板的一侧形成第一遮光层。
可选的，该导电材料可以为金属材料，可以采用构图工艺在提供的衬底基板上形成该第一遮光层。
步骤602、在第一遮光层远离衬底基板的一侧形成第一栅极金属层和第一源 漏极金属层。
然后，可以在形成第一遮光层的衬底基板上再继续采用构图工艺形成第一栅极金属层和第一源漏极金属层。并且设置第一遮光层与第一栅极金属层连接。
综上所述，本公开实施例提供了一种栅极驱动电路的制造方法。通过设置第一遮光层，并设置第一遮光层与第一栅极金属层连接，可以形成两个导电沟道，增大开态电流，进而可以有效抑制栅极驱动电路中晶体管阈值电压的负漂。
图7是本公开实施例提供的一种栅极驱动电路的制造方法流程图，可以用于制造如图1、图2、图4或图5任一所示的栅极驱动电路。如图7所示，该方法可以包括：
步骤701、采用导电材料在衬底基板的一侧形成第一遮光层。
在本公开实施例中，可以先提供一衬底基板作为载体，然后再采用构图工艺在该衬底基板的一侧形成第一遮光层。可选的，该构图工艺可以包括：涂胶、曝光、显影和刻蚀。该衬底基板可以为玻璃基板或者柔性基板。
示例的，该形成有第一遮光层10的衬底基板00可以参考图8所示结构。
步骤702、在第一遮光层远离衬底基板的一侧依次形成缓冲层、有源层和栅绝缘层。
在形成第一遮光层之后，首先，可以通过沉积工艺在第一遮光层远离衬底基板的一侧沉积一层缓冲层。然后，再通过沉积工艺在缓冲层远离第一遮光层的一侧沉积有源层图案，并通过构图工艺处理该有源层图案得到有源层。最后，再通过沉积工艺在有源层远离缓冲层的一侧沉积栅绝缘层图案，并通过构图工艺(如，干法构图工艺)处理该栅绝缘层图案得到栅绝缘层。如此，即得到依次层叠的缓冲层、有源层和栅绝缘层。
此外，在形成有源层后，可以对有源层的两侧进行导体化处理，形成导体化区域，便于后续连接。可选的，可以通过掺杂氦气(He)的等离子体(plasma)对有源层进行导体化处理。
示例的，该形成有缓冲层70的衬底基板00可以参考图9所示结构。该形成有有源层40的衬底基板00可以参考图10所示结构。该形成有栅绝缘层50的衬底基板00可以参考图11所示结构。该对有源层40进行导体化处理后的衬底基板00可以参考图12所示结构，参考图12可以看出，该有源层40具有第一导体化区域Q1和第二导体化区域Q2。
步骤703、在栅绝缘层远离有源层的一侧形成第一栅极金属层。
可选的，在形成栅绝缘层之后，可以继续通过沉积工艺在栅绝缘层远离有源层的一侧沉积形成栅极金属图案，并通过构图工艺(如，湿法构图工艺)处理该栅极金属图案得到第一栅极金属层。相应的，该结构也可以称为顶栅结构。
示例的，该形成有第一栅极金属层20的衬底基板00可以参考图13所示结构。
步骤704、在第一栅极金属层远离衬底基板的一侧形成层间介定层。
可选的，在形成第一栅极金属层之后，可以继续通过沉积工艺在第一栅极金属层远离衬底基板的一侧沉积形成层间介定层。
示例的，该形成有层间介定层70的衬底基板00可以参考图14所示结构。
步骤705、在层间介定层远离第一栅极金属层的一侧形成第一源极图案和第一漏极图案。
可选的，在形成层间介定层之后，可以继续通过沉积工艺在层间介定层远离第一栅极金属层的一侧沉积形成第一源漏极金属层，并通过构图工艺处理该第一源漏极金属层得到第一源极图案和第一漏极图案。
示例的，该形成有第一源极图案301和第一漏极图案302的衬底基板00可以参考图15所示结构。
步骤706、在第一源极图案和第一漏极图案远离层间介定层的一侧形成钝化层。
可选的，在形成第一源极图案和第一漏极图案之后，可以继续通过沉积工艺在第一源极图案和第一漏极图案远离层间介定层的一侧沉积形成钝化层。
示例的，该形成有钝化层80的衬底基板00可以参考图16所示结构。
步骤707、在钝化层、层间介定层和缓冲层中形成暴露第一遮光层的第一过孔。
可选的，在得到上述图16所示结构的衬底基板后，可以涂覆光刻胶，并通过曝光工艺形成暴露第一遮光层的第一过孔。
步骤708、在钝化层和层间介定层中形成暴露第一栅极金属层的第二过孔。
可选的，形成第二过孔的方法可以参考步骤707的描述，在此不再赘述。
此外，还可以继续通过步骤707的方式，在层间介定层中形成暴露第一导电区域Q1的第三过孔，以及暴露第二导电区域Q2的第四过孔。
示例的，形成有第一过孔K1、第二过孔K2、第三过孔K3和第四过孔K4的衬底基板00可以参考图17所示结构。
步骤709、在钝化层远离衬底基板的一侧形成第一连接部，第一连接部通过第一过孔与第一遮光层连接，并通过第二过孔与第一栅极金属层连接。
最后，可以形成第一连接部，通过第一过孔和第二过孔连接第一遮光层和第一栅极金属层。以及，可以再形成第二连接部，通过第三过孔连接第一源极图案和第一导体化区域，且形成第三连接部，通过第四过孔连接第一漏极图案和第二导体化区域。可选的，各个连接部均可以由导电材料制成，如，金属。
示例的，形成有第一连接部B1、第二连接部B2和第三连接部B3的衬底基板00可以参考图18所示结构。
需要说明的是，本公开实施例提供的制造方法的步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。如，可以先形成上述过孔，再形成源漏极图案，最后再形成钝化层。任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本发明的保护范围之内，因此不再赘述。
综上所述，本公开实施例提供了一种栅极驱动电路的制造方法。通过设置第一遮光层，并设置第一遮光层与第一栅极金属层连接，可以形成两个导电沟道，增大开态电流，进而可以有效抑制栅极驱动电路中晶体管阈值电压的负漂。
图19是本公开实施例提供的一种阵列基板的结构示意图。如图19所示，该阵列基板可以包括：具有显示区A1，以及围绕显示区A1的非显示区A2的衬底基板00。位于非显示区A2的栅极驱动电路100，该栅极驱动电路100可以为如图1、图2、图4或图5任一所示的栅极驱动电路100。以及位于显示区A1的多个像素电路200。且，每个像素电路200可以包括多个第二晶体管。
其中，多个第二晶体管中的至少一个第二目标晶体管可以包括：
位于衬底基板00一侧且依次层叠的第二遮光层01、第二栅极金属层02和第二源漏极金属层03，第二遮光层01由导电材料(如，金属材料)制成，且第二源漏极金属层03包括第二源极图案031和第二漏极图案032，第二遮光层01可以与第二源极图案031连接。
可选的，继续参考图19，其示出的像素电路200包括开关晶体管SW和驱 动晶体管DR，且包括第二遮光层01的第二目标晶体管为驱动晶体管DR。
需要说明的是，像素电路200中第二目标晶体管的制造方法可以参考上述图7所示方法，在此不再赘述。此外，图19仅示出了栅极驱动电路100中一个第一目标晶体管的结构，未示出其他晶体管结构。
图20是本公开实施例提供的一种显示装置的结构示意图。如图20所示，该显示装置可以包括：源极驱动电路300，以及如图19所示的阵列基板000。
该源极驱动电路300可以与阵列基板000中的数据线连接，该源极驱动电路300用于向数据线提供数据信号。如此，在上述栅极驱动电路100以及该源极驱动电路300的驱动下，阵列基板000中的像素能够可靠发光。
可选的，该显示装置可以为：有机发光二极管显示装置，液晶显示装置、手机、电脑、电视机、显示器、电子纸、数码相框或导航仪等任何具有显示功能的产品或部件。
应当理解的是，在本文中提及的“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种栅极驱动电路，所述栅极驱动电路包括：多个第一晶体管；所述多个第一晶体管中的至少一个第一目标晶体管包括：
    位于衬底基板一侧的第一遮光层，所述第一遮光层由导电材料制成；
    位于所述第一遮光层远离所述衬底基板一侧的第一栅极金属层和第一源漏极金属层；
    其中，所述第一遮光层与所述第一栅极金属层连接。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述导电材料为金属材料。
  3. 根据权利要求1所述的栅极驱动电路，其中，所述第一遮光层的厚度大于厚度阈值。
  4. 根据权利要求1至3任一所述的栅极驱动电路，其中，所述多个第一晶体管包括：输入晶体管、复位晶体管、第一输出晶体管、第二输出晶体管、第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管、第五下拉控制晶体管、第一下拉晶体管、第二下拉晶体管、第三下拉晶体管和第四下拉晶体管；
    所述输入晶体管的栅极和第一极与输入端连接，第二极与上拉节点连接；
    所述第一输出晶体管的栅极与所述上拉节点连接，第一极与第一时钟信号端连接，第二极与移位输出端连接；
    所述第二输出晶体管的栅极与所述上拉节点连接，第一极与第二时钟信号端连接，第二极与驱动输出端连接；
    所述复位晶体管的栅极与复位信号端连接，第一极与第一下拉电源端连接，第二极与所述上拉节点连接；
    所述第一下拉控制晶体管的栅极和第一极均与下拉控制电源端连接，第二极与所述第二下拉控制晶体管的栅极连接；
    所述第二下拉控制晶体管的第一极与所述下拉控制电源端连接，第二极与下拉节点连接；
    所述第三下拉控制晶体管和所述第四下拉控制晶体管的栅极均与所述上拉节点连接，所述第三下拉控制晶体管和所述第四下拉控制晶体管的第一极均与所述第一下拉电源端连接，所述第三下拉控制晶体管的第二极与所述第二下拉控制晶体管的栅极连接，所述第四下拉控制晶体管的第二极与所述下拉节点连接；
    所述第五下拉控制晶体管的栅极与级联的另一个栅极驱动电路的移位输出端连接，第一极与所述第一下拉电源端连接，第二极与所述下拉节点连接；
    所述第一下拉晶体管、所述第二下拉晶体管和所述第三下拉晶体管的栅极均与所述下拉节点连接，所述第一下拉晶体管和所述第二下拉晶体管的第一极均与所述第一下拉电源端连接，所述第三下拉晶体管的第一极与第二下拉电源端连接，所述第一下拉晶体管的第二极与所述上拉节点连接，所述第二下拉晶体管的第二极与所述移位输出端连接，所述第三下拉晶体管的第二极与所述驱动输出端连接；
    所述第四下拉晶体管的栅极与另一个栅极驱动电路的移位输出端连接，第一极与所述第一下拉电源端连接，第二极与所述上拉节点连接。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述至少一个第一目标晶体管包括：所述第二输出晶体管、所述第二下拉晶体管和/或所述第三下拉晶体管。
  6. 根据权利要求1至5任一所述的栅极驱动电路，其中，所述至少一个第一目标晶体管还包括：有源层和栅绝缘层；
    所述有源层、所述栅绝缘层、所述第一栅极金属层和所述第一源漏极金属层沿远离所述第一遮光层的方向依次层叠。
  7. 根据权利要求6所述的栅极驱动电路，其中，所述第一遮光层在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
  8. 根据权利要求6所述的栅极驱动电路，其中，所述至少一个第一目标晶体管还包括：缓冲层、层间介定层和钝化层；
    所述缓冲层位于所述第一遮光层和所述有源层之间；
    所述层间介定层位于所述第一源漏极金属层和所述第一栅极金属层之间；
    所述钝化层位于所述第一源漏极金属层远离所述层间介定层的一侧。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述钝化层、所述缓冲层和所述层间介定层中具有第一过孔，所述钝化层和所述层间介定层中还具有第二过孔；所述至少一个第一目标晶体管还包括：第一连接部；
    其中，所述第一连接部通过所述第一过孔与所述第一遮光层连接，并通过所述第二过孔与所述第一栅极金属层连接。
  10. 根据权利要求8所述的栅极驱动电路，其中，所述有源层包括第一导体化区域和第二导体化区域；所述层间介定层中具有第三过孔和第四过孔；所述第一源漏极金属层包括第一源极图案和第一漏极图案；所述至少一个第一目标晶体管还包括：第二连接部和第三连接部；
    其中，所述第二连接部的一端与所述第一源极图案连接，另一端通过所述第三过孔连接至所述第一导体化区域；
    所述第三连接部的一端与所述第一漏极图案连接，另一端通过所述第四过孔连接至所述第二导体化区域。
  11. 根据权利要求5所述的栅极驱动电路，其中，所述导电材料为金属材料；所述第一遮光层的厚度大于厚度阈值；
    所述至少一个第一目标晶体管还包括：有源层和栅绝缘层；所述有源层、所述栅绝缘层、所述第一栅极金属层和所述第一源漏极金属层沿远离所述第一遮光层的方向依次层叠；
    所述第一遮光层在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影；
    所述至少一个第一目标晶体管还包括：缓冲层、层间介定层和钝化层；所述缓冲层位于所述第一遮光层和所述有源层之间；所述层间介定层位于所述第一源漏极金属层和所述第一栅极金属层之间；所述钝化层位于所述第一源漏极金属层远离所述层间介定层的一侧；
    所述钝化层、所述缓冲层和所述层间介定层中具有第一过孔，所述钝化层 和所述层间介定层中还具有第二过孔；所述至少一个第一目标晶体管还包括：第一连接部；其中，所述第一连接部通过所述第一过孔与所述第一遮光层连接，并通过所述第二过孔与所述第一栅极金属层连接；
    所述有源层包括第一导体化区域和第二导体化区域；所述层间介定层中具有第三过孔和第四过孔；所述第一源漏极金属层包括第一源极图案和第一漏极图案；所述至少一个第一目标晶体管还包括：第二连接部和第三连接部；其中，所述第二连接部的一端与所述第一源极图案连接，另一端通过所述第三过孔连接至所述第一导体化区域；所述第三连接部的一端与所述第一漏极图案连接，另一端通过所述第四过孔连接至所述第二导体化区域。
  12. 一种栅极驱动电路的制造方法，所述方法包括：
    采用导电材料在衬底基板的一侧形成第一遮光层；
    在所述第一遮光层远离所述衬底基板的一侧形成第一栅极金属层和第一源漏极金属层；
    其中，所述第一遮光层与所述第一栅极金属层连接。
  13. 根据权利要求12所述的方法，其中，所述方法还包括：
    在所述第一遮光层远离所述衬底基板的一侧形成第一栅极金属层之前，在所述第一遮光层远离所述衬底基板的一侧依次形成缓冲层、有源层和栅绝缘层；
    在所述第一遮光层远离所述衬底基板的一侧形成第一栅极金属层之后，在所述第一栅极金属层远离所述衬底基板的一侧形成层间介定层；
    在所述第一遮光层远离所述衬底基板的一侧形成第一源漏极金属层之后，在所述第一源漏极金属层远离所述层间介定层的一侧形成钝化层；
    在所述钝化层、所述层间介定层和所述缓冲层中形成暴露所述第一遮光层的第一过孔；
    在所述钝化层和所述层间介定层中形成暴露所述第一栅极金属层的第二过孔；
    在所述钝化层远离所述衬底基板的一侧形成第一连接部，所述第一连接部通过所述第一过孔与所述第一遮光层连接，并通过所述第二过孔与所述第一栅极金属层连接。
  14. 一种阵列基板，所述阵列基板包括：
    具有显示区，以及围绕所述显示区的非显示区的衬底基板；
    位于所述非显示区的栅极驱动电路，所述栅极驱动电路为如权利要求1至11任一所述的栅极驱动电路；
    位于所述显示区的多个像素电路；
    其中，每个所述像素电路包括多个第二晶体管，所述多个第二晶体管中的至少一个第二目标晶体管包括：位于所述衬底基板一侧且依次层叠的第二遮光层、第二栅极金属层和第二源漏极金属层，所述第二遮光层由导电材料制成，且所述第二源漏极金属层包括第二源极图案和第二漏极图案，所述第二遮光层与所述第二源极图案连接。
  15. 根据权利要求14所述的阵列基板，其中，所述多个第二晶体管包括：开关晶体管和驱动晶体管；
    其中，所述至少一个第二目标晶体管包括所述驱动晶体管。
  16. 一种显示装置，所述显示装置包括：源极驱动电路，以及如权利要求14或15所述的阵列基板；
    所述源极驱动电路与所述阵列基板中的数据线连接，所述源极驱动电路用于向所述数据线提供数据信号。
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