WO2024044894A1 - 触控显示面板及显示装置 - Google Patents

触控显示面板及显示装置 Download PDF

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Publication number
WO2024044894A1
WO2024044894A1 PCT/CN2022/115535 CN2022115535W WO2024044894A1 WO 2024044894 A1 WO2024044894 A1 WO 2024044894A1 CN 2022115535 W CN2022115535 W CN 2022115535W WO 2024044894 A1 WO2024044894 A1 WO 2024044894A1
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WIPO (PCT)
Prior art keywords
touch
area
peripheral
layer
electrode
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PCT/CN2022/115535
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English (en)
French (fr)
Inventor
王威
陈军涛
文平
张毅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002886.6A priority Critical patent/CN117957656A/zh
Priority to PCT/CN2022/115535 priority patent/WO2024044894A1/zh
Publication of WO2024044894A1 publication Critical patent/WO2024044894A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Definitions

  • the present disclosure relates to the field of touch technology, and specifically to a touch display panel and a display device.
  • Touch display panels are an important part of terminal equipment such as mobile phones and smart watches. While displaying images, they can also realize human-computer interaction through touch operations. However, the touch accuracy of existing touch display panels still needs to be improved.
  • the present disclosure provides a touch display panel and a display device.
  • a touch display panel has a display area and a peripheral area located outside the display area.
  • the peripheral area includes a bending area away from the display area and a binding area, the binding area is located on the side of the bending area away from the display area;
  • the touch display panel includes:
  • the driving backplane includes at least part of the peripheral driving traces located in the peripheral area, and at least part of the peripheral driving traces passes through the bending area and extends into the binding area;
  • a plurality of light-emitting devices are provided on one side of the driving backplane and located in the display area.
  • the light-emitting devices include a first electrode, a light-emitting layer and a second electrode sequentially stacked in a direction away from the driving backplane;
  • the boundary of the second electrode extends to the peripheral area and is located on a side of the bending area away from the binding area;
  • a touch layer is provided on the side of the light-emitting device layer away from the driving backplane, and includes peripheral touch traces located in the peripheral area, and the peripheral touch traces pass through the bending area, Extending into the binding area, and at least part of the peripheral touch traces and at least part of the peripheral drive traces have an overlapping area;
  • a shielding layer is provided between the touch layer and the driving backplane, and is at least partially located between the boundary of the second electrode and the bending area; the shielding layer at least partially covers the overlapping area; the shielding layer and the first electrode or the second electrode receive the same signal.
  • the shielding layer and the first electrode are provided in the same layer.
  • the driving backplane includes:
  • a circuit layer is provided on one side of the substrate and includes at least part of the peripheral drive wiring
  • the shielding layer and the first electrode are provided on a surface of the flat layer away from the substrate, and the shielding layer is provided with an exhaust hole.
  • the number of the exhaust holes is multiple, and they are arranged in multiple rows and columns along the row direction and the column direction.
  • each of the peripheral touch traces includes a lead-out section extending to the binding area along the column direction, and each of the lead-out sections is spaced apart along the row direction, And all overlap with the shielding layer;
  • At least two lead-out sections are provided between two adjacent rows of exhaust holes.
  • the distance between two adjacent lead-out sections located between two adjacent rows of the exhaust holes is smaller than the distance between two adjacent lead-out sections located on both sides of one row of exhaust holes. Leading paragraph spacing.
  • each of the peripheral touch traces includes a lead-out section extending to the binding area along the column direction, and each of the lead-out sections is spaced apart along the row direction, And all overlap with the shielding layer;
  • At least a part of the lead-out sections and the exhaust holes in each column are alternately arranged along the row direction.
  • the distance between two adjacent lead-out sections is greater than the width of one row of exhaust holes.
  • At least part of the peripheral touch traces and at least part of the peripheral driving traces intersect between the bending area and the binding area, and the peripheral
  • the width of the area of the touch trace that intersects with the peripheral driving trace is smaller than the width of the region that does not intersect with the peripheral driving trace.
  • the difference between the width of the area where the peripheral touch traces do not intersect with the peripheral driving traces and the width of the area where the peripheral driving traces intersect is 4 ⁇ m - 5 ⁇ m.
  • the extending directions of the peripheral touch traces and the peripheral driving traces that cross each other are perpendicular.
  • the circuit layer includes a power bus located in the peripheral area and a plurality of pixel circuits and power lines located in the display area, one power line and one column of pixels The circuit is connected, and the power line is connected to the power bus; the shielding layer is connected to the power bus or the power line.
  • the circuit layer includes a semiconductor layer, a first gate insulating layer, a first gate electrode layer, a second gate insulating layer, and a third gate insulating layer sequentially stacked in a direction away from the substrate.
  • Two gate layers, a dielectric layer and a source and drain layer, the flat layer is located on the side of the source and drain layer away from the substrate; the power line and the power bus are located on the source and drain layer, so
  • the peripheral driving wiring is located in at least one layer of the first gate layer, the second gate layer and the source and drain layer.
  • the touch layer further includes a touch electrode located in the display area, and the touch electrode is provided on the same layer as the peripheral touch wiring;
  • the distance between the control trace and the boundary of the touch electrode closest to the peripheral touch trace is 20 to 22 times the distance between any two adjacent peripheral touch traces.
  • the touch electrodes include a plurality of first touch electrodes and a plurality of second touch electrodes, and each of the first touch electrodes is spaced apart along the row direction.
  • the first touch electrodes include a plurality of first electrode blocks spaced apart along the column direction and a transfer bridge connecting two adjacent first electrode blocks; each of the second touch electrodes is spaced apart along the column direction.
  • a second touch electrode includes a plurality of second electrode blocks connected in series along the row direction; a transfer bridge is arranged crosswise with a second touch electrode; the first electrode block, the third electrode block The two electrode blocks and the peripheral touch traces are located on the same electrode layer, and one of the peripheral touch traces is connected to one of the first touch electrode or the second touch electrode; the transfer bridge is located on On one side of the electrode layer, an insulating layer is provided between the transfer bridge and the electrode layer.
  • a touch display panel has a display area and a peripheral area located outside the display area.
  • the peripheral area includes a bending area away from the display area and a binding area, the binding area is located on the side of the bending area away from the display area;
  • the touch display panel includes:
  • the touch layer includes touch electrodes located in the display area and peripheral touch traces located in the peripheral area.
  • the peripheral touch traces pass through the bending area and extend into the binding area. ;
  • the distance between the peripheral touch trace closest to the touch electrode and the touch electrode closest to the peripheral touch trace is 20 times the distance between any two adjacent peripheral touch traces. to 22 times.
  • a touch display panel has a display area and a peripheral area located outside the display area.
  • the peripheral area includes a bending area away from the display area and a binding area, the binding area is located on the side of the bending area away from the display area;
  • the touch display panel includes:
  • the driving backplane includes at least part of the peripheral driving traces located in the peripheral area, and at least part of the peripheral driving traces passes through the bending area and extends into the binding area;
  • a plurality of light-emitting devices are provided on one side of the driving backplane and located in the display area.
  • the light-emitting devices include a first electrode, a light-emitting layer and a second electrode sequentially stacked in a direction away from the driving backplane;
  • the boundary of the second electrode extends to the peripheral area and is located on a side of the bending area away from the binding area;
  • a touch layer is provided on the side of the light-emitting device layer away from the driving backplane, and includes peripheral touch traces located in the peripheral area, and the peripheral touch traces pass through the bending area, Extend into the binding area, and at least part of the peripheral touch traces overlap with at least part of the peripheral drive traces;
  • At least part of the peripheral touch traces and at least part of the peripheral drive traces intersect between the bending area and the binding area, and the peripheral touch traces and the peripheral drive traces
  • the width of the intersecting area is smaller than the width of the area not intersecting with the peripheral driving traces.
  • the extending directions of the peripheral touch traces and the peripheral drive traces that cross each other are perpendicular.
  • a display device including the touch display panel described in any one of the above.
  • FIG. 1 is a top view of a touch display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a partial cross-sectional view of a display area of a touch display panel according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a driving backplane in an embodiment of the touch display panel of the present disclosure.
  • FIG. 4 is a schematic diagram of a pixel circuit in an embodiment of the touch display panel of the present disclosure.
  • FIG. 5 is a schematic diagram of a touch layer in an embodiment of the touch display panel of the present disclosure.
  • FIG. 6 is a partial cross-sectional view of the peripheral area of a touch display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a partial top view of the peripheral area of the touch display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a partial top view of the peripheral area of the touch display panel according to another embodiment of the present disclosure.
  • FIG. 9 is a partial top view of the lead-out area of the touch display panel according to one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of transition section intersection in an embodiment of the touch display panel of the present disclosure.
  • FIG. 11 is a partial cross-sectional view of a display area of a touch display panel according to another embodiment of the present disclosure.
  • FIG. 12 is a partial enlarged view of an electrode layer of a touch display panel according to an embodiment of the present disclosure.
  • FIG. 13 is a partial cross-sectional view of the peripheral area of a touch display panel according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the row direction and the column direction Y in this article are only two mutually perpendicular directions.
  • the row direction may be horizontal and the column direction Y may be vertical. However, it is not limited to this. If the touch display panel If rotation occurs, the actual orientation of the row and column directions Y may change.
  • overlap of feature A and feature B in this article means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially overlap.
  • Embodiments of the present disclosure provide a touch display panel.
  • the touch display panel has a display area AA and a peripheral area WA located outside the display area AA.
  • the peripheral area WA can be a continuous or continuous area surrounding the display area AA.
  • the shape of the peripheral area WA is not particularly limited.
  • the peripheral area WA may include a lead-out area FA that protrudes in a direction away from the display area AA along the column direction Y.
  • the lead-out area FA may include a bending area BA and a binding area CA distributed along the column direction Y.
  • the binding area CA is located in the bend.
  • the folding area BA is on the side away from the display area AA. By bending the bending area BA, the lead-out area FA can be bent to the backlight side of the touch display panel, that is, the side opposite to the light emitting direction.
  • the bonding area CA has at least one driver chip and a plurality of pins connected to the driver chip. It can be connected to a flexible circuit board through the pins of the bonding area CA, and the flexible circuit board can be bonded to a control circuit board. Determined, thereby realizing the connection between the touch display panel and the control circuit board, so as to control the touch display panel to display images and realize the touch function through the control circuit board.
  • the binding area CA may not be provided with a driver chip, but the driver chip may be provided on a flexible circuit board or a control circuit board and connected to the pins of the binding area CA to implement display and touch functions.
  • the touch display panel of the present disclosure may include a driving backplane BP, a light emitting device LD, a touch layer TSP and a shielding layer ES, where:
  • the driving backplane BP may include peripheral driving traces WBL located at least partially in the peripheral area WA, and at least part of the peripheral driving traces WBL passes through the bending area BA and extends into the bonding area CA.
  • the light-emitting device LD is provided on one side of the driving backplane BP, and includes a light-emitting device located in the display area AA.
  • the light-emitting device LD includes a second electrode CAT, a light-emitting layer EL and a second electrode CAT sequentially stacked in a direction away from the driving backplane BP.
  • Each light-emitting device LD shares a second electrode CAT, and the boundary of the second electrode CAT extends to the peripheral area WA and is located on the side of the bending area BA away from the binding area CA.
  • the touch layer TSP can be located on the side of the light-emitting device LD layer away from the driving backplane BP, and includes peripheral touch traces WTL located in the peripheral area WA.
  • the peripheral touch traces WTL pass through the bending area BA and extend to the bonding area.
  • the shielding layer ES is provided between the touch layer TSP and the drive backplane BP, and at least part of it is located on the second Between the boundary of the electrode CAT and the bending area BA.
  • the shielding layer ES at least partially covers the overlapping area, and the shielding layer ES partially overlaps the second electrode CAT; the shielding layer ES receives the same signal as the second electrode CAT or the second electrode CAT.
  • a shielding layer ES is provided between the touch layer TSP and the driving backplane BP.
  • the shielding layer ES partially overlaps the second electrode CAT, and is partially located at the boundary and bend of the second electrode CAT. between areas BA, and the shielding layer ES can receive the same signal as the second electrode CAT or the second electrode CAT, so that the peripheral touch trace WTL and the peripheral driving trace WBL can be isolated through the shielding layer ES to prevent peripheral driving
  • the signal of the trace WBL interferes with the signal of the peripheral touch trace WTL, thereby ensuring the normal realization of the touch function and improving the accuracy of the touch.
  • the driving backplane BP may include a driving circuit for driving each light-emitting device LD to emit light independently.
  • the driving circuit may include a pixel circuit PC and a peripheral circuit, wherein the number of the pixel circuit PC is multiple, and at least part of the pixel circuit PC is The pixel circuit PC may be disposed in the display area AA. Of course, a part of the pixel circuit PC may be located in the peripheral area WA.
  • Each pixel circuit PC can include multiple transistors and storage capacitors.
  • the channels of each transistor can be set on the same layer, and they can all use semiconductor materials such as polysilicon.
  • the pixel circuit PC can be a pixel circuit PC such as 3T1C or 7T1C.
  • nTmC means that a pixel circuit PC includes n transistors (indicated by the letter "T") and m capacitors (indicated by the letter "C").
  • the number of pixel circuits PC can be multiple, and the array distribution is in multiple rows and columns.
  • One pixel circuit PC can be connected to one light-emitting device LD. Of course, there can also be a situation where one pixel circuit PC is connected to multiple light-emitting devices LD. This article Only the one-to-one connection between the pixel circuit PC and the light-emitting device LD will be described as an example.
  • the pixel circuit PC may be a 7T1C structure, which may have 7 transistors and 1 capacitor, namely a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a write transistor The input transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7 and the storage capacitor Cst.
  • the driving backplane BP may also include gate lines, reset signal lines, data lines DAL, power lines VDL, etc., where the number of gate lines and reset signal lines is multiple, and They all pass through the display area AA along the row direction X and extend into the peripheral area WA, and a pixel circuit PC connects multiple gate lines and multiple reset signal lines.
  • Gate lines connected to the same pixel circuit PC may include first reset control lines, second reset control lines, scanning lines and light emitting control lines.
  • Reset signal lines connected to the same pixel circuit PC may include first reset signal lines and second reset control lines. Reset signal line.
  • Both the data line DAL and the power line VDL pass through the display area AA along the column direction Y and extend into the peripheral area WA.
  • One column of pixel circuits PC is connected to at least one data line DAL and a power supply line VDL.
  • the first electrode of the first reset transistor T1 is connected to the first reset signal line VIL1 for receiving the reset signal Vinit1, and the second electrode is connected to the gate electrode of the driving transistor T3 and the first plate of the storage capacitor Cst.
  • the first electrode of the compensation transistor T2 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the gate electrode of the driving transistor T3.
  • the first electrode of the writing transistor T4 is connected to the data line DAL for receiving the data signal DA, and the second electrode is connected to the first electrode of the driving transistor T3.
  • the first pole of the first light-emitting control transistor T5 and the second plate of the storage capacitor Cst are connected to the power line VDL for receiving the first power signal VDD, and the second pole is connected to the first pole of the driving transistor T3.
  • the first electrode of the second light emitting control transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the first electrode ANO of a light emitting device LD.
  • the first electrode of the second reset transistor T7 is connected to the second reset signal line VIL2 for receiving the second reset signal Vinit2, and the second electrode is connected to the second electrode of the second light emitting control transistor T6.
  • the second electrode CAT of the light emitting device LD may receive the second power signal VSS.
  • the gate of the first reset transistor T1 is connected to the first reset control line for inputting the first reset control signal RE1
  • the gate of the second reset transistor T7 is connected to the second reset control line.
  • the reset control line is connected and used to input the second reset control signal RE2.
  • the gates of the compensation transistor T2 and the writing transistor T4 are connected to the scan line for inputting the scan signal GA
  • the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control line for inputting the light-emitting control.
  • Signal EM
  • each transistor of the pixel circuit PC is a P-type low-temperature polysilicon transistor to explain its working principle:
  • the first reset control signal RE1 is a low-level signal
  • the first reset transistor T1 is turned on
  • the gate of the driving transistor T3 and the first plate of the storage capacitor Cst are written with the reset signal Vinit1
  • the N1 node is implemented Initialize to eliminate the influence of the data of the previous frame of image.
  • the writing transistor T4 and the compensation transistor T2 can be turned on, and the light-transmitting hole can be written to the gate of the driving transistor T3 and the first plate Cst1 of the storage capacitor Cst.
  • DA that is, writing the light-transmitting hole DA to the N1 node through the N3 node and the N2 node until the potential reaches Vdata+Vth.
  • Vdata is the voltage of the light-transmitting hole DA
  • Vth is the threshold voltage of the driving transistor T3.
  • the scanning signal GA of the writing transistor T4 and the compensation transistor T2 may be the same signal.
  • the second reset control signal RE2 is a low-level signal, causing the second reset transistor T7 to be turned on, and the second electrode CAT of the light-emitting device LD and the second pole of the second light-emitting control transistor T6 are written with the second reset signal Vinit2 , reset the N4 node to implement initialization, and further eliminate the influence of the data of the previous frame image.
  • the light-emitting control signal EM is a low-level signal
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on
  • the driving transistor T3 is the voltage Vdata+Vth stored in the storage capacitor Cst and the first power signal VDD.
  • the light-emitting device LD emits light.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the transistors all adopt P-type transistors as an example for description. Based on the description and teaching of this implementation method in this disclosure, those of ordinary skill in the art can easily think of using N-type transistors for at least some of the transistors in the PC structure of the pixel circuit in the embodiment of the present disclosure, without having to make creative efforts, that is, using Implementations of N-type transistors or combinations of N-type transistors and P-type transistors, therefore, these implementations are also within the protection scope of the embodiments of the present disclosure.
  • the peripheral circuit can be connected to the light-emitting device LD through the pixel circuit PC and apply the first power signal to the first electrode ANO of the light-emitting device LD.
  • the peripheral circuit can also be connected to the second electrode CAT of the light-emitting device LD, and Applying the second power signal VSS to the second electrode CAT, the current passing through the light-emitting device LD can be controlled by controlling the pixel circuit PC, thereby controlling the brightness of the light-emitting device LD.
  • the peripheral circuit may include a peripheral driving circuit GOA, which may include a gate driving circuit, a lighting control circuit, etc., and of course may also include other circuits. The specific structure of the peripheral circuit is not specifically limited here.
  • the driving backplane BP may also include a bus located in the peripheral area WA.
  • the bus may pass from the peripheral area WA through the bending area BA, extend to the lead-out area FA, and extend to the binding area CA, or be located in Within the lead-out area FA.
  • the bus may include a reset signal bus, a first power bus and a second power bus that may be spaced apart in a direction away from the display area AA.
  • the first reset signal line and the second reset signal line are both connected to the reset signal bus and are used to receive the first reset signal and the second reset signal.
  • the power line VDL can be connected to the first power bus for receiving the first power signal VDD
  • the second electrode CAT of each light-emitting device LD can be connected to the second power bus for receiving the second power line number VSS.
  • the gate drive circuit may include multiple cascaded gate shift register units, which may provide reset control signals and scan signals to the multi-row pixel circuit PC, thereby controlling the sequential turning on of the transistors, as described above
  • the scan line, the first reset control line and the second reset control line are all connected to the gate drive circuit.
  • a gate shift register unit may include multiple transistors and capacitors, which may be 8T2C, 10T2C or 12T2C, etc.
  • nTmC indicates that a pixel circuit PC includes n transistors (indicated by the letter “T”) and m capacitors (indicated by the letter “C”), and its specific structure is not specifically limited here.
  • Multiple gate shift register units are cascaded.
  • the first pole of the input transistor in the first-level gate shift register unit is connected to the input terminal.
  • the input terminal is used to receive the trigger signal as the input signal, while the other levels of gate shift registers
  • the input terminal in the unit is electrically connected to the output terminal of the upper-level gate shift register unit to receive the output signal output by the upper-level gate shift register unit as an input signal, thereby realizing a shift output for display.
  • the pixel circuit PC of area AA performs progressive scanning.
  • the driving backplane BP can also include peripheral driving traces WBL located in the peripheral area WA, and the peripheral driving traces WBL can extend through the bending area BA to In the lead-out area FA, and extends to the binding area CA, and can be connected to the driver chip in order to receive signals.
  • the peripheral drive line WBL may include a drive power line, a trigger signal line, a clock signal line, etc. connected to the gate shift register unit.
  • the drive power line includes a first driver for providing power to the gate shift register unit.
  • the power line, the second driving power line, and the trigger signal line are used to provide the above-mentioned trigger signal.
  • the clock signal line may include a first clock signal line and a second clock signal line, and is used to control the turn-on timing of at least part of the transistors.
  • the structure and specific working principle of the gate drive circuit are not particularly limited here.
  • the light-emitting control circuit may include multiple light-emitting shift register units cascaded along the column direction Y.
  • the structure and working principle of the light-emitting shift register unit are similar to the gate shift register unit, which can control the light-emitting control transistors of each row of pixel circuits PC in sequence. On and off.
  • the light-emitting shift register unit may be connected to the light-emitting control line and output the light-emitting control signal EM to the light-emitting control line.
  • the light-emitting shift register unit may be connected to the light-emitting control lines to which the two rows of pixel circuits PC are connected.
  • the light-emitting shift register unit can also be connected to multiple peripheral driving lines WBL. These peripheral driving lines WBL can include driving power lines, trigger signal lines, clock signal lines, etc., and their connection relationships will not be described in detail here. .
  • the pixel circuit PC may not include a light emission control transistor, and accordingly, the peripheral circuit may not include a light emission control circuit.
  • the driving backplane BP may include a substrate SU, a circuit layer CL and a flat layer PLN stacked on one side of the substrate SU, where:
  • the substrate SU can be a substrate for the driving backplane BP, which can carry the circuit layer CL.
  • the substrate SU can be a hard or flexible structure, and it can be a single-layer or multi-layer structure, which is not specifically limited here.
  • the circuit layer CL may include the above-mentioned driving circuit.
  • the transistors and capacitors of the pixel circuit PC and the peripheral circuit, as well as the wiring connecting the pixel circuit PC and the peripheral circuit, are all located in the circuit layer C.
  • the circuit layer CL may include a semiconductor layer SEL, a first gate insulating layer GI1, a first gate layer GA1, and a second gate insulating layer sequentially stacked in a direction away from the substrate SU.
  • GI2, second gate layer GA2, dielectric layer ILD and source and drain layer SD among which:
  • the semiconductor layer SEL may include a channel of each transistor and a doped region connecting at least part of the channel, through which the connection of part of the transistors can be realized.
  • the first gate layer GA1 may include gate lines such as a first plate of each capacitor, a scan line, a first reset control line, a second reset control line, and a light-emitting control line.
  • the second gate layer GAT2 may include a second plate of a storage capacitor, a first reset signal line, a second reset signal line, a reset signal bus line, and the like.
  • the source-drain layer SD may include a data line DAL, a power line VDL, a power bus line, and at least part of the peripheral driving lines WBL such as a trigger signal line, a driving power line, a clock signal line connected to the gate driving circuit.
  • the flat layer PLN may cover the circuit layer CL.
  • the flat layer PLN covers the source and drain layer SD.
  • the material of the flat layer PLN can be organic materials such as transparent resin, and the surface of the flat layer PLN facing away from the driving backplane BP is flat so that the light emitting device LD can be disposed thereon.
  • circuit layer CL may also include a passivation layer, which may cover the source and drain layer SD, and the flat layer PLN may cover the passivation layer.
  • the driving backplane BP may be provided with a first source-drain layer and a second source-drain layer on the side of the dielectric layer ILD away from the substrate SU, and power lines and data lines may be located on the second source-drain layer. Drain layer, the flat layer can cover the second source and drain layer.
  • the above-mentioned 7T1C pixel circuit can also adopt LTPO (LTPS+Oxide) technology.
  • the driving transistor T3, the writing transistor T4, and the second reset transistor T7 The first light-emitting control transistor T5 and the second light-emitting control transistor T6 can use P-type low-temperature polysilicon transistors; the first reset transistor T1 and the compensation transistor T2 can use N-type metal oxide transistors. Since P-type low-temperature polysilicon transistors have higher carrier mobility, they are conducive to realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio in order to obtain higher carrier mobility. Improve response speed.
  • the circuit layer CL may include the first semiconductor layer SEL, the first gate insulating layer GI1, the first gate layer GA1, the first insulating layer IL0, the second gate layer GA2, the second insulating layer IL1, and the second semiconductor layer CL.
  • the first semiconductor layer SEL may be disposed on one side of the substrate SU and includes a channel of the driving transistor T3, the writing transistor T4, the second reset transistor T7, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the pixel circuit. road.
  • the material of the first semiconductor layer SEL may be polysilicon.
  • the first gate insulating layer GI1 may cover the first semiconductor layer SEL.
  • the first gate layer GA1 may be disposed on a surface of the first gate insulating layer GI1 away from the substrate SU, and includes a first plate of the storage capacitor Cst.
  • the first insulation layer IL0 may cover the first gate layer GA1.
  • the second gate layer GA2 may be disposed on a surface of the first insulating layer IL0 away from the substrate SU, and includes a second plate of a storage capacitor.
  • the second insulating layer IL1 covers the second gate layer GA2, which may be a single-layer or multi-layer structure.
  • the second semiconductor layer IGL may be disposed on a surface of the second insulating layer IL1 away from the substrate SU, and includes channels of the first reset transistor T1 and the compensation transistor T2.
  • the material of the second semiconductor layer IGL may include semiconductor metal oxides such as indium gallium zinc oxide (IGZO).
  • the second gate insulating layer GI2 may cover the second semiconductor layer IGL.
  • the third gate layer GA3 may be disposed on a surface of the third gate insulating layer GI2 away from the substrate SU.
  • the third insulating layer IL2 may cover the third gate layer GA3, which may be a single-layer or multi-layer structure.
  • the first source and drain layer SD1 may be disposed on a surface of the third insulating layer IL2 away from the substrate SU.
  • the first planarization layer PLN1 may be disposed on a side of the first source and drain layer SD1 away from the substrate SU.
  • the second source and drain layer SD2 may be disposed on the surface of the first planar layer PLN1 away from the substrate SU.
  • the second flat layer PLN2 is the flat layer PLN mentioned above.
  • the second flat layer PLN2 covers the second source and drain layer SD2, and its material can be an insulating material such as resin.
  • the light emitting device LD may be disposed on a side of the second planar layer PLN2 away from the substrate SU.
  • a light-shielding layer BSM may be provided between the substrate SU and the first semiconductor layer SEL, which may be made of light-shielding metal or other materials, and may be a single-layer or multi-layer structure. At least part of the light-shielding layer BSM may overlap with at least part of the channel region of the transistor to block light irradiating the transistor to stabilize the electrical characteristics of the transistor. Furthermore, the light-shielding layer BSM can be covered by an insulating buffer layer BUF, and the first semiconductor layer SEL can be provided on the surface of the buffer layer BUF facing away from the substrate SU.
  • the buffer layer BUF may have a single-layer or multi-layer structure, and its material may include insulating materials such as silicon nitride and silicon oxide.
  • the light emitting device LD can be disposed on a surface of the flat layer PLN (the second flat layer PLN2) away from the substrate SU, and is connected to the pixel circuit PC.
  • the light-emitting device LD may be an OLED (organic light-emitting diode), a QLED (quantum dot light-emitting diode), a Micro LED or a Mini LED, etc., and may include a second electrode CAT, a second electrode CAT and a second electrode located between the second electrode CAT and the second electrode The luminescent layer EL between CAT, where:
  • the first electrode ANO can be disposed on the surface of the circuit layer CL away from the substrate SU, for example, the flat layer PLN is on the surface away from the substrate SU.
  • the light-emitting layer EL can include a hole injection layer and a hole stacked in a direction away from the driving backplane BP. Transport layer, luminescent material layer, electron transport layer and electron injection layer.
  • Each light-emitting device LD can share the second electrode CAT, that is to say, the second electrode CAT can be a continuous whole-layer structure, and the second electrode CAT can extend to the peripheral area WA and can be connected to the second power bus to receive
  • the second power signal VSS and the first electrode ANO are distributed in an array to ensure that each light-emitting device LD can emit light independently.
  • a pixel definition layer PDL can be provided on the surface where the first electrode ANO is provided, which can have openings exposing each first electrode ANO, and the light-emitting layer EL is connected to the first electrode ANO in the opening.
  • One electrode ANO is stacked.
  • Each light-emitting device LD can at least share a light-emitting material layer, so that the light-emitting color of each light-emitting device LD is the same.
  • a color film layer can be provided on the side of the light-emitting device LD away from the substrate SU. Through the color film layer The filter part corresponding to each light-emitting device LD realizes color display.
  • the light-emitting material layers of each light-emitting device LD can also be made independent, so that the light-emitting device LD can directly emit monochromatic light, and the light-emitting colors of different light-emitting devices LD can be different, thereby achieving color display.
  • the display panel can also include an encapsulation layer TFE, which can cover the light-emitting device LD to protect the light-emitting device LD and prevent external water and oxygen from corroding the light-emitting device LD.
  • the encapsulation layer TFE can be encapsulated by thin film encapsulation, which can include a first inorganic layer, an organic layer and a second inorganic layer, wherein the first inorganic layer covers the light-emitting device LD, and the organic layer can be disposed on the third inorganic layer.
  • An inorganic layer faces away from the surface of the driving backplane BP, and the boundary of the organic layer is limited to the inside of the boundary of the first inorganic layer.
  • the boundary of the orthographic projection of the organic layer on the driving backplane BP can be located in the peripheral area WA to ensure that the organic layer can Cover each light emitting device LD.
  • the second inorganic layer can cover the organic layer and the first inorganic layer that is not covered by the organic layer, can block the intrusion of water and oxygen through the second inorganic layer, and achieve planarization through the flexible organic layer.
  • the touch layer TSP can be disposed on the side of the encapsulation layer TFE away from the substrate. For example, it can be directly disposed on the surface of the encapsulation layer TFE away from the substrate SU.
  • the touch layer TSP may adopt a mutual capacitance structure.
  • the touch layer TSP may include a plurality of touch electrodes located in the display area AA, and the touch electrode may include a first touch electrode.
  • the first touch electrodes Tx and the plurality of second touch electrodes Rx are provided at intervals along the row direction X, and the second touch electrodes Rx are spaced apart along the column direction Y.
  • Both the first touch electrode Tx and the second touch electrode Rx may include a plurality of electrode blocks connected in series, wherein any first touch electrode Tx may include a plurality of first electrode blocks Txc connected in series along the column direction Y, where Two adjacent first electrode blocks Txc in the column direction Y are connected in series through a transfer bridge BR.
  • Any second touch electrode Rx may include a plurality of second electrode blocks Rxc connected in series along the row direction X, and two adjacent second electrode blocks Rxc may be connected in series through a connecting portion Rxo.
  • Each of the first electrode blocks Txc and the second electrode blocks Rxc are distributed in an array, and at least a part of the first electrode blocks Txc is adjacent to different second electrode blocks Rxc in two different directions intersecting the row direction X and the column direction Y. Accordingly, at least a portion of the second electrode blocks Rxc are arranged adjacent to different first electrode blocks Txc in two different directions intersecting the row direction X and the column direction Y.
  • the edges of the first electrode block Txc and the second electrode block Rxc can have interdigitated fingers spaced apart along the circumferential direction.
  • a part of the interdigitals of the first electrode block Txc may be located between a part of the interdigitals of the second electrode block Rxc, but not in contact with each other, so that the The interdigitated fingers of one electrode block Txc and the interdigitated fingers of the second electrode block Rxc are alternately arranged at intervals.
  • the interdigitated fingers FI can make the extension trajectory of the gap between the first electrode block Txc and the second electrode block Rxc more tortuous. Without increasing the area of the first electrode block Txc and the second electrode block Rxc, the area facing each other can be increased, which is beneficial to increasing the capacitance between the two and improving the sensitivity of the inductive touch operation.
  • a capacitance can be formed between any adjacent first electrode block Txc and the second electrode block Rxc.
  • the capacitance at the touch position can change.
  • the change in the sensing capacitance corresponds to the first touch.
  • the control electrode Tx and the second touch electrode Rx can determine the touch position, and the detailed principle will not be described in detail here.
  • each of the above-mentioned electrode blocks and the connection portion Rxo can be located on the same electrode layer, and the electrode layer can be formed simultaneously through a patterning process. That is to say, the electrode layer TMB includes the first electrode block Txc and the second touch Electrode Rx.
  • the transfer bridge BR can be located on one side of the electrode layer TMB. That is, the transfer bridge BR and the electrode layer TMB are in different layers.
  • an insulating layer IN is provided between the transfer bridge BR and the electrode layer TMB, thereby being separated.
  • the first touch electrode Tx can cross with the second touch electrode Rx at the transfer bridge BR.
  • the transfer bridge BR can cross with the connector Rxo.
  • the transfer bridge BR may be connected to the first electrode block Txc through a via hole penetrating the insulation layer IN.
  • each transfer bridge BR can be provided on the surface of the encapsulation layer TFE away from the substrate SU, and can be formed at the same time.
  • Each transfer bridge BR has the same thickness and the same material. , so that they can be formed simultaneously.
  • the insulation layer IN can cover each transfer bridge BR.
  • the electrode layer TMB can be disposed on the surface of the insulating layer IN facing away from the substrate SU, and each transfer bridge BR can be connected to a first electrode block Txc through one or more via holes penetrating the insulating layer IN.
  • Both the transfer bridge BR and the electrode layer TMB can be single-layer or multi-layer conductive structures.
  • the transfer bridge BR can include two outer layers and an intermediate layer located between the two outer layers.
  • the material of the outer layer It can be titanium, and the material of the middle layer can be aluminum, that is, the transfer bridge BR has a Ti/Al/Ti structure; or the material of the outer layer can be indium tin oxide (ITO), and the material of the middle layer can be aluminum, that is,
  • the adapter bridge BR is an ITO/Ag/ITO structure.
  • the electrode layer TMB has a multi-layer structure, it can also be a Ti/Al/Ti structure or an ITO/Ag/ITO structure.
  • the material of the insulating layer IN can be silicon nitride. Of course, it can also be other inorganic insulating materials or organic insulating materials such as silicon oxide, silicon nitride oxide, etc.
  • the touch layer TSP may also include a buffer layer TBU and a protective layer TOC, where the buffer layer TBU may serve as the base of the touch layer TSP, which may be disposed on
  • the encapsulation layer TFE is away from the surface of the substrate SU, and its material may include insulating materials such as silicon nitride and silicon oxide.
  • the transfer bridge BR can be set on the surface of the buffer layer TBU facing away from the substrate SU.
  • the protective layer TOC can cover the electrode layer TMB and the area of the insulating layer IN that is not covered by the electrode layer TMB.
  • the protective layer TOC is used to protect the electrode layer TMB, and its material It can be transparent insulating materials such as polyimide (PI) or optical glue.
  • the first touch electrode Tx and the second touch electrode Rx can both have a mesh structure formed by multiple grid lines. Each grid line can extend along a straight line, but the direction Can be different.
  • the touch layer TSP may also adopt a self-capacitance structure.
  • the touch layer TSP may include a plurality of touch electrodes located on the same electrode layer TMB, and the touch electrode arrays are distributed and interconnected with each other. Interval settings. Each touch electrode and ground form a self-capacitance.
  • the capacitance of the finger will be superimposed on the self-capacitance of the touch electrode, causing the capacitance to increase.
  • the position of the touch point is determined, that is, the position of the touch electrode corresponding to the touch point.
  • the electrode layer TMB in the above embodiments may be a mesh structure surrounded by channel lines TC, with multiple mesh holes.
  • each mesh TH is surrounded by multiple channel lines TC.
  • the light-emitting device LD can correspond to the mesh TH, thereby reducing the light blocking by the electrode layer TMB.
  • the shape of the mesh TH can be rhombus, rectangle, pentagon, hexagon and other polygons.
  • the touch layer TSP may also include multiple peripheral touch traces WTL.
  • the peripheral touch traces WTL may be located on the electrode layer TMB, and a peripheral touch trace WTL may be connected to a touch electrode.
  • the first touch electrode Tx or the second touch electrode Rx is connected in a mutual capacitive structure.
  • it can also be a touch electrode in a self-capacitive structure.
  • the peripheral touch trace WTL can extend through the bending area BA into the lead-out area FA, and extend into the bonding area CA, and be connected to a driver chip.
  • a driver chip Of course, if there is no driver chip in the bonding area CA, It can also be connected to an external driver chip through the pins in the bonding area CA.
  • the touch electrodes can receive/send touch signals through the peripheral touch wires WTL.
  • the first touch electrode Tx can be used as a driving electrode for receiving the driving signal
  • the second touch electrode Rx can be used as a sensing electrode for outputting the sensing signal.
  • the functions of the first touch electrode Tx and the second touch electrode Rx are interchangeable.
  • touch signals are received/sent through touch electrodes in a self-capacitive structure.
  • each peripheral touch trace WTL located in the lead-out area FA can be divided into two touch lead-out parts WTS and one touch lead-out part WTS along the row direction X. Both include a part of the peripheral touch trace WTL located in the lead-out area FA.
  • the two touch lead-out parts WTS may be arranged symmetrically with respect to a straight line extending along the column direction Y.
  • a touch lead-out part WTS includes a lead-out section WTL1, a transition section WTL2 and a binding section WTL3 distributed along the column direction Y.
  • the transition section WTL2 can be connected between the lead-out section WTL1 and the binding section WTL3, and the lead-out section WTL1 can be connected to the peripheral
  • the touch trace WTL is connected to the part outside the lead-out area FA, and the bonding section WTL3 can be extended to the bonding area CA and connected to the driver chip or pin in the bonding area CA.
  • the lead-out section WTL1 and the binding section WTL3 both extend along the column direction Y, and the extension direction of the transition section WTL2 forms a certain angle with the column direction Y, so that it is different from the extension direction of the lead-out section WTL1 and the binding section WTL3.
  • the binding section WTL3 of the two touch lead-out parts WTS is located between the two lead-out sections WTL1 in the row direction X.
  • At least a part of the peripheral driving wiring WBL located in the lead-out area FA can also be divided into two driving lead-out parts WBS along the row direction X.
  • Each driving lead-out part WBS includes a part of the peripheral driving wiring WBL located in the lead-out area Area FA part.
  • the two touch lead-out parts WTS may be arranged symmetrically with respect to a straight line extending along the column direction Y.
  • a driving lead-out part WBS includes a lead-out section WBL1, a transition section WBL2 and a binding section WBL3 distributed along the column direction Y.
  • the transition section WBL2 can be connected between the lead-out section WBL1 and the binding section WBL3, and the lead-out section WBL1 can be connected to the peripheral
  • the driving trace WBL is connected to the part outside the lead-out area FA, and the bonding section WBL3 can be used to connect with the driver chip or pin in the bonding area CA.
  • the lead-out section WBL1 and the binding section WBL3 both extend along the column direction Y, and the extension direction of the transition section WBL2 forms a certain angle with the column direction Y, so that it is different from the extension direction of the lead-out section WBL1 and the binding section WBL3.
  • the lead-out section WBL1 of the above-mentioned two driving lead-out parts WBS is located between the two binding sections WBL3 in the row direction X.
  • the above-mentioned peripheral driving wiring WBL including the driving lead-out part WBS may include peripheral driving wiring WBL connected to the gate driving circuit, such as a clock signal line, a driving power supply line, a trigger signal line, etc., and of course, may also include connecting a light emitting control circuit.
  • the lead-out section WBL1 of the two drive lead-out parts WBS is located between the lead-out sections WTL1 of the two touch lead-out parts WTS, and the binding section WTL3 of the two touch lead-out parts WTS is located between the binding sections WBL3 of the two drive lead-out parts WBS.
  • the transition section WBL2 of the two drive lead-out parts WBS and the transition section WTL2 of the two touch lead-out parts WTS are intersected in a one-to-one correspondence, that is, the orthographic projection of the transition section WTL2 of the drive lead-out part WBS on the substrate SU is the same as
  • the orthographic projections of the transition section WTL2 of a touch lead-out part WTS on the substrate SU intersect, and the angle between the extension directions of the intersecting transition sections WTL2 and WBL2 can be 90°, that is, the extension directions of the two are perpendicular, that is, they are orthogonal projections. pay.
  • the included angle can also be other angles.
  • each light-emitting device LD shares the second electrode CAT, so that the second electrode CAT is a continuous whole-layer structure, and its boundary may be located in the peripheral area WA, and There is an overlapping area with part of the peripheral driving traces WBL and the peripheral touch traces WTL, that is, the orthographic projections of the two on the substrate SU have an overlapping area. Since the second power supply signal VSS is a constant voltage signal, it can pass through the second The electrode CAT acts as a shield between the driving backplane BP and the touch layer TSP, reducing the interference of the signal of the peripheral driving line WBL on the signal of the peripheral touch line WTL, and improving the accuracy of touch.
  • the boundary of the second electrode CAT is located between the bending area BA and the display area AA, and has a certain distance from the bending area BA. In this way, for at least part of the As for the peripheral touch trace WTL, its portion between the second electrode CAT and the bending area BA does not overlap with the second electrode CAT, so it is difficult to use the second electrode CAT to shield the signal driving the backplane BP.
  • a shielding layer ES can be provided between the driving backplane BP and the touch layer TSP.
  • the shielding layer ES is located in the bending area BA away from the display area AA. side, and the shielding layer ES overlaps with the overlapping area of part of the peripheral touch traces WTL and the peripheral driving traces WBL, that is, covering the overlapping area. That is to say, the orthographic projections of the shielding layer ES, the peripheral touch traces WTL and the peripheral drive traces WBL on the substrate SU have overlapping areas.
  • the shielding layer ES also partially overlaps the second electrode CAT, and the shielding layer ES partially overlaps with the second electrode CAT.
  • the shielding layer ES can be connected to the second electrode CAT or the second electrode CAT in order to receive the constant voltage first power signal VDD or the second power signal VSS, thereby playing a shielding role.
  • the shielding layer ES is connected to the second electrode CAT,
  • the two electrodes CAT overlap, so they can be connected through via holes in the overlapping area to transmit the second power signal VSS to the shielding layer ES.
  • the shielding layer ES can be connected to the second electrode CAT or located at the source.
  • the power line or power bus of the drain layer SD is connected, so that the first power signal VDD can be transmitted to the shielding layer ES.
  • the pixel definition layer PDL can extend to a surface of the shielding layer ES away from the substrate and cover the shielding layer ES.
  • the shielding layer ES and the second electrode CAT can be arranged on the same layer, so that the second electrode CAT and the shielding layer ES can be formed simultaneously through the same process.
  • the shielding layer ES and the second electrode CAT are provided on the surface of the flat layer PLN away from the substrate SU. Since the flat layer PLN is an organic material, gas will be generated during the manufacturing process. Therefore, in order to facilitate exhaust and prevent the gas from causing the shielding layer ES to bulge, as shown in Figure 7 and Figure 8, an exhaust hole can be opened in the shielding layer ES.
  • the pixel definition layer PDL can fill the exhaust hole GH, and the buffer layer TBU and the insulating layer of the touch layer TSP can also extend to the side of the shielding layer ES away from the substrate.
  • the number of the exhaust holes GH is multiple, and they are arranged in multiple rows and columns along the row direction X and the column direction Y.
  • the exhaust holes GH can be located in the lead-out section WTL1 in a staggered arrangement. For example:
  • At least two lead-out sections WTL1 are provided between two adjacent rows of exhaust holes GH, and the two adjacent lead-out sections WTL1 between two adjacent rows of exhaust holes GH are There is no vent hole GH between segments WTL1. Furthermore, the distance between two adjacent rows of lead-out sections WTL1 located between two adjacent rows of exhaust holes GH is smaller than the distance between two adjacent rows of lead-out sections WTL1 located on both sides of one row of exhaust holes GH.
  • one row of exhaust holes The spacing between two adjacent lead-out sections WTL1 on both sides of the hole GH is S2, the spacing between two adjacent lead-out sections WTL1 between two adjacent rows of exhaust holes GH is S3, S2 is greater than S3, and the width of one row of exhaust holes GH
  • the distance S3 between adjacent two rows of exhaust holes GH is 13-14 ⁇ m, such as 13.2 ⁇ m. That is to say, each lead-out section WTL1 is not equally spaced.
  • the exhaust holes GH may be located between two rows of lead-out sections WTL1 with a larger distance. No exhaust holes GH may be provided between two lead-out sections WTL1 with a smaller distance.
  • the lead-out sections WTL1 and each column of exhaust holes GH are alternately arranged along the row direction X, and a lead-out section can be provided between two adjacent columns of exhaust holes GH.
  • a row of exhaust holes GH can be provided between two adjacent lead-out sections WTL1.
  • the distance S1 between two adjacent lead-out sections WTL1 may be greater than the width of a row of exhaust holes GH, and the distance S1 may be 29 ⁇ m-30 ⁇ m, such as 29.2 ⁇ m.
  • the lead-out section WTL1 may include a first sub-section WTL11 , a second sub-section WTL12 and a third sub-section WTL13 distributed along the column direction Y.
  • the first sub-section WTL11 is distributed along the column direction Y.
  • the segment WTL11 can be connected to the part of the peripheral touch trace WTL located outside the lead-out area FA, the third sub-segment WTL13 is connected to the transition segment WTL2, and the second sub-segment WTL12 is connected between the first sub-segment WTL11 and the third sub-segment WTL13 .
  • the spacing between two adjacent third sub-sections WTL13 can be defined as the spacing S1 between two adjacent lead-out sections WTL1.
  • the spacing S11 between two adjacent first sub-sections WTL11 is smaller than the spacing S1 between two adjacent second sub-sections WTL12.
  • the width of the transition section WTL2 can be set so that the transition section WTL2 and the transition section WBL2 intersect The width of the area is smaller than the uncrossed area, which can reduce parasitic capacitance and reduce the interference of the peripheral drive line WBL on the peripheral touch line WTL. That is to say, the width W2 of the region of the peripheral touch trace WTL that intersects the peripheral drive trace WBL can be made smaller than the width W1 of the region that does not intersect the peripheral drive trace WBL.
  • the difference between the width W1 of the area where the peripheral touch line WTL does not intersect with the peripheral driving line WBL and the width W2 of the area where it intersects the peripheral driving line WBL can be 4 ⁇ m-5 ⁇ m, such as 4.5 ⁇ m.
  • the width of the area where the peripheral touch trace WTL does not intersect with the peripheral drive trace WBL is 16 ⁇ m-17 ⁇ m, such as 16.5 ⁇ m
  • the width difference between the region where it intersects with the peripheral drive trace WBL is 11 ⁇ m-13 ⁇ m, such as 12 ⁇ m. .
  • the peripheral touch trace WTL and the touch electrode closest to the peripheral touch trace WTL can be The distance between the boundary of the touch electrode Tx and the second touch electrode Rx) is limited to reduce mutual interference between the signals of the peripheral touch trace WTL and the touch electrode.
  • the distance K1 between the boundary of the peripheral touch trace WTL closest to the touch electrode and the boundary of the touch electrode closest to the peripheral touch trace WTL can be The distance between traces WTL is 20 times to 22 times K2, for example:
  • the distance K2 between any two adjacent peripheral touch traces WTL may be 4.5 ⁇ m-5 ⁇ m, and the distance between the peripheral touch trace WTL and the touch electrode closest to the peripheral touch trace WTL is The distance K1 of the boundary is 90 ⁇ m-110 ⁇ m, such as 100 ⁇ m, so that the signals of the peripheral touch traces WTL and the touch electrodes do not interfere with each other.
  • inventions of the present disclosure also provide a touch display panel, which can be used to reduce mutual interference between signals of peripheral touch traces WTL and touch electrodes.
  • the touch display panel may have a display area AA and a peripheral area WA located outside the display area.
  • the peripheral area WA includes a bending area BA far away from the display area and a binding area.
  • the binding area CA is located away from the bending area BA away from the display area.
  • the touch display panel may include a touch layer TSP, which may include touch electrodes located in the display area AA and peripheral touch traces WTL located in the peripheral area WA, and the peripheral touch traces WTL pass through the bending area BA , extending into the binding area CA.
  • the distance K1 between the boundary of the peripheral touch trace WTL closest to the touch electrode and the boundary of the touch electrode closest to the peripheral touch trace WTL is 20 times the distance K2 between any two adjacent peripheral touch traces WTL. to 22 times.
  • the above solutions such as the shielding layer ES, the exhaust hole GH, and the intersection of the peripheral touch trace WTL and the peripheral drive trace WBL may not be used, and only any phase
  • the distance K2 between two adjacent peripheral touch traces WTL can be 4.5 ⁇ m-5 ⁇ m, and the distance K1 between the boundary of the peripheral touch trace WTL and the touch electrode closest to the peripheral touch trace WTL is 90 ⁇ m-110 ⁇ m, for example 100 ⁇ m. , so that the signals of the peripheral touch trace WTL and the touch electrode will not interfere with each other.
  • the above solutions such as the shielding layer ES and the exhaust hole GH can also be used.
  • the touch display panel of the above embodiments please refer to the touch display panel of the above embodiments, which will not be described again here.
  • Embodiments of the present disclosure also provide a touch display panel that can reduce the parasitic capacitance and the impact of the peripheral drive wiring WBL on the peripheral touch by making the width of the area where the transition section WTL2 and the transition section WBL2 intersect smaller than the non-intersecting area.
  • a touch display panel that can reduce the parasitic capacitance and the impact of the peripheral drive wiring WBL on the peripheral touch by making the width of the area where the transition section WTL2 and the transition section WBL2 intersect smaller than the non-intersecting area.
  • at least part of the peripheral touch traces WTL and at least part of the peripheral driving traces WBL intersect between the bending area BA and the binding area CA, and the peripheral touch traces WTL intersect with the peripheral driving traces WBL.
  • the width of the area is smaller than the width of the area that does not intersect the peripheral driving trace WBL.
  • the difference between the width of the area where the peripheral touch trace WTL does not intersect with the peripheral drive trace WBL and the width of the region where the peripheral touch trace WTL intersects with the peripheral drive trace is 4 ⁇ m-5 ⁇ m.
  • the extending directions of the peripheral touch traces WTL and the peripheral driving traces WBL that cross each other are perpendicular. The specific content has been described in the above embodiments, and reference may be made to the touch display panel in the above embodiments, which will not be described again here.
  • the present disclosure also provides a display device, which may include the touch display panel of any of the above embodiments.
  • the touch display panel is a touch display panel according to any of the above embodiments.
  • the display device of the present disclosure can be a mobile phone, a smart watch, a smart bracelet, a tablet computer, a television, and other electronic devices with a display function, which are not listed here.

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Abstract

一种触控显示面板及显示装置，涉及触控技术领域。触控显示面板具有显示区和外围区，外围区包括远离显示区的弯折区和绑定区；触控显示面板包括驱动背板、发光器件、触控层和屏蔽层，驱动背板包括至少部分位于外围区的外围驱动走线，至少部分外围驱动走线穿过弯折区，延伸至绑定区内；发光器件设于驱动背板一侧且位于显示区，发光器件包括第一电极、发光层和第二电极；触控层设于发光器件层远离驱动背板的一侧且包括外围触控走线，外围触控走线穿过弯折区延伸至绑定区内；屏蔽层设于触控层和驱动背板之间，且至少部分位于第二电极的边界和弯折区之间；屏蔽层至少部分覆盖交叠区域；屏蔽层与第一电极或第二电极接收相同的信号。

Description

触控显示面板及显示装置 技术领域
本公开涉及触控技术领域，具体而言，涉及一种触控显示面板及显示装置。
背景技术
触控显示面板是手机、智能手表等终端设备的重要组成部分，在实现图像显示的同时，可以通过触控操作实现人机交互。但是现有触控显示面板的触控的准确性仍有待提高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种触控显示面板及显示装置。
根据本公开的一个方面，提供一种触控显示面板，所述触控显示面板具有显示区和位于所述显示区外的外围区，所述外围区包括远离所述显示区的弯折区和绑定区，所述绑定区位于所述弯折区远离所述显示区的一侧；
所述触控显示面板包括：
驱动背板，包括至少部分位于所述外围区的外围驱动走线，至少部分所述外围驱动走线穿过所述弯折区，延伸至所述绑定区内；
多个发光器件，设于所述驱动背板一侧且位于所述显示区，所述发光器件包括沿远离所述驱动背板的方向依次层叠的第一电极、发光层和第二电极；所述第二电极的边界延伸至所述外围区且位于所述弯折区远离所述绑定区的一侧；
触控层，设于所述发光器件层远离所述驱动背板的一侧，且包括位于所述外围区的外围触控走线，所述外围触控走线穿过所述弯折区，延伸至所述绑定区内，且至少部分外围触控走线和至少部分所述外围驱动 走线存在交叠区域；
屏蔽层，设于所述触控层和所述驱动背板之间，且至少部分位于所述第二电极的边界和所述弯折区之间；所述屏蔽层至少部分覆盖所述交叠区域；所述屏蔽层与所述第一电极或所述第二电极接收相同的信号。
在本公开的一种示例性实施方式中，所述屏蔽层与所述第一电极同层设置。
在本公开的一种示例性实施方式中，所述驱动背板包括：
衬底；
电路层，设于所述衬底一侧，且包括至少部分所述外围驱动走线；
平坦层，覆盖所述电路层；
所述屏蔽层和所述第一电极设于所述平坦层远离所述衬底的表面，且所述屏蔽层设有排气孔。
在本公开的一种示例性实施方式中，所述排气孔的数量为多个，且沿行方向和列方向排成多行和多列。
在本公开的一种示例性实施方式中，各所述外围触控走线包括沿所述列方向延伸至所述绑定区的引出段，各所述引出段沿所述行方向间隔分布，且均与所述屏蔽层交叠；
相邻两列所述排气孔之间设有至少两个所述引出段。
在本公开的一种示例性实施方式中，位于相邻两列所述排气孔之间的相邻两所述引出段的间距小于位于一列所述排气孔两侧的相邻两所述引出段的间距。
在本公开的一种示例性实施方式中，各所述外围触控走线包括沿所述列方向延伸至所述绑定区的引出段，各所述引出段沿所述行方向间隔分布，且均与所述屏蔽层交叠；
至少一部分所述引出段和各列所述排气孔沿所述行方向交替排列。
在本公开的一种示例性实施方式中，相邻两所述引出段的间距大于一列所述排气孔的宽度。
在本公开的一种示例性实施方式中，至少部分所述外围触控走线与至少部分所述外围驱动走线在所述弯折区和所述绑定区之间交叉，且所述外围触控走线的与所述外围驱动走线交叉的区域的宽度小于未与所述 外围驱动走线交叉的区域的宽度。
在本公开的一种示例性实施方式中，所述外围触控走线未与所述外围驱动走线交叉的区域的宽度和与所述外围驱动走线交叉的区域的宽度之差为4μm-5μm。
在本公开的一种示例性实施方式中，相互交叉的所述外围触控走线和所述外围驱动走线的延伸方向垂直。
在本公开的一种示例性实施方式中，所述电路层包括位于所述外围区的电源总线和多个位于所述显示区的像素电路和电源线，一所述电源线与一列所述像素电路连接，且所述电源线与所述电源总线连接；所述屏蔽层与所述电源总线或所述电源线连接。
在本公开的一种示例性实施方式中，所述电路层包括沿远离所述衬底的方向依次堆叠的半导体层、第一栅绝缘层、第一栅极层、第二栅绝缘层、第二栅极层、介电层和源漏层，所述平坦层设于所述源漏层远离所述衬底的一侧；所述电源线和所述电源总线位于所述源漏层，所述外围驱动走线位于所述第一栅极层、所述第二栅极层和所述源漏层中的至少一层。
在本公开的一种示例性实施方式中，所述触控层还包括位于所述显示区的触控电极，所述触控电极与所述外围触控走线同层设置；所述外围触控走线与距离所述外围触控走线最近的触控电极的边界之间的距离为任意相邻两所述外围触控走线间的距离的20倍至22倍。
在本公开的一种示例性实施方式中，所述触控电极包括多个第一触控电极和多个第二触控电极，各所述第一触控电极沿行方向间隔分布，一所述第一触控电极包括沿列方向间隔分布的多个第一电极块和连接相邻两所述第一电极块的转接桥；各所述第二触控电极沿所述列方向间隔分布，一所述第二触控电极包括沿行方向串联的多个第二电极块；一所述转接桥与一所述第二触控电极交叉设置；所述第一电极块、所述第二电极块和所述外围触控走线位于同一电极层，且一所述外围触控走线与一所述第一触控电极或所述第二触控电极连接；所述转接桥位于所述电极层一侧，所述转接桥与所述电极层之间设有绝缘层。
根据本公开的一个方面，提供一种触控显示面板，所述触控显示面 板具有显示区和位于所述显示区外的外围区，所述外围区包括远离所述显示区的弯折区和绑定区，所述绑定区位于所述弯折区远离所述显示区的一侧；
所述触控显示面板包括：
触控层，包括位于所述显示区的触控电极和位于所述外围区的外围触控走线，所述外围触控走线穿过所述弯折区，延伸至所述绑定区内；
距离所述触控电极最近的外围触控走线与距离所述外围触控走线最近的触控电极的之间的距离为任意相邻两所述外围触控走线间的距离的20倍至22倍。
根据本公开的一个方面，提供一种触控显示面板，所述触控显示面板具有显示区和位于所述显示区外的外围区，所述外围区包括远离所述显示区的弯折区和绑定区，所述绑定区位于所述弯折区远离所述显示区的一侧；
所述触控显示面板包括：
驱动背板，包括至少部分位于所述外围区的外围驱动走线，至少部分所述外围驱动走线穿过所述弯折区，延伸至所述绑定区内；
多个发光器件，设于所述驱动背板一侧且位于所述显示区，所述发光器件包括沿远离所述驱动背板的方向依次层叠的第一电极、发光层和第二电极；所述第二电极的边界延伸至所述外围区且位于所述弯折区远离所述绑定区的一侧；
触控层，设于所述发光器件层远离所述驱动背板的一侧，且包括位于所述外围区的外围触控走线，所述外围触控走线穿过所述弯折区，延伸至所述绑定区内，且至少部分外围触控走线和至少部分所述外围驱动走线交叠；
至少部分所述外围触控走线与至少部分所述外围驱动走线在所述弯折区和所述绑定区之间交叉，且所述外围触控走线的与所述外围驱动走线交叉的区域的宽度小于未与所述外围驱动走线交叉的区域的宽度。
在本公开的一种示例性实施方式中，相互交叉的所述外围触控走线和所述外围驱动走线的延伸方向垂直。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所 述的触控显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开触控显示面板一实施方式的俯视图。
图2为本公开触控显示面板一实施方式的显示区的局部截面图。
图3为本公开触控显示面板一实施方式中驱动背板的示意图。
图4为本公开触控显示面板一实施方式中像素电路的原理图。
图5为本公开触控显示面板一实施方式中触控层的示意图。
图6为本公开触控显示面板一实施方式的外围区的局部截面图。
图7为本公开触控显示面板一实施方式中外围区的局部俯视图。
图8为本公开触控显示面板另一实施方式中外围区的局部俯视图。
图9为本公开触控显示面板一实施方式中引出区的局部俯视图。
图10为本公开触控显示面板一实施方式中过渡段交叉的示意图。
图11为本公开触控显示面板另一实施方式的显示区的局部截面图。
图12为本公开触控显示面板一实施方式的电极层的局部放大图。
图13为本公开触控显示面板一实施方式的外围区的局部截面图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性 图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本文中的行方向和列方向Y仅为两个相互垂直的方向，在本公开的附图中，行方向可以是横向，列方向Y可以是纵向，但并不限于此，若触控显示面板发生旋转，则行方向和列方向Y的实际朝向可能发生变化。
本文中的A特征和B特征“交叠”是指A特征在衬底上的正投影和B特征在衬底上的正投影至少部分重合。
本公开实施方式提供了一种触控显示面板，如图1所示，触控显示面板具有显示区AA和位于显示区AA外的外围区WA，外围区WA可以是围绕显示区AA的连续或间断的环形区域，或者也可以是半封闭的区域，在此不对外围区WA的形状做特殊限定。外围区WA可包括沿列方向Y朝远离显示区AA的方向凸出的引出区FA，引出区FA可包括沿列方向Y分布的弯折区BA和绑定区CA，绑定区CA位于弯折区BA远离显示区AA的一侧。通过使弯折区BA弯折，可将引出区FA弯折至触控显示面板的背光侧，即与出光方向相反的一侧。
此外，绑定区CA具有至少一个驱动芯片和与该驱动芯片连接的多个引脚，可通过绑定区CA的引脚与一柔性电路板连接，并将柔性电路板与一控制电路板绑定，从而实现触控显示面板和控制电路板的连接，以便通过控制电路板控制触控显示面板显示图像以及实现触控功能。当然，绑定区CA也可以不设置驱动芯片，而将驱动芯片设置在柔性电路板或控制电路板上，且与绑定区CA的引脚连接，以便实现显示和触控功能。
如图2-图8所示，本公开的触控显示面板可包括驱动背板BP、发光器件LD、触控层TSP和屏蔽层ES，其中：
驱动背板BP可包括至少部分位于外围区WA的外围驱动走线WBL， 至少部分外围驱动走线WBL穿过弯折区BA，延伸至绑定区CA内。
发光器件LD设于驱动背板BP一侧，且包括位于显示区AA的发光器件。发光器件LD包括沿远离驱动背板BP的方向依次层叠的第二电极CAT、发光层EL和第二电极CAT。各发光器件LD共用第二电极CAT，第二电极CAT的边界延伸至外围区WA且位于弯折区BA远离绑定区CA的一侧。
触控层TSP可设于发光器件LD层远离驱动背板BP的一侧，且包括位于外围区WA的外围触控走线WTL，外围触控走线WTL穿过弯折区BA，延伸至绑定区CA内，且至少部分外围触控走线WTL和至少部分外围驱动走线WBL存在交叠区域；屏蔽层ES设于触控层TSP和驱动背板BP之间，且至少部分位于第二电极CAT的边界和弯折区BA之间。屏蔽层ES至少部分覆盖该交叠区域，且屏蔽层ES与第二电极CAT部分交叠；屏蔽层ES与第二电极CAT或第二电极CAT接收相同的信号。
本公开的触控显示面板，在触控层TSP和驱动背板BP之间设置了屏蔽层ES，屏蔽层ES与第二电极CAT部分交叠，且部分位于第二电极CAT的边界和弯折区BA之间，而屏蔽层ES可与第二电极CAT或第二电极CAT接收相同的信号，从而可通过屏蔽层ES对外围触控走线WTL和外围驱动走线WBL进行隔离，防止外围驱动走线WBL的信号对外围触控走线WTL的信号造成干扰，从而保证触控功能的正常实现，有利于提高触控的准确性。
下面对本公开的触控显示面板进行详细说明：
下面对驱动背板BP进行详细说明：
如图3所示，驱动背板BP可包括用于驱动各发光器件LD独立发光的驱动电路，驱动电路可包括像素电路PC和外围电路，其中，像素电路PC的数量为多个，且至少部分像素电路PC可设于显示区AA内，当然，可以存在一部分像素电路PC的部分区域位于外围区WA。
每个像素电路PC可包括多个晶体管和存储电容，各晶体管的沟道可同层设置，且均可以采用多晶硅等半导体材料。像素电路PC可以是3T1C、7T1C等像素电路PC，nTmC表示一个像素电路PC包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。像素电路PC 的数量可以是多个，且阵列分布呈多行和多列，一像素电路PC可连接一个发光器件LD，当然，也可以存在一个像素电路PC连接多个发光器件LD的情况，本文仅以像素电路PC和发光器件LD一一对应的连接为例进行说明。
在本公开的一些实施方式中，如图4所示，像素电路PC可以是7T1C结构，其可具有7个晶体管和1个电容，即第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7以及存储电容Cst。
同时，为了便于向像素电路PC传输信号，驱动背板BP还可包括栅线、复位信号线、数据线DAL和电源线VDL等，其中，栅线和复位信号线的数量均为多个，且均沿行方向X穿过显示区AA，并延伸至外围区WA内，且一像素电路PC连接多个栅线和多个复位信号线。连接于同一像素电路PC的栅线可包括第一复位控制线、第二复位控制线、扫描线和发光控制线，连接于同一像素电路PC的复位信号线可包括第一复位信号线和第二复位信号线。
数据线DAL和电源线VDL均沿列方向Y穿过显示区AA，且延伸至外围区WA内。一列像素电路PC至少连接一个数据线DAL和电源线VDL。
第一复位晶体管T1的第一极与第一复位信号线VIL1连接，用于接收复位信号Vinit1，第二极与驱动晶体管T3的栅极和存储电容Cst的第一极板连接。
补偿晶体管T2的第一极与驱动晶体管T3的第二极连接，第二极与驱动晶体管T3的栅极连接。
写入晶体管T4的第一极与数据线DAL连接，用于接收数据信号DA，第二极与驱动晶体管T3的第一极连接。
第一发光控制晶体管T5的第一极和存储电容Cst的第二极板与电源线VDL连接，用于接收第一电源信号VDD，第二极与驱动晶体管T3的第一极连接。
第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极连接，第二极与一发光器件LD的第一电极ANO连接。
第二复位晶体管T7的第一极与第二复位信号线VIL2连接，用于接收第二复位信号Vinit2，第二极与第二发光控制晶体管T6的第二极连接。发光器件LD的第二电极CAT可接收第二电源信号VSS。
同时，为了控制各晶体管的导通和关断，第一复位晶体管T1的栅极与第一复位控制线连接，用于输入第一复位控制信号RE1，第二复位晶体管T7的栅极与第二复位控制线连接，用于输入第二复位控制信号RE2。补偿晶体管T2和写入晶体管T4的栅极与扫描线连接，用于输入扫描信号GA，第一发光控制晶体管T5和第二发光控制晶体管T6的栅极与发光控制线连接，用于输入发光控制信号EM。
下面以像素电路PC的各晶体管均为P型低温多晶硅晶体管为例，对其工作原理进行说明：
在复位阶段：第一复位控制信号RE1为低电平信号，第一复位晶体管T1导通，驱动晶体管T3的栅极和存储电容Cst的第一极板被写入复位信号Vinit1，对N1节点实现初始化，消除上一帧图像的数据的影响。
在写入阶段：通过扫描信号GA为低电平信号，可使写入晶体管T4和补偿晶体管T2导通，向驱动晶体管T3的栅极和存储电容Cst的第一极板Cst1写入透光孔DA，即经过N3节点和N2节点向N1节点写入透光孔DA，直至电位达到Vdata+Vth。其中，Vdata为透光孔DA的电压，Vth为驱动晶体管T3的阈值电压。写入晶体管T4和补偿晶体管T2的扫描信号GA可为同一信号。同时，第二复位控制信号RE2为低电平信号，使第二复位晶体管T7导通，发光器件LD的第二电极CAT和第二发光控制晶体管T6的第二极被写入第二复位信号Vinit2，对N4节点进行复位，实现初始化，进一步消除上一帧图像的数据的影响。
在发光阶段：发光控制信号EM为低电平信号，第一发光控制晶体管T5和第二发光控制晶体管T6导通，驱动晶体管T3在存储电容Cst存储的电压Vdata+Vth和第一电源信号VDD的作用下导通，此时，发光器件LD发光。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前 提下，能够容易想到将本公开实施例的像素电路PC结构中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开实施例的保护范围内的。
外围电路一方面可通过像素电路PC与发光器件LD连接，向发光器件LD的第一电极ANO施加第一电源信号，另一方面，外围电路也可与发光器件LD的第二电极CAT连接，并向第二电极CAT施加第二电源信号VSS，通过控制像素电路PC可控制通过发光器件LD的电流，从而控制发光器件LD的亮度。外围电路可包括外围驱动电路GOA，其可包括栅极驱动电路和发光控制电路等，当然，还可包括其它电路，在此不对外围电路的具体结构做特殊限定。
如图3所示，驱动背板BP还可包括位于外围区WA的总线，总线可由外围区WA穿过弯折区BA，延伸至引出区FA内，且延伸至绑定区CA内，或者位于引出区FA内。其中，总线可包括沿可沿远离显示区AA的方向间隔分布的复位信号总线、第一电源总线和第二电源总线。第一复位信号线和第二复位信号线均与复位信号总线，用于接收第一复位信号和第二复位信号。电源线VDL可与第一电源总线连接，用于接收第一电源信号VDD，各发光器件LD的第二电极CAT可与第二电源总线连接，用于接收第二电源线号VSS。
在本公开的一些实施方式中，栅极驱动电路可包括多个级联的栅移位寄存器单元，可为多行像素电路PC提供复位控制信号和扫描信号，从而控制晶体管的依次打开，上述的扫描线、第一复位控制线和第二复位控制线均与栅极驱动电路连接。
举例而言，一栅移位寄存器单元可包括多个晶体管和电容，其可以是8T2C、10T2C或12T2C等，nTmC表示一个像素电路PC包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)，在此不对其具体结构做特殊限定。
多个栅移位寄存器单元级联，第一级栅移位寄存器单元中的输入晶体管的第一极和输入端连接，输入端用于接收触发信号作为输入信号，而其它各级栅移位寄存器单元中的输入端和上一级栅移位寄存器单元的输出端电连接，以接收上一级栅移位寄存器单元输出的输出信号作为输 入信号，由此实现移位输出，以用于对显示区AA的像素电路PC进行逐行扫描。
此外，如图3所示，为了便于控制栅移位寄存器单元，驱动背板BP还可包括位于外围区WA内的外围驱动走线WBL，外围驱动走线WBL可穿过弯折区BA延伸至引出区FA内，并延伸至绑定区CA，并可与驱动芯片连接，以便接收信号。
外围驱动走线WBL可包括与栅移位寄存器单元连接的驱动电源线、触发信号线和时钟信号线等，举例而言，驱动电源线包括用于向栅移位寄存器单元提供电源的第一驱动电源线和第二驱动电源线，触发信号线用于提供上述的触发信号。时钟信号线可包括第一时钟信号线和第二时钟信号线，用于控制至少部分晶体管的导通时序。栅极驱动电路的结构和具体工作原理在此不做特殊限定。
发光控制电路可包括沿列方向Y级联的多个发光移位寄存器单元，发光移位寄存器单元的结构和工作原理与栅移位寄存器单元相似，其可控制各行像素电路PC的发光控制晶体管依次导通和关断。例如，发光移位寄存器单元可与发光控制线连接，向发光控制线输出发光控制信号EM。在本公开的一些实施方式中，发光移位寄存器单元可与两行像素电路PC所连接的发光控制线连接。相应的，发光移位寄存器单元也可以与多个外围驱动走线WBL连接，这些外围驱动走线WBL可包括驱动电源线、触发信号线和时钟信号线等，在此不再详述其连接关系。
当然，在本公开的一些实施方式中，像素电路PC可以不包括发光控制晶体管，相应的，外围电路也可以不包括发光控制电路。
如图2所示，驱动背板BP可包括衬底SU、层叠于衬底SU一侧的电路层CL和平坦层PLN，其中：
衬底SU可为驱动背板BP的基底，其可承载电路层CL，衬底SU可为硬质或柔性结构，其可以是单层或多层结构，在此不做特殊限定。
电路层CL可包括上述的驱动电路，像素电路PC和外围电路的晶体管和电容以及连接像素电路PC和外围电路的走线均位于电路层C。以各晶体管为顶栅型低温多晶硅晶体管为例，电路层CL可包括沿远离衬 底SU的方向依次堆叠半导体层SEL、第一栅绝缘层GI1、第一栅极层GA1、第二栅绝缘层GI2、第二栅极层GA2、介电层ILD和源漏层SD，其中：
半导体层SEL可包括各晶体管的沟道以及连接至少部分沟道的掺杂区，通过掺杂区可实现部分晶体管的连接。第一栅极层GA1可包括各电容的第一极板、扫描线、第一复位控制线、第二复位控制线和发光控制线等栅线以及。第二栅极层GAT2可包括存储电容的第二极板、第一复位信号线、第二复位信号线以及复位信号总线等。源漏层SD可包括数据线DAL、电源线VDL、电源总线以及连接栅极驱动电路的触发信号线、驱动电源线和时钟信号线等至少部分外围驱动走线WBL。
平坦层PLN可覆盖电路层CL，例如，平坦层PLN覆盖源漏层SD。平坦层PLN的材料可以是透明的树脂等有机材料，且平坦层PLN背离驱动背板BP的表面为平面，以便在其上设置发光器件LD。
此外，电路层CL还可包括钝化层，其可覆盖源漏层SD，平坦层PLN可覆盖钝化层。
在本公开的其它实施方式中，驱动背板BP在介电层ILD远离衬底SU的一侧可设置第一源漏层和第二源漏层，电源线和数据线等可位于第二源漏层，平坦层可覆盖第二源漏层。
如图11所示，在本公开的其它实施方式中，上述的7T1C的像素电路还可采用LTPO(LTPS+Oxide)技术，具体而言，驱动晶体管T3、写入晶体管T4、第二复位晶体管T7、第一发光控制晶体管T5和第二发光控制晶体管T6则可以采用P型低温多晶硅晶体管；第一复位晶体管T1和补偿晶体管T2则可以采用N型金属氧化物晶体管。由于P型低温多晶硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板，以便获得较高的载流子迁移率，提高响应速度。同时，通过N型金属氧化物晶体管可降低漏电。基于此，电路层CL可包括第一半导体层SEL、第一栅绝缘层GI1、第一栅极层GA1、第一绝缘层IL0、第二栅极层GA2、第二绝缘层IL1，第二半导体层IGL、第二栅绝缘层GI2、第三栅极层GA3、第三绝缘层IL2、第一源漏层SD1、第一平坦层PLN1、第二源漏层SD2，其中：
第一半导体层SEL可设于衬底SU一侧，且包括像素电路中的驱动晶体管T3、写入晶体管T4、第二复位晶体管T7、第一发光控制晶体管T5和第二发光控制晶体管T6的沟道。第一半导体层SEL的材料可以是多晶硅。第一栅绝缘层GI1可覆盖第一半导体层SEL。
第一栅极层GA1可设于第一栅绝缘层GI1远离衬底SU的表面，且包括存储电容Cst的第一极板。第一绝缘层IL0可覆盖第一栅极层GA1。第二栅极层GA2可设于第一绝缘层IL0远离衬底SU的表面，且包括存储电容的第二极板。第二绝缘层IL1覆盖第二栅极层GA2，其可以是单层或多层结构。
第二半导体层IGL可设于第二绝缘层IL1远离衬底SU的表面，且包括第一复位晶体管T1和补偿晶体管T2的沟道。第二半导体层IGL的材料可包括铟镓锌氧化物(IGZO)等半导体金属氧化物。
第二栅绝缘层GI2可覆盖第二半导体层IGL。第三栅极层GA3可设于第三栅绝缘层GI2远离衬底SU的表面。第三绝缘层IL2可覆盖第三栅极层GA3，其可以是单层或多层结构。
第一源漏层SD1可设于第三绝缘层IL2远离衬底SU的表面。第一平坦层PLN1可设于第一源漏层SD1远离衬底SU的一侧。第二源漏层SD2可设于第一平坦层PLN1远离衬底SU的表面。
第二平坦层PLN2即为上文中的平坦层PLN，第二平坦层PLN2覆盖第二源漏层SD2，其材料可以是树脂等绝缘材料。发光器件LD可设于的第二平坦层PLN2远离衬底SU的一侧。
此外，在衬底SU和第一半导体层SEL之间，还可设置遮光层BSM，其可采用遮光的金属或其它材料，且可以是单层或多层结构。遮光层BSM的至少部分区域可与至少部分晶体管的沟道区交叠，以遮蔽照射向晶体管的光线，使得晶体管的电学特性稳定。进一步的，可通过绝缘的缓冲层BUF覆盖遮光层BSM，第一半导体层SEL可设于缓冲层BUF背离衬底SU的表面。缓冲层BUF可以是单层或多层结构，其材料可以包括氮化硅、氧化硅等绝缘材料。
下面对发光器件LD进行详细说明：
如图2所示，发光器件LD可设于平坦层PLN(第二平坦层PLN2) 远离衬底SU的表面，且与像素电路PC连接。发光器件LD的数量可以有多个，且每个发光器件LD可连接一个像素电路PC，同一像素电路PC可以连接一个或多个发光器件LD。该发光器件LD可以是OLED(有机发光二极管)、QLED(量子点发光二极管)、Micro LED或Mini LED等，其可以包括第二电极CAT、第二电极CAT和位于第二电极CAT和第二电极CAT间的发光层EL，其中：
第一电极ANO可设于电路层CL远离衬底SU的表面，例如平坦层PLN远离衬底SU的表面，发光层EL可包括沿远离驱动背板BP的方向层叠的空穴注入层、空穴传输层、发光材料层、电子传输层和电子注入层。各个发光器件LD可共用第二电极CAT，也就是说，第二电极CAT可以是连续的整层结构，且第二电极CAT可延伸至外围区WA，并可与第二电源总线连接，以便接收第二电源信号VSS，第一电极ANO则阵列分布，确保各发光器件LD可以独立发光。此外，为了限定发光器件LD的发光范围，防止串扰，可在设置第一电极ANO的表面设置像素定义层PDL，其可设有露出各第一电极ANO的开口，发光层EL在开口内与第一电极ANO层叠。
各发光器件LD可至少共用发光材料层，使得各发光器件LD的发光颜色相同，此时，为了实现彩色显示，可在发光器件LD远离衬底SU的一侧设置彩膜层，通过彩膜层中与各发光器件LD对应的滤光部，实现彩色显示。当然，各个发光器件LD的发光材料层也可以使独立的，使得发光器件LD可以直接发出单色光，且不同发光器件LD的发光颜色可以不同，从而实现彩色显示。
此外，如图2所示，显示面板还可以包括封装层TFE，其可覆盖发光器件LD，用于保护发光器件LD，阻隔外界的水、氧对发光器件LD造成侵蚀。举例而言，封装层TFE可采用薄膜封装的方式实现封装，其可包括第一无机层、有机层和第二无机层，其中，第一无机层覆盖于发光器件LD，有机层可设于第一无机层背离驱动背板BP的表面，且有机层的边界限定于第一无机层的边界的内侧，有机层在驱动背板BP上的正投影的边界可位于外围区WA，确保有机层能覆盖各发光器件LD。第 二无机层可覆盖有机层和未被有机层覆盖的第一无机层，可通过第二无机层阻挡水氧侵入，通过具有柔性的有机层实现平坦化。
下面对触控层TSP进行详细说明：
如图2所示，触控层TSP可设于封装层TFE远离衬底的一侧，例如，其可直接设于封装层TFE远离衬底SU的表面。如图5所示，触控层TSP可采用互容结构，在本公开的一些实施方式中，触控层TSP可包括多个位于显示区AA的触控电极，触控电极可包括第一触控电极Tx和多个第二触控电极Rx，各第一触控电极Tx可沿行方向X间隔分布，各第二触控电极Rx可沿列方向Y间隔分布。第一触控电极Tx和第二触控电极Rx均可以包括多个串联的电极块，其中，任一第一触控电极Tx可包括沿列方向Y串联的多个第一电极块Txc，在列方向Y上相邻的两第一电极块Txc通过一转接桥BR串联。任一第二触控电极Rx可包括沿行方向X串联的多个第二电极块Rxc，相邻两第二电极块Rxc可通过一连接部Rxo串联。
各个第一电极块Txc和第二电极块Rxc均阵列分布，至少一部分第一电极块Txc在与行方向X和列方向Y相交的两个不同方向上，与不同的第二电极块Rxc相邻设置，相应的，至少一部分第二电极块Rxc在与行方向X和列方向Y相交的两个不同方向上，与不同的第一电极块Txc相邻设置。
相邻的一第一电极块Txc和一第二电极块Rxc之间具有间隙，从而可形成电容，为了增大相邻的一第一电极块Txc和一第二电极块Rxc之间正对的区域，可使第一电极块Txc和第二电极块Rxc的边沿具有沿周向间隔分布的叉指。在相邻的一第一电极块Txc和一第二电极块Rxc中，第一电极块Txc的一部分叉指可位于第二电极块Rxc的一部分叉指之间内，但互不接触，使得第一电极块Txc的该部分叉指与第二电极块Rxc的该部分叉指交替间隔排列，通过叉指FI可使第一电极块Txc和第二电极块Rxc间的间隙的延伸轨迹更加曲折，可在不增大第一电极块Txc和第二电极块Rxc的面积的情况下，增大二者的正对区域，有利于增大二者之间的电容，提高感应触控操作的灵敏度。
任意相邻的第一电极块Txc和第二电极块Rxc之间可形成电容，在手指进行触控操作时，可使触控位置的电容发生变化，通过感应电容的变化量对应的第一触控电极Tx和第二触控电极Rx，可确定触控位置，详细原理在此不再详述。
如图2所示，上述的各电极块和连接部Rxo可位于同一电极层，该电极层可通过一次构图工艺同时形成，也就是说，电极层TMB包括第一电极块Txc和第二触控电极Rx。为了避免第一触控电极Tx和第二触控电极Rx短路，可使转接桥BR位于电极层TMB的一侧，也就是说，转接桥BR与电极层TMB不同层。同时，转接桥BR和电极层TMB之间设有绝缘层IN，从而被分隔，第一触控电极Tx可在转接桥BR处与第二触控电极Rx交叉，进一步的，转接桥BR可与连接部Rxo交叉。此外，转接桥BR可通过贯穿绝缘层IN的过孔与第一电极块Txc连接。
如图2所示，在本公开的一些实施方式中，各转接桥BR可设于封装层TFE远离衬底SU的表面，并可同时形成，各转接桥BR的厚度相同，且材料相同，从而可同时形成。绝缘层IN可覆盖各转接桥BR。电极层TMB可设于绝缘层IN背离衬底SU的表面，每个转接桥BR可通过一个或多个贯穿绝缘层IN的过孔与一第一电极块Txc连接。
转接桥BR和电极层TMB均可以是单层或多层的导电结构，举例而言，转接桥BR可包括两层外部层和位于两层外部层之间的中间层，外部层的材料可为钛，中间层的材料可为铝，即转接桥BR为Ti/Al/Ti结构；或者，外部层的材料可为铟锡氧化物(ITO)，中间层的材料可为铝，即转接桥BR为ITO/Ag/ITO结构。同时，电极层TMB若为多层结构，也可以是Ti/Al/Ti结构、ITO/Ag/ITO结构。
绝缘层IN的材料可为氮化硅，当然，也可以是氧化硅、氮氧化硅等其它无机绝缘材料或有机绝缘材料。
此外，如图2所示，在本公开的一些实施方式中，触控层TSP还可包括缓冲层TBU和保护层TOC，其中，缓冲层TBU可作为触控层TSP的基底，其可设于封装层TFE远离衬底SU的表面，其材料可包括氮化硅、氧化硅等绝缘材料。转接桥BR可设于缓冲层TBU背离衬底SU的表面，保护层TOC可覆盖电极层TMB和绝缘层IN未被电极层TMB覆 盖的区域，保护层TOC用于保护电极层TMB，其材料可以是聚酰亚胺(PI)或光学胶等透明绝缘材料。
为了降低对显示基板PNL发光的遮挡，可使第一触控电极Tx和第二触控电极Rx均为多个网格线形成的网状结构，各网格线均可以沿直线延伸，但方向可以不同。
在本公开的另一些实施方式中，触控层TSP还可以采用自容结构，例如，触控层TSP可包括多个位于同一电极层TMB的触控电极，各触控电极阵列分布，且相互间隔设置。每个触控电极与地构成自电容，当用户的手指触摸时，手指的电容会叠加到触控电极的自电容上，使得电容量增加，从而可通过检测触控电极的电容量的变化，确定出触摸点的位置，即触控点对应的触控电极的位置。
进一步的，在本公开的一些实施方式中，如图12所示，为了提高透光率，上述实施方式中的电极层TMB可以是由通道线TC围成的网状结构，具有多个网孔TH，每个网孔TH均有多个通道线TC围成。发光器件LD可与网孔TH对应，从而减小电极层TMB对光线的遮挡。网孔TH的形状可为菱形、矩形、五边形、六边形等多边形。
如图5所示，触控层TSP还可包括多个外围触控走线WTL，外围触控走线WTL可位于电极层TMB，且一外围触控走线WTL可与一触控电极连接，例如互容式结构中的第一触控电极Tx或第二触控电极Rx连接，当然，也可以是自容式结构中的触控电极。同时，外围触控走线WTL可穿过弯折区BA延伸至引出区FA内，且延伸至绑定区CA内，并与一驱动芯片连接，当然，若绑定区CA内无驱动芯片，也可通过绑定区CA的引脚与外部的驱动芯片连接。触控电极可通过外围触控走线WTL收/发触控信号，例如，第一触控电极Tx可作为接收驱动信号的驱动电极，第二触控电极Rx可作为输出感应信号的感应电极。当然，第一触控电极Tx和第二触控电极Rx的作用可以互换。或者，通过自容式结构中的触控电极收/发触控信号。
在本公开的一些实施方式中，如图5所示，各外围触控走线WTL位于引出区FA内的部分可沿行方向X分为两个触控引出部WTS，一个 触控引出部WTS均包括一部分外围触控走线WTL位于引出区FA的部分。该两个触控引出部WTS可关于一沿列方向Y延伸的直线对称设置。一触控引出部WTS包括沿列方向Y分布的引出段WTL1、过渡段WTL2和绑定段WTL3，过渡段WTL2可连接于引出段WTL1和绑定段WTL3之间，且引出段WTL1可与外围触控走线WTL位于引出区FA外的部分连接，绑定段WTL3可延伸至绑定区CA并与绑定区CA内的驱动芯片或引脚连接。同时，引出段WTL1和绑定段WTL3均沿列方向Y延伸，过渡段WTL2的延伸方向与列方向Y呈一定的夹角，从而与引出段WTL1和绑定段WTL3的延伸方向不同。此外，上述两个触控引出部WTS的绑定段WTL3在行方向X上位于两个引出段WTL1之间。
如图3所示，至少一部分外围驱动走线WBL位于引出区FA内的部分也可沿行方向X分为两个驱动引出部WBS，一个驱动引出部WBS均包括一部分外围驱动走线WBL位于引出区FA的部分。该两个触控引出部WTS可关于一沿列方向Y延伸的直线对称设置。一驱动引出部WBS都包括沿列方向Y分布的引出段WBL1、过渡段WBL2和绑定段WBL3，过渡段WBL2可连接于引出段WBL1和绑定段WBL3之间，且引出段WBL1可与外围驱动走线WBL位于引出区FA外的部分连接，绑定段WBL3可用于与绑定区CA内的驱动芯片或引脚连接。同时，引出段WBL1和绑定段WBL3均沿列方向Y延伸，过渡段WBL2的延伸方向与列方向Y呈一定的夹角，从而与引出段WBL1和绑定段WBL3的延伸方向不同。此外，上述两个驱动引出部WBS的引出段WBL1在行方向X上位于两个绑定段WBL3之间。上述的包括驱动引出部WBS的外围驱动走线WBL可以包括连接栅极驱动电路的外围驱动走线WBL，例如时钟信号线、驱动电源线和触发信号线等，当然，还可以包括连接发光控制电路的外围驱动走线WBL。
两个驱动引出部WBS的引出段WBL1位于两个触控引出部WTS的引出段WTL1之间，两个触控引出部WTS的绑定段WTL3位于两个驱动引出部WBS的绑定段WBL3之间，两个驱动引出部WBS的过渡段WBL2与两个触控引出部WTS的过渡段WTL2一一对应的交叉设置，即一驱动引出部WBS的过渡段WTL2在衬底SU上的正投影与一触控引 出部WTS的过渡段WTL2在衬底SU上的正投影交叉，且相互交叉的过渡段WTL2和WBL2的延伸方向的夹角可以是90°，即二者的延伸方向垂直，即正交。当然，该夹角也可以是其它角度。
发明人发现，驱动背板BP中的至少部分外围驱动走线WBL的信号会对触控层TSP造成干扰，影响触控功能的正常进行，容易出现触控准确性降低等问题。为此，发明人提出了多种方案减小外围驱动走线WBL的信号对触控层TSP的干扰。
如图2和图6所示，在本公开的一些实施方式中，各个发光器件LD共用第二电极CAT，使得第二电极CAT为连续的整层结构，且其边界可位于外围区WA，且与部分外围驱动走线WBL和外围触控走线WTL存在交叠区域，即二者在衬底SU上的正投影具有重合区域，由于第二电源信号VSS为恒压信号，从而可通过第二电极CAT在驱动背板BP和触控层TSP之间起到屏蔽的作用，减小外围驱动走线WBL的信号对外围触控走线WTL的信号的干扰，提高触控的准确性。同时，为了不影响引出区FA的弯折，第二电极CAT的边界位于弯折区BA和显示区AA之间，且与弯折区BA之间具有一定的距离，如此一来，对于至少一部分外围触控走线WTL而言，其位于第二电极CAT和弯折区BA之间的部分未与第二电极CAT交叠，因而难以利用第二电极CAT为其屏蔽驱动背板BP的信号。
基于此，在一些实施方式中，如图6-图8所示，可在驱动背板BP和触控层TSP之间设置屏蔽层ES，屏蔽层ES位于弯折区BA远离显示区AA的一侧，且屏蔽层ES与部分外围触控走线WTL和外围驱动走线WBL的交叠区域交叠，即覆盖该交叠区域。也即屏蔽层ES、外围触控走线WTL和外围驱动走线WBL在衬底SU上的正投影存在重合区域，同时，屏蔽层ES还与第二电极CAT部分交叠，且屏蔽层ES部分位于第二电极CAT的边界和弯折区BA之间，此外，屏蔽层ES在行方向X上的长度不小于弯折区BA的长度。由此，可通过屏蔽层ES对第二电极CAT的边界与弯折区BA之间的空间进行遮挡，从而为该空间的内的外 围触控走线WTL起到屏蔽作用。同时，可将屏蔽层ES与第二电极CAT或第二电极CAT连接，以便接收恒压的第一电源信号VDD或第二电源信号VSS，从而起到屏蔽作用，例如，由于屏蔽层ES与第二电极CAT存在交叠，因而可在交叠的区域将二者通过过孔连接，从而向屏蔽层ES传输第二电源信号VSS，或者，也可将屏蔽层ES与第二电极CAT或位于源漏层SD的电源线或者电源总线连接，从而可向屏蔽层ES传输第一电源信号VDD。
此外，像素定义层PDL可延伸至屏蔽层ES远离衬底的表面，且覆盖屏蔽层ES。
为了简化结构，如图6所示，在本公开的一些实施方式中，可使屏蔽层ES与第二电极CAT同层设置，从而可通过相同的工艺同时形成第二电极CAT和屏蔽层ES。进一步的，屏蔽层ES和第二电极CAT设于平坦层PLN远离衬底SU的表面。由于平坦层PLN为有机材料，在制造过程中，会产生气体，因此，为了便于排气，防止气体导致屏蔽层ES鼓包，如图7和图8所示，可在屏蔽层ES开设排气孔GH，像素定义层PDL可填充排气孔GH，触控层TSP的缓冲层TBU和绝缘层也可延伸至屏蔽层ES远离衬底的一侧。
进一步的，排气孔GH的数量为多个，且沿行方向X和列方向Y排成多行和多列。
为了避免排气孔GH和引出段WTL1交叠，影响屏蔽效果，可使排气孔GH位于引出段WTL1错开排列，举例而言：
如图8所示，在本公开的一些实施方式中，相邻两列排气孔GH之间设有至少两个引出段WTL1，且相邻两列排气孔GH之间的相邻两引出段WTL1之间无排气孔GH。进一步的，位于相邻两列排气孔GH之间的相邻两列引出段WTL1的间距小于位于一列排气孔GH两侧的相邻两引出段WTL1的间距，举例而言：一列排气孔GH两侧的相邻两引出段WTL1的间距为S2，相邻两列排气孔GH之间的相邻两引出段WTL1的间距为S3，S2大于S3，且一列排气孔GH的宽度不大于18μm-19μm，例如18.2μm，相邻两列排气孔GH之间的相邻两引出段WTL1的间距S3为13μm-14μm，例如13.2μm。也就是说，各个引出段WTL1不是等 间距分布，排气孔GH可位于间距较大的两列引出段WTL1之间，间距较小的两引出段WTL1之间可以不设置排气孔GH。
如图7所示，在本公开的另一些实施方式中，至少一部分引出段WTL1和各列排气孔GH沿行方向X交替排列，相邻两列排气孔GH之间可设有一引出段WTL1，相邻两引出段WTL1之间可设有一列排气孔GH。进一步的，相邻两引出段WTL1的间距S1可大于一列排气孔GH的宽度，且间距S1可为29μm-30μm，例如29.2μm。
如图13所示，在本公开的另一些实施方式中，至少部分引出段WTL1可包括沿列方向Y分布的第一子段WTL11、第二子段WTL12和第三子段WTL13，第一子段WTL11可与外围触控走线WTL位于引出区FA外的部分连接，第三子段WTL13与过渡段WTL2连接，第二子段WTL12连接于第一子段WTL11和第三子段WTL13之间。
相邻两第三子段WTL13的间距可定义为相邻两引出段WTL1的间距S1，相邻两第一子段WTL11的间距S11小于相邻两第二子段WTL12的间距为S1。
如图9和图10所示，对于上文中提到的交叉的过渡段WTL2和WBL2，为了防止交叉区域存在干扰，可对过渡段WTL2的宽度进行设置，使过渡段WTL2与过渡段WBL2交叉的区域的宽度小于未交叉的区域，从而可以减少寄生电容，减小外围驱动走线WBL对外围触控走线WTL的干扰。也就是说，可使外围触控走线WTL的与外围驱动走线WBL交叉的区域的宽度W2小于未与外围驱动走线WBL交叉的区域的宽度W1。
举例而言，可使外围触控走线WTL未与外围驱动走线WBL交叉的区域的宽度W1和与外围驱动走线WBL交叉的区域的宽度W2之差为4μm-5μm，例如4.5μm。进一步的，外围触控走线WTL未与外围驱动走线WBL交叉的区域的宽度为16μm-17μm，例如16.5μm，与外围驱动走线WBL交叉的区域的宽度之差为11μm-13μm，例如12μm。
此外，如图5和图12所示，可对外围触控走线WTL与距离外围触控走线WTL最近的触控电极(自容式结构的触控电极或互容式结构的 第一触控电极Tx和第二触控电极Rx)的边界之间的距离进行限定，减小外围触控走线WTL与触控电极的信号之间的互相干扰。具体来说，可使距离触控电极最近的外围触控走线WTL与距离外围触控走线WTL最近的触控电极的边界之间的距离K1为触控电极为任意相邻两外围触控走线WTL间的距离K2的20倍至22倍，举例而言：
在本公开的一些实施方式中，任意相邻两外围触控走线WTL间的距离K2可为4.5μm-5μm，外围触控走线WTL与距离外围触控走线WTL最近的触控电极的边界的距离K1为90μm-110μm，例如100μm，使得外围触控走线WTL与触控电极的信号不会互相干扰。
如图12所示，本公开的实施方式还提供了一种触控显示面板，可用于减小外围触控走线WTL与触控电极的信号之间的互相干扰。该触控显示面板可具有显示区AA和位于显示区外的外围区WA，外围区WA包括远离显示区的弯折区BA和绑定区，绑定区CA位于弯折区BA远离显示区的一侧；触控显示面板可包括触控层TSP，其可包括位于显示区AA的触控电极和位于外围区WA的外围触控走线WTL，外围触控走线WTL穿过弯折区BA，延伸至绑定区CA内。距离触控电极最近的外围触控走线WTL与距离外围触控走线WTL最近的触控电极的边界之间的距离K1为任意相邻两外围触控走线WTL间的距离K2的20倍至22倍。
如图12所示，在本公开的一些实施方式中，可以不采用上文中的屏蔽层ES、排气孔GH以及外围触控走线WTL与外围驱动走线WBL交叉等方案，仅对任意相邻两外围触控走线WTL间的距离K2可为4.5μm-5μm，外围触控走线WTL与距离外围触控走线WTL最近的触控电极的边界的距离K1为90μm-110μm，例如100μm，使得外围触控走线WTL与触控电极的信号不会互相干扰。
当然，在本公开的其它实施方式中，也可以采用上文中的屏蔽层ES以及排气孔GH等方案，具体内容可参考上文的实施方式的触控显示面板，在此不再赘述。
本公开的实施方式还提供了一种触控显示面板，可通过使过渡段 WTL2与过渡段WBL2交叉的区域的宽度小于未交叉的区域，减少寄生电容，减小外围驱动走线WBL对外围触控走线WTL的干扰，而可以不采用上文中的屏蔽层ES、排气孔GH等方案。具体而言，至少部分外围触控走线WTL与至少部分外围驱动走线WBL在弯折区BA和绑定区CA之间交叉，且外围触控走线WTL的与外围驱动走线WBL交叉的区域的宽度小于未与外围驱动走线WBL交叉的区域的宽度。
进一步的，外围触控走线WTL未与外围驱动走线WBL交叉的区域的宽度和与外围驱动走线交叉的区域的宽度之差为4μm-5μm。相互交叉的外围触控走线WTL和外围驱动走线WBL的延伸方向垂直。具体内容已在上文的实施方式中进行了说明，可参考上文的实施方式的触控显示面板，在此不再赘述。
本公开还提供一种显示装置，该显示装置可包括上述任意实施方式的触控显示面板。该触控显示面板为上述任意实施方式的触控显示面板，其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是手机、智能手表、智能手环、平板电脑、电视等具有显示功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种触控显示面板，所述触控显示面板具有显示区和位于所述显示区外的外围区，所述外围区包括远离所述显示区的弯折区和绑定区，所述绑定区位于所述弯折区远离所述显示区的一侧；
    所述触控显示面板包括：
    驱动背板，包括至少部分位于所述外围区的外围驱动走线，至少部分所述外围驱动走线穿过所述弯折区，延伸至所述绑定区内；
    多个发光器件，设于所述驱动背板一侧且位于所述显示区，所述发光器件包括沿远离所述驱动背板的方向依次层叠的第一电极、发光层和第二电极；所述第二电极的边界延伸至所述外围区且位于所述弯折区远离所述绑定区的一侧；
    触控层，设于所述发光器件层远离所述驱动背板的一侧，且包括位于所述外围区的外围触控走线，所述外围触控走线穿过所述弯折区，延伸至所述绑定区内，且至少部分外围触控走线和至少部分所述外围驱动走线存在交叠区域；
    屏蔽层，设于所述触控层和所述驱动背板之间，且至少部分位于所述第二电极的边界和所述弯折区之间；所述屏蔽层至少部分覆盖所述交叠区域；所述屏蔽层与所述第一电极或所述第二电极接收相同的信号。
  2. 根据权利要求1所述的触控显示面板，其中，所述屏蔽层与所述第一电极同层设置。
  3. 根据权利要求2所述的触控显示面板，其中，所述驱动背板包括：
    衬底；
    电路层，设于所述衬底一侧，且包括至少部分所述外围驱动走线；
    平坦层，覆盖所述电路层；
    所述屏蔽层和所述第一电极设于所述平坦层远离所述衬底的表面，且所述屏蔽层设有排气孔。
  4. 根据权利要求3所述的触控显示面板，其中，所述排气孔的数量为多个，且沿行方向和列方向排成多行和多列。
  5. 根据权利要求4所述的触控显示面板，其中，各所述外围触控走线包括沿所述列方向延伸至所述绑定区的引出段，各所述引出段沿所述 行方向间隔分布，且均与所述屏蔽层交叠；
    相邻两列所述排气孔之间设有至少两个所述引出段。
  6. 根据权利要求5所述的触控显示面板，其中，位于相邻两列所述排气孔之间的相邻两所述引出段的间距小于位于一列所述排气孔两侧的相邻两所述引出段的间距。
  7. 根据权利要求4所述的触控显示面板，其中，各所述外围触控走线包括沿所述列方向延伸至所述绑定区的引出段，各所述引出段沿所述行方向间隔分布，且均与所述屏蔽层交叠；
    至少一部分所述引出段和各列所述排气孔沿所述行方向交替排列。
  8. 根据权利要求7所述的触控显示面板，其中，相邻两所述引出段的间距大于一列所述排气孔的宽度。
  9. 根据权利要求1-8任一项所述的触控显示面板，其中，至少部分所述外围触控走线与至少部分所述外围驱动走线在所述弯折区和所述绑定区之间交叉，且所述外围触控走线的与所述外围驱动走线交叉的区域的宽度小于未与所述外围驱动走线交叉的区域的宽度。
  10. 根据权利要求9所述的触控显示面板，其中，所述外围触控走线未与所述外围驱动走线交叉的区域的宽度和与所述外围驱动走线交叉的区域的宽度之差为4μm-5μm。
  11. 根据权利要求9所述的触控显示面板，其中，相互交叉的所述外围触控走线和所述外围驱动走线的延伸方向垂直。
  12. 根据权利要求3所述的触控显示面板，其中，所述电路层包括位于所述外围区的电源总线和多个位于所述显示区的像素电路和电源线，一所述电源线与一列所述像素电路连接，且所述电源线与所述电源总线连接；所述屏蔽层与所述电源总线或所述电源线连接。
  13. 根据权利要求12所述的触控显示面板，其中，所述电路层包括沿远离所述衬底的方向依次堆叠的半导体层、第一栅绝缘层、第一栅极层、第二栅绝缘层、第二栅极层、介电层和源漏层，所述平坦层设于所述源漏层远离所述衬底的一侧；所述电源线和所述电源总线位于所述源漏层，所述外围驱动走线位于所述第一栅极层、所述第二栅极层和所述源漏层中的至少一层。
  14. 根据权利要求1-13任一项所述的触控显示面板，其中，所述触控层还包括位于所述显示区的触控电极，所述触控电极与所述外围触控走线同层设置；所述外围触控走线与距离所述外围触控走线最近的触控电极的边界之间的距离为任意相邻两所述外围触控走线间的距离的20倍至22倍。
  15. 根据权利要求14所述的触控显示面板，其中，所述触控电极包括多个第一触控电极和多个第二触控电极，各所述第一触控电极沿行方向间隔分布，一所述第一触控电极包括沿列方向间隔分布的多个第一电极块和连接相邻两所述第一电极块的转接桥；各所述第二触控电极沿所述列方向间隔分布，一所述第二触控电极包括沿行方向串联的多个第二电极块；一所述转接桥与一所述第二触控电极交叉设置；所述第一电极块、所述第二电极块和所述外围触控走线位于同一电极层，且一所述外围触控走线与一所述第一触控电极或所述第二触控电极连接；所述转接桥位于所述电极层一侧，所述转接桥与所述电极层之间设有绝缘层。
  16. 一种触控显示面板，所述触控显示面板具有显示区和位于所述显示区外的外围区，所述外围区包括远离所述显示区的弯折区和绑定区，所述绑定区位于所述弯折区远离所述显示区的一侧；
    所述触控显示面板包括：
    触控层，包括位于所述显示区的触控电极和位于所述外围区的外围触控走线，所述外围触控走线穿过所述弯折区，延伸至所述绑定区内；
    距离所述触控电极最近的外围触控走线与距离所述外围触控走线最近的触控电极的之间的距离为任意相邻两所述外围触控走线间的距离的20倍至22倍。
  17. 一种触控显示面板，所述触控显示面板具有显示区和位于所述显示区外的外围区，所述外围区包括远离所述显示区的弯折区和绑定区，所述绑定区位于所述弯折区远离所述显示区的一侧；
    所述触控显示面板包括：
    驱动背板，包括至少部分位于所述外围区的外围驱动走线，至少部分所述外围驱动走线穿过所述弯折区，延伸至所述绑定区内；
    多个发光器件，设于所述驱动背板一侧且位于所述显示区，所述发 光器件包括沿远离所述驱动背板的方向依次层叠的第一电极、发光层和第二电极；所述第二电极的边界延伸至所述外围区且位于所述弯折区远离所述绑定区的一侧；
    触控层，设于所述发光器件层远离所述驱动背板的一侧，且包括位于所述外围区的外围触控走线，所述外围触控走线穿过所述弯折区，延伸至所述绑定区内，且至少部分外围触控走线和至少部分所述外围驱动走线交叠；
    至少部分所述外围触控走线与至少部分所述外围驱动走线在所述弯折区和所述绑定区之间交叉，且所述外围触控走线的与所述外围驱动走线交叉的区域的宽度小于未与所述外围驱动走线交叉的区域的宽度。
  18. 根据权利要求17所述的触控显示面板，其中，所述外围触控走线未与所述外围驱动走线交叉的区域的宽度和与所述外围驱动走线交叉的区域的宽度之差为4μm-5μm。
  19. 根据权利要求17所述的触控显示面板，其中，相互交叉的所述外围触控走线和所述外围驱动走线的延伸方向垂直。
  20. 一种显示装置，包括权利要求1-19任一项所述的触控显示面板。
PCT/CN2022/115535 2022-08-29 2022-08-29 触控显示面板及显示装置 WO2024044894A1 (zh)

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