WO2023039926A1 - 显示面板及电子设备 - Google Patents

显示面板及电子设备 Download PDF

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Publication number
WO2023039926A1
WO2023039926A1 PCT/CN2021/120309 CN2021120309W WO2023039926A1 WO 2023039926 A1 WO2023039926 A1 WO 2023039926A1 CN 2021120309 W CN2021120309 W CN 2021120309W WO 2023039926 A1 WO2023039926 A1 WO 2023039926A1
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WO
WIPO (PCT)
Prior art keywords
display panel
signal line
display area
transistor
sub
Prior art date
Application number
PCT/CN2021/120309
Other languages
English (en)
French (fr)
Inventor
刘宏燕
李超
陈涛
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/611,510 priority Critical patent/US20240049507A1/en
Publication of WO2023039926A1 publication Critical patent/WO2023039926A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the invention relates to the field of display technology, in particular to a display panel and electronic equipment.
  • AMOLED Active-matrix organic light-emitting diode (active matrix organic light-emitting diode) display panel design
  • the under-screen camera technology realizes a true full-screen form with no bangs and no digging holes on the front, but optimization improves the area of the under-screen camera of the AMOLED panel.
  • the display effect has always been a difficult problem.
  • the pixel drive circuit density of the under-screen camera area is significantly lower than that of the normal display area.
  • the scanning signal lines in the display area are not at the same horizontal position, and the scanning signal lines are changed at the junction between the two areas, resulting in a complicated wiring environment for the pixels at the junction of the normal display area and the under-screen camera area.
  • the wiring environment of the pixel at the junction is different from that of other pixels in the normal display area, and the wiring change at the junction will form a parasitic capacitance between the adjacent active layer film.
  • the scanning signal is an AC signal, and the jump between high level and low level will affect the brightness of the pixel display due to capacitive coupling. Therefore, the potential crosstalk generated by the high-to-low transition of the scanning signal at other positions in the normal display area will be different from the potential crosstalk produced by the high-to-low transition of the scanning signal at the junction, resulting in the problem of uneven brightness (Mura) on the AMOLED panel.
  • An embodiment of the present invention provides a display panel to solve the problem that in the existing display panel, the scan signal line changes at the junction of the normal display area and the under-screen camera display area, resulting in high-low jumps in the scan signal.
  • the potential crosstalk generated at the location is different from the potential crosstalk generated at other positions in the normal display area, resulting in the technical problem of uneven brightness of the display panel.
  • An embodiment of the present invention provides a display panel, including a first display area and a second display area disposed outside the first display area, the light transmittance of the second display area is lower than the transmittance of the first display area light rate, including:
  • a plurality of first pixel driving circuits are arranged in the second display area, and the first pixel driving circuits include a plurality of thin film transistors;
  • a plurality of second pixel driving circuits located in the transitional display area of the first display area;
  • a semiconductor layer including a plurality of active parts of the thin film transistors and a plurality of connection parts connecting adjacent active parts;
  • a plurality of first signal lines including a first sub-signal line electrically connected to the first pixel drive circuit, a second sub-signal line electrically connected to the second pixel drive circuit, and a second sub-signal line electrically connected to the first pixel drive circuit and the first conversion line corresponding to the second sub-signal line, the first conversion line is arranged in a different layer from the first sub-signal line and the second sub-signal line;
  • a shielding layer is provided between the first conversion line and the semiconductor layer, and the orthographic projection of the shielding layer in the thickness direction of the display panel at least partially covers the connecting portion close to the first conversion line Orthographic projection in the thickness direction of the display panel.
  • the first signal line includes a scanning signal line
  • the first sub-signal line is electrically connected to the first pixel driving circuit in the same row
  • the second sub-signal line is electrically connected to the same row The second pixel driving circuit.
  • the plurality of thin film transistors include a first transistor, a second transistor, and a third transistor electrically connected to each other
  • the display panel includes a plurality of light emitting devices located in the second display area, The first transistor, the third transistor and the light-emitting device are connected in series between the first voltage line and the second voltage line to form a loop, and the source of the third transistor is electrically connected to the first transistor.
  • the drain of the third transistor is electrically connected to the gate of the first transistor, wherein the connecting part includes connecting the active part of the first transistor a first connection part connected to the active part of the second transistor and the active part of the third transistor, the first connection part is close to the corresponding first conversion line, and the shielding layer is The orthographic projection in the thickness direction on the display panel at least partially covers the first connecting portion.
  • the display panel includes a plurality of light emission control signal lines, the gate of the second transistor is electrically connected to a corresponding light emission control signal line, and the gate electrode of the third transistor Connect a corresponding scanning signal line.
  • the first connection part is located between the adjacent light emission control signal lines and the scanning signal lines.
  • the light emission control signal line includes a first light emission control signal line electrically connected to the first pixel drive circuit in the same row, a second light emission control signal line electrically connected to the second pixel drive circuit in the same row a control signal line, and a second conversion line electrically connecting the first light-emitting control signal line and the corresponding second light-emitting control signal line, the first light-emitting control signal line is parallel to the first sub-signal line, The second light emission control signal line is parallel to the second sub-signal line, wherein,
  • the first connecting portion is located between the corresponding first light emission control signal line and the first sub-signal line.
  • the display panel includes a source-drain metal layer disposed on the semiconductor layer, and the shielding layer is disposed between the semiconductor layer and the source-drain metal layer.
  • the display panel includes a gate metal layer disposed on the semiconductor layer, an intermediate metal layer disposed between the gate metal layer and the source-drain metal layer,
  • the shielding layer is disposed between the intermediate metal layer and the source-drain metal layer
  • the gate metal layer includes the gate of the first transistor
  • the intermediate metal layer includes a metal plate
  • the metal plate is electrically connected between the source of the first transistor and the first voltage line
  • the orthographic projection of the gate of the first transistor in the thickness direction of the display panel is the same as the metal plate
  • the orthographic projection of the plate in the thickness direction of the display panel overlaps, the orthographic projection of the shielding layer in the thickness direction of the display panel overlaps with the grid in the thickness direction of the display panel
  • the orthographic projection on , and the orthographic projection of the metal plate in the thickness direction of the display panel do not overlap.
  • the gate metal layer includes the first sub-signal line and the second sub-signal line, and the first conversion line and the source-drain metal layer are arranged in the same layer.
  • the first display area includes a light-transmissive display area
  • the transitional display area is disposed between the second display area and the light-transmissive display area
  • the display panel includes:
  • the first pixel unit is located in the second display area, and the first pixel driving circuit drives the first pixel unit to emit light;
  • the second pixel unit is located in the light-transmitting display area and the transition display area, and the second pixel driving circuit drives the second pixel unit to emit light.
  • the first sub-signal line is located in the second display area
  • the second sub-signal line is located in the transition display area, and is located around the transition display area and close to the first display area.
  • a plurality of the second pixel driving circuits of a conversion line are correspondingly provided with the shielding layer.
  • the second display area surrounds the transition display area
  • the first display area includes a symmetry axis parallel to the first sub-signal line
  • the shielding layer is about the symmetry axis Axisymmetric.
  • An embodiment of the present invention also provides a display panel, including a first display area and a second display area disposed outside the first display area, the light transmittance of the second display area is lower than that of the first display area light transmittance, the display panel includes:
  • the pixel driving circuits include a plurality of thin film transistors
  • a semiconductor layer including a plurality of active parts of the thin film transistors and a plurality of connection parts connecting adjacent active parts;
  • a shielding layer is provided on the semiconductor layer, and the orthographic projection of the shielding layer in the thickness direction of the display panel at least partially covers the connecting portion close to the first display area on the display panel. Orthographic projection in the thickness direction.
  • the display panel includes a plurality of first signal lines
  • the first signal lines include first sub-signal lines located in the first display area, second sub-signal lines located in the second display area, and sub-signal lines located in the second display area.
  • a sub-signal line, and a first conversion line electrically connecting the first sub-signal line and the second sub-signal line, the first conversion line is located at the junction of the first display area and the second display area , the first conversion line is arranged in different layers from the first sub-signal line and the second sub-signal line, and the shielding layer is parallel to the first conversion line.
  • the orthographic projection of the shielding layer in the thickness direction of the display panel completely covers the thickness direction of the connection portion close to the first display area on the display panel.
  • An embodiment of the present invention also provides an electronic device, the electronic device includes a display panel and a photosensitive unit, the photosensitive unit is set corresponding to the first display area of the display panel, and the display panel includes:
  • a plurality of first pixel driving circuits are arranged in the second display area, and the first pixel driving circuits include a plurality of thin film transistors;
  • a plurality of second pixel driving circuits located in the transitional display area of the first display area;
  • a semiconductor layer including a plurality of active parts of the thin film transistors and a plurality of connection parts connecting adjacent active parts;
  • a plurality of first signal lines including a first sub-signal line electrically connected to the first pixel drive circuit, a second sub-signal line electrically connected to the second pixel drive circuit, and a second sub-signal line electrically connected to the first pixel drive circuit and the first conversion line corresponding to the second sub-signal line, the first conversion line is arranged in a different layer from the first sub-signal line and the second sub-signal line;
  • a shielding layer is provided between the first conversion line and the semiconductor layer, and the orthographic projection of the shielding layer in the thickness direction of the display panel at least partially covers the connecting portion close to the first conversion line Orthographic projection in the thickness direction of the display panel.
  • the first signal line includes a scanning signal line
  • the first sub-signal line is electrically connected to the first pixel driving circuit in the same row
  • the second sub-signal line is electrically connected to the same row The second pixel driving circuit.
  • the plurality of thin film transistors include a first transistor, a second transistor, and a third transistor electrically connected to each other
  • the display panel includes a plurality of light emitting devices located in the second display area
  • the first transistor, the third transistor and the light-emitting device are connected in series between the first voltage line and the second voltage line to form a loop
  • the source of the third transistor is electrically connected to the first transistor.
  • the drain of the third transistor is electrically connected to the gate of the first transistor, wherein,
  • connection part includes a first connection part connecting the active part of the first transistor, the active part of the second transistor and the active part of the third transistor to each other, and the first connection part is close to Corresponding to the first conversion line, and the orthographic projection of the shielding layer on the display panel in the thickness direction at least partially covers the first connection portion.
  • the display panel includes a source-drain metal layer disposed on the semiconductor layer, and the shielding layer is disposed between the semiconductor layer and the source-drain metal layer.
  • the display panel includes a gate metal layer disposed on the semiconductor layer, an intermediate metal layer disposed between the gate metal layer and the source-drain metal layer,
  • the shielding layer is disposed between the intermediate metal layer and the source-drain metal layer
  • the gate metal layer includes the gate of the first transistor
  • the intermediate metal layer includes a metal plate
  • the metal plate is electrically connected between the source of the first transistor and the first voltage line
  • the orthographic projection of the gate of the first transistor in the thickness direction of the display panel is the same as the metal plate
  • the orthographic projection of the plate in the thickness direction of the display panel overlaps, the orthographic projection of the shielding layer in the thickness direction of the display panel overlaps with the grid in the thickness direction of the display panel
  • the orthographic projection on , and the orthographic projection of the metal plate in the thickness direction of the display panel do not overlap.
  • Embodiments of the present invention provide a display panel and electronic equipment.
  • the display panel includes a first pixel drive circuit located in the second display area, a second pixel drive circuit located in the first display area, a plurality of first signal lines, and a semiconductor layer.
  • the semiconductor layer includes an active part of the thin film transistor and a connection part connected to the active part
  • the first signal line includes a first sub-signal line connected to the first pixel driving circuit, a second sub-signal line connected to the second pixel driving circuit, and
  • the first conversion line connecting the first sub-signal line and the second sub-signal line, a shielding layer is provided between the first conversion line and the semiconductor layer, and the shielding layer at least partially covers the connection portion close to the first conversion line, which can improve
  • the brightness difference between the pixels at the junction of the first display area and the second display area and the pixels at other positions in the second display area improves the display uniformity of the display panel.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of pixel distribution near the border between the first display area and the second display area provided by the embodiment of the present invention.
  • FIG. 3 is a partially enlarged schematic diagram of the first display area of the display panel provided by an embodiment of the present invention.
  • FIG. 4 is a partially enlarged schematic plan view of the junction of the first display area AA1 and the second display area AA2 provided by the embodiment of the present invention.
  • FIG. 5 is a schematic plan view of a semiconductor layer of the first pixel driving circuit provided by an embodiment of the present invention.
  • FIG. 6 is a schematic plan view of a first pixel driving circuit provided by an embodiment of the present invention.
  • FIG. 7 is a schematic plan view of the positional relationship between the first pixel driving circuit and the shielding layer provided by the embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a circuit principle of a first pixel driving circuit provided by an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a film layer stack structure of a display panel provided by an embodiment of the present invention.
  • first and second are used for description purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • a first feature being "on” or “under” a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them.
  • “above”, “above” and “above” the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.
  • “Below”, “beneath” and “under” the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present invention.
  • An embodiment of the present invention provides a display panel 100, which may be an OLED display panel.
  • the display panel 100 includes a first display area AA1 and a second display area AA2, the area of the first display area AA1 is smaller than the area of the second display area AA2, and the light transmittance of the first display area AA1 is greater than
  • the light transmittance of the second display area AA2, the second display area AA2 is used for conventional display, while the first display area AA1 is used for display, it also has a high light transmittance, which can be used for cameras, etc.
  • the photosensitive element is disposed under the first display area AA1 of the display panel 100 to realize the under-screen camera display technology.
  • the display panel 100 includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, the first pixel driving circuits are located in the second display area AA2, and the first pixel driving circuits are located in the first In the display area AA1, the first pixel driver circuit and the second pixel driver both include a plurality of thin film transistors.
  • the density of the second pixel driving circuits in the first display area AA1 is lower than the density of the first pixel driving circuits in the second display area AA2.
  • FIG. 2 is a schematic diagram of pixel distribution near the border between the first display area and the second display area according to an embodiment of the present invention.
  • the display panel 100 includes a plurality of first pixel units 11 and a plurality of second pixel units 12, the first pixel units 11 are located in the second display area AA2, and the first pixel driving circuit drives the first The pixel unit 11 emits light, the second pixel unit 12 is located in the first display area AA1 , and the second pixel driving circuit drives the second pixel unit 12 to emit light.
  • any of the first pixel units 11 includes a first red sub-pixel 11a, a first green sub-pixel 11b, and a first blue sub-pixel 11c
  • any of the second pixel units 12 includes a second red sub-pixel 12a, a first Two green sub-pixels 12b and a second blue sub-pixel 12c.
  • Each sub-pixel includes a light emitting device, which may be an organic light emitting diode.
  • the shape of the first red sub-pixel 11a may be an octagon
  • the shape of the one green sub-pixel 11b may be an ellipse
  • the shape of the first blue sub-pixel 11c may be Transformed into eight.
  • the shape of the second red sub-pixel 12a may be circular
  • the shape of the second green sub-pixel 12b may be circular
  • the shape of the second blue sub-pixel 12c may be circular.
  • the opening areas of the sub-pixels of the same color in the second display area AA2 and the first display area AA1 are different, and the opening areas of the red, green, and blue sub-pixels in the second display area AA2 are respectively larger than those of the first display area AA1.
  • the opening areas of the corresponding red, green and blue sub-pixels in the area AA1 can provide a larger accommodation space for the arrangement of the second pixel driving circuit by reducing the opening area of a single sub-pixel in the first display area AA1.
  • one second pixel driving circuit can drive multiple sub-pixels of the same color in the first display area AA1 to emit light, so as to reduce the space occupied by the second pixel driving circuit.
  • two second red sub-pixels 12a can be driven by the same second pixel driving circuit
  • four second green sub-pixels 12b can be driven by the same second pixel driving circuit
  • two second blue sub-pixels 12c can be driven by the same second pixel driving circuit.
  • One first pixel driving circuit can drive one sub-pixel of the second display area AA2 to emit light.
  • the first display area AA1 is provided with a plurality of first pixel repeating units 101A
  • the second display area AA2 is provided with a plurality of second pixel repeating units 102A.
  • the number of the first pixel repeating units 101A included in the first display area AA1 is equal to the number of the second pixel repeating units 102A included in the second display area AA2, that is, the first
  • the display area AA1 and the second display area AA2 have the same pixel density (Pixel Per Inch, PPI), which can reduce the overall display of the display screen of the second display area AA2 and the display screen of the first display area AA1 difference.
  • the arrangement of the first pixel repeating unit 101A and the second pixel repeating unit 102A is the same, and the arrangement includes the arrangement rule and arrangement distance of each sub-pixel.
  • Both the first pixel repeating unit 101A and the second pixel repeating unit 102A adopt a pentile arrangement, taking the second pixel repeating unit 102A as an example, the second pixel repeating unit 102A adopts a 4 ⁇ 4 matrix
  • the arrangement method is that the sub-pixels in adjacent rows are arranged in dislocation, and the sub-pixels in adjacent columns are arranged in dislocation.
  • the second pixel repeating unit 102A includes two first red sub-pixels 11a, four first green sub-pixels 11b, two first green sub-pixels 11b, two The first blue sub-pixel 11c, the first red sub-pixel 11a and the first blue sub-pixel 11c are located in the same line and distributed alternately in sequence, the first green sub-pixel 11b is connected to the first red sub-pixel 11a, the first blue sub-pixel 11c Arranged in alternating rows.
  • the first display area AA1 includes a light-transmissive display area 101 and a transitional display area 102 outside the light-transmissive display area 101.
  • the transitional display area 102 is located Between the light-transmitting display area 101 and the transitional display area 102 .
  • the area of the second display area AA2 is larger than the area of the transitional display area 102 and the area of the light-transmitting display area 101.
  • the light-transmitting display area 101 has high transparency while realizing display.
  • the light transmittance of the display area 101 is greater than the light transmittance of the transitional display area 102 and the light transmittance of the second display area AA2.
  • a photosensitive element such as a camera can be arranged correspondingly to the light-transmitting display area 101 .
  • all second pixel driving circuits can be arranged in the transitional display area 102 .
  • the shape of the light-transmissive display area 101 can be circular, the transitional display area 102 surrounds the light-transmissive display area 101, the second display area AA2 surrounds the transitional display area 102, and the transitional display area 102
  • the shape can be a ring, specifically a circular ring.
  • the light-transmitting display area 101 can also be in other shapes such as square, rhombus, oval, etc.
  • the transitional display area 102 can also be in the shape of a square ring or an ellipse ring.
  • FIG. 3 is a partially enlarged schematic view of the first display area of the display panel.
  • Several second pixel driving circuits are collectively arranged to form a pixel driving island 13, that is, one pixel driving island 13 includes several second pixel driving circuits.
  • a plurality of pixel driving islands 13 surround the upper and lower sides of the light-transmitting display area 101, and the signal lines connecting the pixel driving islands 13 are located in the transition display area 102, and the signal lines include data lines VDATA, scanning signal line SCAN, first voltage line (DC power supply signal line VDD), control signal line EM, reset signal line RESET, initialization signal line VI, second voltage line (DC low voltage signal line VSS, usually grounded), etc. .
  • FIG. 4 is a partially enlarged schematic plan view of the junction of the first display area AA1 and the second display area AA2 .
  • the first signal lines of the display panel (such as the scanning signal line SCAN, the control signal line EM) There will be a line change at the junction of the second display area AA2 and the first display area AA1.
  • the first signal line in this embodiment includes a first sub-signal line electrically connected to the first pixel driving circuit, a second sub-signal line electrically connected to the second pixel driving circuit, and a second sub-signal line electrically connected to the first pixel driving circuit.
  • a sub-signal line and a first conversion line corresponding to the second sub-signal line, the first conversion line is arranged in a different layer from the first sub-signal line and the second sub-signal line.
  • the first sub-signal line may be located in the first display area
  • the second sub-signal line may be located in the second display area
  • the first conversion line may be located in the first display area. The junction of the display area and the second display area.
  • the wiring arrangement of the display panel is regular at other positions except at the line changing position, resulting in the wiring environment of the pixel driving circuit (at A in Figure 4) close to the line changing position at the junction and other
  • the wiring environment of the first pixel driving circuit or the second pixel driving circuit at the position there are differences in the wiring environment of the first pixel driving circuit or the second pixel driving circuit at the position, and the capacitive coupling effect caused by the high and low gray scale transition of the first signal line has an impact on the electrical properties of the pixel driving circuit at the position where the line is changed and on other
  • the pixel driving circuit can be located in the first display area AA1 or in the second display area AA2, but the pixel driving circuit needs to be located at the junction of the two areas.
  • the pixel driving circuit located at the junction is described by taking the first pixel driving circuit located in the second display area AA2 as an example.
  • the difference between the high and low jumps generated by the scanning signal line SCAN on the electric properties of the line changing position and other positions is illustrated as an example.
  • the display panel 100 includes a plurality of scanning signal lines SCAN, and the scanning signal lines SCAN include a first sub-signal line 21, a second sub-signal line 22, and a first conversion line 23, and the first conversion line 23 Electrically connect the first sub-signal line 21 and the second sub-signal line 22, the first sub-signal line 21 is electrically connected to the first pixel driving circuit in the same row, and the second sub-signal line 22 is electrically connected to the same row The second pixel driving circuit.
  • the scanning signal lines SCAN include a first sub-signal line 21, a second sub-signal line 22, and a first conversion line 23, and the first conversion line 23 Electrically connect the first sub-signal line 21 and the second sub-signal line 22, the first sub-signal line 21 is electrically connected to the first pixel driving circuit in the same row, and the second sub-signal line 22 is electrically connected to the same row The second pixel driving circuit.
  • the first sub-signal line 21 and the second sub-signal line 22 transmit the same scanning signal, and the first sub-signal line 21 and the second sub-signal line 22 are not at the same horizontal position, that is, the first The connections between the sub-signal lines 21 and the second sub-signal lines 22 are not on the same straight line.
  • the light emission control signal line EM includes a first light emission control signal line 51 electrically connected to the first pixel drive circuit in the same row, and a second light emission control signal line electrically connected to the second pixel drive circuit in the same row. (not shown), and a second conversion line electrically connecting the first light emission control signal line 51 and the corresponding second light emission control signal line, the first light emission control signal line 51 and the second light emission control signal line
  • the control signal line transmits the same light emission control signal, and the first light emission control signal line 51 and the second light emission control signal line are not at the same horizontal position.
  • the first conversion line 23 of the scanning signal line SCAN is adjacent to the active part film layer of the first driving circuit (at A in FIG. 4 ), and the first conversion line 23 will generate parasitic with the adjacent active part film layer. Capacitance (at B in Figure 4), capacitive coupling occurs, and the signal crosstalk caused by the high and low gray scale transition of the scanning signal line SCAN is generated on the first pixel unit 11 at the junction and on the first pixel unit 11 at other positions There are differences in the effects, so there will be mura at the junction and other positions of the second display area AA2 , which will reduce the display effect of the display panel 100 .
  • a shielding layer is correspondingly provided on the active part film layer close to the first conversion line 23 to cut the electric field between the first conversion line 23 and the adjacent active part film layer and reduce the above-mentioned defects.
  • the parasitic capacitance between the two can further reduce the influence of disturbance on the potential of the corresponding point of the first pixel driving circuit there.
  • FIG. 5 is a schematic plan view of the semiconductor layer of the first pixel driving circuit provided by the embodiment of the present invention
  • FIG. 6 is a schematic plan view of the first pixel driving circuit provided by the embodiment of the present invention.
  • Both the first pixel driving circuit and the second pixel driving circuit include a plurality of thin film transistors, and the thin film transistors include a source, a drain, and an active part.
  • FIG. 7 is a schematic plan view of the positional relationship between the first pixel driving circuit and the shielding layer.
  • the display panel 100 includes a semiconductor layer 30 disposed in regions corresponding to the first pixel driving circuit and the second pixel driving circuit.
  • the semiconductor layer 30 is used to form active parts of a plurality of thin film transistors and a plurality of connecting parts 31 , and the connecting parts 31 are used to connect active parts that need to be connected.
  • a shielding layer 40 is provided between the first conversion line 23 and the semiconductor layer 30, and the orthographic projection of the shielding layer 40 in the thickness direction of the display panel 100 at least partially covers the first display area AA1 Orthographic projection of the connecting portion 31 in the thickness direction of the display panel 100 .
  • the orthographic projection of the shielding layer 40 in the thickness direction of the display panel 100 at least partially covers the connection portion 31 close to the first conversion line 23, so as to reduce the number of connections between the first conversion line 23 and the connection portion close to the first conversion line.
  • the material of the shielding layer 40 includes molybdenum (Mo) metal.
  • the orthographic projection of the shielding layer 40 on the display panel 100 can completely cover the connecting portion close to the first conversion line 23 .
  • the orthographic projection of the shielding layer 40 in the thickness direction of the display panel 100 does not overlap with the orthographic projection of its adjacent metal devices (such as grids, capacitor plates, etc.) in the thickness direction of the display panel 100.
  • the first sub-signal line 21 is located in the second display area AA2
  • the second sub-signal line 22 is located in the transitional display area 102, and is located in the transitional display area 102.
  • the shielding layer 40 is correspondingly provided on the plurality of second pixel driving circuits around the display area 102 and close to the first conversion line 23 .
  • the second display area AA2 surrounds the transitional display area 102
  • the first display area AA1 includes a symmetry axis L1 parallel to the first sub-signal line 21, and the shielding layer 40 is about the symmetry axis L1.
  • Axis L1 is symmetrical.
  • the shielding layer 40 is parallel to the first conversion line 23 to prevent the shielding layer 40 from occupying too much wiring space.
  • FIG. 8 is a schematic diagram of a circuit principle of a first pixel driving circuit provided by an embodiment of the present invention.
  • the first pixel driving circuit may have a structure such as 7T1C (7 TFTs and 1 storage capacitor) or 4T1C (4 TFTs and 1 storage capacitor), but is not limited thereto.
  • the embodiment of the present invention is described by taking the 7T1C structure as an example.
  • the wires connected to the first pixel driving circuit include a data line VDATA, an initialization signal line VI, a reset signal line RESET, a scanning signal line SCAN, an emission control signal line EM, and a DC power signal line VDD.
  • the signals transmitted by the n-1th level reset signal line RESET(n-1) and the n-1th level scanning signal line SCAN(n) are derived from the same signal, and the n-th level reset signal line RESET( n) and the signal transmitted by the nth-level scanning signal line SCAN(n) come from the same signal, that is, the signal transmission of the n-1th level reset signal line RESET (n-1) can be transmitted by the n-1th level scanning signal line SCAN( n) transmission, the signal transmission of the nth level reset signal line RESET(n) can be transmitted by the nth level scanning signal line SCAN(n).
  • the plurality of thin film transistors include a first transistor, a second transistor and a third transistor electrically connected to each other, and the display panel includes a plurality of light emitting devices located in the second display area, so The first transistor, the third transistor and the light emitting device are connected in series between the first voltage line (DC power signal line VDD) and the second voltage line (DC low voltage signal line VSS) to form a loop, and the first
  • the source of the three transistors is electrically connected between the drain of the first transistor and the source of the second transistor, the drain of the third transistor is electrically connected to the gate of the first transistor, and the first transistor is electrically connected to the gate of the first transistor.
  • the sources of the three transistors are electrically connected between the drains of the first transistor and the sources of the second transistor.
  • the first pixel driving circuit 1011 includes a first transistor (drive transistor) T1, a switch transistor T2, a third transistor (compensation transistor) T3, an initialization transistor T4, a second light emission control transistor T5, a second transistor (first light emission transistor) control transistor) T6, anode reset transistor T7 and storage capacitor Cst.
  • the above seven transistors T1 - T7 may be P-type transistors.
  • the compensation transistor T3 and the initialization transistor T4 may be double-gate transistors.
  • the gate of the switching transistor T2 is electrically connected to the nth-level scanning signal line SCAN(n), its drain is electrically connected to the data line VDATA, and its source is electrically connected to the drain of the second light emission control transistor T5,
  • the gate of the second light emission control transistor T5 is electrically connected to the light emission control signal line EM(n)
  • the source of the second light emission control transistor T5 is electrically connected to the DC power signal line VDD
  • the gate of the initialization transistor T4 is electrically connected to the first n-1 level scanning signal line SCAN (n-1)
  • the source of the initialization transistor T4 is electrically connected to the initialization signal line VI
  • the drain of the initialization transistor T4 is electrically connected to the gate of the driving transistor
  • the gate of the first light-emitting control transistor T6 Electrically connected to the light emission control signal line EM(n)
  • the source of the first light emission control transistor T6 is electrically connected to the drain of the driving transistor T1 and the drain of the compensation transistor T3,
  • the gate of the compensation transistor T3 is electrically connected to the corresponding scanning signal line SCAN(n), the source of the compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the driving transistor T1 is also used as a storage capacitor.
  • the electrode plate, the other electrode plate of the storage capacitor is electrically connected to the source of the second light emission control transistor T5
  • the gate of the anode reset transistor T7 is electrically connected to the nth level scanning signal line SCAN (n)
  • the source of the anode reset transistor T7 It is electrically connected to the initialization signal line VI, and the drain of the anode reset transistor T7 is electrically connected to the anode of the light emitting device.
  • the first pixel driving circuit includes three working phases: a reset phase, a charging phase and a light emitting phase.
  • the reset phase the scanning signal line Scan(n-1) is set to low level, the initialization transistor T4 is turned on, and the gate of the driving transistor T1 is reset to the initial voltage Vi.
  • Charging phase the scanning signal line Scan(n) is set to low level, the switching transistor T2 and the compensation transistor T3 are turned on, and the gate potential of the driving transistor T1 is charged to Vdata–Vth (Vth is the threshold voltage of the driving transistor T1), and
  • the anode reset transistor T7 is turned on, and the anode potential of the light emitting device is reset to the initial voltage Vi.
  • Light-emitting stage the light-emitting control signal line EM(n) is set to a low level, and the light-emitting device emits light.
  • T1 ⁇ T3 are turned on and T4 ⁇ T6 are turned off.
  • the data line VDATA charges the gate of the driving transistor T1 through the path T1-T3.
  • the driving transistor T1 is turned off, and its gate potential is no longer raised.
  • the architecture of the second pixel driving circuit may be the same as or different from that of the first pixel driving circuit, which is not limited here.
  • the semiconductor layer 30 includes the active portion 32 of the driving transistor T1, the active portion of the switching transistor T2, the active portion 33 of the compensation transistor T3, the active portion of the initialization transistor T4, and the active portion of the second light emission control transistor T5.
  • the active part and the connection part of each thin film transistor mentioned above are formed after patterning the semiconductor layer 30, and the preparation material of the semiconductor layer 30 may be polysilicon.
  • the connecting portion 31 includes connecting the active portion 32 of the driving transistor T1 with the active portion 34 of the first light emission control transistor T6 and the compensation transistor T3
  • the active parts 33 are connected to each other by a first connection part 31 a, and the first connection part 31 a is close to the corresponding first conversion line 23 .
  • a parasitic capacitance will be generated between the first connection part 31a and the first conversion line 23, and when the first conversion line 23 undergoes a high-to-low gray scale transition, due to capacitive coupling, the C of the first pixel driving circuit will be The point potential (see Figure 8) jumps, which will further affect the Q point potential in the pixel, resulting in abnormal pixel brightness display at the junction and Mura.
  • the shielding layer 40 is correspondingly provided on the first connecting portion 31a, and the orthographic projection of the shielding layer 40 in the thickness direction on the display panel 100 at least partially covers the first connecting portion 31a, and the first connecting portion 31a can be cut.
  • the electric field between the portion 31a and the first conversion line 23 can effectively reduce the parasitic capacitance between the two, and reduce the disturbance influence on the potential of point C.
  • the first connection portion 31 a is disposed between the adjacent light emission control line EM and the scanning signal line SCAN.
  • the first light emission control signal line 51 is parallel to the first sub-signal line 21, and the second light emission control signal line is parallel to the second sub-signal line, wherein the first connection part 31a It is located between the corresponding first light emission control signal line 51 and the first sub-signal line 21 .
  • FIG. 9 is a film stack composition diagram of a display panel provided by an embodiment of the present invention.
  • the display panel 100 includes a substrate 10, the semiconductor layer 30 is disposed on the substrate 10, and a barrier layer, a buffer layer, and a gate metal layer can be stacked between the semiconductor layer 30 and the substrate 10.
  • the gate metal layer includes the gate of the thin film transistor (such as the gate 24 of the driving transistor T1), the first sub-signal line 21, the second sub-signal line 22, the light emission control signal line em.
  • the intermediate metal layer is disposed on the gate metal layer and is insulated from the gate metal layer by the first gate insulating layer.
  • the intermediate metal layer includes a metal plate 52 and an initialization signal line VI, the metal plate 52 is electrically connected between the source of the first transistor T1 and the first voltage line VDD, and the metal plate 52 is used for forming an electrode plate of the storage capacitor Cst, the orthographic projection of the metal plate 52 in the thickness direction of the display panel overlaps with the orthographic projection of the gate 24 of the drive transistor T1 in the thickness direction of the display panel,
  • the metal plate 52 and the gate of the driving transistor T1 form a storage capacitor Cst.
  • the source-drain metal layer is disposed on the middle metal layer and insulated by an interlayer insulating layer.
  • the source-drain metal layer includes the source and drain of the thin film transistor (such as the source and drain 61 of the driving transistor), and the data line VDATA.
  • the source and drain are connected to the corresponding active part through corresponding via holes.
  • the first conversion line 23 (not shown in FIG. 9 ) can be provided on the same layer as the source-drain metal layer, and the first conversion line 23 is connected to the first The sub-signal line 21 is connected to the second sub-signal line 22 .
  • the shielding layer 40 is disposed between the semiconductor layer 30 and the source-drain metal layer. Specifically, the shielding layer 40 is disposed between the intermediate metal layer and the source-drain metal layer, separated by an insulating layer, specifically, the shielding layer 40 is disposed corresponding to the first connection portion 31a, The orthographic projection of the shielding layer 40 on the display panel covers the orthographic projection of the first connecting portion 31 a on the display panel.
  • the orthographic projection of the shielding layer 40 in the thickness direction of the display panel 100 is different from the orthographic projection of the gate of the first transistor T1 in the thickness direction of the display panel 100 . overlapping.
  • the orthographic projection of the shielding layer 40 in the thickness direction of the display panel 100 does not overlap with the orthographic projection of the metal plate in the thickness direction of the display panel 100 .
  • the design of the shielding layer 40 avoiding the gate of the first transistor and the metal plate can prevent the shielding layer 40 from affecting the storage capacitor Cst.
  • the anode of the light-emitting device 80 is disposed on the source-drain metal layer, and is electrically connected to the source/drain of the driving transistor T1 through the bridging layer 70 .
  • an embodiment of the present invention also provides an electronic device, including the above-mentioned display panel 100 and a photosensitive unit, the photosensitive unit is set corresponding to the first display area AA1 of the display panel 100, and the photosensitive unit includes a camera, etc. Photosensitive element.
  • the embodiments of the present invention provide a display panel and an electronic device.
  • the display panel includes a first pixel drive circuit located in the second display area, a second pixel drive circuit located in the first display area, a plurality of scanning signal lines, and a semiconductor layer, the semiconductor layer includes the active part of the thin film transistor and the connecting part connected to the active part, the scanning signal line includes the first sub-signal line connected to the first pixel driving circuit in the same row, the second sub-signal line connected to the second pixel driving circuit in the same row.
  • the connection part can improve the brightness difference between the pixels at the junction of the first display area and the second display area and the pixels at other positions in the second display area, and improve the display uniformity of the display panel.

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Abstract

一种显示面板，包括设于第二显示区的第一像素驱动电路、设于第一显示区的第二像素驱动电路、半导体层及第一信号线，半导体层包括有源部、连接部，第一信号线包括第一子信号线、第二子信号线、电连接第一子信号线和第二子信号线的第一转换线，第一转换线和半导体层之间设有屏蔽层，屏蔽层覆盖靠近第一转换线的连接部。

Description

显示面板及电子设备 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及电子设备。
 背景技术
在AMOLED（Active-matrix organic light-emitting diode，有源矩阵有机发光二极体）显示面板的设计中，屏下摄像头技术实现了正面无刘海、无挖孔的真全面屏形态，但优化提高AMOLED面板的屏下摄像头区域的显示效果，一直以来是一个难题。为了提高AMOLED面板的屏下摄像头区的透光性，屏下摄像头区的像素驱动电路密度明显低于正常显示区的像素驱动电路密度，传输同一扫描信号的屏下摄像头区的扫描信号线和正常显示区的扫描信号线不在同一水平位置，扫描信号线在两个区域之间的交界处存在换线，导致正常显示区与屏下摄像头区域交界处的像素所处的布线环境复杂。
交界处的像素所处布线环境与正常显示区其他位置的像素所处布线环境不同，交界处的换线会与其邻近的有源层膜层之间形成寄生电容。而扫描信号是交流信号，高电平与低电平之间的跳变由于电容耦合作用，会影响像素显示的亮度。因此正常显示区其他位置扫描信号的高低跳变产生的电位串扰与交界处扫描信号的高低跳变产生的电位串扰会存在差异，导致AMOLED面板出现亮度明暗不均（Mura）的问题。
 技术问题
本发明实施例提供一种显示面板，以解决现有的显示面板中，扫描信号线在正常显示区和屏下摄像头显示区的交界处存在换线，导致扫描信号发生高低跳变时，在交界处产生的电位串扰与在正常显示区的其他位置产生的电位串扰存在差异，导致显示面板出现亮度明暗不均的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种显示面板，包括第一显示区和设于所述第一显示区外的第二显示区，所述第二显示区的透光率小于所述第一显示区的透光率，包括：
多个第一像素驱动电路，设于所述第二显示区，所述第一像素驱动电路包括多个薄膜晶体管；
多个第二像素驱动电路，设于所述第一显示区的过渡显示区；
半导体层，包括多个所述薄膜晶体管的有源部及多个连接相邻的所述有源部的连接部；
多条第一信号线，包括电连接所述第一像素驱动电路的第一子信号线、电连接所述第二像素驱动电路的第二子信号线，以及电连接所述第一子信号线和对应的所述第二子信号线的第一转换线，所述第一转换线与所述第一子信号线、所述第二子信号线异层设置；其中，
所述第一转换线和所述半导体层之间设有屏蔽层，且所述屏蔽层在所述显示面板的厚度方向上的正投影至少部分覆盖靠近所述第一转换线的所述连接部在所述显示面板的所述厚度方向上的正投影。
在本发明的一些实施例中，所述第一信号线包括扫描信号线，所述第一子信号线电连接同一行所述第一像素驱动电路，所述第二子信号线电连接同一行所述第二像素驱动电路。
在本发明的一些实施例中，多个所述薄膜晶体管包括相互电连接的第一晶体管、第二晶体管及第三晶体管，所述显示面板包括位于所述第二显示区的多个发光器件，所述第一晶体管、所述第三晶体管以及所述发光器件串联在第一电压线和第二电压线之间以形成回路，所述第三晶体管的源极电连接于所述第一晶体管的漏极和所述第二晶体管的源极之间，所述第三晶体管的漏极电连接所述第一晶体管的栅极，其中，所述连接部包括将所述第一晶体管的有源部与所述第二晶体管的有源部以及所述第三晶体管的有源部相互连接的第一连接部，所述第一连接部靠近对应的所述第一转换线，且所述屏蔽层在所述显示面板上的厚度方向上的正投影至少部分覆盖所述第一连接部。
在本发明的一些实施例中，所述显示面板包括多条发光控制信号线，所述第二晶体管的栅极电连接一对应的所述发光控制信号线，所述第三晶体管的栅极电连接对应的一所述扫描信号线。
在本发明的一些实施例中，所述第一连接部位于相邻的所述发光控制信号线和所述扫描信号线之间。
在本发明的一些实施例中，所述发光控制信号线包括电连接同一行所述第一像素驱动电路的第一发光控制信号线、电连接同一行所述第二像素驱动电路的第二发光控制信号线，以及电连接所述第一发光控制信号线和对应的所述第二发光控制信号线的第二转换线，所述第一发光控制信号线与所述第一子信号线平行，所述第二发光控制信号线与所述第二子信号线平行，其中，
所述第一连接部位于对应的所述第一发光控制信号线和所述第一子信号线之间。
在本发明的一些实施例中，所述显示面板包括设于所述半导体层上的源漏极金属层，所述屏蔽层设于所述半导体层和所述源漏极金属层之间。
在本发明的一些实施例中，所述显示面板包括设于所述半导体层上的栅极金属层、设于所述栅极金属层和所述源漏极金属层之间的中间金属层，所述屏蔽层设于所述中间金属层和所述源漏极金属层之间，所述栅极金属层包括所述第一晶体管的所述栅极，所述中间金属层包括金属板，所述金属板电连接于所述第一晶体管的源极和所述第一电压线之间，所述第一晶体管的栅极在所述显示面板的所述厚度方向上的正投影与所述金属板在所述显示面板的所述厚度方向上的正投影重叠，所述屏蔽层在所述显示面板的所述厚度方向上的正投影与所述栅极在所述显示面板的所述厚度方向上的正投影，以及与所述金属板在所述显示面板的厚度方向上的正投影均不重叠。
在本发明的一些实施例中，所述栅极金属层包括所述第一子信号线以及所述第二子信号线，所述第一转换线与所述源漏极金属层同层设置。
在本发明的一些实施例中，所述第一显示区包括透光显示区，所述过渡显示区设于所述第二显示区和所述透光显示区之间，所述显示面板包括：
第一像素单元，位于所述第二显示区，所述第一像素驱动电路驱动所述第一像素单元发光；
第二像素单元，位于所述透光显示区和所述过渡显示区，所述第二像素驱动电路驱动所述第二像素单元发光。
在本发明的一些实施例中，所述第一子信号线位于所述第二显示区，所述第二子信号线位于所述过渡显示区，位于所述过渡显示区周边且靠近所述第一转换线的多个所述第二像素驱动电路对应设置有所述屏蔽层。
在本发明的一些实施例中，所述第二显示区围绕所述过渡显示区，所述第一显示区包括与所述第一子信号线平行的对称轴，所述屏蔽层关于所述对称轴对称。
本发明实施例还提供一种显示面板，包括第一显示区、设于所述第一显示区外的第二显示区，所述第二显示区的透光率小于所述第一显示区的透光率，所述显示面板包括：
多个像素驱动电路，位于所述第一显示区和所述第二显示区的交界处，所述像素驱动电路包括多个薄膜晶体管；以及
半导体层，包括多个所述薄膜晶体管的有源部及多个连接相邻的所述有源部的连接部；
其中，所述半导体层上设有屏蔽层，且所述屏蔽层在所述显示面板的厚度方向上的正投影至少部分覆盖靠近所述第一显示区的所述连接部在所述显示面板的厚度方向上的正投影。
在本发明的一些实施例中，所述显示面板包括多条第一信号线，所述第一信号线包括位于所述第一显示区的第一子信号线、位于第二显示区的第二子信号线，以及电连接所述第一子信号线和所述第二子信号线的第一转换线，所述第一转换线位于所述第一显示区和所述第二显示区的交界处，所述第一转换线与所述第一子信号线、所述第二子信号线异层设置，所述屏蔽层平行于所述第一转换线。
在本发明的一些实施例中，所述屏蔽层在所述显示面板的厚度方向上的正投影完全覆盖靠近所述第一显示区的所述连接部在所述显示面板上的厚度方向上的正投影，所述屏蔽层在所述显示面板上的正投影与所述第一转换线在所述显示面板上的正投影之间具有间隙。
本发明实施例还提供一种电子设备，所述电子设备包括显示面板和感光单元，所述感光单元对应所述显示面板的所述第一显示区设置，所述显示面板包括：
多个第一像素驱动电路，设于所述第二显示区，所述第一像素驱动电路包括多个薄膜晶体管；
多个第二像素驱动电路，设于所述第一显示区的过渡显示区；
半导体层，包括多个所述薄膜晶体管的有源部及多个连接相邻的所述有源部的连接部；
多条第一信号线，包括电连接所述第一像素驱动电路的第一子信号线、电连接所述第二像素驱动电路的第二子信号线，以及电连接所述第一子信号线和对应的所述第二子信号线的第一转换线，所述第一转换线与所述第一子信号线、所述第二子信号线异层设置；其中，
所述第一转换线和所述半导体层之间设有屏蔽层，且所述屏蔽层在所述显示面板的厚度方向上的正投影至少部分覆盖靠近所述第一转换线的所述连接部在所述显示面板的所述厚度方向上的正投影。
在本发明的一些实施例中，所述第一信号线包括扫描信号线，所述第一子信号线电连接同一行所述第一像素驱动电路，所述第二子信号线电连接同一行所述第二像素驱动电路。
在本发明的一些实施例中，多个所述薄膜晶体管包括相互电连接的第一晶体管、第二晶体管及第三晶体管，所述显示面板包括位于所述第二显示区的多个发光器件，所述第一晶体管、所述第三晶体管以及所述发光器件串联在第一电压线和第二电压线之间以形成回路，所述第三晶体管的源极电连接于所述第一晶体管的漏极和所述第二晶体管的源极之间，所述第三晶体管的漏极电连接所述第一晶体管的栅极，其中，
所述连接部包括将所述第一晶体管的有源部与所述第二晶体管的有源部以及所述第三晶体管的有源部相互连接的第一连接部，所述第一连接部靠近对应的所述第一转换线，且所述屏蔽层在所述显示面板上的厚度方向上的正投影至少部分覆盖所述第一连接部。
在本发明的一些实施例中，所述显示面板包括设于所述半导体层上的源漏极金属层，所述屏蔽层设于所述半导体层和所述源漏极金属层之间。
在本发明的一些实施例中，所述显示面板包括设于所述半导体层上的栅极金属层、设于所述栅极金属层和所述源漏极金属层之间的中间金属层，所述屏蔽层设于所述中间金属层和所述源漏极金属层之间，所述栅极金属层包括所述第一晶体管的所述栅极，所述中间金属层包括金属板，所述金属板电连接于所述第一晶体管的源极和所述第一电压线之间，所述第一晶体管的栅极在所述显示面板的所述厚度方向上的正投影与所述金属板在所述显示面板的所述厚度方向上的正投影重叠，所述屏蔽层在所述显示面板的所述厚度方向上的正投影与所述栅极在所述显示面板的所述厚度方向上的正投影，以及与所述金属板在所述显示面板的厚度方向上的正投影均不重叠。
 有益效果
本发明实施例提供一种显示面板和电子设备，显示面板包括位于第二显示区的第一像素驱动电路、位于第一显示区的第二像素驱动电路、多条第一信号线以及半导体层，半导体层包括薄膜晶体管的有源部和连接有源部的连接部，第一信号线包括连接第一像素驱动电路的第一子信号线、连接第二像素驱动电路的第二子信号线，以及连接第一子信号线和第二子信号线的第一转换线，在第一转换线和半导体层之间设置屏蔽层，且将屏蔽层至少部分覆盖靠近第一转换线的连接部，能够改善第一显示区和第二显示区的交界处的像素和第二显示区的其他位置的像素之间的亮度差异，提升显示面板的显示均一性。
 附图说明
图1为本发明实施例提供的显示面板的平面示意图。
图2为本发明实施例提供的第一显示区和第二显示区的交界附近的像素分布示意图。
图3为本发明实施例提供的所述显示面板的第一显示区的局部放大示意图。
图4为本发明实施例提供的第一显示区AA1和第二显示区AA2的交界处的局部放大平面示意图。
图5为本发明实施例提供的第一像素驱动电路的半导体层的平面示意图。
图6为本发明实施例提供的第一像素驱动电路的平面示意图。
图7为本发明实施例提供的第一像素驱动电路与屏蔽层位置关系的平面示意图。
图8为本发明实施例提供的第一像素驱动电路的电路原理示意图。
图9为本发明实施例提供的显示面板的膜层叠构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
请参阅图1，图1为本发明实施例提供的显示面板的平面示意图。本发明实施例提供一种显示面板100，所述显示面板可为有机发光二极管显示面板。所述显示面板100包括第一显示区AA1和第二显示区AA2，所述第一显示区AA1的面积小于所述第二显示区AA2的面积，所述第一显示区AA1的透光率大于所述第二显示区AA2的透光率，所述第二显示区AA2用于常规显示，所述第一显示区AA1在用于显示的同时，还具有高的透光率，可将摄像头等感光元件设于所述显示面板100的所述第一显示区AA1的下方，实现屏下摄像头显示技术。
所述显示面板100包括多个第一像素驱动电路和多个第二像素驱动电路，所述第一像素驱动电路位于所述第二显示区AA2，所述第一像素驱动电路位于所述第一显示区AA1，所述第一像素驱动电路和所述第二像素驱动均包括多个薄膜晶体管。为了提高所述第一显示区AA1的透光率，所述第一显示区AA1的所述第二像素驱动电路的密度低于所述第二显示区AA2的第一像素驱动电路的密度。
请参阅图2，图2为本发明实施例提供的第一显示区和第二显示区的交界附近的像素分布示意图。所述显示面板100包括多个第一像素单元11和多个第二像素单元12，所述第一像素单元11位于所述第二显示区AA2，所述第一像素驱动电路驱动所述第一像素单元11发光，所述第二像素单元12位于所述第一显示区AA1，所述第二像素驱动电路驱动所述第二像素单元12发光。
任一所述第一像素单元11包括第一红色子像素11a、第一绿色子像素11b、第一蓝色子像素11c，任一所述第二像素单元12包括第二红色子像素12a、第二绿色子像素12b、第二蓝色子像素12c。每一子像素包括一发光器件，所述发光器件可为有机发光二极管。
在本发明的实施例中，所述第一红色子像素11a的形状可为八边形，所述一绿色子像素11b的形状可为椭圆形，所述第一蓝色子像素11c的形状可为八变形。所述第二红色子像素12a的形状可为圆形，所述第二绿色子像素12b的形状可为圆形，所述第二蓝色子像素12c的形状可为圆形。
所述第二显示区AA2与所述第一显示区AA1相同颜色的子像素的开口面积不同，所述第二显示区AA2的红、绿、蓝子像素的开口面积分别大于所述第一显示区AA1的对应的红、绿、蓝子像素的开口面积，通过减小第一显示区AA1的单个子像素的开口面积，可为第二像素驱动电路的布置提供更大的容纳空间。
进一步地，一个所述第二像素驱动电路可驱动所述第一显示区AA1的多个颜色相同的子像素发光，以减少第二像素驱动电路占用的空间。例如，两个第二红色子像素12a可由同一个第二像素驱动电路驱动，四个第二绿色子像素12b可由同一个第二像素驱动电路驱动，两个第二蓝色子像素12c可由同一个第二像素驱动电路驱动。一个所述第一像素驱动电路可驱动所述第二显示区AA2的一个子像素发光。
所述第一显示区AA1设置有多个第一像素重复单元101A，所述第二显示区AA2设置有多个第二像素重复单元102A。在相同显示面积内，所述第一显示区AA1包含的所述第一像素重复单元101A的数量与所述第二显示区AA2包含的第二像素重复单元102A的数量相等，即所述第一显示区AA1与所述第二显示区AA2具有相同的像素密度(Pixel Per Inch，PPI)，能够降低所述第二显示区AA2的显示画面与所述第一显示区AA1的显示画面的整体显示差异。
所述第一像素重复单元101A和第二像素重复单元102A的排布方式相同，排布方式包括各个子像素的排布规律、排布距离等。所述第一像素重复单元101A和所述第二像素重复单元102A均采用pentile的排列方式，以所述第二像素重复单元102A为例，所述第二像素重复单元102A采用4×4的矩阵排列方式，相邻行的子像素错位排列，相邻列的子像素错位排列，所述第二像素重复单元102A包括两个第一红色子像素11a、四个第一绿色子像素11b、两个第一蓝色子像素11c，第一红色子像素11a和第一蓝色子像素11c位于同行且依次交替分布，第一绿色子像素11b与第一红色子像素11a、第一蓝色子像素11c呈交替行排布。
请参阅图1，在本发明的实施例中，所述第一显示区AA1包括透光显示区101和设于所述透光显示区101外的过渡显示区102，所述过渡显示区102位于所述透光显示区101和所述过渡显示区102之间。所述第二显示区AA2的面积大于所述过渡显示区102的面积和所述透光显示区101的面积，所述透光显示区101在实现显示的同时具有高的透明度，所述透光显示区101的透光率大于所述过渡显示区102的透光率和所述第二显示区AA2的透光率。
摄像头等感光元件可与所述透光显示区101对应设置，为提高透光显示区101的透光率，可将全部的第二像素驱动电路均设置在过渡显示区102内。
所述透光显示区101的形状可为圆形，所述过渡显示区102环绕所述透光显示区101，所述第二显示区AA2环绕所述过渡显示区102，所述过渡显示区102的形状可为环形，具体可为圆环形。在其他实施例中，所述透光显示区101还可为方形、菱形、椭圆形等其他形状，对应地，所述过渡显示区102还可为方环形、椭圆环形。
请参阅图3，图3为所述显示面板的第一显示区的局部放大示意图。若干个所述第二像素驱动电路集中布置以形成像素驱动岛13，即一个所述像素驱动岛13包括若干个第二像素驱动电路。多个所述像素驱动岛13环绕在所述透光显示区101的上下两侧，连接所述像素驱动岛13之间的信号线位于所述过渡显示区102内，所述信号线包括数据线VDATA、扫描信号线SCAN、第一电压线（直流电源信号线VDD）、控制信号线EM、复位信号线RESET、初始化信号线VI、第二电压线（直流低电压信号线VSS，通常接地）等。
请参阅图4，图4为第一显示区AA1和第二显示区AA2的交界处的局部放大平面示意图。在上述设计中，由于所述第二像素驱动电路的密度与所述第一像素驱动电路的密度存在差异，因此显示面板的第一信号线（如扫描信号线SCAN、控制信号线EM）在第二显示区AA2和第一显示区AA1的交界处会存在换线。
本实施例中的所述第一信号线包括电连接所述第一像素驱动电路的第一子信号线、电连接所述第二像素驱动电路的第二子信号线，以及电连接所述第一子信号线和对应的所述第二子信号线的第一转换线，所述第一转换线与所述第一子信号线、所述第二子信号线异层设置。
在本发明的实施例中，所述第一子信号线可位于所述第一显示区，所述第二子信号线位于所述第二显示区，所述第一转换线位于所述第一显示区和所述第二显示区的交界处。
请继续参阅图4，所述显示面板除开在换线处以外的其他位置的布线排列规整，导致交界处靠近该换线位置的像素驱动电路（图4中的A处）所处布线环境与其他位置的第一像素驱动电路或第二像素驱动电路所处布线环境存在差异，第一信号线的高低灰阶跳变导致的电容耦合作用对换线位置的像素驱动电路电性的影响和对其他位置第一像素驱动电路或第二像素驱动电路电性的影响之间存在差异，导致边界产生Mura现象。
所述像素驱动电路可位于所述第一显示区AA1，也可位于所述第二显示区AA2，但所述像素驱动电路需满足位于两个区域交界处。本实施例位于交界处的像素驱动电路以位于所述第二显示区AA2的第一像素驱动电路为例进行说明。
本发明实施例以扫描信号线SCAN产生的高低跳变对换线位置和其他位置产生的电性影响存在差异为例进行说明。
具体地，所述显示面板100包括多条扫描信号线SCAN，所述扫描信号线SCAN包括第一子信号线21、第二子信号线22以及第一转换线23，所述第一转换线23电连接所述第一子信号线21和所述第二子信号线22，所述第一子信号线21电连接同一行第一像素驱动电路，所述第二子信号线22电连接同一行第二像素驱动电路。所述第一子信号线21和所述第二子信号线22传递同一扫描信号，所述第一子信号线21和所述第二子信号线22不处于同一水平位置，即所述第一子信号线21和所述第二子信号线22的连线不在同一直线上。
请参阅图4和图5，所述发光控制信号线EM包括电连接同一行第一像素驱动电路的第一发光控制信号线51、电连接同一行第二像素驱动电路的第二发光控制信号线（未示出），以及电连接所述第一发光控制信号线51和对应的所述第二发光控制信号线的第二转换线，所述第一发光控制信号线51和所述第二发光控制信号线传递同一发光控制信号，所述第一发光控制信号线51和所述第二发光控制信号线不处于同一水平位置。
扫描信号线SCAN的第一转换线23与其靠近的第一驱动电路（图4的A处）的有源部膜层相邻，第一转换线23会与相邻的有源部膜层产生寄生电容（图4的B处），发生电容耦合作用，因扫描信号线SCAN发生高低灰阶跳变导致的信号串扰对交界处的第一像素单元11和对其他位置的第一像素单元11产生的影响存在差异，因此会导致交界处与第二显示区AA2的其他位置存在Mura，降低显示面板100的显示效果。
本发明实施例针对上述缺陷，在靠近所述第一转换线23的有源部膜层上对应设置屏蔽层，以切割第一转换线23与邻近的有源部膜层之间的电场，减少二者之间的寄生电容，进而减小对该处的第一像素驱动电路的对应点的电位受到的扰动影响。
具体地，请参阅图5和图6，图5为本发明实施例提供的第一像素驱动电路的半导体层的平面示意图，图6为本发明实施例提供的第一像素驱动电路的平面示意图。所述第一像素驱动电路和所述第二像素驱动电路均包括多个薄膜晶体管，所述薄膜晶体管包括源极、漏极以及有源部。
请参阅图7，图7为第一像素驱动电路与屏蔽层位置关系的平面示意图。所述显示面板100包括半导体层30，所述半导体层30设于所述第一像素驱动电路和所述第二像素驱动电路所对应的区域。所述半导体层30用于形成多个薄膜晶体管的有源部及多个连接部31，所述连接部31用于将需要连接的有源部之间连接起来。所述第一转换线23和所述半导体层30之间设有屏蔽层40，所述屏蔽层40在所述显示面板100的厚度方向上的正投影至少部分覆盖靠近所述第一显示区AA1的所述连接部31在所述显示面板100的厚度方向上的正投影。
具体地，所述屏蔽层40在所述显示面板100的厚度方向上的正投影至少部分覆盖靠近第一转换线23的连接部31，以减少第一转换线23和靠近所述第一转换线23的连接部31之间的寄生电容。所述屏蔽层40的材料包括钼（Mo）金属。
优选地，所述屏蔽层40在所述显示面板100上的正投影可完全覆盖靠近所述第一转换线23的所述连接部。但需注意的是，屏蔽层40在显示面板100的厚度方向上的正投影与其邻近的金属器件（如栅极、电容板等）在显示面板100的厚度方向上的正投影不重叠，所述屏蔽层40在所述显示面板100上的正投影与所述第一转换线23在所述显示面板100上的正投影之间具有间隙，避免对其他金属器件的功能及信号产生干扰。
请参阅图3，在本发明的实施例中，所述第一子信号线21位于所述第二显示区AA2，所述第二子信号线22位于所述过渡显示区102，位于所述过渡显示区102周边且靠近所述第一转换线23的多个所述第二像素驱动电路对应设置有所述屏蔽层40。
进一步地，所述第二显示区AA2围绕所述过渡显示区102，所述第一显示区AA1包括与所述第一子信号线21平行的对称轴L1，所述屏蔽层40关于所述对称轴L1对称。一种实施例中，所述屏蔽层40平行于所述第一转换线23，避免屏蔽层40占据过多的布线空间。
请参阅图7和图8，图8为本发明实施例提供的第一像素驱动电路的电路原理示意图。所述第一像素驱动电路可为7T1C（7个薄膜晶体管和1个存储电容）结构或者4T1C（4个薄膜晶体管和1个存储电容）等结构，但不以此为限。本发明实施例以7T1C结构为例进行说明。
与所述第一像素驱动电路连接的走线包括数据线VDATA、初始化信号线VI、复位信号线RESET，扫描信号线SCAN、发光控制信号线EM，以及直流电源信号线VDD。在本发明实施例中，第n-1级复位信号线RESET（n-1）和第n-1级扫描信号线SCAN(n)传输的信号来源于同一信号，第n级复位信号线RESET（n）和第n级扫描信号线SCAN(n)传输的信号来源于同一信号，即第n-1级复位信号线RESET（n-1）的信号传输可由第n-1级扫描信号线SCAN(n)传输，所述第n级复位信号线RESET（n）的信号传输可由第n级扫描信号线SCAN(n)传输。
请参阅图7和图8，多个所述薄膜晶体管包括相互电连接的第一晶体管、第二晶体管及第三晶体管，所述显示面板包括位于所述第二显示区的多个发光器件，所述第一晶体管、所述第三晶体管以及所述发光器件串联在第一电压线（直流电源信号线VDD）和第二电压线（直流低电压信号线VSS）之间以形成回路，所述第三晶体管的源极电连接于所述第一晶体管的漏极和所述第二晶体管的源极之间，所述第三晶体管的漏极电连接所述第一晶体管的栅极，所述第三晶体管的源极电连接于所述第一晶体管的漏极和所述第二晶体管的源极之间。
具体地，第一像素驱动电路1011包括第一晶体管（驱动晶体管）T1、开关晶体管T2、第三晶体管（补偿晶体管）T3、初始化晶体管T4、第二发光控制晶体管T5、第二晶体管（第一发光控制晶体管）T6、阳极复位晶体管T7以及存储电容Cst。上述7个晶体管T1~T7可为P型晶体管。所述补偿晶体管T3和所述初始化晶体管T4可为双栅极晶体管。
具体地，所述开关晶体管T2的栅极电连接第n级扫描信号线SCAN(n)，其漏极电连接数据线VDATA，其源极电连接所述第二发光控制晶体管T5的漏极，所述第二发光控制晶体管T5的栅极电连接发光控制信号线EM(n)，所述第二发光控制晶体管T5的源极电连接直流电源信号线VDD，初始化晶体管T4的栅极电连接第n-1级扫描信号线SCAN(n-1)，初始化晶体管T4的源极电连接初始化信号线VI，初始化晶体管T4的漏极电连接驱动晶体管的栅极，第一发光控制晶体管T6的栅极电连接发光控制信号线EM(n)，第一发光控制晶体管T6的源极电连接所述驱动晶体管T1的漏极以及补偿晶体管T3的漏极，第一发光控制晶体管T6的漏极电连接一发光器件的阳极，发光器件的阴极电连接所述第二电压线VSS。补偿晶体管T3的栅极电连接对应的一所述扫描信号线SCAN（n），补偿晶体管T3的源极电连接所述驱动晶体管T1的栅极，驱动晶体管T1的栅极还作为存储电容的一电极板，存储电容的另一电极板与第二发光控制晶体管T5的源极电连接，阳极复位晶体管T7的栅极电连接第n级扫描信号线SCAN(n)，阳极复位晶体管T7的源极电连接初始化信号线VI，阳极复位晶体管T7的漏极电连接发光器件的阳极。
请参阅图8，所述第一像素驱动电路包括三个工作阶段：复位阶段、充电阶段以及发光阶段。复位阶段时：扫描信号线Scan(n-1)置为低电平，初始化晶体管T4打开，驱动晶体管T1的栅极复位到初始电压Vi。充电阶段：扫描信号线Scan(n)置为低电平，开关晶体管T2和补偿晶体管T3打开，对驱动晶体管T1的栅极电位充电至Vdata–Vth（Vth为驱动晶体管T1的阈值电压），与此同时，阳极复位晶体管T7打开，发光器件的阳极电位复位到初始电压Vi。发光阶段：发光控制信号线EM(n)置为低电平，发光器件发光。在充电阶段中，T1~T3打开，T4~T6关闭。此时，数据线VDATA通过T1~T3路径对驱动晶体管T1的栅极充电。当驱动晶体管T1的栅极电位上升到Vdata-Vth，驱动晶体管T1截止，其栅极电位不再上。
所述第二像素驱动电路的架构可与所述第一像素驱动电路的架构相同，也可不同，这里不做限制。
请参阅图5，半导体层30包括驱动晶体管T1的有源部32、开关晶体管T2的有源部、补偿晶体管T3的有源部33、初始化晶体管T4的有源部、第二发光控制晶体管T5的有源部、第一发光控制晶体管T6的有源部，阳极复位晶体管T7的有源部，以及将需要连接的有源部连接起来的连接部31。上述各个薄膜晶体管的有源部和连接部经半导体层30图案化后形成，半导体层30的制备材料可以为多晶硅。
请参阅图5，在本发明的实施例中，所述连接部31包括将所述驱动晶体管T1的有源部32与所述第一发光控制晶体管T6的有源部34以及所述补偿晶体管T3的有源部33相互连接的第一连接部31a，所述第一连接部31a靠近对应的所述第一转换线23。所述第一连接部31a和所述第一转换线23之间会产生寄生电容，在第一转换线23发生高低灰阶跳变时，由于电容耦合作用，会导致第一像素驱动电路的C点电位（参阅图8）发生跳变，该跳变会进一步影响像素中Q点电位，导致交界处像素亮度显示异常，出现Mura。因此，在所述第一连接部31a上对应设置屏蔽层40，屏蔽层40在所述显示面板100上的厚度方向上的正投影至少部分覆盖所述第一连接部31a，可切割第一连接部31a与第一转换线23之间的电场，有效减少二者之间的寄生电容，降低对C点电位的扰动影响。
请参阅图7，在本发明的实施例中，所述第一连接部31a设置于相邻的所述发光控制线EM和所述扫描信号线SCAN之间。
具体地，所述第一发光控制信号线51与所述第一子信号线21平行，所述第二发光控制信号线与所述第二子信号线平行，其中，所述第一连接部31a位于对应的所述第一发光控制信号线51和所述第一子信号线21之间。
请参阅图9，图9为本发明实施例提供的显示面板的膜层叠构图。所述显示面板100包括衬底10，所述半导体层30设于所述衬底10上，所述半导体层30与所述衬底10之间可层叠有阻挡层、缓冲层，栅极金属层设于所述半导体层30上，所述栅极金属层包括薄膜晶体管的栅极（如驱动晶体管T1的栅极24）、第一子信号线21、第二子信号线22、发光控制信号线EM。
中间金属层设于栅极金属层上，并通过第一栅极绝缘层与所述栅极金属层绝缘。所述中间金属层包括金属板52、初始化信号线VI，所述金属板52电连接于所述第一晶体管T1的源极和所述第一电压线VDD之间，所述金属板52用于形成所述存储电容Cst的一电极板，所述金属板52在所述显示面板的厚度方向上的正投影与驱动晶体管T1的栅极24在所述显示面板的厚度方向上的正投影重叠，所述金属板52与所述驱动晶体管T1的栅极形成存储电容Cst。
源漏极金属层设于所述中间金属层上，并通过层间绝缘层绝缘。所述源漏极金属层包括薄膜晶体管的源、漏极（如驱动晶体管的源、漏极61）、数据线VDATA，源极和漏极通过相应的过孔与对应的有源部连接。
在本发明的实施例中，所述第一转换线23（图9未示出）可与所述源漏极金属层同层设置，所述第一转换线23通过相应的过孔与第一子信号线21和第二子信号线22连接。
所述屏蔽层40设于所述半导体层30和所述源漏极金属层之间。具体地，所述屏蔽层40设于所述中间金属层和所述源漏极金属层之间，通过绝缘层隔开，具体地，所述屏蔽层40对应所述第一连接部31a设置，所述屏蔽层40在显示面板上的正投影覆盖所述第一连接部31a在所述显示面板上的正投影。
优选地，请参阅图7，所述屏蔽层40在所述显示面板100的厚度方向上的正投影与所述第一晶体管T1的栅极在所述显示面板100的厚度方向上的正投影不重叠。所述屏蔽层40在所述显示面板100的厚度方向上的正投影与所述金属板在所述显示面板100的厚度方向上的正投影不重叠。所述屏蔽层40避开第一晶体管的栅极和金属板的设计，可避免屏蔽层40对存储电容Cst造成影响。
所述发光器件80的阳极设于所述源漏极金属层上，并通过桥接线层70与所述驱动晶体管T1的源极/漏极电性连接。
基于上述显示面板100，本发明实施例还提供一种电子设备，包括上述显示面板100和感光单元，所述感光单元与显示面板100的第一显示区AA1对应设置，所述感光单元包括摄像头等感光元件。
综上，本发明实施例提供一种显示面板和电子设备，显示面板包括位于第二显示区的第一像素驱动电路、位于第一显示区的第二像素驱动电路、多条扫描信号线以及半导体层，半导体层包括薄膜晶体管的有源部和连接有源部的连接部，扫描信号线包括连接同一行第一像素驱动电路的第一子信号线、连接同一行第二像素驱动电路的第二子信号线，以及连接第一子信号线和第二子信号线的第一转换线，在第一转换线和半导体层之间设置屏蔽层，且将屏蔽层至少部分覆盖靠近第一转换线的连接部，能够改善第一显示区和第二显示区的交界处的像素和第二显示区的其他位置的像素之间的亮度差异，提升显示面板的显示均一性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本发明实施例所提供的一种显示面板及电子设备进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，包括第一显示区和设于所述第一显示区外的第二显示区，所述第二显示区的透光率小于所述第一显示区的透光率，其中，所述显示面板包括：
    多个第一像素驱动电路，设于所述第二显示区，所述第一像素驱动电路包括多个薄膜晶体管；
    多个第二像素驱动电路，设于所述第一显示区的过渡显示区；
    半导体层，包括多个所述薄膜晶体管的有源部及多个连接相邻的所述有源部的连接部；
    多条第一信号线，包括电连接所述第一像素驱动电路的第一子信号线、电连接所述第二像素驱动电路的第二子信号线，以及电连接所述第一子信号线和对应的所述第二子信号线的第一转换线，所述第一转换线与所述第一子信号线、所述第二子信号线异层设置；其中，
    所述第一转换线和所述半导体层之间设有屏蔽层，且所述屏蔽层在所述显示面板的厚度方向上的正投影至少部分覆盖靠近所述第一转换线的所述连接部在所述显示面板的所述厚度方向上的正投影。
  2. 根据权利要求1所述的显示面板，其中，所述第一信号线包括扫描信号线，所述第一子信号线电连接同一行所述第一像素驱动电路，所述第二子信号线电连接同一行所述第二像素驱动电路。
  3. 根据权利要求1所述的显示面板，其中，多个所述薄膜晶体管包括相互电连接的第一晶体管、第二晶体管及第三晶体管，所述显示面板包括位于所述第二显示区的多个发光器件，所述第一晶体管、所述第三晶体管以及所述发光器件串联在第一电压线和第二电压线之间以形成回路，所述第三晶体管的源极电连接于所述第一晶体管的漏极和所述第二晶体管的源极之间，所述第三晶体管的漏极电连接所述第一晶体管的栅极，其中，
    所述连接部包括将所述第一晶体管的有源部与所述第二晶体管的有源部以及所述第三晶体管的有源部相互连接的第一连接部，所述第一连接部靠近对应的所述第一转换线，且所述屏蔽层在所述显示面板上的厚度方向上的正投影至少部分覆盖所述第一连接部。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板包括多条发光控制信号线，所述第二晶体管的栅极电连接一对应的所述发光控制信号线，所述第三晶体管的栅极电连接对应的一所述扫描信号线。
  5. 根据权利要求4所述的显示面板，其中，所述第一连接部位于相邻的所述发光控制信号线和所述扫描信号线之间。
  6. 根据权利要求5所述的显示面板，其中，所述发光控制信号线包括电连接同一行所述第一像素驱动电路的第一发光控制信号线、电连接同一行所述第二像素驱动电路的第二发光控制信号线，以及电连接所述第一发光控制信号线和对应的所述第二发光控制信号线的第二转换线，所述第一发光控制信号线与所述第一子信号线平行，所述第二发光控制信号线与所述第二子信号线平行，其中，
    所述第一连接部位于对应的所述第一发光控制信号线和所述第一子信号线之间。
  7. 根据权利要求3所述的显示面板，其中，所述显示面板包括设于所述半导体层上的源漏极金属层，所述屏蔽层设于所述半导体层和所述源漏极金属层之间。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板包括设于所述半导体层上的栅极金属层、设于所述栅极金属层和所述源漏极金属层之间的中间金属层，所述屏蔽层设于所述中间金属层和所述源漏极金属层之间，所述栅极金属层包括所述第一晶体管的所述栅极，所述中间金属层包括金属板，所述金属板电连接于所述第一晶体管的源极和所述第一电压线之间，所述第一晶体管的栅极在所述显示面板的所述厚度方向上的正投影与所述金属板在所述显示面板的所述厚度方向上的正投影重叠，所述屏蔽层在所述显示面板的所述厚度方向上的正投影与所述栅极在所述显示面板的所述厚度方向上的正投影，以及与所述金属板在所述显示面板的厚度方向上的正投影均不重叠。
  9. 根据权利要求8所述的显示面板，其中，所述栅极金属层包括所述第一子信号线以及所述第二子信号线，所述第一转换线与所述源漏极金属层同层设置。
  10. 根据权利要求1所述的显示面板，其中，所述第一显示区包括透光显示区，所述过渡显示区设于所述第二显示区和所述透光显示区之间，所述显示面板包括：
    第一像素单元，位于所述第二显示区，所述第一像素驱动电路驱动所述第一像素单元发光；
    第二像素单元，位于所述透光显示区和所述过渡显示区，所述第二像素驱动电路驱动所述第二像素单元发光。
  11. 根据权利要求1所述的显示面板，其中，所述第一子信号线位于所述第二显示区，所述第二子信号线位于所述过渡显示区，位于所述过渡显示区周边且靠近所述第一转换线的多个所述第二像素驱动电路对应设置有所述屏蔽层。
  12. 根据权利要求11所述的显示面板，其中，所述第二显示区围绕所述过渡显示区，所述第一显示区包括与所述第一子信号线平行的对称轴，所述屏蔽层关于所述对称轴对称。
  13. 一种显示面板，包括第一显示区、设于所述第一显示区外的第二显示区，所述第二显示区的透光率小于所述第一显示区的透光率，其中，所述显示面板包括：
    多个像素驱动电路，位于所述第一显示区和所述第二显示区的交界处，所述像素驱动电路包括多个薄膜晶体管；以及
    半导体层，包括多个所述薄膜晶体管的有源部及多个连接相邻的所述有源部的连接部；
    其中，所述半导体层上设有屏蔽层，且所述屏蔽层在所述显示面板的厚度方向上的正投影至少部分覆盖靠近所述第一显示区的所述连接部在所述显示面板的厚度方向上的正投影。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板包括多条第一信号线，所述第一信号线包括位于所述第一显示区的第一子信号线、位于第二显示区的第二子信号线，以及电连接所述第一子信号线和所述第二子信号线的第一转换线，所述第一转换线位于所述第一显示区和所述第二显示区的交界处，所述第一转换线与所述第一子信号线、所述第二子信号线异层设置，所述屏蔽层平行于所述第一转换线。
  15. 根据权利要求14所述的显示面板，其中，所述屏蔽层在所述显示面板的厚度方向上的正投影完全覆盖靠近所述第一显示区的所述连接部在所述显示面板上的所述厚度方向上的正投影，所述屏蔽层在所述显示面板的所述厚度方向上的正投影与所述第一转换线在所述显示面板的所述厚度方向上的正投影之间具有间隙。
  16. 一种电子设备，其中，所述电子设备包括显示面板和感光单元，所述感光单元对应所述显示面板的所述第一显示区设置，所述显示面板包括：
    多个第一像素驱动电路，设于所述第二显示区，所述第一像素驱动电路包括多个薄膜晶体管；
    多个第二像素驱动电路，设于所述第一显示区的过渡显示区；
    半导体层，包括多个所述薄膜晶体管的有源部及多个连接相邻的所述有源部的连接部；
    多条第一信号线，包括电连接所述第一像素驱动电路的第一子信号线、电连接所述第二像素驱动电路的第二子信号线，以及电连接所述第一子信号线和对应的所述第二子信号线的第一转换线，所述第一转换线与所述第一子信号线、所述第二子信号线异层设置；其中，
    所述第一转换线和所述半导体层之间设有屏蔽层，且所述屏蔽层在所述显示面板的厚度方向上的正投影至少部分覆盖靠近所述第一转换线的所述连接部在所述显示面板的所述厚度方向上的正投影。
  17. 根据权利要求16所述的电子设备，其中，所述第一信号线包括扫描信号线，所述第一子信号线电连接同一行所述第一像素驱动电路，所述第二子信号线电连接同一行所述第二像素驱动电路。
  18. 根据权利要求17所述的电子设备，其中，多个所述薄膜晶体管包括相互电连接的第一晶体管、第二晶体管及第三晶体管，所述显示面板包括位于所述第二显示区的多个发光器件，所述第一晶体管、所述第三晶体管以及所述发光器件串联在第一电压线和第二电压线之间以形成回路，所述第三晶体管的源极电连接于所述第一晶体管的漏极和所述第二晶体管的源极之间，所述第三晶体管的漏极电连接所述第一晶体管的栅极，其中，
    所述连接部包括将所述第一晶体管的有源部与所述第二晶体管的有源部以及所述第三晶体管的有源部相互连接的第一连接部，所述第一连接部靠近对应的所述第一转换线，且所述屏蔽层在所述显示面板上的厚度方向上的正投影至少部分覆盖所述第一连接部。
  19. 根据权利要求18所述的电子设备，其中，所述显示面板包括设于所述半导体层上的源漏极金属层，所述屏蔽层设于所述半导体层和所述源漏极金属层之间。
  20. 根据权利要求19所述的电子设备，其中，所述显示面板包括设于所述半导体层上的栅极金属层、设于所述栅极金属层和所述源漏极金属层之间的中间金属层，所述屏蔽层设于所述中间金属层和所述源漏极金属层之间，所述栅极金属层包括所述第一晶体管的所述栅极，所述中间金属层包括金属板，所述金属板电连接于所述第一晶体管的源极和所述第一电压线之间，所述第一晶体管的栅极在所述显示面板的所述厚度方向上的正投影与所述金属板在所述显示面板的所述厚度方向上的正投影重叠，所述屏蔽层在所述显示面板的所述厚度方向上的正投影与所述栅极在所述显示面板的所述厚度方向上的正投影，以及与所述金属板在所述显示面板的厚度方向上的正投影均不重叠。
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