WO2022165712A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2022165712A1
WO2022165712A1 PCT/CN2021/075289 CN2021075289W WO2022165712A1 WO 2022165712 A1 WO2022165712 A1 WO 2022165712A1 CN 2021075289 W CN2021075289 W CN 2021075289W WO 2022165712 A1 WO2022165712 A1 WO 2022165712A1
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WIPO (PCT)
Prior art keywords
transistor
sub
signal line
line
stage
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PCT/CN2021/075289
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English (en)
French (fr)
Inventor
韩龙
刘利宾
皇甫鲁江
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112021001197.9T priority Critical patent/DE112021001197T5/de
Priority to US17/638,836 priority patent/US11837142B2/en
Priority to PCT/CN2021/075289 priority patent/WO2022165712A1/zh
Priority to CN202180000156.8A priority patent/CN115191036A/zh
Publication of WO2022165712A1 publication Critical patent/WO2022165712A1/zh
Priority to US18/494,796 priority patent/US20240078956A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/066—Adjustment of display parameters for control of contrast

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • OLED Organic Light Emitting Diode
  • Organic Light Emitting Diode Organic Light Emitting Diode
  • the purpose of the present disclosure is to provide an array substrate and a display device.
  • an array substrate wherein a plurality of pixel units are arranged in an array, the pixel units include a plurality of sub-pixels, and the array substrate includes:
  • a plurality of initialization signal lines arranged on a conductive layer, extending along the first direction and arranged at intervals along the second direction, for providing initialization signals to each of the sub-pixels; the first direction and the second direction intersect;
  • the projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate are both intersected and connected through via holes, so that the initialization signal lines and the connection lines are connected to the substrate.
  • the projections on the substrate form a grid-like structure.
  • the array substrate includes a base substrate and a first gate line layer, a second gate line layer, a source and drain layer, and an anode that are sequentially stacked on the base substrate.
  • the first direction is the row direction
  • the second direction is the column direction;
  • the initialization signal line is set on the second gate layer;
  • the connection line is set on the source-drain layer or the anode layer .
  • the array substrate further includes:
  • a plurality of scan lines arranged in the first gate line layer, extending along the row direction and arranged at intervals along the column direction, for providing scan signals to each of the sub-pixels;
  • a plurality of reset signal lines are arranged on the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used for providing reset signals to each of the sub-pixels.
  • the projection of the initialization signal line on the base substrate is located between the reset signal line and the scan line of the upper-level sub-pixel between projections, and the projections of the initialization signal line, the reset signal line, and the scan line do not overlap.
  • the projection of the initialization signal line on the base substrate is located at the projection of the reset signal line away from the scanning of the sub-pixel of the previous level one side of the line, and the projections of the initialization signal line, the reset signal line, and the scan line do not overlap.
  • the reset signal line and the scan line of the sub-pixel of the previous level are connected as one; the initialization signal line is on the base substrate The projection intersects the projection of the reset signal line.
  • the initialization signal line includes a plurality of signal segments separated from each other, and each of the signal segments corresponds to each of the pixel units one-to-one; wherein, each of the signal segments corresponds to each of the pixel units. At least one of the sub-pixel regions in the pixel unit has no overlap with the projection of the reset signal line, and the projections of the reset signal line in the remaining sub-pixel regions all intersect.
  • the number of the connection lines is equal to the number of sub-pixels in the row direction, and in the row direction, the initialization signal line and each of the connection lines are in each sub-pixel
  • the pixel regions are all electrically connected through vias; or, the number of the connection lines is smaller than the number of sub-pixels in the row direction, and in the row direction, the initialization signal line and each of the connection lines pass through some sub-pixel regions Via electrical connection.
  • the array substrate further includes:
  • a plurality of power lines arranged on the source and drain layers, extending along the column direction and spaced along the row direction, for providing power signals to each of the sub-pixels;
  • a plurality of data lines are provided on the source and drain layers, extend along the column direction and are arranged at intervals along the row direction, and are used for providing data signals to each of the sub-pixels.
  • the sub-pixel includes an anode, the connection line and the anode are both provided in the anode layer, and the connection line is insulated from the anode.
  • the array substrate further includes a plurality of first conductive connecting portions, which are disposed on the source and drain layers and are distributed on the projections of the initialization signal lines and the connecting lines.
  • the projection of the first conductive connection part on the base substrate has an overlapping area with the initial signal line and the connection line, respectively, and the first conductive connection
  • the first conductive connecting portion is connected to the connection line through a via hole.
  • connection line is provided in the source-drain layer; in the sub-pixel region, the initialization signal line includes a main body segment and an extension segment connected to each other, and the initialization The main body section of the signal line extends along the row direction, and the extension section of the initialization signal line is different from the extension direction of the main body section; wherein the projection of the extension section of the initialization signal line on the base substrate is the same as the connection line
  • the projection has an overlap, and the extension of the initialization signal line and the connection line are connected by via holes in the overlap area.
  • the array substrate further includes a plurality of light-emitting control signal lines, disposed on the first gate line layer, extending along the row direction and spaced along the column direction, It is used to provide a light-emitting control signal to each of the sub-pixels; in the sub-pixel area, the light-emitting control signal line is located on the side of the reset signal line away from the scan line of the previous sub-pixel, and is connected to the The projections of the initialization signal lines do not overlap.
  • the array substrate further includes a plurality of power leads, which are disposed on the second gate line layer, extend along the row direction and are spaced apart along the column direction, and are located in the same Each of the power lines in a row is connected to one of the power leads through vias.
  • the sub-pixel further includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes:
  • a capacitor comprising a first electrode plate and a second stage plate, the first electrode plate is arranged on the first grid line layer, and the second electrode plate is arranged on the second grid line layer;
  • the first plate of the capacitor is multiplexed as the gate of the driving transistor, and the first stage of the driving transistor is connected to the power line;
  • a first transistor the gate of the first transistor is connected to the scan line, the first stage of the first transistor is connected to the data line, and the second stage of the first transistor is connected to the first stage of the capacitor. Diode plate connection;
  • the gate of the second transistor is connected to the scan line
  • the first stage of the second transistor is connected to the second stage of the driving transistor
  • the second stage of the first transistor is connected to the connected to the first plate of the capacitor.
  • the gate of the fourth transistor is connected to the reset signal line, the first stage of the fourth transistor is electrically connected to the initial signal line, and the second stage of the fourth transistor is connected to the reset signal line
  • the first plate of the capacitor is electrically connected.
  • the gate of the fifth transistor is connected to the reset signal line, the first stage of the fifth transistor is electrically connected to the initial signal line, and the second stage of the fifth transistor is connected to the reset signal line
  • the second plate of the capacitor is electrically connected.
  • the gate of the sixth transistor is connected to the light-emitting control signal line, the first stage of the sixth transistor is electrically connected to the initial signal line, and the second stage of the sixth transistor is connected to the The second plate of the capacitor is electrically connected.
  • the gate of the seventh transistor is connected to the light-emitting control signal line
  • the first stage of the seventh transistor is electrically connected to the second stage of the driving transistor
  • the second stage of the seventh transistor is The stage is electrically connected to the anode of the sub-pixel.
  • an eighth transistor the gate of the eighth transistor is connected to the reset signal line, the first stage of the eighth transistor is electrically connected to the initial signal line, and the second stage of the eighth transistor is connected to the reset signal line
  • the anodes of the sub-pixels are electrically connected.
  • a ninth transistor the gate of the ninth transistor is connected to the light-emitting control signal line, and the first stage of the ninth transistor is electrically connected to the first plate of the capacitor.
  • the array substrate further includes:
  • the second conductive connection portion is respectively connected with the second stage of the first transistor, the second stage of the fifth transistor, the second stage of the sixth transistor, and the second electrode plate of the capacitor.
  • the second stage of the first transistor, the second stage of the fifth transistor, and the second stage of the sixth transistor are all electrically connected to the second electrode plate of the capacitor through the second conductive connection part .
  • the third conductive connecting portion is respectively connected with the second stage of the fourth transistor, the first stage of the ninth transistor and the first electrode plate of the capacitor through a via hole, and the first stage of the The second stage of the four transistors and the first stage of the ninth transistor are all electrically connected to the first electrode plate of the capacitor through the third conductive connection part.
  • the array substrate further includes a plurality of fifth conductive connection parts, which are disposed on the source and drain layers and are distributed in each of the sub-pixel regions;
  • the fifth conductive connection part is connected to the first stage of the fifth transistor through a via hole, and the fifth conductive connection part is also connected to the initial signal line through another via hole, so that the fifth The first stage of the transistor is connected to the initial signal line; the connection line is arranged on the source and drain layers, and the connection line is connected to the fifth conductive connection part, so as to be connected to the fifth conductive connection part through the fifth conductive connection part.
  • a display device including the above-mentioned array substrate.
  • FIG. 1 is a schematic diagram of the positional relationship between an initialization signal line and a connection line in an embodiment
  • FIG. 2 is a schematic structural diagram of a sub-pixel circuit of a 9T1C
  • FIG. 3 is a timing diagram of the sub-pixel circuit structure shown in FIG. 2;
  • FIG. 4 is a schematic structural diagram of the arrangement of a plurality of sub-pixel arrays in the first embodiment
  • Fig. 5 is the film layer stack structure of a sub-pixel in Fig. 4;
  • FIG. 6 is a schematic structural diagram of the active layer in FIG. 5;
  • FIG. 7 is a schematic view of the stacking of the active layer and the first gate line layer in FIG. 5;
  • FIG. 8 is a schematic view of the stacking of the active layer, the first gate line layer and the second gate line layer in FIG. 5;
  • FIG. 9 is a schematic view of the stacking of the active layer, the first gate line layer, the second gate line layer, and the source and drain layers in FIG. 5;
  • FIG. 10 is a schematic structural diagram of the first gate line layer in FIG. 5;
  • FIG. 11 is a schematic structural diagram of the second gate line layer in FIG. 5;
  • FIG. 12 is a schematic structural diagram of the source and drain layers in FIG. 5;
  • FIG. 13 is a schematic structural diagram of an anode layer
  • Figure 14 is a sectional view taken along the A-A direction in Figure 12;
  • 15 is a schematic structural diagram of the arrangement of a plurality of sub-pixel arrays in the second embodiment
  • 16 is a schematic diagram of the positional relationship between the initialization signal line and the connection line in the second embodiment
  • 17 is a stacked perspective view of the anode layer and the second grid line layer of the second embodiment
  • FIG. 19 is a film layer stack structure of a sub-pixel in FIG. 18;
  • FIG. 20 is a schematic structural diagram of the first gate line layer in FIG. 19;
  • FIG. 21 is a schematic view of the stacking of the active layer, the first gate line layer, and the second gate line layer in FIG. 19;
  • FIG. 22 is a schematic view of the stacking of the active layer, the first gate line layer, the second gate line layer, and the source and drain layers in FIG. 19;
  • FIG. 23 is a schematic structural diagram of the first gate line layer in FIG. 19;
  • FIG. 24 is a schematic structural diagram of the second gate line layer in FIG. 19;
  • FIG. 25 is a schematic structural diagram of the source and drain layers in FIG. 19;
  • Figure 26 is a sectional view taken along the direction B-B in Figure 25;
  • FIG. 27 is a schematic structural diagram of the arrangement of a plurality of sub-pixel arrays in the fourth embodiment.
  • Fig. 28 is the film layer stack structure of one sub-pixel in Fig. 27;
  • FIG. 29 is a schematic view of the stacking of the active layer and the first gate line layer in FIG. 27;
  • FIG. 30 is a schematic view of the stacking of the active layer, the first gate line layer, the second gate line layer, and the source and drain layers in FIG. 27;
  • FIG. 31 is a schematic structural diagram of the second gate line layer in FIG. 27;
  • FIG. 32 is a schematic structural diagram of the source and drain layers in FIG. 27;
  • FIG. 33 is a cross-sectional view taken along the line C-C in FIG. 32 .
  • active layer 100 active layer; 200, first gate insulating layer; 300, first gate line layer; 400, second gate insulating layer; 500, second gate line layer; 500', second gate Line layer; 600, dielectric layer; 700, source and drain layer; 700', source and drain layer; 800, passivation layer; 900, anode layer;
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • An embodiment of the present disclosure provides an array substrate.
  • the array substrate is arrayed with a plurality of pixel units along a row direction and a column direction, and the pixel unit includes a plurality of sub-pixels.
  • the array substrate includes a plurality of initialization signal lines 51 and a plurality of connection lines 10 .
  • a plurality of initialization signal lines 51 are provided in a conductive layer, extend along the row direction and are arranged at intervals along the column direction.
  • Each initialization signal line 51 is used for An initialization signal is supplied to each sub-pixel located in the same row in the row direction.
  • a plurality of connecting lines 10 are disposed on another conductive layer, extend along the column direction and are arranged at intervals along the row direction. Wherein, the projections of at least one initialization signal line 51 and at least one connection line 10 on the base substrate intersect and are connected through via holes, so that the projections of the initialization signal line 51 and the connection line 10 on the base substrate intersect to form a grid like structure.
  • the horizontal initialization signal lines 51 are connected to a grid-like structure through the vertical connecting lines 10, and the paths of the initialization signals are increased, and the initialization signals can be transmitted to each sub-pixel through more paths, thereby reducing the current transmission path.
  • the problem of too large IR drop Compared with wiring in one layer, the entire grid structure is divided into two layers of wiring, which can reduce the pressure of wiring space and reduce the fact that the single-layer wiring is too tight and the initialization signal is easily affected by the jump of other signals (such as scan signals), reducing the Influence on the luminous performance, improve the display uniformity of the panel.
  • the horizontal arrangement of the initialization signal line 51 means that the main structure of the initialization signal line 51 extends in the horizontal direction. In actual products, there may be some parts that are not completely horizontally arranged, such as turning to avoid other circuit structures, or in other directions. It is extended to facilitate connection with other lines, etc., as long as the overall orientation of the initialization signal line 51 is the lateral direction.
  • the longitudinal arrangement of the connecting line 10 means that the main structure of the connecting line 10 extends in the longitudinal direction, and the overall direction is the longitudinal direction.
  • each pixel unit is composed of four RGBG sub-pixels, and each sub-pixel is driven by a separate sub-pixel driving circuit.
  • FIG. 2 shows a 9T1C sub-pixel circuit structure.
  • the sub-pixel circuit structure includes a capacitor and nine TFT transistors T1-T9.
  • all TFTs are P-type TFTs
  • the third transistor T3 is a driver transistors, other transistors are switching transistors.
  • the capacitor includes a first electrode plate Cst1 and a second electrode plate Cst2 .
  • the first electrode plate Cst1 is provided on the first gate line layer 300
  • the second electrode plate Cst2 is provided on the second gate line layer 500 .
  • the first plate Cst1 is connected to the node N2, and the second plate Cst2 is connected to the node N1.
  • the gate 3g of the driving transistor T3 (third transistor) is multiplexed by the first plate Cst1 of the capacitor, and the source 3s is connected to the power supply line 72; the gate 1g of the first transistor T1 is connected to the scan line 31, and the source 1s is connected to The data line 71 is connected, and the drain 1d is connected to the node N1.
  • the gate 2g of the second transistor T2 is connected to the scan line 31, the source 2s is connected to the drain 3d of the driving transistor T3, and the drain 2d is connected to the node N2.
  • the gate 4g of the fourth transistor T4 is connected to the reset signal line 32, the source 4s is electrically connected to the initial signal line 51, and the drain 4d is connected to the node N2.
  • the gate 5g of the fifth transistor T5 is connected to the reset signal line 32, the source 5s is electrically connected to the initial signal line 51, and the drain 5d is connected to the node N1.
  • the gate 6g of the sixth transistor T6 is connected to the light emission control signal line 33, the source 6s is electrically connected to the initial signal line 51, and the drain 6d is connected to the node N1.
  • the gate 7g of the seventh transistor T7 is connected to the light emission control signal line 33, the source 7s is electrically connected to the drain 3d of the driving transistor T3, and the drain 7d is electrically connected to the anode 91 of the sub-pixel.
  • the gate 8g of the eighth transistor T8 is connected to the reset signal line 32, the source 8s is electrically connected to the initial signal line 51, and the drain 8d is electrically connected to the anode 91 of the sub-pixel.
  • the gate 9g of the ninth transistor T9 is connected to the light emission control signal line 33, and the source 9s is connected to the node N2.
  • the initialization signal provided by the initialization signal line 51 is Vint
  • the reset signal provided by the reset signal line 32 is Reset
  • the light-emitting control signal provided by the light-emitting control signal line 33 is EM
  • the scan signal provided by the scan line 31 is gate
  • the data line 71 The data signal provided is data
  • the power supply signal provided by the power line 72 is ELVDD.
  • the specific working principle of the sub-pixel compensation circuit is as follows:
  • the reset signal Reset is at a low level.
  • the fourth transistor T4 is turned on, and the initial signal Vint initializes the point N2.
  • the potential of the point N2 is the initial signal Vint.
  • the fifth transistor T5 is turned on, and the initial signal Vint is written into the N1 point.
  • the eighth transistor T8 is turned on to release the residual charge displayed in the previous frame, and the initial signal Vint is written to reduce the voltage difference between the anode and cathode of the OLED device, reduce the brightness of the OLED device at low gray levels, and improve the contrast of the pixel.
  • the signal Gate of the scan line 31 is at a low level.
  • the first transistor T1 is turned on.
  • the potential of the N1 point is Vdata, and the data signal voltage is written into the N1 point.
  • the second transistor T2 is turned on, sampling the diode connection of the driving transistor T3, the potential of the N2 point rises to ELVDD+Vth, the driving transistor T3 gradually changes from the on state to the off state, and compensates the threshold voltage Vth of the driving transistor T3.
  • the light emission control signal EM is at a low level.
  • the sixth transistor T6 is turned on, at this time, the potential of the point N1 is the initial signal Vint.
  • the ninth transistor T9 is turned on, and the leakage of the N2 point is reduced in the light-emitting stage. As the potential of the N1 point jumps, the potential of the N2 point becomes ELVDD+Vth+Vint-Vdata at this time.
  • the seventh transistor T7 is turned on, the driving current is output, and the OLED device emits light.
  • the current calculation formula of the OLED device is
  • the threshold voltage Vth of the driving transistor T3 can be compensated in the sampling stage, thereby eliminating the influence of the difference of the DTFT threshold voltage Vth of different pixels on the uniformity of display brightness.
  • Vint can be used as an initialization signal, and can also be used as a reference signal during data writing.
  • the sub-pixel driving circuits of the above-mentioned sub-pixels are fabricated on a base substrate.
  • the active layer 100 , the first gate line layer 300 , the second gate line layer 500 , and the source and drain layers 700 are stacked on the base substrate.
  • These film layers are used to form various signal lines or wires to drive circuits for each sub-pixel. Provide the corresponding electrical signal.
  • Both the two film layers are insulated by an insulating layer.
  • a first gate insulating layer 200 is arranged between the active layer 100 and the first gate layer 300 , and a first gate line layer 300 and a second gate line layer 500 are arranged between them.
  • a dielectric layer 600 is disposed between the second gate insulating layer 400 , the second gate line layer 500 and the source and drain layers 700 , and a passivation layer 800 and other film layers are further disposed above the source and drain layers 700 .
  • Film layers such as the anode layer 900 , the organic light-emitting layer, and the cathode layer of the sub-pixels are disposed above the passivation layer 800 to form an OLED light-emitting device, and the OLED light-emitting devices of each sub-pixel are separated by a pixel defining layer.
  • FIG. 4 shows a schematic structural diagram of the arrangement of a plurality of sub-pixel arrays in an embodiment
  • FIG. 5 is a stacked structure of a sub-pixel driving circuit of a sub-pixel and various signal lines on an array substrate.
  • FIGS. 6-9 show schematic diagrams of film stacking of the active layer 100, the first gate line layer 300, the second gate line layer 500, and the source and drain layers 700
  • FIGS. 10-12 show the first gate line A schematic diagram of the structure of each layer of the layer 300 , the second gate line layer 500 , and the source and drain layers 700 .
  • the active layer 100 is used for disposing channel regions (1g-9g), first stages (1s-9s) and second stages (1d-9d) of each TFT transistor.
  • the first gate line layer 300 is used to set the gates (eg, 1g ⁇ 9g) of the transistors in the sub-pixel driving circuit, the first electrode plate Cst1 of the capacitor, and a plurality of scan lines 31 , A plurality of reset signal lines 32, a plurality of light-emitting control signal lines 33 and other structures.
  • a plurality of scan lines 31 are arranged at intervals in the column direction and extend in the row direction, and are used for providing scan signals to each sub-pixel located in the same row in the row direction.
  • a plurality of reset signal lines 32 are arranged at intervals in the column direction and extend in the row direction, and are used for providing reset signals to sub-pixels located in the same row in the row direction.
  • the plurality of light-emitting control signal lines 33 extend in the row direction and are arranged at intervals in the column direction, and are used for providing light-emitting control signals to sub-pixels located in the same row in the row direction.
  • the reset signal line 32 is located at the top
  • the scan line 31 is located at the bottom
  • the light-emitting control signal line 33 is located between the reset signal line 32 and the scan line 31
  • the first plate Cst1 of the capacitor is located at the bottom. Between the light emission control signal line 33 and the scan line 31 .
  • the reset signal line 32 of the sub-pixel of the next level can be connected to the scan line 31 of the sub-pixel of the previous level, so that the scan signal of the sub-pixel of the previous level can be used as the reset signal of the sub-pixel of the next level, thereby Avoid introducing a separate signal line for the reset signal, effectively reducing the wiring space.
  • the second gate line layer 500 is used to set structures such as the second electrode plate Cst2 for forming a capacitor, and in this embodiment, the initialization signal line 51 is also disposed on the second gate line layer 500 .
  • the second electrode plate Cst2 of the capacitor corresponds to the first electrode plate Cst1 in the thickness direction of the array substrate, and the projection of the initialization signal line 51 on the array substrate is located on the side where the projection of the second electrode plate Cst2 is close to the projection of the reset signal line 32 .
  • the projections of the initialization signal line 51 and the reset signal line 32 on the base substrate overlap, which greatly saves wiring space.
  • the source and drain layers 700 are used to provide vertical power lines 72 , data lines 71 and other structures.
  • the power lines 72 extend along the column direction and are arranged at intervals along the row direction, and are used to provide power signals to each sub-pixel located in the same column.
  • the data lines 71 extend along the column direction and are arranged at intervals along the row direction, and are used for providing signals of the data lines 71 to the sub-pixels located in the same column.
  • the projections of the power line 72 and the data line 71 on the array substrate do not overlap with the first electrode plate Cst1 and the second electrode plate Cst2 of the capacitor.
  • the second gate line layer 500 further includes a plurality of power supply leads 52 , the plurality of power supply leads 52 extend along the row direction and are arranged at intervals along the column direction, and each power supply located in the same row
  • the line 72 is connected to one power lead 52 through the via hole provided in the dielectric layer 600 , so that the power lead 52 and the power line 72 also form a grid-like structure, which can reduce the voltage drop of the power supply voltage.
  • the source-drain layer 700 further includes a plurality of second conductive connection parts 74 , and each second conductive connection part 74 is disposed on the source-drain layer 700 and distributed in each sub-pixel within the area.
  • the projection of the second conductive connection portion 74 on the base substrate overlaps with the projection of the drain 1d of the first transistor T1, the drain 5d of the fifth transistor T5, and the projection 6d of the sixth transistor T6, and passes through
  • the via holes passing through the first gate insulating layer 200, the second gate insulating layer 400, and the dielectric layer 600 are connected, and the projection of the second conductive connection portion 74 on the base substrate also overlaps with the projection of the second electrode plate Cst2 of the capacitor, and They are electrically connected through vias penetrating through the dielectric layer 600 , that is to say, 1 d , 5 d , and 6 d are all electrically connected to the second electrode plate Cst2 of the capacitor through the second conductive connection portion 74 .
  • the source/drain layer 700 further includes a plurality of third conductive connection parts 75 , and each third conductive connection part 75 is disposed on the source/drain layer 700 and distributed in each sub-pixel within the area.
  • the projection of the third conductive connection portion 75 on the base substrate overlaps with the projection of the second transistor T2 2d and the projection of the first stage 9s of the ninth transistor T9, and passes through the first gate insulating layer 200
  • the second gate insulating layer 400 and the via holes of the dielectric layer 600 are connected to each other, and the projection of the third conductive connection portion 75 on the base substrate also overlaps with the projection of the first electrode plate Cst1 of the capacitor, and passes through the second gate insulating layer 400 .
  • the via holes of the dielectric layer 600 are electrically connected, that is to say, both 2d and 9s are electrically connected to the first electrode plate Cst1 of the capacitor through the third conductive connection portion 75 .
  • the source/drain layer 700 further includes a plurality of fourth conductive connection parts 76 , and each fourth conductive connection part 76 is disposed on the source/drain layer 700 and distributed in each sub-pixel within the area.
  • the projection of the fourth conductive connection portion 76 on the base substrate overlaps with 8d of the eighth transistor T8, and passes through the first gate insulating layer 200, the second gate insulating layer 400, and the dielectric layer 600
  • the holes are electrically connected, that is, 8d is electrically connected to the anode 91 through the fourth conductive connection 76 .
  • the source/drain layer 700 further includes a plurality of fifth conductive connection parts 77 , and each fifth conductive connection part 77 is disposed on the source/drain layer 700 and distributed in each sub-pixel In the area, the source electrodes of T4, T5, T6, and T8 are connected to the initial signal line 51.
  • the fifth conductive connection portion 77 is connected to the source electrode 5s of the fifth transistor T5 in the active layer 100 through a via hole penetrating the first gate insulating layer 200 , the second gate insulating layer 400 and the dielectric layer 600 .
  • the conductive connection portion 77 is also connected to the initial signal line 51 of the second gate layer through another via hole penetrating the dielectric layer 600 , so that the source electrode 5s of the fifth transistor T5 is electrically connected to the initial signal line 51 .
  • the source electrode 5s of the fifth transistor T5 and the source electrode 6s of the sixth transistor T6 are commonly connected to the source electrode 8s of the eighth transistor T8 and the source electrode 8s of the fourth transistor T4 in the right sub-pixel in the row direction
  • the source electrode 4s so that the source electrodes of T4, T5, T6, and T8 are all connected to the initial signal line 51, thereby simplifying the number of vias.
  • An OLED light-emitting device is also disposed on the array substrate, a pixel defining layer is disposed above the source and drain layers 700 , and the pixel defining layer has a plurality of openings for defining each sub-pixel.
  • the anode layer 900 is used for disposing the anode 91 of the OLED light emitting device, and is located in the opening of the pixel defining layer. Further, an organic light-emitting layer and a cathode layer are also arranged in the opening.
  • the film layer structure of the OLED light-emitting device may adopt a conventional structure, which will not be repeated here. As shown in FIG. 13 , it is a schematic structural diagram of an anode layer 900 of an RGBG pixel structure.
  • the connecting wire 10 is provided on the anode layer 900 , passes through the gap between two anodes 91 in the longitudinal direction, and is insulated from any anode 91 .
  • the connection line 10 is covered by the pixel definition layer to avoid contact with other film layers above.
  • connection line 10 is formed on the anode layer 900 by etching the anode 91 material (eg, ITO/Ag/ITO), and the anode 91 material is usually etched by wet method, the panel with higher PPI will not be affected. In other words, it is difficult to etch, so try to avoid too many connecting lines 10 in the lateral direction, and ensure that the whole line is longitudinally routed. If a grid-like closed pattern is formed on the anode layer 900, it is easy to cause poor etching .
  • the anode 91 material eg, ITO/Ag/ITO
  • the number of connection lines 10 is smaller than the number of sub-pixels in the row direction, that is, in the row direction, the initialization signal lines 51 and the connection lines 10 are electrically connected through via holes in some sub-pixel regions.
  • the number of connecting lines 10 is half of the number of sub-pixels in the row direction, and one is set every other sub-pixel, then every other sub-pixel, the initialization signal line 51 and one connecting line 10 pass through the via hole. connect. Therefore, one of every two adjacent sub-pixels in the row direction is provided with the connection line 10 and the via hole, and the other is not provided.
  • different numbers of sub-pixels may also be spaced between two adjacent connecting lines 10 .
  • the number of connecting lines 10 may also be equal to the number of sub-pixels in the row direction. That is to say, in the row direction, the initialization signal lines 51 and the connection lines 10 are electrically connected through via holes in each sub-pixel region. Therefore, each sub-pixel in the row direction is provided with a connection line 10 and a via hole. As long as the projections of the plurality of connection lines 10 and the plurality of initialization signal lines 51 on the base substrate can form a grid-like structure.
  • the array substrate further includes a plurality of first conductive connection parts 73 provided on the source and drain layers 700, and the plurality of first conductive connection parts 73 are distributed In the sub-pixel area where the projections of the initialization signal lines 51 and the connection lines 10 intersect, FIG. 9( a ) shows the stacked structure where the projections of the initialization signal lines 51 and the connection lines 10 intersect, and FIG. 9( b ) shows the initialization signal lines 51 A layered structure that does not intersect the projection of the connecting line 10 .
  • 700 represents the structure of the source and drain layers provided with the first conductive connection portion 73
  • 700 ′ represents the structure of the source and drain layers provided with the first conductive connection portion 73
  • the projection of the first conductive connection part 73 on the base substrate has an overlapping area with the initial signal line 51 and the connection line 10, respectively, and the first conductive connection part 73 and the initial signal line.
  • the initialization signal line 51 is connected through a via hole passing through the dielectric layer 600, and the first conductive connection portion 73 and the connection line 10 are connected through a via hole passing through the passivation layer 800, so that the initialization signal line 51 and the connection line 10 pass through the first conductive connection portion.
  • 73 forms an electrical connection.
  • the first conductive connection part 73 and the fifth conductive connection part 77 are connected as a whole, which can simplify the preparation of the conductive connection part of the source-drain layer 700 . Since the first conductive connection portion 73 and the fifth conductive connection portion 77 are integrally connected, the projection of the first conductive connection portion 73 on the base substrate and the initial signal line 51 have an overlapping area, which can also be understood as the fifth conductive connection portion The projection of 77 on the base substrate has an overlapping area with the initial signal line 51 , and the connection between the fifth conductive connection portion 77 and the initial signal line 51 can be realized.
  • the first conductive connection portion 73 is connected to the connection wire 10 through a via hole
  • the fifth conductive connection portion 77 is connected to the connection wire 10 through a via hole.
  • the shape in which the first conductive connection portion 73 and the fifth conductive connection portion 77 are integrally connected includes, but is not limited to, the L-shape shown in FIG. 12 .
  • FIG. 14 shows a cross-sectional view of the first conductive connection portion 73 and the fifth conductive connection portion 77 , which is a cross-sectional view along the A-A direction in FIG. 12 .
  • the via holes are provided, the plurality of via holes are staggered from each other in the thickness direction. .
  • the reset signal line 32 is connected to the upper-level scan line 31 , the initialization signal line 51 and the reset signal line 32 overlap, and the connecting line 10 is wired on the anode layer 900 , which greatly saves wiring space and can be It is suitable for panels with higher PPI, such as panels with PPI greater than 410.
  • the initialization signal line 51 is no longer a whole continuous signal line, but includes multiple signal segments 510 separated from each other, that is, the initialization signal line 51 is divided into a plurality of horizontal small segments, and each signal segment 510 corresponds to each pixel unit one by one , each signal segment 510 does not overlap the projection of the reset signal line 32 in at least one sub-pixel area in the corresponding pixel unit, and intersects with the projection of the reset signal line 32 in the remaining sub-pixel areas.
  • each signal segment 510 spans one pixel unit, and within one pixel unit, the signal segment 510 overlaps with the projection of the reset signal line 32 in three sub-pixel areas, and at one end The sub-pixel area does not overlap with the projection of the reset signal line 32 , and ends at one side of the reset signal line 32 . In this way, the probability of cross static electricity being generated in the pixel unit can be reduced, and the cross static electricity in one pixel unit will not affect other pixel units.
  • each vertical connection line 10 will be connected to a signal segment 510. Therefore, it can be considered that each initialization signal line 51 and each connection line 10 are connected.
  • the initialization signal line 51 in the horizontal direction is disconnected in this embodiment, since it still intersects with the connecting line in the vertical direction, it is also regarded as a grid-like structure. That is to say, the grid-like structure described in the present disclosure includes the complete grid structure shown in FIG. 1 , and also includes the grid structure that is broken in the middle shown in FIG. 16 .
  • FIG. 17 is a perspective view of the connection line 10 provided in the anode layer 900 and the initialization signal line 51 provided in the second gate layer.
  • FIG. 18 shows a schematic structural diagram of the arrangement of a plurality of sub-pixel arrays in another embodiment
  • FIG. 19 is a stacked structure of a sub-pixel driving circuit and various signal lines of one sub-pixel on the array substrate.
  • FIGS. 20-22 show schematic diagrams of film stacking of the first gate line layer 300, the second gate line layer 500, and the source and drain layers 700
  • FIGS. 23-25 show the first gate line layer 300, the second A schematic diagram of the structure of each layer of the gate line layer 500 and the source and drain layers 700 .
  • the structure of the active layer 100 is the same as that of FIG. 6 in the previous embodiment, so the related drawings are omitted here.
  • the connection line 10 is also provided on the anode layer 900 .
  • FIG. 22( a ) shows a stacked structure in which the projections of the initialization signal lines 51 and the connection lines 10 intersect
  • FIG. 22( b ) shows a stacked structure in which the initialization signal lines 51 do not intersect the projections of the connection lines 10
  • 700 represents the structure of the source and drain layers provided with the first conductive connection portion 73
  • 700 ′ represents the structure of the source and drain layers provided with the first conductive connection portion 73 .
  • the projection of the initialization signal line 51 on the base substrate is located between the projection of the reset signal line 32 of the sub-pixel of the current stage and the projection of the scan line 31 of the sub-pixel of the previous stage,
  • the projections of the initialization signal line 51 , the reset signal line 32 of the sub-pixel of the current stage, and the scan line 31 of the sub-pixel of the previous stage do not overlap. That is to say, the projections of the initialization signal line 51 , the reset signal line 32 of the sub-pixel of the current stage, and the scan line 31 of the sub-pixel of the previous stage are all spaced apart from each other.
  • the reset signal line 32 of the sub-pixel of the next level and the scan line 31 of the sub-pixel of the previous level can be connected in the peripheral area of the array substrate, so that the scan signal of the sub-pixel of the previous row is input to the reset of the sub-pixel of the next row in the peripheral area.
  • Signal line 32 This structure can avoid cross static electricity between the initialization signal line 51 , the reset signal line 32 and the scan line 31 , and also avoid the initialization signal being easily affected by the scan signal jump due to the close distance between the initialization signal line 51 and the scan line 31 . Under this structure, compared with the structure shown in FIG. 5 , the wiring method of this embodiment will occupy more area, so it is suitable for a panel with a slightly lower PPI, for example, a panel with a PPI less than 410.
  • the wiring arrangement of the source and drain layers 700 is also the same as that in the previous embodiment, that is, the first to fifth conductive connection parts are included.
  • the connection line 10 is provided on the anode layer 900 , and the connection line 10 is connected to the initialization signal line 51 through the fifth conductive connection portion 77 .
  • the shape in which the first conductive connection part 73 and the fifth conductive connection part 77 are connected as a whole includes, but is not limited to, the T shape shown in FIG. 25 .
  • the cross-sectional view is shown in FIG. 26 , when the via holes are provided, the plurality of via holes are staggered from each other in the thickness direction.
  • FIG. 27 shows a schematic structural diagram of the arrangement of a plurality of sub-pixel arrays in another embodiment
  • FIG. 28 is a stacked structure of a sub-pixel driving circuit of one sub-pixel and various signal lines on the array substrate.
  • FIGS. 29 to 30 show schematic diagrams of film stacking of the second gate line layer 500 and the source and drain layers 700
  • FIGS. 31 to 32 show the layer structures of the second gate line layer 500 and the source and drain layers 700 .
  • the structures of the active layer 100 and the first gate layer 300 are the same as those in FIG. 6 and FIG. 7 , so the related drawings are omitted here.
  • the initialization signal line 51 further includes a main body section 511 and an extension section 512 .
  • the projection is located on the side of the reset signal line 32 away from the scan line 31 of the previous stage, and on the side of the power lead 52 close to the sub-pixel of the previous stage.
  • the extension section 512 of the initialization signal line 51 bypasses the reset signal line 32 and extends between the reset signal line 32 and the scan line 31 of the previous stage. Cross static electricity is generated between them, and it is also convenient to connect with the connecting line 10 .
  • connection line 10 is provided on the source-drain layer 700 .
  • the connection line 10 is located on the side of the power line 72 away from the data line 71 , for example, may be located on the side of the second conductive connection part 74 and the third conductive connection part 75 away from the power supply line 72 .
  • the connection lines 10 extend along the column direction as a whole, and some of them are bent to the right side in order to avoid the fourth conductive connection portion 76 . Since the connection line 10 does not need to be connected to the anode layer 900, the first conductive connection part 73 is not included.
  • the connecting wire 10 can be connected to the fifth conductive connecting portion 77 as a whole, through
  • the fifth conductive connection portion is connected to the initialization signal line 51 .
  • this structure occupies more area for wiring on the source and drain layers 700 , so it is suitable for panels with lower PPI, such as panels with PPI less than 385.
  • the source-drain layer 700 is etched by dry method, compared with that of the anode layer 900 by wet etching, the risk of defects in etching the material of the anode 91 can be reduced.
  • the material of the source and drain layers 700 has lower resistance than the material of the anode layer 900, which is beneficial to improve the IR drop.
  • the wiring arrangement of other lines in the source-drain layer 700 is also the same as that in the previous embodiment.
  • Another difference between this embodiment and the structures shown in FIG. 5 and FIG. 17 is that the number of connecting lines 10 is equal to the number of sub-pixels in the row direction, that is, each sub-pixel has an initialization signal line 51 intersecting with the connecting line 10 And connected through vias, that is, all sub-pixels have the same internal structure.
  • the above embodiments provide various arrangement positions and connection methods of the initialization signal lines and connection lines of the present disclosure, and various structures of the present disclosure can take into account the PPI requirements and performance requirements of different products while making reasonable wiring. It can be understood that the setting positions and connection manners of the initialization signal lines and the connection lines can be combined arbitrarily, so as to meet the requirements of the PPI of the display panel, process practicability and display performance.
  • the above embodiments are described by taking the pixel circuit structure of 9T1C as an example.
  • the initialization signal lines and the connecting lines can also be connected in layers in a grid shape, which can also reduce the IR drop and simultaneously Relieve wiring stress.
  • each of the above pixel units is composed of four sub-pixels of RGBG, and only one algorithm is used as an example for the description.
  • the structure of the layered connection of the initialization signal lines and the connection lines of the present disclosure in a grid shape can also be applied to other Algorithm to arrange the RGBG pixel structure.
  • the initialization signal line and the connecting line can also be connected in layers in a grid shape, which can also reduce the IR drop and relieve the wiring pressure.
  • Embodiments of the present disclosure further provide a display device including the array substrate of the above-mentioned embodiments. Since the display device includes the above-mentioned array substrate, it has the same beneficial effects, and details are not described herein again in this disclosure.
  • the present disclosure does not specifically limit the application of display devices, which can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, in-vehicle displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or components.
  • display devices can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, in-vehicle displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or components.

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Abstract

提供一种阵列基板和显示装置。阵列基板包括多条初始化信号线和多条连接线，初始化信号线设于一导电层，沿第一方向延伸且沿第二方向间隔排列，用于向各子像素提供初始化信号；连接线设于另一导电层，沿第二方向延伸且沿第一方向间隔排列；其中，至少一条初始化信号线与至少一条连接线在衬底基板上的投影均相交且通过过孔连接，以使初始化信号线和连接线在衬底基板上的投影形成网格状结构。可以改善IR drop过大的问题，还能减少布线空间压力。

Description

阵列基板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板和显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示技术，以其轻薄、自发光、视角广、响应速度快、亮度低、功耗低等优点，被业界公认为第三代显示技术，已广泛地被应用于高性能显示领域中。
随着对显示面板PPI(像素密度)的要求越来越高，面板上的布线压力也越来越大，既需要考虑各种线路能够紧密排布，又要尽量降低各种线路之间的互相影响，因此对布线设计提出了更高的要求。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种阵列基板和显示装置。
根据本公开的一个方面，提供一种阵列基板，阵列排布有多个像素单元，所述像素单元包括多个子像素，所述阵列基板包括：
多条初始化信号线，设于一导电层，沿第一方向延伸且沿第二方向间隔排列，用于向各所述子像素提供初始化信号；所述第一方向和第二方向相交；
多条连接线，设于另一导电层，沿所述第二方向延伸且沿所述第一方向间隔排列；
其中，至少一条所述初始化信号线与至少一条所述连接线在所述衬底基板上的投影均相交且通过过孔连接，以使所述初始化信号线和所述连接线在所述衬底基板上的投影形成网格状结构。
在本公开的一种示例性实施例中，所述阵列基板包括衬底基板和依次层叠设置于所述衬底基板上的第一栅线层、第二栅线层、源漏极层、阳极层；所述第一方向为行方向，所述第二方向为列方向；所述初始化信号线设于所述第二栅极层；所述连接线设于所述源漏极层或阳极层。
在本公开的一种示例性实施例中，所述阵列基板还包括：
多条扫描线，设于所述第一栅线层，沿所述行方向延伸且沿列方向间隔排列，用于向各所述子像素提供扫描信号；
多条复位信号线，设于所述第一栅线层，沿所述行方向延伸且沿列方向间隔排列，用于向各所述子像素提供复位信号。
在本公开的一种示例性实施例中，在所述子像素区域内，所述初始化信号线在所述衬底基板上的投影位于所述复位信号线和上一级子像素的扫描线的投影之间，且所述初始化信号线、复位信号线、扫描线三者的投影均不重叠。
在本公开的一种示例性实施例中，在所述子像素区域内，所述初始化信号线在所述衬底基板上的投影位于所述复位信号线的投影背离上一级子像素的扫描线的一侧，且所述初始化信号线、复位信号线、扫描线三者的投影均不重叠。
在本公开的一种示例性实施例中，在所述子像素区域内，所述复位信号线和上一级子像素的扫描线连接为一体；所述初始化信号线在所述衬底基板上的投影与所述复位信号线的投影相交。
在本公开的一种示例性实施例中，所述初始化信号线包括多段相互分隔的信号段，各所述信号段一一对应于各所述像素单元；其中，每一所述信号段在对应的所述像素单元内的至少一个所述子像素区域内与所述复位信号线的投影无重叠，在其余所述子像素区域内与所述复位信号线的投影均相交。
在本公开的一种示例性实施例中，所述连接线的数量与所述行方向上子像素的数量相等，在所述行方向上，所述初始化信号线与各所述连接线在每一子像素区域都通过过孔电连接；或，所述连接线的数量小于所述行方向上子像素的数量，在所述行方向上，所述初始化信号线与各所述连接线在部分子像素区域通过过孔电连接。
在本公开的一种示例性实施例中，所述阵列基板还包括：
多条电源线，设于所述源漏极层，沿列方向延伸且沿所述行方向间隔排列，用于向各所述子像素提供电源信号；
多条数据线，设于所述源漏极层，沿列方向延伸且沿所述行方向间隔排列，用于向各所述子像素提供数据信号。
在本公开的一种示例性实施例中，所述子像素包括阳极，所述连接线和所述阳极均设于所述阳极层，所述连接线与所述阳极绝缘。
在本公开的一种示例性实施例中，所述阵列基板还包括多个第一导电连接部，设于所述源漏极层，且分布于所述初始化信号线与所述连接线的投影相交处所在的子像素区域；
分布有所述第一导电连接部的子像素区域内，所述第一导电连接部在所述衬底基板 的投影分别与所述初始信号线和连接线具有重叠区域，所述第一导电连接部与所述初始信号线通过过孔连接，所述第一导电连接部与所述连接线通过过孔连接。
在本公开的一种示例性实施例中，所述连接线设于所述源漏极层；所述子像素区域内，所述初始化信号线包括相互连接的主体段和延伸段，所述初始化信号线的主体段沿所述行方向延伸，所述初始化信号线的延伸段与主体段延伸方向不同；其中，所述初始化信号线的延伸段在所述衬底基板的投影与所述连接线的投影具有重叠，所述初始化信号线的延伸段和所述连接线在所述重叠区域通过过孔连接。
在本公开的一种示例性实施例中，所述阵列基板还包括多条发光控制信号线，设于所述第一栅线层，沿所述行方向延伸且沿所述列方向间隔排列，用于向各所述子像素提供发光控制信号；在所述子像素区域内，所述发光控制信号线位于所述复位信号线远离上一级子像素的扫描线的一侧，且与所述初始化信号线的投影不重叠。
在本公开的一种示例性实施例中，所述阵列基板还包括多条电源引线，设于所述第二栅线层，沿所述行方向延伸且沿所述列方向间隔排列，位于同一行的各所述电源线通过过孔连接于一条所述电源引线。
在本公开的一种示例性实施例中，所述子像素还包括子像素驱动电路，所述子像素驱动电路包括：
电容，包括第一极板和第二级板，所述第一极板设于所述第一栅线层，所述第二极板设于所述第二栅线层；
驱动晶体管，所述电容的第一极板复用为所述驱动晶体管的栅极，所述驱动晶体管的第一级与所述电源线连接；
第一晶体管，所述第一晶体管的栅极与所述扫描线连接，所述第一晶体管的第一级与所述数据线连接，所述第一晶体管的第二级与所述电容的第二极板连接；
第二晶体管，所述第二晶体管的栅极与所述扫描线连接，所述第二晶体管的第一级与所述驱动晶体管的第二级连接，所述第一晶体管的第二级与所述电容的第一极板连接。
第四晶体管，所述第四晶体管的栅极与所述复位信号线连接，所述第四晶体管的第一级与所述初始信号线电连接，所述第四晶体管的第二级与所述电容的第一极板电连接。
第五晶体管，所述第五晶体管的栅极与所述复位信号线连接，所述第五晶体管的第一级与所述初始信号线电连接，所述第五晶体管的第二级与所述电容的第二极板电连接。
第六晶体管，所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一级与所述初始信号线电连接，所述第六晶体管的第二级与所述电容的第二极板电 连接。
第七晶体管，所述第七晶体管的栅极与所述发光控制信号线连接，所述第七晶体管的第一级与所述驱动晶体管的第二级电连接，所述第七晶体管的第二级与所述子像素的阳极电连接。
第八晶体管，所述第八晶体管的栅极与所述复位信号线连接，所述第八晶体管的第一级与所述初始信号线电连接，所述第八晶体管的第二级与所述子像素的阳极电连接。
第九晶体管，所述第九晶体管的栅极与所述发光控制信号线连接，所述第九晶体管的第一级与所述电容的第一极板电连接。
在本公开的一种示例性实施例中，所述阵列基板还包括：
多个第二导电连接部，设于所述源漏极层且分布于各所述子像素区域内；
多个第三导电连接部，设于所述源漏极层且分布于各所述子像素区域内；
所述子像素区域内，所述第二导电连接部分别与所述第一晶体管的第二级、第五晶体管的第二级、第六晶体管的第二级以及所述电容的第二极板通过过孔连接，所述第一晶体管的第二级、第五晶体管的第二级、第六晶体管的第二级均通过所述第二导电连接部与所述电容的第二极板电连接。
所述子像素区域内，所述第三导电连接部分别与所述第四晶体管的第二级、第九晶体管的第一级以及所述电容的第一极板通过过孔连接，所述第四晶体管的第二级、第九晶体管的第一级均通过所述第三导电连接部与所述电容的第一极板电连接。
在本公开的一种示例性实施例中，所述阵列基板还包括多个第五导电连接部，设于所述源漏极层且分布于各所述子像素区域内；
所述第五导电连接部通过一个过孔与所述第五晶体管的第一级连接，所述第五导电连接部还通过另一个过孔与所述初始信号线连接，以使所述第五晶体管的第一级与初始信号线连接；所述连接线设于所述源漏极层，所述连接线与所述第五导电连接部连接，以通过所述第五导电连接部与所述初始信号线连接。
根据本公开的另一个方面，提供一种显示装置，包括以上所述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是 本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种实施方式中初始化信号线和连接线的位置关系示意图；
图2为一种9T1C的子像素电路结构示意图；
图3为图2所示的子像素电路结构的时序图；
图4为第一种实施方式中多个子像素阵列排布的结构示意图；
图5为图4中一个子像素的膜层层叠结构；
图6为图5中有源层的结构示意图；
图7为图5中有源层和第一栅线层膜层堆叠示意图；
图8为图5中有源层、第一栅线层、第二栅线层膜层堆叠示意图；
图9为图5中有源层、第一栅线层、第二栅线层、源漏极层膜层堆叠示意图；
图10为图5中第一栅线层的结构示意图；
图11为图5中第二栅线层的结构示意图；
图12为图5中源漏极层的结构示意图；
图13为一种阳极层的结构示意图；
图14为图12中A-A向的剖面图；
图15为第二种实施方式中多个子像素阵列排布的结构示意图；
图16为第二种实施方式中初始化信号线、连接线位置关系示意图；
图17为第二种实施方式阳极层和第二栅线层的层叠透视图；
图18为第三种实施方式中多个子像素阵列排布的结构示意图；
图19为图18中一个子像素的膜层层叠结构；
图20为图19中第一栅线层的结构示意图；
图21为图19中有源层、第一栅线层、第二栅线层膜层堆叠示意图；
图22为图19中有源层、第一栅线层、第二栅线层、源漏极层膜层堆叠示意图；
图23为图19中第一栅线层的结构示意图；
图24为图19中第二栅线层的结构示意图；
图25为图19中源漏极层的结构示意图；
图26为图25中B-B向的剖面图；
图27为第四种实施方式中多个子像素阵列排布的结构示意图；
图28为图27中一个子像素的膜层层叠结构；
图29为图27中有源层、第一栅线层膜层堆叠示意图；
图30为图27中有源层、第一栅线层、第二栅线层、源漏极层膜层堆叠示意图；
图31为图27中第二栅线层的结构示意图；
图32为图27中源漏极层的结构示意图；
图33为图32中C-C向的剖面图。
图中：有源层100、有源层；200、第一栅绝缘层；300、第一栅线层；400、第二栅绝缘层；500、第二栅线层；500’、第二栅线层；600、介质层；700、源漏极层；700’、源漏极层；800、钝化层；900、阳极层；
31、扫描线；32、复位信号线；33、发光控制信号线；51、初始化信号线；510、信号段；511、主体段；512、延伸段；52、电源引线；71、数据线；72、电源线；73、第一导电连接部；74、第二导电连接部；75、第三导电连接部；76、第四导电连接部；77、第五导电连接部；80、过孔；91、阳极；10、连接线。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开实施方式中提供了一种阵列基板，参考图1，该阵列基板沿行方向、列方向阵列排布有多个像素单元，像素单元包括多个子像素。阵列基板包括多条初始化信号线51和多条连接线10。以图中第一方向为行方向，第二方向为列方向为例，多条初始化信号线51设于一导电层，沿行方向延伸且沿列方向间隔排列，每一条初始化信号线51 用于向行方向上位于同一行的各子像素提供初始化信号。多条连接线10设于另一导电层，沿列方向延伸且沿行方向间隔排列。其中，至少一条初始化信号线51与至少一条连接线10在衬底基板上的投影均相交且通过过孔连接，以使初始化信号线51和连接线10在衬底基板上的投影相交形成网格状结构。
将横向的初始化信号线51通过纵向的连接线10连接成网格状结构，增多了初始化信号的路径，初始化信号可以通过更多路径传递至每一子像素，进而降低因电流传递路径单一导致的IR drop过大的问题。相比在一层中布线，整个网格结构分为两层布线，可以减少布线空间压力，减少因单层布线过紧密而使初始化信号易受其他信号(如扫描信号)跳变的影响，降低对发光性能的影响，提高面板的显示均一性。
需要说明的是，初始化信号线51横向设置是指初始化信号线51主体结构沿横向延伸，实际产品中，可能会有局部并非完全横向设置，例如会拐弯以避开其他电路结构，或向其他方向延伸以便于与其他线路连接，等等，只要初始化信号线51的整体走向是横向方向即可。同理，连接线10纵向设置是指连接线10主体结构沿纵向延伸，整体走向是纵向方向。
以下对本实施方式的阵列基板进行详细说明：
本实施方式中，每个像素单元由RGBG四个子像素组成，各子像素都通过单独的子像素驱动电路进行驱动。
图2示出了一种9T1C的子像素电路结构，子像素电路结构包括一个电容和九个TFT晶体管T1～T9，本实施例中，所有TFT均为P型TFT，其中第三晶体管T3为驱动晶体管，其他晶体管为开关晶体管。
参考图2，电容包括第一极板Cst1和第二极板Cst2，第一极板Cst1设于第一栅线层300，第二极板Cst2设于第二栅线层500。第一极板Cst1连于节点N2，第二极板Cst2连于节点N1。驱动晶体管T3(第三晶体管)的栅极3g由电容的第一极板Cst1复用，源极3s与电源线72连接；第一晶体管T1的栅极1g与扫描线31连接，源极1s与数据线71连接，漏极1d连于节点N1。第二晶体管T2的栅极2g与扫描线31连接，源极2s与驱动晶体管T3的漏极3d连接，漏极2d连于节点N2。第四晶体管T4的栅极4g与复位信号线32连接，源极4s与初始信号线51电连接，漏极4d连于节点N2。第五晶体管T5的栅极5g与复位信号线32连接，源极5s与初始信号线51电连接，漏极5d连于节点N1。第六晶体管T6的栅极6g与发光控制信号线33连接，源极6s与初始信号线51电连接，漏极6d连于节点N1。第七晶体管T7的栅极7g与发光控制信号线33 连接，源极7s与驱动晶体管T3的漏极3d电连接，漏极7d与子像素的阳极91电连接。第八晶体管T8的栅极8g与复位信号线32连接，源极8s与初始信号线51电连接，漏极8d与子像素的阳极91电连接。第九晶体管T9的栅极9g与发光控制信号线33连接，源极9s连于节点N2。
其中，初始化信号线51提供的初始化信号为Vint，复位信号线32提供的复位信号为Reset，发光控制信号线33提供的发光控制信号为EM，扫描线31提供的扫描信号为gate，数据线71提供的数据信号为data，电源线72提供的电源信号为ELVDD。
参考图3所示的时序图，该子像素补偿电路具体工作原理如下：
第1阶段，复位信号Reset为低电平。第四晶体管T4打开，初始信号Vint对N2点进行初始化，此时N2点电位为初始信号Vint。第五晶体管T5打开，初始信号Vint写入N1点。第八晶体管T8打开，释放上一帧显示残留电荷，初始信号Vint写入降低OLED器件阳极和阴极之间的电压差，在低灰阶时降低OLED器件的亮度，提高像素的对比度。
第2阶段，扫描线31信号Gate为低电平。第一晶体管T1打开，此时N1点电位为Vdata，数据信号电压写入N1点。第二晶体管T2打开，对驱动晶体管T3二极管连接进行采样，N2点电位升高至ELVDD+Vth，驱动晶体管T3逐渐由打开状态变为关闭状态，对驱动晶体管T3的阈值电压Vth进行补偿。
第3阶段，发光控制信号EM为低电平。第六晶体管T6打开，此时N1点电位为初始信号Vint。第九晶体管T9打开，发光阶段降低N2点漏电。随着N1点电位跳变，此时N2点电位变为ELVDD+Vth+Vint-Vdata。第七晶体管T7打开，驱动电流输出，OLED器件发光。OLED器件的电流计算公式为
Figure PCTCN2021075289-appb-000001
通过上述电路，可在采样阶段对驱动晶体管T3的阈值电压Vth进行补偿，进而消除不同像素的DTFT阈值电压Vth差异对显示亮度均一性的影响。
本实施例中，Vint可以作为初始化信号，也可以作为数据写入时的参考信号。
在本实施方式中，上述各子像素的子像素驱动电路制备于一衬底基板。衬底基板上层叠设置有源层100、第一栅线层300、第二栅线层500、源漏极层700，这些膜层用于形成各种信号线或导线，向各子像素驱动电路提供相应的电信号。两膜层之间均通过绝缘层进行绝缘，例如有源层100和第一栅极层300之间设置第一栅绝缘层200，第一栅线层300和第二栅线层500之间设置第二栅绝缘层400，第二栅线层500和源漏极层700 之间设置介质层600，源漏极层700上方还进一步设置钝化层800等膜层。钝化层800上方设置子像素的阳极层900、有机发光层、阴极层等膜层，以形成OLED发光器件，各子像素的OLED发光器件通过像素界定层进行间隔。
图4示出了一种实施方式中多个子像素阵列排布的结构示意图，图5为一个子像素的子像素驱动电路、各种信号线在阵列基板上的层叠结构。图6-图9示出了有源层100、第一栅线层300、第二栅线层500、源漏极层700的膜层堆叠示意图，图10-图12示出了第一栅线层300、第二栅线层500、源漏极层700的各层结构示意图。
参考图6，有源层100用于设置各TFT晶体管的沟道区(1g-9g)、第一级(1s-9s)和第二级(1d-9d)。
参考图7和图10，第一栅线层300用于设置形成子像素驱动电路中各晶体管的栅极(如：1g～9g)、电容的第一极板Cst1、以及多条扫描线31、多条复位信号线32、多条发光控制信号线33等结构。多条扫描线31沿列方向间隔排列且沿行方向延伸，用于向行方向上位于同一行的各子像素提供扫描信号。多条复位信号线32沿列方向间隔排列且沿行方向延伸，用于向行方向上位于同一行的各子像素提供复位信号。多条发光控制信号线33沿行方向延伸且沿列方向间隔排列，用于向行方向上位于同一行的各子像素提供发光控制信号。其中，在每一个子像素区域内，复位信号线32位于最上方，扫描线31位于最下方，发光控制信号线33位于复位信号线32和扫描线31之间，电容的第一极板Cst1位于发光控制信号线33和扫描线31之间。在列方向上，下一级子像素的复位信号线32可以与上一级子像素的扫描线31相连，以使上一级子像素的扫描信号能够作为下一级子像素的复位信号，从而避免为复位信号单独引入专门的信号线，有效减少布线空间。
参考图8和图11，第二栅线层500用于设置形成电容的第二极板Cst2等结构，且本实施方式中初始化信号线51也设置于第二栅线层500。其中，电容的第二极板Cst2在阵列基板厚度方向上与第一极板Cst1对应，初始化信号线51在阵列基板上的投影位于第二极板Cst2投影靠近复位信号线32投影的一侧。本实施方式中，初始化信号线51与复位信号线32在衬底基板上的投影有交叠，大大节省了布线空间。
参考图9和图12，源漏极层700用于设置纵向的电源线72、数据线71及其他结构。电源线72沿列方向延伸且沿行方向间隔排列，用于向位于同一列的各子像素提供电源信号。数据线71沿列方向延伸且沿行方向间隔排列，用于向位于同一列的各子像素提供数据线71信号。其中，电源线72和数据线71在阵列基板上的投影均与电容的第一 极板Cst1、第二极板Cst2无重叠。
参考图8和图11，在一种实施方式中，第二栅线层500还包括多条电源引线52，多条电源引线52沿行方向延伸且沿列方向间隔排列，位于同一行的各电源线72通过设于介质层600的过孔连接于一条电源引线52，由此使得电源引线52与电源线72也形成了网格状结构，能够降低电源电压的压降。
参考图9和图12，在一种实施方式中，源漏极层700还包括多个第二导电连接部74，各第二导电连接部74设于源漏极层700且分布于各子像素区域内。每个子像素区域内，第二导电连接部74在衬底基板上的投影与第一晶体管T1的漏极1d、第五晶体管T5的漏极5d、第六晶体管T6的6d的投影重叠，且通过贯穿第一栅绝缘层200、第二栅绝缘层400、介质层600的过孔相连，第二导电连接部74在衬底基板上的投影还与电容的第二极板Cst2的投影重叠，且通过贯穿介质层600的过孔电连接，也就是说，1d、5d、6d均通过第二导电连接部74与电容的第二极板Cst2电连接。
参考图9和图12，在一种实施方式中，源漏极层700还包括多个第三导电连接部75，各第三导电连接部75设于源漏极层700且分布于各子像素区域内。每个子像素区域内，第三导电连接部75在衬底基板上的投影与第二晶体管T2的2d、第九晶体管T9的第一级9s的投影重叠，且通过贯穿第一栅绝缘层200、第二栅绝缘层400、介质层600的过孔相连，第三导电连接部75在衬底基板上的投影还与电容的第一极板Cst1的投影重叠，且通过贯穿第二栅绝缘层400、介质层600的过孔电连接，也就是说，2d、9s均通过第三导电连接部75与电容的第一极板Cst1电连接。
参考图9和图12，在一种实施方式中，源漏极层700还包括多个第四导电连接部76，各第四导电连接部76设于源漏极层700且分布于各子像素区域内。每个子像素区域内，第四导电连接部76在衬底基板上的投影与第八晶体管T8的8d重叠，且通过贯穿第一栅绝缘层200、第二栅绝缘层400、介质层600的过孔电连接，也就是说，8d通过第四导电连接部76与阳极91电连接。
参考图9和图12，在一种实施方式中，源漏极层700还包括多个第五导电连接部77，各第五导电连接部77设于源漏极层700且分布于各子像素区域内，用于连接T4、T5、T6、T8的源极和初始信号线51。具体而言，第五导电连接部77通过一个贯穿第一栅绝缘层200、第二栅绝缘层400、介质层600的过孔与有源层100第五晶体管T5的源极5s连接，第五导电连接部77还通过另一个贯穿介质层600的过孔与第二栅极层的初始信号线51连接，从而使得第五晶体管T5的源极5s与初始信号线51实现电连接。 同时，参考图4，由于第五晶体管T5的源极5s和第六晶体管T6的源极6s共同连接于行方向上右侧的子像素中的第八晶体管T8的源极8s、第四晶体管T4的源极4s，由此使得T4、T5、T6、T8的源极均与初始信号线51实现连接，由此可以简化过孔的数量。
阵列基板上还设置有OLED发光器件，源漏极层700上方设有像素界定层，像素界定层具有多个开口，用于定义各子像素。阳极层900用于设置OLED发光器件的阳极91，位于像素界定层的开口内。进一步地，开口内还设置有有机发光层、阴极层。OLED发光器件的膜层结构可采用常规结构，此处不再赘述。如图13所示，为一种RGBG像素结构的阳极层900结构示意图。
在本实施方式中，参考图13，连接线10设于阳极层900，在纵向方向上穿过两个阳极91之间的空隙，且与任意阳极91都绝缘。连接线10被像素界定层覆盖，以避免与上方其他膜层接触。
需要说明的是，由于在阳极层900形成连接线10是通过对阳极91材料(例如ITO/Ag/ITO)进行刻蚀，且阳极91材料通常采用湿法刻蚀，对PPI较高的面板而言刻蚀难度较大，因此应尽量避免连接线10在横向方向上有过多的设置，而保证整体沿纵向走线，若在阳极层900形成网格状封闭图形，则容易产生刻蚀不良。
在本实施方式中，连接线10的数量小于行方向上子像素的数量，也就是说，在行方向上，初始化信号线51与各连接线10在部分子像素区域通过过孔电连接。参考图1和图4，连接线10的数量为行方向上子像素数量的一半，且每间隔一个子像素设置一条，那么每间隔一个子像素，初始化信号线51就和一条连接线10通过过孔连接。因此，行方向上每相邻两个子像素中有一个设置有连接线10和过孔，而另一个不设置。在其他实施方式中，连接线10的数量小于行方向上子像素的数量时，相邻两条连接线10之间也可以间隔不同数量的子像素。
在其他实施方式中，参考图27，连接线10的数量与行方向上子像素的数量也可以相等。也就是说，在行方向上，初始化信号线51与各连接线10在每一子像素区域都通过过孔电连接。因此，行方向上每个子像素中都设置有连接线10和过孔。只要多条连接线10和多条初始化信号线51在衬底基板上的投影能形成网格状结构即可。可以理解的是，连接线10的数量越多，网格越密，初始化信号的传递路径越多，越能够降低IR drop，但布线的空间压力也会越大，制备工艺难度也越大。因此具体数量可根据实际情况进行设置。
为了实现初始化信号线51和连接线10的连接，参考图9和图12，阵列基板还包括 多个设于源漏极层700的第一导电连接部73，多个第一导电连接部73分布于初始化信号线51与连接线10的投影相交处所在的子像素区域，图9(a)表示初始化信号线51与连接线10的投影相交的层叠结构，图9(b)表示初始化信号线51不与连接线10的投影相交的层叠结构。换句话说，不一定所有子像素的源漏极层700都设置有第一导电连接部73，而是初始化信号线51与连接线10在哪个子像素连接，就在哪个子像素设置。图12中700表示设置有第一导电连接部73的源漏极层结构，700’表示未设置第一导电连接部73的源漏极层结构。设置有第一导电连接部73的子像素区域内，第一导电连接部73在衬底基板的投影分别与初始信号线51和连接线10具有重叠区域，第一导电连接部73与初始信号线51通过贯穿介质层600的过孔连接，第一导电连接部73与连接线10通过贯穿钝化层800上的过孔连接，由此使得初始化信号线51和连接线10通过第一导电连接部73形成电连接。
本实施例中，如图12所示，第一导电连接部73和第五导电连接部77连接为一体，由此可见简化源漏极层700导电连接部的制备。由于第一导电连接部73和第五导电连接部77连接为一体，那么第一导电连接部73在衬底基板上的投影与初始信号线51具有重叠区域，也可以理解为第五导电连接部77在衬底基板上的投影与初始信号线51具有重叠区域，都可以实现第五导电连接部77与初始化信号线51的连接。相应的，第一导电连接部73与连接线10通过过孔连接，也可以理解为第五导电连接部77与连接线10通过过孔连接。第一导电连接部73和第五导电连接部77连接为一体的形状包括但不限于图12所示的L形。图14示出了第一导电连接部73和第五导电连接部77部分的剖面图，为图12中A-A向的剖面图，在设置过孔时，使多个过孔在厚度方向上相互错开。
图4所示的实施方式中，复位信号线32和上一级扫描线31连接，初始化信号线51和复位信号线32交叠，连接线10在阳极层900布线，大大节省了布线空间，可适用于PPI更高一些的面板，例如PPI大于410的面板。
在另一种具体实施方式中，为了尽量减少初始化信号线51和复位信号线32交叠产生的交叉静电对面板的影响，对图1、图5的结构进行了改进，参考图15和图16，初始化信号线51不再是一整条连续的信号线，而是包括多段相互分隔的信号段510，即初始化信号线51分为横向多个小段，各信号段510一一对应于各像素单元，每一信号段510在对应的像素单元内的至少一个子像素区域内与复位信号线32的投影无重叠，在其余子像素区域内与复位信号线32的投影均相交。
举例而言，如图15所示，每个信号段510横跨一个像素单元，在一个像素单元内， 信号段510在三个子像素区域内与复位信号线32的投影有重叠，而在一端的子像素区域内与复位信号线32的投影无重叠，截止于复位信号线32的一侧。这样能够减少像素单元内产生交叉静电的概率，且一个像素单元内的交叉静电也不会影响其他像素单元。
需要说明的是，即使初始化信号线51被划分为多个信号段510，但每个纵向的连接线10都会连接一个信号段510，因此，可以认为，每一条初始化信号线51与每一条连接线10都连接。另外，本实施方式横向的初始化信号线51虽然是断开的，但那由于其与纵向的连接线仍然形成交叉，因此也视为网格状结构。也就是说，本公开所述的网格状结构包括图1所示的完整的网格结构，也包括图16所示的中间断开的网格结构。如图17所示为设于阳极层900的连接线10和设于第二栅极层的初始化信号线51的透视图。
图18示出了另一种实施方式中多个子像素阵列排布的结构示意图，图19为一个子像素的子像素驱动电路、各种信号线在阵列基板上的层叠结构。图20-图22示出了第一栅线层300、第二栅线层500、源漏极层700的膜层堆叠示意图，图23-图25示出了第一栅线层300、第二栅线层500、源漏极层700的各层结构示意图。有源层100与上一实施方式图6结构相同，故此处省略相关附图。本实施方式中，连接线10也设于阳极层900。其中，图22(a)表示初始化信号线51与连接线10的投影相交的层叠结构，图22(b)表示初始化信号线51不与连接线10的投影相交的层叠结构。图25中700表示设置有第一导电连接部73的源漏极层结构，700’表示未设置第一导电连接部73的源漏极层结构。
参考图20和图21，在一个子像素区域内，初始化信号线51在衬底基板上的投影位于本级子像素的复位信号线32和上一级子像素的扫描线31的投影之间，且初始化信号线51、本级子像素的复位信号线32、上一级子像素的扫描线31三者的投影均不重叠。也即是说，初始化信号线51、本级子像素的复位信号线32、上一级子像素的扫描线31三者的投影都相互间隔。下一级子像素的复位信号线32和上一级子像素的扫描线31可在在阵列基板的周边区进行连接，以使上一行子像素的扫描信号在周边区输入下一行子像素的复位信号线32。该结构可以避免初始化信号线51与复位信号线32、扫描线31之间产生交叉静电，也可以避免因初始化信号线51与扫描线31距离过近导致初始化信号易受扫描信号跳变的影响。在该结构下，相比图5所示结构，本实施方式的布线方式会占用较多的面积，因此适用于PPI稍低的面板，例如PPI小于410的面板。
本实施方式中，源漏极层700的走线布置也与上一实施方式相同，即包括了第一- 第五导电连接部。且同样的，在本实施方式中，连接线10设于阳极层900，连接线10通过第五导电连接部77与初始化信号线51连接。第一导电连接部73和第五导电连接部77连接为一体的形状包括但不限于图25所示的T形，第一导电连接部73和第五导电连接部77在图25中B-B向的剖面图如图26所示，在设置过孔时，多个过孔在厚度方向上相互错开。
图27示出了另一种实施方式中多个子像素阵列排布的结构示意图，图28为一个子像素的子像素驱动电路、各种信号线在阵列基板上的层叠结构。图29-图30示出了第二栅线层500、源漏极层700的膜层堆叠示意图，图31-图32示出了第二栅线层500、源漏极层700的各层结构示意图。有源层100和第一栅极层300的结构与图6、图7结构相同，故此处省略相关附图。
参考图29和图31，与前面实施方式不同的是，初始化信号线51还包括了主体段511和延伸段512，初始化信号线51的主体段511沿行方向延伸，其在衬底基板上的投影位于复位信号线32远离上一级扫描线31的一侧，且位于电源引线52靠近上一级子像素的一侧。初始化信号线51的延伸段512绕过复位信号线32并延伸至复位信号线32和上一级扫描线31之间，该结构即可以避免初始化信号线51与复位信号线32、扫描线31之间产生交叉静电，也便于与连接线10连接。
参考图30和图32，与前面实施方式不同的是，连接线10设于源漏极层700。如图所示，在子像素区域内，连接线10位于电源线72远离数据线71的一侧，例如可以位于第二导电连接部74和第三导电连接部75远离电源线72的一侧。连接线10整体沿列方向延伸，其中部分为了避开第四导电连接部76向右侧弯折。由于连接线10不需要与阳极层900连接，因此不包括第一导电连接部73。具体参考图33示出的连接线10和第五导电连接部77部分的剖面图，该图为图32中C-C向的剖面图，连接线10可与第五导电连接部77连接为一体，通过第五导电连接部与初始化信号线51连接。由此即可以避开其他线路结构，又可以实现跨层连接，还简化了连接结构。该结构相比图5和图17所示结构，在源漏极层700上布线会占用较多的面积，因此适用于PPI更低的面板，例如PPI小于385的面板。但由于源漏极层700采用干法刻蚀，相比阳极层900采用湿法刻蚀，可降低刻蚀阳极91材料时存在的不良风险。而且源漏极层700材料相比阳极层900材料，电阻更低，有利于改善IR drop。
本实施方式中，源漏极层700其他线路的走线布置也与上一实施方式相同。本实施方式与图5和图17所示结构的另外一不同之处在于，连接线10的数量与行方向上子像 素的数量相等，即每个子像素内都有初始化信号线51和连接线10相交并通过过孔连接，也就是说，所有子像素内部结构都一样。
以上实施方式给出了本公开初始化信号线和连接线的多种设置位置和连接方式，本公开的各种结构均可以在合理布线的同时兼顾不同产品PPI的要求、性能的要求。可以理解的是，初始化信号线和连接线的设置位置、连接方式可以任意组合，以便适应显示面板PPI、工艺可实施性和显示性能的需求。另外，以上实施方式是以9T1C的像素电路结构为例进行说明，当阵列基板采用其他像素电路结构时，也可以将初始化信号线和连接线分层连接呈网格状，同样能够降低IR drop同时缓解布线压力。另外，上述每个像素单元由RGBG四个子像素组成，且仅以一种算法进行排列为例进行了说明，本公开初始化信号线和连接线分层连接呈网格状的结构也能够适用于其他算法进行排列的RGBG像素结构。进一步地，当像素单元采用其他设置方式时，例如RGB、RGBW等时，也可以将初始化信号线和连接线分层连接呈网格状，同样能够降低IR drop同时缓解布线压力。
本公开实施方式还提供一种显示装置，该显示装置包括上述实施方式的阵列基板。由于该显示装置包括上述阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
本公开对于显示装置的适用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有柔性显示功能的产品或部件。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (18)

  1. 一种阵列基板，阵列排布有多个像素单元，所述像素单元包括多个子像素，其中，所述阵列基板包括：
    多条初始化信号线，设于衬底基板上的一导电层，沿第一方向延伸且沿第二方向间隔排列，用于向各所述子像素提供初始化信号；所述第一方向和第二方向相交；
    多条连接线，设于所述衬底基板上的另一导电层，沿所述第二方向延伸且沿所述第一方向间隔排列；
    其中，至少一条所述初始化信号线与至少一条所述连接线在所述衬底基板上的投影均相交且通过过孔连接，以使所述初始化信号线和所述连接线在所述衬底基板上的投影形成网格状结构。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括衬底基板和依次层叠设置于所述衬底基板上的第一栅线层、第二栅线层、源漏极层、阳极层；所述第一方向为行方向，所述第二方向为列方向；
    所述初始化信号线设于所述第二栅极层；
    所述连接线设于所述源漏极层或阳极层。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    多条扫描线，设于所述第一栅线层，沿所述行方向延伸且沿列方向间隔排列，用于向各所述子像素提供扫描信号；
    多条复位信号线，设于所述第一栅线层，沿所述行方向延伸且沿列方向间隔排列，用于向各所述子像素提供复位信号。
  4. 根据权利要求3所述的阵列基板，其中，在所述子像素区域内，所述初始化信号线在所述衬底基板上的投影位于所述复位信号线和上一级子像素的扫描线的投影之间，且所述初始化信号线、复位信号线、扫描线三者的投影均不重叠。
  5. 根据权利要求3所述的阵列基板，其中，在所述子像素区域内，所述初始化信号线在所述衬底基板上的投影位于所述复位信号线的投影背离上一级子像素的扫描线的一侧，且所述初始化信号线、复位信号线、扫描线三者的投影均不重叠。
  6. 根据权利要求3所述的阵列基板，其中，在所述子像素区域内，所述复位信号线和上一级子像素的扫描线连接为一体；
    所述初始化信号线在所述衬底基板上的投影与所述复位信号线的投影相交。
  7. 根据权利要求6所述的阵列基板，其中，所述初始化信号线包括多段相互分隔 的信号段，各所述信号段一一对应于各所述像素单元；
    其中，每一所述信号段在对应的所述像素单元内的至少一个所述子像素区域内与所述复位信号线的投影无重叠，在其余所述子像素区域内与所述复位信号线的投影均相交。
  8. 根据权利要求1-7中任一项所述的阵列基板，其中，所述连接线的数量与所述行方向上子像素的数量相等，在所述行方向上，所述初始化信号线与各所述连接线在每一子像素区域都通过过孔电连接；
    或，所述连接线的数量小于所述行方向上子像素的数量，在所述行方向上，所述初始化信号线与各所述连接线在部分子像素区域通过过孔电连接。
  9. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括：
    多条电源线，设于所述源漏极层，沿列方向延伸且沿所述行方向间隔排列，用于向各所述子像素提供电源信号；
    多条数据线，设于所述源漏极层，沿列方向延伸且沿所述行方向间隔排列，用于向各所述子像素提供数据信号。
  10. 根据权利要求9所述的阵列基板，其中，所述子像素包括阳极，所述连接线和所述阳极均设于所述阳极层，所述连接线与所述阳极绝缘。
  11. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括：
    多个第一导电连接部，设于所述源漏极层，且分布于所述初始化信号线与所述连接线的投影相交处所在的子像素区域；
    分布有所述第一导电连接部的子像素区域内，所述第一导电连接部在所述衬底基板的投影分别与所述初始信号线和连接线具有重叠区域，所述第一导电连接部与所述初始信号线通过过孔连接，所述第一导电连接部与所述连接线通过过孔连接。
  12. 根据权利要求9所述的阵列基板，其中，所述连接线设于所述源漏极层；
    所述子像素区域内，所述初始化信号线包括相互连接的主体段和延伸段，所述初始化信号线的主体段沿所述行方向延伸，所述初始化信号线的延伸段与主体段延伸方向不同；
    其中，所述初始化信号线的延伸段在所述衬底基板的投影与所述连接线的投影具有重叠，所述初始化信号线的延伸段和所述连接线在所述重叠区域通过过孔连接。
  13. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括：
    多条发光控制信号线，设于所述第一栅线层，沿所述行方向延伸且沿所述列方向间隔排列，用于向各所述子像素提供发光控制信号；
    在所述子像素区域内，所述发光控制信号线位于所述复位信号线远离上一级子像素的扫描线的一侧，且与所述初始化信号线的投影不重叠。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括：
    多条电源引线，设于所述第二栅线层，沿所述行方向延伸且沿所述列方向间隔排列，位于同一行的各所述电源线通过过孔连接于一条所述电源引线。
  15. 根据权利要求14所述的阵列基板，其中，所述子像素还包括子像素驱动电路，所述子像素驱动电路包括：
    电容，包括第一极板和第二极板，所述第一极板设于所述第一栅线层，所述第二极板设于所述第二栅线层；
    驱动晶体管，所述电容的第一极板复用为所述驱动晶体管的栅极，所述驱动晶体管的第一级与所述电源线连接；
    第一晶体管，所述第一晶体管的栅极与所述扫描线连接，所述第一晶体管的第一级与所述数据线连接，所述第一晶体管的第二级与所述电容的第二极板连接；
    第二晶体管，所述第二晶体管的栅极与所述扫描线连接，所述第二晶体管的第一级与所述驱动晶体管的第二级连接，所述第二晶体管的第二级与所述电容的第一极板连接；
    第四晶体管，所述第四晶体管的栅极与所述复位信号线连接，所述第四晶体管的第一级与所述初始信号线电连接，所述第四晶体管的第二级与所述电容的第一极板电连接；
    第五晶体管，所述第五晶体管的栅极与所述复位信号线连接，所述第五晶体管的第一级与所述初始信号线电连接，所述第五晶体管的第二级与所述电容的第二极板电连接；
    第六晶体管，所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一级与所述初始信号线电连接，所述第六晶体管的第二级与所述电容的第二极板电连接；
    第七晶体管，所述第七晶体管的栅极与所述发光控制信号线连接，所述第七晶体管的第一级与所述驱动晶体管的第二级电连接，所述第七晶体管的第二级与所述子像素的阳极电连接；
    第八晶体管，所述第八晶体管的栅极与所述复位信号线连接，所述第八晶体管的第一级与所述初始信号线电连接，所述第八晶体管的第二级与所述子像素的阳极电连接；
    第九晶体管，所述第九晶体管的栅极与所述发光控制信号线连接，所述第九晶体管的第一级与所述电容的第一极板电连接。
  16. 根据权利要求15所述的阵列基板，其中，所述阵列基板还包括：
    多个第二导电连接部，设于所述源漏极层且分布于各所述子像素区域内；
    多个第三导电连接部，设于所述源漏极层且分布于各所述子像素区域内；
    所述子像素区域内，所述第二导电连接部分别与所述第一晶体管的第二级、第五晶体管的第二级、第六晶体管的第二级以及所述电容的第二极板通过过孔连接，所述第一晶体管的第二级、第五晶体管的第二级、第六晶体管的第二级均通过所述第二导电连接部与所述电容的第二极板电连接；
    所述子像素区域内，所述第三导电连接部分别与所述第四晶体管的第二级、第九晶体管的第一级以及所述电容的第一极板通过过孔连接，所述第四晶体管的第二级、第九晶体管的第一级均通过所述第三导电连接部与所述电容的第一极板电连接。
  17. 根据权利要求16所述的阵列基板，其中，所述阵列基板还包括：
    多个第五导电连接部，设于所述源漏极层且分布于各所述子像素区域内；
    所述第五导电连接部通过一个过孔与所述第五晶体管的第一级连接，所述第五导电连接部还通过另一个过孔与所述初始信号线连接，以使所述第五晶体管的第一级与初始信号线连接；
    所述连接线设于所述源漏极层，所述连接线与所述第五导电连接部连接，以通过所述第五导电连接部与所述初始信号线连接。
  18. 一种显示装置，其中，包括权利要求1-17中任一项所述的阵列基板。
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