WO2021035416A1 - 显示装置及其制备方法 - Google Patents

显示装置及其制备方法 Download PDF

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Publication number
WO2021035416A1
WO2021035416A1 PCT/CN2019/102309 CN2019102309W WO2021035416A1 WO 2021035416 A1 WO2021035416 A1 WO 2021035416A1 CN 2019102309 W CN2019102309 W CN 2019102309W WO 2021035416 A1 WO2021035416 A1 WO 2021035416A1
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Prior art keywords
transistor
doped region
electrode
base substrate
driving
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PCT/CN2019/102309
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English (en)
French (fr)
Inventor
李大超
杨盛际
许晨
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/960,729 priority Critical patent/US11600681B2/en
Priority to CN201980001449.0A priority patent/CN112740421A/zh
Priority to CN202210506912.0A priority patent/CN114864647A/zh
Priority to EP19933233.9A priority patent/EP4020596A4/en
Priority to PCT/CN2019/102309 priority patent/WO2021035416A1/zh
Priority to US16/814,119 priority patent/US11600234B2/en
Publication of WO2021035416A1 publication Critical patent/WO2021035416A1/zh
Priority to US17/852,485 priority patent/US20220328608A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the embodiment of the present disclosure relates to a display device and a manufacturing method thereof.
  • the Micro Organic Light-Emitting Diode (Micro-OLED) display device is a new type of OLED display device using a silicon substrate as a substrate, and is also called a silicon-based organic light-emitting diode (silicon-based OLED) display device.
  • the silicon-based OLED display device has the advantages of small size and high resolution. It is prepared by mature CMOS integrated circuit technology, which can realize the active addressing of pixels, and can be prepared on a silicon-based substrate including TCON (timing control) circuits, Various functional circuits such as OCP (operation control) circuit can be lightweight.
  • At least one embodiment of the present disclosure provides a display device, including a base substrate and at least one pixel circuit formed on the base substrate, the pixel circuit including a driving transistor, a first transistor, and a second transistor; the driving The transistor includes a control electrode, a first electrode, and a second electrode, and is configured to control the voltage flowing through the first electrode of the driving transistor and the second electrode of the driving transistor according to the voltage of the control electrode of the driving transistor.
  • the first electrode of the first transistor is connected to the control electrode of the driving transistor, and is configured to write a data signal to the control of the driving transistor in response to a first scan signal
  • the first electrode of the second transistor is connected to the control electrode of the driving transistor and is configured to write the data signal to the control electrode of the driving transistor in response to a second scan signal;
  • the substrate includes a doped semiconductor body, and a first conductive layer and a second conductive layer on the semiconductor body;
  • the first transistor includes a first doped region in contact with the first electrode of the first transistor , The second doped region in contact with the second electrode of the first transistor, the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other and have the same doping type And are all located in the semiconductor body;
  • the first transistor also includes a drift doped region in contact with the first doped region, the drift doped region of the first transistor and the second doped region of
  • the base substrate further includes a first insulating layer located between the semiconductor body and the first conductive layer; the first insulating layer includes The first part of the first doped region of the first transistor and the second part of the second doped region away from the first transistor.
  • the thickness of the first portion of the first insulating layer is greater than the thickness of the second portion of the first insulating layer, and the thickness is greater than that of the base substrate.
  • the thickness in the vertical direction is greater than the thickness of the first portion of the first insulating layer.
  • At least one embodiment of the present disclosure provides a display device, including a base substrate and at least one pixel circuit formed on the base substrate, the pixel circuit including a driving transistor, a first transistor, and a second transistor; the driving The transistor includes a control electrode, a first electrode, and a second electrode, and is configured to control the voltage flowing through the first electrode of the driving transistor and the second electrode of the driving transistor according to the voltage of the control electrode of the driving transistor.
  • the first electrode of the first transistor is connected to the control electrode of the driving transistor, and is configured to write a data signal to the control of the driving transistor in response to a first scan signal
  • the first electrode of the second transistor is connected to the control electrode of the driving transistor, and is configured to write the data signal to the control electrode of the driving transistor in response to a second scan signal;
  • the The base substrate includes a doped semiconductor body, and a first conductive layer and a second conductive layer formed on the surface of the semiconductor body;
  • the first transistor includes a first electrode in contact with the first transistor A first doped region, a second doped region in contact with the second electrode of the first transistor, the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other ,
  • the doping type is the same and they are all located in the semiconductor body;
  • the base substrate further includes a first insulating layer formed between the semiconductor body and the first conductive layer, and the first insulating layer includes The first
  • the first transistor further includes a drift doped region in contact with the first doped region of the first transistor, and the drift doped region of the first transistor And the second doped region of the first transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body; the orthographic projection of the gate of the first transistor on the base substrate and the The orthographic projection of the drift doped region of the first transistor on the base substrate partially overlaps, and the orthographic projection of the first doped region of the first transistor on the base substrate is located on the base substrate of the first transistor.
  • the drift doped region is in an orthographic projection on the base substrate; the doping concentration of the drift doped region of the first transistor is lower than the doping concentration of the first doped region of the first transistor.
  • the first transistor is a P-type MOS transistor, and the doping type of the first doped region in the first transistor is P-type; the semiconductor body The doping type is P-type bulk silicon or silicon on insulating layer.
  • the first doped region, the second doped region, and the drift doped region of the first transistor are located in the first well in the semiconductor body, and the The doping type of the first well is N-type; the orthographic projection of the gate of the first transistor on the base substrate is located in the orthographic projection of the first well on the base substrate, and the The portion of the first well located between the first doped region of the first transistor and the second doped region of the first transistor constitutes the channel region of the first transistor.
  • the first transistor further includes an auxiliary doped region, the doping type of the auxiliary doped region of the first transistor is N-type, and the The auxiliary doped region is in contact with the second doped region of the first transistor, the auxiliary doped region of the first transistor is electrically connected to the second electrode of the first transistor, and the auxiliary doped region of the first transistor is The orthographic projection of the miscellaneous region on the base substrate is located in the orthographic projection of the first well on the base substrate.
  • the first transistor is an N-type MOS transistor, and the doping type of the first doped region in the first transistor is N-type; the semiconductor body The doping type is P-type bulk silicon or silicon on insulating layer.
  • the first transistor further includes an auxiliary doped region, the doping type of the auxiliary doped region of the first transistor is P-type, and the The auxiliary doped region is in contact with the second doped region of the first transistor, and the auxiliary doped region is electrically connected to the second electrode of the first transistor.
  • the base substrate further includes a planarization insulating layer, the planarization insulating layer covers the gate of the first transistor, and the light-emitting element is located in the Planarize the insulating layer.
  • the second transistor includes a first doped region in contact with the first electrode of the second transistor, and a doped region in contact with the second electrode of the second transistor.
  • the first doped region of the second transistor and the second doped region of the second transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body.
  • the second transistor further includes an auxiliary doped region, and the auxiliary doped region of the second transistor is in contact with the second doped region of the second transistor,
  • the auxiliary doped region of the second transistor is electrically connected to the second electrode of the second transistor, and the doping type of the auxiliary doped region of the second transistor is the same as that of the second doped region of the second transistor.
  • the doping type is opposite.
  • the doping type of the first doped region of the first transistor is opposite to the doping type of the first doped region of the second transistor.
  • the first transistor is a P-type MOS transistor, the doping type of the first doped region of the first transistor is P-type, and the second transistor is N-type MOS transistor, the doping type of the first doped region of the second transistor is N-type;
  • the semiconductor body is bulk silicon or silicon-on-insulating layer with the doping type of P-type;
  • the second transistor includes The first doped region in contact with the first electrode of the second transistor, the second doped region in contact with the second electrode of the second transistor, and the first doped region of the second transistor is in contact with the The second doped regions of the second transistor are spaced apart from each other, have the same doping type, and are all located in the semiconductor body.
  • the second transistor further includes a drift doped region in contact with the first doped region of the second transistor, and the drift doped region of the second transistor And the second doped region of the second transistor are spaced apart from each other, have the same doping type, and are both located in the semiconductor body; the orthographic projection of the gate of the second transistor on the base substrate is the same as the The orthographic projection of the drift doped region of the second transistor on the base substrate partially overlaps, and the orthographic projection of the first doped region of the second transistor on the base substrate is located on the base substrate of the second transistor.
  • the drift doped region is in an orthographic projection on the base substrate; the doping concentration of the drift doped region of the second transistor is lower than the doping concentration of the first doped region of the second transistor.
  • the first doped region, the second doped region, and the drift doped region of the first transistor are located in the first well in the semiconductor body, and the The doping type of the first well is N-type, the orthographic projection of the gate of the first transistor on the base substrate is located in the orthographic projection of the first well on the base substrate, and the The portion of the first well located between the first doped region of the first transistor and the second doped region of the first transistor constitutes the channel region of the first transistor.
  • the first transistor further includes an auxiliary doped region, the doping type of the auxiliary doped region of the first transistor is N-type, and the The auxiliary doped region is in contact with the second doped region of the first transistor, the auxiliary doped region of the first transistor is electrically connected to the second electrode of the first transistor, and the auxiliary doped region of the first transistor is The orthographic projection of the impurity region on the base substrate is located in the orthographic projection of the first well on the base substrate; the second transistor also includes an auxiliary doping region, and the auxiliary doping of the second transistor The doping type of the doping region is P-type, the auxiliary doping region of the second transistor is in contact with the second doping region of the second transistor, and the auxiliary doping region of the second transistor is in contact with the second transistor The second pole is electrically connected.
  • the base substrate further includes a first insulating layer and a second insulating layer formed between the semiconductor body and the first conductive layer;
  • An insulating layer includes a first part close to the first doped region of the first transistor and a second part away from the first doped region of the first transistor;
  • the second insulating layer includes a first part close to the second transistor The first part of the first doped region and the second part of the first doped region away from the second transistor.
  • the thickness of the first part of the first insulating layer is greater than the thickness of the second part of the first insulating layer, and the thickness of the first part of the second insulating layer is The thickness is greater than the thickness of the second portion of the second insulating layer, and the thickness is the thickness in a direction perpendicular to the base substrate.
  • the pixel circuit further includes a third transistor connected to the first electrode of the driving transistor and configured to switch The first power supply voltage is applied to the first pole of the driving transistor.
  • the base substrate is a P-type silicon base substrate
  • the first transistor is a P-type MOS transistor
  • the second transistor is a P-type MOS transistor
  • the driving transistors are all N-type MOS transistors.
  • the display device provided by an embodiment of the present disclosure further includes a driving circuit located in the base substrate, and the driving circuit is configured to provide the first scan signal to at least one pixel circuit in the display device, The second scan signal and the light emission control signal.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display device, including: forming a pixel circuit on a base substrate; the pixel circuit includes a driving transistor, a first transistor, and a second transistor; the driving transistor includes a control electrode , The first electrode and the second electrode, and are configured to control the first electrode of the driving transistor and the second electrode of the driving transistor for driving light emission according to the voltage of the control electrode of the driving transistor The driving current for the element to emit light; the first electrode of the first transistor is connected to the control electrode of the driving transistor and is configured to write a data signal to the control electrode of the driving transistor in response to a first scan signal; the The first electrode of the second transistor is connected to the control electrode of the driving transistor, and is configured to write the data signal to the control electrode of the driving transistor in response to the second scan signal; the base substrate includes a doped A heterogeneous semiconductor body; the preparation method further includes: forming a first conductive layer and a second conductive layer of the base substrate on the semiconductor body, wherein
  • the preparation method provided by an embodiment of the present disclosure further includes: forming a first insulating layer of the base substrate between the semiconductor body and the first conductive layer, and the first insulating layer includes The first part of the first doped region of the first transistor and the second part away from the first doped region of the first transistor; the thickness of the first part of the first insulating layer is greater than that of the first insulating layer The thickness of the second part is the thickness in a direction perpendicular to the base substrate.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display device, including: forming a pixel circuit on a base substrate; the pixel circuit includes a driving transistor, a first transistor, and a second transistor; the driving transistor includes a control electrode , The first electrode and the second electrode, and are configured to control the first electrode of the driving transistor and the second electrode of the driving transistor for driving light emission according to the voltage of the control electrode of the driving transistor The driving current for the element to emit light; the first electrode of the first transistor is connected to the control electrode of the driving transistor and is configured to write a data signal to the control electrode of the driving transistor in response to a first scan signal; the The first electrode of the second transistor is connected to the control electrode of the driving transistor, and is configured to write the data signal to the control electrode of the driving transistor in response to the second scan signal; the base substrate includes a doped A heterogeneous semiconductor body; the preparation method further includes: forming a first conductive layer and a second conductive layer of the base substrate on the semiconductor body, wherein
  • the manufacturing method provided by an embodiment of the present disclosure further includes: forming a drift doped region of the first transistor with the same doping type as the second doped region of the first transistor in the semiconductor body, so The drift doped region of the first transistor is located in the semiconductor body and is spaced apart from the second doped region of the first transistor, and the orthographic projection of the gate of the first transistor on the substrate is the same as The orthographic projection of the drift doped region of the first transistor on the base substrate partially overlaps, and the orthographic projection of the first doped region of the first transistor on the base substrate is located in the first In the orthographic projection of the drift doped region of the transistor on the base substrate, the doping concentration of the drift doped region of the first transistor is lower than the doping concentration of the first doped region of the first transistor.
  • Figure 1 is a schematic cross-sectional view of a display substrate
  • FIG. 2 is a circuit diagram of a display device provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a layout corresponding to FIG. 2 provided by at least one embodiment of the present disclosure
  • 4A-4E respectively show plan views of the five-layer layout of the display device shown in FIG. 3;
  • FIG. 5 is a schematic diagram illustrating a region where a storage capacitor is located according to at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the layout of storage capacitors provided by at least one embodiment of the present disclosure.
  • Figures 7A-7D respectively show plan views of the four layer distribution shown in Figure 6;
  • FIG. 7E is a schematic cross-sectional view of a storage capacitor provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view of a first transistor and a second transistor provided by at least one embodiment of the present disclosure
  • FIG. 9 is another schematic cross-sectional view of the first transistor and the second transistor provided by at least one embodiment of the present disclosure.
  • FIG. 10 is another schematic cross-sectional view of the first transistor and the second transistor provided by at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • silicon-based OLED display panels are widely used in near-eye display fields such as Virtual Reality (VR) or Augmented Reality (AR).
  • VR Virtual Reality
  • AR Augmented Reality
  • PPI Pixel Per Inch, the number of pixels per inch.
  • the display device and the manufacturing method thereof provided by at least one embodiment of the present disclosure can reduce the layout area occupied by the display device through layout design, thereby making the display device easier to achieve high PPI.
  • at least one embodiment of the present disclosure also provides a structure design of a transistor that can reduce or avoid the risk of breakdown by high voltage.
  • FIG. 1 is a schematic diagram of a structure of a display substrate 1000.
  • the display substrate 1000 includes a base substrate 600 and a light-emitting element 620.
  • the light-emitting element 620 is disposed on the base substrate 600, and the first electrode 621 of the light-emitting element 620 is closer to the base substrate 600 than the second electrode 629 of the light-emitting element 620 is.
  • the base substrate 600 is a silicon-based base substrate, and embodiments of the present disclosure include but are not limited to this.
  • the semiconductor manufacturing process used in the silicon-based substrate is mature and stable in performance, which is conducive to the manufacture of miniature display devices.
  • the silicon-based substrate 600 includes a driving circuit electrically connected to the light-emitting element 620 for driving the light-emitting element 620 to emit light.
  • the driving circuit includes a transistor T.
  • the specific circuit structure of the driving circuit can be set according to actual needs.
  • FIG. 1 does not show all the structure of the driving circuit, and the driving circuit may also include other transistors, for example, storage capacitors, etc., which is not limited in the embodiments of the present disclosure.
  • the transistor T includes a gate electrode G, a source electrode S, and a drain electrode D.
  • the three electrodes correspond to the three electrode connection parts, respectively.
  • the gate electrode G is electrically connected to the gate electrode connection portion 610g
  • the source electrode S is electrically connected to the source electrode connection portion 610s
  • the drain electrode D is electrically connected to the drain electrode connection portion 610d.
  • all three electrodes are electrically connected to the three electrode connecting portions through tungsten vias 605.
  • the source electrode connection portion 610s is electrically connected to the first electrode 621 of the light emitting element 620 through a tungsten via.
  • the source electrode connection portion 610s is electrically connected to the metal reflective layer 622 of the first electrode 621 through a tungsten via hole, and at the same time, in the first electrode 621, the transparent conductive layer 626 reflects the metal through the via hole 624a in the inorganic insulating layer 624.
  • Layer 622 is electrically connected.
  • the electrical signal provided by the power line can be transmitted to the transparent conductive layer 626 through the source electrode S of the transistor T, the source electrode connection portion 610s, and the metal reflective layer 622.
  • the positions of the source electrode S and the drain electrode D are interchangeable (correspondingly, the positions of the source electrode connection portion 610s and the drain electrode connection portion 610d are also interchangeable), that is, the position of the transistor One of the source electrode S and the drain electrode D (ie, the source electrode S or the drain electrode D) and the light emitting element 620 may be electrically connected to each other.
  • the material of the gate electrode connection part 610g, the source electrode connection part 610s, and the drain electrode connection part 610d may include a metal material.
  • an anti-oxidation layer 607 may be provided on at least one side (for example, the upper side and/or the lower side) of each of the gate electrode connection portion 610g, the source electrode connection portion 610s, and the drain electrode connection portion 610d. It can effectively prevent these electrode connections from being oxidized and improve their conductivity.
  • the display substrate 1000 further includes a defining layer 728 for defining the light-emitting function layer 727.
  • the defining layer 728 defines the organic light-emitting function layer 727 in the opening 728a thereof to avoid sub-pixels adjacent to each other. Crosstalk between.
  • the via 624 a in the inorganic insulating layer 624 may be disposed between the transparent conductive layer 626 and the edge area of the metal reflective layer 622.
  • the orthographic projection of the light-emitting function layer 627 on the base substrate 600 and the orthographic projection of the via 624a on the base substrate 600 are both located within the orthographic projection of the metal reflective layer 622 on the base substrate 600.
  • the via 624a basically has no effect on the reflection process.
  • At least one embodiment of the present disclosure provides a display device 100 that includes a base substrate, at least one pixel circuit formed on the base substrate, and a light-emitting element driven by the pixel circuit.
  • the base substrate is, for example, a silicon-based base substrate, and the silicon-based base substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate.
  • the pixel circuit can be prepared in a base substrate through a silicon semiconductor process (for example, a CMOS process), and the light-emitting element is prepared on a silicon substrate with the pixel circuit.
  • the display device 100 will be described below with reference to FIGS. 2 and 3. It should be noted that the base substrate is not shown in FIGS. 2 and 3. Regarding the base substrate, reference may be made to the base substrate 600 shown in FIG. 1.
  • the pixel circuit includes a driving transistor 140, a first transistor 110, a second transistor 120 and a third transistor 130. It should be noted that in some embodiments, the pixel circuit may not include the third transistor 130, which is not limited in the embodiments of the present disclosure.
  • the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and the driving transistor 140 is configured to control the flow of the first electrode 141 of the driving transistor 140 according to the voltage of the control electrode 143 of the driving transistor 140 And the driving current of the second pole 142 of the driving transistor 140 for driving the light-emitting element LE to emit light.
  • the light emitting element LE can emit light of different intensities according to the magnitude of the driving current.
  • the source and drain of the transistor used in the embodiments of the present disclosure may be symmetrical in structure, so the source and drain may be indistinguishable in structure.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, in the embodiments of the present disclosure, all or part of the transistors have the first pole.
  • the pole and the second pole are interchangeable as needed.
  • the first electrode of the transistor described in the embodiments of the present disclosure may be a source and the second electrode may be a drain; or, the first electrode of the transistor may be a drain and the second electrode may be a source.
  • the first electrode drain and the second electrode source of the transistor are used as examples for description, and will not be repeated here.
  • the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.
  • the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.
  • the third transistor 130 is connected to the first electrode 141 of the driving transistor 140 and is configured to apply the first power supply voltage ELVDD to the first electrode 141 of the driving transistor 140 in response to the light emission control signal EN.
  • the first power supply voltage ELVDD in the embodiment of the present disclosure is a high-level voltage, for example, the first power supply voltage ELVDD is 5V.
  • the first electrode 111 (for example, the drain) of the first transistor 110 and the first electrode 121 (for example, the drain) of the second transistor 120 are connected to obtain a common electrode, and
  • the common electrode is connected to the control electrode 143 of the driving transistor 140.
  • the first scan signal line SL1, the second scan signal line SL2, the data line DL, the first power supply voltage line VL1, the light emitting control line EL, etc. are also provided to provide corresponding electrical signals.
  • the control electrode 113 of the first transistor 110 is configured to receive the first scan signal SCAN1 from the first scan signal line SL1, and the second electrode 112 (for example, the source) of the first transistor 110 is configured to receive the data signal from the data line DL DATA.
  • the control electrode 123 of the second transistor 120 is configured to receive the second scan signal SCAN2 from the second scan signal line SL2, and the second electrode 122 (eg, source) of the second transistor 120 is configured to receive the data signal from the data line DL DATA.
  • the control electrode 133 of the third transistor 130 is configured to receive the light emission control signal EN from the light emission control line EL, and the first electrode 131 (for example, the drain) of the third transistor 130 is configured to receive the first light emission control signal EN from the first power supply voltage line VL1.
  • the second electrode 132 (for example, the source) of the third transistor 130 and the first electrode 141 (for example, the drain) of the driving transistor 140 are connected.
  • the second electrode 142 (for example, the source electrode) of the driving transistor 140 is configured to be connected to the first electrode of the light emitting element LE.
  • the second electrode 142 of the driving transistor 140 may be connected to the anode of the OLED.
  • the second pole of the light emitting element LE is configured to receive the fourth power supply voltage VCOM.
  • the fourth power supply voltage VCOM in the embodiment of the present disclosure is a low-level voltage.
  • the light-emitting element LE may be an OLED.
  • the second electrode (for example, the cathode electrode) of the plurality of light-emitting elements OLED in the plurality of pixel units ) Can be electrically connected together, for example, respectively connected to the same electrode or integrally formed to receive the fourth power supply voltage VCOM, that is, the multiple light-emitting elements OLED in multiple pixel units adopt a common cathode connection.
  • the light-emitting element OLED may be of various types, such as top emission, bottom emission, etc., which can emit red light, green light, blue light, or white light, which is not limited in the embodiments of the present disclosure.
  • the pixel circuit further includes a storage capacitor CST to store the data signal DATA written to the control electrode 143 of the driving transistor 140, so that the driving transistor 140 can control the driving according to the voltage of the stored data signal DATA.
  • the first electrode of the storage capacitor CST is connected to the control electrode 143 of the driving transistor 140, and the second electrode of the storage capacitor CST is configured to receive the third power supply voltage AVSS.
  • the third power supply voltage AVSS in the embodiment of the present disclosure is a low-level voltage.
  • the third power supply voltage AVSS may be the same as the fourth power supply voltage VCOM.
  • the third power supply voltage AVSS and the fourth power supply voltage VCOM may both be grounded.
  • the embodiments of the present disclosure include But it is not limited to this.
  • the first transistor 110 may be a P-type MOS transistor
  • the second transistor 120, the third transistor 130, and the driving transistor 140 may be N-type MOS transistors, for example, the first transistor The transistor 110, the second transistor 120, the third transistor 130, and the driving transistor 140 are formed in a base substrate.
  • the third stage of the first transistor 110 is configured to receive the second power supply voltage VDD.
  • the third stage of the first transistor 110 is connected to the second power supply voltage line VL2 to receive the second power supply voltage. VDD.
  • the second transistor 120, the third transistor 130, and the third electrode of the driving transistor 140 are configured as ground (GND).
  • GND ground
  • the third electrode of a transistor is opposite to the control electrode (gate) 113 of the transistor. The following embodiments are the same as this, and will not be repeated.
  • the first transistor 110 and the second transistor 120 may constitute a transmission gate switch having complementary characteristics.
  • the first scan signal SCAN1 provided to the first transistor 110 and the second scan signal SCAN2 provided to the second transistor 120 can be mutually inverted signals, so that the first transistor 110 can be guaranteed
  • One of the second transistors 120 and the second transistor 120 are always turned on at the same time, so that the data signal DATA can be transmitted to the storage capacitor CST without voltage loss, so that the reliability and stability of the pixel circuit can be improved.
  • FIG. 3 shows a schematic diagram of a layout on a base substrate corresponding to the display device 100 shown in FIG. 2.
  • the direction along the first pole 111 of the first transistor 110 to the second pole 112 of the first transistor 110 is referred to as the first direction D1.
  • the direction from the first pole 121 to the second pole 122 of the second transistor 120 is called the second direction D2
  • the direction along the first pole 131 of the third transistor 130 to the second pole 132 of the third transistor 130 is called the first
  • the three directions D3 and the direction along the first pole 141 of the driving transistor 140 to the second pole 142 of the driving transistor 140 is referred to as the fourth direction D4.
  • the fourth direction D4 is the lateral direction from left to right in FIG. 3.
  • the driving transistor 140 since the size of the driving transistor 140 is generally larger than that of other switching transistors (for example, the first transistor 110, the second transistor 120, and the third transistor 130), when the position of the transistor is laid out, the driving transistor can be
  • the transistors 140 are arranged along the fourth direction D4, and at least one of the first direction D1, the second direction D2, and the third direction D3 is intersected with the fourth direction D4. This makes the layout of the four transistors more compact, thereby reducing The layout area occupied by the display device 100 is small, so that the display device 100 can more easily achieve high PPI.
  • the first direction D1 and the second direction D2 can be made to intersect the fourth direction D4; for another example, the first direction D1, the second direction D2, and the third direction D3 can all be made to intersect the fourth direction D4.
  • the fourth direction D4 is a lateral direction
  • the first direction D1, the second direction D2, and the third direction D3 are all longitudinal directions perpendicular to the lateral direction in FIG. 3.
  • the first direction D1 and the second direction D2 are both perpendicular to the fourth direction D4; for another example, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4. vertical.
  • this method can make the layout of the display device 100 more compact, and thus can further reduce the footprint of the display device 100.
  • the layout area can make the display device 100 easier to achieve high PPI.
  • the first transistor 110 includes a first active region 114 extending along the first direction D1, and the first active region 114 includes a first electrode 111 of the first transistor 110 and a first electrode 111 of the first transistor 110.
  • the second transistor 120 includes a second active region 124 extending along the second direction D2.
  • the second active region 124 includes a first electrode 121 of the second transistor 120, a second electrode 122 of the second transistor 120, and a second transistor A channel region formed between the first pole 121 of the 120 and the second pole 122 of the second transistor 120.
  • the third transistor 130 includes a third active region 134 extending along the third direction D3.
  • the third active region 134 includes a first electrode 131 of the third transistor 130, a second electrode 132 of the third transistor 130, and a third body. A channel region formed between the first electrode 131 of the tube 130 and the second electrode 132 of the third transistor 130.
  • the driving transistor 140 includes a fourth active region 144 extending along the fourth direction D4.
  • the fourth active region 144 includes a first electrode 141 of the fourth transistor 140, a second electrode 142 of the fourth transistor 140, and a fourth body tube. A channel region formed between the first electrode 141 of the 140 and the second electrode 142 of the fourth transistor 140.
  • the base substrate in the display device 100 provided by the embodiment of the present disclosure is a silicon-based base substrate, and the first active region 114, the second active region 124, the third active region 134, and the fourth active region are described above.
  • the regions 144 are all doped regions in the silicon-based substrate, and these doped regions are obtained, for example, by ion implantation or ion diffusion.
  • P-type doping can be achieved by doping with boron (B), and N
  • the type doping can be achieved by doping phosphorus (P) or arsenic (As), which is not limited in the embodiments of the present disclosure.
  • the doping types of the first active region 114 and the second active region 124 are opposite.
  • the doping type of the first active region 114 is P-type
  • the doping type of the second active region 124 is N-type.
  • the two end portions of the first active region 114 and the two end portions of the second active region 124 are aligned with each other in the fourth direction D4, and for example, two ends of the first active region 114
  • the end portion and the second active region 124 are arranged adjacent to each other. In this way, the layout design of the display device 100 can be simplified.
  • the line connecting one edge of the first active region 114 along the first direction D1 and one edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4; the first active region 114 is along the first direction D1
  • the line connecting the other edge of the second active region 124 with the other edge of the second active region 124 in the second direction D2 is parallel to the fourth direction D4.
  • the driving current for the light-emitting element LE in the display device 100 is 1 to 2 orders of magnitude smaller.
  • the current characteristics of the driving transistor 140 in a saturated state are:
  • I D is the driving current provided by the driving transistor 140
  • W/L is the aspect ratio of the driving transistor 140
  • K is a constant value
  • V GS4 is the voltage difference between the gate and source of the driving transistor 140
  • V th is the threshold voltage of the driving transistor 140.
  • the L value of the driving transistor 140 must be increased during the size design, which is not conducive to reducing the layout area of the display device 100 using the driving transistor 140.
  • the pixel circuit 100 provided by some embodiments of the present disclosure is performed by comparing the relative relationship among the doping concentrations of the first active region 114, the second active region 124, the third active region 134, and the fourth active region 144. Adjustments can improve or avoid the above-mentioned problems.
  • the doping concentration of the fourth active region 144 is less than the doping concentration of the third active region 134.
  • the doping concentration of the third active region 134 is about 10 17 cm -3
  • the doping concentration of the fourth active region 144 is about 10 13 cm -3
  • the doping concentration of the fourth active region 144 is higher than that of the fourth active region 144.
  • the doping concentration of the three active regions 134 is 4 orders of magnitude smaller.
  • the embodiment of the present disclosure reduces the doping concentration of the fourth active region 144, and can make the output of the driving transistor 140 smaller without changing the size of the driving transistor 140 (for example, the aspect ratio W/L remains unchanged).
  • the output driving current changes more smoothly, so that the pixel circuit employing the driving transistor 140 to drive the light-emitting element LE (for example, OLED) to emit light can achieve better uniformity of the gray scale value.
  • the doping concentration of at least one of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region 134.
  • the doping concentration of the first active region 114 and the second active region 124 are both greater than the doping concentration of the third active region.
  • the doping concentration of the first active region 114 and the second active region 124 is about 10 20 cm -3 .
  • the doping concentration of the first active region 114 and the second active region 124 The doping concentration of the third active region 134 is 3 orders of magnitude greater.
  • the first transistor 110 and the second transistor 120 are used as switching transistors in the pixel circuit, so they need to have good switching characteristics.
  • the doping concentration of the first active region 114 or/and the second active region 124 is larger, a larger driving current can be obtained and the driving current changes more rapidly, so that the first transistor 110 or/and The second transistor 120 has better switching characteristics.
  • the first transistor 110 is a first semiconductor type MOS transistor
  • the second transistor, the third transistor, and the driving transistor are all second semiconductor type MOS transistors, and the first semiconductor type and the second semiconductor type in contrast.
  • the first semiconductor type is P type
  • the second semiconductor type is N type.
  • the embodiments of the present disclosure include but are not limited to this.
  • the display device 100 provided by some embodiments of the present disclosure further includes a first scan signal line SL1 for transmitting the first scan signal SCAN1 and a second scan signal line SL2 for transmitting the second scan signal SCAN2 ,
  • the first scan signal line SL1 and the second scan signal line SL2 are arranged in parallel.
  • the first scan signal line SL1 is connected to the control electrode 113 of the first transistor 110 to provide the first scan signal SCAN1
  • the second scan signal line SL2 is connected to the control electrode 123 of the second transistor 120 to provide the second scan signal SCAN2.
  • the extension directions of the first scan signal line SL1 and the second scan signal line SL2 are both parallel to the fourth direction D4.
  • the orthographic projection of the first scan signal line SL1 on the base substrate is parallel to the orthographic projection of the second scan signal line SL2 on the base substrate, for example, both are parallel to the fourth direction D4.
  • the area where the orthographic projection of the pixel circuit on the base substrate is located is the pixel area, and the first scan signal line SL1 and the second scan signal line SL2 are located in parallel on one side of the pixel area.
  • the display device 100 provided by some embodiments of the present disclosure further includes a data line DL for transmitting a data signal DATA, the orthographic projection of the second scan signal line SL2 on the base substrate and the data line DL on the substrate
  • the orthographic projections of the substrates overlap at least partially.
  • the second scan signal line SL2 and the data line DL overlap in a direction perpendicular to the base substrate.
  • the plane where FIG. 3 is located can be regarded as the plane where the base substrate is located, and it is perpendicular to the base substrate, that is, perpendicular to the plane where FIG. 3 is located.
  • the second scan signal line SL2 and the data line DT overlap in the direction perpendicular to the base substrate, so that the data line DL does not occupy additional layout area, thereby further reducing the display device 100
  • the occupied layout area is more conducive to achieving high PPI.
  • the display device 100 provided by some embodiments of the present disclosure further includes a first power supply voltage line VL1 for transmitting a first power supply voltage ELVDD and a light emitting control line EL for transmitting a light emitting control signal EN.
  • the first power supply voltage line VL1 and the light emission control line EL partially extend in parallel to the fourth direction D4, and the first scan signal line SL1, the second scan signal line SL2, the first power supply voltage line VL1 and the light emission control line EL are in parallel with each other.
  • the orthographic projections of the base substrate are sequentially arranged along the direction perpendicular to the fourth direction D4.
  • the orthographic projection of the first power voltage line VL1 on the base substrate is located on the second scan signal line SL2 on the base substrate.
  • the first power supply voltage ELVDD transmitted by the first power supply voltage line VL1 is a DC signal
  • the light-emitting control signal EN transmitted by the light-emitting control line EL is a jump signal, so the above arrangement can effectively shield the mutual interference between the second scan signal SCAN2 and the light-emitting control signal EN.
  • the display device 100 provided by some embodiments of the present disclosure further includes a second power supply voltage line VL2 for transmitting a second power supply voltage VDD, a third electrode of the first transistor 110 and a second power supply voltage line VL2 It is electrically connected to receive the second power supply voltage VDD.
  • the second power supply voltage VDD in the embodiment of the present disclosure is a high-level voltage, for example, the second power supply voltage is 5V.
  • the first transistor 110 is a P-type MOS transistor, and its channel region is P-type doped.
  • the third electrode opposite to the control electrode (gate) 113 of the first transistor 110 receives the second power supply voltage VDD.
  • the second transistor 120, the third transistor 130, and the driving transistor 140 are all N-type MOS transistors, and the channel region of the second transistor 120, the third transistor 130, and the third electrode of the driving transistor 140 are all N-type doped. Configure as ground (GND).
  • the orthographic projection of the second power supply voltage line VL2 on the base substrate is located between the orthographic projection of the first power supply voltage line VL1 on the base substrate and the light emission control line EL on the orthographic projection of the base substrate, and the second power supply voltage line Part of the extension direction of VL2 is parallel to the fourth direction D4.
  • the first transistor 110 and the second transistor 120 are both disposed between the second scan signal line SL2 and the light emission control line EL, and the first transistor 110 and the first power supply voltage line VL1 and the second power supply The voltage line VL2 intersects, and the second transistor 120 intersects the first power supply voltage line VL1 and the second power supply voltage line VL2.
  • the orthographic projection of the first active region 114 of the first transistor 110 on the base substrate and the orthographic projection of the second active region 124 of the second transistor 120 on the base substrate are both located on the second scan signal line SL2. Between the orthographic projection on the base substrate and the orthographic projection of the emission control line EL on the base substrate.
  • the orthographic projection of the first active region 114 of the first transistor 110 on the base substrate intersects the orthographic projection of the first power supply voltage line VL1 on the base substrate, and the first active region 114 of the first transistor 110 is on the base substrate.
  • the orthographic projection on the base substrate intersects the orthographic projection of the second power supply voltage line VL2 on the base substrate.
  • the orthographic projection of the second active region 124 of the second transistor 120 on the base substrate intersects the orthographic projection of the first power supply voltage line VL1 on the base substrate, and the second active region 124 of the second transistor 120 is on the base substrate.
  • the orthographic projection on the base substrate intersects the orthographic projection of the second power supply voltage line VL2 on the base substrate.
  • the display device 100 provided by some embodiments of the present disclosure further includes a first adapter electrode AE1 disposed on the first side of the light-emitting control line EL, and extends from the first side of the light-emitting control line EL to the light-emitting The second transfer electrode AE2 on the second side of the control line EL.
  • a first adapter electrode AE1 disposed on the first side of the light-emitting control line EL, and extends from the first side of the light-emitting control line EL to the light-emitting The second transfer electrode AE2 on the second side of the control line EL.
  • the orthographic projection of the second transfer electrode AE2 on the base substrate crosses the orthographic projection of the emission control line EL on the base substrate.
  • the two ends of the first transfer electrode AE1 are respectively electrically connected to the first pole 111 of the first transistor 110 and the first pole 121 of the second transistor 120, and the first transfer electrode AE1 and the second transfer electrode AE2 are electrically connected , And the second transfer electrode AE2 is electrically connected to the control electrode 143 of the driving transistor 140.
  • the extension direction of the second transfer electrode AE2 is perpendicular to the extension direction of the first transfer electrode AE1, and is perpendicular to the fourth direction D4.
  • the level of the second transfer electrode AE2 may fluctuate greatly during the operation of the pixel circuit, and this fluctuation may cause crosstalk to the first power supply voltage line VL1. Produce noise.
  • the first power supply voltage line VL1 and the second transfer electrode AE2 are spaced apart by the second power supply voltage line VL2, so that the level on the second transfer electrode AE2 can be reduced
  • the crosstalk caused by the fluctuation on the first power supply voltage line VL1 isolates noise.
  • the first active region 114 of the first transistor 110 is extended and the second active region 124 of the second transistor 120 is extended, thereby leaving a space for the second power supply voltage line VL2. Wiring channel.
  • the layout size of the pixel circuit (rectangular shape) provided by the embodiment of the present disclosure is approximately 4.5um ⁇ 2.9um.
  • 4A-4E respectively show plan views of the layout of each layer of the display device 100 shown in FIG. 3.
  • FIG. 4A shows the first active region 114 of the first transistor 110, the second active region 124 of the second transistor 120, the third active region 134 of the third transistor 130, and the fourth active region of the driving transistor 140 144.
  • the layer shown in FIG. 4A may be referred to as an effective display (AA) layer.
  • 4B shows the control electrode 113 of the first transistor 110, the control electrode 123 of the second transistor 120, the control electrode 133 of the third transistor 130, and the control electrode 143 of the driving transistor 140.
  • the layer shown in 4B may be referred to as a first conductive layer, and the first conductive layer will be further described below.
  • the material of the first conductive layer may be polysilicon.
  • FIG. 4C shows the first power supply voltage line VL1, the second power supply voltage line VL2, the light emission control line EL, the data line DL, the ground line GND, the first transfer electrode AE1, and the like.
  • the layer shown in FIG. 4C may be referred to as the first metal layer (metal1).
  • FIG. 4D shows the second transfer electrode AE2, the electrode connecting the first scan signal line SL1 and the first transistor 110, and the electrode connecting the second scan signal line SL2 and the second transistor 120.
  • the layer shown in FIG. 4D may be referred to as a second metal layer (metal2).
  • FIG. 4E shows the first scan signal line SL1 and the second scan signal line SL2, and the layer shown in FIG. 4E may be referred to as a third metal layer (metal3).
  • the area 800 shown in FIG. 5 is the area where the storage capacitor CST is provided. It should be noted that, for clarity of illustration, FIG. 5 does not show the corresponding signs of all the structures, and the omitted parts can refer to the corresponding signs in FIG. 3.
  • FIG. 6 is a layout diagram of the storage capacitor CST
  • FIGS. 7A-7D are plan views corresponding to the layout of each layer in FIG. 6,
  • FIG. 7E is a schematic cross-sectional view of the storage capacitor CST.
  • Figure 6 shows a four-layer structure, namely the third metal layer metal3, the fourth metal layer metal4, the auxiliary metal layer metal4', and the fifth metal layer metal5; in addition, the first via V1 and the second via are shown.
  • V2 the first via V1 and the second via V2 will be described below in conjunction with a schematic cross-sectional view, which will not be repeated here.
  • FIG. 7A shows the third metal layer metal3.
  • the third metal layer is the same layer as the layer shown in FIG. 4E.
  • the third metal layer metal3 includes two parts, an electrode 811 serving as the first electrode of the first capacitor C1 and an electrode 812 serving as the second electrode of the first capacitor C1.
  • the electrode 811 is configured to receive the third power supply voltage AVSS; the electrode 812 is electrically connected to the electrode 840 in the fifth metal layer metal5 through the second via V2, so as to be electrically connected to the control electrode 143 of the driving transistor 140.
  • the electrode 811 includes a plurality of strip electrodes
  • the electrode 812 includes a plurality of strip electrodes.
  • the plurality of strip electrodes of the electrode 811 and the plurality of strip electrodes of the electrode 812 are alternately arranged with each other, and the electrode 811 and the electrode 812 and between The space part forms a first capacitor C1.
  • the first capacitor C1 is a part of the storage capacitor CST.
  • the first capacitor C1 and the second capacitor C2 hereinafter are connected in parallel to form the storage capacitor CST.
  • FIG. 7B shows an electrode 820 located on the fourth metal layer metal4.
  • the electrode 820 is a planar electrode, and the electrode 820 serves as the first electrode of the second capacitor C2.
  • FIG. 7C shows an electrode 830 located on the auxiliary metal layer metal4'.
  • the electrode 830 is a planar electrode, and the electrode 830 serves as the second electrode of the second capacitor C2.
  • FIG. 7D shows the electrode 840 located on the fifth metal layer metal5, and the first via V1 and the second via V2.
  • FIG. 7E shows a schematic cross-sectional view of a part of the structure of the storage capacitor CST.
  • the electrode 840 on the fifth metal layer metal5 is electrically connected to the electrode 830 on the auxiliary metal layer metal4' through the first via V1;
  • the electrode 840 located on the fifth metal layer metal5 is electrically connected to the electrode 812 located on the third metal layer metal3 through the second via V2.
  • the second via hole V2 penetrates the fourth metal layer metal4, which is not shown in FIG. 7E.
  • the electrode 820 located on the fourth metal layer metal4 and the electrode 830 located on the auxiliary metal layer metal4' and the space between them form a second capacitor C2; for example, the first capacitor C1 described above and this
  • the second capacitor C2 is connected in parallel to form a storage capacitor CST.
  • an auxiliary metal layer metal4' is provided between the fourth metal layer metal4 and the fifth metal layer metal5, so that the fourth metal layer metal4 and the auxiliary metal layer metal4'
  • the distance therebetween is, for example, about 1/10 of the distance between the fourth metal layer metal4 and the fifth metal layer metal5, so that the capacitance value per unit area of the second capacitor C2 can be effectively increased.
  • an embodiment of the present disclosure further provides a display device 100, which includes a base substrate and at least one pixel circuit formed on the base substrate.
  • the pixel circuit includes a driving transistor 140, a first transistor 110, a second transistor 120, and a third crystal 130.
  • the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the voltage flowing through the first electrode 141 and the driving transistor 140 of the driving transistor 140 according to the voltage of the control electrode 143 of the driving transistor 140.
  • the driving current of the second pole 142 for driving the light-emitting element LE to emit light.
  • the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.
  • the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.
  • the third transistor 130 is connected to the first electrode 141 of the driving transistor 140 and is configured to apply the first power supply voltage ELVDD to the first electrode 141 of the driving transistor 140 in response to the light emission control signal EN.
  • the display device 100 further includes a first scan signal line SL1 for transmitting the first scan signal SCAN1 and a second scan signal line SL2 for transmitting the second scan signal SCAN2, and a first power supply for transmitting the first power supply voltage ELVDD
  • the voltage line VL1 and the light emission control line EL for transmitting the light emission control signal EN; the first scan signal line SL1, the second scan signal line SL2, the first power supply voltage line VL1 and the light emission control line EL along the orthographic projection of the base substrate It is arranged in sequence in the direction perpendicular to the fourth direction D4.
  • the direction along the first electrode 111 of the first transistor 110 to the second electrode 112 of the first transistor 110 is the first direction D1
  • the direction along the first electrode 121 of the second transistor 120 to the second electrode 122 of the second transistor 120 is the third direction D3
  • the direction of the second pole 142 is the fourth direction D4, and the first direction D1, the second direction D2, and the third direction D3 all intersect the fourth direction D4.
  • the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4.
  • At least one embodiment of the present disclosure also provides a manufacturing method of the display device 100, the manufacturing method including: forming a pixel circuit on a base substrate.
  • the pixel circuit includes a driving transistor 140, a first transistor 110, and a second transistor 120.
  • the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the voltage flowing through the first electrode 141 and the driving transistor 140 of the driving transistor 140 according to the voltage of the control electrode 143 of the driving transistor 140.
  • the driving current of the second pole 142 for driving the light-emitting element LE to emit light.
  • the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.
  • the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.
  • the direction along the first electrode 111 of the first transistor 110 to the second electrode 112 of the first transistor 110 is the first direction D1
  • the direction along the first electrode 121 of the second transistor 120 to the second electrode 122 of the second transistor 120 Is the second direction D2
  • the direction along the first pole 141 of the driving transistor 140 to the second pole 142 of the driving transistor 140 is the fourth direction D4
  • the pixel circuits in the display devices need to output a higher driving current to the anode of the OLED.
  • the anode voltage of the OLED needs a higher voltage V anode
  • V GS4 V GS4 is the voltage difference between the gate of the driving transistor 140 and the second electrode
  • V GS4 is the voltage difference between the gate of the driving transistor 140 and the second electrode
  • V GS4 is the voltage difference between the gate of the driving transistor 140 and the second electrode
  • the first electrode 121 for example, the drain
  • the first transistor 110 and the second transistor 120 in the pixel circuit will withstand high voltage, and a breakdown phenomenon may occur, which may affect the reliability and stability of the pixel circuit.
  • At least one embodiment of the present disclosure also provides a structural design of a transistor that can reduce or avoid the risk of high voltage breakdown, so that the pixel circuit using the transistor is not easily broken down by high voltage and the pixel circuit can be realized
  • the high-brightness display driver also provides a structural design of a transistor that can reduce or avoid the risk of high voltage breakdown, so that the pixel circuit using the transistor is not easily broken down by high voltage and the pixel circuit can be realized The high-brightness display driver.
  • At least one embodiment of the present disclosure provides a display device 100 including a base substrate and a pixel circuit formed on the base substrate.
  • the pixel circuit includes a driving transistor 140, a first transistor 110, and a second transistor 120;
  • the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to depend on the voltage of the control electrode 143 of the driving transistor 140 , Controlling the driving current flowing through the first electrode 141 of the driving transistor 140 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light;
  • the first electrode 111 of the first transistor 110 is connected to the control electrode of the driving transistor 140 143, and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1;
  • the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to respond to the second scan
  • the signal SCAN2 writes the data signal DATA into the control electrode 143
  • the base substrate includes a doped semiconductor body 330 and a first conductive layer 310 and a second conductive layer 320 on the semiconductor body 330.
  • the first transistor 110 includes a gate GE1 in the first conductive layer 310, a second electrode SE1 and a first electrode DE1 in the second conductive layer 320, and a first electrode DE1 in contact with the first electrode DE1 of the first transistor 110.
  • the doped region DR1, the second doped region SR1 in contact with the second electrode SE1 of the first transistor 110, the first doped region DR1 of the first transistor 110 and the second doped region SR1 of the first transistor 110 are spaced apart from each other ,
  • the doping type is the same and they are all located in the semiconductor body 330.
  • the channel region of the first transistor 110 is between the first doped region DR1 and the second doped region SR1.
  • the gate GE1 of the first transistor 110 is the control electrode 113 of the first transistor 110 described above, and the following embodiments are the same as this, and will not be repeated.
  • the first transistor 110 further includes a drift doped region DF1 in contact with the first doped region DR1.
  • the drift doped region DF1 of the first transistor 110 and the second doped region SR1 of the first transistor 110 are mutually connected. They are spaced apart, have the same doping type, and are located in the semiconductor body 330.
  • the first transistor 110 is a P-type MOS transistor, and the doping types of the first doped region DR1, the second doped region SR1, and the drift doped region DF1 of the first transistor 110 are all P-type doped, and the semiconductor body 330 is bulk silicon or silicon-on-insulating layer whose doping type is P-type.
  • the orthographic projection of the gate GE1 of the first transistor 110 on the base substrate partially overlaps the orthographic projection of the drift doped region DF1 of the first transistor 110 on the base substrate, and the first doping of the first transistor 110
  • the orthographic projection of the region DR1 on the base substrate is in the orthographic projection of the drift doped region DF1 of the first transistor 110 on the base substrate; the doping concentration of the drift doped region DF1 of the first transistor 110 is lower than that of the first transistor The doping concentration of the first doping region DR1 of 110.
  • the drift doping region DF1 is provided in the first transistor 110, and the doping concentration of the drift doping region DF1 of the first transistor 110 is lower than that of the first transistor 110.
  • the doping concentration of the first doped region DR1 can increase the breakdown voltage between the first electrode DE1 to the second electrode SE1 of the first transistor 110, so that the first transistor 110 can reduce or avoid high voltage Risk of breakdown.
  • the first transistor 110 is a P-type MOS transistor.
  • the drift doped region DF1 of the first transistor 110 includes a first portion DF11 and a second portion DF12; the orthographic projection of the second portion DF12 on the base substrate is the same as that of the first transistor 110 The orthographic projection of the first doped region DR1 on the base substrate overlaps.
  • the second portion DF12 of the first doped region DF1 of the first transistor 110 constitutes a part of the channel region and is connected to the channel region.
  • the rest of the district is different.
  • the first doped region DR1 of the first transistor 110 is in the drift doped region DF1 of the first transistor 110.
  • the doping depth of the first doped region DR1 of the first transistor 110 in the semiconductor body 330 may be less than, equal to or greater than the doping depth of the drift doped region DF1 of the first transistor 110.
  • the first doped region DR1, the second doped region SR1, and the drift doped region DF1 of the first transistor 110 are located in the semiconductor body 330 In the first well WL1, for example, the doping type of the first well WL1 is N-type doping.
  • the orthographic projection of the gate GE1 of the first transistor 110 on the base substrate is located in the orthographic projection of the first well WL1 on the base substrate, and the first well WL1 is located in the first doped region DR1 and the second doped region DR1 of the first transistor 110.
  • the portion between the second doped regions SR1 of a transistor 110 constitutes the channel region of the first transistor 110.
  • FIG. 3 shows the region where the first well WL1 is located.
  • the first transistor 110 further includes an auxiliary doping region BR; for example, the doping type of the auxiliary doping region BR of the first transistor 110 is N-type doping, and the auxiliary doping of the first transistor 110 is The region BR is in contact with the second doped region SR1 of the first transistor 110, the auxiliary doped region BR of the first transistor 110 is electrically connected to the second electrode SE1 of the first transistor 110, and the auxiliary doped region BR of the first transistor 110
  • the orthographic projection on the base substrate is in the orthographic projection of the first well WL1 on the base substrate.
  • the auxiliary doped region BR can serve as an isolation function to prevent leakage.
  • the base substrate in the display device 100 provided by some embodiments of the present disclosure further includes a first insulating layer IS1 located between the semiconductor body 330 and the first conductive layer 310, and the first insulating layer IS1 may The gate GE1 of the first transistor 110 is insulated from the semiconductor body 330.
  • the first insulating layer IS1 may be a gate insulating layer, such as a silicon oxide layer, and may be formed by a vapor deposition process, or obtained by directly oxidizing a silicon-based substrate through a thermal oxidation process.
  • the first insulating layer IS1 includes a first portion IS11 close to the first doped region DR1 of the first transistor 110 and a second portion IS12 far away from the first doped region DR1 of the first transistor 110.
  • the thickness of the first portion IS11 of the first insulating layer IS1 is greater than the thickness of the second portion IS12 of the first insulating layer IS1, and the thickness is the thickness in a direction perpendicular to the base substrate.
  • the thickness of the first portion IS11 of the first insulating layer IS1 is 7 to 8 nanometers
  • the thickness of the second portion IS12 of the first insulating layer IS1 is 2 to 3 nanometers.
  • the thickness of the first portion IS11 of the first insulating layer IS1 is thickened, for example, thickened to more than twice the thickness of the second portion IS12, so that the gate GE1 of the first transistor 110 and the first portion IS11 are thickened. The risk of high voltage breakdown between the first electrode DE1 of the transistor 110 can be reduced or avoided.
  • the base substrate further includes a planarization insulating layer PL, the planarization insulating layer PL covers the gate GE1 of the first transistor 110, and the light-emitting element LE is located on the planarization insulating layer PL.
  • the planarization insulating layer PL can cover the above-mentioned pixel circuit, so that the surface of the planarization insulating layer PL is flatter, which is more advantageous for forming the light emitting element LE on the planarization insulating layer PL.
  • the planarization insulating layer PL can be silicon oxide, silicon oxynitride, silicon nitride, etc., and can be obtained by a process such as vapor deposition.
  • the first transistor 110 adopts a structural design that can reduce or avoid the risk of breakdown by high voltage
  • the second transistor 120 adopts a common MOS transistor structure design.
  • the second transistor 120 includes a gate GE2 located in the first conductive layer 310, a first electrode DE2 and a second electrode SE2 located in the second conductive layer 320, and a first electrode GE2 located in the second conductive layer 320.
  • the impurity regions SR2 are spaced apart from each other, have the same doping type, and are all located in the semiconductor body 330.
  • the gate GE2 of the second transistor 120 here is the control electrode 123 of the second transistor 120 described above, and the following embodiments are the same as this, and will not be repeated here.
  • the second transistor 120 is an N-type MOS transistor, and the doping type of the first doped region DR2 and the second doped region SR2 of the second transistor 120 are both N-type doping.
  • the second transistor 120 further includes an auxiliary doped region BR2.
  • the auxiliary doped region BR2 of the second transistor 120 is in contact with the second doped region SR2 of the second transistor 120.
  • the doped region BR2 is electrically connected to the second electrode SE2 of the second transistor 120, and the doping type of the auxiliary doped region BR2 of the second transistor 120 is opposite to the doping type of the second doped region SR2 of the second transistor 120, for example
  • the doping type of the auxiliary doping region BR2 of the second transistor 120 is P-type doping.
  • the auxiliary doped region BR2 can play a role of isolation and prevent leakage.
  • the first transistor 110 may also be an N-type MOS transistor.
  • the doping type of the first doped region DR1 in the first transistor 110 is N-type.
  • the main body 330 is bulk silicon or silicon-on-insulating layer whose doping type is P-type.
  • the first transistor 110 may further include an auxiliary doped region.
  • the doping type of the auxiliary doped region of the first transistor 110 is P-type.
  • the auxiliary doped region of a transistor 110 is in contact with the second doped region SR1 of the first transistor 110, and the auxiliary doped region is electrically connected to the second electrode SE1 of the first transistor 110.
  • the second transistor 120 adopts a structural design that can reduce or avoid the risk of high voltage breakdown
  • the first transistor 110 adopts a common MOS transistor structure design.
  • the second transistor 120 includes a gate GE2 located in the first conductive layer 310, a first electrode DE2 and a second electrode SE2 located in the second conductive layer 320, and a The first doped region DR2 in contact with the electrode DE2, the second doped region SR2 in contact with the second electrode SE2 of the second transistor 120, the first doped region DR2 of the second transistor 120 and the second doped region DR2 of the second transistor 120
  • the impurity regions SR2 are spaced apart from each other, have the same doping type, and are all located in the semiconductor body 330.
  • the second transistor 120 further includes a drift doped region DF2 in contact with the first doped region DR2.
  • the drift doped region DF2 of the second transistor 120 and the second doped region SR2 of the second transistor 120 are spaced apart from each other.
  • the doping types are the same and they are all located in the semiconductor body 330.
  • the second transistor 120 is a P-type MOS transistor, and the doping types of the first doped region DR2, the second doped region SR2, and the drift doped region DF2 of the second transistor 120 are all N-type doped, and the semiconductor body 330 is bulk silicon or silicon-on-insulating layer whose doping type is P-type.
  • the orthographic projection of the gate GE2 of the second transistor 120 on the base substrate partially overlaps the orthographic projection of the drift doped region DF2 of the second transistor 120 on the base substrate, and the first doping of the second transistor 120
  • the orthographic projection of the region DR2 on the base substrate is in the orthographic projection of the drift doped region DF2 of the second transistor 120 on the base substrate; the doping concentration of the drift doped region DF2 of the second transistor 120 is lower than that of the second transistor 120 doping concentration of the first doping region DR2.
  • the drift doped region DF2 is provided in the second transistor 120, and the doping concentration of the drift doped region DF2 of the second transistor 120 is lower than that of the second transistor 120.
  • the doping concentration of the first doped region DR2 can increase the breakdown voltage between the first electrode DE2 and the second electrode SE2 of the second transistor 120, so that the second transistor 120 can reduce or avoid high voltage Risk of breakdown. As shown in FIG.
  • the drift doped region DF2 of the second transistor 120 includes a first portion DF21 and a second portion DF22; the orthographic projection of the second portion DF22 on the base substrate is similar to the first doped region DR2 of the second transistor 120 The orthographic projections on the base substrate overlap.
  • the first doped region DR2 of the second transistor 120 is in the drift doped region DF2 of the second transistor 120.
  • the second transistor 120 further includes an auxiliary doping region BR2; for example, the doping type of the auxiliary doping region BR2 of the second transistor 120 is P-type doping, and the auxiliary doping of the second transistor 120
  • the region BR2 is in contact with the second doped region SR2 of the second transistor 120, and the auxiliary doped region BR2 of the second transistor 120 is electrically connected to the second electrode SE2 of the second transistor 120.
  • the auxiliary doped region BR2 can play a role of isolation and prevent leakage.
  • the base substrate in the display device 100 provided by some embodiments of the present disclosure further includes a second insulating layer IS2 located between the semiconductor body 330 and the first conductive layer 310, and the second insulating layer IS2 may The gate GE2 of the second transistor 120 is insulated from the semiconductor body 330.
  • the second insulating layer IS2 may be a gate insulating layer, such as a silicon oxide layer, and may be formed by a vapor deposition process, or obtained by directly oxidizing a silicon-based substrate through a thermal oxidation process.
  • the second insulating layer IS2 includes a first portion IS21 close to the first doped region DR2 of the second transistor 120 and a second portion IS22 far away from the first doped region DR2 of the second transistor 120.
  • the thickness of the first portion IS21 of the second insulating layer IS2 is greater than the thickness of the second portion IS22 of the second insulating layer IS2, and the thickness is the thickness in the direction perpendicular to the base substrate.
  • the thickness of the first portion IS21 of the second insulating layer IS2 is 7 to 8 nanometers
  • the thickness of the second portion IS22 of the second insulating layer IS2 is 2 to 3 nanometers.
  • the thickness of the first portion IS21 of the second insulating layer IS2 is thickened, for example, thickened to more than twice the thickness of the second portion IS22, so that the gate GE2 of the second transistor 120 and the second The risk of high voltage breakdown between the first electrode DE2 of the transistor 120 can be reduced or avoided.
  • the base substrate further includes a planarization insulating layer PL, the planarization insulating layer PL covers the gate GE2 of the second transistor 120, and the light-emitting element LE is located on the planarization insulating layer PL.
  • the planarization insulating layer PL can cover the above-mentioned pixel circuit, so that the surface of the planarization insulating layer PL is flatter, which is more conducive to forming a light emitting element on the planarization insulating layer PL.
  • the planarization insulating layer PL can be silicon oxide, silicon oxynitride, silicon nitride, etc., and can be obtained by a process such as vapor deposition.
  • the second transistor 120 adopts a structural design that can reduce or avoid the risk of breakdown by high voltage
  • the first transistor 110 adopts a common MOS transistor structure design.
  • the first transistor 110 includes a gate GE1 located in the first conductive layer 310, a first electrode DE1 and a second electrode SE1 located in the second conductive layer 320, and a first transistor 110 connected to the first transistor 110.
  • the first doped region DR1 in contact with the electrode DE1, the second doped region SR1 in contact with the second electrode SE1 of the first transistor 110, the first doped region DR1 of the first transistor 110 and the second doped region DR1 of the first transistor 110 The impurity regions SR1 are spaced apart from each other, have the same doping type, and are all located in the semiconductor body 330.
  • the first transistor 110 is a P-type MOS transistor, and the doping types of the first doped region DR1 and the second doped region SR1 of the first transistor 110 are both P-type doping.
  • the first doped region DR1 and the second doped region SR1 of the first transistor 110 are located in the second well WL2 in the semiconductor body 330
  • the doping type of the second well WL2 is N-type doping.
  • the orthographic projection of the gate GE1 of the first transistor 110 on the base substrate is located in the orthographic projection of the second well WL2 on the base substrate, and the second well WL2 is located in the first doped region DR1 and the second doped region DR1 of the first transistor 110.
  • the portion between the second doped regions SR1 of a transistor 110 constitutes the channel region of the first transistor 110.
  • the first transistor 110 further includes an auxiliary doping region BR; for example, the doping type of the auxiliary doping region BR of the first transistor 110 is N-type doping, and the auxiliary doping of the first transistor 110 is The region BR is in contact with the second doped region SR1 of the first transistor 110, the auxiliary doped region BR of the first transistor 110 is electrically connected to the second electrode SE1 of the first transistor 110, and the auxiliary doped region BR of the first transistor 110
  • the orthographic projection on the base substrate is in the orthographic projection of the second well WL2 on the base substrate.
  • the auxiliary doped region BR can serve as an isolation function to prevent leakage.
  • both the first transistor 110 and the second transistor 120 adopt a structural design that can reduce or avoid the risk of breakdown by high voltage.
  • the specific structure of the second transistor 120 reference may be made to the corresponding descriptions in the embodiments shown in FIG. 5 and FIG. 6, which will not be repeated here.
  • the base substrate is a P-type silicon base substrate
  • the first transistor 110 is a P-type MOS transistor
  • the second transistor 120, the third transistor 130, and the driving transistor 140 All are N-type MOS transistors.
  • At least one embodiment of the present disclosure also provides a manufacturing method of the display device 100, the manufacturing method including: forming a pixel circuit on a base substrate.
  • the pixel circuit includes a driving transistor 140, a first transistor 110, and a second transistor 120.
  • the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the first electrode 141 and the driving transistor 140 flowing through the driving transistor 140 according to the voltage of the control electrode 143 of the driving transistor 140 The driving current of the second pole 142 for driving the light-emitting element LE to emit light.
  • the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.
  • the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.
  • the above-mentioned base substrate further includes a doped semiconductor body 330; the above-mentioned preparation method further includes: forming a first conductive layer 310 and a second conductive layer 320 of the base substrate on the semiconductor body 330, and the first transistor 110 includes The gate GE1 in the conductive layer 310 and the first electrode DE1 and the second electrode SE1 in the second conductive layer 320.
  • the above manufacturing method further includes: forming a first doped region DR1 of the first transistor 110 in contact with the first electrode DE1 of the first transistor 110 and a first doped region DR1 in contact with the second electrode SE1 of the first transistor 110 in the semiconductor body 330.
  • the second doped region SR1 of the transistor 110, the first doped region DR1 of the first transistor 110 and the second doped region SR1 of the first transistor 110 are spaced apart from each other, have the same doping type, and are all located in the semiconductor body 330.
  • the above-mentioned preparation method further includes: forming the drift doped region DF1 of the first transistor 110 with the same doping type as the second doped region SR1 of the first transistor 110 in the semiconductor body 330; the drift doped region of the first transistor 110 DF1 is located in the semiconductor body 330 and is spaced apart from the second doped region SR1 of the first transistor 110.
  • the orthographic projection of the gate GE1 of the first transistor 110 on the base substrate is in the same position as the drift doped region DF1 of the first transistor 110.
  • the orthographic projections on the base substrate partially overlap, and the orthographic projection of the first doped region DR1 of the first transistor 110 on the base substrate is located in the orthographic projection of the drift doped region DF1 of the first transistor 110 on the base substrate ,
  • the doping concentration of the drift doped region DF1 of the first transistor 110 is lower than the doping concentration of the first doped region DR1 of the first transistor 110.
  • the above-mentioned preparation method further includes: forming a first insulating layer IS1 of the base substrate between the semiconductor body 330 and the first conductive layer 310.
  • the first insulating layer IS1 includes a first portion IS11 close to the first doped region DR1 of the first transistor 110 and a second portion IS12 away from the first doped region DR1 of the first transistor 110; a first portion IS11 of the first insulating layer IS1
  • the thickness of is greater than the thickness of the second portion IS12 of the first insulating layer IS1, and the thickness is the thickness along the direction perpendicular to the base substrate.
  • At least one embodiment of the present disclosure also provides a manufacturing method of the display device 100, the manufacturing method including: forming a pixel circuit on a base substrate.
  • the pixel circuit includes a driving transistor 140, a first transistor 110, and a second transistor 120.
  • the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the first electrode 141 and the driving transistor 140 flowing through the driving transistor 140 according to the voltage of the control electrode 143 of the driving transistor 140 The driving current of the second pole 142 for driving the light-emitting element LE to emit light.
  • the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.
  • the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA into the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.
  • the first transistor 110 includes a first active region 114
  • the second transistor 120 includes a second active region 124
  • the driving transistor 140 includes a fourth active region 144;
  • the two active regions 124 and the fourth active region 144 are doped so that the doping concentration of at least one of the first active region 114 and the second active region 124 is greater than the doping concentration of the fourth active region 144.
  • the above-mentioned pixel circuit further includes a third transistor 130 connected to the first electrode 141 of the driving transistor 140 and configured to apply the first power supply voltage ELVDD to the first electrode of the driving transistor 140 in response to the light emission control signal EN. 141.
  • the third transistor 130 includes a third active region 134; the above preparation method further includes: doping the third active region 134 so that the doping concentration of the fourth active region 144 is less than that of the third active region 134 Doping concentration.
  • the following takes the embodiment shown in FIG. 8 as an example to describe a method for manufacturing the display device 100 provided by the embodiment of the present disclosure.
  • a semiconductor body 330 is first provided, and then N-type doping is performed in the semiconductor body 330 to form a first well WL1; then, P-type doping is performed in the first well WL1 to form a first well WL1.
  • the doping concentration of the doped region DR1 is higher than that of the drift doped region DF1 of the first transistor 110; at the same time, P-type doping is performed in the first well WL1 to form the second doped region of the first transistor 110 SR1, and N-type doping is performed to form the auxiliary doped region BR of the first transistor 110.
  • a first insulating layer IS1 is formed on the semiconductor body 330, and the thickness of the first portion IS11 of the first insulating layer IS1 is greater than the thickness of the second portion IS12 of the first insulating layer IS1; then, on the first insulating layer IS1 A first conductive layer 310 is formed thereon, and the first conductive layer 310 includes the gate GE1 of the first transistor 110.
  • a planarization insulating layer PL is formed to cover the gate GE1 of the first transistor 110; then, a via is formed in the planarization insulating layer PL to expose the first doped region DR1 of the first transistor and the second transistor 110.
  • the second doped region SR1 and the auxiliary doped region BR of the first transistor 110 are formed to cover the gate GE1 of the first transistor 110; then, a via is formed in the planarization insulating layer PL to expose the first doped region DR1 of the first transistor and the second transistor 110.
  • the second conductive layer 320 includes the first electrode DE1 of the first transistor 110 electrically connected to the first doped region DR1 of the first transistor 110 through the via hole in the planarization insulating layer PL. , And the second electrode SE1 of the first transistor 110 electrically connected to the second impurity region SR1 of the first transistor 110 through the via hole in the planarization insulating layer PL.
  • the manufacturing method of the second transistor 120 is similar to the above, and will not be repeated here.
  • At least one embodiment of the present disclosure also provides a display device 100.
  • the display device 100 includes a display panel including a plurality of pixels arranged in an array in the display area 300.
  • the unit PU for example, at least one of the plurality of pixel units PU may adopt any pixel circuit in the display device 100 provided by the embodiment of the present disclosure.
  • the display device 100 further includes a driving circuit 200 prepared in a base substrate, and the driving circuit 200 is configured to provide a first pixel circuit in a plurality of pixel units PU in the display device 100.
  • the driving circuit 200 is provided in the peripheral area 400 surrounding the display area 300.
  • the display device 100 provided by the embodiment of the present disclosure may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

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Abstract

一种显示装置（100）及其制备方法。该显示装置（100）包括衬底基板（600）以及形成在衬底基板（600）上的至少一个像素电路。像素电路包括驱动晶体管（140）、第一晶体管（110）以及第二晶体管（120）；衬底基板（600）包括可掺杂的半导体主体（330）以及位于半导体主体（330）之上的第一导电层（310）以及第二导电层（320）；第一晶体管（110）包括与第一晶体管（110）的第一极（DE1）接触的第一掺杂区（DR1），与第一晶体管（110）的第二极（SE1）接触的第二掺杂区（SR1），第一晶体管（110）的第一掺杂区（DR1）与第一晶体管（110）的第二掺杂区（SR1）彼此间隔开、掺杂类型相同且都位于半导体主体（330）中；第一晶体管（110）还包括与第一掺杂区（DR1）接触的漂移掺杂区（DF1），第一晶体管（110）的漂移掺杂区（DF1）与第一晶体管（110）的第二掺杂区（SR1）彼此间隔开、掺杂类型相同且都位于半导体主体（330）中。该显示装置（100）可以降低或避免被高电压击穿的风险。

Description

显示装置及其制备方法 技术领域
本公开实施例涉及一种显示装置及其制备方法。
背景技术
微型有机发光二极管(Micro Organic Light-Emitting Diode，简称Micro-OLED)显示装置是一种以硅基板为衬底的新型OLED显示装置，又叫做硅基有机发光二极管(简称硅基OLED)显示装置。硅基OLED显示装置具有体积小、分辨率高等优点，其采用成熟的CMOS集成电路工艺制备，可以实现像素的有源寻址，并且可以在硅基衬底上制备包括TCON(时序控制)电路、OCP(操作控制)电路等多种功能电路，可以实现轻量化。
发明内容
本公开至少一实施例提供一种显示装置，包括衬底基板以及形成在所述衬底基板上的至少一个像素电路，所述像素电路包括驱动晶体管、第一晶体管以及第二晶体管；所述驱动晶体管包括控制极、第一极和第二极，且被配置为，根据所述驱动晶体管的控制极的电压，控制流经所述驱动晶体管的第一极和所述驱动晶体管的第二极的用于驱动发光元件发光的驱动电流；所述第一晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第一扫描信号将数据信号写入所述驱动晶体管的控制极；所述第二晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第二扫描信号将所述数据信号写入所述驱动晶体管的控制极；所述衬底基板包括可掺杂的半导体主体以及位于所述半导体主体之上的第一导电层以及第二导电层；所述第一晶体管包括与所述第一晶体管的第一极接触的第一掺杂区，与所述第一晶体管的第二极接触的第二掺杂区，所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；所述第一晶体管还包括与所述第一掺杂区接触的漂移掺杂区，所述第一晶体管的漂移掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；所述第一晶体管的栅极在所述衬底基板上的正 投影与所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第一晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影中；所述第一晶体管的漂移掺杂区的掺杂浓度低于所述第一晶体管的第一掺杂区的掺杂浓度。
例如，在本公开一实施例提供的显示装置中，所述衬底基板还包括位于所述半导体主体和所述第一导电层之间的第一绝缘层；所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第二掺杂区的第二部分。
例如，在本公开一实施例提供的显示装置中，所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
本公开至少一实施例提供一种显示装置，包括衬底基板以及形成在所述衬底基板上的至少一个像素电路，所述像素电路包括驱动晶体管、第一晶体管以及第二晶体管；所述驱动晶体管包括控制极、第一极和第二极，且被配置为，根据所述驱动晶体管的控制极的电压，控制流经所述驱动晶体管的第一极和所述驱动晶体管的第二极的用于驱动发光元件发光的驱动电流；所述第一晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第一扫描信号将数据信号写入所述驱动晶体管的控制极；所述第二晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第二扫描信号将所述数据信号写入所述驱动晶体管的控制极；其中，所述衬底基板包括可掺杂的半导体主体以及形成在所述半导体主体的表面之上的第一导电层以及第二导电层；所述第一晶体管包括与所述第一晶体管的第一极接触的第一掺杂区，与所述第一晶体管的第二极接触的第二掺杂区，所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；所述衬底基板还包括形成在所述半导体主体和所述第一导电层之间的第一绝缘层，所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第二掺杂区的第二部分；所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管还包括与所述第一晶体管的第一掺杂区接触的漂移掺杂区，所述第一晶体管的漂移掺 杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；所述第一晶体管的栅极在所述衬底基板上的正投影与所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第一晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影中；所述第一晶体管的漂移掺杂区的掺杂浓度低于所述第一晶体管的第一掺杂区的掺杂浓度。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管为P型MOS晶体管，所述第一晶体管的中的第一掺杂区的掺杂类型为P型；所述半导体主体为掺杂类型为P型的体硅或绝缘层上硅。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管的第一掺杂区、第二掺杂区以及漂移掺杂区位于所述半导体主体中的第一阱中，所述第一阱的掺杂类型为N型；所述第一晶体管的栅极在所述衬底基板上的正投影位于所述第一阱在所述衬底基板上的正投影中，且所述第一阱位于所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区之间的部分构成所述第一晶体管的沟道区。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管还包括辅助掺杂区，所述第一晶体管的辅助掺杂区的掺杂类型为N型，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二掺杂区接触，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二极电连接，且所述第一晶体管的辅助掺杂区在所述衬底基板上的正投影位于所述第一阱在所述衬底基板上的正投影中。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管为N型MOS晶体管，所述第一晶体管的中的第一掺杂区的掺杂类型为N型；所述半导体主体为掺杂类型为P型的体硅或绝缘层上硅。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管还包括辅助掺杂区，所述第一晶体管的辅助掺杂区的掺杂类型为P型，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二掺杂区接触，所述辅助掺杂区与所述第一晶体管的第二极电连接。
例如，在本公开一实施例提供的显示装置中，所述衬底基板还包括平坦化绝缘层，所述平坦化绝缘层覆盖所述第一晶体管的栅极，且所述发光元件位于所述平坦化绝缘层之上。
例如，在本公开一实施例提供的显示装置中，所述第二晶体管包括与所述第二晶体管的第一极接触的第一掺杂区，与所述第二晶体管的第二极接触的第二掺杂区，所述第二晶体管的第一掺杂区与所述第二晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中。
例如，在本公开一实施例提供的显示装置中，所述第二晶体管还包括辅助掺杂区，所述第二晶体管的辅助掺杂区与所述第二晶体管的第二掺杂区接触，所述第二晶体管的辅助掺杂区与所述第二晶体管的第二极电连接，所述第二晶体管的辅助掺杂区的掺杂类型与所述第二晶体管的第二掺杂区的掺杂类型相反。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管的第一掺杂区的掺杂类型与所述第二晶体管的第一掺杂区的掺杂类型相反。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管为P型MOS晶体管，所述第一晶体管的第一掺杂区的掺杂类型为P型，所述第二晶体管为N型MOS晶体管，所述第二晶体管的第一掺杂区的掺杂类型为N型；所述半导体主体为掺杂类型为P型的体硅或绝缘层上硅；所述第二晶体管包括与所述第二晶体管的第一极接触的第一掺杂区，与所述第二晶体管的第二极接触的第二掺杂区，所述第二晶体管的第一掺杂区与所述第二晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中。
例如，在本公开一实施例提供的显示装置中，所述第二晶体管还包括与所述第二晶体管的第一掺杂区接触的漂移掺杂区，所述第二晶体管的漂移掺杂区与所述第二晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；所述第二晶体管的栅极在所述衬底基板上的正投影与所述第二晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第二晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第二晶体管的漂移掺杂区在所述衬底基板上的正投影中；所述第二晶体管的漂移掺杂区的掺杂浓度低于所述第二晶体管的第一掺杂区的掺杂浓度。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管的第一掺杂区、第二掺杂区以及漂移掺杂区位于所述半导体主体中的第一阱中，所述第一阱的掺杂类型为N型，所述第一晶体管的栅极在所述衬底基板上的正投影位于所述第一阱在所述衬底基板上的正投影中，且所述第一阱位于所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区之间的部分构成所 述第一晶体管的沟道区。
例如，在本公开一实施例提供的显示装置中，所述第一晶体管还包括辅助掺杂区，所述第一晶体管的辅助掺杂区的掺杂类型为N型，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二掺杂区接触，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二极电连接，且所述第一晶体管的辅助掺杂区在所述衬底基板上的正投影位于所述第一阱在所述衬底基板上的正投影中；所述第二晶体管还包括辅助掺杂区，所述第二晶体管的辅助掺杂区的掺杂类型为P型，所述第二晶体管的辅助掺杂区与所述第二晶体管的第二掺杂区接触，所述第二晶体管的辅助掺杂区与所述第二晶体管的第二极电连接。
例如，在本公开一实施例提供的显示装置中，所述衬底基板还包括形成在所述半导体主体和所述第一导电层之间的第一绝缘层与第二绝缘层；所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第一掺杂区的第二部分；所述第二绝缘层包括靠近所述第二晶体管的第一掺杂区的第一部分以及远离所述第二晶体管的第一掺杂区的第二部分。
例如，在本公开一实施例提供的显示装置中，所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，且所述第二绝缘层的第一部分的厚度大于所述第二绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
例如，在本公开一实施例提供的显示装置中，所述像素电路还包括第三晶体管，所述第三晶体管连接到所述驱动晶体管的第一极，且被配置为响应于发光控制信号将第一电源电压施加到所述驱动晶体管的第一极。
例如，在本公开一实施例提供的显示装置中，所述衬底基板为P型硅衬底基板，所述第一晶体管为P型MOS晶体管，所述第二晶体管、所述第三晶体管以及所述驱动晶体管均为N型MOS晶体管。
例如，本公开一实施例提供的显示装置还包括位于所述衬底基板中的驱动电路，所述驱动电路被配置为向所述显示装置中的至少一个像素电路提供所述第一扫描信号、所述第二扫描信号以及所述发光控制信号。
本公开至少一实施例还提供一种显示装置的制备方法，包括：在衬底基板上形成像素电路；所述像素电路包括驱动晶体管、第一晶体管以及第二晶体管；所述驱动晶体管包括控制极、第一极和第二极，且被配置为，根据所 述驱动晶体管的控制极的电压，控制流经所述驱动晶体管的第一极和所述驱动晶体管的第二极的用于驱动发光元件发光的驱动电流；所述第一晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第一扫描信号将数据信号写入所述驱动晶体管的控制极；所述第二晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第二扫描信号将所述数据信号写入所述驱动晶体管的控制极；所述衬底基板包括可掺杂的半导体主体；所述制备方法还包括：在所述半导体主体上形成所述衬底基板的第一导电层以及第二导电层，其中，所述第一晶体管包括位于所述第一导电层中的栅极以及位于所述第二导电层中的第一极和第二极；在所述半导体主体中形成与所述第一晶体管的第一极接触的第一晶体管的第一掺杂区以及与所述第一晶体管的第二极接触的第一晶体管的第二掺杂区，所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；以及在所述半导体主体中形成与所述第一晶体管的第二掺杂区的掺杂类型相同的第一晶体管的漂移掺杂区，其中，所述第一晶体管的漂移掺杂区位于所述半导体主体中且与所述第一晶体管的第二掺杂区间隔开，所述第一晶体管的栅极在所述衬底基板上的正投影与所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第一晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影中，所述第一晶体管的漂移掺杂区的掺杂浓度低于所述第一晶体管的第一掺杂区的掺杂浓度。
例如，本公开的一实施例提供的制备方法还包括：在所述半导体主体和所述第一导电层之间形成所述衬底基板的第一绝缘层，所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第一掺杂区的第二部分；所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
本公开至少一实施例还提供一种显示装置的制备方法，包括：在衬底基板上形成像素电路；所述像素电路包括驱动晶体管、第一晶体管以及第二晶体管；所述驱动晶体管包括控制极、第一极和第二极，且被配置为，根据所述驱动晶体管的控制极的电压，控制流经所述驱动晶体管的第一极和所述驱动晶体管的第二极的用于驱动发光元件发光的驱动电流；所述第一晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第一扫描信号将 数据信号写入所述驱动晶体管的控制极；所述第二晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第二扫描信号将所述数据信号写入所述驱动晶体管的控制极；所述衬底基板包括可掺杂的半导体主体；所述制备方法还包括：在所述半导体主体上形成所述衬底基板的第一导电层以及第二导电层，其中，所述第一晶体管包括位于所述第一导电层中的栅极以及位于所述第二导电层中的第一极和第二极；在所述半导体主体中形成与所述第一晶体管的第一极接触的第一晶体管的第一掺杂区以及与所述第一晶体管的第二极接触的第一晶体管的第二掺杂区，所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；以及在所述半导体主体和所述第一导电层之间形成所述衬底基板的第一绝缘层，其中，所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第一掺杂区的第二部分；所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
例如，本公开的一实施例提供的制备方法还包括：在所述半导体主体中形成与所述第一晶体管的第二掺杂区的掺杂类型相同的第一晶体管的漂移掺杂区，所述第一晶体管的漂移掺杂区位于所述半导体主体中且与所述第一晶体管的第二掺杂区间隔开，所述第一晶体管的栅极在所述衬底基板上的正投影与所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第一晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影中，所述第一晶体管的漂移掺杂区的掺杂浓度低于所述第一晶体管的第一掺杂区的掺杂浓度。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的截面示意图；
图2为本公开至少一实施例提供的一种显示装置的电路图；
图3为本公开至少一实施例提供的对应于图2的布局示意图；
图4A-4E分别示出了图3所示的显示装置的五个层布局的平面图；
图5为本公开至少一实施例提供的一种示意存储电容所在区域的示意图；
图6为本公开至少一实施例提供的关于存储电容的布局示意图；
图7A-图7D分别示出了图6所示的四个层分布的平面图；
图7E为本公开至少一实施例提供的关于存储电容的截面示意图；
图8为本公开至少一实施例提供的一种关于第一晶体管和第二晶体管的截面示意图；
图9为本公开至少一实施例提供的另一种关于第一晶体管和第二晶体管的截面示意图；
图10为本公开至少一实施例提供的又一种关于第一晶体管和第二晶体管的截面示意图；以及
图11为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前，硅基OLED显示面板广泛应用于虚拟现实(Virtual Reality，简称VR)或增强现实(Augmented Reality，简称AR)等近眼显示领域中，随着用户对显示质量越来越高的要求，例如，需要实现更高的分辨率和PPI(Pixels  Per Inch，每英寸像素数目)。为了实现更高的PPI，就需要对显示装置的布局进行设计以减小占用的布局面积，从而在相同大小的显示区域中可以设置更多个像素单元，从而可以实现高PPI。
本公开的至少一实施例提供的显示装置及其制备方法，可以通过布局设计减小显示装置占用的布局面积，从而可以使得该显示装置更易于实现高PPI。另外，本公开的至少一实施例还提供了一种可以降低或避免被高电压击穿风险的晶体管的结构设计。
下面结合附图对本公开的实施例进行详细说明。
图1为一种显示基板1000的结构示意图。如图1所示，该显示基板1000包括衬底基板600和发光元件620。例如，该发光元件620设置在衬底基板600上，且发光元件620的第一电极621比发光元件620的第二电极629更靠近衬底基板600。
例如，在一些示例中，该衬底基板600为硅基衬底基板，本公开的实施例包括但不限于此。例如，硅基衬底基板所采用的半导体制作工艺成熟，性能稳定，有利于制作微型显示器件。
例如，在一些示例中，该硅基衬底基板600包括驱动电路，该驱动电路与发光元件620电连接，以用于驱动发光元件620发光。例如，如图1所示，该驱动电路包括晶体管T。需要说明的是，驱动电路的具体电路结构可以根据实际需要进行设置。例如，图1中并未示出驱动电路的全部结构，驱动电路还可以包括例如其他晶体管，又例如存储电容等，本公开的实施例对此不作限制。
例如，如图1所示，晶体管T包括栅电极G、源电极S和漏电极D。三个电极分别对应三个电极连接部。例如，栅电极G与栅电极连接部610g电连接，源电极S与源电极连接部610s电连接，漏电极D与漏电极连接部610d电连接。例如，三个电极均是通过钨过孔605与三个电极连接部对应电连接。
例如，如图1所示，源电极连接部610s通过钨过孔与发光元件620的第一电极621电连接。例如，源电极连接部610s通过钨过孔与第一电极621的金属反射层622电连接，同时，在第一电极621中，透明导电层626通过无机绝缘层624中的过孔624a与金属反射层622电连接。在晶体管T处于导通状态，由电源线提供的电信号可经过晶体管T的源电极S、源电极连接部610s、金属反射层622传输到透明导电层626。由于透明导电层626与第二 电极629之间形成电压差，在二者之间形成电场，空穴和电子被注入到发光功能层627中，发光功能层627在该电场作用下发光。可以理解的是，晶体管T中，源电极S和漏电极D的位置可互换(对应地，源电极连接部610s和漏电极连接部610d的位置也可互换)，也就是说，晶体管的源电极S和漏电极D之一(即源电极S或漏电极D)与发光元件620彼此电连接即可。
例如，栅电极连接部610g、源电极连接部610s和漏电极连接部610d的材料可以包括金属材料。例如，如图1所示，在栅电极连接部610g、源电极连接部610s和漏电极连接部610d每个的至少一侧(例如上侧和/或下侧)可以设置抗氧化层607，这样能有效防止这些电极连接部被氧化，提高其导电性能。
例如，如图1所示，该显示基板1000还包括用于限定发光功能层727的限定层728，该限定层728将有机发光功能层727限定在其开口728a中，避免彼此相邻的子像素之间的串扰。
需要说明的是，在图1所示的显示基板1000中，无机绝缘层624中的过孔624a可以设置在透明导电层626与金属反射层622的边缘区域之间。例如，在一些示例中，发光功能层627在衬底基板600上的正投影和过孔624a在衬底基板600上的正投影均位于金属反射层622在衬底基板600上的正投影内，同时，发光功能层627在衬底基板600上的正投影和过孔624a在衬底基板600上的正投影之间不存在交叠，从而金属反射层对发光功能层627发出的光进行反射时，过孔624a对该反射过程基本没有影响。
本公开的至少一实施例提供一种显示装置100，该显示装置100包括衬底基板以及形成在衬底基板上的至少一个像素电路和由该像素电路驱动的发光元件。该衬底基板例如为硅基衬底基板，该硅基衬底基板可以为体硅基板或者绝缘层上硅(SOI)基板。像素电路可以通过硅半导体工艺(例如CMOS工艺)制备在衬底基板中，而发光元件制备在具有像素电路的硅基板上。
下面结合图2和图3介绍该显示装置100，需要说明的是，图2和图3中未示出衬底基板。关于衬底基板可以参考图1中所示的衬底基板600。
如图2所示，该像素电路包括驱动晶体管140、第一晶体管110、第二晶体管120以及第三晶体管130。需要说明的是，在一些实施例中，像素电路也可以不包括第三晶体管130，本公开的实施例对此不作限定。
例如，驱动晶体管140包括控制极143、第一极141和第二极142，且 该驱动晶体管140被配置为根据驱动晶体管140的控制极143的电压，控制流经驱动晶体管140的第一极141和驱动晶体管140的第二极142的用于驱动发光元件LE发光的驱动电流。发光元件LE可以根据驱动电流的大小发出不同强度的光。
需要说明的是，本公开的实施例中采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开的实施例中所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。以下各实施例以晶体管的第一极为漏极，第二极为源极为例进行说明，不再赘述。
例如，第一晶体管110连接到驱动晶体管140的控制极143，且被配置为响应于第一扫描信号SCAN1将数据信号DATA写入驱动晶体管140的控制极143。
例如，第二晶体管120连接到驱动晶体管140的控制极143，且被配置为响应于第二扫描信号SCAN2将数据信号DATA写入驱动晶体管140的控制极143。
例如，第三晶体管130连接到驱动晶体管140的第一极141，且被配置为响应于发光控制信号EN将第一电源电压ELVDD施加到驱动晶体管140的第一极141。例如，本公开的实施例中的第一电源电压ELVDD为高电平电压，例如，第一电源电压ELVDD为5V。
如图2所示，在一些实施例中，第一晶体管110的第一极111(例如，漏极)以及第二晶体管120的第一极121(例如，漏极)连接以得到公共电极，并通过该公共电极与驱动晶体管140的控制极143连接。
在上述实施例中，还提供了第一扫描信号线SL1、第二扫描信号线SL2、数据线DL、第一电源电压线VL1以及发光控制线EL等以提供相应的电信号。第一晶体管110的控制极113被配置为从第一扫描信号线SL1接收第一扫描信号SCAN1，第一晶体管110的第二极112(例如，源极)被配置为从数据线DL接收数据信号DATA。第二晶体管120的控制极123被配置为从第二扫描信号线SL2接收第二扫描信号SCAN2，第二晶体管120的第二极 122(例如，源极)被配置为从数据线DL接收数据信号DATA。第三晶体管130的控制极133被配置为从发光控制线EL接收发光控制信号EN，第三晶体管130的第一极131(例如，漏极)被配置为从第一电源电压线VL1接收第一电源电压ELVDD，第三晶体管130的第二极132(例如，源极)和驱动晶体管140的第一极141(例如，漏极)连接。
驱动晶体管140的第二极142(例如，源极)被配置为和发光元件LE的第一极连接。例如，当发光元件LE为OLED时，驱动晶体管140的第二极142可以和该OLED的阳极连接。例如，该发光元件LE的第二极被配置为接收第四电源电压VCOM。例如，本公开的实施例中的第四电源电压VCOM为低电平电压。
例如，在本公开的实施例中，发光元件LE可以采用OLED，当多个像素单元构成显示面板中的像素阵列时，多个像素单元中的多个发光元件OLED的第二极(例如，阴极)可以电连接在一起，例如分别连接到同一个电极或一体形成，以接收第四电源电压VCOM，即多个像素单元中的多个发光元件OLED采用共阴极连接方式。
例如，发光元件OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图2所示，像素电路还包括存储电容CST，以存储写入到驱动晶体管140的控制极143的数据信号DATA，从而使得驱动晶体管140可以根据该存储的数据信号DATA的电压控制驱动发光元件LE的驱动电流的大小。存储电容CST的第一极和驱动晶体管140的控制极143连接，存储电容CST的第二极被配置为接收第三电源电压AVSS。例如，本公开的实施例中的第三电源电压AVSS为低电平电压。需要说明的是，在本公开的实施例中，第三电源电压AVSS可以和第四电源电压VCOM相同，例如，第三电源电压AVSS可以和第四电源电压VCOM均接地，本公开的实施例包括但不限于此。
如图2所示，在本公开的一些实施例中，第一晶体管110可以采用P型MOS晶体管，第二晶体管120、第三晶体管130以及驱动晶体管140可以采用N型MOS晶体管，例如，第一晶体管110、第二晶体管120、第三晶体管130以及驱动晶体管140形成在衬底基板中。
例如，如图2所示，第一晶体管110的第三级被配置为接收第二电源电 压VDD，例如，第一晶体管110的第三级和第二电源电压线VL2连接以接收第二电源电压VDD。
例如，第二晶体管120、第三晶体管130以及驱动晶体管140的第三极被配置为接地(GND)。需要说明的是，在本公开的实施例中，一个晶体管的第三极为与该晶体管的控制极(栅极)113相对的一极，以下各实施例与此相同，不再赘述。
在本公开的实施例中，由于第一晶体管110和第二晶体管120采用具有相反半导体型的MOS晶体管，所以第一晶体管110和第二晶体管120可以构成具有互补特性的传输门开关。在这种情形中，例如，可以使得提供至第一晶体管110的第一扫描信号SCAN1和提供至第二晶体管120的第二扫描信号SCAN2彼此互为反相信号，这样就可以保证第一晶体管110和第二晶体管120在同一时刻总有一个处于导通状态，从而可以没有电压损失地将数据信号DATA传输至存储电容CST，从而可以提高该像素电路的可靠性和稳定性。
图3示出了对应于图2所示的显示装置100衬底基板上的布局示意图。如图3所示，在本公开的实施例中，将沿第一晶体管110的第一极111至第一晶体管110的第二极112的方向称为第一方向D1，将沿第二晶体管120的第一极121至第二晶体管120的第二极122的方向称为第二方向D2，将沿第三晶体管130的第一极131至第三晶体管130的第二极132的方向称为第三方向D3，将沿驱动晶体管140的第一极141至驱动晶体管140的第二极142的方向称为第四方向D4。
例如，第一方向D1和第二方向D2中的至少一个和第四方向D4相交。例如，在像素电路包括第三晶体管130的情形下，第一方向D1、第二方向D2以及第三方向D3中的至少一个和第四方向D4相交。例如，第四方向D4为图3中从左至右的横向方向。
在像素电路中，由于驱动晶体管140的尺寸相对于其它开关晶体管(例如，第一晶体管110、第二晶体管120以及第三晶体管130)一般较大，所以在布局晶体管的位置时，可以将该驱动晶体管140沿第四方向D4布置，同时使得第一方向D1、第二方向D2以及第三方向D3中的至少一个和第四方向D4相交，这样可以使得四个晶体管的布局更紧凑，从而可以减小该显示装置100所占用的布局面积，从而可以使得该显示装置100更易于实现高 PPI。
在本公开的一些实施例中，可以使得第一方向D1和第二方向D2均和第四方向D4相交；又例如，可以使得第一方向D1、第二方向D2以及第三方向D3均和第四方向D4相交。例如，如图3所示，第四方向D4为横向方向，第一方向D1、第二方向D2以及第三方向D3均为图3中的与横向方向垂直的纵向方向。
例如，在本公开的一些实施中，第一方向D1和第二方向D2均和第四方向D4垂直；又例如，第一方向D1、第二方向D2以及第三方向D3均和第四方向D4垂直。对于显示装置的显示区域中的多个像素单元按照多行多列方式排布的情形，采用这种方式可以使得该显示装置100的布局更紧凑，从而可以进一步减小该显示装置100所占用的布局面积，从而可以使得该显示装置100更易于实现高PPI。
例如，如图3所示，第一晶体管110包括沿第一方向D1延伸的第一有源区114，第一有源区114包括第一晶体管110的第一极111、第一晶体管110的第二极112、以及第一晶体管110的第一极111和第一晶体管110的第二极112之间形成的沟道区。
第二晶体管120包括沿第二方向D2延伸的第二有源区124，第二有源区124包括第二晶体管120的第一极121、第二晶体管120的第二极122、以及第二晶体管120的第一极121和第二晶体管120的第二极122之间形成的沟道区。
第三晶体管130包括沿第三方向D3延伸的第三有源区134，第三有源区134包括第三晶体管130的第一极131、第三晶体管130的第二极132、以及第三体管130的第一极131和第三晶体管130的第二极132之间形成的沟道区。
驱动晶体管140包括沿第四方向D4延伸的第四有源区144，第四有源区144包括第四晶体管140的第一极141、第四晶体管140的第二极142、以及第四体管140的第一极141和第四晶体管140的第二极142之间形成的沟道区。
例如，本公开的实施例提供的显示装置100中的衬底基板为硅基衬底基板，上述第一有源区114、第二有源区124、第三有源区134和第四有源区144均为硅基衬底基板中的掺杂区，这些掺杂区例如通过离子注入工艺或离 子扩散工艺得到，对于非晶硅，P型掺杂可以通过掺杂硼(B)实现，N型掺杂可以通过掺杂磷(P)或砷(As)实现，本公开的实施例对此不作限制。
例如，在本公开的一些实施例中，第一有源区114与第二有源区124的掺杂类型相反。例如，第一有源区114的掺杂类型为P型，第二有源区124的掺杂类型为N型。
如图3所示，第一有源区114的两个端部和第二有源区124的两个端部在第四方向D4上彼此对齐，并且例如，第一有源区114的两个端部和第二有源区124彼此相邻布置。采用这种方式可以简化该显示装置100的布局设计。
第一有源区114沿第一方向D1的一个边缘与第二有源区124沿第二方向D2的一个边缘的连线和第四方向D4平行；第一有源区114沿第一方向D1的另一个边缘与第二有源区124沿第二方向D2的另一个边缘的连线和第四方向D4平行。采用这种方式可以简化该显示装置100的布局设计。
与用于非显示用途的硅基模拟CMOS电路相比，本公开的实施例提供的显示装置100中的用于发光元件LE的驱动电流要小1到2个数量级。驱动晶体管140在饱和状态下的电流特性为：
Figure PCTCN2019102309-appb-000001
其中，I D为驱动晶体管140提供的驱动电流，W/L为驱动晶体管140的宽长比，K为一常数值，V GS4为驱动晶体管140的栅极和源极之间的电压差，V th为驱动晶体管140的阈值电压。
由上面的公式可以看出，要实现较低的驱动电流，则驱动晶体管140在尺寸设计时就要增大L值，这不利于减小采用该驱动晶体管140的显示装置100的布局面积。
本公开的一些实施例提供的像素电路100通过对第一有源区114、第二有源区124、第三有源区134以及第四有源区144的掺杂浓度之间的相对关系进行调整，可以改善或避免上述问题。
例如，第四有源区144的掺杂浓度小于第三有源区134的掺杂浓度。例如，第三有源区134的掺杂浓度约为10 17cm -3，第四有源区144的掺杂浓度约为10 13cm -3，第四有源区144的掺杂浓度比第三有源区134的掺杂浓度小4个数量级。本公开的实施例通过降低第四有源区144的掺杂浓度，在不改变驱动晶体管140的尺寸(例如，宽长比W/L不变)的情形下，可以使得驱 动晶体管140输出更小的驱动电流，输出的驱动电流的变化更平缓，从而使得采用该驱动晶体管140的像素电路驱动发光元件LE(例如，OLED)进行发光时的灰阶值可以获得较好的均匀性。
例如，在本公开的一些实施例提供的显示装置100中，第一有源区114以及第二有源区124中的至少一个的掺杂浓度大于第三有源区134的掺杂浓度。
例如，第一有源区114以及第二有源区124的掺杂浓度均大于第三有源区的掺杂浓度。例如，第一有源区114以及第二有源区124的掺杂浓度约为10 20cm -3，在这种情形下，第一有源区114以及第二有源区124的掺杂浓度比第三有源区134的掺杂浓度大3个数量级。
如图2所示，第一晶体管110和第二晶体管120在像素电路里是用作开关晶体管的，所以需要具有良好的开关特性。当第一有源区114或/和第二有源区124的掺杂浓度较大时，可以获得较大的驱动电流且该驱动电流的变化更快速，从而使得该第一晶体管110或/和第二晶体管120具有更好的开关特性。
例如，在本公开的实施例中，第一晶体管110为第一半导体型MOS晶体管，第二晶体管、第三晶体管以及驱动晶体管均为第二半导体型MOS晶体管，第一半导体型和第二半导体型相反。例如，第一半导体型为P型，第二半导体型为N型，本公开的实施例包括但不限于此。
如图3所示，本公开的一些实施例提供的显示装置100还包括用于传输第一扫描信号SCAN1的第一扫描信号线SL1以及用于传输第二扫描信号SCAN2的第二扫描信号线SL2，第一扫描信号线SL1与第二扫描信号线SL2平行设置。
例如，第一扫描信号线SL1和第一晶体管110的控制极113连接以提供第一扫描信号SCAN1，第二扫描信号线SL2和第二晶体管120的控制极123连接以提供第二扫描信号SCAN2。
例如，第一扫描信号线SL1以及第二扫描信号线SL2的延伸方向均与第四方向D4平行。第一扫描信号线SL1在衬底基板的正投影与第二扫描信号线SL2在衬底基板的正投影平行，例如，均和第四方向D4平行。
例如，像素电路在衬底基板的正投影所在的区域为像素区域，第一扫描信号线SL1和第二扫描信号线SL2并列位于像素区域的一侧。
如图3所示，本公开的一些实施例提供的显示装置100还包括用于传输数据信号DATA的数据线DL，第二扫描信号线SL2在衬底基板的正投影与数据线DL在衬底基板的正投影至少部分重叠。例如，第二扫描信号线SL2与数据线DL在垂直于衬底基板的方向上重叠。例如，如图3所示，可以把图3所在的平面看做衬底基板所在的平面，则垂直于衬底基板即垂直于图3所在的平面。本公开的实施例通过使得第二扫描信号线SL2与数据线DT在垂直于衬底基板的方向上重叠，可以使得该数据线DL不占用额外的布局面积，从而可以进一步减小该显示装置100所占用的布局面积，更有利于实现高PPI。
如图3所示，本公开的一些实施例提供的显示装置100还包括用于传输第一电源电压ELVDD的第一电源电压线VL1以及用于传输发光控制信号EN的发光控制线EL。
例如，第一电源电压线VL1和发光控制线EL的部分延伸方向与第四方向D4平行，第一扫描信号线SL1、第二扫描信号线SL2、第一电源电压线VL1以及发光控制线EL在衬底基板的正投影沿与第四方向D4的垂直方向依次排布。
需要说明的是，在本公开的一些实施例提供的显示装置100中，如图3所示，使得第一电源电压线VL1在衬底基板的正投影位于第二扫描信号线SL2在衬底基板的正投影和发光控制线EL在衬底基板的正投影之间，由于第一电源电压线VL1传输的第一电源电压ELVDD为直流信号，而第二扫描信号线SL2传输的第二扫描信号SCAN2以及发光控制线EL传输的发光控制信号EN均为跳变信号，所以采用上述排布方式可以有效屏蔽第二扫描信号SCAN2与发光控制信号EN之间的相互干扰。
如图3所示，本公开的一些实施例提供的显示装置100还包括用于传输第二电源电压VDD的第二电源电压线VL2，第一晶体管110的第三极和第二电源电压线VL2电连接以接收第二电源电压VDD。例如，本公开的实施例中的第二电源电压VDD为高电平电压，例如，第二电源电压为5V。
例如，第一晶体管110为P型MOS晶体管，其沟道区为P型掺杂。如图2所示，与第一晶体管110的控制极(栅极)113相对的第三极接收第二电源电压VDD。例如，第二晶体管120、第三晶体管130以及驱动晶体管140均为N型MOS晶体管，其沟道区为N型掺杂，第二晶体管120、第三晶体 管130以及驱动晶体管140的第三极均配置为接地(GND)。
例如，第二电源电压线VL2在衬底基板的正投影位于第一电源电压线VL1在衬底基板的正投影以及发光控制线EL在衬底基板的正投影之间，且第二电源电压线VL2的部分延伸方向与第四方向D4平行。
如图3所示，第二电源电压线VL2在沿第四方向D4延伸时，有一个弯折区域；另外，发光控制线EL在沿第四方向D4延伸时，也有一个弯折区域，且第二电源电压线VL2与发光控制线EL的弯折方向不同。采用这种走线方式例如可以为下文中描述的第一转接电极AE1留出布局空间。
例如，如图3所示，第一晶体管110以及第二晶体管120均设置在第二扫描信号线SL2与发光控制线EL之间，且第一晶体管110和第一电源电压线VL1以及第二电源电压线VL2相交，且第二晶体管120和第一电源电压线VL1以及第二电源电压线VL2相交。
例如，第一晶体管110的第一有源区114在衬底基板上的正投影以及第二晶体管120的第二有源区124在衬底基板上的正投影均位于第二扫描信号线SL2在衬底基板上的正投影与发光控制线EL在衬底基板上的正投影之间。
第一晶体管110的第一有源区114在衬底基板上的正投影与第一电源电压线VL1在衬底基板上的正投影相交，且第一晶体管110的第一有源区114在衬底基板上的正投影与第二电源电压线VL2在衬底基板上的正投影相交。
第二晶体管120的第二有源区124在衬底基板上的正投影与第一电源电压线VL1在衬底基板上的正投影相交，且第二晶体管120的第二有源区124在衬底基板上的正投影与第二电源电压线VL2在衬底基板上的正投影相交。
如图3所示，本公开的一些实施例提供的显示装置100还包括设置在发光控制线EL的第一侧的第一转接电极AE1，以及从发光控制线EL的第一侧延伸至发光控制线EL的第二侧的第二转接电极AE2。
例如，第二转接电极AE2在衬底基板的正投影与发光控制线EL在衬底基板上的正投影交叉。第一转接电极AE1的两个端部分别和第一晶体管110的第一极111以及第二晶体管120的第一极121电连接，第一转接电极AE1和第二转接电极AE2电连接，且第二转接电极AE2和驱动晶体管140的控制极143电连接。
例如，第二转接电极AE2的延伸方向与第一转接电极AE1的延伸方向垂直，并且和第四方向D4垂直。
由于第二转接电极AE2连接存储电容CST，像素电路在工作中该第二转接电极AE2上的电平可能会有较大的波动，该波动可能会对第一电源电压线VL1造成串扰，产生噪声。在本公开的实施例提供的显示装置100中，利用第二电源电压线VL2将第一电源电压线VL1和第二转接电极AE2间隔开，从而可以降低第二转接电极AE2上的电平波动对第一电源电压线VL1造成的串扰，隔绝噪声。
另外，本公开的一些实施例提供的显示装置100通过延长第一晶体管110的第一有源区114以及延长第二晶体管120的第二有源区124，从而为第二电源电压线VL2留出布线通道。
例如，本公开的实施例提供的像素电路(矩形形状)的布局尺寸大致为4.5um×2.9um。
图4A-4E分别示出了图3中所示的显示装置100的各层布局的平面图。
图4A示出了第一晶体管110的第一有源区114、第二晶体管120的第二有源区124、第三晶体管130的第三有源区134以及驱动晶体管140的第四有源区144，可以将图4A示出的层称为有效显示(AA)层。
图4B示出了第一晶体管110的控制极113、第二晶体管120的控制极123、第三晶体管130的控制极133以及驱动晶体管140的控制极143。可以将4B示出的层称为第一导电层，下文中将对第一导电层进一步描述。例如，第一导电层的材料可以采用多晶硅。
图4C示出了第一电源电压线VL1、第二电源电压线VL2、发光控制线EL、数据线DL、接地线GND、第一转接电极AE1等。可以将图4C示出的层称为第一金属层(metal1)。
图4D示出了第二转接电极AE2、连接第一扫描信号线SL1与第一晶体管110的电极、连接第二扫描信号线SL2与第二晶体管120的电极。可以将图4D示出的层称为第二金属层(metal2)。
图4E示出了第一扫描信号线SL1以及第二扫描信号线SL2，可以将图4E示出的层称为第三金属层(metal3)。
需要说明的是，在本公开的实施例中为了示意清楚在图3中并没有示意出存储电容CST，下面结合图5-图7E对图2中的所示出的存储电容CST进行进一步描述。
如图5所示，图5中所示的区域800为设置存储电容CST的区域。需要 说明的是，为了示意清楚，图5中并没有示出全部结构的对应标记，省略的部分可以参考图3中的对应标记。
图6为存储电容CST的布局图，图7A-图7D为对应图6的各层布局的平面图，图7E为存储电容CST的截面示意图。
图6示出了4层结构，分别为第三金属层metal3、第四金属层metal4、辅助金属层metal4'、第五金属层metal5；另外还示出了第一过孔V1以及第二过孔V2，在下文中将结合截面示意图对第一过孔V1以及第二过孔V2进行描述，这里不再赘述。
例如，图7A示出了第三金属层metal3，例如，该第三金属层和图4E中示出的层是同一层。如图7A所示，该第三金属层metal3包括两部分，分别为充当第一电容C1的第一极的电极811和充当第一电容C1的第二极的电极812。例如，电极811被配置为接收第三电源电压AVSS；电极812通过第二过孔V2和第五金属层metal5中的电极840电连接，从而实现和驱动晶体管140的控制极143电连接。
电极811包括多个条状电极，电极812包括多个条状电极，电极811的多个条状电极和电极812的多个条状电极相互交替排布，且电极811和电极812以及之间的间隔部分形成第一电容C1。例如，该第一电容C1为存储电容CST的一部分，例如，该第一电容C1和下文中的第二电容C2并联从而形成存储电容CST。
例如，图7B示出了位于第四金属层metal4的电极820，例如，电极820为一个面状电极，该电极820充当第二电容C2的第一极。
例如，图7C示出了位于辅助金属层metal4'的电极830，例如，电极830为一个面状电极，该电极830充当第二电容C2的第二极。
例如，图7D示出了位于第五金属层metal5的电极840，以及第一过孔V1和第二过孔V2。
图7E示出了上述存储电容CST的部分结构的截面示意图，如图7E所示，位于第五金属层metal5的电极840通过第一过孔V1和位于辅助金属层metal4'的电极830电连接；另外，位于第五金属层metal5的电极840通过第二过孔V2和位于第三金属层metal3的电极812电连接。需要说明的是，第二过孔V2会贯穿第四金属层metal4，图7E中未示出。
如图7E所示，位于第四金属层metal4的电极820和位于辅助金属层 metal4'的电极830以及之间的间隔部分形成第二电容C2；例如，上文中所述的第一电容C1以及该第二电容C2并联共同构成存储电容CST。
在本公开的实施例中，如图7E所示，在第四金属层metal4和第五金属层metal5之间设置辅助金属层metal4'，从而可以使得第四金属层metal4与辅助金属层metal4'之间的间距例如为第四金属层metal4与第五金属层metal5之间的间距的约1/10，从而可以有效地增大该第二电容C2单位面积内的电容值。
如图2和图3所示，本公开的实施例还提供一种显示装置100，包括衬底基板以及形成在衬底基板上的至少一个像素电路。像素电路包括驱动晶体管140、第一晶体管110、第二晶体管120以及第三晶体130。
驱动晶体管140包括控制极143、第一极141和第二极142，且被配置为，根据驱动晶体管140的控制极143的电压，控制流经驱动晶体管140的第一极141和驱动晶体管140的第二极142的用于驱动发光元件LE发光的驱动电流。
第一晶体管110连接到驱动晶体管140的控制极143，且被配置为响应于第一扫描信号SCAN1将数据信号DATA写入驱动晶体管140的控制极143。第二晶体管120连接到驱动晶体管140的控制极143，且被配置为响应于第二扫描信号SCAN2将数据信号DATA写入驱动晶体管140的控制极143。第三晶体管130连接到驱动晶体管140的第一极141，且被配置为响应于发光控制信号EN将第一电源电压ELVDD施加到驱动晶体管140的第一极141。
该显示装置100还包括用于传输第一扫描信号SCAN1的第一扫描信号线SL1以及用于传输第二扫描信号SCAN2的第二扫描信号线SL2，用于传输第一电源电压ELVDD的第一电源电压线VL1以及用于传输发光控制信号EN的发光控制线EL；第一扫描信号线SL1、第二扫描信号线SL2、第一电源电压线VL1以及发光控制线EL在衬底基板的正投影沿与第四方向D4的垂直方向依次排布。
例如，沿第一晶体管110的第一极111至第一晶体管110的第二极112的方向为第一方向D1，沿第二晶体管120的第一极121至第二晶体管120的第二极122的方向为第二方向D2，沿第三晶体管130的第一极131至第三晶体管130的第二极132的方向为第三方向D3，沿驱动晶体管140的第 一极141至驱动晶体管140的第二极142的方向为第四方向D4，第一方向D1、第二方向D2以及第三方向D3均和第四方向D4相交。例如，第一方向D1、第二方向D2以及第三方向D3均和第四方向D4垂直。
本公开的至少一实施例还提供一种显示装置100的制备方法，该制备方法包括：在衬底基板上形成像素电路。
像素电路包括驱动晶体管140、第一晶体管110以及第二晶体管120。
驱动晶体管140包括控制极143、第一极141和第二极142，且被配置为，根据驱动晶体管140的控制极143的电压，控制流经驱动晶体管140的第一极141和驱动晶体管140的第二极142的用于驱动发光元件LE发光的驱动电流。
第一晶体管110连接到驱动晶体管140的控制极143，且被配置为响应于第一扫描信号SCAN1将数据信号DATA写入驱动晶体管140的控制极143。第二晶体管120连接到驱动晶体管140的控制极143，且被配置为响应于第二扫描信号SCAN2将数据信号DATA写入驱动晶体管140的控制极143。
沿第一晶体管110的第一极111至第一晶体管110的第二极112的方向为第一方向D1，沿第二晶体管120的第一极121至第二晶体管120的第二极122的方向为第二方向D2，沿驱动晶体管140的第一极141至驱动晶体管140的第二极142的方向为第四方向D4，第一方向D1以及第二方向D2中的至少一个和第四方向D4相交；例如，第一方向D1和第二方向D2均和第四方向D4垂直。
目前，随着用户对硅基OLED显示装置的高亮度显示的需求不断提高，该显示装置中的像素电路需要输出更高的驱动电流至OLED的阳极。例如，如图2所示，当OLED需要输出较大亮度时，OLED阳极电压需要较高的电压V anode，此时第一晶体管110的第一极111(例如，漏极)和第二晶体管120的第一极121(例如，漏极)会出现高电压V anode+V GS4(V GS4为驱动晶体管140的栅极和第二极之间的电压差)，第一晶体管110和第二晶体管120的栅极和第一极之间都会出现高电压。在这种情形下，该像素电路中的第一晶体管110和第二晶体管120会承受高电压，可能会发生击穿现象，从而可能会影响该像素电路的可靠性和稳定性。
本公开的至少一实施例还提供了一种可以降低或避免被高电压击穿风 险的晶体管的结构设计，从而可以使得采用该晶体管的像素电路不容易被高电压击穿以及可以实现该像素电路的高亮度显示驱动。
本公开至少一实施例提供一种显示装置100，包括衬底基板以及形成在衬底基板上的像素电路。像素电路包括驱动晶体管140、第一晶体管110以及第二晶体管120；驱动晶体管140包括控制极143、第一极141和第二极142，且被配置为，根据驱动晶体管140的控制极143的电压，控制流经驱动晶体管140的第一极141和驱动晶体管140的第二极142的用于驱动发光元件LE发光的驱动电流；第一晶体管110的第一极111连接到驱动晶体管140的控制极143，且被配置为响应于第一扫描信号SCAN1将数据信号DATA写入驱动晶体管140的控制极143；第二晶体管120连接到驱动晶体管140的控制极143，且被配置为响应于第二扫描信号SCAN2将数据信号DATA写入驱动晶体管140的控制极143。
例如，如图8所示，衬底基板包括可掺杂的半导体主体330以及位于半导体主体330之上的第一导电层310以及第二导电层320。
第一晶体管110包括位于第一导电层310中的栅极GE1、位于第二导电层320中的第二极SE1和第一极DE1，以及与第一晶体管110的第一极DE1接触的第一掺杂区DR1、与第一晶体管110的第二极SE1接触的第二掺杂区SR1，第一晶体管110的第一掺杂区DR1与第一晶体管110的第二掺杂区SR1彼此间隔开、掺杂类型相同且都位于半导体主体330中。该第一晶体管110的沟道区在第一掺杂区DR1和第二掺杂区SR1之间。当第一晶体管110由于栅极GE1上施加的控制电压而导通时，第一掺杂区DR1和第二掺杂区SR1通过该沟道区而导通。需要说明的是，这里的第一晶体管110的栅极GE1即为上文中的所描述的第一晶体管110的控制极113，以下各实施例与此相同，不再赘述。
如图8所示，第一晶体管110还包括与第一掺杂区DR1接触的漂移掺杂区DF1，第一晶体管110的漂移掺杂区DF1与第一晶体管110的第二掺杂区SR1彼此间隔开、掺杂类型相同且都位于半导体主体330中。例如，第一晶体管110为P型MOS晶体管，第一晶体管110的第一掺杂区DR1、第二掺杂区SR1以及漂移掺杂区DF1的掺杂类型均为P型掺杂，且半导体主体330为掺杂类型为P型的体硅或绝缘层上硅。
例如，第一晶体管110的栅极GE1在衬底基板上的正投影与第一晶体管110的漂移掺杂区DF1在衬底基板上的正投影部分重叠，并且第一晶体管110的第一掺杂区DR1在衬底基板上的正投影位于第一晶体管110的漂移掺杂区DF1在衬底基板上的正投影中；第一晶体管110的漂移掺杂区DF1的掺杂浓度低于第一晶体管110的第一掺杂区DR1的掺杂浓度。当第一晶体管110由于栅极GE1上施加的控制电压而导通时，第一掺杂区DR1和第二掺杂区SR1通过沟道区以及第一晶体管110的漂移掺杂区DF1而导通。
本公开的实施例提供的显示装置100中的像素电路通过在第一晶体管110中设置漂移掺杂区DF1，并使得第一晶体管110的漂移掺杂区DF1的掺杂浓度低于第一晶体管110的第一掺杂区DR1的掺杂浓度，从而可以提高第一晶体管110的第一极DE1到第二极SE1之间的击穿电压，从而使得该第一晶体管110可以降低或避免被高电压击穿风险。例如，该第一晶体管110为P型MOS晶体管。
如图8所示，在至少一个实施例中，第一晶体管110的漂移掺杂区DF1包括第一部分DF11和第二部分DF12；第二部分DF12在衬底基板上的正投影与第一晶体管110的第一掺杂区DR1在衬底基板上的正投影重叠，此时，可以认为第一晶体管110的第一掺杂区DF1的第二部分DF12构成了沟道区的一部分，且与沟道区的其他部分不同。例如，第一晶体管110的第一掺杂区DR1在第一晶体管110的漂移掺杂区DF1之中。例如，第一晶体管110的第一掺杂区DR1在半导体主体330中的掺杂深度可以小于、等于或大于第一晶体管110的漂移掺杂区DF1的掺杂深度。
如图8所示，在本公开的一些实施例提供的第一晶体管110中，第一晶体管110的第一掺杂区DR1、第二掺杂区SR1和漂移掺杂区DF1位于半导体主体330中的第一阱WL1中，例如，第一阱WL1的掺杂类型为N型掺杂。
第一晶体管110的栅极GE1在衬底基板上的正投影位于第一阱WL1在衬底基板上的正投影中，且第一阱WL1位于第一晶体管110的第一掺杂区DR1与第一晶体管110的第二掺杂区SR1之间的部分构成第一晶体管110的沟道区。例如，图3中示出了第一阱WL1所在的区域。
例如，如图8所示，第一晶体管110还包括辅助掺杂区BR；例如，第一晶体管110的辅助掺杂区BR的掺杂类型为N型掺杂，第一晶体管110的辅 助掺杂区BR与第一晶体管110的第二掺杂区SR1接触，第一晶体管110的辅助掺杂区BR与第一晶体管110的第二极SE1电连接，且第一晶体管110的辅助掺杂区BR在衬底基板上的正投影位于第一阱WL1在衬底基板上的正投影中。该辅助掺杂区BR可以起到隔离作用，防止发生漏电。
如图8所示，本公开的一些实施例提供的显示装置100中的衬底基板还包括位于半导体主体330和第一导电层310之间的第一绝缘层IS1，该第一绝缘层IS1可以使得第一晶体管110的栅极GE1与半导体主体330绝缘。例如，该第一绝缘层IS1可以为栅绝缘层，例如可以为氧化硅层，并且可以通过气相沉积工艺形成，或通过热氧化工艺直接对硅基衬底基板进行氧化而得到。
该第一绝缘层IS1包括靠近第一晶体管110的第一掺杂区DR1的第一部分IS11以及远离第一晶体管110的第一掺杂区DR1的第二部分IS12。
例如，在至少一个实施例中，上述第一绝缘层IS1的第一部分IS11的厚度大于第一绝缘层IS1的第二部分IS12的厚度，厚度为沿与衬底基板垂直的方向上的厚度。例如，第一绝缘层IS1的第一部分IS11的厚度为7～8纳米，第一绝缘层IS1的第二部分IS12的厚度为2～3纳米。
在本公开的实施例中，通过将第一绝缘层IS1的第一部分IS11的厚度加厚，例如加厚到第二部分IS12的两倍以上，从而使得第一晶体管110的栅极GE1和第一晶体管110的第一极DE1之间可以降低或避免被高电压击穿的风险。
如图8所示，衬底基板还包括平坦化绝缘层PL，该平坦化绝缘层PL覆盖第一晶体管110的栅极GE1，且发光元件LE位于平坦化绝缘层PL之上。该平坦化绝缘层PL可以覆盖上述像素电路，从而使得平坦化绝缘层PL的表面较平坦，从而更有利于在平坦化绝缘层PL之上形成发光元件LE。该平坦化绝缘层PL可以为氧化硅、氧氮化硅、氮化硅等，可以采用气相沉积等工艺得到。
例如，在图8所示的实施例中，第一晶体管110采用可以降低或避免被高电压击穿风险的结构设计，而第二晶体管120采用普通MOS晶体管结构设计。如图8所示，第二晶体管120包括位于第一导电层310中的栅极GE2、位于第二导电层320中的第一极DE2和第二极SE2，以及与第二晶体管120的第一极DE2接触的第一掺杂区DR2，与第二晶体管120的第二极SE2接 触的第二掺杂区SR2，第二晶体管120的第一掺杂区DR2与第二晶体管120的第二掺杂区SR2彼此间隔开、掺杂类型相同且都位于半导体主体330中。需要说明的是，这里的第二晶体管120的栅极GE2即为上文中的所描述的第二晶体管120的控制极123，以下各实施例与此相同，不再赘述。例如，第二晶体管120为N型MOS晶体管，第二晶体管120的第一掺杂区DR2、第二掺杂区SR2的掺杂类型均为N型掺杂。
例如，如图8所示，第二晶体管120还包括辅助掺杂区BR2，第二晶体管120的辅助掺杂区BR2与第二晶体管120的第二掺杂区SR2接触，第二晶体管120的辅助掺杂区BR2与第二晶体管120的第二极SE2电连接，第二晶体管120的辅助掺杂区BR2的掺杂类型与第二晶体管120的第二掺杂区SR2的掺杂类型相反，例如，第二晶体管120的辅助掺杂区BR2的掺杂类型为P型掺杂。该辅助掺杂区BR2可以起到隔离作用，防止发生漏电。
需要说明的是，本公开的实施例包括但不限于上述情形，第一晶体管110也可以采用N型MOS晶体管，第一晶体管110中的第一掺杂区DR1的掺杂类型为N型，半导体主体330为掺杂类型为P型的体硅或绝缘层上硅。
例如，在第一晶体管110为N型MOS晶体管的情形下，该第一晶体管110还可以进一步包括辅助掺杂区，此时第一晶体管110的辅助掺杂区的掺杂类型为P型，第一晶体管110的辅助掺杂区与第一晶体管110的第二掺杂区SR1接触，辅助掺杂区与第一晶体管110的第二极SE1电连接。
如图9所示，在本公开的一些实施例提供的像素单元中，第二晶体管120采用可以降低或避免被高电压击穿风险的结构设计，而第一晶体管110采用普通MOS晶体管结构设计。
如图9所示，第二晶体管120包括位于第一导电层310中的栅极GE2、位于第二导电层320中的第一极DE2和第二极SE2，以及与第二晶体管120的第一极DE2接触的第一掺杂区DR2、与第二晶体管120的第二极SE2接触的第二掺杂区SR2，第二晶体管120的第一掺杂区DR2与第二晶体管120的第二掺杂区SR2彼此间隔开、掺杂类型相同且都位于半导体主体330中。
例如，该第二晶体管120还包括与第一掺杂区DR2接触的漂移掺杂区DF2，第二晶体管120的漂移掺杂区DF2与第二晶体管120的第二掺杂区SR2彼此间隔开、掺杂类型相同且都位于半导体主体330中。例如，第二晶体管120为P型MOS晶体管，第二晶体管120的第一掺杂区DR2、第二掺 杂区SR2以及漂移掺杂区DF2的掺杂类型均为N型掺杂，且半导体主体330为掺杂类型为P型的体硅或绝缘层上硅。
例如，第二晶体管120的栅极GE2在衬底基板上的正投影与第二晶体管120的漂移掺杂区DF2在衬底基板上的正投影部分重叠，并且第二晶体管120的第一掺杂区DR2在衬底基板上的正投影位于第二晶体管120的漂移掺杂区DF2在衬底基板上的正投影中；第二晶体管120的漂移掺杂区DF2的掺杂浓度低于第二晶体管120的第一掺杂区DR2的掺杂浓度。
本公开的实施例提供的显示装置100中的像素电路通过在第二晶体管120中设置漂移掺杂区DF2，并使得第二晶体管120的漂移掺杂区DF2的掺杂浓度低于第二晶体管120的第一掺杂区DR2的掺杂浓度，从而可以提高第二晶体管120的第一极DE2到第二极SE2之间的击穿电压，从而使得该第二晶体管120可以降低或避免被高电压击穿风险。如图9所示，第二晶体管120的漂移掺杂区DF2包括第一部分DF21和第二部分DF22；第二部分DF22在衬底基板上的正投影与第二晶体管120的第一掺杂区DR2在衬底基板上的正投影重叠。例如，第二晶体管120的第一掺杂区DR2在第二晶体管120的漂移掺杂区DF2之中。
例如，如图9所示，第二晶体管120还包括辅助掺杂区BR2；例如，第二晶体管120的辅助掺杂区BR2的掺杂类型为P型掺杂，第二晶体管120的辅助掺杂区BR2与第二晶体管120的第二掺杂区SR2接触，第二晶体管120的辅助掺杂区BR2与第二晶体管120的第二极SE2电连接。该辅助掺杂区BR2可以起到隔离作用，防止发生漏电。
如图9所示，本公开的一些实施例提供的显示装置100中的衬底基板还包括位于半导体主体330和第一导电层310之间的第二绝缘层IS2，该第二绝缘层IS2可以使得第二晶体管120的栅极GE2与半导体主体330绝缘。例如，该第二绝缘层IS2可以为栅绝缘层，例如可以为氧化硅层，并且可以通过气相沉积工艺形成，或通过热氧化工艺直接对硅基衬底基板进行氧化而得到。
该第二绝缘层IS2包括靠近第二晶体管120的第一掺杂区DR2的第一部分IS21以及远离第二晶体管120的第一掺杂区DR2的第二部分IS22。
例如，第二绝缘层IS2的第一部分IS21的厚度大于第二绝缘层IS2的第二部分IS22的厚度，厚度为沿与衬底基板垂直的方向上的厚度。例如，第二 绝缘层IS2的第一部分IS21的厚度为7～8纳米，第二绝缘层IS2的第二部分IS22的厚度为2～3纳米。
在本公开的实施例中，通过将第二绝缘层IS2的第一部分IS21的厚度加厚，例如加厚到第二部分IS22的两倍以上，从而使得第二晶体管120的栅极GE2和第二晶体管120第一极DE2之间可以降低或避免被高电压击穿的风险。
如图9所示，衬底基板还包括平坦化绝缘层PL，该平坦化绝缘层PL覆盖第二晶体管120的栅极GE2，且发光元件LE位于平坦化绝缘层PL之上。该平坦化绝缘层PL可以覆盖上述像素电路，从而使得平坦化绝缘层PL的表面较平坦，从而更有利于在平坦化绝缘层PL之上形成发光元件。该平坦化绝缘层PL可以为氧化硅、氧氮化硅、氮化硅等，可以采用气相沉积等工艺得到。
例如，在图9所示的实施例中，第二晶体管120采用可以降低或避免被高电压击穿风险的结构设计，而第一晶体管110采用普通MOS晶体管结构设计。如图9所示，第一晶体管110包括位于第一导电层310中的栅极GE1、位于第二导电层320中的第一极DE1和第二极SE1，以及与第一晶体管110的第一极DE1接触的第一掺杂区DR1，与第一晶体管110的第二极SE1接触的第二掺杂区SR1，第一晶体管110的第一掺杂区DR1与第一晶体管110的第二掺杂区SR1彼此间隔开、掺杂类型相同且都位于半导体主体330中。例如，第一晶体管110为P型MOS晶体管，第一晶体管110的第一掺杂区DR1、第二掺杂区SR1的掺杂类型均为P型掺杂。
如图9所示，在本公开的一些实施例提供的第一晶体管110中，第一晶体管110的第一掺杂区DR1以及第二掺杂区SR1位于半导体主体330中的第二阱WL2中，例如，第二阱WL2的掺杂类型为N型掺杂。
第一晶体管110的栅极GE1在衬底基板上的正投影位于第二阱WL2在衬底基板上的正投影中，且第二阱WL2位于第一晶体管110的第一掺杂区DR1与第一晶体管110的第二掺杂区SR1之间的部分构成第一晶体管110的沟道区。
例如，如图9所示，第一晶体管110还包括辅助掺杂区BR；例如，第一晶体管110的辅助掺杂区BR的掺杂类型为N型掺杂，第一晶体管110的辅助掺杂区BR与第一晶体管110的第二掺杂区SR1接触，第一晶体管110的 辅助掺杂区BR与第一晶体管110的第二极SE1电连接，且第一晶体管110的辅助掺杂区BR在衬底基板上的正投影位于第二阱WL2在衬底基板上的正投影中。该辅助掺杂区BR可以起到隔离作用，防止发生漏电。
如图10所示，在本公开的一些实施例提供的显示装置中，第一晶体管110和第二晶体管120均采用可以降低或避免被高电压击穿风险的结构设计，关于第一晶体管110和第二晶体管120的具体结构可以参考图5和图6所示的实施例中的相应描述，这里不再赘述。
在本公开的实施例提供的显示装置中，通过使得第一晶体管110和第二晶体管120均采用可以降低或避免被高电压击穿风险的结构设计，可以改善或避免被高电压击穿的风险，从而提高该显示装置的可靠性和稳定性。
例如，在本公开的一些实施例提供的显示装置100中，衬底基板为P型硅衬底基板，第一晶体管110为P型MOS晶体管，第二晶体管120、第三晶体管130以及驱动晶体管140均为N型MOS晶体管。
本公开的至少一实施例还提供一种显示装置100的制备方法，该制备方法包括：在衬底基板上形成像素电路。
该像素电路包括驱动晶体管140、第一晶体管110以及第二晶体管120。
该驱动晶体管140包括控制极143、第一极141和第二极142，且被配置为，根据驱动晶体管140的控制极143的电压，控制流经驱动晶体管140的第一极141和驱动晶体管140的第二极142的用于驱动发光元件LE发光的驱动电流。
第一晶体管110连接到驱动晶体管140的控制极143，且被配置为响应于第一扫描信号SCAN1将数据信号DATA写入驱动晶体管140的控制极143。第二晶体管120连接到驱动晶体管140的控制极143，且被配置为响应于第二扫描信号SCAN2将数据信号DATA写入驱动晶体管140的控制极143。
上述衬底基板还包括可掺杂的半导体主体330；上述制备方法还包括：在半导体主体330上形成衬底基板的第一导电层310以及第二导电层320，第一晶体管110包括位于第一导电层310中的栅极GE1以及位于第二导电层320中的第一极DE1和第二极SE1。
上述制备方法还包括：在半导体主体330中形成与第一晶体管110的第一极DE1接触的第一晶体管110的第一掺杂区DR1以及与第一晶体管110 的第二极SE1接触的第一晶体管110的第二掺杂区SR1，第一晶体管110的第一掺杂区DR1与第一晶体管110的第二掺杂区SR1彼此间隔开、掺杂类型相同且都位于半导体主体330中。
上述制备方法还包括：在半导体主体330中形成与第一晶体管110的第二掺杂区SR1的掺杂类型相同的第一晶体管110的漂移掺杂区DF1；第一晶体管110的漂移掺杂区DF1位于半导体主体330中且与第一晶体管110的第二掺杂区SR1间隔开，第一晶体管110的栅极GE1在衬底基板上的正投影与第一晶体管110的漂移掺杂区DF1在衬底基板上的正投影部分重叠，并且第一晶体管110的第一掺杂区DR1在衬底基板上的正投影位于第一晶体管110的漂移掺杂区DF1在衬底基板上的正投影中，第一晶体管110的漂移掺杂区DF1的掺杂浓度低于第一晶体管110的第一掺杂区DR1的掺杂浓度。
上述制备方法还包括：在半导体主体330和第一导电层310之间形成衬底基板的第一绝缘层IS1。第一绝缘层IS1包括靠近第一晶体管110的第一掺杂区DR1的第一部分IS11以及远离第一晶体管110的第一掺杂区DR1的第二部分IS12；第一绝缘层IS1的第一部分IS11的厚度大于第一绝缘层IS1的第二部分IS12的厚度，厚度为沿与衬底基板垂直的方向上的厚度。
本公开的至少一实施例还提供一种显示装置100的制备方法，该制备方法包括：在衬底基板上形成像素电路。
该像素电路包括驱动晶体管140、第一晶体管110以及第二晶体管120。
该驱动晶体管140包括控制极143、第一极141和第二极142，且被配置为，根据驱动晶体管140的控制极143的电压，控制流经驱动晶体管140的第一极141和驱动晶体管140的第二极142的用于驱动发光元件LE发光的驱动电流。
第一晶体管110连接到驱动晶体管140的控制极143，且被配置为响应于第一扫描信号SCAN1将数据信号DATA写入驱动晶体管140的控制极143。第二晶体管120连接到驱动晶体管140的控制极143，且被配置为响应于第二扫描信号SCAN2将数据信号DATA写入驱动晶体管140的控制极143。
第一晶体管110包括第一有源区114，第二晶体管120包括第二有源区124，驱动晶体管140包括第四有源区144；上述制备方法还包括：对第一有源区114、第二有源区124以及第四有源区144进行掺杂以使得第一有源区 114以及第二有源区124中的至少一个的掺杂浓度大于第四有源区144的掺杂浓度。
上述像素电路还包括第三晶体管130，第三晶体管130连接到驱动晶体管140的第一极141，且被配置为响应于发光控制信号EN将第一电源电压ELVDD施加到驱动晶体管140的第一极141，第三晶体管130包括第三有源区134；上述制备方法还包括：对第三有源区134进行掺杂以使得第四有源区144的掺杂浓度小于第三有源区134的掺杂浓度。
需要说明的是，本公开的实施例提供的显示装置100的制备方法的技术效果可以参考上述关于显示装置100的实施例中的相应描述，这里不再赘述。
下面以图8所示的实施例为例描述本公开的实施例提供的显示装置100的制备方法。
如图8所示，首先提供一半导体主体330，然后，在该半导体主体330中进行N型掺杂以形成第一阱WL1；然后，在第一阱WL1中进行P型掺杂以形成第一晶体管110的漂移掺杂区DF1；然后，在第一晶体管110的漂移掺杂区DF1中进行P型掺杂以形成第一晶体管110的第一掺杂区DR1，该第一晶体管110的第一掺杂区DR1的掺杂浓度高于第一晶体管110的漂移掺杂区DF1的掺杂浓度；同时，在第一阱WL1中进行P型掺杂以形成第一晶体管110的第二掺杂区SR1，以及进行N型掺杂以形成第一晶体管110的辅助掺杂区BR。
然后，在半导体主体330的上面形成第一绝缘层IS1，并且使得第一绝缘层IS1的第一部分IS11的厚度大于第一绝缘层IS1的第二部分IS12的厚度；然后，在第一绝缘层IS1的上面形成第一导电层310，第一导电层310包括第一晶体管110的栅极GE1。
然后，形成平坦化绝缘层PL以覆盖第一晶体管110的栅极GE1；然后，在平坦化绝缘层PL中形成过孔以暴露第一晶体管的第一掺杂区DR1、第一晶体管110的第二掺杂区SR1以及第一晶体管110的辅助掺杂区BR。
最后，形成第二导电层320，第二导电层320包括通过上述平坦化绝缘层PL中的过孔和第一晶体管110的第一掺杂区DR1电连接的第一晶体管110的第一极DE1，以及通过上述平坦化绝缘层PL中的过孔和第一晶体管110的第二杂区SR1电连接的第一晶体管110的第二极SE1。
需要说明的是，关于第二晶体管120的制备方法和上述类似，这里不再 赘述。
本公开的至少一实施例还提供一种显示装置100，如图11所示，例如，该显示装置100包括显示面板，该显示面板包括设置在显示区域300中的呈阵列排布的多个像素单元PU，例如，该多个像素单元PU中的至少一个可以采用本公开的实施例提供的任一显示装置100中的像素电路。
例如，如图11所示，该显示装置100还包括制备在衬底基板中的驱动电路200，该驱动电路200被配置为向显示装置100中的多个像素单元PU中的像素电路提供第一扫描信号SCAN1、第二扫描信号SCAN2以及发光控制信号EN。例如，该驱动电路200设置在围绕显示区域300的周边区域400中。
例如，本公开的实施例提供的显示装置100可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种显示装置，包括衬底基板以及形成在所述衬底基板上的至少一个像素电路，其中，
    所述像素电路包括驱动晶体管、第一晶体管以及第二晶体管；
    所述驱动晶体管包括控制极、第一极和第二极，且被配置为，根据所述驱动晶体管的控制极的电压，控制流经所述驱动晶体管的第一极和所述驱动晶体管的第二极的用于驱动发光元件发光的驱动电流；
    所述第一晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第一扫描信号将数据信号写入所述驱动晶体管的控制极；
    所述第二晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第二扫描信号将所述数据信号写入所述驱动晶体管的控制极；
    其中，所述衬底基板包括可掺杂的半导体主体以及位于所述半导体主体之上的第一导电层以及第二导电层；
    所述第一晶体管包括与所述第一晶体管的第一极接触的第一掺杂区，与所述第一晶体管的第二极接触的第二掺杂区，所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；
    所述第一晶体管还包括与所述第一掺杂区接触的漂移掺杂区，所述第一晶体管的漂移掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；
    所述第一晶体管的栅极在所述衬底基板上的正投影与所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第一晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影中；
    所述第一晶体管的漂移掺杂区的掺杂浓度低于所述第一晶体管的第一掺杂区的掺杂浓度。
  2. 根据权利要求1所述的显示装置，其中，所述衬底基板还包括位于所述半导体主体和所述第一导电层之间的第一绝缘层；
    所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第二掺杂区的第二部分。
  3. 根据权利要求2所述的显示装置，其中，
    所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
  4. 一种显示装置，包括衬底基板以及形成在所述衬底基板上的至少一个像素电路，其中，
    所述像素电路包括驱动晶体管、第一晶体管以及第二晶体管；
    所述驱动晶体管包括控制极、第一极和第二极，且被配置为，根据所述驱动晶体管的控制极的电压，控制流经所述驱动晶体管的第一极和所述驱动晶体管的第二极的用于驱动发光元件发光的驱动电流；
    所述第一晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第一扫描信号将数据信号写入所述驱动晶体管的控制极；
    所述第二晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第二扫描信号将所述数据信号写入所述驱动晶体管的控制极；
    其中，所述衬底基板包括可掺杂的半导体主体以及形成在所述半导体主体的表面之上的第一导电层以及第二导电层；
    所述第一晶体管包括与所述第一晶体管的第一极接触的第一掺杂区，与所述第一晶体管的第二极接触的第二掺杂区，所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；
    所述衬底基板还包括形成在所述半导体主体和所述第一导电层之间的第一绝缘层，所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第二掺杂区的第二部分；
    所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
  5. 根据权利要求4所述的显示装置，其中，
    所述第一晶体管还包括与所述第一晶体管的第一掺杂区接触的漂移掺杂区，所述第一晶体管的漂移掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；
    所述第一晶体管的栅极在所述衬底基板上的正投影与所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第一晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第一晶体管的漂移掺杂区 在所述衬底基板上的正投影中；
    所述第一晶体管的漂移掺杂区的掺杂浓度低于所述第一晶体管的第一掺杂区的掺杂浓度。
  6. 根据权利要求1-5任一项所述的显示装置，其中，
    所述第一晶体管为P型MOS晶体管，所述第一晶体管的中的第一掺杂区的掺杂类型为P型；
    所述半导体主体为掺杂类型为P型的体硅或绝缘层上硅。
  7. 根据权利要求6所述的显示装置，其中，
    所述第一晶体管的第一掺杂区、第二掺杂区以及漂移掺杂区位于所述半导体主体中的第一阱中，所述第一阱的掺杂类型为N型；
    所述第一晶体管的栅极在所述衬底基板上的正投影位于所述第一阱在所述衬底基板上的正投影中，且所述第一阱位于所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区之间的部分构成所述第一晶体管的沟道区。
  8. 根据权利要求7所述的显示装置，其中，
    所述第一晶体管还包括辅助掺杂区，所述第一晶体管的辅助掺杂区的掺杂类型为N型，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二掺杂区接触，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二极电连接，
    且所述第一晶体管的辅助掺杂区在所述衬底基板上的正投影位于所述第一阱在所述衬底基板上的正投影中。
  9. 根据权利要求1-5任一项所述的显示装置，其中，
    所述第一晶体管为N型MOS晶体管，所述第一晶体管的中的第一掺杂区的掺杂类型为N型；
    所述半导体主体为掺杂类型为P型的体硅或绝缘层上硅。
  10. 根据权利要求9所述的显示装置，其中，
    所述第一晶体管还包括辅助掺杂区，所述第一晶体管的辅助掺杂区的掺杂类型为P型，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二掺杂区接触，所述辅助掺杂区与所述第一晶体管的第二极电连接。
  11. 根据权利要求1-10任一项所述的显示装置，其中，
    所述衬底基板还包括平坦化绝缘层，所述平坦化绝缘层覆盖所述第一晶体管的栅极，且所述发光元件位于所述平坦化绝缘层之上。
  12. 根据权利要求1-11任一项所述的显示装置，其中，
    所述第二晶体管包括与所述第二晶体管的第一极接触的第一掺杂区，与所述第二晶体管的第二极接触的第二掺杂区，所述第二晶体管的第一掺杂区与所述第二晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中。
  13. 根据权利要求12所述的显示装置，其中，
    所述第二晶体管还包括辅助掺杂区，所述第二晶体管的辅助掺杂区与所述第二晶体管的第二掺杂区接触，所述第二晶体管的辅助掺杂区与所述第二晶体管的第二极电连接，所述第二晶体管的辅助掺杂区的掺杂类型与所述第二晶体管的第二掺杂区的掺杂类型相反。
  14. 根据权利要求12或13所述的显示装置，其中，
    所述第一晶体管的第一掺杂区的掺杂类型与所述第二晶体管的第一掺杂区的掺杂类型相反。
  15. 根据权利要求1-5任一项所述的显示装置，其中，
    所述第一晶体管为P型MOS晶体管，所述第一晶体管的第一掺杂区的掺杂类型为P型，所述第二晶体管为N型MOS晶体管，所述第二晶体管的第一掺杂区的掺杂类型为N型；
    所述半导体主体为掺杂类型为P型的体硅或绝缘层上硅；
    所述第二晶体管包括与所述第二晶体管的第一极接触的第一掺杂区，与所述第二晶体管的第二极接触的第二掺杂区，所述第二晶体管的第一掺杂区与所述第二晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中。
  16. 根据权利要求15所述的显示装置，其中，
    所述第二晶体管还包括与所述第二晶体管的第一掺杂区接触的漂移掺杂区，所述第二晶体管的漂移掺杂区与所述第二晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；
    所述第二晶体管的栅极在所述衬底基板上的正投影与所述第二晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第二晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第二晶体管的漂移掺杂区在所述衬底基板上的正投影中；
    所述第二晶体管的漂移掺杂区的掺杂浓度低于所述第二晶体管的第一 掺杂区的掺杂浓度。
  17. 根据权利要求16所述的显示装置，其中，
    所述第一晶体管的第一掺杂区、第二掺杂区以及漂移掺杂区位于所述半导体主体中的第一阱中，所述第一阱的掺杂类型为N型，
    所述第一晶体管的栅极在所述衬底基板上的正投影位于所述第一阱在所述衬底基板上的正投影中，且所述第一阱位于所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区之间的部分构成所述第一晶体管的沟道区。
  18. 根据权利要求17所述的显示装置，其中，
    所述第一晶体管还包括辅助掺杂区，所述第一晶体管的辅助掺杂区的掺杂类型为N型，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二掺杂区接触，所述第一晶体管的辅助掺杂区与所述第一晶体管的第二极电连接，
    且所述第一晶体管的辅助掺杂区在所述衬底基板上的正投影位于所述第一阱在所述衬底基板上的正投影中；
    所述第二晶体管还包括辅助掺杂区，所述第二晶体管的辅助掺杂区的掺杂类型为P型，所述第二晶体管的辅助掺杂区与所述第二晶体管的第二掺杂区接触，所述第二晶体管的辅助掺杂区与所述第二晶体管的第二极电连接。
  19. 根据权利要求15-18任一项所述的显示装置，其中，
    所述衬底基板还包括形成在所述半导体主体和所述第一导电层之间的第一绝缘层与第二绝缘层；
    所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第一掺杂区的第二部分；
    所述第二绝缘层包括靠近所述第二晶体管的第一掺杂区的第一部分以及远离所述第二晶体管的第一掺杂区的第二部分。
  20. 根据权利要求19所述的显示装置，其中，
    所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，且所述第二绝缘层的第一部分的厚度大于所述第二绝缘层的第二部分的厚度，
    所述厚度为沿与所述衬底基板垂直的方向上的厚度。
  21. 根据权利要求1-20任一项所述的显示装置，其中，
    所述像素电路还包括第三晶体管，所述第三晶体管连接到所述驱动晶体 管的第一极，且被配置为响应于发光控制信号将第一电源电压施加到所述驱动晶体管的第一极。
  22. 根据权利要求21所述的显示装置，其中，
    所述衬底基板为P型硅衬底基板，所述第一晶体管为P型MOS晶体管，所述第二晶体管、所述第三晶体管以及所述驱动晶体管均为N型MOS晶体管。
  23. 根据权利要求22所述的显示装置，还包括位于所述衬底基板中的驱动电路，所述驱动电路被配置为向所述显示装置中的至少一个像素电路提供所述第一扫描信号、所述第二扫描信号以及所述发光控制信号。
  24. 一种显示装置的制备方法，包括：
    在衬底基板上形成像素电路，其中，
    所述像素电路包括驱动晶体管、第一晶体管以及第二晶体管；
    所述驱动晶体管包括控制极、第一极和第二极，且被配置为，根据所述驱动晶体管的控制极的电压，控制流经所述驱动晶体管的第一极和所述驱动晶体管的第二极的用于驱动发光元件发光的驱动电流；
    所述第一晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第一扫描信号将数据信号写入所述驱动晶体管的控制极；
    所述第二晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第二扫描信号将所述数据信号写入所述驱动晶体管的控制极；
    所述衬底基板包括可掺杂的半导体主体；
    所述制备方法还包括：
    在所述半导体主体上形成所述衬底基板的第一导电层以及第二导电层，其中，所述第一晶体管包括位于所述第一导电层中的栅极以及位于所述第二导电层中的第一极和第二极；
    在所述半导体主体中形成与所述第一晶体管的第一极接触的第一晶体管的第一掺杂区以及与所述第一晶体管的第二极接触的第一晶体管的第二掺杂区，所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；以及
    在所述半导体主体中形成与所述第一晶体管的第二掺杂区的掺杂类型相同的第一晶体管的漂移掺杂区，其中，所述第一晶体管的漂移掺杂区位于所述半导体主体中且与所述第一晶体管的第二掺杂区间隔开，所述第一晶体 管的栅极在所述衬底基板上的正投影与所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第一晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影中，所述第一晶体管的漂移掺杂区的掺杂浓度低于所述第一晶体管的第一掺杂区的掺杂浓度。
  25. 根据权利要求24所述的制备方法，还包括：在所述半导体主体和所述第一导电层之间形成所述衬底基板的第一绝缘层，其中，
    所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第一掺杂区的第二部分；
    所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
  26. 一种显示装置的制备方法，包括：
    在衬底基板上形成像素电路，其中，
    所述像素电路包括驱动晶体管、第一晶体管以及第二晶体管；
    所述驱动晶体管包括控制极、第一极和第二极，且被配置为，根据所述驱动晶体管的控制极的电压，控制流经所述驱动晶体管的第一极和所述驱动晶体管的第二极的用于驱动发光元件发光的驱动电流；
    所述第一晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第一扫描信号将数据信号写入所述驱动晶体管的控制极；
    所述第二晶体管的第一极连接到所述驱动晶体管的控制极，且被配置为响应于第二扫描信号将所述数据信号写入所述驱动晶体管的控制极；
    所述衬底基板包括可掺杂的半导体主体；
    所述制备方法还包括：
    在所述半导体主体上形成所述衬底基板的第一导电层以及第二导电层，其中，所述第一晶体管包括位于所述第一导电层中的栅极以及位于所述第二导电层中的第一极和第二极；
    在所述半导体主体中形成与所述第一晶体管的第一极接触的第一晶体管的第一掺杂区以及与所述第一晶体管的第二极接触的第一晶体管的第二掺杂区，所述第一晶体管的第一掺杂区与所述第一晶体管的第二掺杂区彼此间隔开、掺杂类型相同且都位于所述半导体主体中；以及
    在所述半导体主体和所述第一导电层之间形成所述衬底基板的第一绝 缘层，其中，所述第一绝缘层包括靠近所述第一晶体管的第一掺杂区的第一部分以及远离所述第一晶体管的第一掺杂区的第二部分；
    所述第一绝缘层的第一部分的厚度大于所述第一绝缘层的第二部分的厚度，所述厚度为沿与所述衬底基板垂直的方向上的厚度。
  27. 根据权利要求26所述的制备方法，还包括：在所述半导体主体中形成与所述第一晶体管的第二掺杂区的掺杂类型相同的第一晶体管的漂移掺杂区，其中，
    所述第一晶体管的漂移掺杂区位于所述半导体主体中且与所述第一晶体管的第二掺杂区间隔开，所述第一晶体管的栅极在所述衬底基板上的正投影与所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影部分重叠，并且所述第一晶体管的第一掺杂区在所述衬底基板上的正投影位于所述第一晶体管的漂移掺杂区在所述衬底基板上的正投影中，所述第一晶体管的漂移掺杂区的掺杂浓度低于所述第一晶体管的第一掺杂区的掺杂浓度。
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