WO2024000249A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2024000249A1
WO2024000249A1 PCT/CN2022/102292 CN2022102292W WO2024000249A1 WO 2024000249 A1 WO2024000249 A1 WO 2024000249A1 CN 2022102292 W CN2022102292 W CN 2022102292W WO 2024000249 A1 WO2024000249 A1 WO 2024000249A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
active layer
layer
gate
coupled
Prior art date
Application number
PCT/CN2022/102292
Other languages
English (en)
French (fr)
Inventor
李秋婕
侯唯玮
李栓柱
王文涛
史大为
巩伟兴
牛力强
Original Assignee
京东方科技集团股份有限公司
重庆京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002102.XA priority Critical patent/CN117642866A/zh
Priority to PCT/CN2022/102292 priority patent/WO2024000249A1/zh
Publication of WO2024000249A1 publication Critical patent/WO2024000249A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • AMOLED active matrix organic light-emitting diode
  • LTPO low temperature polycrystalline oxide
  • LTPS low temperature polysilicon
  • LTPS low temperature polysilicon
  • IGZO Metal oxide semiconductor
  • IGZO has a lower electron mobility than LTPS, and has the advantages of good uniformity, transparency, and simple manufacturing process.
  • IGZO has a relatively low leakage current, which can ensure stability at low refresh rates. Power consumption is also lower.
  • LTPO combines LTPS with metal oxide semiconductors to reduce the power consumption of screen display by reducing the energy consumption of exciting pixels.
  • the technical problem to be solved by this disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, which can improve the yield rate of the display substrate.
  • a display substrate including: a substrate and a plurality of sub-pixels disposed on the substrate.
  • the sub-pixels include a sub-pixel drive circuit and a light-emitting element.
  • the sub-pixel drive circuit includes:
  • the active layer structure of the first transistor includes a first active layer and a second active layer connected to the first active layer.
  • the second active layer is located away from the first active layer.
  • the first active layer includes a first active part and a second active part that are independent of each other, and the first active part and the second active part are respectively connected with the second active part. The two ends of the active layer are connected;
  • the first active layer and the second active layer are made of different materials, and the active layers of the first active layer and the second transistor are arranged in the same layer and made of the same material.
  • the first active layer is made of polysilicon
  • the second active layer uses a metal oxide semiconductor.
  • the first transistor further includes:
  • a gate located on the side of the second active layer facing the substrate
  • the gate electrode is located on a side of the first active layer away from the substrate.
  • the gate electrode of the first transistor and the gate electrode of the second transistor are arranged in the same layer and made of the same material.
  • the display substrate includes: the first active layer, the first gate insulating layer, the gate electrode, the second gate insulating layer and the second active layer located on the substrate in sequence.
  • the display substrate includes a groove penetrating the first gate insulating layer and the second gate insulating layer, and the second active layer is connected to the first active layer through the groove.
  • the display substrate further includes an interlayer insulating layer located on a side of the second active layer away from the substrate, and an orthographic projection of the interlayer insulating layer on the substrate covers the slot. an orthographic projection onto said substrate;
  • the source electrode and the drain electrode located on the side of the interlayer insulating layer away from the substrate, the source electrode and the drain electrode of the first transistor are connected to the first active layer through via holes penetrating the insulating layer, and the
  • the insulating layer is the interlayer insulating layer or the interlayer insulating layer, the first gate insulating layer and the second gate insulating layer;
  • the source and drain of the second transistor are connected to the active layer of the second transistor through via holes penetrating the interlayer insulating layer, the first gate insulating layer and the second gate insulating layer.
  • the orthographic projection of the via hole on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate;
  • the orthographic projection of the via hole on the substrate does not overlap with the orthographic projection of the slot on the substrate.
  • the display substrate includes multiple power lines, multiple light-emitting control lines, multiple gate lines, multiple data lines, multiple reset lines, and multiple initialization signal lines;
  • the sub-pixel driving circuit includes: a reset transistor, a first compensation transistor, a data writing transistor, an initialization transistor, a first luminescence control transistor, a second luminescence control transistor and a driving transistor;
  • the gate of the reset transistor is coupled to the corresponding reset line, the first electrode of the reset transistor is coupled to the corresponding initialization signal line, and the second electrode of the reset transistor is coupled to the gate of the driving transistor. coupling;
  • the gate of the compensation transistor is coupled to the corresponding gate line, the first electrode of the compensation transistor is coupled to the gate of the driving transistor, and the second electrode of the compensation transistor is coupled to the drain of the driving transistor. coupling;
  • the gate of the data writing transistor is coupled to the corresponding gate line, the first pole of the data writing transistor is coupled to the corresponding data line, and the second pole of the data writing transistor is coupled to the driving transistor.
  • the gate of the first light-emitting control transistor is coupled to the corresponding light-emitting control line, the first pole of the first light-emitting control transistor is coupled to the first pole of the light-emitting unit, and the first light-emitting control transistor has a
  • the second electrode is coupled to the drain of the driving transistor;
  • the gate of the second light-emitting control transistor is coupled to the corresponding light-emitting control line, the first electrode of the second light-emitting control transistor is coupled to the corresponding power line, and the second electrode of the second light-emitting control transistor is coupled to the corresponding power line.
  • the source of the driving transistor is coupled;
  • the gate electrode of the initialization transistor is coupled to the corresponding gate line
  • the first electrode of the initialization transistor is coupled to the corresponding initialization signal line
  • the second electrode of the initialization transistor is coupled to the first electrode of the light-emitting unit. Extremely coupled.
  • the first transistor includes the reset transistor, the compensation transistor, the data writing transistor and the initialization transistor;
  • the first transistor includes the reset transistor and the compensation transistor.
  • the orthographic projection of the first active layer of the first transistor on the substrate does not coincide with the orthographic projection of the gate line on the substrate.
  • connection line between the second electrode of the data writing transistor and the source electrode of the driving transistor includes a first connection part and a second connection part, and the first connection part is connected to the first connection part.
  • the active layer is arranged on the same layer and with the same material, and the second connection part is made of a source-drain metal layer. At the intersection of the connection line and the light-emitting control line, the first connection part is disconnected. The first connecting parts are connected through the second connecting parts.
  • An embodiment of the present disclosure also provides a display device, including the display substrate as described above.
  • Embodiments of the present disclosure also provide a method for manufacturing a display substrate, including: forming a plurality of sub-pixels on a substrate.
  • the sub-pixels include a sub-pixel driving circuit and a light-emitting element.
  • Forming the sub-pixel driving circuit includes:
  • the active layer structure of the first transistor includes a first active layer and a second active layer connected to the first active layer.
  • the second active layer is located away from the first active layer.
  • the first active layer includes a first active part and a second active part that are independent of each other, and the first active part and the second active part are respectively connected with the second active part. The two ends of the active layer are connected;
  • first active layer and the second active layer different materials are used to form the first active layer and the second active layer, and the first active layer and the active layer of the second transistor are formed through one patterning process.
  • the manufacturing method includes:
  • the second active layer is formed by wet etching.
  • the first active layer and the active layer of the second transistor are arranged in the same layer and with the same material.
  • the same patterning process can be used to form the via hole exposing the active layer of the second transistor.
  • Figure 1 is a schematic diagram of a display substrate in the prior art
  • FIGS. 2-9 are schematic cross-sectional views of display substrates according to embodiments of the present disclosure.
  • Figures 10a-10h are schematic diagrams showing the layout of a substrate according to an embodiment of the present disclosure.
  • Figures 11a-11h are schematic diagrams showing the layout of a substrate according to another embodiment of the present disclosure.
  • FIG. 12 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • the active layer of the LTPO thin film transistor is composed of polysilicon layer 01 and metal oxide semiconductor layer 09.
  • Polysilicon layer 01 and metal oxide semiconductor layer 09 are located in different film layers.
  • a via G1 that penetrates the first gate insulating layer 14, the first interlayer insulating layer 15, the second gate insulating layer 16 and the second interlayer insulating layer 17, exposing to expose the polysilicon layer 01; it is also necessary to form a via G2 that penetrates the second gate insulating layer 16 and the second interlayer insulating layer 17 to expose the metal oxide semiconductor layer 09; due to the different etching depths of the via G1 and the via G2 , it is easy to have uneven critical dimensions of via G1 and via G2, abnormal slope angle, etc., affecting product yield.
  • embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can improve the yield rate of the display substrate.
  • Embodiments of the present disclosure provide a display substrate, as shown in Figures 2 to 9, including: a substrate 13 and a plurality of sub-pixels provided on the substrate 13.
  • the sub-pixels include sub-pixel driving circuits and light-emitting elements,
  • the sub-pixel driving circuit includes:
  • first transistor B and a second transistor A, the second transistor A including only one active layer;
  • the active layer structure of the first transistor B includes a first active layer and a second active layer 10 connected to the first active layer.
  • the second active layer 10 is located on the first active layer.
  • the first active layer includes a first active portion 31 and a second active portion 32 that are independent of each other. The portions 32 are respectively connected to the two ends of the second active layer 10;
  • the first active layer and the second active layer 10 are made of different materials, and the active layers of the first active layer and the second transistor are arranged in the same layer and made of the same material.
  • the first active layer and the active layer of the second transistor are arranged in the same layer and with the same material. In this way, when forming a via hole exposing the active layer of the second transistor, the same patterning process can be used to form the exposed via hole.
  • Via holes in the first active layer are provided so that the source and drain electrodes of the subsequent first transistor are connected to the first active layer through the via holes. Since the first active layer and the active layer of the second transistor are in the same layer, the etching depths of the plurality of via holes exposing the first active layer are the same or substantially the same, which can avoid critical dimensions due to different via hole depths. Uneven, abnormal slope angle, etc., to ensure product yield.
  • the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array.
  • the plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits.
  • the multiple rows of sub-pixel driving circuits are arranged along a first direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction.
  • the multiple columns of sub-pixel driving circuits are arranged along the second direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction.
  • the first direction and the second direction intersect.
  • the first direction includes the longitudinal direction
  • the second direction includes the transverse direction.
  • the sub-pixel includes a sub-pixel driving circuit and a light-emitting element.
  • the sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element and drive the light-emitting element to emit light.
  • the above sub-pixel driving circuit can use 7T1C (that is, 7 transistors and a capacitor), but it is not limited to this.
  • the base 13 can be a flexible base or a hard base; when the base 13 is a flexible base, the base 13 is formed on the hard base 11.
  • a base 13 is provided between the base 13 and the hard base 11.
  • the buffer layer 12 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc. It can also be made of high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., and can be a single layer, multi-layer or composite layer.
  • the first active layer uses polysilicon
  • the second active layer uses a metal oxide semiconductor, such as amorphous indium gallium zinc oxide material a-IGZO, zinc oxynitride ZnON, indium zinc tin oxide IZTO, or IGZO.
  • the first transistor is an LTPO transistor. Through the LTPO transistor, the minimum refresh rate of the screen can be reached 1Hz. A lower refresh rate will bring lower power consumption, and a large amount of power can be saved by reducing the refresh rate.
  • the first active layer is not limited to polysilicon
  • the second active layer is not limited to metal oxide semiconductor, and other semiconductor materials can also be used.
  • the display substrate includes a first active layer, a first gate insulating layer 14 , a first gate metal layer 02 , a second gate insulating layer 18 , and a second gate metal layer 04 located on a substrate 13 and an interlayer insulating layer 20, wherein the first gate metal layer 02 is used to form the gate electrode of the second transistor A and the gate electrode of the first transistor B, and the second gate metal layer 04 is used to form a storage capacitor; the first active The layer includes a first active part 31 and a second active part 32 that are independent of each other.
  • the first active layer and the active layer of the second transistor A are arranged in the same layer and made of the same material, and are both made of polysilicon layer 01.
  • the second gate insulating layer 18 and the first gate insulating layer 14 are etched to expose the first active portion 31 and the second active portion 32
  • the slot 03 is formed; then, as shown in Figure 3, the second gate metal layer 04 is formed, and the second gate metal layer 04 is etched, as shown in Figure 4, to form the pattern of the second gate metal layer 04; after that, as shown in Figure 3
  • the second active layer 10 is formed; as shown in Figure 6, the second active layer 10 is etched to form a pattern of the second active layer 10, and the second active layer 10 is connected to the second active layer 10 through the groove 03.
  • the first active part 31 and the second active part 32 are connected respectively, and the second active layer 10 together with the first active part 31 and the second active part 32 constitute the active layer structure of the first transistor B.
  • the first active part 31 and the second active part 32 are arranged in the same layer and with the same material as the active layer of the second transistor A.
  • the second gate insulating layer 18 is formed.
  • the first gate insulating layer 14 is etched to form a via hole exposing the first active part 31 and the second active part 32, and then a gate electrode of the thin film transistor is formed, and then the second active layer 10 and the first active part 32 are formed.
  • the active part 31 and the second active part 32 are connected separately.
  • the gate electrode of the first transistor B and the gate electrode of the second transistor A are arranged in the same layer and made of the same material, and can be produced through one patterning process, which can reduce the number of patterning processes for producing the display substrate and reduce the production cost of the display substrate;
  • the first active part 31 and the second active part 32 are arranged in the same layer and with the same material as the active layer of the second transistor A, and can be produced through one patterning process, which can reduce the number of patterning processes for making the display substrate and reduce the cost of the display substrate. Production costs.
  • an interlayer insulating layer 20 is provided on the side of the second active layer 10 away from the substrate.
  • the interlayer insulating layer 20 can be silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiON. etc.
  • High k materials can also be used, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., which can be single layer, multi-layer or composite layer.
  • the orthographic projection of the interlayer insulating layer 20 on the substrate covers Orthographic projection of the slot on the substrate.
  • the interlayer insulating layer 20 is etched to form via holes 21, 22, 23 and 24, exposing the active layer of the second transistor A and the first active layer.
  • the source part 31 and the second active part 32 wherein the source of the second transistor A is connected to the polysilicon layer 01 through the via hole 21, the drain of the second transistor A is connected to the polysilicon layer 01 through the via hole 22, and the first transistor A
  • the source of transistor B is connected to the first active part 31 through the via hole 23
  • the drain of the first transistor B is connected to the second active part 32 through the via hole 24 .
  • the etching depths of the via holes 21 , 22 , 23 and 24 are basically the same, which can avoid the problem due to the depth of the via holes. Different key dimensions are uneven, the slope angle is abnormal, etc. to ensure product yield.
  • the orthographic projection of the via hole on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate.
  • the groove is on the substrate.
  • the orthographic projection on the substrate may be located within the orthographic projection of the via hole on the substrate, or the orthographic projection of the via hole on the substrate may not overlap with the orthographic projection of the slot on the substrate. , as long as the source and drain of the thin film transistor can be connected to the first active layer.
  • the orthographic projection of the via hole 23 and the via hole 24 on the substrate is located within the orthographic projection of the groove on the substrate, so that the interlayer insulating layer 20 is formed.
  • the first gate insulating layer 14 and the second gate insulating layer 18 in the area where the via hole 23 and the via hole 24 are located have been removed.
  • the via hole 23 and the via hole 24 Only the interlayer insulating layer needs to be penetrated; in the second transistor A, after the interlayer insulating layer 20 is formed, when the via holes are prepared, the via holes 21 and the via holes 22 need to penetrate the first gate insulating layer 14 and the second gate insulating layer 18 and the interlayer insulating layer 20. After the interlayer insulating layer 20 is prepared, the surface of the side of the interlayer insulating layer 20 away from the substrate is not completely flush. Therefore, the via hole 21 and the via hole 22 are not the same as the via hole 23 and the via hole. The etching depth of 24 cannot be exactly the same.
  • the position of the via hole of the first transistor can be designed, for example, the via hole 24 is in the The orthographic projection on the substrate does not overlap with the orthographic projection of the groove on the substrate, so that at the location of the via hole 24, the first gate insulating layer 14 and the second gate insulating layer 18 are still retained, and the via hole 24 It is necessary to penetrate the first gate insulating layer 14, the second gate insulating layer 18 and the interlayer insulating layer 20, so that the etching depth of the via hole 21, the via hole 22 and the via hole 24 can be basically the same.
  • the position of the via hole 23 can also be designed so that the orthographic projection of the via hole 23 on the substrate does not overlap with the orthographic projection of the slot on the substrate.
  • the display substrate includes multiple power lines Vdd, multiple light emission control lines EM, multiple gate lines Gate, multiple data lines Vdata, and multiple reset lines Reset. Multiple initialization signal lines Vinit;
  • the sub-pixel driving circuit includes: a reset transistor T1, a compensation transistor T2, a data writing transistor T4, an initialization transistor T7, a first light-emitting control transistor T5, a driving transistor T3 and a second light-emitting control transistor T6;
  • the gate of the reset transistor T1 is coupled to the corresponding reset line Reset, the first electrode of the reset transistor T1 is coupled to the corresponding initialization signal line Vinit, and the second electrode of the reset transistor T1 is coupled to the corresponding reset line Reset.
  • the gate of the driving transistor T3 is coupled;
  • the gate of the compensation transistor T2 is coupled to the corresponding gate line, the first electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the driving transistor T3.
  • the drain of transistor T3 is coupled;
  • the gate of the data writing transistor T4 is coupled to the corresponding gate line, the first pole of the data writing transistor T4 is coupled to the corresponding data line Vdata, and the second pole of the data writing transistor T4 is coupled to the corresponding gate line.
  • the source of the driving transistor T3 is coupled;
  • the gate of the first light-emitting control transistor T5 is coupled to the corresponding light-emitting control line EM, and the first pole of the first light-emitting control transistor T5 is coupled to the first pole 08 of the light-emitting unit.
  • the second electrode of the light emission control transistor T5 is coupled to the drain electrode of the driving transistor T3;
  • the gate of the second light-emitting control transistor T6 is coupled to the corresponding light-emitting control line EM, and the first electrode of the second light-emitting control transistor T6 is coupled to the corresponding power supply line Vdd.
  • the second light-emitting control transistor T6 The second electrode is coupled to the source of the driving transistor T3;
  • the gate of the initialization transistor T7 is coupled to the corresponding gate line, the first electrode of the initialization transistor T7 is coupled to the corresponding initialization signal line, and the second electrode of the initialization transistor T7 is coupled to the light-emitting unit.
  • the first pole 08 is coupled.
  • the display substrate may include four LTPO transistors, as shown in Figure 11h; the display substrate may also include two LTPO transistors, as shown in Figure 10h.
  • the first transistor includes the reset transistor T1, the compensation transistor T2, the data writing transistor T4 and the initialization transistor T7, that is, the reset transistor T1, the compensation transistor T2, the The data writing transistor T4 and the initialization transistor T7 are LTPO transistors, and the other transistors are second transistors; in Figure 10h, the first transistor includes the reset transistor T1 and the compensation transistor T2, that is, the reset transistor T1 and the compensation transistor T2 are LTPO transistors, and the other transistors are second transistors.
  • the pixel circuit structure shown in Figure 11h can reduce the number of gate lines compared to the pixel circuit structure shown in Figure 10h.
  • the orthographic projection of the first active layer of the first transistor is the same as the orthogonal projection of the gate line Gate1 on the substrate.
  • the projections do not overlap.
  • the orthographic projection of the first active layer of the first transistor, that is, the polysilicon layer 01 on the substrate does not coincide with the orthographic projection of the gate line Gate on the substrate. Since the orthographic projection of the slot 03 on the substrate is located within the orthographic projection of the first active part 31 and the second active part 32 on the substrate, the orthographic projection of the slot 03 on the substrate is in line with the first grid.
  • the orthographic projection of the metal layer 02 on the substrate does not overlap, and the second active layer 10 is filled in the slot 03 to form a semi-surrounding structure for the gate of the first transistor, forming a structure surrounding the gate of the first transistor.
  • the three-dimensional channel can increase the channel width of the thin film transistor and improve the width-to-length ratio of the thin film transistor channel through the structure of the three-dimensional channel surrounding the gate, thereby increasing the on-state current of the thin film transistor. At the same time, the three-dimensional channel surrounds the gate.
  • the structure of the gate strengthens the control of the gate's conductivity over the channel, effectively improving the operating stability of the thin film transistor; in addition, the structure of the three-dimensional channel surrounding the gate effectively reduces the area of the thin film transistor, which is beneficial to improving the performance of the thin film transistor.
  • the aperture ratio of the display device meets the high resolution requirements.
  • connection line between the second electrode of the data writing transistor T4 and the source electrode of the driving transistor T3 includes a first connection part and a second connection part, and the first connection part and the The first active layer is arranged in the same layer and with the same material, and the second connection part is made of a source-drain metal layer.
  • the first The connecting parts are disconnected, and the disconnected first connecting parts are connected through the second connecting parts.
  • An embodiment of the present disclosure also provides a display device, including the display substrate as described above.
  • the display device includes but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, a power supply and other components.
  • a radio frequency unit a radio frequency unit
  • a network module an audio output unit
  • an input unit a sensor
  • a display unit a user input unit
  • an interface unit a memory
  • a processor a power supply and other components.
  • display devices include but are not limited to monitors, mobile phones, tablet computers, televisions, wearable electronic devices, navigation display devices, and the like.
  • the display device may be any product or component with a display function such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc.
  • the display device further includes a flexible circuit board, a printed circuit board and a backplane.
  • Embodiments of the present disclosure also provide a method for manufacturing a display substrate, as shown in Figures 2 to 9, 10a to 10h, and 11a to 11h, including: forming a plurality of sub-pixels on a substrate, and the sub-pixels are The pixel includes a sub-pixel driving circuit and a light-emitting element. Forming the sub-pixel driving circuit includes:
  • the active layer structure of the first transistor B includes a first active layer and a second active layer 10 connected to the first active layer.
  • the second active layer 10 is located on the first active layer.
  • the first active layer includes a first active portion 31 and a second active portion 32 that are independent of each other. The portions 32 are respectively connected to the two ends of the second active layer 10;
  • first active layer and the second active layer different materials are used to form the first active layer and the second active layer, and the first active layer and the active layer of the second transistor are formed through one patterning process.
  • the first active layer and the active layer of the second transistor are formed through a patterning process.
  • the first active layer and the active layer of the second transistor are arranged in the same layer and with the same material. In this way, the first active layer and the active layer of the second transistor are formed.
  • the same patterning process can be used to form the via hole exposing the first active layer, so that the source and drain electrodes of the first transistor can subsequently communicate with the first active layer through the via hole. Source layer connection. Since the first active layer and the active layer of the second transistor are in the same layer, the etching depth of the via holes is the same or basically the same, which can avoid uneven critical dimensions and abnormal slope angles due to different depths of the via holes, ensuring that Product yield.
  • the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array.
  • the plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits.
  • the multiple rows of sub-pixel driving circuits are arranged along a first direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction.
  • the multiple columns of sub-pixel driving circuits are arranged along the second direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction.
  • the first direction and the second direction intersect.
  • the first direction includes the longitudinal direction
  • the second direction includes the transverse direction.
  • the sub-pixel includes a sub-pixel driving circuit and a light-emitting element.
  • the sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element and drive the light-emitting element to emit light.
  • the above-mentioned sub-pixel driving circuit can use 7T1C (that is, 7 transistors and a capacitor), but it is not limited to this.
  • the first active layer uses polysilicon
  • the second active layer uses a metal oxide semiconductor, such as amorphous indium gallium zinc oxide material a-IGZO, zinc oxynitride ZnON, indium zinc tin oxide IZTO, or IGZO.
  • the first transistor is an LTPO transistor. Through the LTPO transistor, the minimum refresh rate of the screen can be reached 1Hz. A lower refresh rate will bring lower power consumption, and a large amount of power can be saved by lowering the refresh rate.
  • the first active layer is not limited to polysilicon
  • the second active layer is not limited to metal oxide semiconductor, and other semiconductor materials can also be used.
  • the manufacturing method of this embodiment includes the following steps:
  • a hard substrate 11 is provided, and a buffer layer 12 and a substrate 13 are formed on the hard substrate 11.
  • the substrate 13 can be a flexible substrate and is made of polyimide;
  • the buffer layer 12 can be made of silicon oxide SiOx, Silicon nitride SiNx, silicon nitride oxide SiON, etc., can also use high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., which can be single layer, multi-layer or composite layer.
  • a pattern of the polysilicon layer 01 is formed.
  • the pattern of the polysilicon layer 01 includes the first active part 31 and the second active part 32 of the first transistor B, and also includes the active layer of the second transistor B.
  • Figure 2 is a schematic cross-sectional view of Figure 10a in the EE' direction.
  • the first gate insulating layer 14 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k material, such as aluminum oxide AlOx, Hafnium oxide HfOx, tantalum oxide TaOx, etc. can be single layer, multi-layer or composite layer.
  • forming the pattern of the first gate metal layer 02 includes: forming a metal film, patterning the metal film to form the pattern of the first gate metal layer 02, including the gate electrode of the first transistor B, the The gate electrode of the two transistors and the gate line Gate1.
  • the gate electrode of the first transistor B can be integrated with the gate line Gate1.
  • the metal film can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc.
  • Figure 2 is a schematic cross-sectional view in the EE' direction of Figure 10b.
  • a second gate insulating layer 18 is formed.
  • the second gate insulating layer 18 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of High k material, such as oxide Aluminum AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., can be single layer, multi-layer or composite layer.
  • the second gate insulating layer 18 is etched to form a groove 03 .
  • Figure 2 is a schematic cross-sectional view of Figure 10c in the EE' direction.
  • forming the pattern of the second gate metal layer 04 includes: forming a metal film, patterning the metal film to form the pattern of the second gate metal layer 04, which serves as a memory for the sub-pixel driving circuit.
  • the metal film can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc.
  • Fig. 4 is a schematic cross-sectional view in the EE' direction of Fig. 10b.
  • a layer of metal oxide semiconductor material is deposited to form a second active layer 10 .
  • the second active layer 10 may be IGZO.
  • the second active layer 10 is etched to form a pattern of the second active layer 10.
  • the second active layer 10 can be etched through a wet etching process.
  • the source layer 10 is etched, and the second active layer 10 is connected to the first active part 31 and the second active part 32 through the grooves 03 respectively.
  • Figure 6 is a schematic cross-sectional view of Figure 10e in the EE' direction.
  • an interlayer insulating layer 20 is formed.
  • the interlayer insulating layer 20 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., may be a single layer, multiple layers or composite layers, and the orthographic projection of the interlayer insulating layer 20 on the substrate covers the orthographic projection of the groove on the substrate.
  • the interlayer insulating layer 20 is etched to form a via hole 05.
  • the via hole 05 includes via holes 21-24, and the via hole 05 exposes the active layer of the thin film transistor.
  • Figures 8 and 9 are schematic cross-sectional views of Figure 10f in the EE' direction.
  • a pattern of the source-drain metal layer 06 is formed.
  • the pattern of the source-drain metal layer 06 includes the source and drain of the thin film transistor.
  • the source and drain of the thin film transistor are connected to the active terminal of the thin film transistor through the via hole 05. layer connection.
  • the first pole 08 of the light-emitting unit and the data line Vdata are formed.
  • the first pole 08 of the light-emitting unit may be the anode of the light-emitting unit.
  • the sub-pixel driving circuit includes: a reset transistor T1, a compensation transistor T2, a data writing transistor T4, an initialization transistor T7, a first light-emitting control transistor T5 and a second light-emitting control transistor T6;
  • the gate of the reset transistor T1 is coupled to the corresponding reset line Reset, the first electrode of the reset transistor T1 is coupled to the corresponding initialization signal line Vinit, and the second electrode of the reset transistor T1 is coupled to the corresponding reset line Reset.
  • the gate of the driving transistor T3 is coupled;
  • the gate of the compensation transistor T2 is coupled to the corresponding gate line, the first electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the driving transistor T3.
  • the drain of transistor T3 is coupled;
  • the gate of the data writing transistor T4 is coupled to the corresponding gate line, the first pole of the data writing transistor T4 is coupled to the corresponding data line Vdata, and the second pole of the data writing transistor T4 is coupled to the corresponding gate line.
  • the source of the driving transistor T3 is coupled;
  • the gate of the first light-emitting control transistor T5 is coupled to the corresponding light-emitting control line EM, and the first pole of the first light-emitting control transistor T5 is coupled to the first pole 08 of the light-emitting unit.
  • the second electrode of the light emission control transistor T5 is coupled to the drain electrode of the driving transistor T3;
  • the gate of the second light-emitting control transistor T6 is coupled to the corresponding light-emitting control line EM, and the first electrode of the second light-emitting control transistor T6 is coupled to the corresponding power supply line Vdd.
  • the second light-emitting control transistor T6 The second electrode is coupled to the source of the driving transistor T3;
  • the gate of the initialization transistor T7 is coupled to the corresponding gate line, the first electrode of the initialization transistor T7 is coupled to the corresponding initialization signal line, and the second electrode of the initialization transistor T7 is coupled to the light-emitting unit.
  • the first pole 08 is coupled.
  • the reset transistor T1 and the compensation transistor T2 are LTPO transistors, that is, the first transistors, and the other transistors are second transistors.
  • the manufacturing method of this embodiment includes the following steps:
  • a hard substrate 11 is provided, and a buffer layer 12 and a substrate 13 are formed on the hard substrate 11.
  • the substrate 13 can be a flexible substrate and is made of polyimide;
  • the buffer layer 12 can be made of silicon oxide SiOx, Silicon nitride SiNx, silicon nitride oxide SiON, etc., can also use high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., which can be single layer, multi-layer or composite layer.
  • a pattern of polysilicon layer 01 is formed.
  • the pattern of polysilicon layer 01 includes the first active part 31 and the second active part 32 of the first transistor B, and also includes the active layer of the second transistor.
  • Figure 2 is a schematic cross-sectional view of Figure 11a in the FF' direction.
  • the first gate insulating layer 14 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k material, such as aluminum oxide AlOx, Hafnium oxide HfOx, tantalum oxide TaOx, etc. can be single layer, multi-layer or composite layer.
  • forming the pattern of the first gate metal layer 02 includes: forming a metal film, patterning the metal film to form the pattern of the first gate metal layer 02, including the gate electrode of the first transistor B, the The gate electrode of the two transistors and the gate line Gate.
  • the gate electrode of the first transistor B can be integrated with the gate line Gate.
  • the metal film can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc.
  • Fig. 2 is a schematic cross-sectional view in the FF' direction of Fig. 11b.
  • a second gate insulating layer 18 is formed.
  • the second gate insulating layer 18 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of High k material, such as oxide Aluminum AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., can be single layer, multi-layer or composite layer.
  • the second gate insulating layer 18 is etched to form a groove 03 .
  • Fig. 2 is a schematic cross-sectional view in the FF' direction of Fig. 11c.
  • forming the pattern of the second gate metal layer 04 includes: forming a metal film, patterning the metal film to form the pattern of the second gate metal layer 04, which serves as a memory for the sub-pixel driving circuit.
  • the metal film can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc.
  • Figure 4 is a schematic cross-sectional view of Figure 11b in the FF' direction.
  • a layer of metal oxide semiconductor material is deposited to form a second active layer 10.
  • the second active layer 10 can be IGZO.
  • the second active layer 10 is etched to form a pattern of the second active layer 10.
  • the second active layer 10 can be etched through a wet etching process.
  • the source layer 10 is etched, and the second active layer 10 is connected to the first active part 31 and the second active part 32 through the grooves 03 respectively.
  • Fig. 6 is a schematic cross-sectional view of Fig. 11e in the FF' direction.
  • an interlayer insulating layer 20 is formed.
  • the interlayer insulating layer 20 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., may be a single layer, multiple layers or composite layers, and the orthographic projection of the interlayer insulating layer 20 on the substrate covers the orthographic projection of the groove on the substrate.
  • the interlayer insulating layer 20 is etched to form a via hole 05.
  • the via hole 05 includes via holes 21-24, and the via hole 05 exposes the active layer of the thin film transistor.
  • Figures 8 and 9 are schematic cross-sectional views of Figure 11f in the FF' direction.
  • a pattern of the source-drain metal layer 06 is formed.
  • the pattern of the source-drain metal layer 06 includes the source and drain of the thin film transistor.
  • the source and drain of the thin film transistor are connected to the active terminal of the thin film transistor through the via hole 05. layer connection.
  • the first pole 08 of the light-emitting unit and the data line Vdata are formed.
  • the first pole 08 of the light-emitting unit may be the anode of the light-emitting unit.
  • the sub-pixel driving circuit includes: a reset transistor T1, a compensation transistor T2, a data writing transistor T4, an initialization transistor T7, a first light-emitting control transistor T5 and a second light-emitting control transistor T6;
  • the gate of the reset transistor T1 is coupled to the corresponding reset line Reset, the first electrode of the reset transistor T1 is coupled to the corresponding initialization signal line Vinit, and the second electrode of the reset transistor T1 is coupled to the corresponding reset line Reset.
  • the gate of the driving transistor T3 is coupled;
  • the gate of the compensation transistor T2 is coupled to the corresponding gate line, the first electrode of the compensation transistor T2 is coupled to the gate of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the driving transistor T3.
  • the drain of transistor T3 is coupled;
  • the gate of the data writing transistor T4 is coupled to the corresponding gate line, the first pole of the data writing transistor T4 is coupled to the corresponding data line Vdata, and the second pole of the data writing transistor T4 is coupled to the corresponding gate line.
  • the source of the driving transistor T3 is coupled;
  • the gate of the first light-emitting control transistor T5 is coupled to the corresponding light-emitting control line EM, and the first pole of the first light-emitting control transistor T5 is coupled to the first pole 08 of the light-emitting unit.
  • the second electrode of the light emission control transistor T5 is coupled to the drain electrode of the driving transistor T3;
  • the gate of the second light-emitting control transistor T6 is coupled to the corresponding light-emitting control line EM, and the first electrode of the second light-emitting control transistor T6 is coupled to the corresponding power supply line Vdd.
  • the second light-emitting control transistor T6 The second electrode is coupled to the source of the driving transistor T3;
  • the gate of the initialization transistor T7 is coupled to the corresponding gate line, the first electrode of the initialization transistor T7 is coupled to the corresponding initialization signal line, and the second electrode of the initialization transistor T7 is coupled to the light-emitting unit.
  • the first pole 08 is coupled.
  • the reset transistor T1, the compensation transistor T2, the data writing transistor T4 and the initialization transistor T7 are LTPO transistors, that is, the first transistors, and the other transistors are the second transistors.
  • the first active layer of the first transistor that is, the polysilicon layer, and the active layer of the second transistor are arranged in the same layer and with the same material.
  • the via holes and the exposed first active layer can be formed through the same patterning process.
  • the etching depths of the via holes that expose the active layer of the second transistor, the multiple via holes that expose the first active layer, and the active layer that exposes the second transistor are the same or substantially the same, which can avoid problems due to the depth of the via holes. Different key dimensions are uneven, the slope angle is abnormal, etc. to ensure product yield.
  • Figure 12 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • the working process of the sub-pixel driving circuit may include:
  • the signal of the second scanning signal line S2 is a low-level signal, turning on the reset transistor T1, and the signal of the initialization signal line Vinit is provided to the second node N2 to initialize the storage capacitor C and clear the original data in the storage capacitor. Voltage.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, causing the compensation transistor T2, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the initialization transistor T7 to turn off.
  • the OLED does not emit light at this stage.
  • the driving transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low-level signal, which turns on the compensation transistor T2, the data writing transistor T4 and the initialization transistor T7.
  • the compensation transistor T2 and the data writing transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on driving transistor T3, the third node N3, and the turned-on compensation transistor T2. , and the difference between the data voltage output by the data signal line D and the threshold voltage of the driving transistor T3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the initialization transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, causing the reset transistor T1 to turn off.
  • the signal of the light-emitting signal line E is a high-level signal, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned off.
  • the signal of the light-emitting signal line E is a low-level signal, causing the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned on.
  • the power supply voltage output by the first power supply line VDD passes through the turned-on first light-emitting control transistor.
  • T5, the driving transistor T3 and the second light emitting control transistor T6 provide a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the driving transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the driving transistor T3
  • Vth is the threshold of the driving transistor T3.
  • Voltage is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本公开提供了一种显示基板及其制作方法、显示装置，属于显示技术领域。其中，显示基板，包括：基底和设置于所述基底上的多个子像素，所述子像素包括子像素驱动电路和发光元件，所述子像素驱动电路包括：第一晶体管和第二晶体管；所述第一晶体管的有源层结构包括第一有源层和与所述第一有源层连接的第二有源层，所述第二有源层位于所述第一有源层远离所述基底的一侧，所述第一有源层包括相互独立的第一有源部分和第二有源部分，所述第一有源部分和所述第二有源部分分别与所述第二有源层的两个端部连接；其中，所述第一有源层与所述第二有源层采用不同的材料，所述第一有源层与所述第二晶体管的有源层同层同材料设置。本公开的技术方案能够提高显示基板的良率。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，特别是指一种显示基板及其制作方法、显示装置。
背景技术
AMOLED(主动矩阵有机发光二极管)显示技术发展逐渐成熟，在对AMOLED显示屏显示效果要求逐渐增加的现状下，AMOLED产品对于功耗以及显示效果的需求逐渐增加，自适应性刷新率的产品属性成为了一大工艺目标，为实现低功耗与刷新率自适应的目标，产生了LTPO(低温多晶氧化物)技术。
LTPS(低温多晶硅)具备超高电子迁移率，而且还拥有高分辨率、高反应速度、高亮度、高开口率等优势，但是由于电子迁移率比较大，漏电电流也比较大，驱动功耗较大，不太适合低刷新率。金属氧化物半导体(IGZO)相比LTPS来说电子迁移率要低一些，具有均一性好、透明以及制作工艺简单等优点，而且IGZO的漏电电流比较下，能够保证低刷新率时的稳定性，功耗也更低。
LTPO便是将LTPS与金属氧化物半导体相结合，通过降低激发像素点的能耗，用来降低屏幕显示时的功耗。
发明内容
本公开要解决的技术问题是提供一种显示基板及其制作方法、显示装置，能够提高显示基板的良率。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种显示基板，包括：基底和设置于所述基底上的多个子像素，所述子像素包括子像素驱动电路和发光元件，所述子像素驱动电路包括：
第一晶体管和第二晶体管；
所述第一晶体管的有源层结构包括第一有源层和与所述第一有源层连接的第二有源层，所述第二有源层位于所述第一有源层远离所述基底的一侧，所述第一有源层包括相互独立的第一有源部分和第二有源部分，所述第一有源部分和所述第二有源部分分别与所述第二有源层的两个端部连接；
其中，所述第一有源层与所述第二有源层采用不同的材料，所述第一有源层与所述第二晶体管的有源层同层同材料设置。
一些实施例中，所述第一有源层采用多晶硅；
所述第二有源层采用金属氧化物半导体。
一些实施例中，所述第一晶体管还包括：
位于所述第二有源层朝向所述基底一侧的栅极；
所述栅极位于所述第一有源层远离所述基底的一侧。
一些实施例中，所述第一晶体管的栅极与所述第二晶体管的栅极同层同材料设置。
一些实施例中，所述显示基板包括依次位于所述基底上的：所述第一有源层、第一栅绝缘层、所述栅极、第二栅绝缘层和所述第二有源层，所述显示基板包括贯穿所述第一栅绝缘层和所述第二栅绝缘层的开槽，所述第二有源层通过所述开槽与所述第一有源层连接。
一些实施例中，所述显示基板还包括位于所述第二有源层远离所述基底一侧的层间绝缘层，所述层间绝缘层在所述基底上的正投影覆盖所述开槽在所述基底上的正投影；
位于所述层间绝缘层远离所述基底一侧的源极和漏极，所述第一晶体管的源极和漏极通过贯穿绝缘层的过孔与所述第一有源层连接，所述绝缘层为所述层间绝缘层或者所述层间绝缘层、所述第一栅绝缘层和所述第二栅绝缘层；
所述第二晶体管的源极和漏极通过贯穿所述层间绝缘层、所述第一栅绝缘层和所述第二栅绝缘层的过孔与所述第二晶体管的有源层连接。
一些实施例中，所述第一晶体管中，所述过孔在所述基底上的正投影与所述开槽在所述基底上的正投影至少部分交叠；或
所述过孔在所述基底上的正投影与所述开槽在所述基底上的正投影不重叠。
一些实施例中，所述显示基板包括多条电源线，多条发光控制线，多条栅线，多条数据线，多条复位线，多条初始化信号线；
所述子像素驱动电路包括：复位晶体管，第一补偿晶体管，数据写入晶体管，初始化晶体管，第一发光控制晶体管、第二发光控制晶体管和驱动晶体管；
所述复位晶体管的栅极与对应的复位线耦接，所述复位晶体管的第一极与对应的所述初始化信号线耦接，所述复位晶体管的第二极与所述驱动晶体管的栅极耦接；
所述补偿晶体管的栅极与对应的栅线耦接，所述补偿晶体管的第一极与所述驱动晶体管的栅极耦接，所述补偿晶体管的第二极与所述驱动晶体管的漏极耦接；
所述数据写入晶体管的栅极与对应的栅线耦接，所述数据写入晶体管的第一极与对应的数据线耦接，所述数据写入晶体管的第二极与所述驱动晶体管的源极耦接；
所述第一发光控制晶体管的栅极与对应的发光控制线耦接，所述第一发光控制晶体管的第一极与所述发光单元的第一极耦接，所述第一发光控制晶体管的第二极与所述驱动晶体管的漏极耦接；
所述第二发光控制晶体管的栅极与对应的发光控制线耦接，所述第二发光控制晶体管的第一极与对应的电源线耦接，所述第二发光控制晶体管的第二极与所述驱动晶体管的源极耦接；
所述初始化晶体管的栅极与对应的栅线耦接，所述初始化晶体管的第一极与对应的所述初始化信号线耦接，所述初始化晶体管的第二极与所述发光单元的第一极耦接。
一些实施例中，所述第一晶体管包括所述复位晶体管、所述补偿晶体管、所述数据写入晶体管和所述初始化晶体管；
或，
所述第一晶体管包括所述复位晶体管和所述补偿晶体管。
一些实施例中，所述第一晶体管的第一有源层在所述基底上的正投影与所述栅线在所述基底上的正投影不重合。
一些实施例中，所述数据写入晶体管的第二极与所述驱动晶体管的源极之间的连接线包括第一连接部分和第二连接部分，所述第一连接部分与所述第一有源层同层同材料设置，所述第二连接部分采用源漏金属层制作，在所述连接线与所述发光控制线的交叉位置处，所述第一连接部分断开，断开的第一连接部分之间通过所述第二连接部分连接。
本公开的实施例还提供了一种显示装置，包括如上所述的显示基板。
本公开的实施例还提供了一种显示基板的制作方法，包括：在基底上形成多个子像素，所述子像素包括子像素驱动电路和发光元件，形成所述子像素驱动电路包括：
形成第一晶体管和第二晶体管；
所述第一晶体管的有源层结构包括第一有源层和与所述第一有源层连接的第二有源层，所述第二有源层位于所述第一有源层远离所述基底的一侧，所述第一有源层包括相互独立的第一有源部分和第二有源部分，所述第一有源部分和所述第二有源部分分别与所述第二有源层的两个端部连接；
其中，采用不同的材料形成所述第一有源层与所述第二有源层，通过一次构图工艺形成所述第一有源层和所述第二晶体管的有源层。
一些实施例中，所述制作方法包括：
通过湿刻的方式形成所述第二有源层。
本公开的实施例具有以下有益效果：
上述方案中，第一有源层与第二晶体管的有源层同层同材料设置，这样在形成暴露出第二晶体管的有源层的过孔时，可以利用同一次构图工艺形成暴露出第一有源层的过孔，以便后续第一晶体管的源极和漏极通过过孔与第一有源层连接。由于第一有源层与第二晶体管的有源层同层，因此，暴露出第一有源层的多个过孔的刻蚀深度相同或基本相同，能够避免由于过孔深度不同的关键尺寸不均，坡度角异常等情况，保证产品良率。
附图说明
图1为现有技术显示基板的示意图；
图2-图9为本公开实施例显示基板的截面示意图；
图10a-图10h为本公开一实施例显示基板的布局示意图；
图11a-图11h为本公开另一实施例显示基板的布局示意图；
图12为本公开实施例子像素驱动电路的等效电路图。
附图标记
01多晶硅层
02第一栅金属层
04第二栅金属层
03开槽
05过孔
08发光单元的第一极
09金属氧化物半导体层
10第二有源层
11硬质基板
12缓冲层
13基底
14第一栅绝缘层
15第一层间绝缘层
16第二栅绝缘层
17第二层间绝缘层
18第二栅绝缘层
20层间绝缘层
21、22、23、24过孔
G1、G2过孔
31第一有源部分
32第二有源部分
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
如图1所示，LTPO技术的显示基板中，LTPO薄膜晶体管的有源层由多晶硅层01和金属氧化物半导体层09组成，多晶硅层01和金属氧化物半导体层09位于不同的膜层，为了连接多晶硅层01和金属氧化物半导体层09，需要形成贯穿第一栅绝缘层14、第一层间绝缘层15、第二栅绝缘层16和第二层间绝缘层17的过孔G1，暴露出多晶硅层01；还需要形成贯穿第二栅绝缘层16和第二层间绝缘层17的过孔G2，暴露出金属氧化物半导体层09；由于过孔G1和过孔G2的刻蚀深度不同，容易出现过孔G1和过孔G2的关键尺寸不均，坡度角异常等情况，影响产品良率。
为解决上述技术问题，本公开的实施例提供一种显示基板及其制作方法、显示装置，能够提高显示基板的良率。
本公开的实施例提供一种显示基板，如图2-图9所示，包括：基底13和设置于所述基底13上的多个子像素，所述子像素包括子像素驱动电路和发光元件，所述子像素驱动电路包括：
第一晶体管B和第二晶体管A，所述第二晶体管A仅包括一层有源层；
所述第一晶体管B的有源层结构包括第一有源层和与所述第一有源层连接的第二有源层10，所述第二有源层10位于所述第一有源层远离所述基底13的一侧，所述第一有源层包括相互独立的第一有源部分31和第二有源部分32，所述第一有源部分31和所述第二有源部分32分别与所述第二有源层10的两个端部连接；
其中，所述第一有源层与所述第二有源层10采用不同的材料，所述第一有源层与所述第二晶体管的有源层同层同材料设置。
本实施例中，第一有源层与第二晶体管的有源层同层同材料设置，这样在形成暴露出第二晶体管的有源层的过孔时，可以利用同一次构图工艺形成暴露出第一有源层的过孔，以便后续第一晶体管的源极和漏极通过过孔与第一有源层连接。由于第一有源层与第二晶体管的有源层同层，因此，暴露出第一有源层的多个过孔的刻蚀深度相同或基本相同，能够避免由于过孔深度 不同的关键尺寸不均，坡度角异常等情况，保证产品良率。
示例性的，所述显示基板包括多个子像素，所述多个子像素包括的多个子像素驱动电路呈阵列分布。所述多个子像素驱动电路划分为多行子像素驱动电路和多列子像素驱动电路。所述多行子像素驱动电路沿第一方向排列，每行子像素驱动电路包括沿第二方向排列的多个子像素驱动电路。所述多列子像素驱动电路沿第二方向排列，每列子像素驱动电路包括沿第一方向排列的多个子像素驱动电路。示例性的，所述第一方向和所述第二方向相交。例如：所述第一方向包括纵向，所述第二方向包括横向。
示例性的，所述子像素包括子像素驱动电路和发光元件。所述子像素驱动电路与所述发光元件的阳极耦接，用于为发光元件提供驱动信号，驱动发光元件发光。
示例性的，上述子像素驱动电路可以采用7T1C(即7个晶体管和一个电容)，但不仅限于此。
示例性的，基底13可以为柔性基底，也可以为硬质基底；在基底13为柔性基底时，基底13形成在硬质基板11上，另外，在基底13和硬质基板11之间还设置有缓冲层12，缓冲层12可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。
一些实施例中，所述第一有源层采用多晶硅，所述第二有源层采用金属氧化物半导体，比如非晶态氧化铟镓锌材料a-IGZO、氮氧化锌ZnON、氧化铟锌锡IZTO、或IGZO。即第一晶体管为LTPO晶体管，通过LTPO晶体管能够将屏幕最低刷新率做到1Hz，更低的刷新率会带来更低的功耗，通过降低刷新率来节省大量的电量。当然，第一有源层并不局限于采用多晶硅，第二有源层并不局限于采用金属氧化物半导体，还可以采用其他半导体材料。
如图8和图9所示，显示基板包括位于基底13上的第一有源层、第一栅绝缘层14、第一栅金属层02、第二栅绝缘层18、第二栅金属层04和层间绝缘层20，其中，第一栅金属层02用以形成第二晶体管A的栅极和第一晶体管B的栅极，第二栅金属层04用于形成存储电容；第一有源层包括相互独立的第一有源部分31和第二有源部分32，第一有源层与第二晶体管A的有源 层同层同材料设置，均采用多晶硅层01制作。
如图2所示，在形成第二栅绝缘层18后，对第二栅绝缘层18和第一栅绝缘层14进行刻蚀，形成暴露出第一有源部分31和第二有源部分32的开槽03；之后如图3所示，形成第二栅金属层04，对第二栅金属层04进行刻蚀，如图4所示，形成第二栅金属层04的图形；之后如图5所示，形成第二有源层10；如图6所示，对第二有源层10进行刻蚀，形成第二有源层10的图形，第二有源层10通过开槽03与第一有源部分31和第二有源部分32分别连接，第二有源层10与第一有源部分31和第二有源部分32共同组成第一晶体管B的有源层结构。
本实施例中，第一有源部分31和第二有源部分32与第二晶体管A的有源层同层同材料设置，在形成第二栅绝缘层18后，对第二栅绝缘层18和第一栅绝缘层14进行刻蚀，形成暴露出第一有源部分31和第二有源部分32的过孔，之后形成薄膜晶体管的栅极，再形成第二有源层10与第一有源部分31和第二有源部分32分别连接。其中，第一晶体管B的栅极和第二晶体管A的栅极同层同材料设置，可以通过一次构图工艺制作得到，能够减少制作显示基板的构图工艺的次数，降低显示基板的制作成本；第一有源部分31和第二有源部分32与第二晶体管A的有源层同层同材料设置，可以通过一次构图工艺制作得到，能够减少制作显示基板的构图工艺的次数，降低显示基板的制作成本。
如图7-图9所示，在第二有源层10远离基底的一侧设置有层间绝缘层20，层间绝缘层20可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层，所述层间绝缘层20在所述基底上的正投影覆盖所述开槽在所述基底上的正投影。
为了使得薄膜晶体管的源极和漏极与有源层连通，对层间绝缘层20进行刻蚀形成过孔21、22、23和24，暴露出第二晶体管A的有源层、第一有源部分31和第二有源部分32，其中，第二晶体管A的源极通过过孔21与多晶硅层01连接，第二晶体管A的漏极通过过孔22与多晶硅层01连接，第一晶体管B的源极通过过孔23与第一有源部分31连接，第一晶体管B的漏极 通过过孔24与第二有源部分32连接。由于第二晶体管的有源层、第一有源部分31和第二有源部分32位于同一层，因此，过孔21、22、23和24的刻蚀深度基本相同，能够避免由于过孔深度不同的关键尺寸不均，坡度角异常等情况，保证产品良率。
本实施例中，在第一晶体管B中，所述过孔在所述基底上的正投影与所述开槽在所述基底上的正投影至少部分交叠，比如所述开槽在所述基底上的正投影可以位于所述过孔在所述基底上的正投影内，或，所述过孔在所述基底上的正投影与所述开槽在所述基底上的正投影不重叠，只要能够实现薄膜晶体管的源极和漏极能够与第一有源层连接即可。
如图8所示，第一晶体管B中，过孔23和过孔24在所述基底上的正投影位于所述开槽在所述基底上的正投影内，这样在形成层间绝缘层20之前，过孔23和过孔24所在区域的第一栅绝缘层14和第二栅绝缘层18已经被去除，在形成层间绝缘层20后，制备过孔时，过孔23和过孔24仅需要贯穿层间绝缘层；而第二晶体管A中，在形成层间绝缘层20后，制备过孔时，过孔21和过孔22需要贯穿第一栅绝缘层14、第二栅绝缘层18和层间绝缘层20，在制备层间绝缘层20后，层间绝缘层20远离基底的一侧表面不是完全齐平的，因此，过孔21和过孔22与过孔23和过孔24的刻蚀深度不能做到完全相同。为了保证第二晶体管A的过孔与第一晶体管B的过孔的刻蚀深度基本相同，如图9所示，可以对第一晶体管的过孔的位置进行设计，比如过孔24在所述基底上的正投影与所述开槽在所述基底上的正投影不重叠，这样在过孔24所在位置处，第一栅绝缘层14和第二栅绝缘层18仍然被保留，过孔24需要贯穿第一栅绝缘层14、第二栅绝缘层18和层间绝缘层20，这样可以做到过孔21和过孔22与过孔24的刻蚀深度基本相同，同样，对于过孔23，也可以对过孔23的位置进行设计，使得过孔23在所述基底上的正投影与所述开槽在所述基底上的正投影不重叠。
一些实施例中，如图10h和图11h所示，所述显示基板包括多条电源线Vdd，多条发光控制线EM，多条栅线Gate，多条数据线Vdata，多条复位线Reset，多条初始化信号线Vinit；
所述子像素驱动电路包括：复位晶体管T1，补偿晶体管T2，数据写入 晶体管T4，初始化晶体管T7，第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6；
所述复位晶体管T1的栅极与对应的复位线Reset耦接，所述复位晶体管T1的第一极与对应的所述初始化信号线Vinit耦接，所述复位晶体管T1的第二极与所述驱动晶体管T3的栅极耦接；
所述补偿晶体管T2的栅极与对应的栅线耦接，所述补偿晶体管T2的第一极与所述驱动晶体管T3的栅极耦接，所述补偿晶体管T2的第二极与所述驱动晶体管T3的漏极耦接；
所述数据写入晶体管T4的栅极与对应的栅线耦接，所述数据写入晶体管T4的第一极与对应的数据线Vdata耦接，所述数据写入晶体管T4的第二极与所述驱动晶体管T3的源极耦接；
所述第一发光控制晶体管T5的栅极与对应的发光控制线EM耦接，所述第一发光控制晶体管T5的第一极与所述发光单元的第一极08耦接，所述第一发光控制晶体管T5的第二极与所述驱动晶体管T3的漏极耦接；
所述第二发光控制晶体管T6的栅极与对应的发光控制线EM耦接，所述第二发光控制晶体管T6的第一极与对应的电源线Vdd耦接，所述第二发光控制晶体管T6的第二极与所述驱动晶体管T3的源极耦接；
所述初始化晶体管T7的栅极与对应的栅线耦接，所述初始化晶体管T7的第一极与对应的所述初始化信号线耦接，所述初始化晶体管T7的第二极与所述发光单元的第一极08耦接。
本实施例中，显示基板可以包括四个LTPO晶体管，如图11h所示；显示基板也可以包括两个LTPO晶体管，如图10h所示。图11h中，所述第一晶体管包括所述复位晶体管T1、所述补偿晶体管T2、所述数据写入晶体管T4和所述初始化晶体管T7，即所述复位晶体管T1、所述补偿晶体管T2、所述数据写入晶体管T4和所述初始化晶体管T7为LTPO晶体管，其他晶体管为第二晶体管；图10h中，所述第一晶体管包括所述复位晶体管T1和所述补偿晶体管T2，即所述复位晶体管T1和所述补偿晶体管T2为LTPO晶体管，其他晶体管为第二晶体管。
其中，图11h所示的像素电路结构相比图10h所示的像素电路结构，可 以减少一根栅线的数量。
一些实施例中，如图10a、图10b所示，所述第一晶体管的第一有源层即多晶硅层01在所述基底上的正投影与所述栅线Gate1在所述基底上的正投影不重合。如图11a、图11b所示，所述第一晶体管的第一有源层即多晶硅层01在所述基底上的正投影与栅线Gate在所述基底上的正投影不重合。由于开槽03在基底上的正投影位于第一有源部分31和第二有源部分32在所述基底上的正投影内，这样开槽03在所述基底上的正投影与第一栅金属层02在所述基底上的正投影不重合，第二有源层10填充在开槽03内，能够形成对第一晶体管的栅极的半包围结构，形成包围第一晶体管的栅极的立体沟道，通过立体沟道包围栅极的结构，能够增加薄膜晶体管的沟道宽度，提高薄膜晶体管沟道的宽长比，进而增加薄膜晶体管的开态电流，同时，通过立体沟道包围栅极的结构，加强了栅极对沟道导电能力的控制，有效提高了薄膜晶体管的工作稳定性；另外，通过立体沟道包围栅极的结构，有效减小了薄膜晶体管的面积，有利于提高显示装置的开口率，满足高分辨率要求。
一些实施例中，所述数据写入晶体管T4的第二极与所述驱动晶体管T3的源极之间的连接线包括第一连接部分和第二连接部分，所述第一连接部分与所述第一有源层同层同材料设置，所述第二连接部分采用源漏金属层制作，为避免信号影响，在所述连接线与所述发光控制线EM的交叉位置处，所述第一连接部分断开，断开的第一连接部分之间通过所述第二连接部分连接。
本公开的实施例还提供了一种显示装置，包括如上所述的显示基板。
该显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
本公开的实施例还提供了一种显示基板的制作方法，如图2-图9、图10a-图10h、图11a-图11h所示，包括：在基底上形成多个子像素，所述子像素包括子像素驱动电路和发光元件，形成所述子像素驱动电路包括：
形成第一晶体管B和第二晶体管A；
所述第一晶体管B的有源层结构包括第一有源层和与所述第一有源层连接的第二有源层10，所述第二有源层10位于所述第一有源层远离所述基底13的一侧，所述第一有源层包括相互独立的第一有源部分31和第二有源部分32，所述第一有源部分31和所述第二有源部分32分别与所述第二有源层10的两个端部连接；
其中，采用不同的材料形成所述第一有源层与所述第二有源层，通过一次构图工艺形成所述第一有源层和所述第二晶体管的有源层。
本实施例中，通过一次构图工艺形成所述第一有源层和所述第二晶体管的有源层，第一有源层与第二晶体管的有源层同层同材料设置，这样在形成暴露出第二晶体管的有源层的过孔时，可以利用同一次构图工艺形成暴露出第一有源层的过孔，以便后续第一晶体管的源极和漏极通过过孔与第一有源层连接。由于第一有源层与第二晶体管的有源层同层，因此，过孔的刻蚀深度相同或基本相同，能够避免由于过孔深度不同的关键尺寸不均，坡度角异常等情况，保证产品良率。
示例性的，所述显示基板包括多个子像素，所述多个子像素包括的多个子像素驱动电路呈阵列分布。所述多个子像素驱动电路划分为多行子像素驱动电路和多列子像素驱动电路。所述多行子像素驱动电路沿第一方向排列，每行子像素驱动电路包括沿第二方向排列的多个子像素驱动电路。所述多列子像素驱动电路沿第二方向排列，每列子像素驱动电路包括沿第一方向排列的多个子像素驱动电路。示例性的，所述第一方向和所述第二方向相交。例如：所述第一方向包括纵向，所述第二方向包括横向。
示例性的，所述子像素包括子像素驱动电路和发光元件。所述子像素驱动电路与所述发光元件的阳极耦接，用于为发光元件提供驱动信号，驱动发光元件发光。
示例性的，上述子像素驱动电路可以采用7T1C(即7个晶体管和一个电 容)，但不仅限于此。
一些实施例中，所述第一有源层采用多晶硅，所述第二有源层采用金属氧化物半导体，比如非晶态氧化铟镓锌材料a-IGZO、氮氧化锌ZnON、氧化铟锌锡IZTO、或IGZO。这样第一晶体管为LTPO晶体管，通过LTPO晶体管能够将屏幕最低刷新率做到1Hz，更低的刷新率会带来更低的功耗，通过降低刷新率来节省大量的电量。当然，第一有源层并不局限于采用多晶硅，第二有源层并不局限于采用金属氧化物半导体，还可以采用其他半导体材料。
一具体示例中，如图2-图9、图10a-图10h所示，本实施例的制作方法包括以下步骤：
如图2所示，提供硬质基板11，在硬质基板11上形成缓冲层12和基底13，基底13可以为柔性基底，采用聚酰亚胺制作；缓冲层12可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。
如图2和图10a所示，形成多晶硅层01的图形，多晶硅层01的图形包括第一晶体管B的第一有源部分31和第二有源部分32，还包括第二晶体管的有源层，其中，图2为图10a在EE’方向上的截面示意图。
如图2所示，形成第一栅绝缘层14，第一栅绝缘层14可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。
如图2和图10b所示，形成第一栅金属层02的图形，包括：形成金属薄膜，对金属薄膜进行构图形成第一栅金属层02的图形，包括第一晶体管B的栅极、第二晶体管的栅极和栅线Gate1，其中，为了简化子像素驱动电路的结构，第一晶体管B的栅极可以与栅线Gate1为一体结构。金属薄膜可以采用金属材料，如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。其中，图2为图10b在EE’方向上的截面示意图。
如图2和图10c所示，形成第二栅绝缘层18，第二栅绝缘层18可以采用 硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。对第二栅绝缘层18进行刻蚀，形成开槽03。其中，图2为图10c在EE’方向上的截面示意图。
如图3、图4和图10d所示，形成第二栅金属层04的图形，包括：形成金属薄膜，对金属薄膜进行构图形成第二栅金属层04的图形，作为子像素驱动电路的存储电容的极板。金属薄膜可以采用金属材料，如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。其中，图4为图10b在EE’方向上的截面示意图。
如图5所示，沉积一层金属氧化物半导体材料，形成第二有源层10，第二有源层10可以采用IGZO。
如图6和图10e所示，对第二有源层10进行刻蚀，形成第二有源层10的图形，为了减少对第二栅金属层的影响，可以通过湿刻工艺对第二有源层10进行刻蚀，第二有源层10通过开槽03与第一有源部分31和第二有源部分32分别连接。其中，图6为图10e在EE’方向上的截面示意图。
如图7所示，形成层间绝缘层20，层间绝缘层20可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层，所述层间绝缘层20在所述基底上的正投影覆盖所述开槽在所述基底上的正投影。
如图8、图9和图10f所示，对层间绝缘层20进行刻蚀，形成过孔05，过孔05包括过孔21-24，过孔05暴露出薄膜晶体管的有源层。其中，图8、图9为图10f在EE’方向上的截面示意图。
如图10g所示，形成源漏金属层06的图形，源漏金属层06的图形包括薄膜晶体管的源极和漏极，薄膜晶体管的源极和漏极通过过孔05与薄膜晶体管的有源层连接。
如图10h所示，形成发光单元的第一极08和数据线Vdata，发光单元的 第一极08可以为发光单元的阳极。
本实施例中，子像素驱动电路包括：复位晶体管T1，补偿晶体管T2，数据写入晶体管T4，初始化晶体管T7，第一发光控制晶体管T5和第二发光控制晶体管T6；
所述复位晶体管T1的栅极与对应的复位线Reset耦接，所述复位晶体管T1的第一极与对应的所述初始化信号线Vinit耦接，所述复位晶体管T1的第二极与所述驱动晶体管T3的栅极耦接；
所述补偿晶体管T2的栅极与对应的栅线耦接，所述补偿晶体管T2的第一极与所述驱动晶体管T3的栅极耦接，所述补偿晶体管T2的第二极与所述驱动晶体管T3的漏极耦接；
所述数据写入晶体管T4的栅极与对应的栅线耦接，所述数据写入晶体管T4的第一极与对应的数据线Vdata耦接，所述数据写入晶体管T4的第二极与所述驱动晶体管T3的源极耦接；
所述第一发光控制晶体管T5的栅极与对应的发光控制线EM耦接，所述第一发光控制晶体管T5的第一极与所述发光单元的第一极08耦接，所述第一发光控制晶体管T5的第二极与所述驱动晶体管T3的漏极耦接；
所述第二发光控制晶体管T6的栅极与对应的发光控制线EM耦接，所述第二发光控制晶体管T6的第一极与对应的电源线Vdd耦接，所述第二发光控制晶体管T6的第二极与所述驱动晶体管T3的源极耦接；
所述初始化晶体管T7的栅极与对应的栅线耦接，所述初始化晶体管T7的第一极与对应的所述初始化信号线耦接，所述初始化晶体管T7的第二极与所述发光单元的第一极08耦接。
其中，复位晶体管T1和所述补偿晶体管T2为LTPO晶体管，也就是第一晶体管，其他晶体管为第二晶体管。
另一具体示例中，如图2-图9、图11a-图11h所示，本实施例的制作方法包括以下步骤：
如图2所示，提供硬质基板11，在硬质基板11上形成缓冲层12和基底13，基底13可以为柔性基底，采用聚酰亚胺制作；缓冲层12可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如 氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。
如图2和图11a所示，形成多晶硅层01的图形，多晶硅层01的图形包括第一晶体管B的第一有源部分31和第二有源部分32，还包括第二晶体管的有源层，其中，图2为图11a在FF’方向上的截面示意图。
如图2所示，形成第一栅绝缘层14，第一栅绝缘层14可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。
如图2和图11b所示，形成第一栅金属层02的图形，包括：形成金属薄膜，对金属薄膜进行构图形成第一栅金属层02的图形，包括第一晶体管B的栅极、第二晶体管的栅极和栅线Gate，其中，为了简化子像素驱动电路的结构，第一晶体管B的栅极可以与栅线Gate为一体结构。金属薄膜可以采用金属材料，如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。其中，图2为图11b在FF’方向上的截面示意图。
如图2和图11c所示，形成第二栅绝缘层18，第二栅绝缘层18可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。对第二栅绝缘层18进行刻蚀，形成开槽03。其中，图2为图11c在FF’方向上的截面示意图。
如图3、图4和图11d所示，形成第二栅金属层04的图形，包括：形成金属薄膜，对金属薄膜进行构图形成第二栅金属层04的图形，作为子像素驱动电路的存储电容的极板。金属薄膜可以采用金属材料，如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。其中，图4为图11b在FF’方向上的截面示意图。
如图5所示，沉积一层金属氧化物半导体材料，形成第二有源层10，第 二有源层10可以采用IGZO。
如图6和图11e所示，对第二有源层10进行刻蚀，形成第二有源层10的图形，为了减少对第二栅金属层的影响，可以通过湿刻工艺对第二有源层10进行刻蚀，第二有源层10通过开槽03与第一有源部分31和第二有源部分32分别连接。其中，图6为图11e在FF’方向上的截面示意图。
如图7所示，形成层间绝缘层20，层间绝缘层20可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层，所述层间绝缘层20在所述基底上的正投影覆盖所述开槽在所述基底上的正投影。
如图8、图9和图11f所示，对层间绝缘层20进行刻蚀，形成过孔05，过孔05包括过孔21-24，过孔05暴露出薄膜晶体管的有源层。其中，图8、图9为图11f在FF’方向上的截面示意图。
如图11g所示，形成源漏金属层06的图形，源漏金属层06的图形包括薄膜晶体管的源极和漏极，薄膜晶体管的源极和漏极通过过孔05与薄膜晶体管的有源层连接。
如图11h所示，形成发光单元的第一极08和数据线Vdata，发光单元的第一极08可以为发光单元的阳极。
本实施例中，子像素驱动电路包括：复位晶体管T1，补偿晶体管T2，数据写入晶体管T4，初始化晶体管T7，第一发光控制晶体管T5和第二发光控制晶体管T6；
所述复位晶体管T1的栅极与对应的复位线Reset耦接，所述复位晶体管T1的第一极与对应的所述初始化信号线Vinit耦接，所述复位晶体管T1的第二极与所述驱动晶体管T3的栅极耦接；
所述补偿晶体管T2的栅极与对应的栅线耦接，所述补偿晶体管T2的第一极与所述驱动晶体管T3的栅极耦接，所述补偿晶体管T2的第二极与所述驱动晶体管T3的漏极耦接；
所述数据写入晶体管T4的栅极与对应的栅线耦接，所述数据写入晶体管T4的第一极与对应的数据线Vdata耦接，所述数据写入晶体管T4的第二极 与所述驱动晶体管T3的源极耦接；
所述第一发光控制晶体管T5的栅极与对应的发光控制线EM耦接，所述第一发光控制晶体管T5的第一极与所述发光单元的第一极08耦接，所述第一发光控制晶体管T5的第二极与所述驱动晶体管T3的漏极耦接；
所述第二发光控制晶体管T6的栅极与对应的发光控制线EM耦接，所述第二发光控制晶体管T6的第一极与对应的电源线Vdd耦接，所述第二发光控制晶体管T6的第二极与所述驱动晶体管T3的源极耦接；
所述初始化晶体管T7的栅极与对应的栅线耦接，所述初始化晶体管T7的第一极与对应的所述初始化信号线耦接，所述初始化晶体管T7的第二极与所述发光单元的第一极08耦接。
其中，所述复位晶体管T1、所述补偿晶体管T2、所述数据写入晶体管T4和所述初始化晶体管T7为LTPO晶体管，也就是第一晶体管，其他晶体管为第二晶体管。
本实施例中，第一晶体管的第一有源层也就是多晶硅层与第二晶体管的有源层同层同材料设置，可以通过同一次构图工艺形成暴露出第一有源层的过孔和暴露出第二晶体管的有源层的过孔，暴露出第一有源层和暴露出第二晶体管的有源层的多个过孔的刻蚀深度相同或基本相同，能够避免由于过孔深度不同的关键尺寸不均，坡度角异常等情况，保证产品良率。
图12为本公开实施例子像素驱动电路的等效电路图，子像素驱动电路的工作过程可以包括：
复位阶段，第二扫描信号线S2的信号为低电平信号，使复位晶体管T1导通，初始化信号线Vinit的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使补偿晶体管T2、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和初始化晶体管T7断开，此阶段OLED不发光。
数据写入阶段或者阈值补偿阶段，此阶段由于存储电容C的第二端为低电平，因此驱动晶体管T3导通。第一扫描信号线S1的信号为低电平信号使补偿晶体管T2、数据写入晶体管T4和初始化晶体管T7导通。补偿晶体管 T2和数据写入晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的驱动晶体管T3、第三节点N3、导通的补偿晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与驱动晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为驱动晶体管T3的阈值电压。初始化晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使复位晶体管T1断开。发光信号线E的信号为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
发光阶段，发光信号线E的信号为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为驱动晶体管T3的栅电极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不 同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种显示基板，包括：基底和设置于所述基底上的多个子像素，所述子像素包括子像素驱动电路和发光元件，其特征在于，所述子像素驱动电路包括：
    第一晶体管和第二晶体管；
    所述第一晶体管的有源层结构包括第一有源层和与所述第一有源层连接的第二有源层，所述第二有源层位于所述第一有源层远离所述基底的一侧，所述第一有源层包括相互独立的第一有源部分和第二有源部分，所述第一有源部分和所述第二有源部分分别与所述第二有源层的两个端部连接；
    其中，所述第一有源层与所述第二有源层采用不同的材料，所述第一有源层与所述第二晶体管的有源层同层同材料设置。
  2. 根据权利要求1所述的显示基板，其特征在于，所述第一有源层采用多晶硅；
    所述第二有源层采用金属氧化物半导体。
  3. 根据权利要求2所述的显示基板，其特征在于，所述第一晶体管还包括：
    位于所述第二有源层朝向所述基底一侧的栅极；
    所述栅极位于所述第一有源层远离所述基底的一侧。
  4. 根据权利要求3所述的显示基板，其特征在于，所述第一晶体管的栅极与所述第二晶体管的栅极同层同材料设置。
  5. 根据权利要求3所述的显示基板，其特征在于，所述显示基板包括依次位于所述基底上的：所述第一有源层、第一栅绝缘层、所述栅极、第二栅绝缘层和所述第二有源层，所述显示基板包括贯穿所述第一栅绝缘层和所述第二栅绝缘层的开槽，所述第二有源层通过所述开槽与所述第一有源层连接。
  6. 根据权利要求5所述的显示基板，其特征在于，所述显示基板还包括位于所述第二有源层远离所述基底一侧的层间绝缘层，所述层间绝缘层在所述基底上的正投影覆盖所述开槽在所述基底上的正投影；
    位于所述层间绝缘层远离所述基底一侧的源极和漏极，所述第一晶体管 的源极和漏极通过贯穿绝缘层的过孔与所述第一有源层连接，所述绝缘层为所述层间绝缘层或者所述层间绝缘层、所述第一栅绝缘层和所述第二栅绝缘层；
    所述第二晶体管的源极和漏极通过贯穿所述层间绝缘层、所述第一栅绝缘层和所述第二栅绝缘层的过孔与所述第二晶体管的有源层连接。
  7. 根据权利要求6所述的显示基板，其特征在于，所述第一晶体管中，所述过孔在所述基底上的正投影与所述开槽在所述基底上的正投影至少部分交叠；或
    所述过孔在所述基底上的正投影与所述开槽在所述基底上的正投影不重叠。
  8. 根据权利要求1所述的显示基板，其特征在于，所述显示基板包括多条电源线，多条发光控制线，多条栅线，多条数据线，多条复位线，多条初始化信号线；
    所述子像素驱动电路包括：复位晶体管，补偿晶体管，数据写入晶体管，初始化晶体管，第一发光控制晶体管、第二发光控制晶体管和驱动晶体管；
    所述复位晶体管的栅极与对应的复位线耦接，所述复位晶体管的第一极与对应的所述初始化信号线耦接，所述复位晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述补偿晶体管的栅极与对应的栅线耦接，所述补偿晶体管的第一极与所述驱动晶体管的栅极耦接，所述补偿晶体管的第二极与所述驱动晶体管的漏极耦接；
    所述数据写入晶体管的栅极与对应的栅线耦接，所述数据写入晶体管的第一极与对应的数据线耦接，所述数据写入晶体管的第二极与所述驱动晶体管的源极耦接；
    所述第一发光控制晶体管的栅极与对应的发光控制线耦接，所述第一发光控制晶体管的第一极与所述发光单元的第一极耦接，所述第一发光控制晶体管的第二极与所述驱动晶体管的漏极耦接；
    所述第二发光控制晶体管的栅极与对应的发光控制线耦接，所述第二发光控制晶体管的第一极与对应的电源线耦接，所述第二发光控制晶体管的第 二极与所述驱动晶体管的源极耦接；
    所述初始化晶体管的栅极与对应的栅线耦接，所述初始化晶体管的第一极与对应的所述初始化信号线耦接，所述初始化晶体管的第二极与所述发光单元的第一极耦接。
  9. 根据权利要求8所述的显示基板，其特征在于，所述第一晶体管包括所述复位晶体管、所述补偿晶体管、所述数据写入晶体管和所述初始化晶体管；
    或，
    所述第一晶体管包括所述复位晶体管和所述补偿晶体管。
  10. 根据权利要求9所述的显示基板，其特征在于，所述第一晶体管的第一有源层在所述基底上的正投影与所述栅线在所述基底上的正投影不重合。
  11. 根据权利要求9所述的显示基板，其特征在于，
    所述数据写入晶体管的第二极与所述驱动晶体管的源极之间的连接线包括第一连接部分和第二连接部分，所述第一连接部分与所述第一有源层同层同材料设置，所述第二连接部分采用源漏金属层制作，在所述连接线与所述发光控制线的交叉位置处，所述第一连接部分断开，断开的第一连接部分之间通过所述第二连接部分连接。
  12. 一种显示装置，其特征在于，包括如权利要求1-11中任一项所述的显示基板。
  13. 一种显示基板的制作方法，包括：在基底上形成多个子像素，所述子像素包括子像素驱动电路和发光元件，其特征在于，形成所述子像素驱动电路包括：
    形成第一晶体管和第二晶体管；
    所述第一晶体管的有源层结构包括第一有源层和与所述第一有源层连接的第二有源层，所述第二有源层位于所述第一有源层远离所述基底的一侧，所述第一有源层包括相互独立的第一有源部分和第二有源部分，所述第一有源部分和所述第二有源部分分别与所述第二有源层的两个端部连接；
    其中，采用不同的材料形成所述第一有源层与所述第二有源层，通过一 次构图工艺形成所述第一有源层和所述第二晶体管的有源层。
  14. 根据权利要求13所述的显示基板的制作方法，其特征在于，所述制作方法包括：
    通过湿刻的方式形成所述第二有源层。
PCT/CN2022/102292 2022-06-29 2022-06-29 显示基板及其制作方法、显示装置 WO2024000249A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202280002102.XA CN117642866A (zh) 2022-06-29 2022-06-29 显示基板及其制作方法、显示装置
PCT/CN2022/102292 WO2024000249A1 (zh) 2022-06-29 2022-06-29 显示基板及其制作方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/102292 WO2024000249A1 (zh) 2022-06-29 2022-06-29 显示基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2024000249A1 true WO2024000249A1 (zh) 2024-01-04

Family

ID=89383429

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/102292 WO2024000249A1 (zh) 2022-06-29 2022-06-29 显示基板及其制作方法、显示装置

Country Status (2)

Country Link
CN (1) CN117642866A (zh)
WO (1) WO2024000249A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103456744A (zh) * 2013-09-05 2013-12-18 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置
CN106298857A (zh) * 2016-08-31 2017-01-04 深圳市华星光电技术有限公司 一种有机发光显示装置及其制造方法
CN107978610A (zh) * 2017-11-30 2018-05-01 上海天马微电子有限公司 一种阵列基板、显示面板、显示装置及阵列基板的制造方法
CN110060998A (zh) * 2019-04-29 2019-07-26 厦门天马微电子有限公司 一种反相电路结构、栅极驱动电路及显示面板
CN114388533A (zh) * 2020-10-20 2022-04-22 乐金显示有限公司 薄膜晶体管阵列基板及包含其的电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103456744A (zh) * 2013-09-05 2013-12-18 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置
CN106298857A (zh) * 2016-08-31 2017-01-04 深圳市华星光电技术有限公司 一种有机发光显示装置及其制造方法
CN107978610A (zh) * 2017-11-30 2018-05-01 上海天马微电子有限公司 一种阵列基板、显示面板、显示装置及阵列基板的制造方法
CN110060998A (zh) * 2019-04-29 2019-07-26 厦门天马微电子有限公司 一种反相电路结构、栅极驱动电路及显示面板
CN114388533A (zh) * 2020-10-20 2022-04-22 乐金显示有限公司 薄膜晶体管阵列基板及包含其的电子设备

Also Published As

Publication number Publication date
CN117642866A (zh) 2024-03-01

Similar Documents

Publication Publication Date Title
US20220310010A1 (en) Display substrate and display device
WO2020198975A1 (zh) 显示基板及其制备方法、显示面板
CN109326624B (zh) 像素电路、其制造方法及显示装置
JP2021524926A (ja) 表示パネルおよび表示装置
US11437457B2 (en) Display substrate and display device
WO2022267531A1 (zh) 显示基板及其制备方法、显示面板
US11957008B2 (en) Display substrate and display device
US10916613B1 (en) Array substrate and OLED display device
US20230097504A1 (en) Display substrate and display device
US10008517B2 (en) Display device having reduced parasitic capacitance and cross-talk and method of manufacturing the same
JP2022539621A (ja) ディスプレイパネル及びその製造方法、表示装置
CN113035925A (zh) 显示面板及显示装置
US20240153461A1 (en) Display Apparatus with Compensation and Driving Method therefor
CN110010060B (zh) 垂直堆叠晶体管和包括垂直堆叠晶体管的显示设备
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
WO2022156039A1 (zh) 显示面板及显示装置
US20230154401A1 (en) Display panel and display device
WO2024000249A1 (zh) 显示基板及其制作方法、显示装置
WO2021207930A9 (zh) 显示基板及显示装置
CN114361185A (zh) 显示面板及其制备方法、显示装置
CN113450715A (zh) 显示基板及其制备方法、显示装置
WO2023016341A1 (zh) 显示基板及其制备方法、显示装置
US11980060B2 (en) Pixel circuit having increased capacitance and display device including the same
WO2023040356A1 (zh) 显示基板和显示装置
WO2024060127A1 (zh) 显示基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22948367

Country of ref document: EP

Kind code of ref document: A1