WO2022156039A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022156039A1
WO2022156039A1 PCT/CN2021/078086 CN2021078086W WO2022156039A1 WO 2022156039 A1 WO2022156039 A1 WO 2022156039A1 CN 2021078086 W CN2021078086 W CN 2021078086W WO 2022156039 A1 WO2022156039 A1 WO 2022156039A1
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WIPO (PCT)
Prior art keywords
sub
dummy
display panel
hole
holes
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PCT/CN2021/078086
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English (en)
French (fr)
Inventor
杨程
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/287,170 priority Critical patent/US11963398B2/en
Publication of WO2022156039A1 publication Critical patent/WO2022156039A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • the under-screen camera Camera Under Panel, CUP
  • the driving circuit that drives the pixels in the CUP area to emit light is placed on the periphery of the CUP area.
  • the density difference of the driving circuit settings and the electrical difference of the transistors used in each driving circuit will cause the pixels in the CUP area to receive the same driving signal.
  • Embodiments of the present application provide a display panel and a display device, which can reduce electrical differences between sub-pixel driving circuits, thereby improving the display uniformity of the display panel.
  • An embodiment of the present application provides a display panel, the display panel includes a display light-transmitting area and a transition display area located at the periphery of the display light-transmitting area, the display panel includes a plurality of auxiliary pixel driving circuits and a plurality of auxiliary sub-regions pixel.
  • a plurality of the sub-pixel driving circuits are located in the transition display area, and a plurality of the sub-pixels are located in the display light-transmitting area, and are electrically connected to the sub-pixel driving circuits.
  • Each of the sub-pixel driving circuits includes a transistor including an active layer and an insulating layer on the active layer.
  • the display panel is provided with a first dummy hole in the transition display area, and the first dummy hole penetrates a part of the insulating layer away from the active layer.
  • the display panel further includes a plurality of pixel circuit drive islands located in the transition display area, each of the pixel circuit drive islands includes a plurality of the sub-pixel drive circuits, the first dummy The hole includes a plurality of first sub-dummy holes, and each of the first sub-dummy holes is located between corresponding two adjacent pixel circuit driving islands.
  • each pixel circuit driving island has a length direction
  • each sub-pixel driving circuit has a first length in the length direction
  • a plurality of pixel circuit driving islands located between adjacent two pixel circuit driving islands
  • the first sub-virtual hole has a second length; wherein, the second length is greater than the first length, and the second length is equal to the first sub-virtual hole located at the head end of the plurality of first sub-virtual holes The distance between the virtual hole and the first sub-virtual hole located at the end in the length direction.
  • the second length is greater than or equal to 2 times the first length.
  • the first dummy hole includes a plurality of second sub-dummy holes located on a side of the pixel circuit driving island close to the display light-transmitting area.
  • the number of rows and/or columns of the plurality of second sub-virtual holes is greater than or equal to four.
  • the display panel further includes a main display area located on a side of the transition display area away from the display light-transmitting area, and the first dummy hole includes a main display area located on a side of the pixel circuit driving island close to all the display light-transmitting areas. a plurality of third sub-virtual holes on one side of the main display area.
  • the display panel further includes a plurality of main sub-pixels located in the main display area and a plurality of main pixel driving circuits for driving the plurality of main sub-pixels to emit light; wherein, each of the main pixel driving circuits A plurality of via holes are provided, and in a top view, the arrangement manner of the plurality of first dummy holes is the same as that of the plurality of via holes, or the plurality of first dummy holes are arranged in a matrix.
  • the display panel is further provided with a second dummy hole located in the transition display area, and the second dummy hole is located on a side of the pixel circuit driving island close to the display light-transmitting area, The second dummy hole penetrates the insulating layer, and the diameter of the second dummy hole is larger than that of the first dummy hole.
  • the display panel is further provided with a third dummy hole located in the transition display area, the third dummy hole penetrates the insulating layer, and the depth of the third dummy hole is greater than or less than that of the the depth of the first virtual hole.
  • the transistor further includes: a first insulating layer, a first electrode layer, a second insulating layer, and a second electrode layer.
  • the first insulating layer is located on the active layer; the first electrode layer is located on the first insulating layer, and the first electrode layer includes a first wiring part and is aligned with the active layer the first electrode part provided; the second insulating layer is located on the first electrode layer; the second electrode layer is located on the second insulating layer, and the second electrode layer includes a second wiring part and a second electrode portion electrically connected to the active layer.
  • the insulating layer includes the first insulating layer and the second insulating layer, and the first dummy hole does not penetrate through the active layer, the first electrode layer and the second electrode layer.
  • the display panel further includes a flat layer on a side of the insulating layer away from the active layer, and the flat layer includes a filling portion in the first dummy hole.
  • the diameter of the first virtual hole is greater than or equal to 2 micrometers and less than or equal to 3.5 micrometers, and the distance between two adjacent virtual holes is greater than or equal to 2 micrometers and less than or equal to 5 micrometers .
  • the diameter of the second virtual hole is greater than or equal to 4 micrometers and less than or equal to 7 micrometers, and the difference between the diameters of the second virtual hole and the first virtual hole is greater than or equal to 1 micrometer and less than or equal to 1 micrometer. or equal to 4.5 microns.
  • the auxiliary sub-pixels include organic light emitting diodes, micro light emitting diodes, sub-millimeter light emitting diodes.
  • the first virtual pores are prepared after dehydrogenation.
  • Embodiments of the present application further provide a display device including any of the above-mentioned display panels.
  • an embodiment of the present application provides a display panel and a display device
  • the display panel includes a display light-transmitting area and a transition display area located at the periphery of the display light-transmitting area
  • the display panel includes A plurality of auxiliary pixel driving circuits and a plurality of auxiliary sub-pixels.
  • a plurality of the sub-pixel driving circuits are located in the transition display area, and a plurality of the sub-pixels are located in the display light-transmitting area, and are electrically connected to the sub-pixel driving circuits.
  • Each of the sub-pixel driving circuits includes a transistor including an active layer and an insulating layer on the active layer.
  • the display panel is provided with a first dummy hole in the transition display area, and the first dummy hole penetrates a part of the insulating layer away from the active layer, so as to be lowered by the first dummy hole
  • the electrical property difference between a plurality of sub-pixel driving circuits improves the uniformity of the electrical properties of the sub-pixel driving circuits, thereby realizing uniform display of the display panel.
  • FIGS. 1A to 1C are schematic structural diagrams of a display panel according to an embodiment of the present application.
  • Fig. 1D is a partial enlarged view of A in Fig. 1A;
  • FIG. 1E is a schematic structural diagram of a pixel circuit driving island provided by an embodiment of the present application.
  • FIGS. 1F to 1G are schematic structural diagrams of a first sub-virtual hole and a pixel circuit driving island provided by an embodiment of the present application;
  • 1H is a schematic structural diagram of a first sub-virtual hole and a sub-pixel driving circuit according to an embodiment of the present application
  • FIGS. 2A to 2C are schematic diagrams of the arrangement of virtual holes according to embodiments of the present application.
  • FIG. 4 is a schematic diagram of providing a virtual hole to improve the electrical performance of a transistor according to an embodiment of the present application.
  • Table 1 provides a result verification table for setting virtual holes provided in the embodiments of the present application.
  • FIGS. 1A to 1C are schematic structural diagrams of a display panel provided by an embodiment of the present application; and FIG. 1D , which is a partial enlarged view of part A in FIG. 1A .
  • An embodiment of the present application provides a display panel, the display panel includes a display light-transmitting area 100b and a transition display area 100a located at the periphery of the display light-transmitting area 100b.
  • the display panel includes a plurality of auxiliary pixel driving circuits 101 and a plurality of auxiliary sub-pixels 103 .
  • a plurality of the sub-pixel driving circuits 101 are located in the transition display area 100a, a plurality of the sub-pixels 103 are located in the transition display area 100a and the display light-transmitting area 100b, and the sub-pixel driving circuits 101 is electrically connected to the auxiliary sub-pixel 103, and the auxiliary pixel driving circuit 101 is used for driving at least one of the auxiliary sub-pixels 103 to emit light.
  • the display panel includes a self-luminous display panel
  • the auxiliary sub-pixels 103 include at least one of organic light emitting diodes, micro light emitting diodes, and sub-millimeter light emitting diodes.
  • Each of the sub-pixel driving circuits 101 includes a plurality of transistors 102 , and each of the transistors 102 includes an active layer 1021 and an insulating layer 1022 on the active layer 1021 .
  • the display panel is provided with a plurality of dummy holes 200 in the transition display area 100a, and the dummy holes 200 penetrate through the part of the insulating layer 1022 away from the active layer 1021 to pass through the dummy holes 200 improves the electrical uniformity of the auxiliary pixel driving circuit 101, thereby realizing uniform display of the display panel.
  • the transistor 102 is a current-driven device. Further, the transistor 102 includes a thin film transistor.
  • the active layer 1021 includes a silicon active layer; further, the active layer 1021 includes a low temperature polysilicon active layer.
  • the transistor 102 includes a P-type transistor and an N-type transistor.
  • the defect density at the interface between the active layer 1021 and the insulating layer 1022 will affect the electrical properties such as threshold voltage and sub-threshold swing of the transistor 102 . Therefore, when the transistor 102 is a current-driven device, the larger the absolute value of the threshold voltage of the transistor 102 is, the larger the sub-threshold swing of the transistor 102 is, and the fluctuation of the gate-source voltage of the transistor 102 is convection. The effect of the current passing through the source and drain of the transistor 102 is smaller, so that the transistor 102 can provide a more stable driving current to the sub-sub-pixel 103, so that the luminance of the sub-sub-pixel 103 can be improved. The fluctuation is smaller, which is beneficial to improve the display uniformity of the display panel.
  • Disposing the dummy hole 200 in the transition display area 100a can increase the defect density at the interface between the active layer 1021 and the insulating layer 1022, thereby increasing the subthreshold swing of the transistor 102 and reducing the
  • the fluctuation of the gate-source voltage of the transistor 102 affects the current flowing through the source and drain of the transistor 102, so as to avoid that the sub-threshold swing of the transistor 102 is small when the display panel is driven by a low gray scale.
  • the driving current for driving the auxiliary sub-pixel 103 to emit light is sensitive to the fluctuation of the gate-source voltage of the transistor 102 , resulting in the problem of uneven display on the display panel.
  • the plurality of virtual holes 200 include a first virtual hole 201 , a second virtual hole 202 and a third virtual hole 203 .
  • the first dummy hole 201 penetrates a portion of the insulating layer 1022 away from the active layer 1021
  • the second dummy hole 202 and the third dummy hole 203 penetrate the insulating layer 1022 .
  • the virtual hole 200 may be a rectangle, a circle, a diamond, an ellipse, or the like.
  • the diameter of the first virtual hole 201 is different from the diameter of the second virtual hole 202 . Further, the diameter of the second virtual hole 202 is larger than the diameter of the first virtual hole 201 . Specifically, the diameter of the first virtual hole 201 is greater than or equal to 2 micrometers and less than or equal to 3.5 micrometers. The diameter of the second virtual hole 202 is greater than or equal to 4 micrometers and less than or equal to 7 micrometers, and the difference between the diameters of the second virtual hole 202 and the first virtual hole 201 is greater than or equal to 1 micrometer and less than or equal to 4.5 microns. Further, the diameter of the first virtual hole 201 is greater than or equal to 2.5 micrometers and less than or equal to 3 micrometers.
  • the depth of the first virtual hole 201 is different from the depth of the third virtual hole 203 . Further, the depth of the third virtual hole 203 is greater or less than the depth of the first virtual hole 201 . Specifically, the first dummy hole 201 completely penetrates the insulating layer 1022 , the third dummy hole 203 partially penetrates the insulating layer 1022 , or the third dummy hole 203 completely penetrates the insulating layer 1022 .
  • the insulating layer 1022 includes a first insulating layer 1022a and a second insulating layer 1022b.
  • the first insulating layer 1022a is located on the active layer 1021
  • the second insulating layer 1022b is located on the side of the first insulating layer 1022a away from the active layer 1021
  • the depth of 201 is equal to the sum of the thicknesses of the first insulating layer 1022a and the second insulating layer 1022b.
  • the transistor 102 further includes: a first electrode layer 1023 and a second electrode layer 1024 .
  • the first electrode layer 1023 is located on the first insulating layer 1022a, and the first electrode layer 1023 includes a first wiring portion and a first electrode portion 1023a positioned in alignment with the active layer 1021.
  • the second electrode layer 1024 is located on the second insulating layer 1022b, and the second electrode layer 1024 includes a second wiring portion and a second electrode portion 1024a electrically connected to the active layer 1021.
  • the dummy hole 200 does not penetrate the active layer 1021 , the first electrode layer 1023 and the second electrode layer 1024 to ensure that the connection structure of the sub-pixel driving circuit 101 is not affected by the dummy hole 200 .
  • the first dummy hole 201 does not penetrate through the active layer 1021 , the first electrode layer 1023 and the second electrode layer 1024 .
  • the transistor 102 further includes a third electrode layer 1025 and a third insulating layer 1022c.
  • the third insulating layer 1022c is located on the third electrode layer 1025, and the third electrode layer 1025 and the third insulating layer 1022c are located between the second insulating layer 1022b and the second electrode layer 1024 .
  • the dummy hole 200 does not penetrate through the first electrode layer 1023 , the second electrode layer 1024 and the third electrode layer 1025 .
  • the depth of the first dummy hole 201 is equal to the sum of the thicknesses of the first insulating layer 1022a, the second insulating layer 1022b and the third insulating layer 1022c.
  • the display panel further includes a substrate 104 and a buffer layer 105 .
  • the buffer layer 105 is located between the substrate 104 and the active layer 1021, and the third dummy hole 203 penetrates through the buffer layer 105, so that the depth of the third dummy hole 203 is greater than that of the third dummy hole 203.
  • the depth of a dummy hole 201 ; or the third dummy hole 203 partially penetrates the insulating layer 1022 , so that the depth of the third dummy hole 203 is smaller than the depth of the first dummy hole 201 .
  • the substrate 104 includes a flexible substrate or a rigid substrate.
  • the defect density at the interface between the active layer 1021 and the insulating layer 1022 can be increased by setting the density of the first dummy holes 201.
  • FIG. 1E which is a schematic structural diagram of a pixel circuit drive island provided by an embodiment of the present application
  • FIGS. 1F to 1G the first sub-virtual hole provided by the embodiment of the present application and the A schematic structural diagram of a pixel circuit driving island
  • FIG. 1H is a schematic structural diagram of a first sub-virtual hole and a sub-pixel driving circuit provided in an embodiment of the present application.
  • the display panel further includes a plurality of pixel circuit driving islands 110 , the pixel circuit driving islands 110 are located in the transition display area 100 a , and each pixel circuit driving island 110 includes a plurality of pixel circuit driving islands 110 .
  • the auxiliary pixel driving circuit 101 includes the transistor 102 . Therefore, by arranging a plurality of the first sub-dummy holes 2011 between two adjacent pixel circuit driving islands 110 , the first sub-dummy holes 2011 can be separated from the active layer 1021 of the transistor 102 . It is beneficial to improve the electrical uniformity of the auxiliary pixel driving circuit 101 through the dummy hole 200 .
  • a plurality of the first sub-virtual holes 2011 may also be included between two adjacent sub-pixel driving circuits 101 in the same pixel circuit driving island 110 .
  • each of the pixel circuit driving islands 110 has a length direction a, and each of the sub-pixel drive circuits 101 has a first length L1 in the length direction a, located in the phase
  • the plurality of first sub-dummy holes 2011 between two adjacent pixel circuit driving islands 110 have a second length L2; wherein, the second length L2 is greater than the first length L1, and the second length L2 It is equal to the distance in the length direction a between the first sub-virtual hole located at the head end and the first sub-virtual hole located at the end of the plurality of first sub-virtual holes 2011 .
  • the plurality of first sub-virtual holes 2011 include a beginning sub-virtual hole 2011a and a terminal sub-virtual hole 2011b located at both ends.
  • Each of the sub-pixel driving circuits 101 has the first length L1 in the longitudinal direction a, and has a second length L2 in the longitudinal direction a from the start terminal dummy hole 2011a to the end terminal dummy hole 2011b (That is, the second length L2 is equal to the sum of the diameters of the plurality of first sub-virtual holes 2011 and the hole distance of two adjacent first sub-virtual holes 2011 ), and the second length L2 is greater than the first sub-virtual hole 2011 .
  • a length L1 so that the plurality of first sub-dummy holes 2011 adjacent to the sub-pixel driving circuit 101 can achieve the purpose of improving the electrical performance of the transistor 102 .
  • the second length L2 is greater than or equal to twice the first length L1, so that the set length of the first sub-virtual hole 2011 (ie the second length L2) is greater than or equal to two
  • the length of the auxiliary pixel driving circuit 101 ie, twice the first length L1 ) is used to further improve the electrical uniformity of the auxiliary pixel driving circuit 101 .
  • the first length L1 of the auxiliary pixel driving circuit 101 is taken as an example to be equal to 60 micrometers, and the second length L2 is greater than or equal to 120 micrometers.
  • the pixel circuit driving island 110 has a third length L3 in the length direction a, and the second length L2 is greater than or equal to the third length L3 . Further, in a top view, at least one of the two adjacent pixel circuit driving islands 110 is located in the first sub-virtual hole located at the head end and the first sub-dummy hole located at the end of the first sub-dummy hole 2011 . between a sub-virtual hole. Specifically, please continue to refer to FIG. 1F , the pixel circuit driving island 110 includes a first pixel circuit driving island 1101 and a second pixel circuit driving island 1102 .
  • the first sub-dummy hole 2011a and the end sub-dummy hole 2011b of the plurality of first sub-dummy holes 2011 adjacent to the first pixel circuit driving island 1101 are located on the first pixel circuit driving island 1101 on both sides; the first sub-virtual hole 2011a and the end sub-dummy hole 2011b in the plurality of first sub-virtual holes 2011 adjacent to the second pixel circuit driving island 1102 are located in the second sub-pixel driving circuit 1012 on both sides.
  • the pixel circuit driving island 110 includes a first pixel circuit driving island 1101 and a second pixel circuit driving island 1102 , and a plurality of the first sub-virtual holes 2011 are located in the first pixel circuit between the driving island 1101 and the second pixel circuit driving island 1102 .
  • the first pixel circuit driving island 1101 and the second pixel circuit driving island 1102 are arranged in parallel and out of alignment, and the plurality of first sub-dummy holes 2011 include driving A plurality of first holes 2011c adjacent to the island 1101, a plurality of second holes 2012d adjacent to the second sub-pixel driving circuit 1012, the plurality of first holes 2011c are parallel to the plurality of second holes 2011d Misaligned settings.
  • the extension line of the first side 1101a of the first pixel circuit driving island 1101 and the first side 1102a of the second pixel circuit driving island 1102 has a fourth in the length direction a.
  • the length L4 the plurality of first holes 2011c include first head holes and first end holes at both ends, and the plurality of second holes 2011d include second head holes and second end holes at both ends.
  • the first side of the first head end hole and the first side of the second head end hole have a fifth length L5 in the length direction a, wherein the fourth length L4 may be equal to the fifth length Length L5.
  • the plurality of first sub-virtual holes 2011 further includes a plurality of third holes 2011e located between the first hole 2011c and the second hole 2011d, wherein the plurality of third holes 2011e The number of columns is greater than or equal to 1 column. From the first hole 2011c to the second hole 2011d, the first hole 2011c, the third hole 2011e and the second hole 2011d are arranged in a trend of ascending or descending order.
  • the first virtual hole 201 further includes a plurality of second sub-virtual holes 2012 .
  • the second sub-dummy hole 2012 is located on the side of the pixel circuit driving island 110 close to the display light-transmitting region 100b, that is, the second sub-dummy hole 2012 is located in the area II in FIG. 1D .
  • the number of rows and/or columns of the plurality of second sub-virtual holes 2012 is greater than or equal to 4, so that a plurality of The first sub-virtual hole 2011 can further improve the electrical performance of the transistor 102 .
  • the display panel further includes a main display area 100c, and the main display area 100c is located on a side of the transition display area 100a away from the display light-transmitting area 100b.
  • the display panel includes a plurality of main sub-pixels 303 located in the main display area 100c and a main pixel driving circuit 301 for driving the plurality of main sub-pixels 303 to emit light.
  • the first virtual hole 201 further includes a plurality of third sub-virtual holes 2013 .
  • the third sub-dummy hole 2013 is located on the side of the pixel circuit driving island 110 close to the main display area 100c, that is, the third sub-dummy hole 2013 is located in the area III in FIG. 1D .
  • the main sub-pixel 303 includes at least one of organic light emitting diodes, micro light emitting diodes, and sub-millimeter light emitting diodes.
  • the main pixel driving circuit 301 includes a plurality of main transistors 302 , each of the main transistors 302 includes a main active layer 3021 and a main insulating layer 3022 covering the main active layer 3021 , the gate layer and the source and drain layers on the side of the main insulating layer 3022 away from the main active layer 3021 .
  • the source and drain layers include first wirings and source and drain electrodes that are electrically connected to the main active layer 3021 through first vias on the main insulating layer 3022 .
  • the gate layer includes a second wiring and a main gate disposed in alignment with the main active layer 3021 .
  • the first trace and the second trace are respectively electrically connected to the source, drain or main gate of the main transistor 3021 through second vias on the main insulating layer 3022 .
  • the gate layer and the source and drain layers may include multiple layers; the main transistor 302 may further include a wiring layer, and the wiring layer is connected to the first via the second via hole. At least one of the wiring and the second wiring is electrically connected.
  • the main insulating layer 3022 is the same layer as the insulating layer 1022
  • the main active layer 3021 is the same layer as the active layer 1021
  • the source and drain layers are the same as the second electrode layer 1024
  • the gate layer and the first electrode layer 1023 are in the same layer to save process steps.
  • the main active layer 3021 includes a silicon active layer and an oxide active layer.
  • the main transistor 302 includes a P-type transistor and an N-type transistor.
  • the main transistor 302 includes a field effect transistor; further, the main transistor 302 includes a thin film transistor.
  • the main pixel driving circuit 301 includes a plurality of via holes 301 a, and in a top view, the plurality of the virtual holes 200
  • the arrangement is the same as the arrangement of the plurality of vias 301a, as shown in FIG. 2A, or the virtual holes 200 are arranged in a matrix, or the virtual holes 200 are arranged in a parallelogram, as shown in FIG. 2B shown.
  • the via hole 301a includes a source-drain via hole (ie, the first via hole) and a wiring via hole (ie, including the second via hole).
  • the multiple via holes 301a are also arranged in different forms, as shown in FIG. 2A and FIG. 2C .
  • the distance between two adjacent dummy holes 200 is greater than or equal to 2 microns and less than or equal to 5 microns. Further, the distance between two adjacent virtual holes 200 is greater than or equal to 3 micrometers and less than or equal to 4 micrometers.
  • the arrangement manner of the plurality of first dummy holes 201 is the same as the arrangement manner of the plurality of the via holes 301a, or the plurality of the first dummy holes 201 are arranged in a matrix, or the plurality of the first dummy holes 201 are arranged in a matrix.
  • the holes 201 are arranged in a parallelogram.
  • the main pixel driving circuit 301 adopts 7T1C (that is, the main pixel driving circuit 301 includes 7 main transistors 302 and 1 storage capacitor, and the main pixel driving circuit 301 is connected to The structure of the scan line SL, the data line DL, the power supply line VDD, the light emission control line EML, and the reset line VL) is described.
  • the main pixel driving circuit 301 includes a plurality of via holes 301a.
  • the arrangement of the dummy holes 201 is the same as the arrangement of the plurality of vias 301a.
  • the display panel further includes a flat layer 106 , the flat layer 106 is located on the side of the insulating layer 1022 away from the active layer 1021 , and the flat layer 106 includes a Filling parts in the first dummy hole 201 , the second dummy hole 202 and the third dummy hole 203 .
  • the auxiliary sub-pixel 103 includes a first anode 1031 electrically connected to the auxiliary pixel driving circuit 101 , a first light-emitting layer 1032 located on the first anode 1031 , and a first light-emitting layer 1032 located on the first light-emitting layer 1032 .
  • the first cathode 1033 is a first cathode 1033 .
  • the first anodes 1031 of the plurality of auxiliary sub-pixels 103 may be electrically connected to the same auxiliary pixel driving circuit 101, so that one auxiliary pixel driving circuit 101 drives a plurality of the auxiliary sub-pixels
  • the pixel 103 emits light.
  • the main sub-pixel 303 includes a second anode 3031 electrically connected to the main pixel driving circuit 301 , a second light-emitting layer 3032 on the second anode 3031 , and a second light-emitting layer 3032 on the second light-emitting layer 1032 .
  • the display panel further includes a pixel definition layer 107 located on the first anode 1031 and the second anode 3031, the pixel definition layer 107 includes a plurality of pixel definition regions, the first light emitting layer 1032 and the The second light emitting layer 3032 is located in the pixel definition area.
  • the light transmittance of the display light transmission area 100b is greater than the light transmittance of the main display area 100c, and the display panel further includes a sensor 108, and the sensor 108 faces the display light transmission area 100b.
  • the senor 108 includes a fingerprint recognition sensor, a camera, a structured light sensor, a time-of-flight sensor, a distance sensor, a light sensor, etc., so that the sensor can collect signals through the display light-transmitting area, so that the The display device implements off-screen sensing solutions such as off-screen fingerprint recognition, off-screen cameras, off-screen face recognition, and off-screen distance perception.
  • the display panel further includes parts not shown, such as an encapsulation layer, touch electrodes, and the like.
  • FIG. 3 is a simulation result diagram provided by an embodiment of the present application.
  • the first sub-dummy hole 2011 between two adjacent pixel circuit driving islands 110 as an example, when the display panel is provided with a plurality of the first sub-dummy holes 2011 between two adjacent pixel circuit driving islands 110 After the sub-dummy holes 2011 are formed, the sub-threshold swing SS of the transistor 102 is improved, and the arrangement density of the first sub-dummy holes 2011 affects the sub-threshold swing of the transistor 102 .
  • the sub-threshold swing SS of the transistor 102 when the second length L2 is equal to the first length L1, the sub-threshold swing SS of the transistor 102 is about 0.45; when the second length L2 is greater than or equal to the first length L1 When 2 times, the sub-threshold swing SS of the transistor 102 is about 0.567; the plurality of first sub-dummy holes 2011 are arranged in the same form as the arrangement of the plurality of via holes 301a in two adjacent ones.
  • the sub-threshold swing SS of the transistor 102 is about 0.541; that is, when the second length L2 is greater than or equal to twice the first length L1, the transistor 102
  • the subthreshold swing of the transistor 102 in the transition display area 100a is large, so that the subthreshold swing SS of the transistor 102 in the transition display area 100a is similar to the subthreshold swing SS of the main transistor 503 in the main display area 100c, It has a better effect of improving the electrical uniformity of the sub-pixel driving circuit 101 , so that the transition display area 100a and the main display area 100c can have similar display effects.
  • Table 1 is a result verification table for setting virtual holes provided by the embodiments of the present application.
  • Embodiments of the present application also provide a method for manufacturing a display panel, wherein the display panel has a transition display area, including the following steps:
  • Step S10 providing a substrate
  • Step S20 preparing an active layer on the substrate and an insulating layer covering the active layer
  • Step S30 preparing virtual holes.
  • the dummy hole is located in the transition display area, the first dummy hole penetrates a part of the insulating layer away from the active layer, and the display panel includes a plurality of auxiliary holes located in the transition display area
  • a pixel driving circuit each of the sub-pixel driving circuits includes a transistor, and the transistor includes the active layer.
  • a step S40 is further included: performing dehydrogenation treatment on the display panel.
  • FIG. 4 is a schematic diagram of setting the dummy hole to improve the electrical performance of a transistor according to an embodiment of the present application.
  • the Si-H bond is broken, and H combines with H 2 to overflow; the other is free state H and Si- Dangling bonds form bonds.
  • the probability of occurrence of the first mechanism is greater than the probability of occurrence of the second mechanism.
  • the opening density of the virtual pores determines the interfacial free state H concentration.
  • the greater the opening density of the virtual holes the faster the free state H forms the H overflow, so that the probability of the second mechanism occurring is lower, that is, the probability that the free state H combines with the Si-dangling bonds at the interface to form bonds. lower.
  • the density of defect states at the interface between the active layer and the insulating layer increases, which in turn increases the subthreshold swing of the transistor and reduces the current flowing through the source and drain of the transistor. Sensitivity to gate-source voltage fluctuations of the transistor, reducing the effect of gate-source voltage fluctuations of the transistor on the current flowing through the source and drain of the transistor.
  • the insulating layer includes a first insulating layer and a second insulating layer
  • the step S20 further includes:
  • Step S21 preparing the first insulating layer covering the active layer
  • Step S22 preparing a first electrode layer, where the first electrode layer includes a first wiring portion and a first electrode portion aligned with the active layer;
  • Step S23 preparing the second insulating layer covering the first electrode layer
  • the dummy hole penetrates the portion of the first insulating layer, the second insulating layer, the active layer, the first electrode layer and the second electrode layer that do not overlap.
  • step S23 it also includes:
  • Step S24 preparing a third electrode layer and the third insulating layer covering the third electrode layer.
  • the dummy hole penetrates through the first insulating layer, the second insulating layer, the third insulating layer and the active layer, the first electrode layer and the second electrode layer without overlapping part.
  • step S30 it also includes:
  • Step S50 preparing a second electrode layer on the insulating layer, the second electrode layer including a second wiring part and a second electrode part electrically connected to the active layer;
  • Step S60 preparing a flat layer, where the flat layer includes a filling portion located in the virtual hole;
  • the dummy hole penetrates the non-overlapping portion of the insulating layer and the second electrode layer.
  • the preparation method of the display panel further includes a plurality of process steps such as preparing auxiliary sub-pixels, encapsulation layers, etc., which will not be repeated here.
  • Embodiments of the present application further provide a display device, including any of the above-mentioned display panels.
  • the display device includes fixed terminals such as televisions and desktop computers, mobile terminals such as mobile phones and notebook computers, and wearable devices such as wristbands, VR (virtual display) devices, and AR (augmented display) devices.
  • fixed terminals such as televisions and desktop computers
  • mobile terminals such as mobile phones and notebook computers
  • wearable devices such as wristbands, VR (virtual display) devices, and AR (augmented display) devices.

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Abstract

提供了一种显示面板及一种显示装置，显示面板包括多个辅像素驱动电路（101）。每一辅像素驱动电路（101）包括晶体管（102），晶体管（102）包括有源层（1021）及绝缘层（1022）。显示面板在过渡显示区（100a）内设有第一虚拟孔（201），第一虚拟孔（201）贯穿绝缘层（1022）的远离有源层（1021）的部分，以通过第一虚拟孔（201）降低多个辅像素驱动电路（101）之间出现的电性差异，从而实现显示面板的均一显示。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及一种显示装置。
背景技术
在显示面板中采用屏下摄像头(Camera Under Panel,CUP)技术，可以兼顾摄像头的成像效果及全面屏显示设计。但驱动CUP区像素发光的驱动电路被放置在CUP区外围，驱动电路设置的密度差异及各驱动电路中所采用的晶体管的电性差异，会导致CUP区像素在接收相同的驱动信号时出现不同的亮度差异，引起CUP区出现显示不均的问题。
技术问题
本申请实施例提供一种显示面板及一种显示装置，可以降低辅像素驱动电路之间出现的电性差异，进而改善显示面板的显示的均一性。
技术解决方案
本申请的实施例提供一种显示面板，所述显示面板包括显示透光区及位于所述显示透光区外围的过渡显示区，所述显示面板包括多个辅像素驱动电路及多个辅子像素。多个所述辅像素驱动电路位于所述过渡显示区内，多个所述辅子像素位于所述显示透光区内，且电性连接于所述辅像素驱动电路。每一所述辅像素驱动电路包括晶体管，所述晶体管包括有源层以及位于所述有源层上的绝缘层。
其中，所述显示面板在所述过渡显示区内设有第一虚拟孔，所述第一虚拟孔贯穿所述绝缘层的远离所述有源层的部分。
在一些实施例中，所述显示面板还包括位于所述过渡显示区内的多个像素电路驱动岛，每一所述像素电路驱动岛包括多个所述辅像素驱动电路，所述第一虚拟孔包括多个第一子虚拟孔，每一所述第一子虚拟孔位于对应的相邻两所述像素电路驱动岛之间。
在一些实施例中，每一所述像素电路驱动岛具有长度方向，每一辅像素驱动电路在所述长度方向上具有第一长度，位于相邻两所述像素电路驱动岛之间 的多个所述第一子虚拟孔具有第二长度；其中，所述第二长度大于所述第一长度，所述第二长度等于多个所述第一子虚拟孔中位于首端的所述第一子虚拟孔与位于末端的所述第一子虚拟孔在所述长度方向上的距离。
在一些实施例中，所述第二长度大于或等于所述第一长度的2倍。
在一些实施例中，所述第一虚拟孔包括位于所述像素电路驱动岛的靠近所述显示透光区一侧的多个第二子虚拟孔。
在一些实施例中，多个所述第二子虚拟孔的行数和/或列数大于或等于4。
在一些实施例中，所述显示面板还包括位于所述过渡显示区远离所述显示透光区的一侧的主显示区，所述第一虚拟孔包括位于所述像素电路驱动岛的靠近所述主显示区一侧的多个第三子虚拟孔。
在一些实施例中，所述显示面板还包括位于所述主显示区的多个主子像素及驱动多个所述主子像素发光的多个主像素驱动电路；其中，每一所述主像素驱动电路设有多个过孔，在俯视视角下，多个所述第一虚拟孔的排列方式与多个所述过孔的排列方式相同，或多个所述第一虚拟孔呈矩阵排列。
在一些实施例中，所述显示面板还设有位于所述过渡显示区内的第二虚拟孔，所述第二虚拟孔位于所述像素电路驱动岛靠近所述显示透光区的一侧，所述第二虚拟孔贯穿所述绝缘层，所述第二虚拟孔的孔径大于所述第一虚拟孔的孔径。
在一些实施例中，所述显示面板还设有位于所述过渡显示区内的第三虚拟孔，所述第三虚拟孔贯穿所述绝缘层，所述第三虚拟孔的深度大于或小于所述第一虚拟孔的深度。
在一些实施例中，所述晶体管还包括：第一绝缘层、第一电极层、第二绝缘层、第二电极层。
所述第一绝缘层位于所述有源层上；所述第一电极层位于所述第一绝缘层上，所述第一电极层包括第一走线部和与所述有源层对位设置的第一电极部；所述第二绝缘层位于所述第一电极层上；所述第二电极层位于所述第二绝缘层上，所述第二电极层包括第二走线部和与所述有源层电性连接的第二电极部。
其中，所述绝缘层包括所述第一绝缘层和所述第二绝缘层，所述第一虚拟孔不贯穿所述有源层、所述第一电极层和所述第二电极层。
在一些实施例中，所述显示面板还包括位于所述绝缘层远离所述有源层一侧的平坦层，所述平坦层包括位于所述第一虚拟孔内的填充部。
在一些实施例中，所述第一虚拟孔的孔径大于或等于2微米且小于或等于3.5微米，相邻的两个所述虚拟孔之间的距离大于或等于2微米且小于或等于5微米。
在一些实施例中，所述第二虚拟孔的孔径大于或等于4微米且小于或等于7微米，所述第二虚拟孔与所述第一虚拟孔的孔径之差大于或等于1微米且小于或等于4.5微米。
在一些实施例中，所述辅子像素包括有机发光二极管、微型发光二极管、次毫米发光二极管。
在一些实施例中，所述第一虚拟孔经脱氢处理后制备得到。
本申请的实施例还提供一种显示装置，包括任一上述的显示面板。
有益效果
相较于现有技术，本申请实施例提供一种显示面板及一种显示装置，所述显示面板包括显示透光区和位于所述显示透光区外围的过渡显示区，所述显示面板包括多个辅像素驱动电路及多个辅子像素。多个所述辅像素驱动电路位于所述过渡显示区内，多个所述辅子像素位于所述显示透光区内，且电性连接于所述辅像素驱动电路。每一所述辅像素驱动电路包括晶体管，所述晶体管包括有源层以及位于所述有源层上的绝缘层。其中，所述显示面板在所述过渡显示区内设有第一虚拟孔，所述第一虚拟孔贯穿所述绝缘层的远离所述有源层的部分，以通过所述第一虚拟孔降低多个辅像素驱动电路之间出现的电性差异，改善所述辅像素驱动电路的电性的均一性，从而实现所述显示面板的均一显示。
附图说明
图1A～图1C为本申请的实施例提供的显示面板的结构示意图；
图1D为图1A中A处的局部放大图；
图1E为本申请的实施例提供的像素电路驱动岛的结构示意图；
图1F～图1G为本申请的实施例提供的第一子虚拟孔与像素电路驱动岛的结构示意图；
图1H为本申请的实施例提供的第一子虚拟孔与辅像素驱动电路的结构示意图；
图2A～图2C为本申请的实施例提供的虚拟孔的排布示意图；
图3为本申请的实施例提供的仿真结果图；
图4为本申请的实施例提供的设置虚拟孔改善晶体管电性能的原理图。
表1为本申请的实施例提供的设置虚拟孔的结果验证表。
本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
具体地，请参阅图1A～图1C，其为本申请的实施例提供的显示面板的结构示意图；如图1D，其为图1A中A处的局部放大图。
本申请的实施例提供一种显示面板，所述显示面板包括显示透光区100b及位于所述显示透光区100b外围的过渡显示区100a。所述显示面板包括多个辅像素驱动电路101及多个辅子像素103。多个所述辅像素驱动电路101位于所述过渡显示区100a内，多个所述辅子像素103位于所述过渡显示区100a和所述显示透光区100b内，且所述辅像素驱动电路101与所述辅子像素103电性连接，所述辅像素驱动电路101用于驱动至少一所述辅子像素103发光。
可选地，所述显示面板包括自发光显示面板，所述辅子像素103包括有机发光二极管、微型发光二极管、次毫米发光二极管中的至少一种。
每一所述辅像素驱动电路101包括多个晶体管102，每一所述晶体管102包括有源层1021及位于所述有源层1021上的绝缘层1022。
其中，所述显示面板在所述过渡显示区100a内设置有多个虚拟孔200，所述虚拟孔200贯穿所述绝缘层1022的远离所述有源层1021的部分，以通过所述虚拟孔200改善所述辅像素驱动电路101的电性的均一性，从而实现所述显示面板的均一显示。
可选地，所述晶体管102为电流驱动型器件。进一步地，所述晶体管102包括薄膜晶体管。所述有源层1021包括硅有源层；进一步地，所述有源层1021 包括低温多晶硅有源层。所述晶体管102包括P型晶体管、N型晶体管。
由于所述有源层1021与所述绝缘层1022交界面处的缺陷密度会影响所述晶体管102的阈值电压、亚阈值摆幅等电学性能。因此在所述晶体管102为电流驱动型器件时，所述晶体管102的阈值电压的绝对值越大，所述晶体管102的亚阈值摆幅就越大，所述晶体管102的栅源电压的波动对流经所述晶体管102的源极和漏极的电流影响就越小，从而使所述晶体管102可以向所述辅子像素103提供更稳定的驱动电流，使所述辅子像素103的发光亮度的波动更小，有利于提高所述显示面板的显示的均一性。
而在所述过渡显示区100a内设置所述虚拟孔200可以增加所述有源层1021与所述绝缘层1022交界面处的缺陷密度，从而提高所述晶体管102的亚阈值摆幅，降低所述晶体管102的栅源电压的波动对流经所述晶体管102的源极和漏极的电流影响，避免所述显示面板在采用低灰阶驱动时，因所述晶体管102的亚阈值摆幅较小，驱动所述辅子像素103发光的驱动电流对所述晶体管102的栅源电压的波动较敏感，导致所述显示面板出现显示不均的问题。
具体地，请继续参阅图1B～图1C，多个所述虚拟孔200包括第一虚拟孔201、第二虚拟孔202及第三虚拟孔203。其中，所述第一虚拟孔201贯穿所述绝缘层1022的远离所述有源层1021的部分，所述第二虚拟孔202与所述第三虚拟孔203贯穿所述绝缘层1022。可选地，在俯视视角下，所述虚拟孔200可以为矩形、圆形、菱形、椭圆形等。
进一步地，所述第一虚拟孔201的孔径与所述第二虚拟孔202的孔径不同。更进一步地，所述第二虚拟孔202的孔径大于所述第一虚拟孔201的孔径。具体地，所述第一虚拟孔201的孔径大于或等于2微米且小于或等于3.5微米。所述第二虚拟孔202的孔径大于或等于4微米且小于或等于7微米，所述第二虚拟孔202与所述第一虚拟孔201的孔径之差大于或等于1微米且小于或等于4.5微米。进一步地，所述第一虚拟孔201的孔径大于或等于2.5微米且小于或等于3微米。
进一步地，所述第一虚拟孔201的深度与所述第三虚拟孔203的深度不同。进一步地，所述第三虚拟孔203的深度大于或小于所述第一虚拟孔201的深度。具体地，所述第一虚拟孔201完全贯穿所述绝缘层1022，所述第三虚拟孔203 部分贯穿所述绝缘层1022，或所述第三虚拟孔203完全贯穿所述绝缘层1022。
请继续参阅图1B～图1C，所述绝缘层1022包括第一绝缘层1022a和第二绝缘层1022b。其中，所述第一绝缘层1022a位于所述有源层1021上，所述第二绝缘层1022b位于所述第一绝缘层1022a远离所述有源层1021的一侧，所述第一虚拟孔201的深度等于所述第一绝缘层1022a与所述第二绝缘层1022b的厚度之和。
进一步地，所述晶体管102还包括：第一电极层1023、第二电极层1024。其中，所述第一电极层1023位于所述第一绝缘层1022a上，所述第一电极层1023包括第一走线部和与所述有源层1021对位设置的第一电极部1023a。所述第二电极层1024位于所述第二绝缘层1022b上，所述第二电极层1024包括第二走线部和与所述有源层1021电性连接的第二电极部1024a。
所述虚拟孔200不贯穿所述有源层1021、所述第一电极层1023和所述第二电极层1024，以保证所述辅像素驱动电路101的连接结构不受所述虚拟孔200影响。具体地，所述第一虚拟孔201不贯穿所述有源层1021、所述第一电极层1023和所述第二电极层1024。
进一步地，请继续参阅图1C，所述晶体管102还包括第三电极层1025、第三绝缘层1022c。所述第三绝缘层1022c位于所述第三电极层1025上，所述第三电极层1025与所述第三绝缘层1022c位于所述第二绝缘层1022b与所述第二电极层1024之间。其中，所述虚拟孔200不贯穿所述第一电极层1023、所述第二电极层1024、所述第三电极层1025。所述第一虚拟孔201的深度等于所述第一绝缘层1022a、所述第二绝缘层1022b和所述第三绝缘层1022c的厚度之和。
进一步地，所述显示面板还包括衬底104，缓冲层105。所述缓冲层105位于所述衬底104与所述有源层1021之间，所述第三虚拟孔203贯穿所述缓冲层105，以使所述第三虚拟孔203的深度大于所述第一虚拟孔201的深度；或所述第三虚拟孔203部分贯穿所述绝缘层1022，以使所述第三虚拟孔203的深度小于所述第一虚拟孔201的深度。
可选地，所述衬底104包括柔性衬底、刚性衬底。
由于所述第一虚拟孔201完全贯穿所述绝缘层1022，因此可通过设置所 述第一虚拟孔201的密度增加所述有源层1021与所述绝缘层1022交界面处的缺陷密度。
具体地，如图1E所示，其为本申请的实施例提供的像素电路驱动岛的结构示意图；如图1F～图1G所示，其为本申请的实施例提供的第一子虚拟孔与像素电路驱动岛的结构示意图；如图1H，其为本申请的实施例提供的第一子虚拟孔与辅像素驱动电路的结构示意图。
请继续参阅图1D～图1H，所述显示面板还包括多个像素电路驱动岛110，所述像素电路驱动岛110位于所述过渡显示区100a内，每一所述像素电路驱动岛110包括多个所述辅像素驱动电路101，所述第一虚拟孔201包括多个第一子虚拟孔2011，每一所述第一子虚拟孔2011位于对应的相邻两个所述像素电路驱动岛110之间，即所述第一子虚拟孔2011位于图1D中的Ⅰ区内。
由于所述像素电路驱动岛110包括所述辅像素驱动电路101，所述辅像素驱动电路101包括所述晶体管102。因此，在相邻的两所述像素电路驱动岛110之间设置多个所述第一子虚拟孔2011，可以使所述第一子虚拟孔2011距所述晶体管102的所述有源层1021较近，有利于通过所述虚拟孔200改善所述辅像素驱动电路101的电性均一性。
可以理解的，在布局空间允许的情况下，同一所述像素电路驱动岛110内的相邻两所述辅像素驱动电路101之间也可包括多个所述第一子虚拟孔2011。
请继续参阅图1D和图1F～图1H，每一所述像素电路驱动岛110具有长度方向a，每一所述辅像素驱动电路101在所述长度方向a上具有第一长度L1，位于相邻两所述像素电路驱动岛110之间的多个所述第一子虚拟孔2011具有第二长度L2；其中，所述第二长度L2大于所述第一长度L1，所述第二长度L2等于多个所述第一子虚拟孔2011中位于首端的所述第一子虚拟孔与位于末端的所述第一子虚拟孔在所述长度方向a上的距离。
具体地，请继续参阅图1H，多个所述第一子虚拟孔2011包括位于两端的始端子虚拟孔2011a和末端子虚拟孔2011b。每一所述辅像素驱动电路101在所述长度方向a上具有所述第一长度L1，在所述长度方向a上从始端子虚拟孔2011a至所述末端子虚拟孔2011b具有第二长度L2(即所述第二长度L2等 于多个所述第一子虚拟孔2011的孔径与相邻两所述第一子虚拟孔2011的孔距之和)，所述第二长度L2大于所述第一长度L1，以使与所述辅像素驱动电路101相邻的多个所述第一子虚拟孔2011可以达到改善所述晶体管102的电学性能的目的。
进一步地，所述第二长度L2大于或等于所述第一长度L1的2倍，以使所述第一子虚拟孔2011的设置长度(即所述第二长度L2)大于或等于2个所述辅像素驱动电路101的长度(即所述第一长度L1的2倍)，以进一步改善所述辅像素驱动电路101的电性的均一性。
具体地，以所述辅像素驱动电路101的所述第一长度L1等于60微米为例进行说明，所述第二长度L2大于或等于120微米。
更进一步地，请继续参阅图1F，所述像素电路驱动岛110在所述长度方向a上具有第三长度L3，所述第二长度L2大于或等于所述第三长度L3。更进一步地，在俯视视角下，相邻两所述像素电路驱动岛110中的至少一个位于所述第一子虚拟孔2011的位于首端的所述第一子虚拟孔与位于末端的所述第一子虚拟孔之间。具体地，请继续参阅图1F，所述像素电路驱动岛110包括第一像素电路驱动岛1101和第二像素电路驱动岛1102。在俯视视角下，与所述第一像素电路驱动岛1101相邻的多个所述第一子虚拟孔2011中的始端子虚拟孔2011a和末端子虚拟孔2011b位于所述第一像素电路驱动岛1101的两侧；与所述第二像素电路驱动岛1102相邻的多个所述第一子虚拟孔2011中的始端子虚拟孔2011a和末端子虚拟孔2011b位于所述第二辅像素驱动电路1012的两侧。
进一步地，在相邻的两所述像素电路驱动岛110不位于同一水平线时，多个所述第一子虚拟孔2011可根据与之相邻的所述像素电路驱动岛110的位置进行设置。具体地，如图1G所示，所述像素电路驱动岛110包括第一像素电路驱动岛1101和第二像素电路驱动岛1102，多个所述第一子虚拟孔2011位于所述第一像素电路驱动岛1101和所述第二像素电路驱动岛1102之间。其中，在俯视视角下，所述第一像素电路驱动岛1101和所述第二像素电路驱动岛1102平行不对齐设置，多个所述第一子虚拟孔2011包括与所述第一像素电路驱动岛1101相邻的多个第一孔2011c、与所述第二辅像素驱动电路1012相邻 的多个第二孔2012d，多个所述第一孔2011c与多个所述第二孔2011d平行不对齐设置。
进一步地，在俯视视角下，所述第一像素电路驱动岛1101的第一侧1101a与所述第二像素电路驱动岛1102的第一侧1102a的延长线在所述长度方向a上具有第四长度L4，多个所述第一孔2011c包括位于两端的第一首端孔和第一末端孔，多个所述第二孔2011d包括位于两端的第二首端孔和第二末端孔。所述第一首端孔的第一侧与所述第二首端孔的第一侧在所述长度方向a上具有第五长度L5，其中，所述第四长度L4可等于所述第五长度L5。
更进一步地，多个所述第一子虚拟孔2011还包括位于所述第一孔2011c与所述第二孔2011d之间的多个第三孔2011e，其中，多个所述第三孔2011e的列数大于或等于1列。自所述第一孔2011c至所述第二孔2011d的方向上，所述第一孔2011c、所述第三孔2011e及所述第二孔2011d呈依次上升或依次下降的趋势排列。
请继续参阅图1A～图1D，所述第一虚拟孔201还包括多个第二子虚拟孔2012。其中，所述第二子虚拟孔2012位于所述像素电路驱动岛110靠近所述显示透光区100b的一侧，即所述第二子虚拟孔2012位于图1D中的Ⅱ区内。
进一步地，多个所述第二子虚拟孔2012的行数和/或列数大于或等于4，以使所述过渡显示区100a在靠近所述显示透光区100b的一侧设置的多个所述第一子虚拟孔2011可以达到进一步改善所述晶体管102的电学性能的目的。
请继续参阅图1A～图1D，所述显示面板还包括主显示区100c，所述主显示区100c位于所述过渡显示区100a远离所述显示透光区100b的一侧。
所述显示面板包括位于所述主显示区100c内的多个主子像素303及驱动多个所述主子像素303发光的主像素驱动电路301。所述第一虚拟孔201还包括多个第三子虚拟孔2013。所述第三子虚拟孔2013位于所述像素电路驱动岛110靠近所述主显示区100c的一侧，即所述第三子虚拟孔2013位于图1D中的Ⅲ区内。
可选地，所述主子像素303包括有机发光二极管、微型发光二极管、次毫米发光二极管中的至少一种。
请继续参阅图1B～图1C，所述主像素驱动电路301包括多个主晶体管302， 每一所述主晶体管302包括主有源层3021，覆盖所述主有源层3021的主绝缘层3022，位于所述主绝缘层3022远离所述主有源层3021一侧的栅极层及源漏极层。其中，所述源漏极层包括第一走线及通过所述主绝缘层3022上的第一过孔与所述主有源层3021电性连接的源极和漏极。所述栅极层包括第二走线及与所述主有源层3021对位设置的主栅极。所述第一走线与所述第二走线分别通过所述主绝缘层3022上的第二过孔与所述主晶体管3021的源极、漏极或主栅极电性连接。进一步地，所述栅极层、所述源漏极层均可包括多层；所述主晶体管302还可包括走线层，所述走线层通过所述第二过孔与所述第一走线、所述第二走线中的至少一个电性连接。
可选地，所述主绝缘层3022与所述绝缘层1022同层，所述主有源层3021与所述有源层1021同层，所述源漏极层与所述第二电极层1024同层，所述栅极层与所述第一电极层1023同层，以节省制程工序。所述主有源层3021包括硅有源层、氧化物有源层。所述主晶体管302包括P型晶体管、N型晶体管。所述主晶体管302包括场效应晶体管；进一步地，所述主晶体管302包括薄膜晶体管。
如图2A～图2C，其为本申请的实施例提供的虚拟孔200的排布示意图，所述主像素驱动电路301包括多个过孔301a，在俯视视角下，多个所述虚拟孔200的排列方式与多个所述过孔301a的排列方式相同，如图2A所示，或多个所述虚拟孔200呈矩阵排列，或多个所述虚拟孔200呈平行四边形排列，如图2B所示。其中，所述过孔301a包括源漏极过孔(即所述第一过孔)及走线过孔(即包括所述第二过孔)，根据所述主像素驱动电路301的结构形式的不同，多个所述过孔301a发排布形式也有所不同，如图2A和图2C所示。
其中，多个所述虚拟孔200以图2B所示的排列形式排列时，相邻的两个所述虚拟孔200之间的距离大于或等于2微米且小于或等于5微米。进一步地，相邻的两个所述虚拟孔200之间的距离大于或等于3微米且小于或等于4微米。
进一步地，多个所述第一虚拟孔201的排列方式与多个所述过孔301a的排列方式相同，或多个所述第一虚拟孔201呈矩阵排列，或多个所述第一虚拟孔201呈平行四边形排列。
具体地，请参阅图2A，以所述主像素驱动电路301采用7T1C(即所述主像素驱动电路301包括7个所述主晶体管302，1个存储电容，所述主像素驱动电路301接入扫描线SL、数据线DL、电源线VDD、发光控制线EML、复位线VL)结构进行说明，所述主像素驱动电路301包括多个过孔301a，在俯视视角下，多个所述第一虚拟孔201的排列方式与多个所述过孔301a的排列方式相同。
请继续参阅图1B～图1C，所述显示面板还包括平坦层106，所述平坦层106位于所述绝缘层1022远离所述有源层1021的一侧，所述平坦层106包括位于所述第一虚拟孔201、所述第二虚拟孔202及所述第三虚拟孔203内的填充部。
所述辅子像素103包括与所述辅像素驱动电路101电性连接的第一阳极1031，位于所述第一阳极1031上的第一发光层1032，以及位于所述第一发光层1032上的第一阴极1033。
可选地，多个所述辅子像素103的所述第一阳极1031可与同一所述辅像素驱动电路101电性连接，以使一个所述辅像素驱动电路101驱动多个所述辅子像素103发光。
所述主子像素303包括与所述主像素驱动电路301电性连接的第二阳极3031，位于所述第二阳极3031上的第二发光层3032，以及位于所述第二发光层1032上的第二阴极3033。
所述显示面板还包括像素定义层107，位于所述第一阳极1031及所述第二阳极3031上，所述像素定义层107包括多个像素定义区，所述第一发光层1032及所述第二发光层3032位于所述像素定义区内。
进一步地，所述显示透光区100b的透光率大于所述主显示区100c的透光率，所述显示面板还包括传感器108，所述传感器108正对所述显示透光区100b。
可选地，所述传感器108包括指纹识别传感器、摄像头、结构光传感器、飞行时间传感器、距离传感器、光线传感器等，以使所述传感器可以通过所述显示透光区采集信号，从而使所述显示装置实现屏下指纹识别、屏下摄像头、屏下面部识别、屏下距离感知等屏下传感方案。
进一步地，所述显示面板还包括封装层、触控电极等未示出部分。
如图3所示，其为本申请的实施例提供的仿真结果图。以所述第一子虚拟孔2011位于相邻两所述像素电路驱动岛110之间为例，当所述显示面板在相邻两所述像素电路驱动岛110之间设置多个所述第一子虚拟孔2011后，所述晶体管102的亚阈值摆幅SS得以提高，所述第一子虚拟孔2011的设置密度影响所述晶体管102的亚阈值摆幅。具体地，在所述第二长度L2等于所述第一长度L1时，所述晶体管102的亚阈值摆幅SS约为0.45；在所述第二长度L2大于或等于所述第一长度L1的2倍时，所述晶体管102的亚阈值摆幅SS约为0.567；在多个所述第一子虚拟孔2011以与多个所述过孔301a的排列方式相同的形式设置在相邻两所述像素电路驱动岛110之间时，所述晶体管102的亚阈值摆幅SS约为0.541；即在所述第二长度L2大于或等于所述第一长度L1的2倍时，所述晶体管102的亚阈值摆幅较大，使得位于所述过渡显示区100a内的所述晶体管102的亚阈值摆幅SS与位于所述主显示区100c内的所述主晶体管503的亚阈值摆幅相近，对改善所述辅像素驱动电路101的电性的均一性具有较佳的效果，可使所述过渡显示区100a与所述主显示区100c具有相近的显示效果。
请参阅表1，其为本申请的实施例提供的设置虚拟孔的结果验证表。
Figure PCTCN2021078086-appb-000001
由表1可知，在所述像素电路驱动岛110的靠近所述显示透光区100b的一侧(即Ⅱ区)，相邻两所述像素电路驱动岛110之间(即Ⅰ区)，以及所述 像素电路驱动岛110的靠近所述主显示区100c的一侧(即Ⅲ区)采用图2A～图2C所示的方式设置多个所述虚拟孔，可以改善所述显示面板在所述显示透光区100b出现显示不均的问题。更具体地，避免了位于所述显示透光区100b内的所述辅子像素103在显示时出现高灰阶偏亮，低灰阶偏暗的问题。其中，所述虚拟孔200采用图2B中的排列形式为密集排列形式，采用图2A及图2C所示的排列形式为过孔排列形式。
本申请的实施例还提供一种显示面板的制备方法，所述显示面板具有过渡显示区，包括以下步骤：
步骤S10：提供衬底；
步骤S20：在所述衬底上制备有源层及覆盖所述有源层的绝缘层；
步骤S30：制备虚拟孔。
其中，所述虚拟孔位于所述过渡显示区内，所述第一虚拟孔贯穿所述绝缘层的远离所述有源层的部分，所述显示面板包括位于所述过渡显示区的多个辅像素驱动电路，每一所述辅像素驱动电路包括晶体管，所述晶体管包括所述有源层。
可选地，为使所述虚拟孔进一步改善所述辅像素驱动电路电性均一性，在所述步骤S30后还包括步骤S40：对所述显示面板进行脱氢处理。请继续参阅图4，其为本申请的实施例提供的设置所述虚拟孔改善晶体管电性能的原理图。由于在脱氢处理制程中，所述有源层与所述绝缘层的交界面同时存在两种机制，一是Si-H键断键，H结合H 2溢出；二是自由态H与Si-悬空键结合成键。而第一种机制发生的概率大于第二种机制发生的概率。因此，所述虚拟孔的开孔密度决定了所述界面自由态H浓度。所述虚拟孔的开孔密度越大，自由态H形成H 2溢出的速度越快，使得第二种机制发生的概率越低，即自由态H与界面处Si-悬空键结合成键的概率越低。从而导致所述有源层与所述绝缘层的交界面处的缺陷态密度增大，继而使得所述晶体管的亚阈值摆幅增大，降低了流经所述晶体管源极和漏极的电流对所述晶体管的栅源电压波动的敏感度，降低所述晶体管的栅源电压波动对流经所述晶体管源极和漏极的电流的影响。
进一步地，所述绝缘层包括第一绝缘层和第二绝缘层，所述步骤S20还包 括：
步骤S21：制备覆盖所述有源层的所述第一绝缘层；
步骤S22：制备第一电极层，所述第一电极层包括第一走线部和与所述有源层对位设置的第一电极部；
步骤S23：制备覆盖所述第一电极层的所述第二绝缘层；
其中，所述虚拟孔贯穿所述第一绝缘层、所述第二绝缘层与所述有源层、所述第一电极层及所述第二电极层无重叠的部分。
进一步地，在所述步骤S23后还包括：
步骤S24：制备第三电极层及覆盖所述第三电极层的所述第三绝缘层。
其中，所述虚拟孔贯穿所述第一绝缘层、所述第二绝缘层、所述第三绝缘层与所述有源层、所述第一电极层及所述第二电极层无重叠的部分。
进一步地，在所述步骤S30后还包括：
步骤S50：在所述绝缘层上制备第二电极层，所述第二电极层包括第二走线部和与所述有源层电性连接的第二电极部；
步骤S60：制备平坦层，所述平坦层包括位于所述虚拟孔内的填充部；
其中，所述虚拟孔贯穿所述绝缘层与所述第二电极层无重叠的部分。
进一步地，所述显示面板的制备方法还包括制备辅子像素、封装层等多个制程工序，在此不再进行赘述。
本申请的实施例还提供一种显示装置，包括上述任一所述的显示面板。
进一步地，所述显示装置包括固定终端如电视、台式电脑，移动终端如手机、笔记本电脑，以及可穿戴设备如手环、VR(虚拟显示)设备、AR(增强显示)设备。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (17)

  1. 一种显示面板，其中，所述显示面板包括显示透光区及位于所述显示透光区外围的过渡显示区，所述显示面板包括：
    多个辅像素驱动电路，位于所述过渡显示区内，每一所述辅像素驱动电路包括晶体管，所述晶体管包括有源层以及位于所述有源层上的绝缘层；
    多个辅子像素，位于所述显示透光区内，所述辅子像素电性连接于所述辅像素驱动电路；
    其中，所述显示面板在所述过渡显示区内设有第一虚拟孔，所述第一虚拟孔贯穿所述绝缘层的远离所述有源层的部分。
  2. 根据权利要求1所述的显示面板，其中，还包括位于所述过渡显示区内的多个像素电路驱动岛，每一所述像素电路驱动岛包括多个所述辅像素驱动电路，所述第一虚拟孔包括多个第一子虚拟孔，每一所述第一子虚拟孔位于对应的相邻两所述像素电路驱动岛之间。
  3. 根据权利要求2所述的显示面板，其中，每一所述像素电路驱动岛具有长度方向，每一辅像素驱动电路在所述长度方向上具有第一长度，位于相邻两所述像素电路驱动岛之间的多个所述第一子虚拟孔具有第二长度；其中，所述第二长度大于所述第一长度，所述第二长度等于多个所述第一子虚拟孔中位于首端的所述第一子虚拟孔与位于末端的所述第一子虚拟孔在所述长度方向上的距离。
  4. 根据权利要求3所述的显示面板，其中，所述第二长度大于或等于所述第一长度的2倍。
  5. 根据权利要求2所述的显示面板，其中，所述第一虚拟孔包括位于所述像素电路驱动岛的靠近所述显示透光区一侧的多个第二子虚拟孔。
  6. 根据权利要求5所述的显示面板，其中，多个所述第二子虚拟孔的行数和/或列数大于或等于4。
  7. 根据权利要求2所述的显示面板，其中，还包括位于所述过渡显示区远离所述显示透光区的一侧的主显示区，所述第一虚拟孔包括位于所述像素电路驱动岛的靠近所述主显示区一侧的多个第三子虚拟孔。
  8. 根据权利要求7所述的显示面板，其中，还包括位于所述主显示区的 多个主子像素及驱动多个所述主子像素发光的多个主像素驱动电路；其中，每一所述主像素驱动电路设有多个过孔，在俯视视角下，多个所述第一虚拟孔的排列方式与多个所述过孔的排列方式相同，或多个所述第一虚拟孔呈矩阵排列。
  9. 根据权利要求2所述的显示面板，其中，还设有位于所述过渡显示区内的第二虚拟孔，所述第二虚拟孔位于所述像素电路驱动岛靠近所述显示透光区的一侧，所述第二虚拟孔贯穿所述绝缘层，所述第二虚拟孔的孔径大于所述第一虚拟孔的孔径。
  10. 根据权利要求1所述的显示面板，其中，还设有位于所述过渡显示区内的第三虚拟孔，所述第三虚拟孔贯穿所述绝缘层，所述第三虚拟孔的深度大于或小于所述第一虚拟孔的深度。
  11. 根据权利要求1所述的显示面板，其中，所述晶体管还包括：
    第一绝缘层，位于所述有源层上；
    第一电极层，位于所述第一绝缘层上，所述第一电极层包括第一走线部和与所述有源层对位设置的第一电极部；
    第二绝缘层，位于所述第一电极层上，
    第二电极层，位于所述第二绝缘层上，所述第二电极层包括第二走线部和与所述有源层电性连接的第二电极部；
    其中，所述绝缘层包括所述第一绝缘层和所述第二绝缘层，所述第一虚拟孔不贯穿所述有源层、所述第一电极层和所述第二电极层。
  12. 根据权利要求1所述的显示面板，其中，还包括位于所述绝缘层远离所述有源层一侧的平坦层，所述平坦层包括位于所述第一虚拟孔内的填充部。
  13. 根据权利要求1所述的显示面板，其中，所述第一虚拟孔的孔径大于或等于2微米且小于或等于3.5微米，相邻的两个所述虚拟孔之间的距离大于或等于2微米且小于或等于5微米。
  14. 根据权利要求9所述的显示面板，其中，所述第二虚拟孔的孔径大于或等于4微米且小于或等于7微米，所述第二虚拟孔与所述第一虚拟孔的孔径之差大于或等于1微米且小于或等于4.5微米。
  15. 根据权利要求1所述的显示面板，其中，所述辅子像素包括有机发光 二极管、微型发光二极管、次毫米发光二极管。
  16. 根据权利要求1所述的显示面板，其中，所述第一虚拟孔经脱氢处理后制备得到。
  17. 一种显示装置，其中，包括如权利要求1～16任一所述的显示面板。
PCT/CN2021/078086 2021-01-21 2021-02-26 显示面板及显示装置 WO2022156039A1 (zh)

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