WO2024021011A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2024021011A1
WO2024021011A1 PCT/CN2022/108922 CN2022108922W WO2024021011A1 WO 2024021011 A1 WO2024021011 A1 WO 2024021011A1 CN 2022108922 W CN2022108922 W CN 2022108922W WO 2024021011 A1 WO2024021011 A1 WO 2024021011A1
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WIPO (PCT)
Prior art keywords
display
area
conductive layer
display substrate
substrate
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PCT/CN2022/108922
Other languages
English (en)
French (fr)
Inventor
徐海峰
王子峰
王文涛
王利娜
王培�
侯耀达
唐庆
刘原涛
曹鑫
谢艳春
Original Assignee
京东方科技集团股份有限公司
绵阳京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 绵阳京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/108922 priority Critical patent/WO2024021011A1/zh
Priority to CN202280002454.5A priority patent/CN117795412A/zh
Publication of WO2024021011A1 publication Critical patent/WO2024021011A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a display substrate and a display device.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate having a display area, an edge area provided at least on one side of the display area, and a transition area provided between the display area and the edge area;
  • the display substrate includes: a substrate, a plurality of sub-pixels and redundant wiring located on the substrate; the plurality of sub-pixel arrays are arranged in the display area; the redundant wiring is along the sub-pixel The column direction extends and runs through the transition zone;
  • Each of the sub-pixels includes: a pixel driving circuit; the pixel driving circuit includes: a storage capacitor;
  • At least part of the second plate of the storage capacitor extends from the display area to the transition area and is electrically connected to the redundant wiring.
  • the second plate of the storage capacitor in a column of sub-pixels close to the transition region is electrically connected to the redundant wiring.
  • the second plate of the storage capacitor in a column of sub-pixels close to the transition region includes: a main body part and a protruding part connected to the main body part; the protruding part and the redundant Trace electrical connections.
  • the length of the projection of the protruding portion on the base along the column direction is 1/2 to 1/3 of the length of the orthographic projection of the main body portion on the base along the column direction;
  • the length of the orthographic projection of the protrusion on the substrate along the row direction is 2 to 4 times the length of the orthographic projection of the redundant trace on the substrate along the row direction.
  • the display substrate further includes: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer located on the substrate and sequentially arranged in a direction away from the substrate;
  • the second conductive layer includes: a second plate of the storage capacitor
  • the third conductive layer includes: the redundant wiring.
  • the display substrate further includes: a plurality of first transition portions located on the substrate and disposed in the edge area, and a plurality of first transition portions extending from the edge area through the transition area to the display area.
  • the pixel driving circuit also includes: a plurality of thin film transistors;
  • Part of the first adapter part is electrically connected to the gate electrode of part of the thin film transistor through the scanning signal line;
  • Part of the first transfer part is electrically connected to the gate electrode of part of the thin film transistor through the light emission control signal line;
  • Part of the first transfer part is electrically connected to the gate electrode of part of the thin film transistor through the reset signal line.
  • the first conductive layer includes: the scanning signal line, the plurality of first transfer parts, the gate electrode of the thin film transistor, the plurality of light emission control signal lines, and the plurality of Reset at least one of the signal lines.
  • the display substrate further includes: a plurality of first initialization signal lines and a plurality of second initialization signal lines located on the substrate and extending from the edge area to the display area through the transition area;
  • Part of the first transfer part is electrically connected to part of the first pole or the second pole of the thin film transistor through the plurality of first initialization signal lines or the plurality of second initialization signal lines.
  • the second conductive layer further includes: the plurality of first initialization signal lines and the plurality of second initialization signal lines;
  • the third conductive layer also includes: a first electrode and a second electrode of the thin film transistor.
  • first switching parts are electrically connected through first switching wires
  • the third conductive layer further includes: the first transfer wiring.
  • the display substrate further includes: a plurality of data signal lines located on the substrate and disposed in the display area;
  • the data signal is electrically connected to the first pole or the second pole of part of the thin film transistor
  • the third conductive layer also includes: the plurality of data signal lines.
  • the display substrate further has an imaging device area disposed in the display area; in the imaging device area, part of the data signal lines are electrically connected through second transfer lines;
  • the third conductive layer also includes: the second transfer wiring.
  • the display substrate further includes: a plurality of second transfer portions and bonding traces located on the substrate and disposed in the edge area; the second transfer portions are disposed on the first The side of the adapter part away from the display area;
  • the second transfer part and the first transfer part are electrically connected through the bonding wire.
  • the third conductive layer further includes: the plurality of second transfer portions and the bonding traces.
  • an embodiment of the present disclosure provides a display device, wherein the display device includes the display substrate provided as above.
  • Figure 1 is a schematic structural diagram of an exemplary display substrate
  • Figure 2 is a schematic structural diagram of an exemplary pixel driving circuit
  • Figure 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, the source , the drain is no different. In the embodiment of the present disclosure, in order to distinguish the source electrode and the drain electrode of the transistor, one electrode is called the first electrode, the other electrode is called the second electrode, and the gate electrode is called the control electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor.
  • Figure 1 is a schematic structural diagram of an exemplary display substrate.
  • the display substrate has a display area, an edge area disposed at least on one side of the display area, and a transition disposed between the display area and the edge area. area; wherein, the display substrate includes: a substrate 101, a plurality of sub-pixels P located on the substrate 101 and arranged in an array in the display area; each sub-pixel P includes: a pixel driving circuit; the pixel driving circuit includes: a plurality of thin film transistors and memory Capacitor C; the display substrate also includes: a plurality of first transition portions 102 located on the substrate 101 and disposed in the edge area, and a plurality of signal transmission lines extending from the edge area through the transition area to the display area.
  • the signal transmission lines may be the scanning signal line S1, the light emission control signal line EM, the first initialization signal line INIT1, and the second initialization signal line INIT2.
  • FIG. 2 is a schematic structural diagram of an exemplary pixel driving circuit.
  • the pixel driving circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor.
  • the third transistor T3 is a driving transistor configured to control the brightness of the light emitting device OLED by controlling the current flowing through the transistor.
  • the node connected to the gate of the third transistor is the first node N1, the node connected to the third transistor T3 and the fourth transistor T4 is the second node N2, and the node connected to the second transistor T2 and the third transistor T3 is the third node N3. .
  • the first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, the control electrode of the first transistor T1 is connected to the first reset signal line Re1, and the second electrode of the first transistor T1 is connected to the first node N1; when the conductor When the on-level scanning signal is applied to the first reset signal line Re1, the first transistor T1 transmits the first initialization signal to the control electrode of the third transistor T3 to initialize the voltage of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the scanning signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3; when the conductor When the on-level scanning signal is applied to the scanning signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the first node N1. That is, the control electrode of the third transistor T3 is connected to the second plate of the storage capacitor C. The first electrode of the third transistor T3 is connected to the second node N2. The second pole of the transistor T3 is connected to the third node N3.
  • the third transistor T3 determines the driving current value flowing between the first electrode and the second electrode of the light-emitting device OLED according to the potential difference between its control electrode and the first electrode, so as to drive the light-emitting device OLED to emit light.
  • the first electrode of the fourth transistor T4 is connected to the data signal line DATA
  • the second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3
  • the control electrode of the fourth transistor T4 is connected to the scanning signal line S1; when the conductor When the on-level scanning signal is applied to the scanning signal line S1, the fourth transistor T4 is configured to input the data voltage provided by the data signal line DATA to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal control line EM, the first electrode of the fifth transistor T5 is connected to the first power signal line VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3. , that is, the second electrode of the fifth transistor T5 is connected to the second node N2; the control electrode of the sixth transistor T6 is connected to the light-emitting signal control line EM, and the first electrode of the sixth transistor is connected to the second electrode of the third transistor T3, The second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device, and the first electrode of the sixth transistor T6 is connected to the third node N3.
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving current flows through the light-emitting device OLED, so that the light-emitting device OLED emits light.
  • the control electrode of the seventh transistor T7 is connected to the second reset signal line Re2, the first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.
  • the seventh transistor T7 transmits the second initialization signal to the first electrode of the light-emitting device to initialize the amount of charge accumulated in the first electrode of the light-emitting device or The amount of charge accumulated in the first pole of the light-emitting device is released.
  • the storage capacitor C has a first plate and a second plate C', the first plate is connected to the first power supply signal line VDD, and the second plate C' is connected to the first node N1. That is, the second plate C' of the storage capacitor C is connected to the control electrode of the third transistor T3.
  • the light-emitting device may be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be It is a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED), including a stacked first electrode (anode), a quantum dot light-emitting layer and a second electrode (cathode).
  • OLED organic light-emitting diode
  • QLED quantum dot Light Emitting Diodes
  • other types of light-emitting devices can also be used, which will not be listed one by one here.
  • the second pole of the light-emitting device is connected to the second power signal line VSS, the signal of the second power signal line VSS is a low-level signal, and the signal of the first power signal line VDD continuously provides a high-level signal.
  • the second reset signal line Re2 is Re(m)
  • the first reset signal line Re1 is Re(m-1)
  • the first reset signal line Re1 of this display row is the same as the pixel drive of the previous display row.
  • the second reset signal line Re2 in the circuit can be the same signal, which can reduce the number of signal lines of the display panel and achieve a narrow frame of the display panel.
  • each of the seven transistors in the pixel driving circuit may be a P-type transistor, or may be an N-type transistor.
  • the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polycrystalline silicon thin film transistors. .
  • the source and drain of a transistor can be symmetrical in structure, so there can be no difference in physical structure between the source and drain.
  • the transistors in addition to the gate electrode as the control electrode, one of them is directly described as the first electrode and the other as the second electrode. Therefore, in the embodiments of the present disclosure, the third electrode of all or part of the transistors is The first and second poles are interchangeable as needed.
  • the pixel driving circuit of the sub-pixel can also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, 6T2C structure or 9T2C structure, the embodiment of the present disclosure does not limit this.
  • the display substrate is generally provided with multiple conductive layers in sequence along the direction away from the substrate 101, for example, four conductive layers.
  • the four conductive layers are a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer.
  • the conductive layers may be respectively referred to as the first gate conductive layer Gate1, the second gate conductive layer Gate2, the first source-drain conductive layer SD1, and the second source-drain conductive layer SD2.
  • the data in the high-resolution display substrate Lines and power signal lines need to be routed using the second source-drain conductive layer SD2.
  • the first source-drain conductive layer SD1 only serves to transfer the data line DATA around the display area of the camera device.
  • a passivation layer needs to be formed on the first source-drain conductive layer SD1, and then a second source-drain conductive layer SD2 is formed on the passivation layer. Since the wiring density of the first source-drain conductive layer SD1 is greatly reduced, the effective transmission path of charges is reduced.
  • static electricity is released at a high rate, causing static electricity to be released from the signal transmission line to the devices in the display area.
  • the first path 1 is released along the scanning signal line S1
  • the second path 2 is released along the light emission control signal line EM
  • the third path 3 is released along the The first initialization signal line INIT1 is released
  • the fourth path 4 is released along the second initialization signal line INIT2.
  • first initialization signal line INIT1 is connected to the first electrode of the first transistor T1 and the second initialization signal line INIT2 is connected to the first electrode of the seventh transistor T7, both of which are electrically connected to the active layer of the corresponding thin film transistor, during electrostatic discharge During the process, static electricity can easily cause the active layers of the first transistor T1 and the seventh transistor T7 in the display area to be broken down by static electricity, affecting the display effect.
  • embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate and display device provided by the embodiments of the present disclosure will be further described in detail below with reference to the drawings and specific implementations.
  • an embodiment of the present disclosure provides a display substrate.
  • Figure 3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure. As shown in Figure 3, the display substrate has a display area and is at least disposed in the display area.
  • the display substrate includes: a substrate 101, a plurality of sub-pixels P and redundant wiring 103 located on the substrate 101; a plurality of sub-pixel P arrays Arranged in the display area; the redundant wiring 103 extends along the column direction of the sub-pixel P and runs through the transition area; each sub-pixel includes: a pixel driving circuit; the pixel driving circuit includes: a storage capacitor C; at least part of the second storage capacitor C The plate C′ extends from the display area to the transition area and is electrically connected to the redundant wiring 103 .
  • the substrate 101 can be made of rigid materials such as glass, which can improve the carrying capacity of other film layers on the substrate 101 .
  • the substrate 101 can also be made of flexible materials such as polyimide (PI), which can improve the bending resistance and tensile resistance of the entire display substrate and avoid the bending, stretching, and twisting processes. The stress causes the substrate 101 to break, resulting in poor circuit breaking.
  • the material of the substrate 101 can be reasonably selected according to actual needs to ensure that the display substrate has good performance.
  • the display substrate may include a plurality of sub-pixels P arranged in an array in the display area, and each adjacent sub-pixel P may emit light of different colors. For example, three adjacent sub-pixels can emit red light, green light and blue light respectively.
  • Each sub-pixel P may include a pixel driving circuit and a light-emitting device, wherein the structure of the pixel driving circuit may be the same as that shown in FIG. 3 .
  • the pixel driving circuit in each sub-pixel is respectively connected to the scanning signal line S1, the data signal line DATA, the light emission control signal line EM, the first initialization signal line INIT1, the second initialization signal line INIT2, etc.
  • the pixel driving circuit is connected to the scanning signal line S1 Under the control of the light-emitting control signal line EM, it receives the data voltage transmitted by the data signal line DATA and outputs a corresponding current to the light-emitting device.
  • the light-emitting device in each sub-pixel is connected to the pixel driving circuit respectively, and the light-emitting device can emit light with corresponding brightness according to the current output by the pixel driving circuit.
  • the redundant wiring 103 and the second plate C′ of the storage capacitor C can be made of metal materials with good electrical conductivity, such as at least one of copper, aluminum, molybdenum, and nickel.
  • the redundant wiring 103 and the second plate C′ of the storage capacitor C may adopt a single-layer structure made of one of the above-mentioned materials, or may adopt a multi-layer structure made of multiple of the above-mentioned materials.
  • the redundant wiring 103 can extend along the column direction of the sub-pixel P and penetrate the transition area, and the second plate C' of the storage capacitor C can extend from the display area to the transition area and be connected to the transition area. Redundant traces 103 are electrically connected. It can be seen that the extension direction of the redundant trace 103 intersects the extension direction of the second plate C' of the storage capacitor C, and the two can be electrically connected to form a mesh structure.
  • the cross-sectional area of the formed mesh structure is much larger than the cross-sectional area of the signal transmission line in the display substrate, so that the impedance of the formed mesh structure is much smaller than the impedance of the signal transmission line.
  • the network structure formed can be the optimal charge release path (i.e., the path 5 shown in the figure), which can prevent charges from being transmitted from other signal transmission lines to the devices in the display area, thereby avoiding Static electricity breaks down the active layer of the thin film transistor in the pixel driving circuit, thereby improving the display effect.
  • the formed network structure increases the path for electrostatic release, which can effectively release charges and avoid accumulation of a large amount of charges in the display substrate, thereby improving the display effect.
  • the second plate C′ of the storage capacitor C in a column of sub-pixels P close to the transition region is electrically connected to the redundant wiring 103.
  • the second plate C' of each storage capacitor C in the driving circuit of a column of sub-pixels P close to the transition region can be electrically connected to the redundant wiring 103
  • the second plate C' of each storage capacitor C in the column of sub-pixels P can be electrically connected to the redundant wiring 103.
  • the plate C' can form a mesh structure with the redundant wiring 103.
  • the cross-sectional area of the formed mesh structure is much larger than the cross-sectional area of the signal transmission line in the display substrate, so that the impedance of the formed mesh structure is It is much smaller than the impedance of the signal transmission line.
  • the network structure formed can be the optimal charge release path, which can prevent charges from being transmitted from other signal transmission lines to the devices in the display area, thereby preventing static electricity from damaging the thin film transistors in the pixel drive circuit.
  • the active layer breaks down, thereby improving the display effect.
  • the distance between a row of sub-pixels P close to the transition area and the redundant wiring 103 is relatively close, which facilitates wiring between the redundant wiring 103 and the second plate C' of each capacitor C, thus reducing the process difficulty. Save preparation costs.
  • the second plate C' of the storage capacitor C in other columns of sub-pixels P can also be used to be electrically connected to the redundant wiring 103, which will not be listed here.
  • the second plate C' of the storage capacitor C in a column of sub-pixels P close to the transition region includes: a main body part a and a protruding part b connected to the main body part a; the protruding part b is electrically connected to the redundant wiring 103.
  • the main body part a of the second plate C' of the storage capacitor C can overlap with the first plate to store charges.
  • the protruding portion b extends toward the transition area to electrically connect with the redundant trace 103 .
  • the length of the projection of the protruding portion b on the base 101 along the column direction is 1/2 to 1 of the length of the orthographic projection of the main body portion a on the base 101 along the column direction. /3;
  • the length of the orthographic projection of the protrusion b on the substrate 101 along the row direction is 2 to 4 times the length of the orthographic projection of the redundant trace 103 on the substrate 101 along the row direction.
  • the length of the protruding portion b in the column direction can be slightly smaller than the length of the main body portion a in the column direction to avoid overlap between the protruding portion b and other signal traces, causing short circuits and affecting the performance of the display substrate.
  • the length of the protruding part b in the row direction is greater than the length of the redundant wiring 103 in the row direction, so as to facilitate the overlap between the protruding part b and the redundant wiring 103 and avoid affecting the transmission of charges due to poor contact between the two. path.
  • the display substrate further includes: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer located on the substrate 101 and sequentially arranged in a direction away from the substrate 101; the second conductive layer includes : the second plate C' of the storage capacitor C; the third conductive layer includes: redundant wiring 103.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be respectively referred to as the first gate conductive layer Gate1, the second gate conductive layer Gate2, the first source-drain conductive layer SD1 and the second source Drain conductive layer SD2.
  • the second plate C' of the storage capacitor C can be wired using the second gate conductive layer Gate2, and the redundant wiring 103 can be wired using the first source-drain conductive layer SD1.
  • An insulation layer is provided between the redundant trace 103 and the second plate C′ of the storage capacitor C, and the two are electrically connected through a via hole penetrating the insulation layer.
  • the setting of the redundant wiring 103 does not affect the wiring of other signal transmission lines. At the same time, it also affects the narrow frame and high resolution of the display substrate. Structural design.
  • the display substrate further includes: a plurality of first transition portions 102 located on the substrate 101 and disposed in the edge area, and a plurality of scanning signal lines S1 extending from the edge area through the transition area to the display area.
  • the pixel driving circuit also It includes: a plurality of thin film transistors; part of the first adapter part 102 is electrically connected to the gate electrodes of some thin film transistors through the scanning signal line S1; part of the first adapter part 102 is electrically connected to the gate electrodes of part of the thin film transistors through the light emission control signal line EM. Connection; part of the first switching part 102 is electrically connected to the gate electrode of part of the thin film transistor through the reset signal line Re.
  • Part of the first adapter 102 can transmit the scanning signal provided by the gate driving circuit, which can be electrically connected to the scanning signal line S1 and transmitted to the gate of the second transistor T2 in the display area through the scanning signal line S1.
  • the cross-sectional area of the mesh structure formed by the redundant wiring 103 and the second plate C' of the storage capacitor C is much larger than the cross-sectional area of the scanning signal line S1 in the display substrate, so that the mesh structure formed
  • the impedance is much smaller than the impedance of the scanning signal line S1.
  • the network structure formed can be an optimal charge release path, which can prevent charges from being transferred from the scanning signal line S1 to the devices in the display area, thereby preventing static electricity from affecting the second device in the pixel driving circuit.
  • Transistor T2 has an impact, which can improve the display effect.
  • Part of the first adapter 102 can transmit the light-emitting control signal provided by the gate driving circuit, which can be electrically connected to the light-emitting control signal line EM, and transmitted to the gate of the fifth transistor T5 in the display area through the light-emitting control signal line EM. and the gate of the sixth transistor T6.
  • the cross-sectional area of the mesh structure formed by the redundant wiring 103 and the second plate C' of the storage capacitor C is much larger than the cross-sectional area of the light-emitting control signal line EM in the display substrate, so that the formed mesh structure
  • the impedance of the structure is much smaller than the impedance of the light-emitting control signal line EM.
  • the network structure formed can be the optimal charge release path, which can prevent charges from being transferred from the light-emitting control signal line EM to the devices in the display area, thereby avoiding the impact of static electricity on the third device in the pixel driving circuit.
  • the five transistors T5 and the sixth transistor T6 have an impact, thereby improving the display effect.
  • the reset signal line Re can be specifically divided into a first reset signal line Re1 and a second reset signal line Re2, which are connected to the gate of the first transistor T1 and the gate of the seventh transistor T7 respectively.
  • Part of the first adapter 102 can transmit a reset signal provided by the gate driving circuit, which can be electrically connected to the reset signal line Re, and transmitted to the gate of the first transistor T1 and the seventh transistor T1 in the display area through the reset signal line Re. Gate of transistor T7.
  • the cross-sectional area of the mesh structure formed by the redundant wiring 103 and the second plate C' of the storage capacitor C is much larger than the cross-sectional area of the reset signal line Re in the display substrate, so that the mesh structure formed
  • the impedance of is much smaller than the impedance of the reset signal line Re.
  • the network structure formed can be the optimal charge release path, which can avoid the transfer of charges from the reset signal line Re to the devices in the display area, thereby avoiding the impact of static electricity on the first device in the pixel driving circuit.
  • the transistor T1 and the seventh transistor T7 have an impact, thereby improving the display effect.
  • the first conductive layer includes: at least one of the scanning signal line S1, a plurality of first transition portions 102, a gate electrode of a thin film transistor, a plurality of light emission control signal lines EM, and a plurality of reset signal lines Re.
  • the scanning signal line S1 a plurality of first transition portions 102
  • a gate electrode of a thin film transistor a plurality of light emission control signal lines EM
  • a plurality of reset signal lines Re Re.
  • the scanning signal line S1, the first connecting portion 102 and the gate of the thin film transistor can all be wired using the first conductive layer, that is, the first gate conductive layer Gate1.
  • the scanning signal line S1, the first transfer part 102 and the gate electrode of the thin film transistor can be made of the same material and formed by the same process, which can reduce process steps and save manufacturing costs.
  • the plurality of light emission control signal lines EM can be wired using the first conductive layer, that is, the first gate conductive layer Gate1.
  • the multiple light-emitting control signal lines EM, the scanning signal line S1, the first transfer part 102 and the gate electrode of the thin film transistor can be made of the same material and formed by the same process, which can reduce process steps and save manufacturing costs.
  • the multiple reset signal lines Re can be wired using the first conductive layer, that is, the first gate conductive layer Gate1.
  • the multiple reset signal lines Re, the multiple light-emitting control signal lines EM, the scanning signal line S1, the first transfer part 102 and the gate electrode of the thin film transistor can be made of the same material and formed by the same process, which can reduce process steps and save manufacturing costs. .
  • the display substrate further includes: a plurality of first initialization signal lines INIT1 and a plurality of second initialization signal lines INIT2 located on the substrate 101 and extending from the edge area to the display area through the transition area; part of the first transition The part 102 is electrically connected to the first pole or the second pole of some thin film transistors through a plurality of first initialization signal lines INIT1 or a plurality of second initialization signal lines INIT2.
  • the first initialization signal line INIT1 and the second initialization signal line INIT2 are respectively connected to the gate electrode of the first transistor T1 and the source electrode (or drain electrode) of the seventh transistor T7.
  • Part of the first adapter 102 can transmit the initialization signal provided by the gate driving circuit, which can be electrically connected to the first initialization signal line INIT1 and the second initialization signal line INIT2, and pass through the first initialization signal line INIT1 and the second initialization signal
  • the line INIT2 is transmitted to the source (or drain) of the first transistor T1 and the source (or drain) of the seventh transistor T7 in the display area.
  • the cross-sectional area of the mesh structure formed by the redundant wiring 103 and the second plate C' of the storage capacitor C is much larger than the cross-section of the first initialization signal line INIT1 and the second initialization signal line INIT2 in the display substrate. area, so that the impedance of the formed mesh structure is much smaller than the impedance of the first initialization signal line INIT1 and the second initialization signal line INIT2.
  • the formed network structure can be an optimal charge release path, which can prevent charges from being transferred from the first initialization signal line INIT1 and the second initialization signal line INIT2 to the devices in the display area, thereby avoiding Static electricity breaks down the active layers of the first transistor T1 and the second transistor T7, thereby improving the display effect.
  • the second conductive layer further includes: a plurality of first initialization signal lines INIT1 and a plurality of second initialization signal lines INIT2; the third conductive layer further includes: a first pole and a second pole of a thin film transistor.
  • the plurality of first initialization signal lines INIT1 and the plurality of second initialization signal lines INIT2 can be wired using the second conductive layer, that is, the second gate conductive layer Gate2.
  • the plurality of first initialization signal lines INIT1, the plurality of second initialization signal lines INIT2 and the second plate C' of the storage capacitor C can be made of the same material and produced by the same process, which can reduce process steps and save preparation costs.
  • the first and second electrodes of the thin film transistor can be wired using the third conductive layer, that is, the first source-drain conductive layer SD1, which and the redundant wiring 103 can be made of the same material and formed by the same process, which can reduce process steps and save money. Preparation costs.
  • first transfer portions 102 are electrically connected through first transfer wires 104; the third conductive layer also includes: first transfer wires 104.
  • the timing of some of the signals transmitted by the first switching part 102 is the same, for example, the lighting control signal.
  • the timing of the lighting control signal input to the fifth transistor T5 and the sixth transistor T6 is the same.
  • the timing of the transmitted signal can be
  • the same first switching parts 102 are electrically connected together through the first switching wires 104 .
  • the first transfer wiring 104 can be wired using the third conductive layer, that is, the first source-drain conductive layer SD1. It can be made of the same material as the source and drain electrodes of the thin film transistor and formed by the same process, which can reduce process steps and save money. Preparation costs.
  • the display substrate further includes: a plurality of data signal lines DATA (not shown in FIG. 4 ) located on the substrate 101 and disposed in the display area; the data signal DATA and the first or second electrodes of some thin film transistors. The electrodes are electrically connected; the third conductive layer also includes: a plurality of data signal lines DATA.
  • DATA data signal lines
  • the data signal line DATA can be electrically connected to the first pole or the second pole of the second transistor T2, and can input the data signal through the second transistor T2 to the second node N2, that is, the source of the third transistor T3, to control the third transistor T3.
  • the opening degree of the three transistors T3 controls the current in the light-emitting device, thereby controlling the brightness of the light-emitting device.
  • the multiple data signal lines DATA can be wired using the third conductive layer, that is, the first source-drain conductive layer SD1, which can be made of the same material as the source and drain electrodes of the thin film transistor and formed by the same process, which can reduce process steps and save preparation. cost.
  • the display substrate also has a camera device area (not shown in the figure) disposed in the display area; in the camera device area, part of the data signal line DATA passes through the second transfer wiring (not shown in the figure) ) is electrically connected; the third conductive layer also includes: a second transfer trace.
  • the second transfer trace can be routed using the third conductive layer, that is, the first source-drain conductive layer SD1. It can be made of the same material as the source and drain electrodes of the thin film transistor and formed by the same process, which can reduce process steps and save preparation. cost.
  • Figure 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the display substrate also includes: a plurality of second transfer portions 105 and bonding parts located on the substrate 101 and disposed in the edge area.
  • the wiring 106; the second switching part 105 is provided on the side of the first switching part 102 away from the display area; the second switching part 105 and the first switching part 102 are electrically connected through the bonding wiring 106.
  • the second transfer part 105 may be an transfer part in the gate drive circuit, and the second transfer part 105 and the first transfer part 102 may be electrically connected through the bonding wire 106, so that the gate drive circuit provides The signal is transmitted to the signal line in the display through the second adapter part 105, the bonding wire 106 and the first adapter part 102.
  • the second bonding trace 106 can provide an electrostatic discharge path to release charges to the edge area (ie, the path 6 shown in the figure), which can prevent charges from being transmitted from other signal transmission lines to devices in the display area, thereby This is to prevent static electricity from breaking down the active layer of the thin film transistor in the pixel driving circuit, thereby improving the display effect.
  • the second bonding trace 106 increases the path for electrostatic discharge, which can effectively release charges and avoid accumulation of a large amount of charges in the display substrate, thereby improving the display effect.
  • the third conductive layer further includes: a plurality of second transfer portions 105 and bonding traces 106 .
  • the plurality of second transfer portions 105 and the bonding traces 106 can be wired using the third conductive layer, that is, the first source-drain conductive layer SD1, and it is not necessary to use the original fourth conductive layer, that is, the second source-drain electrode layer SD2. Wiring can prevent charges from being transmitted from other signal transmission lines to devices in the display area, thereby preventing static electricity from breaking down the active layer of the thin film transistor in the pixel driving circuit, thereby improving the display effect.
  • the display substrate further includes: a gate drive circuit (not shown in the figure) located on the substrate and disposed in the edge area; the gate drive circuit is disposed on a side of the second transfer portion 105 away from the display area. ;
  • the gate drive circuit includes: a plurality of thin film transistors; the channel area width to length ratio of the active layer of the thin film transistor in the gate drive circuit is greater than the channel area width to length ratio of the active layer of the thin film transistor in the pixel drive circuit .
  • the channel area width to length ratio of the active layer of the thin film transistor in the gate drive circuit is greater than the channel area width to length ratio of the active layer of the thin film transistor in the pixel drive circuit, and its withstand capacity for electrostatic discharge is greater, even if The charge is conducted to the thin film transistor in the gate driving circuit, and has little impact on the thin film transistor therein. This can prevent static electricity from breaking down the active layer of the thin film transistor in the pixel driving circuit, thereby improving the display effect.
  • an embodiment of the present disclosure provides a display device.
  • the display device includes the display substrate provided in any of the above embodiments.
  • the display device can be a mobile phone, a tablet computer, a television, a computer monitor, a notebook computer,
  • the implementation principles and beneficial effects of any products or components with display functions, such as digital photo frames and navigators, are the same as those of the above-mentioned display substrate, and will not be described again here.

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Abstract

本公开提供一种显示基板及显示装置，属于显示技术领域，其可解决现有的显示基板中电荷有效传输路径较少的问题。本公开的显示基板具有显示区、至少设置于显示区一侧的边缘区、及设置于显示区与边缘区之间的过渡区；其中，显示基板包括：基底、位于基底上的多个子像素及冗余走线；多个子像素阵列排布于显示区；冗余走线沿子像素的列方向延伸且贯穿过渡区；每个子像素包括：像素驱动电路；像素驱动电路包括：存储电容；至少部分存储电容的第二极板由显示区延伸至过渡区且与冗余走线电连接。

Description

显示基板及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种显示基板及显示装置。
背景技术
随着显示技术的不断发展，用户对显示画面的要求也越来越高，全面屏摄像头(Full Display Camera，FDC)技术应运而生。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供了一种显示基板及显示装置。
第一方面，本公开实施例提供了一种显示基板，具有显示区、至少设置于所述显示区一侧的边缘区、及设置于所述显示区与所述边缘区之间的过渡区；其中，所述显示基板包括：基底、位于所述基底上的多个子像素及冗余走线；所述多个子像素阵列排布于所述显示区；所述冗余走线沿所述子像素的列方向延伸且贯穿所述过渡区；
每个所述子像素包括：像素驱动电路；所述像素驱动电路包括：存储电容；
至少部分所述存储电容的第二极板由所述显示区延伸至所述过渡区且与所述冗余走线电连接。
可选地，靠近所述过渡区的一列所述子像素中的所述存储电容的第二极板与所述冗余走线电连接。
可选地，靠近所述过渡区的一列所述子像素中的所述存储电容的第二极板包括：主体部及与所述主体部连接的突出部；所述突出部与所述冗余走线 电连接。
可选地，所述突出部在所述基底上的投影沿列方向上的长度为所述主体部在所述基底上的正投影沿列方向上的长度的1/2至1/3；
所述突出部在所述基底上的正投影沿行方向上的长度为所述冗余走线在所述基底上的正投影沿行方向上的长度的2倍至4倍。
可选地，所述显示基板还包括：位于所述基底上且沿着背离所述基底方向依次设置的第一导电层、第二导电层、第三导电层和第四导电层；
所述第二导电层包括：所述存储电容的第二极板；
所述第三导电层包括：所述冗余走线。
可选地，所述显示基板还包括：位于所述基底上且设置于所述边缘区的多个第一转接部和由所述边缘区经所述过渡区延伸至所述显示区的多条扫描信号线、位于所述基底上且由所述边缘区经所述过渡区延伸至所述显示区的多条发光控制信号线、及位于所述基底上且由所述边缘区经所述过渡区延伸至所述显示区的多条复位信号线；所述像素驱动电路还包括：多个薄膜晶体管；
部分所述第一转接部通过所述扫描信号线与部分所述薄膜晶体管的栅极电连接；
部分所述第一转接部通过所述发光控制信号线与部分所述薄膜晶体管的栅极电连接；
部分所述第一转接部通过所述复位信号线与部分所述薄膜晶体管的栅极电连接。
可选地，所述第一导电层包括：所述扫描信号线、所述多个第一转接部、所述薄膜晶体管的栅极、所述多条发光控制信号线、及所述多条复位信号线中的至少一者。
可选地，所述显示基板还包括：位于所述基底上且由所述边缘区经所述 过渡区延伸至所述显示区的多条第一初始化信号线和多条第二初始化信号线；
部分所述第一转接部通过所述多条第一初始化信号线或所述多条第二初始化信号线与部分所述薄膜晶体管的第一极或第二极电连接。
可选地，所述第二导电层还包括：所述多条第一初始化信号线和所述多条第二初始化信号线；
所述第三导电层还包括：所述薄膜晶体管的第一极和第二极。
可选地，部分所述第一转接部之间通过第一转接走线电连接；
所述第三导电层还包括：所述第一转接走线。
可选地，所述显示基板还包括：位于所述基底上且设置于所述显示区的多条数据信号线；
所述数据信号与部分所述薄膜晶体管的第一极或第二极电连接；
所述第三导电层还包括：所述多条数据信号线。
可选地，所述显示基板还具有设置于所述显示区中的摄像器件区；在所述摄像器件区，部分所述数据信号线通过第二转接走线电连接；
所述第三导电层还包括：所述第二转接走线。
可选地，所述显示基板还包括：位于所述基底上且设置于所述边缘区的多个第二转接部和邦定走线；所述第二转接部设置于所述第一转接部远离所述显示区的一侧；
所述第二转接部与所述第一转接部通过所述邦定走线电连接。
可选地，所述第三导电层还包括：所述多个第二转接部和所述邦定走线。
第二方面，本公开实施例提供了一种显示装置，其中，所述显示装置包括如上述提供的显示基板。
附图说明
图1为一种示例性的显示基板的结构示意图；
图2为一种示例性的像素驱动电路的结构示意图；
图3为本公开实施例提供的一种显示基板的结构示意图；
图4为本公开实施例提供的另一种显示基板的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在此需要说明的是，本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型。当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源漏极导通，P型相反。可以想到的是采用P型晶体管 实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开实施例的保护范围内的。
图1为一种示例性的显示基板的结构示意图，如图1所示，该显示基板具有显示区、至少设置于显示区一侧的边缘区、及设置于显示区与边缘区之间的过渡区；其中，显示基板包括：基底101、位于基底101上且设置于显示区阵列排布的多个子像素P；每个子像素P包括：像素驱动电路；像素驱动电路包括：多个薄膜晶体管及存储电容C；显示基板还包括：位于基底101上且设置于边缘区的多个第一转接部102和由边缘区经过渡区延伸至显示区的多条信号传输线。具体地，信号传输线可以为扫描信号线S1、发光控制信号线EM、第一初始化信号线INIT1、第二初始化信号线INIT2。
图2为一种示例性的像素驱动电路的结构示意图，如图2所示，该像素驱动电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、存储电容C，发光器件OLED。其中，第三晶体管T3为驱动晶体管，被配置为通过控制流过该晶体管的电流大小来控制发光器件OLED的亮度。与第三晶体管栅极连接的节点为第一节点N1，第三晶体管T3与第四晶体管T4连接的节点为第二节点N2，第二晶体管T2与第三晶体管T3连接的节点为第三节点N3。
第一晶体管T1的第一极与第一初始化信号线INIT1连接，第一晶体管T1的控制极与第一复位信号线Re1连接，第一晶体管T1的第二极与第一节点N1连接；当导通电平扫描信号施加到第一复位信号线Re1时，第一晶体管T1将第一初始化信号传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电压初始化。
第二晶体管T2的控制极与扫描信号线S1连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三晶体管T3的第二极连接；当导通电平扫描信号施加到扫描信号线S1时，第二晶体管T2使第三 晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第一节点N1连接，即第三晶体管T3的控制极与存储电容C的第二极板连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3根据其控制极与第一极之间的电位差来确定在发光器件OLED的第一电极和第二电极之间流动的驱动电流值，以驱动发光器件OLED进行发光。
第四晶体管T4的第一极与数据信号线DATA连接，第四晶体管T4的第二极与第三晶体管T3的第二极连接，第四晶体管T4的控制极与扫描信号线S1连接；当导通电平扫描信号施加到扫描信号线S1时，第四晶体管T4被配置为将数据信号线DATA提供的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号控制线EM连接，第五晶体管T5的第一极与第一电源信号线VDD连接，第五晶体管T5的第二极与第三晶体管T3的第一极连接，即第五晶体管T5的第二极与第二节点N2连接；第六晶体管T6的控制极与发光信号控制线EM连接，第六晶体管的第一极与第三晶体管T3的第二极连接，第六晶体管T6的第二极与发光器件的第一电极连接，第六晶体管T6的第一极与第三节点N3连接。当导通电平发光信号施加到发光信号线EM时，第五晶体管T5和第六晶体管T6导通，驱动电流流过发光器件OLED，以使发光器件OLED发光。
第七晶体管T7的控制极与第二复位信号线Re2连接，第七晶体管T7的第一极与第二初始化信号线INIT2连接，第七晶体管T7的第二极与发光器件的第一电极连接。当导通电平扫描信号施加到第二复位信号线Re2时，第七晶体管T7将第二初始化信号传输到发光器件的第一极，以使发光器件的第一电极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
存储电容C具有第一极板和第二极板C’，第一极板与第一电源信号线 VDD连接，第二极板C’与第一节点N1连接。即存储电容C的第二极板C’与第三晶体管T3的控制极连接。
在示例性实施方式中，发光器件可以是有机电致发光二极管(Organic Light-Emitting Diode，OLED)，包括层叠设置的第一电极(阳极)、有机发光层和第二电极(阴极)，或者可以是量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)，包括层叠设置的第一电极(阳极)、量子点发光层和第二电极(阴极)。当然还可以为其他类型的发光器件，在此不再进行一一列举。
在示例性实施方式中，发光器件的第二极与第二电源信号线VSS连接，第二电源信号线VSS的信号为低电平信号，第一电源信号线VDD的信号为持续提供高电平信号。即对于第m显示行，第二复位信号线Re2为Re(m)，第一复位信号线Re1为Re(m-1)，本显示行的第一复位信号线Re1与上一显示行像素驱动电路中的第二复位信号线Re2可为同一信号，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，像素驱动电路中的七个晶体管均可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
在示例性实施方式中，子像素的像素驱动电路除了可以为上述的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
显示基板中一般沿着背离基底101的方向上依次设置有多层导电层，例如，四层导电层，四层导电层依次为第一导电层、第二导电层、第三导电层和第四导电层，可以分别称为第一栅极导电层Gate1、第二栅极导电层Gate2、第一源漏导电层SD1和第二源漏导电层SD2。在高分辨显示结合全面屏摄像头技术中，为了保证高分辨率和窄边框的要求，将在显示基板显示区边缘的冗余子像素取消，同时为了降低寄生电容，高分辨率的显示基板中数据线及电源信号线等需要利用第二源漏导电层SD2进行布线，第一源漏导电层SD1仅在摄像器件显示区周围起到转接数据线DATA的作用。
在显示基板的制备过程中，第一源漏导电层SD1形成后，需要在第一源漏导电层SD1上形成钝化层，之后再在钝化层上形成第二源漏导电层SD2。由于第一源漏导电层SD1的走线密度大幅降低，导致电荷有效传输路径减少，在钝化层制备工艺过程中静电释放高发，使得静电由信号传输线向显示区中的器件进行释放，例如图1中所示的四个路径，其中，第一条路径①为沿着扫描信号线S1进行释放，第二条路径②为沿着发光控制信号线EM进行释放，第三条路径③为沿着第一初始化信号线INIT1进行释放，第四条路径④为沿着第二初始化信号线INIT2进行释放。
由于第一初始化信号线INIT1连接第一晶体管T1的第一极，第二初始化信号线INIT2连接第七晶体管T7的第一极，其均与对应的薄膜晶体管的有源层电连接，在静电释放过程中，静电容易导致显示区中的第一晶体管T1和第七晶体管T7的有源层被静电击穿，影响显示效果。
为了至少解决上述的技术问题之一，本公开实施例提供了一种显示基板 及显示装置，下面将结合附图及具体实施方式对本公开实施例提供的显示基板及显示装置进行进一步详细描述。
第一方面，本公开实施例提供了一种显示基板，图3为本公开实施例提供的一种显示基板的结构示意图，如图3所示，该显示基板具有显示区、至少设置于显示区一侧的边缘区、及设置于显示区与边缘区之间的过渡区；其中，显示基板包括：基底101、位于基底101上的多个子像素P及冗余走线103；多个子像素P阵列排布于显示区；冗余走线103沿子像素P的列方向延伸且贯穿过渡区；每个子像素包括：像素驱动电路；像素驱动电路包括：存储电容C；至少部分存储电容C的第二极板C’由显示区延伸至过渡区且与冗余走线103电连接。
基底101可以采用玻璃等刚性材料制成，可以提高基底101对其上的其他膜层的承载能力。当然，基底101还可以采用聚酰亚胺(polyimide，PI)等柔性材料制成，可以提高显示基板整体的抗弯折、抗拉伸性能，避免在弯折、拉伸、扭曲过程中产生的应力使得基底101发生断裂，造成断路不良。在实际应用中，可以根据实际需要，合理选择基底101的材料，以保证显示基板具有良好的性能。
显示基板可以包括阵列方式排布于显示区的多个子像素P，且相邻的各个子像素可P可以发出不同颜色的光线。例如，相邻的三个子像素可以分别发出红色光线，绿色光线和蓝色光线。每个子像素P可以均包括像素驱动电路和发光器件，其中，像素驱动电路的结构可以与图3所示的结构相同。每个子像素中的像素驱动电路分别与扫描信号线S1、数据信号线DATA、发光控制信号线EM、第一初始化信号线INIT1、第二初始化信号线INIT2等连接，像素驱动电路在扫描信号线S1和发光控制信号线EM的控制下，接收数据信号线DATA传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与像素驱动电路连接，发光器件可以在像素驱动电路输 出的电流发出相应亮度的光。
冗余走线103和存储电容C的第二极板C’可以采用导电性能较好的金属材料制成，例如，铜、铝、钼、镍中的至少一种。冗余走线103和存储电容C的第二极板C’可以采用由上述的一种材料制成的单层结构，也可以采用由上述的多种材料制成的多层结构。
本公开实施例提供的显示基板中，冗余走线103可以沿着子像素P的列方向延伸且贯穿过渡区，存储电容C的第二极板C’可以由显示区延伸至过渡区且与冗余走线103电连接。可见，冗余走线103的延伸方向与存储电容C的第二极板C’的延伸方向相交，二者可以电连接形成网状结构。所形成的网状结构的横截面积要远远大于显示基板中的信号传输线的横截面积，使得所形成的网状结构的阻抗要远远小于信号传输线的阻抗。在静电释放过程中，所形成的网状结构可以为最优的电荷释放路径(即图中所示的路径⑤)，可以避免电荷由其他信号传输线传输至显示区中的器件中，从而以避免静电对像素驱动电路中的薄膜晶体管的有源层击穿，进而可以提高显示效果。同时，所形成的网状结构增加了静电释放的路径，可以将电荷进行有效释放，避免显示基板中积累大量的电荷，从而可以提高显示效果。
在一些实施例中，如图3所示，靠近过渡区的一列子像素P中的存储电容C的第二极板C’与冗余走线103电连接。
具体地，靠近过渡区的一列子像素P的驱动电路中的各个存储电容C的第二极板C’可以与冗余走线103电连接，该列子像素P中的各个存储电容C的第二极板C’可以与冗余走线103形成网状结构，所形成的网状结构的横截面积要远远大于显示基板中的信号传输线的横截面积，使得所形成的网状结构的阻抗要远远小于信号传输线的阻抗。在静电释放过程中，所形成的网状结构可以为最优的电荷释放路径，可以避免电荷由其他信号传输线传输至显示区中的器件中，从而以避免静电对像素驱动电路中的薄膜晶体管的有 源层击穿，进而可以提高显示效果。并且，靠近过渡区的一列子像素P与冗余走线103的距离较近，便于冗余走线103与各个电容C的第二极板C’之间的走线，从而可以降低工艺难度，节约制备成本。当然，也可以采用其他列子像素P中的存储电容C的第二极板C’与冗余走线103电连接，在此不在一一进行列举。
在一些实施例中，如图3所示，靠近过渡区的一列子像素P中的存储电容C的第二极板C’包括：主体部a及与主体部a连接的突出部b；突出部b与冗余走线103电连接。
存储电容C的第二极板C’的主体部a可以与第一极板之间相互交叠，以起到存储电荷的作用。突出部b向过渡区延伸，以与冗余走线103电连接。
在一些实施例中，如图3所示，突出部b在基底101上的投影沿列方向上的长度为主体部a在基底101上的正投影沿列方向上的长度的1/2至1/3；突出部b在基底101上的正投影沿行方向上的长度为冗余走线103在基底101上的正投影沿行方向上的长度的2倍至4倍。
突出部b在列方向上的长度可以稍小于主体部a在列方向上的长度，避免突出部b与其他信号走线之间相互交叠，造成短路，影响显示基板的性能。同时，突出部b在行方向上的长度要大于冗余走线103在行方向上的长度，以利于突出部b与冗余走线103之间搭接，避免由于二者接触不良，影响电荷的传输路径。
在一些实施例中，显示基板还包括：位于基底101上且沿着背离基底101方向依次设置的第一导电层、第二导电层、第三导电层和第四导电层；第二导电层包括：存储电容C的第二极板C’；第三导电层包括：冗余走线103。
第一导电层、第二导电层、第三导电层和第四导电层可以分别称为第一栅极导电层Gate1、第二栅极导电层Gate2、第一源漏导电层SD1和第二源漏导电层SD2。存储电容C的第二极板C’可以采用第二栅极导电层Gate2 进行布线，冗余走线103可以采用第一源漏导电层SD1进行布线。冗余走线103与存储电容C的第二极板C’之间设置有绝缘层，二者通过贯穿绝缘层的过孔电连接。由于显示基板中信号传输线并不采用第一源漏导电层SD1进行布线，冗余走线103的设置并不影响其他信号传输线的走线，同时也不同影响显示基板的窄边框及高分辨率的结构设计。
在一些实施例中，显示基板还包括：位于基底101上且设置于边缘区的多个第一转接部102和由边缘区经过渡区延伸至显示区的多条扫描信号线S1、位于基底101上且由边缘区经过渡区延伸至显示区的多条发光控制信号线EM、及位于基底101上且由边缘区经过渡区延伸至显示区的多条复位信号线Re；像素驱动电路还包括：多个薄膜晶体管；部分第一转接部102通过扫描信号线S1与部分薄膜晶体管的栅极电连接；部分第一转接部102通过发光控制信号线EM与部分薄膜晶体管的栅极电连接；部分第一转接部102通过复位信号线Re与部分薄膜晶体管的栅极电连接。
部分第一转接部102可以传输栅极驱动电路提供的扫描信号，其可以与扫描信号线S1电连接，并通过扫描信号线S1传输至显示区中的第二晶体管T2的栅极。冗余走线103与存储电容C的第二极板C’所形成的网状结构的横截面积要远远大于显示基板中的扫描信号线S1的横截面积，使得所形成的网状结构的阻抗要远远小于扫描信号线S1的阻抗。在静电释放过程中，所形成的网状结构可以为最优的电荷释放路径，可以避免电荷由扫描信号线S1传输至显示区中的器件中，从而以避免静电对像素驱动电路中的第二晶体管T2造成影响，进而可以提高显示效果。
部分第一转接部102可以传输栅极驱动电路提供的发光控制信号，其可以与发光控制信号线EM电连接，并通过发光控制信号线EM传输至显示区中的第五晶体管T5的栅极和第六晶体管T6的栅极。冗余走线103与存储电容C的第二极板C’所形成的网状结构的横截面积要远远大于显示基板中的 发光控制信号线EM的横截面积，使得所形成的网状结构的阻抗要远远小于发光控制信号线EM的阻抗。在静电释放过程中，所形成的网状结构可以为最优的电荷释放路径，可以避免电荷由发光控制信号线EM传输至显示区中的器件中，从而以避免静电对像素驱动电路中的第五晶体管T5和第六晶体管T6造成影响，进而可以提高显示效果。
复位信号线Re具体可以分为第一复位信号线Re1和第二复位信号线Re2，其分别连接第一晶体管T1的栅极和第七晶体管T7的栅极。部分第一转接部102可以传输栅极驱动电路提供的复位信号，其可以与复位信号线Re电连接，并通过复位信号线Re传输至显示区中的第一晶体管T1的栅极和第七晶体管T7的栅极。冗余走线103与存储电容C的第二极板C’所形成的网状结构的横截面积要远远大于显示基板中的复位信号线Re的横截面积，使得所形成的网状结构的阻抗要远远小于复位信号线Re的阻抗。在静电释放过程中，所形成的网状结构可以为最优的电荷释放路径，可以避免电荷由复位信号线Re传输至显示区中的器件中，从而以避免静电对像素驱动电路中的第一晶体管T1和第七晶体管T7造成影响，进而可以提高显示效果。
在一些实施例中，第一导电层包括：扫描信号线S1、多个第一转接部102、薄膜晶体管的栅极、多条发光控制信号线EM、及多条复位信号线Re中的至少一者。
扫描信号线S1、第一转接部102和薄膜晶体管的栅极均可以采用第一导电层即第一栅极导电层Gate1进行布线。扫描信号线S1、第一转接部102和薄膜晶体管的栅极可以采用相同材料，同一工艺制备形成，可以减少工艺步骤，节约制备成本。
多条发光控制信号线EM可以采用第一导电层即第一栅极导电层Gate1进行布线。多条发光控制信号线EM、扫描信号线S1、第一转接部102和薄膜晶体管的栅极可以采用相同材料，同一工艺制备形成，可以减少工艺步骤， 节约制备成本。
多条复位信号线Re可以采用第一导电层即第一栅极导电层Gate1进行布线。多条复位信号线Re、多条发光控制信号线EM、扫描信号线S1、第一转接部102和薄膜晶体管的栅极可以采用相同材料，同一工艺制备形成，可以减少工艺步骤，节约制备成本。
在一些实施例中，显示基板还包括：位于基底101上且由边缘区经过渡区延伸至显示区的多条第一初始化信号线INIT1和多条第二初始化信号线INIT2；部分第一转接部102通过多条第一初始化信号线INIT1或多条第二初始化信号线INIT2与部分薄膜晶体管的第一极或第二极电连接。
第一初始化信号线INIT1和第二初始化信号线INIT2分别连接第一晶体管T1的栅极和第七晶体管T7的源极(或漏极)。部分第一转接部102可以传输栅极驱动电路提供的初始化信号，其可以与第一初始化信号线INIT1和第二初始化信号线INIT2电连接，并通过第一初始化信号线INIT1和第二初始化信号线INIT2传输至显示区中的第一晶体管T1的源极(或漏极)和第七晶体管T7的源极(或漏极)。冗余走线103与存储电容C的第二极板C’所形成的网状结构的横截面积要远远大于显示基板中的第一初始化信号线INIT1和第二初始化信号线INIT2的横截面积，使得所形成的网状结构的阻抗要远远小于第一初始化信号线INIT1和第二初始化信号线INIT2的阻抗。在静电释放过程中，所形成的网状结构可以为最优的电荷释放路径，可以避免电荷由第一初始化信号线INIT1和第二初始化信号线INIT2传输至显示区中的器件中，从而以避免静电击穿第一晶体管T1和第二晶体管T7的有源层，进而可以提高显示效果。
在一些实施例中，第二导电层还包括：多条第一初始化信号线INIT1和多条第二初始化信号线INIT2；第三导电层还包括：薄膜晶体管的第一极和第二极。
多条第一初始化信号线INIT1和多条第二初始化信号线INIT2可以采用第二导电层即第二栅极导电层Gate2进行布线。多条第一初始化信号线INIT1、多条第二初始化信号线INIT2和存储电容C的第二极板C’可以采用相同材料，同一工艺制备形成，可以减少工艺步骤，节约制备成本。薄膜晶体管的第一极和第二极可以采用第三导电层即第一源漏导电层SD1进行布线，其与冗余走线103可以采用相同材料，同一工艺制备形成，可以减少工艺步骤，节约制备成本。
在一些实施例中，部分第一转接部102之间通过第一转接走线104电连接；第三导电层还包括：第一转接走线104。
部分第一转接部102所传输的信号的时序是相同的，例如发光控制信号，向第五晶体管T5和第六晶体管T6所输入的发光控制信号的时序是相同的，可以将传输的信号时序相同的第一转接部102通过第一转接走线104电连接在一起。第一转接走线104可以采用第三导电层即第一源漏导电层SD1进行布线，其可以与薄膜晶体管的源极及漏极采用相同材料，同一工艺制备形成，可以减少工艺步骤，节约制备成本。
在一些实施例中，显示基板还包括：位于基底101上且设置于显示区的多条数据信号线DATA(图4中未示出)；数据信号DATA与部分薄膜晶体管的第一极或第二极电连接；第三导电层还包括：多条数据信号线DATA。
数据信号线DATA可以与第二晶体管T2的第一极或第二极电连接，可以将数据信号输入通过第二晶体管T2输入至第二节点N2，即第三晶体管T3的源极，以控制第三晶体管T3的开启程度，来控制发光器件中的电流大小，从而控制发光器件的发光亮度。多条数据信号线DATA可以采用第三导电层即第一源漏导电层SD1进行布线，其可以与薄膜晶体管的源极及漏极采用相同材料，同一工艺制备形成，可以减少工艺步骤，节约制备成本。
在一些实施例中，显示基板还具有设置于显示区中的摄像器件区(图中 未示出)；在摄像器件区，部分数据信号线DATA通过第二转接走线(图中未示出)电连接；第三导电层还包括：第二转接走线。
在摄像器件区中，为了实现全面屏摄像头的显示效果，需要将其中的部分的数据信号线DATA通过第二转接走线进行电连接。第二转接走线可以采用第三导电层即第一源漏导电层SD1进行布线，其可以与薄膜晶体管的源极及漏极采用相同材料，同一工艺制备形成，可以减少工艺步骤，节约制备成本。
图4为本公开实施例提供的另一种显示基板的结构示意图，如图4所示，显示基板还包括：位于基底101上且设置于边缘区的多个第二转接部105和邦定走线106；第二转接部105设置于第一转接部102远离显示区的一侧；第二转接部105与第一转接部102通过邦定走线106电连接。
第二转接部可105可以为栅极驱动电路中的转接部，第二转接部105与第一转接部102可以通过邦定走线106电连接，以使得栅极驱动电路提供的信号通过第二转接部105、邦定走线106及第一转接部102传输至显示中的信号线。同时，第二绑定走线106可以提供静电释放路径，使得电荷向边缘区进行释放(即图中所示的路径⑥)，可以避免电荷由其他信号传输线传输至显示区中的器件中，从而以避免静电对像素驱动电路中的薄膜晶体管的有源层击穿，进而可以提高显示效果。同时，第二绑定走线106增加了静电释放的路径，可以将电荷进行有效释放，避免显示基板中积累大量的电荷，从而可以提高显示效果。
在一些实施例中，第三导电层还包括：多个第二转接部105和邦定走线106。
多个第二转接部105和邦定走线106可以采用第三导电层即第一源漏导电层SD1进行布线，可以不必采用原有的第四导电层即第二源漏电极层SD2进行布线，可以避免电荷由其他信号传输线传输至显示区中的器件中，从而 以避免静电对像素驱动电路中的薄膜晶体管的有源层击穿，进而可以提高显示效果。
在一些实施例中，显示基板还包括：位于基底上且设置于边缘区的栅极驱动电路(图中未示出)；栅极驱动电路设置于第二转接部105远离显示区的一侧；栅极驱动电路包括：多个薄膜晶体管；栅极驱动电路中的薄膜晶体管的有源层的沟道区宽长比大于像素驱动电路中的薄膜晶体管的有源层的沟道区宽长比。
栅极驱动电路中的薄膜晶体管的有源层的沟道区宽长比大于像素驱动电路中的薄膜晶体管的有源层的沟道区宽长比，其对静电释放的承受能力较大，即使电荷传导至栅极驱动电路中的薄膜晶体管中，对其中的薄膜晶体管的影响较小，可以避免静电对像素驱动电路中的薄膜晶体管的有源层击穿，进而可以提高显示效果。
第二方面，本公开实施例提供了一种显示装置，该显示装置包括如上述任一实施例提供的显示基板，该显示装置具体可以为手机、平板电脑、电视机、电脑显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，其实现原理及有益效果与上述的显示基板的实现原理及有益效果相同，在此不再进行赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种显示基板，具有显示区、至少设置于所述显示区一侧的边缘区、及设置于所述显示区与所述边缘区之间的过渡区；其中，所述显示基板包括：基底、位于所述基底上的多个子像素及冗余走线；所述多个子像素阵列排布于所述显示区；所述冗余走线沿所述子像素的列方向延伸且贯穿所述过渡区；
    每个所述子像素包括：像素驱动电路；所述像素驱动电路包括：存储电容；
    至少部分所述存储电容的第二极板由所述显示区延伸至所述过渡区且与所述冗余走线电连接。
  2. 根据权利要求1所述的显示基板，其中，靠近所述过渡区的一列所述子像素中的所述存储电容的第二极板与所述冗余走线电连接。
  3. 根据权利要求2所述的显示基板，其中，靠近所述过渡区的一列所述子像素中的所述存储电容的第二极板包括：主体部及与所述主体部连接的突出部；所述突出部与所述冗余走线电连接。
  4. 根据权利要求3所述的显示基板，其中，所述突出部在所述基底上的投影沿列方向上的长度为所述主体部在所述基底上的正投影沿列方向上的长度的1/2至2/3；
    所述突出部在所述基底上的正投影沿行方向上的长度为所述冗余走线在所述基底上的正投影沿行方向上的长度的2倍至4倍。
  5. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：位于所述基底上且沿着背离所述基底方向依次设置的第一导电层、第二导电层、第三导电层和第四导电层；
    所述第二导电层包括：所述存储电容的第二极板；
    所述第三导电层包括：所述冗余走线。
  6. 根据权利要求5所述的显示基板，其中，所述显示基板还包括：位 于所述基底上且设置于所述边缘区的多个第一转接部和由所述边缘区经所述过渡区延伸至所述显示区的多条扫描信号线、位于所述基底上且由所述边缘区经所述过渡区延伸至所述显示区的多条发光控制信号线、及位于所述基底上且由所述边缘区经所述过渡区延伸至所述显示区的多条复位信号线；所述像素驱动电路还包括：多个薄膜晶体管；
    部分所述第一转接部通过所述扫描信号线与部分所述薄膜晶体管的栅极电连接；
    部分所述第一转接部通过所述发光控制信号线与部分所述薄膜晶体管的栅极电连接；
    部分所述第一转接部通过所述复位信号线与部分所述薄膜晶体管的栅极电连接。
  7. 根据权利要求6所述的显示基板，其中，所述第一导电层包括：所述扫描信号线、所述多个第一转接部、所述薄膜晶体管的栅极、所述多条发光控制信号线、及所述多条复位信号线中的至少一者。
  8. 根据权利要求6所述的显示基板，其中，所述显示基板还包括：位于所述基底上且由所述边缘区经所述过渡区延伸至所述显示区的多条第一初始化信号线和多条第二初始化信号线；
    部分所述第一转接部通过所述多条第一初始化信号线或所述多条第二初始化信号线与部分所述薄膜晶体管的第一极或第二极电连接。
  9. 根据权利要求8所述的显示基板，其中，所述第二导电层还包括：所述多条第一初始化信号线和所述多条第二初始化信号线；
    所述第三导电层还包括：所述薄膜晶体管的第一极和第二极。
  10. 根据权利要求6所述的显示基板，其中，部分所述第一转接部之间通过第一转接走线电连接；
    所述第三导电层还包括：所述第一转接走线。
  11. 根据权利要求6所述显示基板，其中，所述显示基板还包括：位于 所述基底上且设置于所述显示区的多条数据信号线；
    所述数据信号与部分所述薄膜晶体管的第一极或第二极电连接；
    所述第三导电层还包括：所述多条数据信号线。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板还具有设置于所述显示区中的摄像器件区；在所述摄像器件区，部分所述数据信号线通过第二转接走线电连接；
    所述第三导电层还包括：所述第二转接走线。
  13. 根据权利要求6所述的显示基板，其中，所述显示基板还包括：位于所述基底上且设置于所述边缘区的多个第二转接部和邦定走线；所述第二转接部设置于所述第一转接部远离所述显示区的一侧；
    所述第二转接部与所述第一转接部通过所述邦定走线电连接。
  14. 根据权利要求13所述的显示基板，其中，所述第三导电层还包括：所述多个第二转接部和所述邦定走线。
  15. 一种显示装置，其中，所述显示装置包括如权利要求1至14任一项所述的显示基板。
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