WO2022188091A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022188091A1
WO2022188091A1 PCT/CN2021/080199 CN2021080199W WO2022188091A1 WO 2022188091 A1 WO2022188091 A1 WO 2022188091A1 CN 2021080199 W CN2021080199 W CN 2021080199W WO 2022188091 A1 WO2022188091 A1 WO 2022188091A1
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WIPO (PCT)
Prior art keywords
line
display area
control
data
test
Prior art date
Application number
PCT/CN2021/080199
Other languages
English (en)
French (fr)
Inventor
魏锋
周宏军
杜丽丽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to GB2215345.6A priority Critical patent/GB2609339A/en
Priority to US17/635,871 priority patent/US11839123B2/en
Priority to PCT/CN2021/080199 priority patent/WO2022188091A1/zh
Priority to CN202180000461.7A priority patent/CN115485756A/zh
Publication of WO2022188091A1 publication Critical patent/WO2022188091A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • circuit units such as pixel circuits, gate driver circuits (Gate Driver on Array, GOA), data selection circuits (Multiplexer, MUX) and test circuits ( Cell Test, CT), etc.
  • GOA Gate Driver on Array
  • MUX Multiplexer
  • CT Cell Test, CT
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate, a plurality of sub-pixels, a plurality of data lines, a control signal line, a plurality of data test lines, a test circuit and an auxiliary electrode line.
  • the base substrate includes a display area and a peripheral area at least on one side of the display area; a plurality of sub-pixels are located in the display area and are arranged in an array; a plurality of data lines are located in the display area and are configured to face the plurality of sub-pixels
  • the pixels provide data signals; the control signal lines are located in the peripheral area and on at least one side of the display area; a plurality of data test lines are located in the peripheral area and on at least one side of the display area; test circuits are located in the The peripheral area is electrically connected to the plurality of data lines, the control signal lines and the plurality of data test lines, and is configured to transmit test signals through the plurality of data test lines under the control of the control signal lines transmitted to the plurality
  • the first control line and the auxiliary electrode line are located in different layers relative to the base substrate, and the first control line and the auxiliary electrode line are located in different layers.
  • the lines are respectively located in the first conductive layer and the second conductive layer which are spaced apart and insulated from each other.
  • the auxiliary electrode line is located on a side of the test circuit far away from the display area or on a side close to the display area.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an electrostatic discharge circuit disposed between the test circuit and the display area, the electrostatic discharge circuit is electrically connected to the plurality of data lines, and the auxiliary Electrode lines are located between the test circuit and the electrostatic discharge circuit.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of connection lines, the plurality of connection lines are respectively disposed between the plurality of control switches, the first control line and the plurality of control switches
  • the active layer overlaps, and the overlapping portion of the first control line and the active layer forms the control ends of the plurality of control switches, the first ends of the plurality of connection lines and the first control line connected, and the second ends of the plurality of connecting lines are connected with the auxiliary electrode lines.
  • the plurality of data test lines extend along a first direction and are spaced apart along a second direction on a side of the test circuit away from the display area, so The first direction and the second direction intersect, and the first ends of the plurality of control switches are respectively connected to the plurality of data test lines correspondingly, and are configured to receive test signals provided by the plurality of data test lines, The second ends of the plurality of control switches are respectively electrically connected to the plurality of data lines.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of first lead segments and a plurality of data leads, and the plurality of first lead segments and the plurality of data leads extend along the second direction, so The plurality of first lead segments are respectively connected to the first ends of the plurality of data test lines and the plurality of control switches, and the plurality of data leads are respectively connected to the second ends of the plurality of control switches and all the control switches. multiple data lines.
  • the plurality of data leads include second lead segments, and the plurality of second lead segments are respectively connected to the second ends of the plurality of control switches and all the In the electrostatic discharge circuit, the plurality of first lead segments and the plurality of second lead segments are located in a third conductive layer, and the third conductive layer is located between the first conductive layer and the second conductive layer and insulated from each other, the orthographic projections of the plurality of second lead segments on the board surface of the base substrate and the orthographic projections of the auxiliary electrodes on the board surface of the base substrate overlap with each other.
  • the plurality of data leads further includes a third lead segment, and the third lead segment is located in the peripheral area and located in the display area and the electrostatic discharge. Between circuits, one end of the plurality of third lead segments is electrically connected to the control end of the electrostatic discharge circuit, and the other ends of the plurality of third lead segments are respectively connected to the plurality of data lines correspondingly.
  • the third lead segment is located on the third conductive layer.
  • At least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element
  • the pixel driving circuit includes a semiconductor layer, a first display area metal layer, The second display area metal layer and the third display area metal layer
  • the light emitting element is located on the side of the pixel driving circuit away from the base substrate and is connected to the third display area metal layer of the pixel driving circuit
  • the first An insulating layer is located on the base substrate
  • the semiconductor layer is located on the side of the first display area metal layer close to the base substrate
  • the second display area metal layer is located in the first display area the side of the metal layer away from the base substrate
  • the third display area metal layer is located at the side of the second display area metal layer away from the base substrate
  • the first conductive layer and the first conductive layer A display area metal layer is arranged on the same layer
  • the third conductive layer is arranged on the same layer as the second display area metal layer
  • the second conductive layer is
  • the pixel driving circuit further includes a first transistor and a storage capacitor
  • the first transistor includes a gate electrode, a source electrode, a drain electrode and an active layer
  • the The storage capacitor includes a first electrode plate and a second electrode plate
  • the active layer is located in the semiconductor layer
  • the gate electrode and the first electrode plate are located in the metal layer of the first display area
  • the second electrode plate is located in the metal layer of the first display area.
  • the plate is located in the metal layer of the second display area
  • the source electrode and the drain electrode are located in the metal layer of the third display area.
  • the test circuit further includes at least one dummy test unit, and the at least one dummy test unit is located on a side of the test circuit away from the plurality of test units , the second conductive layer includes a plurality of first switching electrodes, each of the at least one virtual test unit includes a plurality of virtual control switches, and the first ends of the plurality of virtual control switches are connected with the plurality of data
  • the test lines are respectively connected correspondingly, the control ends of the plurality of virtual control switches are connected to the first control line, and the plurality of transfer electrodes are respectively connected to the first ends and the second ends of the plurality of virtual control switches.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of power lines, and the plurality of power lines are routed around at least one side of the display area, wherein the plurality of power lines include a first power line and a second power line configured to provide a first power signal, the second power line configured to provide a second power line, the first power line and at least a portion of the second power line Located on the second conductive layer, the first power line is routed on a side of the electrostatic discharge circuit away from the display area, and the second power line is located on the electrostatic discharge circuit close to the display area
  • the first power line and the second power line are respectively connected to the first end and the second end of the electrostatic discharge circuit
  • the electrostatic discharge circuit includes a plurality of first electrostatic discharge units, One ends of the plurality of second lead segments away from the test circuit are respectively connected to the control ends of the plurality of first electrostatic discharge units correspondingly.
  • the test circuit and the electrostatic discharge circuit are located on a first side of the display area, and the second side and the third side of the display area are disposed opposite to each other and Adjacent to the first side, the plurality of data test lines include a first data test line, a second data test line and a third data test line, the first data test line and the second data test line At least part of the line is routed around the second side and the first side of the display area, the second data test line is located on the side of the first data test line close to the display area, the third data test line and at least part of the control signal line is routed around the third side and the first side of the display area, the control signal line is located on the side of the third data test line close to the display area, On the side of the test circuit away from the display area, the second data test line is located between the first data test line and the third data test line, and the first data test line is located away from the test On one side of the circuit, the
  • the first data test line, the second data test line, the third data test line, the control signal line, and the first control line At least one of the wires is connected to the electrostatic discharge circuit.
  • the electrostatic discharge circuit further includes a second electrostatic discharge unit, and the second electrostatic discharge unit is located on at least one side of the plurality of first electrostatic discharge units, and is located on the side close to the third side of the display area
  • the first conductive layer includes a second connection line and a third connection line
  • the semiconductor layer includes a second resistor
  • the second connection line One end of the wire is connected to the control end of the second electrostatic discharge unit, the other end of the second connection wire is connected to the first end of the control signal wire, and the second resistor is connected to the second electrostatic discharge unit
  • the electrostatic discharge circuit further includes a third electrostatic discharge unit, and the third electrostatic discharge unit is located on the third side of the second electrostatic discharge unit close to the display area. On one side, one end of the third connection wire is connected to the third data test wire, and the other end of the third connection wire is connected to the control end of the third electrostatic discharge unit.
  • the first conductive layer further includes a fourth connection line, the fourth connection line extends along the second direction, and the semiconductor layer includes a fourth connection line.
  • the second conductive layer includes a second transfer electrode, the second transfer electrode extends along the first direction, and the first end of the fourth connection trace is connected to the first control wire.
  • One end close to the second side of the display area is connected, the second end of the fourth connection trace is connected with the first end of the second transfer electrode, and the first end of the third data test line is located at A side of the test circuit away from the display area and the third resistor are connected to the second end of the second transfer electrode and the first end of the third data test line.
  • the first conductive layer further includes a fifth connection trace
  • the electrostatic discharge circuit further includes a fourth electrostatic discharge unit
  • the fourth electrostatic discharge unit is located in the One side of the plurality of first electrostatic discharge units close to the second side of the display area, one end of the fifth connecting line is connected to the second end of the fourth connecting line, and the fifth connecting line is connected to the second end of the fourth connecting line.
  • the other end of the connecting wire is connected to the control end of the fourth electrostatic discharge unit.
  • the first conductive layer further includes a sixth connection line and a seventh connection line
  • the electrostatic discharge circuit further includes a fifth electrostatic discharge unit and a sixth connection line.
  • An electrostatic discharge unit, the sixth electrostatic discharge unit is located on a side of the fourth electrostatic discharge unit close to the second side of the display area
  • the fifth electrostatic discharge unit is located between the fourth electrostatic discharge unit and the second side of the display area.
  • one end of the sixth connection line is connected to the first data test line, and the other end of the sixth connection line is connected to the control end of the fifth electrostatic discharge unit , one end of the seventh connection line is connected to the second data test line, and the other end of the seventh connection line is connected to the control end of the sixth electrostatic discharge unit.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a bonding area and a signal access unit on a fourth side of the display area opposite to the first side, and the signal access unit is located on the Between the bonding area and the display area, the bonding area includes a plurality of contact pads arranged along the first direction, the plurality of contact pads including a first contact close to the second side of the display area pads and second contact pads, and third and fourth contact pads close to the third side of the display area, the second ends of the first data test lines extending to the fourth side of the display area and connected to the second contact pad, the second end of the second data test line extends to the fourth side of the display area and is connected to the first contact pad, the second end of the control signal line extends to the fourth side of the display area and connected to the third contact pad, and the second end of the third data test line extends to the fourth side of the display area and is connected to the fourth contact pad.
  • the bonding area includes a plurality of contact pads arranged along the first direction, the pluralit
  • parts of the first data test line, the second data test line, the third data test line, and the control signal line are located in the second conductive line Floor.
  • the plurality of power supply lines further include a third power supply line and a fourth power supply line
  • the third power supply line is configured to provide a third power supply line to the plurality of sub-pixels a power supply signal
  • the fourth power supply line is configured to provide a fourth power supply signal to the plurality of sub-pixels
  • the plurality of contact pads further include a fifth contact pad, a sixth contact pad, a seventh contact pad, and an eighth contact pad
  • the seventh contact pad is located on the side of the second contact pad close to the second side of the display area
  • the eighth contact pad is located on the third contact pad close to the display area
  • the fifth contact pad is located between the seventh contact pad and the second contact pad
  • the sixth contact pad is located between the fourth contact pad and the eighth contact pad
  • both ends of the third power line are respectively connected to the seventh contact pad and the eighth contact pad and route around the display area
  • the third power line is located between the first data test line and the On the side of the side of the
  • the first data test line includes a first portion connected to its first end, a second portion connected to its second end, and an eighth connection trace, the The first part and the second part of the first data test line are located in the second conductive layer, the eighth connection line is located in the first conductive layer, and the two ends of the eighth connection line are respectively connected with the first data line.
  • the first part and the second part of the test line are connected, and the second data test line includes a first part connected to its first end, a second part connected to its second end, and a ninth connection trace, the second data test line
  • the first part and the second part of the line are located in the second conductive layer
  • the ninth connection line is located in the first conductive layer
  • the two ends of the ninth connection line are respectively connected with the second data test line
  • the first part and the second part are connected, and the orthographic projection of the eighth connection line and the ninth connection line on the board surface of the base substrate is the same as that of the fourth power line on the base substrate.
  • the orthographic projections on the board overlap.
  • the third data test line includes a first portion connected to its first end, a second portion connected to its second end, and a tenth connection trace
  • the first part and the second part of the third data test line are located in the second conductive layer
  • the tenth connection trace is located in the first conductive layer
  • two ends of the tenth connection trace are respectively connected to the first conductive layer.
  • the first part and the second part of the three data test lines are connected.
  • the control signal line includes a first part connected to its first end, a second part connected to its second end, and an eleventh connection line.
  • the control signal line The first part and the second part are located in the second conductive layer, the eleventh connection line is located in the first conductive layer, and the two ends of the eleventh connection line are respectively connected with the first part and the first part of the control signal line.
  • the two parts are connected, and the orthographic projection of the tenth connection trace and the eleventh connection trace on the board surface of the base substrate is the orthographic projection of the fourth power supply line on the board surface of the base substrate. Projection overlap.
  • the signal access unit includes a plurality of signal access pads
  • the first conductive layer further includes a twelfth connection trace, and the twelfth connection One end of the wire is connected to at least one of the plurality of signal access pads, and the other end of the twelfth connection wire is connected to the control signal wire.
  • At least one embodiment of the present disclosure provides a display device including the display substrate described in any one of the above.
  • 1A is a schematic structural diagram of a test circuit unit of a display substrate
  • 1B is a schematic diagram of the working principle of a test circuit of a display substrate
  • FIG. 2 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 3 is a partial structural schematic diagram of a peripheral area of a display substrate on a first side of the display area according to at least one embodiment of the present disclosure
  • Fig. 4 is a sectional view along line A-B in Fig. 3;
  • FIG. 5 is a schematic cross-sectional view of a display area of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of another part of the peripheral area of a display substrate on a first side of the display area according to at least one embodiment of the present disclosure
  • FIG. 7A is a schematic structural diagram of another part of the peripheral area of a display substrate on a first side of the display area according to at least another embodiment of the present disclosure
  • FIG. 7B is an enlarged schematic view of the virtual test unit in FIG. 7A;
  • FIG. 8 is a schematic structural diagram of another part of the peripheral area of a display substrate on a first side of the display area according to at least one embodiment of the present disclosure
  • FIG. 9 is a partial structural schematic diagram of a peripheral area of a display substrate on a fourth side of the display area according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 1A is a schematic structural diagram of a test circuit unit of a display substrate
  • FIG. 1B is a schematic diagram of a working principle of a test circuit of a display substrate.
  • test unit CT0 includes a plurality of test switches CT01.
  • the plurality of test switches CT01 includes three, which are respectively electrically connected to different data test signal lines.
  • the first electrode (eg, one of the source electrode or the drain electrode) of the test cell CT0 receives the DR0 data signal, the DG0 data signal, and the DB0 data signal.
  • the DR0 signal, the DG0 signal, and the DB0 signal are respectively data signals and are provided by different data test signal lines.
  • the gate of test cell CT0 eg, test switch CT01 ) receives the CTSW0 switching signal.
  • the working principle of the above test circuit is shown in Figure 1B.
  • the working principle of the test circuit shown in FIG. 1A is: the test unit CT01 opens the switch of the test switch CT01 in response to the received switch signal, that is, the switch signal received through the control signal line CTSW0 connected to the gate of the test switch CT01; A data signal (eg, a DR0 data signal, a DG0 data signal, or a DB0 data signal) transmitted by the data test signal line CT_D is provided to the Data_R data line, the Data_G data line, or the Data_B data line.
  • the Data_R data line, the Data_G data line, and the Data_B data line are respectively connected to the sub-pixels P10 in different columns. At this time, the voltages of the data signals of all sub-pixels are the same, and only a pure color picture can be displayed. If there are colored points, such as black points, during detection, it means that there are abnormal points in the display panel.
  • the impedance of the signal line plays an important role in the transmission efficiency of the signal and the display effect.
  • the gate of the test switch CT01 is a single-layer trace (for example, located in the first gate electrode layer), and is connected to the control signal line CTSW0 respectively.
  • Such a design usually follows the signal line.
  • the trace distance increases, its impedance also increases.
  • the distances between the gates of the three test switches CT01 shown in FIG. 1A and the control signal line in the longitudinal direction of the figure are different, and the impedance of the signal received by the test switch CT01 that is farther away from the control signal line is greater.
  • the increase of the impedance of the signal will also cause uneven strength of the gate signal of each test switch CT01, thereby affecting the test result.
  • At least one embodiment of the present disclosure provides a display substrate including: a base substrate, a plurality of sub-pixels, a plurality of data lines, a control signal line, a data test line, a test circuit, and an auxiliary electrode line.
  • the base substrate includes a display area and a peripheral area at least on one side of the display area; a plurality of sub-pixels are located in the display area and are arranged in an array; a plurality of data lines are located in the display area and are configured to provide data signals to the plurality of sub-pixels;
  • the peripheral area is located on at least one side of the display area; a plurality of data test lines are located in the peripheral area and are located on at least one side of the display area;
  • the test circuit is located in the peripheral area and is electrically connected to a plurality of data lines, control signal lines and a plurality of data test lines connected and configured to transmit a test signal to a plurality of data lines through a plurality of data test lines under the control of the control signal
  • At least one embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • the display substrate can reduce the impedance of the first control line, improve the transmission efficiency of the first control line, prevent signal distortion, and provide a more stable control signal for the test circuit.
  • FIG. 2 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 3 is a partial structural schematic diagram of a peripheral area of a display substrate on a first side of the display area according to at least one embodiment of the present disclosure.
  • the display substrate 1 includes a base substrate 100 .
  • the base substrate 100 includes a display area 10 and a peripheral area 20 .
  • the peripheral area 20 surrounds the display area 10 .
  • the display substrate 1 includes a plurality of sub-pixels P10.
  • the plurality of sub-pixels P10 are located in the display area 10 and are arranged in an array, for example, arranged in rows and columns along the first direction X and the second direction Y.
  • the display substrate 1 further includes a plurality of data lines D10 and control signal lines CW.
  • the plurality of data lines D10 are located in the display area 10, for example, pass through the display area 10 along the second direction Y (longitudinal direction).
  • the plurality of data lines D10 are configured to respectively provide data signals to the sub-pixels P10 corresponding to each column.
  • the control signal line CW is located in the peripheral area 20 and is routed around at least one side of the display area 10 , eg, routed around the third side 13 of the display area 10 (eg, the right side of the display area 10 in FIG. 2 ).
  • the included angle between the first direction X and the second direction Y involved in the present disclosure is between 70° and 90°, inclusive.
  • the included angle between the first direction X and the second direction Y is 70°, 90°, or 80°, etc., which can be set according to actual conditions, which is not limited in the embodiments of the present disclosure.
  • the included angle between the first direction X and the second direction Y may also be 75°, 85°, or the like.
  • the base substrate 100 may be a glass plate, a quartz plate, a metal plate, a resin-based plate, or the like.
  • the material of the base substrate may include an organic material, for example, the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate and other resin materials; for example, the base substrate 100 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.
  • the display substrate 1 further includes a test circuit CT.
  • the test circuit CT is located in the peripheral area 20 , eg, on the first side 11 of the display area 10 (eg, the upper side of the display area 10 in FIG. 2 ).
  • the test circuit CT is electrically connected to the data lines D10 respectively corresponding to the plurality of sub-pixels P10 to transmit test signals (eg, data signals).
  • the test circuit CT includes a plurality of test cells CT1 (as shown in FIG. 3 ).
  • the at least one test unit CT1 each includes a first control line CT11 and a plurality of control switches CT12.
  • Each of the plurality of control switches CT12 includes a control terminal CT121 (eg gate), the first control line CT11 and the control signal line CW and the control terminal CT121 of the plurality of control switches CT12 in the test unit CT1 are connected to the plurality of control switches CT12 provides control signals.
  • the test circuit CT transmits the test signal to the plurality of data lines D10 under the control of the control signal line CW (e.g., through the plurality of data test lines DR/DG/DB).
  • the first control line CT11 and the control terminal CT121 of the control switch CT12 are disposed at the same layer and formed integrally.
  • the display substrate 1 further includes auxiliary electrode lines SW.
  • the auxiliary electrode lines SW are located in the peripheral area 20 , eg, the first side 11 of the display area 10 .
  • the wiring directions of the auxiliary electrode line SW and the first control line CT11 are basically the same, for example, both extend along the first direction X.
  • the auxiliary electrode line SW and the first control line CT11 are connected in parallel with each other, and at least a part of the control switch CT12 of at least one of the plurality of control switches CT12 is on the positive side of the board surface S (shown in FIG. 4 ) of the base substrate 100 .
  • each of the plurality of control switches CT12 further includes a first end CT122 (eg, a first end away from the auxiliary electrode line SW) and a second end CT123 (eg, a first end close to the auxiliary electrode line SW) , the second terminals CT123 of a plurality of control switches CT12 are spaced between the first control line CT11 and the auxiliary electrode line SW.
  • the orthographic projection of the second terminal CT123 of the control switch CT12 on the board surface S of the base substrate 100 is located in the orthographic projection of the first control line CT11 and the auxiliary electrode line SW on the board surface S of the base substrate 100 between.
  • the auxiliary electrode line SW and the first control line CT11 may not be parallel to the first direction X, for example, intersect the first direction X at a certain angle.
  • the intersection angle is 20° or less.
  • the control terminal CT121 of each of the plurality of control switches CT12 is connected to the first control line CT11
  • the control terminals CT121 of the plurality of control switches CT12 are connected in series, so as to be connected with the control terminal CT121 of each control switch CT12
  • the connected first control line CT11 and the auxiliary electrode line SW form a parallel structure.
  • R (R CT11 +R SW )/(R CT11 *R SW )
  • R CT11 represents the resistance of the first control line CT11
  • R SW represents the resistance of the auxiliary electrode line SW
  • the auxiliary electrode line SW The impedance of the first control line CT11 decreases after being connected in parallel with the first control line CT11.
  • the display substrate 1 can reduce the impedance of the first control line CT11, improve the transmission efficiency of the first control line CT11, and prevent signal distortion without changing the structure or working performance of the control switch CT12. , to provide a more stable control signal for the test circuit.
  • control switch CT12 is taken as an example of a P-type transistor.
  • the control switch CT12 may also select an N-type transistor, which is not limited to this embodiment of the present disclosure.
  • control terminal CT121 of the control switch CT12 is, for example, the gate of the transistor, and the first terminal CT122 and the second terminal CT123 of the control switch CT12 are the source and drain of the transistor, respectively.
  • FIG. 4 is a cross-sectional view taken along line A-B in FIG. 3 .
  • the first control line CT11 and the auxiliary electrode line SW are located in different layers with respect to the base substrate 100 , that is, disposed in different layers.
  • the first control line CT11 and the auxiliary electrode line SW are respectively located in the first conductive layer 201 and the second conductive layer 203 which are spaced apart and insulated from each other.
  • a second peripheral insulating layer 2243 and a peripheral interlayer insulating layer 2244 are spaced between the first conductive layer 201 and the second conductive layer 203 .
  • the peripheral interlayer insulating layer 2244 is located on the side of the first conductive layer 201 away from the base substrate 100, the peripheral interlayer insulating layer 2244 is located on the side of the second peripheral insulating layer 2243 away from the base substrate 100, and the second conductive layer 203 is located on the side of the peripheral interlayer insulating layer 2244 away from the base substrate 100 . Therefore, compared to the fact that the auxiliary electrode line SW is located in the first conductive layer 201 (for example, provided in the same layer as the first control line CT11 ), the resistance value of the auxiliary electrode line SW can be increased, thereby further reducing the impedance of the first control line CT11 .
  • the auxiliary electrode line SW is located on a side of the test circuit CT away from the display area 10 (eg, the upper side of the test circuit CT in FIG. 3 ) or on a side close to the display area 10 (eg, FIG. 3 ) the underside of the test circuit CT in the middle).
  • the display substrate 1 further includes an electrostatic discharge circuit ESD disposed between the test circuit CT and the display area 10 .
  • the electrostatic discharge circuit ESD is electrically connected to the plurality of data lines D10 to remove the electrostatic interference generated during the transmission of the test signal of the test circuit CT.
  • the auxiliary electrode line SW is located between the test circuit CT and the electrostatic discharge circuit ESD, and is further connected in parallel with the first control line CT11.
  • the display substrate 1 further includes a plurality of connecting lines 101 .
  • the plurality of connection lines 101 are respectively disposed between the plurality of control switches CT12, that is, arranged in the gaps of the plurality of control switches CT12.
  • the first control line CT11 overlaps with the active layers CT124 of the plurality of control switches CT12, and the overlapping portion of the first control line CT11 and the active layer CT124 forms the control terminals CT121 of the plurality of control switches CT12.
  • the first control line is integrally formed with the control terminal CT121 of the control switch CT12.
  • first ends 1011 of the plurality of connection lines 101 are connected to the first control line CT11, and the second ends 1012 of the plurality of connection lines 101 are connected to the auxiliary electrode line SW, so that the first control line CT11 and the auxiliary electrode line SW form a parallel connection connection structure.
  • connection lines 101 and the first control line CT11 are disposed in the same layer and are all located in the first conductive layer 201 .
  • the plurality of connection lines 101 are integrally formed with the first control line CT11.
  • “same layer arrangement” includes that two functional layers or structural layers are formed in the same layer and with the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers are formed on the same layer and with the same material.
  • the layers or structural layers can be formed from the same material layer, and the desired patterns and structures can be formed by the same patterning process.
  • a patterning process includes, for example, steps such as photoresist formation, exposure, development, and etching.
  • the display substrate 1 further includes a plurality of data test lines (eg, a first data test line DR, a second data test line DG, and a third data test line DB ).
  • a plurality of data test lines are located in the peripheral area 20 and route around at least one side (eg, the first side 11 , the second side 12 and the third side 13 ) of the display area 10 .
  • a plurality of data test lines extend along the first direction X and are arranged at intervals on a side of the test circuit CT away from the display area 10 (above the test circuit CT in the figure).
  • each of the plurality of control switches CT12 is based on a control signal received on the control terminal CT121.
  • the control terminal CT121 of the control switch CT12 is turned on, so that the first terminal CT122 and the second terminal CT123 can transmit test signals.
  • the first ends CT122 of the plurality of control switches CT12 are respectively connected to the plurality of data test lines correspondingly, and are configured to receive test signals provided by the plurality of data test lines.
  • the second terminals CT123 of the plurality of control switches CT12 are respectively electrically connected to the plurality of data lines D10 to provide the test signal to the sub-pixels P10 of the display area 10 .
  • the display substrate 1 further includes a plurality of first lead segments 102 and a plurality of data leads 103 .
  • the plurality of first lead segments 102 and the plurality of data leads 103 extend along the second direction Y.
  • the plurality of first lead segments 102 are respectively connected to the plurality of data test lines (eg, the first data test line DR, the second data test line DG, and the third data test line DB) and the first of the plurality of control switches CT12. terminal CT122.
  • the plurality of data leads 103 are respectively connected to the second terminals CT123 of the plurality of control switches CT12 and the plurality of data lines D10, so as to provide test signals to the sub-pixels P10 of the display area 10 when the control switches CT12 are turned on.
  • the plurality of first lead segments 102 and the plurality of data leads 103 may not be parallel to the second direction Y, for example, intersect the second direction Y at a certain angle.
  • the intersection angle is 20° or less.
  • each of the plurality of data leads 103 includes a second lead segment 1031, respectively.
  • the plurality of second lead segments 1031 are respectively connected to the second terminals CT123 of the plurality of control switches CT12 and the electrostatic discharge circuit ESD.
  • a plurality of first lead segments 102 and a plurality of second lead segments 1031 are located on the third conductive layer 202 .
  • the third conductive layer 202 is located between the first conductive layer 201 and the second conductive layer 203 and is insulated from each other.
  • the third conductive layer 202 is located between the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 .
  • a peripheral interlayer insulating layer 2244 is spaced between the third conductive layer 202 and the second conductive layer 203 .
  • a second peripheral insulating layer 2243 is spaced between the third conductive layer 202 and the first conductive layer 201 .
  • the first lead segment 102 is connected to the first terminal CT122 of the control switch CT12 through a via hole passing through the interlayer insulating layer 2244 .
  • the second lead segment 1031 is connected to the second terminal CT123 of the control switch CT12 through a via hole passing through the interlayer insulating layer 2244 .
  • the orthographic projections of the plurality of second lead segments 1031 on the board surface S of the base substrate 100 and the orthographic projections of the auxiliary electrodes SW on the board surface S of the base substrate 100 overlap with each other.
  • the plurality of second lead segments 1031 and the auxiliary electrodes SW are located on different layers to save wiring space.
  • the plurality of first lead segments 102 do not overlap with the first control line CT11 , which can avoid the generation of parasitic capacitance between the first lead segments 102 and the first control line CT11 .
  • FIG. 6 is a schematic diagram of another part of the structure of a peripheral area of a display substrate on a first side of the display area according to at least one embodiment of the present disclosure.
  • each of the plurality of data leads 103 further includes a third lead segment 1032 .
  • the third lead segment 1032 is located in the peripheral area 20 and between the display area 10 and the electrostatic discharge circuit ESD.
  • one end of the plurality of third lead segments 1032 (one end close to the electrostatic discharge circuit ESD) is electrically connected to the control end of the electrostatic discharge circuit ESD.
  • the other ends of the plurality of third lead segments 1032 are respectively connected to the plurality of data lines D10 correspondingly, so as to provide test signals to the sub-pixels P10 of the display area 10 .
  • the third lead segment 1032 is located on the third conductive layer 202 .
  • FIG. 5 is a schematic cross-sectional view of a display area of a display substrate according to at least one embodiment of the present disclosure.
  • each of the plurality of sub-pixels P10 includes a pixel structure.
  • the pixel structure includes a pixel driving circuit 104 and a light-emitting element 11 .
  • the pixel driving circuit 104 includes a semiconductor layer 304, a first display area metal layer 301, a second display area metal layer 302, a third display area metal layer 303, a first insulating layer 1242 (ie, a first gate insulating layer), a second insulating layer layer 1243 (ie, the second gate insulating layer) and the interlayer insulating layer 1244 .
  • the light emitting element 11 is located on the side of the pixel driving circuit 104 away from the base substrate 100 and is connected to the third display region metal layer 303 of the pixel driving circuit 104 .
  • the first insulating layer 1242 is located on the base substrate 100 .
  • the semiconductor layer 304 is located on the side of the first insulating layer 1242 close to the base substrate 100 .
  • the first display area metal layer 301 is located on the side of the first insulating layer 1242 away from the base substrate 100.
  • the second insulating layer 1243 is located on the side of the first display region metal layer 301 away from the base substrate 100 .
  • the second display region metal layer 302 is located on the side of the second insulating layer 1243 away from the base substrate 100 .
  • the interlayer insulating layer 1244 is located on the side of the second display region metal layer 302 away from the base substrate.
  • the third display region metal layer 303 is located on the side of the interlayer insulating layer 1244 away from the base substrate 100 .
  • the display substrate 1 may further include a buffer layer 1241 and a barrier layer 1240 .
  • the buffer layer 1241 is located on the side of the semiconductor layer 304 close to the base substrate 100
  • the barrier layer 1240 is located on the side of the buffer layer 1241 close to the base substrate 100 .
  • the buffer layer 1241 serves as a transition layer, which can not only prevent harmful substances in the base substrate from intruding into the interior of the display substrate, but also increase the adhesion of the films in the display substrate on the base substrate 100 .
  • the barrier layer 1240 can provide a flat surface for forming the pixel driver circuit 104 and can prevent impurities that may exist in the base substrate 100 from diffusing into the sub-pixel driver circuit or the pixel driver circuit 104 and adversely affect the performance of the display substrate.
  • materials of one or more of the first insulating layer 1242, the second insulating layer 1243, and the interlayer insulating layer 1244 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the first insulating layer 1242 , the second insulating layer 1243 and the interlayer insulating layer 1244 may be the same or different.
  • the material of the buffer layer 1241 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the barrier layer 1240 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.
  • the material of the semiconductor layer 304 may include polysilicon or an oxide semiconductor (eg, indium gallium zinc oxide (IGZO)).
  • oxide semiconductor eg, indium gallium zinc oxide (IGZO)
  • the materials of the first display area metal layer 301, the second display area metal layer 302, and the third display area metal layer 303 may include metal materials or alloy materials, such as single or multiple metal layers formed by molybdenum, aluminum, and titanium.
  • the structure, for example, the multi-layer structure is a multi-metal stack (eg, titanium, aluminum, and titanium tri-metal stack (Ti/Al/Ti)).
  • the materials of the first display area metal layer 301 , the second display area metal layer 302 , and the third display area metal layer 303 may be the same or different, and the embodiments of the present disclosure are not limited thereto.
  • the first conductive layer 201 and the first display area metal layer 301 are disposed in the same layer.
  • the third conductive layer 202 and the second display region metal layer 302 are disposed in the same layer.
  • the second conductive layer 203 and the third display region metal layer 303 are disposed in the same layer.
  • the active layers CT124 of the plurality of control switches CT12 are provided in the same layer as the semiconductor layer 304 .
  • the second peripheral insulating layer 2243 and the second insulating layer 1243 are provided in the same layer, and the peripheral interlayer insulating layer 2244 and the interlayer insulating layer 1244 are provided in the same layer.
  • the preparation process is simplified.
  • the plurality of connection lines 101 are located on the first conductive layer 201, and the second ends 1012 of the plurality of connection lines 101 pass through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 (for example, the first The via hole GK1 of the two insulating layers 1243 and the interlayer insulating layer 1244) is connected to the auxiliary electrode line SW.
  • the display substrate 1 further includes a first peripheral insulating layer 2242 , a peripheral buffer layer 2241 and a peripheral barrier layer 2240 .
  • the first peripheral insulating layer 2242 is located on the side of the first conductive layer 201 close to the base substrate 100
  • the peripheral buffer layer 2241 is located on the side of the first peripheral insulating layer 2242 close to the base substrate 100
  • the peripheral barrier layer 2240 is located on the peripheral buffer layer 2241 Close to the side of the base substrate 100 .
  • the first peripheral insulating layer 2242 and the first insulating layer 1242 are arranged in the same layer
  • the peripheral buffer layer 2241 and the buffer layer 1241 are arranged in the same layer
  • the peripheral barrier layer 2240 and the barrier layer 1240 are arranged in the same layer.
  • the pixel driving circuit 104 further includes a first transistor 12 and a storage capacitor 13 .
  • the first transistor 13 includes a transistor that is directly electrically connected to the light-emitting element 11 , and the transistor is, for example, a switching transistor (eg, a light-emitting control transistor) or a driving transistor.
  • the first transistor 12 includes a gate electrode 122 , two source-drain electrodes (a source electrode 123 and a drain electrode 124 ), and an active layer 121 .
  • the gate 122 is located in the first display area metal layer 301 , the two source and drain electrodes (source 123 and drain 124 ) are located in the third display area metal layer 303 , and the active layer 121 is located in the semiconductor layer 304 .
  • the storage capacitor 13 includes a first electrode plate 131 and a second electrode plate 132 .
  • the first electrode plate 131 is located on the metal layer 301 in the first display area
  • the second electrode plate 132 is located on the metal layer 302 in the second display area.
  • the gate electrode 122 and the first electrode plate 131 are disposed in the same layer.
  • a second insulating layer 1243 is spaced between the first electrode plate 131 and the second electrode plate 132 to form a capacitance function.
  • the first electrode plate 131 may be located at the metal layer 302 in the second display area, and the second electrode plate 132 may be located at the metal layer 303 in the third display area. At this time, the first electrode plate 131 and A side key insulating layer 1244 is spaced between the second electrode plates 132 .
  • the embodiment of the present disclosure is not limited to the specific arrangement of the storage capacitor 13 .
  • the display substrate 1 further includes a first planarization layer 1245 .
  • the first planarization layer 1245 is located on the side of the source electrode 123 and the drain electrode 124 (ie, the pixel driving circuit 104 ) away from the base substrate 100 to provide a first planarization surface to planarize the pixel driving circuit 104 away from the base substrate 100 surface on one side.
  • the first planarization layer 1245 includes a first via hole 252 , and the pixel driving circuit 104 (eg, the metal layer 303 in the third display area) is electrically connected to the light emitting element through the first via hole 252 .
  • the material of the first planarization layer 1245 includes inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include polyimide, polyphthalimide, polyphthalamide, acrylic resin, and benzoic ring.
  • Organic insulating materials such as butene or phenolic resin, which are not limited in the embodiments of the present disclosure.
  • the display substrate 1 further includes a pixel defining layer 146 .
  • the light emitting element 11 is disposed on the side of the second planarization layer 1245 away from the base substrate 100 .
  • the light-emitting element 11 includes a first electrode 113 (eg, an anode), a light-emitting layer 112 and a second electrode 111 (eg, a cathode).
  • the first electrode 113 is located on a side of the first planarization layer 1245 away from the base substrate 100 , and is electrically connected to the pixel driving circuit 104 (eg, the drain 124 of the first transistor 12 ) through the via hole 252 .
  • the second electrode 111 is located on the side of the pixel defining layer 146 away from the base substrate 100 .
  • the pixel defining layer 146 is located on a side of the first electrode 113 away from the base substrate 100 and includes a first pixel opening 1461 .
  • the first pixel opening 1461 is disposed corresponding to the light emitting element 11 .
  • the light emitting layer 112 is located in the first pixel opening 1461 and between the first electrode 113 and the second electrode 111 .
  • the portion of the light-emitting layer 112 directly sandwiched between the first electrode 113 and the second electrode 111 will emit light after being electrified, and thus the area occupied by this portion corresponds to the light-emitting region of the light-emitting element 11 .
  • the pixel driving circuit 104 generates a light-emitting driving current under the control of a data signal (such as a test signal) provided by the data line D10, a gate scanning signal and a light-emitting control signal provided by a shift register, etc., and the light-emitting driving current makes the light-emitting element 11 may emit red light, green light, blue light, or may emit white light, and the like.
  • a data signal such as a test signal
  • a gate scanning signal and a light-emitting control signal provided by a shift register, etc.
  • the pixel driving circuit 104 includes conventional 2T1C (ie, two transistors and one capacitor) pixel circuits, 7T1C (ie, seven transistors and one capacitor) pixel circuits, and the like.
  • the pixel driving circuit 104 includes at least one switching transistor and one driving transistor (the first transistor 12 shown in FIG. 5 ).
  • the gate of the switching transistor receives the gate scanning signal, and the source or drain of the switching transistor is connected to the data line. D10 is connected to receive data signals.
  • the pixel driving circuit 104 may further include a compensation circuit, the compensation circuit includes an internal compensation circuit or an external compensation circuit, and the compensation circuit may include a transistor, a capacitor, and the like.
  • the pixel circuit may further include a reset circuit, a light emission control circuit, a detection circuit, and the like, as required.
  • the embodiments of the present disclosure do not limit the type of the first light emitting device and the specific structure of the pixel circuit.
  • the material of the pixel defining layer 146 may include organic insulating materials such as polyimide, polyimide, polyamine, acrylic resin, benzocyclobutene, or phenolic resin, or include inorganic materials such as silicon oxide and silicon nitride. Insulation material, which is not limited in the embodiments of the present disclosure.
  • the material of the first electrode 113 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 113 may include a metal having high reflectivity, such as silver (Ag), as a reflective layer.
  • the light-emitting layer 112 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, may emit red light, green light, blue light, or may emit white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light emitting layer 112 may include quantum dot materials, eg, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20 nm.
  • the second electrode 111 may include various conductive materials.
  • the second electrode 111 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the display substrate 1 further includes an encapsulation layer 147 .
  • the encapsulation layer 147 is located on the side of the second electrode 111 away from the base substrate 100 .
  • the encapsulation layer 147 seals the light emitting element 11 (light emitting element 11 ), so that deterioration of the light emitting element 11 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 147 may be a single-layer structure or a composite-layer structure, and the composite-layer structure includes a structure in which an inorganic layer and an organic layer are stacked.
  • the encapsulation layer 147 includes at least one encapsulation sublayer.
  • the encapsulation layer 147 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence.
  • the material of the encapsulation layer 147 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high compactness and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc. , such as polymer resin, etc.
  • the display substrate to planarize the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccants to absorb the water intruding inside, substances such as oxygen.
  • water-absorbing materials such as desiccants to absorb the water intruding inside, substances such as oxygen.
  • FIG. 7A is a schematic structural diagram of another part of the peripheral area of a display substrate on the first side of the display area according to at least another embodiment of the present disclosure
  • FIG. 7B is an enlarged schematic diagram of the virtual test unit in FIG. 7A .
  • the test circuit CT further includes at least one dummy test cell DCT1 located on a side of the test circuit CT away from the plurality of test cells CT1.
  • the number of the at least one dummy test unit DCT1 is at least two, and is disposed on both sides of the test circuit CT away from the plurality of test units CT1.
  • the second conductive layer 203 includes a plurality of first transfer electrodes ZL1.
  • each of the at least one dummy test unit DCT1 includes a plurality of dummy control switches DCT11.
  • the first terminals DCT13 of the plurality of virtual control switches DCT11 are respectively connected to a plurality of data test lines (eg, the first data test line DR, the second data test line DG, and the third data test line DB).
  • the control terminals DCT12 of the plurality of virtual control switches DCT11 are connected to the first control line CT11.
  • the plurality of switching electrodes ZL1 are provided in the plurality of virtual control switches DCT11 in a one-to-one correspondence.
  • the switching electrode ZL1 is connected to the first terminal DCT13 and the second terminal DCT14 of the virtual control switch DCT11. That is, the dummy control switch DCT11 is provided with more switching electrodes ZL1 than the structure of the control switch CT12.
  • the setting of the dummy test unit DCT1 can increase the uniformity of the wiring of the peripheral area 20 on the first side 11 of the display area 10 .
  • the display substrate 1 further includes a plurality of power lines (eg, including a first power line VGH and a second power line VGL).
  • a plurality of power lines are routed around at least one side (eg, the first side 11 , the second side 12 and the third side 13 ) of the display area 10 .
  • the plurality of power supply lines include a first power supply line VGH and a second power supply line VGL, the first power supply line VGH is configured to provide a first power supply signal (eg, a high-level voltage signal), and the second power supply line VGL is configured to provide a second power supply line Power signal (eg low level voltage signal).
  • At least parts of the first power line VGH and the second power line VGL are located in the second conductive layer 203 .
  • the portion where the first power supply line VGH and the second power supply line VGL and other wirings (eg, the fourth power supply line VDD in FIG. 2 ) overlap the wirings is located in the first conductive layer 201 .
  • the first power line VGH is routed on the side of the electrostatic discharge circuit ESD away from the display area 10
  • the second power line VGL is routed on a side of the electrostatic discharge circuit ESD close to the display area 10 side routing.
  • the first power supply line VGH and the second power supply line VGL are respectively connected to the first end ESD1 and the second end ESD2 of the electrostatic discharge circuit ESD.
  • the electrostatic discharge circuit ESD includes a plurality of first electrostatic discharge units ESD10.
  • one ends of the plurality of second lead segments 1031 away from the test circuit CT are respectively connected to the control ends ESD11 of the plurality of first electrostatic discharge units ESD10, respectively.
  • the first electrostatic discharge unit ESD10 is implemented as a plurality of transistors connected in series.
  • One of the source and drain electrodes (eg, the first terminal ESD1 and the second terminal ESD2 ) of each transistor is short-circuited with the control terminal (eg, the control terminal ESD11 ) to form a diode structure to have unidirectional conduction characteristics.
  • the control terminal eg, the control terminal ESD11
  • the first electrostatic discharge unit ESD10 is configured to derive, the test signals provided by the data test signal lines (eg, the first data test line DR, the second data test line DG, and the third data test line DB) are directed to the data lines Static electricity on the D10 transmission path.
  • the data test signal lines eg, the first data test line DR, the second data test line DG, and the third data test line DB
  • the test circuit CT and the electrostatic discharge circuit ESD are located on the first side of the display area 10 .
  • the second side 12 and the third side 13 of the display area 10 are arranged opposite to and adjacent to the first side 11
  • the fourth side 14 of the display area 10 is arranged opposite to the first side 11 .
  • the plurality of data test lines include a first data test line DR, a second data test line DG, and a third data test line DB.
  • the first data test line DR and the second data test line DG are (eg at least partially) routed around the second side 12 and the first side 11 of the display area 10, and the second data test line DG is located close to the first data test line DR.
  • the third data test line DB and the control signal line CW are (eg at least partially) routed around the third side 13 and the first side 11 of the display area 10 , and the control signal line CW is located on the third data test line DB close to the display area 10 . side.
  • the second data test line DG is located between the first data test line DR and the third data test line DB, and the first data test line DR is located away from the test circuit CT. side.
  • the first data test line DR, the second data test line DG, and the third data test line DB are arranged in parallel in the second direction Y at intervals.
  • the first conductive layer 201 includes a first connection line LL1 , and the first connection line LL1 extends along the second direction Y.
  • the semiconductor layer 304 includes a plurality of first resistors R1.
  • the first end CW1 of the control signal line CW is located at the first side 11 of the display area 10 and close to the test circuit CT.
  • One end of the first connection line LL1 is connected to the first end CW1 of the control signal line CW (for example, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ), and the other end of the first connection line LL1 is connected.
  • One end is connected to one end of the first control line CT11 close to the third side 13 of the display area 10 .
  • the first control line CT11 and the first connection wiring LL1 are disposed in the same layer and formed integrally, so as to simplify the manufacturing process.
  • the first end DR1 of the first data test line DR and the first end DG1 of the second data test line DG are located on the side of the test circuit CT away from the display area 10 , that is, on the side close to the third side 13 of the display area 10 .
  • one of the plurality of first resistors R1 (eg, at least one of the first resistors) is connected (eg, by passing through the first peripheral insulating layer 2242 , the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ) Via) the first end DR1 of the first data test line DR and the control signal line CW, and the other of the plurality of first resistors R1 (for example, at least the other of the first resistors) is connected to the second data test line DG and the second data test line DG.
  • One end DG1 and control signal line CW The first resistor R1 can prevent the first end DR1 of the first data test line DR and the first end DG1 of the second data test line DG from generating static electricity.
  • the first connection line LL1 may not be parallel to the second direction Y, for example, intersect the second direction Y at a certain angle.
  • the intersection angle is 20° or less.
  • FIG. 8 is a schematic structural diagram of another part of the peripheral area of a display substrate on a first side of the display area according to at least one embodiment of the present disclosure.
  • the first data test line DR, the second data test line DG, the third data test line DB, the control signal line CW, and the first control line CT11 At least one of them is connected to the electrostatic discharge circuit ESD.
  • the first data test line DR, the second data test line DG, the third data test line DB, the control signal line CW, and the first control line CT11 are respectively electrically connected to different electrostatic discharge units in the electrostatic discharge circuit ESD to remove Static electricity generated during the signal transmission process of the first data test line DR, the second data test line DG, the third data test line DB, the control signal line CW and the first control line CT11.
  • the electrostatic discharge circuit ESD further includes a second electrostatic discharge unit ESD20.
  • the second electrostatic discharge unit ESD20 is located on one side of the plurality of first electrostatic discharge units ESD10 close to the third side 13 of the display area 10 (eg, on the right side of the plurality of first electrostatic discharge units ESD10).
  • the first conductive layer 201 includes a second connection line LL2, and the semiconductor layer 304 includes a second resistor R2.
  • the second connection line LL2 overlaps with the first power line VGH.
  • the second connection wire LL2 is approximately an "L"-shaped wire.
  • connection line LL2 is connected to the control end ESD21 of the second electrostatic discharge unit ESD20 (for example, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ), and the second connection line LL2 The other end is connected to the first end CW1 of the control signal line CW to remove static electricity generated by the first end CW1 of the control signal line CW.
  • the second resistor R2 is located on a side of the second electrostatic discharge unit ESD20 away from the first electrostatic discharge unit ESD10.
  • the second resistor R2 connects (eg, via vias penetrating the first peripheral insulating layer 2242 , the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ) the control terminal ESD21 of the second electrostatic discharge unit ESD20 and the first power supply line VGH , so as to prevent the control terminal ESD21 of the second electrostatic discharge unit ESD20 from generating static electricity.
  • the first conductive layer 201 further includes a third connection line LL3 .
  • the third connection line LL3 overlaps with the first power line VGH and the control signal line CW, and the third connection line LL3 is bent.
  • the electrostatic discharge circuit ESD further includes a third electrostatic discharge unit ESD30.
  • the third electrostatic discharge unit ESD30 is located on a side of the second electrostatic discharge unit ESD20 close to the third side 13 of the display area 10 (eg, the right side in the figure).
  • one end of the third connection line LL3 is connected to the third data test line DB (eg, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ), and the other end of the third connection line LL3 It is connected to the control terminal ESD31 of the third electrostatic discharge unit ESD30 (eg, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ) to remove static electricity from the third data test line DB.
  • the first conductive layer 201 further includes a fourth connection line LL4 .
  • the fourth connection line LL4 extends along the second direction Y.
  • the fourth connection line LL4 and the first connection line LL1 are symmetrically arranged to increase the uniformity of the lines.
  • the first end LL41 of the fourth connection line LL4 is connected to an end of the first control line CT11 close to the second side 12 of the display area 10 .
  • the fourth connection line LL4 and the first control line CT11 are disposed in the same layer and formed integrally, so as to simplify the manufacturing process.
  • the semiconductor layer 304 includes a third resistor R3.
  • the second conductive layer 203 includes a second transfer electrode ZL2, and the second transfer electrode ZL2 extends along the first direction X.
  • the second end LL42 of the fourth connection line LL4 is connected to the first end ZL21 of the second transfer electrode ZL2 (eg, connected by a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ).
  • the first end DB1 of the third data test line DB is located on the side of the test circuit CT away from the display area 10 .
  • the third data test line DB extends in a direction close to the second side 12 on the first side 11 of the display area 10 .
  • the third resistor R3 connects (eg, via vias penetrating the first peripheral insulating layer 2242, the second peripheral insulating layer 2243, and the peripheral interlayer insulating layer 2244) the second end ZL22 of the second transfer electrode ZL2 and the third The first end DB1 of the data test line line DB.
  • the fourth connection line LL4 may not be parallel to the second direction Y, for example, intersect the second direction Y at a certain angle.
  • the intersection angle is 20° or less.
  • the second transfer electrode ZL2 may also not be parallel to the first direction X, for example, intersect the first direction X at a certain angle.
  • the intersection angle is 20° or less.
  • the first conductive layer 201 further includes a fifth connection line LL5 .
  • the electrostatic discharge circuit ESD further includes a fourth electrostatic discharge unit ESD40 located on a side (eg, left side) of the plurality of first electrostatic discharge units ESD10 close to the second side 12 of the display area 10 .
  • the fifth connection line LL5 is substantially "L" shaped.
  • one end of the fifth connection line LL5 is connected to the second end LL42 of the fourth connection line LL4 (eg, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ).
  • the other end of the fifth connection line LL5 is connected to the control end ESD41 of the fourth electrostatic discharge unit ESD40 to remove static electricity generated by the first control line CT11.
  • the first conductive layer 201 further includes a sixth connection line LL6 and a seventh connection line LL7 .
  • the sixth connection trace LL6 and the seventh connection trace LL7 are bent and traced.
  • the electrostatic discharge circuit ESD further includes a fifth electrostatic discharge unit ESD50 and a sixth electrostatic discharge unit ESD60.
  • the sixth electrostatic discharge unit ESD60 is located on one side (eg, the left side) of the fourth electrostatic discharge unit ESD40 close to the second side 12 of the display area 10 .
  • the fifth electrostatic discharge unit ESD50 is located between the fourth electrostatic discharge unit ESD40 and the sixth electrostatic discharge unit ESD60.
  • one end of the sixth connection line LL6 is connected to the first data test line DR (for example, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ), and the other end of the sixth connection line LL6 It is connected to the control terminal ESD51 of the fifth electrostatic discharge unit ESD50 (eg, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ) to remove static electricity generated by the first data test line DR.
  • one end of the seventh connection line LL7 is connected to the second data test line DG (for example, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ), and the other end of the seventh connection line LL7 It is connected to the control terminal ESD61 of the sixth electrostatic discharge unit ESD60 (eg, through a via hole passing through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ) to remove static electricity generated by the second data test line DG.
  • FIG. 9 is a partial structural schematic diagram of a peripheral area of a display substrate on a fourth side of the display area according to at least one embodiment of the present disclosure.
  • the display substrate 1 further includes a bonding area 21 and a signal access unit 22 located on the fourth side 14 of the display area 10 .
  • the signal access unit 22 is located between the bonding area 21 and the display area 10 .
  • the bonding area 21 includes a plurality of contact pads arranged along the first direction X.
  • the plurality of contact pads include a first contact pad 211 and a second contact pad 212 near the second side 12 of the display area 10 (eg, on the left side of the bonding area 21 ), and a first contact pad 211 near the third side 13 of the display area 10 .
  • the three contact pads 213 and the fourth contact pad 214 (eg, on the right side of the bonding area 21 ).
  • the second end DR2 of the first data test line DR extends to the fourth side 14 of the display area 10 and is connected to the second contact pad 212 .
  • the second end DG2 of the second data test line DG extends to the fourth side 14 of the display area 10 and is connected to the first contact pad 211 .
  • the second end CW2 of the control signal line CW extends to the fourth side 14 of the display area 10 and is connected to the third contact pad 213 .
  • the second end DB2 of the third data test line DB extends to the fourth side 14 of the display area 10 and is connected to the fourth contact pad 214 .
  • the plurality of contact pads are configured to be electrically connected to external test circuits (eg, bonding, probe contact, etc.) during the test phase, so as to apply test signals to the sub-pixels P10 through the test circuit CT, thereby testing the display of the sub-pixels P10 of the display substrate 1. Performance in black and white, monochrome, and grayscale.
  • external test circuits eg, bonding, probe contact, etc.
  • the signal access unit 22 is configured to bond with a signal input element, eg, the signal input element including an integrated circuit (IC), and another example, the signal input element including a data driving circuit IC.
  • the signal input element provides a display signal of the display substrate 1 in the display stage, so that the sub-pixel P10 displays a picture.
  • portions of the first data test line DR, the second data test line DG, the third data test line DB, and the control signal line CW are located on the second conductive layer 203 .
  • the first data test line DR, the second data test line DG, the third data test line DB and other parts of the control signal line CW are located in the first conductive layer 201 .
  • the plurality of power supply lines further include a third power supply line VSS and a fourth power supply line VDD.
  • the third power supply line VSS is configured to provide a third power supply signal to the plurality of sub-pixels P10.
  • the fourth power supply line VDD is configured to supply a fourth power supply signal to the plurality of sub-pixels P10.
  • the fourth power supply line VDD is a power supply line for supplying a high voltage to the plurality of sub-pixels P10
  • the third power supply line VSS is a power supply line for supplying a low voltage (lower than the aforementioned high voltage) to the plurality of sub-pixels P10.
  • the fourth power supply line VDD provides a constant fourth power supply voltage
  • the fourth power supply voltage is a positive voltage
  • the third power supply line VSS provides a constant third power supply voltage
  • the third power supply voltage may be a negative voltage, etc.
  • the third supply voltage may be a ground voltage.
  • the plurality of contact pads of the bonding area 21 further include a fifth contact pad 215 , a sixth contact pad 216 , a seventh contact pad 217 and an eighth contact pad 218 .
  • the seventh contact pad 217 is located on the side of the second contact pad 212 close to the second side 12 of the display area 10 (eg, the left side in FIG. 9 )
  • the eighth contact pad 218 is located on the fourth contact pad 214 close to the display area The side of the third side 13 of 10 (eg the right side in FIG. 9 ).
  • the fifth contact pad 215 is located between the seventh contact pad 217 and the second contact pad 212
  • the sixth contact pad 216 is located between the fourth contact pad 214 and the eighth contact pad 218 .
  • two ends of the third power line VSS are respectively connected to the seventh contact pad 217 and the eighth contact pad 218 and route around the display area 10 (eg, the second side 12 , the third side 13 and the fourth side 14 ).
  • the third power supply line VSS is located on a side of the first data test line DR and the third data test line DB away from the display area 10 .
  • both ends of the fourth power line VDD are connected to the fifth contact pad 215 and the sixth contact pad 216 respectively, and are routed between the signal access unit 22 and the display area 10 and extend to the display area 10 .
  • the orthographic projection of the fourth power line VDD on the board surface S of the base substrate 100 is on the substrate with the first data test line DR, the second data test line DG, the third data test line DB and the control signal line CW The orthographic projections on the board surface S of the substrate 100 overlap to reduce wiring space.
  • the fourth power line VDD is located in the second conductive layer 203, the first data test line DR, the second data test line DG, the third data test line DB and the control signal line
  • the CW is spaced and insulated from the second conductive layer 203 .
  • the first data test line DR, the second data test line DG, the third data test line DB and the control signal line CW are located on the first conductive layer 201 .
  • the first data test line DR includes a first portion DR3 connected to its first end DR1, a second portion DR4 connected to its second end DR2, and an eighth connection trace LL8 .
  • the first part DR3 and the second part DR4 of the first data test line DR are located in the second conductive layer 203
  • the eighth connection line LL8 is located in the first conductive layer 201
  • both ends of the eighth connection line LL8 are respectively connected to the first conductive layer 201.
  • the first portion DR3 and the second portion DR4 of the data test line DR are connected (eg, through via holes penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ).
  • the second data test line DG includes a first portion DG3 connected to its first end DG1, a second portion DG4 connected to its second end DG2, and a ninth connection trace LL9.
  • the first part DG3 and the second part DG4 of the second data test line DG are located on the second conductive layer 203
  • the ninth connection line LL9 is located in the first conductive layer LL9
  • the two ends of the ninth connection line LL9 are respectively connected to the second conductive layer LL9.
  • the first portion DG3 and the second portion DG4 of the data test line DG are connected (eg, through via holes penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244).
  • the eighth connection line LL8 and the ninth connection line LL9 are bent lines.
  • the orthographic projections of the eighth connection line LL8 and the ninth connection line LL9 on the board surface S of the base substrate 100 overlap with the orthographic projection of the fourth power supply line VDD on the board surface S of the base substrate 100 ( For example, the left side of the signal access unit 22 in FIG. 9 ) to reduce the wiring space.
  • the third data test line DB includes a first portion DB3 connected to its first end DB1 , a second portion DB4 connected to its second end DB2 , and a tenth connection trace LL10 .
  • the first part DB3 and the second part DB4 of the third data test line DB are located in the second conductive layer 203
  • the tenth connection line LL10 is located in the first conductive layer 201
  • both ends of the tenth connection line LL10 are respectively connected to the third
  • the first portion DB3 and the second portion DB4 of the data test line DB are connected (eg, through via holes penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ).
  • the control signal line CW includes a first portion CW3 connected to its first end CW1 , a second portion CW4 connected to its second end CW2 , and an eleventh connection line LL11 .
  • the first part CW3 and the second part CW4 of the control signal line CW are located in the second conductive layer 203
  • the eleventh connection line LL11 is located in the first conductive layer 201 .
  • Two ends of the eleventh connection trace LL11 are respectively connected to the first portion CW3 and the second portion CW4 of the control signal line CW (eg, through via holes penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 ).
  • the tenth connection wire LL10 and the eleventh connection wire LL11 are bent and routed.
  • the orthographic projections of the tenth connection line LL10 and the eleventh connection line LL11 on the board surface S of the base substrate 100 overlap with the orthographic projection of the fourth power supply line VDD on the board surface S of the base substrate 100 (eg, the right side of the signal access unit 22 in FIG. 9 ) to reduce wiring space.
  • the fourth side 14 of the first power line VGH and the second power line VGL also extends to the display area 10 and is connected to other contact pads of the bonding area 21 .
  • the first power supply line VGH and the second power supply line VGL also overlap with the fourth power supply line VDD on the fourth side 14 of the display area 10, and the first power supply line VGH and the second power supply line VGL in the overlapping area adopt layer-changing wiring The way.
  • the wiring modes of the first power line VGH and the second power line VGL are related to the first data test line DR, the second data test line DG, the third data test line DB and the control signal line
  • the wiring method of CW is similar, and will not be described in detail here.
  • the signal access unit 22 includes a plurality of signal access pads 221 .
  • the first conductive layer 201 further includes a twelfth connection line LL12.
  • One end of the twelfth connection line LL12 is connected to at least one of the plurality of signal access pads 221, and the other end of the twelfth connection line LL12 is connected to the control signal line CW (for example, the second part CW4) (for example, through vias penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244).
  • the twelfth connection line LL12 can provide a control signal to the test circuit CT through the control signal line CW in the display stage to turn off the test circuit CT, so that the sub-pixel P10 displays a picture based on the display signal provided by the signal input unit.
  • FIG. 10 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • the display device 2 includes the display substrate 1 provided in any embodiment of the present disclosure and a signal input element.
  • the display substrate 1 adopts the display substrate 1 shown in FIG. 2 .
  • the signal input element includes a data drive circuit IC.
  • the data driving circuit IC may be bonded to the signal input unit 22 of the display substrate 1 .
  • the data driving circuit IC provides display signals of the display substrate 1 in the display stage, so that the sub-pixels P10 display a picture.
  • the display device 2 may be a wearable device.
  • the display device 2 can also be any product or component with display function, such as OLED panel, OLED TV, QLED panel, QLED TV, mobile phone, tablet computer, notebook computer, digital photo frame, navigator, etc.
  • the display device 2 may further include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

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Abstract

一种显示基板(1)及显示装置。显示基板(1)包括衬底基板(100)、多个子像素(P10)、多条数据线(D10)、控制信号线(CW)、数据测试线(DR/DG/DB)、测试电路(CT)以及辅助电极线(SW)。测试电路(CT)包括多个测试单元(CT1)，多个测试单元(CT1)中至少一个测试单元(CT1)的每个包括第一控制线(CT11)以及多个控制开关(CT12)，辅助电极线(SW)与第一控制线(CT11)彼此并联连接，且多个控制开关(CT12)中至少一个控制开关(CT12)的部分在衬底基板(100)的板面(S)上的正投影位于第一控制线(CT11)和辅助电极线(SW)在衬底基板(100)的板面(S)上的正投影之间。显示基板(1)可以降低第一控制线(CT11)的阻抗，提高第一控制线(CT11)的传输效率。

Description

显示基板及显示装置 技术领域
本公开的实施例涉及一种显示基板及显示装置。
背景技术
对于OLED(OrganicLight-Emitting Diode，有机发光二极管)显示产品，其电路单元类型众多，如像素电路、栅极驱动电路(Gate Driver on Array，GOA)、数据选择电路(Multiplexer，MUX)及测试电路(Cell Test，CT)等。每种电路在显示中均发挥着各自的作用。其中，测试电路单元作为一种测试电路结构，检测显示产品的像素单元是否显示正常，在显示产品的面板(panel)测试阶段发挥着重要作用。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板、多个子像素、多条数据线、控制信号线、多条数据测试线、测试电路以及辅助电极线。衬底基板包括显示区以及至少位于所述显示区一侧的周边区；多个子像素位于所述显示区且阵列排布；多条数据线，位于所述显示区且配置为向所述多个子像素提供数据信号；控制信号线位于所述周边区且位于所述显示区的至少一侧；多条数据测试线位于所述周边区且位于所述显示区的至少一侧；测试电路位于所述周边区并与所述多条数据线、所述控制信号线和所述多条数据测试线电连接，被配置为在所述控制信号线的控制下通过所述多条数据测试线将测试信号传递给所述多条数据线，其中，所述测试电路包括多个测试单元，多个所述测试单元中至少一个测试单元的每个包括第一控制线以及多个控制开关，所述多个控制开关的包括控制端，所述第一控制线和所述控制信号线以及所述多个控制开关的控制端连接；辅助电极线位于所述周边区并与所述第一控制线彼此并联连接，且所述多个控制开关中至少一个控制开关的部分在所述衬底基板的板面上的正投影位于所述第一控制线和所述辅助电极线在所述衬底基板的板面上的正投影之间。
例如，在本公开至少一实施例提供的显示基板中，所述第一控制线和所述辅助电极线相对于所述衬底基板位于不同层，以及所述第一控制线和所述辅助电极线分别位于彼此间隔绝缘的第一导电层和第二导电层。
例如，在本公开至少一实施例提供的显示基板中，所述辅助电极线位于所述测试电路的远离所述显示区的一侧或靠近所述显示区的一侧。
例如，本公开至少一实施例提供的显示基板还包括设置在所述测试电路与所述显示区之间的静电释放电路，所述静电释放电路与所述多条数据线电连接，所述辅助电极线位于所述测试电路与所述静电释放电路之间。
例如，本公开至少一实施例提供的显示基板还包括多个连接线，所述多条连接线分 别设置于所述多个控制开关之间，所述第一控制线与所述多个控制开关的有源层交叠，以及所述第一控制线与有源层的交叠部分形成所述多个控制开关的控制端，所述多条连接线的第一端与所述第一控制线连接，所述多个条连接线的第二端与所述辅助电极线连接。
例如，在本公开至少一实施例提供的显示基板中，所述多条数据测试线在所述测试电路的远离所述显示区的一侧沿第一方向延伸且沿第二方向间隔设置，所述第一方向和所述第二方向交叉，所述多个控制开关的第一端与所述多条数据测试线分别对应连接，且配置为接收所述多条数据测试线提供的测试信号，所述多个控制开关的第二端与所述多条数据线分别对应电连接。
例如，本公开至少一实施例提供的显示基板还包括多个第一引线段和多条数据引线，所述多个第一引线段和所述多条数据引线沿所述第二方向延伸，所述多个第一引线段分别对应连接所述多条数据测试线和所述多个控制开关的第一端，所述多条数据引线分别对应连接所述多个控制开关的第二端和所述多条数据线。
例如，在本公开至少一实施例提供的显示基板中，所述多条数据引线包括第二引线段，多个所述第二引线段分别对应连接所述多个控制开关的第二端和所述静电释放电路，所述多个第一引线段和所述多个第二引线段位于第三导电层，所述第三导电层位于所述第一导电层和所述第二导电层之间且彼此间隔绝缘，所述多个第二引线段在所述衬底基板的板面上的正投影和所述辅助电极在所述衬底基板的板面上的正投影相互交叠。
例如，在本公开至少一实施例提供的显示基板中，所述多条数据引线还包括第三引线段，所述第三引线段位于所述周边区且位于所述显示区和所述静电释放电路之间，多条所述第三引线段的一端与所述静电释放电路的控制端电连接，所述多条第三引线段的另一端与所述多条数据线分别对应连接，所述第三引线段位于所述第三导电层。
例如，在本公开至少一实施例提供的显示基板中，所述多个子像素中的至少一个包括像素驱动电路以及发光元件，其中，所述像素驱动电路包括半导体层，第一显示区金属层、第二显示区金属层以及第三显示区金属层，发光元件位于所述像素驱动电路远离所述衬底基板的一侧且与所述像素驱动电路的第三显示区金属层连接，所述第一绝缘层位于所述衬底基板上，所述半导体层位于所述第一显示区金属层的靠近所述衬底基板的一侧，所述第二显示区金属层位于所述第一显示区金属层的远离所述衬底基板的一侧，所述第三显示区金属层位于所述第二显示区金属层远离所述衬底基板的一侧，所述第一导电层与所述第一显示区金属层同层设置，所述第三导电层与所述第二显示区金属层同层设置，所述第二导电层与所述第三显示区金属层同层设置，所述多个控制开关的有源层与所述半导体层同层设置，所述多条连接线位于所述第一导电层，以及所述多条连接线的第二端与所述辅助电极线连接。
例如，在本公开至少一实施例提供的显示基板中，所述像素驱动电路还包括第一晶体管和存储电容，所述第一晶体管包括栅极、源电极、漏电极以及有源层，所述存储电容包括第一极板和第二极板，所述有源层位于所述半导体层，所述栅极和所述第一极板 位于所述第一显示区金属层，所述第二极板位于所述第二显示区金属层，所述源电极和所述漏电极位于所述第三显示区金属层。
例如，在本公开至少一实施例提供的显示基板中，所述测试电路还包括至少一个虚拟测试单元，所述至少一个虚拟测试单元位于所述测试电路的远离所述多个测试单元的一侧，所述第二导电层包括多个第一转接电极，所述至少一个虚拟测试单元的每个包括多个虚拟控制开关，所述多个虚拟控制开关的第一端与所述多个数据测试线分别对应连接，所述多个虚拟控制开关的控制端与所述第一控制线连接，所述多个转接电极分别连接所述多个虚拟控制开关的第一端和第二端。
例如，本公开至少一实施例提供的显示基板还包括多条电源线，所述多条电源线围绕所述显示区的至少一侧走线，其中，所述多条电源线包括第一电源线和第二电源线，所述第一电源线配置为提供第一电源信号，所述第二电源线配置为提供第二电源线，所述第一电源线和所述第二电源线的至少部分位于所述第二导电层，所述第一电源线在所述静电释放电路的远离所述显示区的一侧走线，所述第二电源线在所述静电释放电路的靠近所述显示区的一侧走线，所述第一电源线和所述第二电源线分别与所述静电释放电路的第一端和第二端连接，所述静电释放电路包括多个第一静电释放单元，所述多个第二引线段的远离所述测试电路的一端与所述多个第一静电释放单元的控制端分别对应连接。
例如，在本公开至少一实施例提供的显示基板中，所述测试电路和所述静电释放电路位于所述显示区的第一侧，所述显示区的第二侧和第三侧相对设置且与所述第一侧临接，所述多条数据测试线包括第一数据测试线、第二数据测试线和第三数据测试线，所述第一数据测试线和所述第二数据测试线的至少部分围绕所述显示区的第二侧和第一侧走线，所述第二数据测试线位于所述第一数据测试线靠近所述显示区的一侧，所述第三数据测试线和所述控制信号线的至少部分围绕所述显示区的第三侧和第一侧走线，所述控制信号线位于所述第三数据测试线靠近所述显示区的一侧，在所述测试电路的远离所述显示区的一侧，所述第二数据测试线位于所述第一数据测试线和所述第三数据测试线之间，所述第一数据测试线位于远离所述测试电路的一侧，所述第一导电层包括第一连接走线，所述第一连接走线沿所述第二方向延伸，所述半导体层包括多个第一电阻，所述控制信号线的第一端位于所述显示区的第一侧且靠近所述测试电路，所述第一连接走线的一端与所述控制信号线的第一端连接，所述第一连接走线的另一端与所述第一控制线的靠近所述显示区的第三侧的一端连接，所述第一数据测试线和所述第二数据测试线的第一端位于所述测试电路的远离所述显示区的一侧，所述多个第一电阻的其中至少之一连接所述第一数据测试线的第一端和所述控制信号线，所述多个第一电阻的其中至少另一连接所述第二数据测试线和第一端和所述控制信号线。
例如，在本公开至少一实施例提供的显示基板中，所述第一数据测试线、所述第二数据测试线、所述第三数据测试线、所述控制信号线以及所述第一控制线中的至少其中之一与所述静电释放电路连接。
例如，在本公开至少一实施例提供的显示基板中，所述静电释放电路还包括第二静电释放单元，所述第二静电释放单元位于所述多个第一静电释放单元的至少一侧，且位于靠近所述显示区的第三侧的一侧，所述第一导电层包括第二连接走线以及第三连接走线，所述半导体层包括第二电阻，所述第二连接走线的一端与所述第二静电释放单元的控制端连接，所述第二连接走线的另一端与所述控制信号线的第一端连接，所述第二电阻连接所述第二静电释放单元的控制端和所述第一电源线，所述静电释放电路还包括第三静电释放单元，所述第三静电释放单元位于所述第二静电释放单元的靠近所述显示区的第三侧的一侧，所述第三连接走线的一端与所述第三数据测试线连接，所述第三连接走线的另一端与所述第三静电释放单元的控制端连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一导电层还包括第四连接走线，所述第四连接走线沿所述第二方向延伸，所述半导体层包括第三电阻，所述第二导电层包括第二转接电极，所述第二转接电极沿所述第一方向延伸，所述第四连接走线的第一端与所述第一控制线的靠近所述显示区的第二侧的一端连接，所述第四连接走线的第二端与所述第二转接电极的第一端连接，所述第三数据测试线的第一端位于所述测试电路的远离所述显示区的一侧，以及所述第三电阻连接所述第二转接电极的第二端和所述第三数据测试线的第一端。
例如，在本公开至少一实施例提供的显示基板中，所述第一导电层还包括第五连接走线，所述静电释放电路还包括第四静电释放单元，所述第四静电释放单元位于所述多个第一静电释放单元的靠近所述显示区的第二侧的一侧，所述第五连接走线的一端与所述第四连接走线的第二端连接，所述第五连接走线的另一端与所述第四静电释放单元的控制端连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一导电层还包括第六连接走线和第七连接走线，所述静电释放电路还包括第五静电释放单元和第六静电释放单元，所述第六静电释放单元位于所述第四静电释放单元的靠近所述显示区的第二侧的一侧，所述第五静电释放单元位于所述第四静电释放单元和所述第六静电释放单元之间，所述第六连接走线的一端与所述第一数据测试线连接，所述第六连接走线的另一端与所述第五静电释放单元的控制端连接，所述第七连接走线的一端与所述第二数据测试线连接，所述第七连接走线的另一端与所述第六静电释放单元的控制端连接。
例如，本公开至少一实施例提供的显示基板还包括位于所述显示区的与所述第一侧相对的第四侧的邦定区和信号接入单元，所述信号接入单元位于所述邦定区和所述显示区之间，所述邦定区包括多个沿所述第一方向排列的接触垫，所述多个接触垫包括靠近所述显示区的第二侧的第一接触垫和第二接触垫，以及靠近所述显示区的第三侧的第三接触垫和第四接触垫，所述第一数据测试线的第二端延伸至所述显示区的第四侧并与所述第二接触垫连接，所述第二数据测试线的第二端延伸至所述显示区的第四侧并与所述第一接触垫连接，所述控制信号线的第二端延伸至所述显示区的第四侧并与所述第三接触垫连接，所述第三数据测试线的第二端延伸至所述显示区的第四侧并与所述第四接触 垫连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一数据测试线、所述第二数据测试线、所述第三数据测试线以及所述控制信号线的部分位于第二导电层。
例如，在本公开至少一实施例提供的显示基板中，所述多条电源线还包括第三电源线和第四电源线，所述第三电源线配置为向所述多个子像素提供第三电源信号，所述第四电源线配置为向所述多个子像素提供第四电源信号，所述多个接触垫还包括第五接触垫、第六接触垫、第七接触垫以及第八接触垫，所述第七接触垫位于所述第二接触垫的靠近所述显示区的第二侧的一侧，所述第八接触垫位于所述第四接触垫的靠近所述显示区的第三侧的一侧，所述第五接触垫位于所述第七接触垫和所述第二接触垫之间，所述第六接触垫位于所述第四接触垫和所述第八接触垫之间，所述第三电源线的两端分别与所述第七接触垫和所述第八接触垫连接且围绕所述显示区走线，所述第三电源线位于所述第一数据测试线和所述第三数据测试线的远离所述显示区的一侧，所述第四电源线的两端分别与所述第五接触垫和所述第六接触垫连接，且在所述信号接入单元和所述显示区之间走线并延伸至所述显示区，所述第四电源线在所述衬底基板的板面上的正投影，与所述第一数据测试线、所述第二数据测试线、所述第三数据测试线以及所述控制信号线在所述衬底基板的板面上的正投影交叠，在所述第四电源线与所述第一数据测试线、所述第二数据测试线、所述第三数据测试线以及所述控制信号线的所述衬底基板的板面上的正投影交叠的区域，所述第四电源线位于第二导电层，所述第一数据测试线、所述第二数据测试线、所述第三数据测试线以及所述控制信号线与所述第二导电层间隔绝缘。
例如，在本公开至少一实施例提供的显示基板中，所述第一数据测试线包括与其第一端连接的第一部分、与其第二端连接的第二部分以及第八连接走线，所述第一数据测试线的第一部分和第二部分位于第二导电层，所述第八连接走线位于所述第一导电层，所述第八连接走线的两端分别与所述第一数据测试线的第一部分和第二部分连接，所述第二数据测试线包括与其第一端连接的第一部分、与其第二端连接的第二部分以及第九连接走线，所述第二数据测试线的第一部分和第二部分位于所述第二导电层，所述第九连接走线位于所述第一导电层，所述第九连接走线的两端分别与所述第二数据测试线的第一部分和第二部分连接，所述第八连接走线和所述第九连接走线在所述衬底基板的板面上的正投影与所述第四电源线在所述衬底基板的板面上的正投影交叠。
例如，在本公开至少一实施例提供的显示基板中，所述第三数据测试线包括与其第一端连接的第一部分、与其第二端连接的第二部分以及第十连接走线，所述第三数据测试线的第一部分和第二部分位于所述第二导电层，所述第十连接走线位于所述第一导电层，所述第十连接走线的两端分别与所述第三数据测试线的第一部分和第二部分连接，所述控制信号线包括与其第一端连接的第一部分、与其第二端连接的第二部分以及第十一连接走线，所述控制信号线的第一部分和第二部分位于第二导电层，所述第十一连接走线位于第一导电层，所述第十一连接走线的两端分别与所述控制信号线的第一部分和第二部分连接，所述第十连接走线和所述第十一连接走线在所述衬底基板的板面上的正 投影与所述第四电源线在衬底基板的板面上的正投影交叠。
例如，在本公开至少一实施例提供的显示基板中，所述信号接入单元包括多个信号接入垫，所述第一导电层还包括第十二连接走线，所述第十二连接走线的一端与所述多个信号接入垫的其中至少之一连接，所述第十二连接走线的另一端与所述控制信号线连接。
本公开至少一实施例提供一种显示装置，包括上述任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板的测试电路单元的结构示意图；
图1B为一种显示基板的测试电路工作原理示意图；
图2为本公开至少一实施例提供的一种显示基板的示意图；
图3为本公开至少一实施例提供的一种显示基板的周边区在显示区的第一侧的部分结构示意图；
图4为沿图3中线A-B的截面图；
图5为本公开至少一实施例提供的一种显示基板的显示区的截面示意图；
图6为本公开至少一实施例提供的一种显示基板的周边区在显示区的第一侧的另一部分结构示意图；
图7A为本公开至少另一实施例提供的一种显示基板的周边区在显示区的第一侧的再一部分结构示意图；
图7B为图7A中虚拟测试单元的放大示意图；
图8为本公开至少一实施例提供的一种显示基板的周边区在显示区的第一侧的再一部分结构示意图；
图9为本公开至少一实施例提供的一种显示基板的周边区在显示区的第四侧的部分结构示意图；以及
图10为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并 不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同。为了描述方便，在部分附图中，给出了“上”、“下”、“前”、“后”，本公开的实施例中，竖直方向为从上到下的方向，竖直方向为重力方向，水平方向为与竖直方向垂直的方向，从右到左的水平方向为从前到后的方向。
图1A为一种显示基板的测试电路单元的结构示意图；图1B为一种显示基板的测试电路工作原理示意图。
常用于穿戴产品的显示基板的测试电路的测试单元CT0的基本结构如图1A所示。例如，测试单元CT0包括多个测试开关CT01。例如，多个测试开关CT01包括三个，分别与不同的数据测试信号线电连接。在图1A中，测试单元CT0的第一极(例如源极或漏极其中之一)，接收DR0数据信号、DG0数据信号、DB0数据信号。DR0信号、DG0信号、DB0信号分别由为数据信号，且由不同的数据测试信号线提供。例如，测试单元CT0(例如测试开关CT01)的栅极接收CTSW0开关信号。
上述测试电路的工作原理如图1B所示。例如，图1A所示测试电路的工作原理为：测试单元CT01响应于接收的开关信号打开测试开关CT01开关，即通过与测试开关CT01的栅极连接的控制信号线CTSW0接收的开关信号；将通过数据测试信号线CT_D传输的数据信号(例如，DR0数据信号、DG0数据信号或DB0数据信号)提供给Data_R数据线、Data_G数据线或Data_B数据线。例如，Data_R数据线、Data_G数据线以及Data_B数据线分别与不同列子像素P10对应连接。此时，所有子像素的数据信号的电压相同，只能显示纯色画面。若在检测时出现了着色点，例如黑点，则说明检测出该显示面板中有异常点。
例如，对于显示器件而言，信号线的阻抗对于信号的传输效率及显示效果起着重要作用。如图1A所示，对于常用测试单元CT0，测试开关CT01的栅极为单层走线(例如位于第一栅电极层)，并分别连接在控制信号线CTSW0上，这样的设计通常随着信号线走线距离的增加，其阻抗也会随之增加。例如图1A中所示出的三个测试开关CT01的栅极与控制信号线的沿图中纵向上的距离不相同，且相距控制信号线越远的测试开关CT01接收到的信号的阻抗越大。此外，信号的阻抗的增加还会造成每个测试开关CT01栅极信号强弱不均，从而影响测试结果。
本公开至少一实施例提供一种显示基板，该显示基板包括：衬底基板、多个子像素、多条数据线、控制信号线、数据测试线、测试电路以及辅助电极线。衬底基板包括显示区以及至少位于显示区一侧的周边区；多个子像素位于显示区且阵列排布；多条数据线位于显示区且配置为向多个子像素提供数据信号；控制信号线位于周边区且位于显示区的至少一侧；多条数据测试线位于周边区且位于显示区的至少一侧；测试电路位于周边区并与多条数据线、控制信号线和多条数据测试线电连接，被配置为在控制信号线的控制下通过多条数据测试线将测试信号传递给多条数据线，测试电路包括多个测试单元， 多个测试单元中至少一个测试单元的每个包括第一控制线以及多个控制开关，多个控制开关包括控制端，第一控制线和控制信号线以及所述多个控制开关的控制端连接；辅助电极线位于周边区并与第一控制线彼此并联连接，且多个控制开关中至少一个控制开关的部分在衬底基板的板面上的正投影位于第一控制线和辅助电极线在衬底基板的板面上的正投影之间。
本公开至少一实施例还提供一种包括上述显示基板的显示装置。
在上述实施例提供的显示基板和显示装置中，该显示基板可以降低第一控制线的阻抗，提高第一控制线的传输效率，防止信号的失真，为测试电路提供更加稳定的控制信号。
下面结合附图对本公开的实施例及其示例进行详细说明。
图2为本公开至少一实施例提供的一种显示基板的示意图。图3为本公开至少一实施例提供的一种显示基板的周边区在显示区的第一侧的部分结构示意图。
例如，在一些实施例中，如图2所示，显示基板1包括衬底基板100。衬底基板100包括显示区10和周边区20。例如，周边区20围绕显示区10。显示基板1包括多个子像素P10。多个子像素P10位于显示区10且阵列排布，例如沿第一方向X和第二方向Y排布为多行多列。显示基板1还包括多条数据线D10和控制信号线CW。多条数据线D10位于显示区10，例如沿第二方向Y(纵向)穿过显示区10。多条数据线D10配置为分别向各列对应的子像素P10提供数据信号。控制信号线CW位于周边区20且围绕显示区10的至少一侧走线，例如围绕显示区10的第三侧13(例如，图2中显示区10的右侧)走线。
例如，在本公开中所涉及的第一方向X与第二方向Y的夹角在70°到90°之间，并包括70°和90°。例如，第一方向X与第二方向Y的夹角为70°、90°或80°等，可根据实际情况设定，本公开的实施例对此不作限制。例如，第一方向X与所述第二方向Y的夹角还可以为75°、85°等。
例如，衬底基板100可以为玻璃板、石英板、金属板或树脂类板件等。例如，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料；例如，衬底基板100可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
如图2和图3所示，显示基板1还包括测试电路CT。测试电路CT位于周边区20，例如位于显示区10的第一侧11(例如，图2中显示区10的上侧)。测试电路CT与多个子像素素P10分别对应的数据线D10电连接以传输测试信号(例如数据信号)。测试电路CT包括多个测试单元CT1(如图3所示)。至少一个测试单元CT1每个包括第一控制线CT11以及多个控制开关CT12。多个控制开关CT12的每个包括控制端CT121(例如栅极)，第一控制线CT11和控制信号线CW以及测试单元CT1中多个控制开关CT12的控制端CT121连接，以向多个控制开关CT12提供控制信号。例如，测试电路CT在控制信号线CW的控制下(例如，通过多条数据测试线DR/DG/DB)将测试信号传递给多 条数据线D10。例如，第一控制线CT11和控制开关CT12的控制端CT121同层设置且一体形成。
例如，如图2和图3所示，显示基板1还包括辅助电极线SW。辅助电极线SW位于周边区20，例如，显示区10的第一侧11。例如，辅助电极线SW和第一控制线CT11的走线方向基本相同，例如都沿第一方向X延伸。例如，辅助电极线SW与第一控制线CT11彼此并联连接，且多个控制开关CT12中至少一个控制开关CT12的至少部分在衬底基板100的板面S(如图4所示)上的正投影位于第一控制线CT11和辅助电极线SW在衬底基板100的板面S上的正投影之间。例如，在图3中，多个控制开关CT12的每个还包括第一端CT122(例如远离辅助电极线SW的第一端)和第二端CT123(例如靠近辅助电极线SW的第一端)，第一控制线CT11和辅助电极线SW之间间隔多个控制开关CT12的第二端CT123。也就是说，控制开关CT12的第二端CT123在衬底基板100的板面S上的正投影，位于第一控制线CT11和辅助电极线SW在衬底基板100的板面S上的正投影之间。
例如，例如，辅助电极线SW和第一控制线CT11也可以不与第一方向X平行，例如与第一方向X相交一定的角度。例如，该交叉角度小于等于20°。
例如，将多个控制开关CT12每个的控制端CT121连接到第一控制线CT11的同时，将多个控制开关CT12的控制端CT121串接在一起，从而与每个控制开关CT12的控制端CT121连接的第一控制线CT11和辅助电极线SW形成了并联结构。根据并联电阻公式：R＝(R CT11+R SW)/(R CT11*R SW)，其中，R CT11表示第一控制线CT11的电阻，R SW表示辅助电极线SW的电阻，辅助电极线SW和第一控制线CT11并联之后第一控制线CT11的阻抗会降低。
在本公开上述实施例中，该显示基板1可以在不改变控制开关CT12的结构或工作性能的同时，降低第一控制线CT11的阻抗，提高第一控制线CT11的传输效率，防止信号的失真，为测试电路提供更加稳定的控制信号。
需要说明的是，以控制开关CT12为P型晶体管为例。控制开关CT12也可以选择N型晶体管，本公开实施例不以此为限。例如，控制开关CT12的控制端CT121，例如为晶体管的栅极，控制开关CT12的第一端CT122和第二端CT123分别为晶体管的源极和漏极。
图4为沿图3中线A-B的截面图。
例如，在一些实施例中，如图3和图4所示，第一控制线CT11和辅助电极线SW相对于衬底基板100位于不同层，即非同层设置。例如，第一控制线CT11和辅助电极线SW分别位于彼此间隔绝缘的第一导电层201和第二导电层203。例如，第一导电层201和第二导电层203之间间隔第二周边绝缘层2243和周边层间绝缘层2244。例如，周边层间绝缘层2244位于第一导电层201的远离衬底基板100的一侧，周边层间绝缘层2244位于第二周边绝缘层2243远离衬底基板100的一侧，第二导电层203位于周边层间绝缘层2244远离衬底基板100的一侧。由此，相比于辅助电极线SW位于第一导电层201(例 如，与第一控制线CT11同层设置)，辅助电极线SW的电阻值得以增加，从而进一步降低第一控制线CT11的阻抗。
例如，在一些实施例中，辅助电极线SW位于测试电路CT的远离显示区10的一侧(例如，图3中测试电路CT的上侧)或靠近显示区10的一侧(例如，图3中测试电路CT的下侧)。
例如，在一些实施例中，如图2和图3所示，显示基板1还包括设置在测试电路CT与显示区10之间的静电释放电路ESD。静电释放电路ESD与多条数据线D10电连接，以去除测试电路CT的测试信号被传输过程中产生的静电干扰。辅助电极线SW位于测试电路CT与静电释放电路ESD之间，进而与第一控制线CT11并联。
例如，在一些实施例中，如图3所示，显示基板1还包括多条连接线101。多条连接线101分别设置于多个控制开关CT12之间，即布置在多个控制开关CT12的间隙中。第一控制线CT11与多个控制开关CT12的有源层CT124交叠，以及第一控制线CT11与有源层CT124的交叠部分形成多个控制开关CT12的控制端CT121。例如，第一控制线与控制开关CT12的控制端CT121是一体形成的。例如，多条连接线101的第一端1011与第一控制线CT11连接，多条连接线101的第二端1012与辅助电极线SW连接，使得第一控制线CT11和辅助电极线SW形成并联连接结构。
例如，如图4所示，多条连接线101与第一控制线CT11同层设置且都位于第一导电层201。例如，多条连接线101与第一控制线CT11一体形成。
需要说明的是，在本公开的实施例中，“同层设置”包括两个功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。一次构图工艺例如包括光刻胶的形成、曝光、显影、刻蚀等工序。
例如，在一些实施例中，如图2和图3所示，显示基板1还包括多条数据测试线(例如，第一数据测试线DR、第二数据测试线DG和第三数据测试线DB)。多条数据测试线位于周边区20且围绕显示区10的至少一侧(例如，第一侧11、第二侧12和第三侧13)走线。多条数据测试线在测试电路CT的远离显示区10的一侧(图中的测试电路CT的上方)沿第一方向X延伸且间隔设置。即，在显示区10的第一侧11，多条数据测试线沿第一方向X走线。例如，多个控制开关CT12的每个根据控制端CT121上接收的控制信号。例如，当控制开关CT12为P型晶体管时，控制信号为低电平时，控制开关CT12的控制端CT121打开，从而第一端CT122和第二端CT123可以传输测试信号。多个控制开关CT12的第一端CT122与多条数据测试线分别对应连接，且配置为接收多条数据测试线提供的测试信号。多个控制开关CT12的第二端CT123与多条数据线D10分别对应电连接，以将测试信号提供至显示区10的子像素P10。
例如，在一些实施例中，如图3所示，显示基板1还包括多个第一引线段102和多条数据引线103。多个第一引线段102和多条数据引线103沿第二方向Y延伸。例如，多个第一引线段102分别对应连接多条数据测试线(例如，第一数据测试线DR、第二数 据测试线DG和第三数据测试线DB)和多个控制开关CT12的第一端CT122。例如，多条数据引线103分别对应连接多个控制开关CT12的第二端CT123和多条数据线D10，以在控制开关CT12导通时，将测试信号提供至显示区10的子像素P10。
例如，多个第一引线段102和多条数据引线103也可以不与第二方向Y平行，例如与第二方向Y相交一定的角度。例如，该交叉角度小于等于20°。
例如，在一些实施例中，如图3所示，多条数据引线103的每个分别包括第二引线段1031。多个第二引线段1031分别对应连接多个控制开关CT12的第二端CT123和静电释放电路ESD。
例如，如图4所示，多个第一引线段102和多个第二引线段1031位于第三导电层202。第三导电层202位于第一导电层201和第二导电层203之间且彼此间隔绝缘。例如，第三导电层202位于第二周边绝缘层2243和周边层间绝缘层2244之间。第三导电层202与第二导电层203之间间隔周边层间绝缘层2244。第三导电层202与第一导电层201之间间隔第二周边绝缘层2243。例如，第一引线段102通过贯穿层间绝缘层2244的过孔与控制开关CT12的第一端CT122连接。例如，第二引线段1031通过贯穿层间绝缘层2244的过孔与控制开关CT12的第二端CT123连接。多个第二引线段1031在衬底基板100的板面S上的正投影和辅助电极SW在衬底基板100的板面S上的正投影相互交叠。多个第二引线段1031和辅助电极SW位于不同层以节省布线空间。
例如，如图3所示，多个第一引线段102不与第一控制线CT11交叠，可以避免第一引线段102与第一控制线CT11之间产生寄生电容。
图6为本公开至少一实施例提供的一种显示基板的周边区在显示区的第一侧的另一部分结构示意图。
例如，在一些实施例中，如图2和图6所示，多条数据引线103的每个还包括第三引线段1032。第三引线段1032位于周边区20且位于显示区10和静电释放电路ESD之间。例如，多条第三引线段1032的一端(靠近静电释放电路ESD的一端)与静电释放电路ESD的控制端电连接。多条第三引线段1032的另一端与多条数据线D10分别对应连接，以将测试信号提供至显示区10的子像素P10。例如，所述第三引线段1032位于第三导电层202。
图5为本公开至少一实施例提供的一种显示基板的显示区的截面示意图。
例如，在一些实施例中，如图5所示，多个子像素P10的每个包括像素结构。像素结构包括像素驱动电路104以及发光元件11。像素驱动电路104包括半导体层304，第一显示区金属层301、第二显示区金属层302、第三显示区金属层303、第一绝缘层1242(即第一栅绝缘层)、第二绝缘层1243(即第二栅绝缘层)以及层间绝缘层1244。发光元件11位于像素驱动电路104远离衬底基板100的一侧且与像素驱动电路104的第三显示区金属层303连接。
如图5所示，第一绝缘层1242位于衬底基板100上。半导体层304位于第一绝缘层1242的靠近衬底基板100的一侧。第一显示区金属层301位于第一绝缘层1242远离衬底 基板100的一侧。第二绝缘层1243位于第一显示区金属层301远离衬底基板100的一侧。第二显示区金属层302位于第二绝缘层1243远离衬底基板100的一侧。层间绝缘层1244位于第二显示区金属层302远离所述衬底基板的一侧。第三显示区金属层303位于层间绝缘层1244远离衬底基板100的一侧。
如图5所示，显示基板1还可以包括缓冲层1241和阻挡层1240。缓冲层1241位于半导体层304的靠近衬底基板100的一侧，阻挡层1240位于缓冲层1241靠近衬底基板100的一侧。缓冲层1241作为过渡层，其即可以防止衬底基板中的有害物质侵入显示基板的内部，又可以增加显示基板中的膜层在衬底基板100上的附着力。阻挡层1240可以提供用于形成像素驱动电路104的平坦表面，并且可以避免衬底基板100中可能存在的杂质扩散到子像素驱动电路或像素驱动电路104中而不利影响显示基板的性能。
例如，第一绝缘层1242、第二绝缘层1243以及层间绝缘层1244中的一种或多种的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第一绝缘层1242、第二绝缘层1243以及层间绝缘层1244的材料可以相同也可以不相同。
例如，缓冲层1241的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。例如，阻挡层1240的材料可以包括氧化硅、氮化硅、氧氮化硅等无机绝缘材料，或其它适合的材料。
例如，半导体层304的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌(IGZO))。
例如，第一显示区金属层301、第二显示区金属层302、第三显示区金属层303的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。例如，第一显示区金属层301、第二显示区金属层302、第三显示区金属层303的材料可以相同也可以不同，本公开实施例不以此为限。
例如，在一些实施例中，如图4和图5所示，第一导电层201与第一显示区金属层301同层设置。例如，第三导电层202与第二显示区金属层302同层设置。例如，第二导电层203与第三显示区金属层303同层设置。例如，多个控制开关CT12的有源层CT124与半导体层304同层设置。例如，第二周边绝缘层2243与第二绝缘层1243同层设置，周边层间绝缘层2244与层间绝缘层1244同层设置。由此，简化制备工艺流程。
例如，如图4所示，多条连接线101位于第一导电层201，以及多条连接线101的第二端1012通过贯穿第二周边绝缘层2243和周边层间绝缘层2244(例如，第二绝缘层1243和层间绝缘层1244)的过孔GK1与辅助电极线SW连接。
例如，如图4所示，在周边区20，显示基板1还包括第一周边绝缘层2242、周边缓冲层2241和周边阻挡层2240。第一周边绝缘层2242位于第一导电层201靠近衬底基板100的一侧，周边缓冲层2241位于第一周边绝缘层2242靠近衬底基板100的一侧，周边阻挡层2240位于周边缓冲层2241靠近衬底基板100的一侧。例如，第一周边绝缘层2242与第一绝缘层1242同层设置，周边缓冲层2241与缓冲层1241同层设置，周边阻挡层2240 与阻挡层1240同层设置。
例如，如图5所示，像素驱动电路104还包括第一晶体管12和存储电容13。第一晶体管13包括与发光元件11直接电连接的晶体管，该晶体管例如为开关晶体管(例如发光控制晶体管)或驱动晶体管。第一晶体管12包括栅极122、两个源漏电极(源极123和漏极124)以及有源层121。栅极122位于第一显示区金属层301、两个源漏电极(源极123和漏极124)位于第三显示区金属层303，有源层121位于半导体层304。存储电容13包括第一极板131和第二极板132。例如，第一极板131位于第一显示区金属层301，第二极板132位于第二显示区金属层302。栅极122和第一极板131同层设置。第一极板131和第二极板132之间间隔第二绝缘层1243，以形成电容功能。
例如，在其它实施例中，第一极板131可以设置为位于第二显示区金属层302，第二极板132设置为位于第三显示区金属层303，此时，第一极板131和第二极板132之间间隔侧键绝缘层1244。本公开实施例不以存储电容13的具体设置方式为限。
例如，如图5所示，显示基板1还包括第一平坦化层1245。第一平坦化层1245位于源极123和漏极124(也就是像素驱动电路104)的远离衬底基板100的一侧提供第一平坦化表面，以平坦化像素驱动电路104远离衬底基板100一侧的表面。第一平坦化层1245包括第一过孔252，像素驱动电路104(例如第三显示区金属层303)通过该第一过孔252与发光元件电连接。
例如，第一平坦化层1245的材料包括括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，也可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，本公开的实施例对此不做限定。
例如，如图5所示，显示基板1还包括像素限定层146。发光元件11设置在第二平坦化层1245远离衬底基板100一侧。发光元件11包括第一电极113(例如阳极)、发光层112以及第二电极111(例如为阴极)。第一电极113位于第一平坦化层1245的远离衬底基板100的一侧，并通过过孔252与像素驱动电路104(例如第一晶体管12的漏极124)电连接。第二电极111位于像素限定层146的远离衬底基板100的一侧。像素限定层146位于第一电极113远离衬底基板100的一侧，并包括第一像素开口1461。第一像素开口1461与发光元件11对应设置。发光层112位于第一像素开口1461中且位于第一电极113与第二电极111之间。发光层112直接夹置在第一电极113与第二电极111之间的部分在通电后将会发光，由此该部分所占据的区域对应于发光元件11的发光区。
例如，像素驱动电路104在数据线D10提供的数据信号(例如测试信号)、例如移位寄存器提供的栅极扫描信号和发光控制信号等的控制下产生发光驱动电流，该发光驱动电流使得发光元件11可以发射红光、绿光、蓝光，或可以发白光等。
例如，像素驱动电路104包括常规的2T1C(即两个晶体管和一个电容)像素电路、7T1C(即七个晶体管和一个电容)像素电路等。该像素驱动电路104包括至少一个开关晶体管和一个驱动晶体管(如图5所的第一晶体管12)，该开关晶体管的栅极接收栅极扫描信号，该开关晶体管的源极或漏极与数据线D10连接以接收数据信号。在不同的实施 例中，该像素驱动电路104还可以进一步包括补偿电路，该补偿电路包括内部补偿电路或外部补偿电路，补偿电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以包括复位电路、发光控制电路、检测电路等。本公开的实施例对于第一发光器件的类型、像素电路的具体结构不作限制。
例如，像素限定层146的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，第一电极113的材料可以包括至少一种透明导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。此外，第一电极113可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，发光层112可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。
例如，对于QLED，发光层112可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二电极111可以包括各种导电材料。例如，第二电极111可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，如图5所示，显示基板1还包括封装层147。封装层147位于第二电极111远离衬底基板100的一侧。封装层147将发光元件11(发光元件11)密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件11的劣化。封装层147可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构。封装层147包括至少一层封装子层。例如，封装层147可以包括依次设置的第一无机封装层、第一有机封装层、第二无机封装层。
例如，该封装层147的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
图7A为本公开至少另一实施例提供的一种显示基板的周边区在显示区的第一侧的再一部分结构示意图；图7B为图7A中虚拟测试单元的放大示意图。
例如，在一些实施例中，如图7A和图7B所示，测试电路CT还包括至少一个虚拟测试单元DCT1，至少一个虚拟测试单元DCT1位于测试电路CT的远离多个测试单元CT1的一侧。例如，至少一个虚拟测试单元DCT1的数量为至少两个，并设置在测试电路CT的远离多个测试单元CT1的两侧。第二导电层203包括多个第一转接电极ZL1。 例如，至少一个虚拟测试单元DCT1的每个包括多个虚拟控制开关DCT11。多个虚拟控制开关DCT11的第一端DCT13与多个数据测试线(例如，第一数据测试线DR、第二数据测试线DG和第三数据测试线DB)分别对应连接。例如，多个虚拟控制开关DCT11的控制端DCT12与第一控制线CT11连接。例如，多个转接电极ZL1一一对应地设置在多个虚拟控制开关DCT11中。转接电极ZL1连接虚拟控制开关DCT11的第一端DCT13和第二端DCT14。也就是说，虚拟控制开关DCT11与控制开关CT12的结构相比，多设置了转接电极ZL1。虚拟测试单元DCT1的设置可以增加周边区20在显示区10的第一侧11的走线的均匀性。
例如，在一些实施例中，如图2和图6所示，显示基板1还包括多条电源线(例如包括第一电源线VGH和第二电源线VGL)。多条电源线围绕显示区10的至少一侧(例如第一侧11、第二侧12以及第三侧13)走线。例如，多条电源线包括第一电源线VGH和第二电源线VGL，第一电源线VGH配置为提供第一电源信号(例如高电平电压信号)，第二电源线VGL配置为提供第二电源信号(例如低电平电压信号)。第一电源线VGH和第二电源线VGL的至少部分位于第二导电层203。例如，第一电源线VGH和第二电源线VGL和其它走线(例如图2中第四电源线VDD)交叠走线的部分位于第一导电层201。例如，在显示区10的第一侧11，第一电源线VGH在静电释放电路ESD的远离显示区10的一侧走线，第二电源线VGL在静电释放电路ESD的靠近显示区10的一侧走线。第一电源线VGH和第二电源线VGL分别与静电释放电路ESD的第一端ESD1和第二端ESD2连接。例如，静电释放电路ESD包括多个第一静电释放单元ESD10。例如，多个第二引线段1031的远离测试电路CT的一端与多个第一静电释放单元ESD10的控制端ESD11分别对应连接。
例如，第一静电释放单元ESD10实现为串联的多个晶体管。每个晶体管的源漏电极(例如第一端ESD1和第二端ESD2)的其中之一与控制端(例如控制端ESD11)短接，形成二极管结构，以具有单向导通特性。当与第一静电释放单元ESD10连接的第二引线段1031传输的信号为高电平信号时，第一静电释放单元ESD10导通，从而导出第二引线段1031上的静电。也就是说，第一静电释放单元ESD10配置为导出，数据测试信号线(例如，第一数据测试线DR、第二数据测试线DG和第三数据测试线DB)提供的测试信号在向数据线D10传输路径上的静电。
例如，如图2所示，测试电路CT和静电释放电路ESD位于显示区10的第一侧。显示区10的第二侧12和第三侧13相对设置且与第一侧11临接，显示区10的第四侧14与第一侧11相对设置。结合图7A所示，多条数据测试线包括第一数据测试线DR、第二数据测试线DG和第三数据测试线DB。第一数据测试线DR和第二数据测试线DG的(例如至少部分)围绕显示区10的第二侧12和第一侧11走线，第二数据测试线DG位于第一数据测试线DR靠近显示区10的一侧。第三数据测试线DB和控制信号线CW的(例如至少部分)围绕显示区10的第三侧13和第一侧11走线，控制信号线CW位于第三数据测试线DB靠近显示区10的一侧。例如，在测试电路CT的远离显示区10的一侧， 第二数据测试线DG位于第一数据测试线DR和第三数据测试线DB之间，第一数据测试线DR位于远离测试电路CT的一侧。例如，第一数据测试线DR、第二数据测试线DG和第三数据测试线DB在第二方向Y上并列间隔设置。
例如，如图7A所示，第一导电层201包括第一连接走线LL1，第一连接走线LL1沿第二方向Y延伸。半导体层304包括多个第一电阻R1。控制信号线CW的第一端CW1位于显示区10的第一侧11且靠近测试电路CT，例如，控制信号线CW延伸至测试电路CT的靠近显示区10的第三侧13的一侧。第一连接走线LL1的一端与控制信号线CW的第一端CW1连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)，第一连接走线LL1的另一端与第一控制线CT11的靠近显示区10的第三侧13的一端连接。例如，第一控制线CT11和第一连接走线LL1同层设置且一体形成，以简化制备工艺。例如，第一数据测试线DR的第一端DR1和第二数据测试线DG的第一端DG1位于测试电路CT的远离显示区10的一侧，即位于靠近显示区10的第三侧13的虚拟测试单元DCT1的远离显示区10的一侧。例如，多个第一电阻R1的其中之一(例如第一电阻的至少其中之一)连接(例如，通过贯穿第一周边绝缘层2242、第二周边绝缘层2243和周边层间绝缘层2244的过孔)第一数据测试线DR的第一端DR1和控制信号线CW，多个第一电阻R1的其中另一(例如第一电阻的其中至少另一)连接第二数据测试线DG和第一端DG1和控制信号线CW。第一电阻R1可以防止第一数据测试线DR的第一端DR1和第二数据测试线DG的第一端DG1产生静电。
例如，例如，第一连接走线LL1也可以不与第二方向Y平行，例如与第二方向Y相交一定的角度。例如，该交叉角度小于等于20°。
图8为本公开至少一实施例提供的一种显示基板的周边区在显示区的第一侧的再一部分结构示意图。
例如，在一些实施例中，如图7A和图8所示，第一数据测试线DR、第二数据测试线DG、第三数据测试线DB、控制信号线CW以及第一控制线CT11中的至少其中之一与静电释放电路ESD连接。例如，第一数据测试线DR、第二数据测试线DG、第三数据测试线DB、控制信号线CW以及第一控制线CT11分别与静电释放电路ESD中的不同静电释放单元电连接，以去除第一数据测试线DR、第二数据测试线DG、第三数据测试线DB、控制信号线CW以及第一控制线CT11在传输信号过程中产生的静电。
例如，在一些实施例中，如图7A所示，静电释放电路ESD还包括第二静电释放单元ESD20。第二静电释放单元ESD20位于多个第一静电释放单元ESD10的靠近显示区10的第三侧13的一侧(例如多个第一静电释放单元ESD10的右侧)。例如，第一导电层201包括第二连接走线LL2，半导体层304包括第二电阻R2。例如，第二连接走线LL2与第一电源线VGH交叠。例如，第二连接走线LL2大致呈“L”形走线。第二连接走线LL2的一端与第二静电释放单元ESD20的控制端ESD21连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)，第二连接走线LL2的另一端与控制信号线CW的第一端CW1连接，以去除所述控制信号线CW的第一端CW1产生的静电。第二 电阻R2位于第二静电释放单元ESD20的远离第一静电释放单元ESD10的一侧。第二电阻R2连接(例如，通过贯穿第一周边绝缘层2242、第二周边绝缘层2243和周边层间绝缘层2244的过孔)第二静电释放单元ESD20的控制端ESD21和第一电源线VGH，以防止第二静电释放单元ESD20的控制端ESD21产生静电。
例如，在一些实施例中，如图7A所示，第一导电层201还包括第三连接走线LL3。例如，第三连接走线LL3与第一电源线VGH和控制信号线CW交叠，第三连接走线LL3弯折走线。静电释放电路ESD还包括第三静电释放单元ESD30。第三静电释放单元ESD30位于第二静电释放单元ESD20的靠近显示区10的第三侧13的一侧(例如图中右侧)。例如，第三连接走线LL3的一端与第三数据测试线DB连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)，第三连接走线LL3的另一端与第三静电释放单元ESD30的控制端ESD31连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)，以去除第三数据测试线DB的静电。
例如，在一些实施例中，如图8所示，第一导电层201还包括第四连接走线LL4。例如，第四连接走线LL4沿第二方向Y延伸。例如，第四连接走线LL4与第一连接走线LL1对称设置，以增加走线的均匀性。例如，第四连接走线LL4的第一端LL41与第一控制线CT11的靠近显示区10的第二侧12的一端连接。例如，第四连接走线LL4和第一控制线CT11同层设置且一体形成，以简化制备工艺。例如，半导体层304包括第三电阻R3。第二导电层203包括第二转接电极ZL2，第二转接电极ZL2沿第一方向X延伸。例如，第四连接走线LL4的第二端LL42与第二转接电极ZL2的第一端ZL21连接(例如通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔连接)。例如，第三数据测试线DB的第一端DB1位于测试电路CT的远离显示区10的一侧。例如，第三数据测试线DB在显示区10的第一侧11向靠近第二侧12的方向延伸。例如，第三电阻R3连接(例如，通过贯穿第一周边绝缘层2242、第二周边绝缘层2243和周边层间绝缘层2244的过孔)第二转接电极ZL2的第二端ZL22和第三数据测试线线DB的第一端DB1。
例如，例如，第四连接走线LL4也可以不与第二方向Y平行，例如与第二方向Y相交一定的角度。例如，该交叉角度小于等于20°。第二转接电极ZL2也可以不与第一方向X平行，例如与第一方向X相交一定的角度。例如，该交叉角度小于等于20°。
例如，在一些实施例中，如图8所示，第一导电层201还包括第五连接走线LL5。例如，静电释放电路ESD还包括第四静电释放单元ESD40，第四静电释放单元ESD40位于多个第一静电释放单元ESD10的靠近显示区10的第二侧12的一侧(例如，左侧)。例如，第五连接走线LL5的大致呈“L”形走线。例如，第五连接走线LL5的一端与所述第四连接走线LL4的第二端LL42连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)。第五连接走线LL5的另一端与第四静电释放单元ESD40的控制端ESD41连接，以去除第一控制线CT11产生的静电。
例如，在一些实施例中，如图8所示，第一导电层201还包括第六连接走线LL6和第七连接走线LL7。第六连接走线LL6和第七连接走线LL7弯折走线。例如，静电释放 电路ESD还包括第五静电释放单元ESD50和第六静电释放单元ESD60。第六静电释放单元ESD60位于第四静电释放单元ESD40的靠近显示区10的第二侧12的一侧(例如左侧)。例如，第五静电释放单元ESD50位于第四静电释放单元ESD40和第六静电释放单元ESD60之间。例如，第六连接走线LL6的一端与第一数据测试线DR连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)，第六连接走线LL6的另一端与第五静电释放单元ESD50的控制端ESD51连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)，以去除第一数据测试线DR产生的静电。例如，第七连接走线LL7的一端与第二数据测试线DG连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)，第七连接走线LL7的另一端与第六静电释放单元ESD60的控制端ESD61连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)，以去除第二数据测试线DG产生的静电。
图9为本公开至少一实施例提供的一种显示基板的周边区在显示区的第四侧的部分结构示意图。
例如，在一些实施例中，如图2和图9所示，显示基板1还包括位于显示区10的第四侧14的邦定区21和信号接入单元22。例如，在第二方向Y上，信号接入单元22位于邦定区21和显示区10之间。邦定区21包括多个沿第一方向X排列的接触垫。多个接触垫包括靠近显示区10的第二侧12(例如位于邦定区21的左侧)的第一接触垫211和第二接触垫212，以及靠近显示区10的第三侧13的第三接触垫213和第四接触垫214(例如位于邦定区21的右侧)。例如，第一数据测试线DR的第二端DR2延伸至显示区10的第四侧14并与第二接触垫212连接。第二数据测试线DG的第二端DG2延伸至显示区10的第四侧14并与第一接触垫211连接。例如，控制信号线CW的第二端CW2延伸至显示区10的第四侧14并与第三接触垫213连接。第三数据测试线DB的第二端DB2延伸至显示区10的第四侧14并与第四接触垫214连接。多个接触垫配置为在测试阶段与外部测试电路进行电连接(例如邦定、探针接触等)，以通过测试电路CT向子像素P10施加测试信号，从而测试显示基板1的子像素P10显示黑白画面、单色以及灰阶画面等方面的性能。
例如，信号接入单元22配置为与信号输入元件邦定，例如，信号输入元件包括集成电路(IC)，又例如，信号输入元件包括数据驱动电路IC。信号输入元件提供显示基板1在显示阶段的显示信号，以使子像素P10显示画面。
例如，在一些实施例中，第一数据测试线DR、第二数据测试线DG、第三数据测试线DB以及控制信号线CW的部分位于第二导电层203。例如，第一数据测试线DR、第二数据测试线DG、第三数据测试线DB以及控制信号线CW的其它部分位于第一导电层201。
例如，在一些实施例中，如图2和图9所示，多条电源线还包括第三电源线VSS和第四电源线VDD。第三电源线VSS配置为向多个子像素P10提供第三电源信号。第四电源线VDD配置为向多个子像素P10提供第四电源信号。
需要说明的是，第四电源线VDD为向多个子像素P10提供高电压的电源线，第三电源线VSS为向多个子像素P10提供低电压(低于前述高电压)的电源线。在本公开实施例中，第四电源线VDD提供恒定的第四电源电压，第四电源电压为正电压；第三电源线VSS提供恒定的第三电源电压，第三电源电压可以为负电压等。例如，在一些示例中，第三电源电压可以为接地电压。
例如，如图2和图9所示，例如，邦定区21的多个接触垫还包括第五接触垫215、第六接触垫216、第七接触垫217以及第八接触垫218。例如，第七接触垫217位于第二接触垫212的靠近显示区10的第二侧12的一侧(例如图9中左侧)，第八接触垫218位于第四接触垫214的靠近显示区10的第三侧13(例如图9中右侧)的一侧。例如，第五接触垫215位于第七接触垫217和第二接触垫212之间，第六接触垫216位于第四接触垫214和第八接触垫218之间。例如，第三电源线VSS的两端分别与第七接触垫217和第八接触垫218连接且围绕显示区10(例如第二侧12、第三侧13和第四侧14)走线。第三电源线VSS位于第一数据测试线DR和第三数据测试线DB的远离显示区10的一侧。例如，第四电源线VDD的两端分别与第五接触垫215和第六接触垫216连接，且在信号接入单元22和显示区10之间走线并延伸至显示区10。例如，第四电源线VDD在衬底基板100的板面S上的正投影，与第一数据测试线DR、第二数据测试线DG、第三数据测试线DB以及控制信号线CW在衬底基板100的板面S上的正投影交叠，以减少布线空间。
例如，在一些实施例中，如图9所示，在第四电源线VDD与第一数据测试线DR、第二数据测试线DG、第三数据测试线DB以及控制信号线CW的衬底基板100的板面S上的正投影交叠的区域，第四电源线VDD位于第二导电层203，第一数据测试线DR、第二数据测试线DG、第三数据测试线DB以及控制信号线CW与第二导电层203间隔绝缘。例如，在该区域，第一数据测试线DR、第二数据测试线DG、第三数据测试线DB以及控制信号线CW位于第一导电层201。
例如，在一些实施例中，如图9所示，第一数据测试线DR包括与其第一端DR1连接的第一部分DR3、与其第二端DR2连接的第二部分DR4以及第八连接走线LL8。例如，第一数据测试线DR的第一部分DR3和第二部分DR4位于第二导电层203，第八连接走线LL8位于第一导电层201，第八连接走线LL8的两端分别与第一数据测试线DR的第一部分DR3和第二部分DR4连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)。例如，第二数据测试线DG包括与其第一端DG1连接的第一部分DG3、与其第二端DG2连接的第二部分DG4以及第九连接走线LL9。例如，第二数据测试线DG的第一部分DG3和第二部分DG4位于第二导电层203，第九连接走线LL9位于第一导电层LL9，第九连接走线LL9的两端分别与第二数据测试线DG的第一部分DG3和第二部分DG4连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)。例如，第八连接走线LL8和第九连接走线LL9弯折走线。例如，第八连接走线LL8和第九连接走线LL9在衬底基板100的板面S上的正投影与第四电源线VDD在 衬底基板100的板面S上的正投影交叠(例如图9中信号接入单元22的左侧)，以减少布线空间。
例如，在一些实施例中，如图9所示，第三数据测试线DB包括与其第一端DB1连接的第一部分DB3、与其第二端DB2连接的第二部分DB4以及第十连接走线LL10。例如，第三数据测试线DB的第一部分DB3和第二部分DB4位于第二导电层203，第十连接走线LL10位于第一导电层201，第十连接走线LL10的两端分别与第三数据测试线DB的第一部分DB3和第二部分DB4连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)。例如，控制信号线CW包括与其第一端CW1连接的第一部分CW3、与其第二端CW2连接的第二部分CW4以及第十一连接走线LL11。例如，控制信号线CW的第一部分CW3和第二部分CW4位于第二导电层203，第十一连接走线LL11位于第一导电层201。第十一连接走线LL11的两端分别与控制信号线CW的第一部分CW3和第二部分CW4连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)。例如，第十连接走线LL10和第十一连接走线LL11弯折走线。例如，第十连接走线LL10和第十一连接走线LL11在衬底基板100的板面S上的正投影与第四电源线VDD在衬底基板100的板面S上的正投影交叠(例如图9中信号接入单元22的右侧)，以减少布线空间。
需要说明的是，第一电源线VGH和第二电源线VGL的也延伸至显示区10的第四侧14与邦定区21的其它接触垫连接。第一电源线VGH和第二电源线VGL在显示区10的第四侧14也与第四电源线VDD交叠，在交叠区域第一电源线VGH和第二电源线VGL采用换层走线的方式。在显示区10的第四侧14，第一电源线VGH和第二电源线VGL的走线方式与第一数据测试线DR、第二数据测试线DG、第三数据测试线DB以及控制信号线CW的走线方式相似，这里不再详细赘述。
例如，在一些实施例中，如图9所示，信号接入单元22包括多个信号接入垫221。第一导电层201还包括第十二连接走线LL12。第十二连接走线LL12的一端与多个信号接入垫221的其中至少之一连接，第十二连接走线LL12的另一端与控制信号线CW(例如第二部分CW4)连接(例如，通过贯穿第二周边绝缘层2243和周边层间绝缘层2244的过孔)。第十二连接走线LL12可以在显示阶段通过控制信号线CW向测试电路CT提供控制信号以将测试电路CT关断，以使子像素P10基于信号输入单元提供的显示信号显示画面。
图10为本公开至少一实施例提供的一种显示装置的示意图。
本公开至少一实施例还提供一种显示装置。图10为本公开一实施例提供的一种显示装置的示意图。如图10所示，该显示装置2包括本公开任一实施例提供的显示基板1以及信号输入元件。例如，显示基板1采用图2中所示的显示基板1。例如信号输入元件包括数据驱动电路IC。例如，数据驱动电路IC可以与显示基板1的信号输入单元22邦定。数据驱动电路IC提供显示基板1在显示阶段的显示信号，以使子像素P10显示画面。
需要说明的是，该显示装置2可以为可穿戴设备。例如，该显示装置2还可以为OLED 面板、OLED电视、QLED面板、QLED电视、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置2还可以包括其他部件，例如数据驱动电路、时序控制器等，本公开的实施例对此不作限定。
需要说明的是，为表示清楚、简洁，本公开的实施例并没有给出该显示装置的全部组成单元。为实现该显示装置的基板功能，本领域技术人员可以根据具体需要提供、设置其他未示出的结构，本公开的实施例对此不作限制。
关于上述实施例提供的显示装置2的技术效果可以参考本公开的实施例中提供的显示基板1的技术效果，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，包括显示区以及至少位于所述显示区一侧的周边区；
    多个子像素，位于所述显示区且阵列排布；
    多条数据线，位于所述显示区且配置为向所述多个子像素提供数据信号；
    控制信号线，位于所述周边区且位于所述显示区的至少一侧；
    多条数据测试线，位于所述周边区且位于所述显示区的至少一侧；
    测试电路，位于所述周边区并与所述多条数据线、所述控制信号线和所述多条数据测试线电连接，被配置为在所述控制信号线的控制下通过所述多条数据测试线将测试信号传递给所述多条数据线，其中，所述测试电路包括多个测试单元，多个所述测试单元中至少一个测试单元的每个包括第一控制线以及多个控制开关，所述多个控制开关包括控制端，所述第一控制线和所述控制信号线以及所述多个控制开关的控制端连接；以及
    辅助电极线，位于所述周边区并与所述第一控制线彼此并联连接，且所述多个控制开关中至少一个控制开关的部分在所述衬底基板的板面上的正投影位于所述第一控制线和所述辅助电极线在所述衬底基板的板面上的正投影之间。
  2. 根据权利要求1所述的显示基板，其中，所述第一控制线和所述辅助电极线相对于所述衬底基板位于不同层，以及
    所述第一控制线和所述辅助电极线分别位于彼此间隔绝缘的第一导电层和第二导电层。
  3. 根据权利要求2所述的显示基板，其中，所述辅助电极线位于所述测试电路的远离所述显示区的一侧或靠近所述显示区的一侧。
  4. 根据权利要求3所述的显示基板，还包括设置在所述测试电路与所述显示区之间的静电释放电路，所述静电释放电路与所述多条数据线电连接，
    所述辅助电极线位于所述测试电路与所述静电释放电路之间。
  5. 根据权利要求4所述的显示基板，还包括多条连接线，所述多条连接线分别设置于所述多个控制开关之间，
    所述第一控制线与所述多个控制开关的有源层交叠，以及所述第一控制线与有源层的交叠部分形成所述多个控制开关的控制端，
    所述多条连接线的第一端与所述第一控制线连接，所述多个条连接线的第二端与所述辅助电极线连接。
  6. 根据权利要求4或5所述的显示基板，其中，所述多条数据测试线在所述测试电路的远离所述显示区的一侧沿第一方向延伸且沿第二方向间隔设置，所述第一方向和所述第二方向交叉，
    所述多个控制开关的每个还包括第一端和第二端，所述多个控制开关的第一端与所述多条数据测试线分别对应连接，且配置为接收所述多条数据测试线提供的测试信号，
    所述多个控制开关的第二端与所述多条数据线分别对应电连接。
  7. 根据权利要求6所述的显示基板，还包括多个第一引线段和多条数据引线，所述多个第一引线段和所述多条数据引线沿所述第二方向延伸，
    所述多个第一引线段分别对应连接所述多条数据测试线和所述多个控制开关的第一端，
    所述多条数据引线分别对应连接所述多个控制开关的第二端和所述多条数据线。
  8. 根据权利要求7所述的显示基板，其中，所述多条数据引线包括第二引线段，
    多个所述第二引线段分别对应连接所述多个控制开关的第二端和所述静电释放电路，
    所述多个第一引线段和所述多个第二引线段位于第三导电层，所述第三导电层位于所述第一导电层和所述第二导电层之间且彼此间隔绝缘，
    所述多个第二引线段在所述衬底基板的板面上的正投影和所述辅助电极在所述衬底基板的板面上的正投影相互交叠。
  9. 根据权利要求8所述的显示基板，其中，所述多条数据引线还包括第三引线段，所述第三引线段位于所述周边区且位于所述显示区和所述静电释放电路之间，
    多条所述第三引线段的一端与所述静电释放电路的控制端电连接，所述多条第三引线段的另一端与所述多条数据线分别对应连接，
    所述第三引线段位于所述第三导电层。
  10. 根据权利要求8或9所述的显示基板，其中，所述多个子像素中的至少一个包括像素驱动电路以及发光元件，
    其中，所述像素驱动电路包括半导体层，第一显示区金属层、第二显示区金属层以及第三显示区金属层，发光元件位于所述像素驱动电路远离所述衬底基板的一侧且与所述像素驱动电路的第三显示区金属层连接，
    所述第一绝缘层位于所述衬底基板上，所述半导体层位于所述第一显示区金属层的靠近所述衬底基板的一侧，所述第二显示区金属层位于所述第一显示区金属层的远离所述衬底基板的一侧，所述第三显示区金属层位于所述第二显示区金属层远离所述衬底基板的一侧，所述第一导电层与所述第一显示区金属层同层设置，
    所述第三导电层与所述第二显示区金属层同层设置，
    所述第二导电层与所述第三显示区金属层同层设置，
    所述多个控制开关的有源层与所述半导体层同层设置，
    所述多条连接线位于所述第一导电层，以及所述多条连接线的第二端与所述辅助电极线连接。
  11. 根据权利要求10所述的显示基板，其中，所述像素驱动电路还包括第一晶体 管和存储电容，所述第一晶体管包括栅极、源电极、漏电极以及有源层，所述存储电容包括第一极板和第二极板，
    所述有源层位于所述半导体层，所述栅极和所述第一极板位于所述第一显示区金属层，所述第二极板位于所述第二显示区金属层，所述源电极和所述漏电极位于所述第三显示区金属层。
  12. 根据权利要求10或11所述的显示基板，其中，所述测试电路还包括至少一个虚拟测试单元，所述至少一个虚拟测试单元位于所述测试电路的远离所述多个测试单元的一侧，所述第二导电层包括多个第一转接电极，
    所述至少一个虚拟测试单元的每个包括多个虚拟控制开关，所述多个虚拟控制开关的第一端与所述多个数据测试线分别对应连接，所述多个虚拟控制开关的控制端与所述第一控制线连接，所述多个转接电极分别连接所述多个虚拟控制开关的第一端和第二端。
  13. 根据权利要求10-12任一所述的显示基板，还包括多条电源线，所述多条电源线围绕所述显示区的至少一侧走线，
    其中，所述多条电源线包括第一电源线和第二电源线，所述第一电源线配置为提供第一电源信号，所述第二电源线配置为提供第二电源线，
    所述第一电源线和所述第二电源线的至少部分位于所述第二导电层，
    所述第一电源线在所述静电释放电路的远离所述显示区的一侧走线，所述第二电源线在所述静电释放电路的靠近所述显示区的一侧走线，所述第一电源线和所述第二电源线分别与所述静电释放电路的第一端和第二端连接，
    所述静电释放电路包括多个第一静电释放单元，
    所述多个第二引线段的远离所述测试电路的一端与所述多个第一静电释放单元的控制端分别对应连接。
  14. 根据权利要求10-13任一所述的显示基板，其中，所述测试电路和所述静电释放电路位于所述显示区的第一侧，所述显示区的第二侧和第三侧相对设置且与所述第一侧临接，
    所述多条数据测试线包括第一数据测试线、第二数据测试线和第三数据测试线，所述第一数据测试线和所述第二数据测试线的至少部分围绕所述显示区的第二侧和第一侧走线，所述第二数据测试线位于所述第一数据测试线靠近所述显示区的一侧，
    所述第三数据测试线和所述控制信号线的至少部分围绕所述显示区的第三侧和第一侧走线，所述控制信号线位于所述第三数据测试线靠近所述显示区的一侧，
    在所述测试电路的远离所述显示区的一侧，所述第二数据测试线位于所述第一数据测试线和所述第三数据测试线之间，所述第一数据测试线位于远离所述测试电路的一侧，所述第一导电层包括第一连接走线，所述第一连接走线沿所述第二方向延伸，所述半导体层包括多个第一电阻，
    所述控制信号线的第一端位于所述显示区的第一侧且靠近所述测试电路，所述第 一连接走线的一端与所述控制信号线的第一端连接，所述第一连接走线的另一端与所述第一控制线的靠近所述显示区的第三侧的一端连接，
    所述第一数据测试线和所述第二数据测试线的第一端位于所述测试电路的远离所述显示区的一侧，
    所述多个第一电阻的其中至少之一连接所述第一数据测试线的第一端和所述控制信号线，所述多个第一电阻的其中至少另一连接所述第二数据测试线和第一端和所述控制信号线。
  15. 根据权利要求14所述的显示基板，其中，所述第一数据测试线、所述第二数据测试线、所述第三数据测试线、所述控制信号线以及所述第一控制线中的至少其中之一与所述静电释放电路连接。
  16. 根据权利要求15所述的显示基板，其中，所述静电释放电路还包括第二静电释放单元，所述第二静电释放单元位于所述多个第一静电释放单元的至少一侧，且位于靠近所述显示区的第三侧的一侧，
    所述第一导电层包括第二连接走线以及第三连接走线，所述半导体层包括第二电阻，
    所述第二连接走线的一端与所述第二静电释放单元的控制端连接，所述第二连接走线的另一端与所述控制信号线的第一端连接，
    所述第二电阻连接所述第二静电释放单元的控制端和所述第一电源线，
    所述静电释放电路还包括第三静电释放单元，所述第三静电释放单元位于所述第二静电释放单元的靠近所述显示区的第三侧的一侧，
    所述第三连接走线的一端与所述第三数据测试线连接，所述第三连接走线的另一端与所述第三静电释放单元的控制端连接。
  17. 根据权利要求14-16任一所述的显示基板，还包括位于所述显示区的与所述第一侧相对的第四侧的邦定区和信号接入单元，所述信号接入单元位于所述邦定区和所述显示区之间，所述邦定区包括多个沿所述第一方向排列的接触垫，
    所述多个接触垫包括靠近所述显示区的第二侧的第一接触垫和第二接触垫，以及靠近所述显示区的第三侧的第三接触垫和第四接触垫，
    所述第一数据测试线的第二端延伸至所述显示区的第四侧并与所述第二接触垫连接，所述第二数据测试线的第二端延伸至所述显示区的第四侧并与所述第一接触垫连接，
    所述控制信号线的第二端延伸至所述显示区的第四侧并与所述第三接触垫连接，
    所述第三数据测试线的第二端延伸至所述显示区的第四侧并与所述第四接触垫连接。
  18. 根据权利要求17所述的显示基板，其中，所述第一数据测试线、所述第二数据测试线、所述第三数据测试线以及所述控制信号线的部分位于第二导电层。
  19. 根据权利要求17或18所述的显示基板，其中，所述多条电源线还包括第三 电源线和第四电源线，
    所述第三电源线配置为向所述多个子像素提供第三电源信号，
    所述第四电源线配置为向所述多个子像素提供第四电源信号，
    所述多个接触垫还包括第五接触垫、第六接触垫、第七接触垫以及第八接触垫，
    所述第七接触垫位于所述第二接触垫的靠近所述显示区的第二侧的一侧，所述第八接触垫位于所述第四接触垫的靠近所述显示区的第三侧的一侧，
    所述第五接触垫位于所述第七接触垫和所述第二接触垫之间，所述第六接触垫位于所述第四接触垫和所述第八接触垫之间，
    所述第三电源线的两端分别与所述第七接触垫和所述第八接触垫连接且围绕所述显示区走线，所述第三电源线位于所述第一数据测试线和所述第三数据测试线的远离所述显示区的一侧，
    所述第四电源线的两端分别与所述第五接触垫和所述第六接触垫连接，且在所述信号接入单元和所述显示区之间走线并延伸至所述显示区，
    所述第四电源线在所述衬底基板的板面上的正投影，与所述第一数据测试线、所述第二数据测试线、所述第三数据测试线以及所述控制信号线在所述衬底基板的板面上的正投影交叠，
    在所述第四电源线与所述第一数据测试线、所述第二数据测试线、所述第三数据测试线以及所述控制信号线的所述衬底基板的板面上的正投影交叠的区域，所述第四电源线位于第二导电层，所述第一数据测试线、所述第二数据测试线、所述第三数据测试线以及所述控制信号线与所述第二导电层间隔绝缘。
  20. 一种显示装置，包括权利要求1-19任一所述的显示基板。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080192162A1 (en) * 2007-02-08 2008-08-14 Toshiba Matsushita Display Technology Co., Ltd. Liquid crystal display device
US20140176844A1 (en) * 2012-12-20 2014-06-26 Japan Display Inc. Display device
CN105974689A (zh) * 2016-07-22 2016-09-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法、液晶显示面板
CN110579913A (zh) * 2019-08-09 2019-12-17 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN111681552A (zh) * 2020-06-30 2020-09-18 上海中航光电子有限公司 阵列基板及显示面板
CN111739474A (zh) * 2019-03-21 2020-10-02 三星显示有限公司 显示面板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200634375A (en) 2005-03-28 2006-10-01 Elan Microelectronics Corp Power line structure for liquid crystal display panel
TWI322319B (en) 2005-12-30 2010-03-21 Au Optronics Corp Active component array substrate
CN107134474B (zh) 2017-06-12 2020-07-24 武汉华星光电半导体显示技术有限公司 薄膜晶体管及其制作方法、有机电致发光显示器
CN109345990B (zh) * 2018-12-14 2020-10-13 武汉华星光电半导体显示技术有限公司 显示面板测试电路及显示面板
CN109872632A (zh) 2019-03-20 2019-06-11 武汉华星光电技术有限公司 阵列基板
CN110176464A (zh) 2019-05-30 2019-08-27 武汉华星光电技术有限公司 阵列基板及其制作方法与显示装置
CN110993617A (zh) 2019-12-03 2020-04-10 武汉华星光电技术有限公司 阵列基板、显示面板及显示装置
CN111474790A (zh) 2020-05-14 2020-07-31 深圳市华星光电半导体显示技术有限公司 阵列基板和液晶显示面板
CN111785226B (zh) 2020-07-08 2021-09-24 Tcl华星光电技术有限公司 信号传输线结构及显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080192162A1 (en) * 2007-02-08 2008-08-14 Toshiba Matsushita Display Technology Co., Ltd. Liquid crystal display device
US20140176844A1 (en) * 2012-12-20 2014-06-26 Japan Display Inc. Display device
CN105974689A (zh) * 2016-07-22 2016-09-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法、液晶显示面板
CN111739474A (zh) * 2019-03-21 2020-10-02 三星显示有限公司 显示面板
CN110579913A (zh) * 2019-08-09 2019-12-17 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN111681552A (zh) * 2020-06-30 2020-09-18 上海中航光电子有限公司 阵列基板及显示面板

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