WO2022205364A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2022205364A1
WO2022205364A1 PCT/CN2021/085079 CN2021085079W WO2022205364A1 WO 2022205364 A1 WO2022205364 A1 WO 2022205364A1 CN 2021085079 W CN2021085079 W CN 2021085079W WO 2022205364 A1 WO2022205364 A1 WO 2022205364A1
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Prior art keywords
sub
signal line
layer
source
gate
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PCT/CN2021/085079
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English (en)
French (fr)
Inventor
李梅
刘利宾
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/773,595 priority Critical patent/US20240179985A1/en
Priority to CN202180000690.9A priority patent/CN115443538A/zh
Priority to PCT/CN2021/085079 priority patent/WO2022205364A1/zh
Publication of WO2022205364A1 publication Critical patent/WO2022205364A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • OLED Organic Light Emitting Diode
  • Organic Light Emitting Diode Organic Light Emitting Diode
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide an array substrate and a display device.
  • an array substrate having a display area and a peripheral area surrounding the display area, the array substrate further comprising:
  • a gate material layer disposed on one side of the base substrate
  • a source and drain material layer disposed on the side of the gate material layer away from the base substrate;
  • the array substrate further includes a driving signal line, the driving signal line includes a first sub-signal line and a second sub-signal line, the first sub-signal line is arranged on the gate material layer and extends from the peripheral region To the display area, the second sub-signal line is disposed on the source-drain material layer and at least in the display area, and the first sub-signal line and the second sub-signal line are electrically connected through via holes.
  • the driving signal line includes a first sub-signal line and a second sub-signal line
  • the first sub-signal line is arranged on the gate material layer and extends from the peripheral region To the display area
  • the second sub-signal line is disposed on the source-drain material layer and at least in the display area
  • the first sub-signal line and the second sub-signal line are electrically connected through via holes.
  • the source and drain material layers include:
  • a first source and drain material sub-layer disposed on the side of the gate material layer away from the base substrate;
  • a second source-drain material sub-layer disposed on the side of the second source-drain material sub-layer away from the first source-drain material sub-layer;
  • the second sub-signal line is arranged on the first source-drain material sub-layer or the second source-drain material sub-layer.
  • the driving signal line includes a gate driving signal line
  • the first sub-signal line includes a first sub-gate driving line
  • the second sub-signal line includes a second sub-signal line a sub-gate driving line
  • the first sub-gate driving line is arranged on the gate material layer and extends from the peripheral region to the display region
  • the second sub-gate driving line is arranged on the first source
  • the drain material sub-layer or the second source-drain material sub-layer is located at least in the display area, and the first sub-gate driving line and the second sub-gate driving line are electrically connected through via holes.
  • the driving signal line includes an enable signal line
  • the first sub-signal line includes a first sub-enable signal line
  • the second sub-signal line includes a second sub-signal line an enable signal line
  • the first sub-enable signal line is arranged on the gate material layer and extends from the peripheral region to the display region
  • the second sub-enable signal line is arranged on the first source and drain
  • the electrode material sub-layer or the second source-drain material sub-layer is located at least in the display area, and the first sub-enable signal line and the second sub-enable signal line are electrically connected through via holes.
  • the driving signal line includes a reset signal line
  • the first sub-signal line includes a first sub-reset signal line
  • the second sub-signal line includes a second sub-reset signal line
  • the first sub-reset signal line is arranged in the gate material layer and extends from the peripheral region to the display region
  • the second sub-reset signal line is arranged in the first source-drain material sub-layer or
  • the second source-drain material sub-layer is located at least in the display area
  • the first sub-reset signal line and the second sub-reset signal line are electrically connected through via holes.
  • the first sub-signal line and the second sub-signal line extend in the same direction, or extend in different directions.
  • the array substrate further includes a power supply line
  • the power supply line includes a first sub-power supply line and a second sub-power supply line
  • the first sub-power supply line is provided on the first sub-power supply line.
  • a source-drain material sub-layer, the second sub-power supply line is disposed on the second source-drain material sub-layer, and the first sub-power supply line and the second sub-power supply line are electrically connected through via holes.
  • both the second sub-signal line and the second sub-power supply line are located in the second source-drain material sub-layer, the second sub-signal line and the second sub-power supply line
  • the lines extend in the same direction and are aligned in the other direction.
  • the first sub-signal line extends in a first direction
  • the first sub-power supply line extends in a second direction
  • the second sub-signal line and the second sub-power supply line The lines all extend along the first direction and are aligned along the second direction, and the first direction and the second direction intersect.
  • the projections of the first sub-signal line and the second sub-signal line on the base substrate overlap.
  • the second sub-signal line is also located in the peripheral region, and the first sub-signal line and the second sub-signal line are electrically connected through via holes in the peripheral region. connect.
  • the line width of the second sub-signal line is greater than the line width of the first sub-signal line.
  • the line width of the second sub-signal line is greater than or equal to 5 ⁇ m.
  • the array substrate includes a GOA driving circuit, and the first sub-signal line is connected to an output end of the GOA driving circuit.
  • the gate material layer includes a first gate material layer and a second gate material layer that are stacked and disposed on the first gate material layer and the second gate a gate insulating layer between material layers, and the first sub-signal line is located in the first gate material layer or the second gate material layer.
  • a display device including the above-mentioned array substrate.
  • FIG. 1 is a schematic diagram of a pixel circuit structure of a 7T1C
  • FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 1;
  • FIG. 3 is a structural layout of the array substrate in this embodiment
  • FIG. 4 is a schematic structural diagram of the active layer in FIG. 3;
  • FIG. 5 is a schematic structural diagram of the first gate material layer in FIG. 3;
  • FIGS. 4 and 5 are schematic diagrams of the stacked structure of FIGS. 4 and 5;
  • FIG. 7 is a schematic structural diagram of the second gate material layer in FIG. 3;
  • FIGS. 6 and 7 are schematic diagrams of the stacked structure of FIGS. 6 and 7;
  • FIG. 9 is a schematic structural diagram of the first source-drain material sub-layer in FIG. 3;
  • Figure 10 is a schematic diagram of the stacked structure of Figures 8 and 9;
  • FIG. 11 is a schematic structural diagram of the second source-drain material sub-layer in FIG. 3;
  • Figure 12 is a schematic diagram of the stacked structure of Figures 10 and 11;
  • FIG. 13 is a schematic cross-sectional view of FIG. 3 and FIG. 12 in the direction A-A;
  • FIG. 15 is a structural layout of the GOA drive circuit shown in FIG. 14;
  • FIG. 16 is a schematic cross-sectional view taken along the direction B-B in FIG. 15 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • Embodiments of the present disclosure provide an array substrate having a display area and a peripheral area surrounding the display area, the array substrate further includes a base substrate 100 , a gate material layer 300 and a source and drain electrode that are sequentially stacked on the base substrate 100 Material layer 400 .
  • the array substrate further includes a driving signal line.
  • the driving signal line includes a first sub-signal line and a second sub-signal line.
  • the first sub-signal line is provided on the gate material layer 300 and extends from the peripheral area to the display area.
  • the second sub-signal line Provided on the source-drain material layer 400 and at least in the display area, the first sub-signal line and the second sub-signal line are electrically connected through via holes.
  • the present disclosure divides the wiring of the driving signal line into two layers, one is located in the gate material layer 300 and the other is located in the source and drain material layer 400, and the two layers are connected in parallel to reduce the load resistance on the driving signal line, thereby reducing the load resistance on the driving signal line.
  • the output power consumption of the drive circuit is reduced, while the size of the drive circuit is reduced.
  • the resistivity of the gate material layer 300 is relatively high, about 0.52 ⁇ /m
  • the resistivity of the source-drain material layer 400 is relatively low, about 0.045 ⁇ /m
  • a resistor is connected in parallel with the signal line with high resistivity
  • the lower rate signal line further reduces the overall load resistance of the signal line.
  • the gate material layer refers to the material layer of the gate metal of the driving circuit, which may include gate patterns, scan line patterns, etc.; similarly, the source-drain material layer refers to the film layer of the source-drain electrode material of the transistor in the driving circuit, which may Including source-drain electrodes or power signal line patterns, or other transfer patterns, etc.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, The seventh transistor T7 and the capacitor C.
  • the first electrode of the first transistor T1 is connected to the node N, the second electrode is connected to the initialization signal line Vinit, and the gate is connected to the reset signal line Re; the first electrode of the second transistor T2 is connected to the first electrode of the driving transistor T3, and the second electrode is connected to the first electrode of the driving transistor T3.
  • the gate is connected to the gate driving signal line Gate; the gate of the driving transistor T3 is connected to the node N; the first pole of the fourth transistor T4 is connected to the data signal line Data, and the second pole is connected to the second pole of the driving transistor T3, The gate is connected to the gate driving signal line Gate; the first pole of the fifth transistor T5 is connected to the first power supply signal line VDD, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal line EM; the sixth transistor The first pole of T6 is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal line EM; the first pole of the seventh transistor T7 is connected to the initialization signal line Vinit, and the second pole is connected to the second pole of the sixth transistor T6.
  • the pixel driving circuit may be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power line VSS.
  • the transistors T1-T7 may all be P-type transistors.
  • FIG. 2 it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 1 .
  • Gate represents the timing of the gate driving signal terminal Gate
  • Re represents the timing of the reset signal terminal Re
  • EM represents the timing of the enable signal terminal EM
  • Data represents the timing of the data signal terminal Data.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the reset signal terminal Re outputs a low level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the initialization signal terminal Vinit inputs the initialization signal to the node N and the second pole of the sixth transistor T6.
  • the gate driving signal terminal Gate outputs a low level signal
  • the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Data outputs a driving signal to write a voltage to the node N.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage stored by the capacitor C.
  • FIG. 3 is an exemplary structural layout of the array substrate in this embodiment.
  • the array substrate shown in FIG. 3 can form the pixel driving circuit shown in FIG. 1 , and FIGS. 4 to 12 are shown in sequence.
  • the schematic diagram of each film layer and the schematic diagram of stacking of the array substrate are shown.
  • the array substrate includes a base substrate 100, an active layer 200 on one side of the base substrate 100, a first gate material layer 310 on the side of the active layer 200 away from the base substrate 100, a first gate material layer 310 on the side of the active layer 200 away from the base substrate 100, The second gate material layer 320 on the side of the gate material layer 310 away from the base substrate 100 , the first source and drain material sub-layer 410 on the side of the second gate material layer 320 away from the base substrate 100 , The source-drain material sub-layer 410 is the second source-drain material sub-layer 420 on the side facing away from the base substrate 100 .
  • a gate insulating layer 201 is provided between the active layer 200 and the first gate material layer 310, and between the first gate material layer 310 and the second gate material layer 320.
  • the second gate material layer 320 and the first gate material layer 320 A first interlayer dielectric layer 301 is disposed between the source and drain material sublayers 410 , and an insulating layer 401 is disposed between the first source and drain material sublayers 410 and the second source and drain material sublayers 420 .
  • the base substrate 100 may be formed of an insulating material, for example, the base substrate 100 may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyamide layer which are arranged in sequence Imine (PI) layer, second silicon dioxide layer.
  • the original material for forming the active layer can be a semiconductor.
  • the active layer can be conductively processed by using the first conductive layer as a mask, so as to convert the semiconductor structure outside the transistor channel region into a conductive layer. conduction structure.
  • Both the first source and drain material sub-layer 410 and the second source and drain material sub-layer 420 may be formed by at least one metal layer.
  • both the first source and drain material sub-layer 410 and the second source and drain material sub-layer 420 may be any one or more metal materials such as magnesium, silver, copper, aluminum, molybdenum, etc., or any two of the above-mentioned materials. or a variety of alloy materials, which can be a single-layer structure or a stacked structure.
  • the first source and drain material sub-layer 410 and the second source and drain material sub-layer 420 can pass through the first titanium layer, The aluminum layer and the second titanium layer are sequentially stacked and formed.
  • the gate insulating layer disposed between the first gate material layer 310 and the active layer 200 and between the first gate material layer 310 and the second gate material layer 320 may be a silicon oxide layer, and the second gate material layer may be a silicon oxide layer.
  • the interlayer dielectric layer between 320 and the first source and drain material sublayer 410, and the insulating layer between the first source and drain material sublayer 410 and the second source and drain material sublayer 420 may be silicon nitride layers.
  • the gate material layer may also be a single metal material or an alloy material, and may be a single-layer or stacked-layer structure, which will not be repeated here.
  • the array substrate further includes a gate driving signal line, and the gate driving signal line can be used to provide the gate driving signal Gate in FIG. 1 to provide the gate driving signal to the driving transistor.
  • the gate driving signal line includes a first sub-gate driving line 51 and a second sub-gate driving line 52 , and the first sub-gate driving line 51 is provided on the first gate
  • the electrode material layer 310 extends from the peripheral area to the display area, and one end located in the peripheral area is connected to the driving chip or the GOA driving circuit to receive the driving signal.
  • the second sub-gate driving line 52 is disposed on the first source-drain material sub-layer 410 or the second source-drain material sub-layer 420 and at least in the display region. Since the first sub-gate driving line 51 and the second sub-gate driving line 52 are located in different layers, they are electrically connected through via holes. Connecting two layers of gate drive lines in parallel can reduce the load resistance on the gate drive signal lines, thereby reducing the output power consumption of the drive circuit.
  • the first sub-gate driving line 51 and the second sub-gate driving line 52 may extend in the same direction, or may extend in different directions.
  • the array substrate further includes a power supply line, and the power supply line can be used to provide the power supply terminal signal VDD in FIG. 1 to provide a power supply signal to the first electrode of the capacitor C.
  • the power supply line includes a first sub-power supply line 81 and a second sub-power supply line 82 , the first sub-power supply line 81 is provided on the first source-drain material sub-layer 410 , and the first sub-power supply line 81 The two sub-power lines 82 are disposed on the second source-drain material sub-layer 420. Since the first sub-power lines 81 and the second sub-power lines 82 are located in different layers, they are electrically connected through vias.
  • the first sub-power line 81 extends in the longitudinal direction
  • the second sub-power line 82 extends in the horizontal direction, and the two intersect in a grid shape, which can increase the transmission of power signals. path to minimize the IR Drop of the power cord.
  • the A-A section of the electrical connection between the first sub-power supply line 81 and the second sub-power supply line 82 can be referred to FIG. 13 .
  • the first sub-power supply line 81 and the second sub-power supply line 82 The holes are electrically connected.
  • the via hole also needs to penetrate other film layers.
  • the projection of the second sub-power supply line 82 extending laterally on the base substrate overlaps with the projection of the initialization signal line located on the second gate material layer 320 on the base substrate, which can reduce wiring costs.
  • the space occupied further improves the transmittance of the panel. Since both the power supply signal and the initialization signal are constant signals, the projection overlap has little effect on the signal stability.
  • the second sub-gate driving line 52 and the second sub-power supply line 82 are both located in the second source-drain material sub-layer 420, it should be ensured that they do not intersect, that is, they need to extend in the same direction and in another direction. Orientation arrangement. As shown in the figure, the second sub-gate driving lines 52 also extend laterally, and are spaced from the second sub-power supply lines 82 in the longitudinal direction. In other embodiments, when the second sub-power supply lines 82 extend in other directions, the second sub-gate driving lines 52 also need to maintain the same extension direction as the second sub-power supply lines 82 .
  • the extending direction of the second sub-gate driving line 52 is not limited by the second sub-power supply line 82 .
  • the first sub-gate driving line 51 extends in the first direction
  • the second sub-gate driving line 52 extends in the second direction.
  • the first sub-gate driving lines 51 extend along the first direction
  • the second sub-gate driving lines 52 cross transversely and longitudinally in a grid shape.
  • the second sub-gate driving line 52 when the second sub-gate driving line 52 is located in the first source-drain material sub-layer 410 , the second sub-gate driving line 52 and the first sub-power supply line 81 do not intersect.
  • the first sub-gate driving line 51 and the second sub-gate driving line 52 both extend laterally, and both are on the base substrate 100
  • the projections of the second sub-gate driving lines 52 are substantially overlapped, thereby preventing the second sub-gate driving line 52 from overlapping with other signal lines to increase parasitic capacitance.
  • the projections of the first sub-gate driving line 51 and the second sub-gate driving line 52 on the base substrate 100 do not completely overlap. The projection of the position not covered by the projection of the second sub-gate driving line 52 is exposed, which can reduce the influence on the gate potential of the driving transistor.
  • the array substrate further includes an enable signal line, and the enable signal line can be used to provide the enable signal EM in FIG. 1 .
  • the enable signal line includes a first sub-enable signal line 61 and a second sub-enable signal line 62 , and the first sub-enable signal line 61 is provided on the first gate
  • the material layer 310 extends from the peripheral area to the display area, and one end of the peripheral area is connected to the driving chip or the GOA driving circuit to receive the driving signal.
  • the second sub-enable signal line 62 is disposed in the first source-drain material sub-layer 410 or the second source-drain material sub-layer 420 and at least in the display region.
  • first sub-enable signal line 61 and the second sub-enable signal line 62 are located in different layers, they are electrically connected through via holes. Connecting two layers of enable signal lines in parallel can reduce the load resistance on the enable signal lines, thereby reducing the output power consumption of the driving circuit.
  • the first sub-enable signal line 61 and the second sub-enable signal line 62 may extend in the same direction, or may extend in different directions.
  • both the second sub-enable signal line 62 and the second sub-power supply line 82 are located in the second source-drain material sub-layer 420, it should be ensured that the two do not intersect, that is, they need to extend in the same direction, and along another Orientation arrangement.
  • the second sub-enable signal lines 62 also extend laterally, and are spaced from the second sub-power supply lines 82 in the longitudinal direction. In other embodiments, when the second sub-power line 82 extends in other directions, the second sub-enable signal line 62 also needs to maintain the same extension direction as the second sub-power line 82 .
  • the extending direction of the second sub-enable signal line 62 is not limited by the second sub-power supply line 82 .
  • the first sub-enable signal line 61 extends in the first direction
  • the second sub-enable signal line 62 extends in the second direction.
  • the first sub-enable signal line 61 extends along the first direction
  • the second sub-enable signal line 62 crosses horizontally and vertically in a grid shape.
  • the second sub-enable signal line 62 when the second sub-enable signal line 62 is located in the first source-drain material sub-layer 410, it should be ensured that the second sub-enable signal line 62 and the first sub-power supply line 81 do not intersect .
  • the first sub-enable signal line 61 and the second sub-enable signal line 62 both extend in the lateral direction, and their projections on the base substrate 100 overlap, so that the second sub-enable signal line 62 can be avoided.
  • the sub-enable signal line 62 overlaps with other signal lines to increase parasitic capacitance.
  • the projections of the first sub-enable signal line 61 and the second sub-enable signal line 62 on the base substrate 100 do not completely overlap, in order to avoid the second sub-enable signal line
  • the signal line 62 is too close to other conductive structures in the layer. It can be understood that, on the basis of ensuring sufficient layout space, the overlap of the two projections is an optimal design.
  • the array substrate of this embodiment includes both enable signal lines and gate drive signal lines. Therefore, the first sub-enable signal lines 61 and the first sub-gate drive lines 51 located on the same layer should not intersect, that is, extend in the same direction.
  • the first sub-enable signal line 61 and the first sub-gate driving line 51 are both located in the first gate material layer 310, both extend laterally and are arranged at intervals along the longitudinal direction.
  • the second sub-enable signal line 62 and the second sub-gate driving line 52 are also located in the same layer, they should not intersect, that is, extend in the same direction.
  • the second sub-enable signal line 62 and the second sub-gate driving line 52 are both located in the second source-drain material sub-layer 420, both extend laterally and are arranged at intervals along the longitudinal direction.
  • the array substrate further includes a reset signal line
  • the reset signal line may be used to provide the reset signal Reset in FIG. 1 . 5 , 6 , 11 and 12
  • the reset signal line includes a first sub-reset signal line 71 and a second sub-reset signal line 72
  • the first sub-reset signal line 71 is provided in the first gate material layer 310 and It extends from the peripheral area to the display area, and one end located in the peripheral area is connected to the driving chip or the GOA driving circuit to receive the driving signal.
  • the second sub-reset signal line 72 is disposed in the first source-drain material sub-layer 410 or the second source-drain material sub-layer 420 and at least in the display region.
  • first sub-reset signal line 71 and the second sub-reset signal line 72 are located in different layers, they are electrically connected through via holes. Connecting two layers of reset signal lines in parallel can reduce the load resistance on the reset signal lines, thereby reducing the output power consumption of the driving circuit.
  • the first sub-reset signal line 71 and the second sub-reset signal line 72 may extend in the same direction, or may extend in different directions.
  • both the second sub-reset signal line 72 and the second sub-power supply line 82 are located in the second source-drain material sub-layer 420, it should be ensured that they do not intersect, that is, they need to extend in the same direction and in the other direction arrangement.
  • the second sub-reset signal lines 72 also extend in the lateral direction, and are spaced apart from the second sub-power supply lines 82 in the longitudinal direction. In other embodiments, when the second sub-power line 82 extends in other directions, the second sub-reset signal line 72 also needs to maintain the same extension direction as the second sub-power line 82 .
  • the extension direction of the second sub-reset signal line 72 is not limited by the second sub-power supply line 82, for example , the first sub-reset signal line 71 extends along the first direction, and the second sub-reset signal line 72 extends along the second direction.
  • the first sub-reset signal lines 71 extend in the first direction, and the second sub-reset signal lines 72 intersect in a grid shape horizontally and vertically.
  • the second sub-reset signal line 72 when the second sub-reset signal line 72 is located in the first source-drain material sub-layer 410 , it should be ensured that the second sub-reset signal line 72 and the first sub-power supply line 81 do not intersect.
  • first sub-reset signal line 71 and the second sub-reset signal line 72 both extend in the lateral direction, and their projections on the base substrate 100 overlap, so that the second sub-reset signal line 72 and other signals can be avoided. Lines overlap to increase parasitic capacitance.
  • the array substrate of this embodiment includes enable signal lines, gate driving signal lines and reset signal lines at the same time. Therefore, the first sub-enable signal lines 61, the first sub-gate driving lines 51, The first sub-reset signal lines 71 should not intersect, ie, extend in the same direction. As shown in the figure, the first sub-enable signal line 61 , the first sub-gate driving line 51 , and the first sub-reset signal line 71 are all located in the first gate material layer 310 , and all extend laterally and are spaced apart along the longitudinal direction. arrangement.
  • the second sub-enable signal line 62 , the second sub-gate driving line 52 , and the second sub-reset signal line 72 are also located on the same layer, they should not intersect, that is, extend in the same direction.
  • the second sub-enable signal line 62 , the second sub-gate driving line 52 , and the second sub-reset signal line 72 are all located in the second source-drain material sub-layer 420 , and all extend laterally and along the Vertically spaced.
  • the array substrate may further include a planarization layer 402 .
  • the planarization layer 402 is disposed between the first source and drain material sub-layer 410 and the second source and drain material sub-layer 420 , and is located on the insulating layer 401 away from the first source and drain material.
  • the distance between the first source and drain material sub-layer 410 and the second source and drain material sub-layer 420 is increased, which helps to reduce the distance between the crisscrossed data lines and power lines signal crosstalk.
  • the flat layer is usually made of organic material, its thickness is larger than that of inorganic layers such as the interlayer dielectric layer 301 and the insulating layer 401, which can further alleviate the influence of signal crosstalk.
  • the driving signal lines are arranged in two layers, the wiring space becomes larger, and the load resistance can be further reduced by increasing the line width of the signal lines.
  • the first sub-signal line is located in the first gate material layer 310, and the second sub-driving signal line is located in the first source-drain material sub-layer 410 or the second source-drain material sub-layer 420.
  • the resistivity of the drain material sub-layer 410 or the second source-drain material sub-layer 420 is lower than that of the first gate material layer 310, and the line width of the second sub-signal line can be increased, for example, the second sub-signal line can be made
  • the line width is larger than the line width of the first sub-signal line, so as to further reduce the overall load resistance of the driving signal line.
  • the line width of the first sub-signal line is set to be about 3 ⁇ m
  • the line width of the second sub-signal line is set to be greater than or equal to 5 ⁇ m, thereby greatly reducing the load resistance of the GOA circuit.
  • the gate material layer includes a first gate material layer 310 and a second gate material layer 320, a first sub-enable signal line 61, a first sub-gate driving signal line 51 and The first sub-reset signal lines 71 are all located in the first gate material layer 310 , the first gate material layer 310 is further provided with an electrode plate 91 for capacitance (refer to FIG. 6 ), and the second gate material layer 320 is used to set the capacitance The other electrode plate 92 and other conductive connections (refer to FIG. 7 ).
  • the first sub-enable signal line 61 , the first sub-gate driving signal line 51 and the first sub-reset signal line 71 may all be disposed on the second gate material layer 320 .
  • the three signal lines may be distributed in two gate material layers. Of course, only one gate material layer may be provided, and the three signal lines are all located in the gate material layer.
  • the second sub-signal line of the present disclosure may also be located in other film layers with lower load resistance.
  • the backplane Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide, that is, two TFT devices, LTPS and Oxide are integrated in the same pixel, Oxide is a bottom gate structure, LTPS is a top gate structure
  • the backplane also Including a third gate material layer disposed between the second gate material layer 320 and the first source and drain material sub-layer 410, and other conductive layers such as a shielding layer disposed between the poly semiconductor active layer and the base substrate
  • the film layers when the second sub-signal lines are located in these conductive film layers, can also reduce the overall load resistance of the driving signal lines.
  • the third sub-signal lines may also be arranged on other conductive layers (eg, the third gate material layer, the shielding layer, etc.), and the first sub-signal lines respectively located in the three conductive layers , The second sub-signal line and the third sub-signal line are connected in parallel through the transfer hole, which can also reduce the overall load resistance of the driving signal line.
  • other conductive layers eg, the third gate material layer, the shielding layer, etc.
  • the enable signal, gate driving signal and reset signal required in the pixel driving circuit can be provided by the GOA driving circuit located in the peripheral area.
  • the GOA driving circuit can realize row scanning and can reduce the fabrication cost of the array substrate.
  • the shift register circuit may include: a first switch unit T1, a second switch unit T2, a third switch unit T3, a fourth switch unit T4, a fifth switch unit T4, and a fifth switch unit T1.
  • the control terminal of the first switch unit T1 is connected to the clock signal terminal CK, the first terminal is connected to the input signal terminal, and the second terminal is connected to the first node N1;
  • the control terminal of the third switch unit T3 is connected to the clock signal terminal CK, and the first terminal is connected to the power supply terminal VL, the second terminal is connected to the second node N2;
  • the control terminal of the second switch unit T2 is connected to the first node N1, the terminal clock signal terminal CK, the second terminal is connected to the second node N2;
  • the control terminal of the sixth switch unit T6 is connected to The second node N2, the first end is connected to the power signal end VH;
  • the control end of the seventh switch unit T7 is connected to the clock signal end CB, the first end is connected to the second end of the sixth switch unit T6, and the second end is connected to the first node N1
  • the control terminal of the eighth switch unit T8 is connected to the power supply terminal VL, and the first terminal is connected to the first node
  • FIG. 15 it is a layout of the GOA driving circuit shown in FIG. 14, in which the power signal line VH, the clock signal line CK, and the clock signal line CB are all arranged on the second source-drain material sub-layer 420, and the first capacitor One electrode plate of C1 is arranged on the first gate material layer 310, and the other electrode plate is arranged on the second grid electrode material layer 320; The plate is disposed on the second gate material layer 320 .
  • the output terminal OUT of the first gate material layer 310 is connected to the first sub-gate driving line 51 for outputting a gate driving signal to the first sub-gate driving line 51 .
  • the GOA driving circuit is located in the peripheral area, so the first sub-gate driving line 51 also extends from the peripheral area to the display area.
  • the second sub-gate driving line 52 can also extend from the peripheral area to the display area, and the projection of the second sub-gate driving line 52 on the base substrate 100 and the projection of the peripheral area of the first sub-gate driving line 51 The projections overlap, and the two are electrically connected through vias provided in the peripheral area. Referring to FIG. 15, a cross-sectional view of the direction B-B in FIG. 14 is shown.
  • the conductive connection portion 80 on the first source-drain material sub-layer 410 connects the first sub-gate driving line 51 and the second sub-gate driving line, that is, the conductive connection portion 80 and the first sub-gate driving line 51 pass through A via hole is connected, and the conductive connection portion 80 and the second sub-gate driving line 52 are connected by another via hole.
  • the via holes may also be arranged in other positions, such as the display area.
  • the number of vias can be set to one or more, which is not specifically limited in this application. When the number of via holes is multiple, they can be provided on opposite sides of the peripheral area respectively, so as to electrically connect the first sub-gate driving line 51 and the second sub-gate driving line 52, but not provided in the display area Via holes are used to reduce the production of via holes in the display area and improve the resolution.
  • FIG. 15 and FIG. 16 illustrate a layout structure between the GOA drive circuit and the pixel circuit by taking the gate drive line as an example.
  • the GOA is the Gate GOA.
  • the reset signal line can be connected to the gate driving line of the sub-pixel of the previous level, so that the gate driving signal of the sub-pixel of the previous level can be used as the reset signal of the sub-pixel of the next level, so as to avoid introducing a separate signal for the reset signal line, effectively reducing the wiring space.
  • the Gate GOA driving circuit is also connected to the first sub-reset signal line 71, and then connected to the second sub-reset signal line 72 through the via hole, so as to transmit the reset signal to each pixel unit.
  • the GOA drive circuit may also include an output terminal capable of outputting an enable signal, the output terminal is connected to the first sub-enable signal line 61 of the pixel circuit, and further connected to the second sub-enable signal line 62 through a via hole, using In order to transmit the enable signal to each pixel unit, that is, the GOA is the EM GOA.
  • the Gate GOA and the EM GOA may be an integral GOA or two independent GOAs, which are not specifically limited in this application.
  • the shift register unit provided in FIG. 13 can be applied to the display panel in cooperation with the pixel driving circuit in FIG. 1 , and the shift register unit provided in this exemplary embodiment can also be used in conjunction with other pixel driving circuits to be applied to the display panel. In a display panel, or, the pixel driving circuit provided in this exemplary embodiment can also be used in a display panel with other shift register units.
  • the present disclosure does not limit the shift register unit and the pixel driving circuit.
  • Embodiments of the present invention further provide a display device, which includes the array substrate of the above-mentioned embodiments. Since the display device includes the above-mentioned array substrate, it has the same beneficial effects, and details are not described herein again in the present invention.
  • the present invention does not specifically limit the application of display devices, which can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, in-vehicle displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or parts.
  • display devices can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, in-vehicle displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or parts.
  • the double-layer structure of the driving signal line of the present disclosure can reduce the load resistance of the GOA circuit to 0.65k ⁇ .
  • the GOA circuit load of the present disclosure is reduced to 49% of the single-layer structure, which greatly reduces the The output power consumption of the GOA can also reduce the size of the output tube of the GOA circuit.

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Abstract

一种阵列基板和显示装置，阵列基板具有显示区和围绕所述显示区的周边区，阵列基板还包括依次层叠设置于衬底基板(100)上的栅极材料层(300)和源漏极材料层(400)，阵列基板还包括驱动信号线，驱动信号线包括第一子信号线和第二子信号线，第一子信号线设于栅极材料层(300)且由周边区延伸至显示区，第二子信号线设于源漏极材料层(400)且至少位于显示区，第一子信号线和第二子信号线通过过孔电连接。

Description

阵列基板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板和显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示技术，以其轻薄、自发光、视角广、响应速度快、亮度低、功耗低等优点，被业界公认为第三代显示技术，已广泛地被应用于高性能显示领域中。
在AMOLED显示产品中，由于信号线较长，导致GOA电路输出线的负载过大。一方面，负载变大会导致显示面板整体功耗变大；另一方面，负载变大要求GOA电路带负载能力变强，则输出管尺寸需要更长，不利于窄边框的实现，因此对信号线设计提出了更高的要求。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板和显示装置。
根据本公开的一个方面，提供一种阵列基板，具有显示区和围绕所述显示区的周边区，所述阵列基板还包括：
衬底基板；
栅极材料层，设于所述衬底基板的一侧；
源漏极材料层，设于所述栅极材料层背离所述衬底基板的一侧；
所述阵列基板还包括驱动信号线，所述驱动信号线包括第一子信号线和第二子信号线，所述第一子信号线设于所述栅极材料层且由所述周边区延伸至显示区，所述第二子信号线设于所述源漏极材料层且至少位于所述显示区，所述第一子信号线和第二子信号线通过过孔电连接。
在本公开的一种示例性实施例中，所述源漏极材料层包括：
第一源漏极材料子层，设于所述栅极材料层背离所述衬底基板的一侧；
第二源漏极材料子层，设于所述第二源漏极材料子层背离所述第一源漏极材料子层的一侧；
其中，所述第二子信号线设于所述第一源漏极材料子层或第二源漏极材料子层。
在本公开的一种示例性实施例中，所述驱动信号线包括栅极驱动信号线，所述第一子信号线包括第一子栅极驱动线，所述第二子信号线包括第二子栅极驱动线，所述第一子栅极驱动线设于所述栅极材料层且由所述周边区延伸至显示区，所述第二子栅极驱动线设于所述第一源漏极材料子层或第二源漏极材料子层且至少位于所述显示区，所述第一子栅极驱动线和第二子栅极驱动线通过过孔电连接。
在本公开的一种示例性实施例中，所述驱动信号线包括使能信号线，所述第一子信号线包括第一子使能信号线，所述第二子信号线包括第二子使能信号线，所述第一子使能信号线设于所述栅极材料层且由所述周边区延伸至显示区，所述第二子使能信号线设于所述第一源漏极材料子层或第二源漏极材料子层且至少位于所述显示区，所述第一子使能信号线和第二子使能信号线通过过孔电连接。
在本公开的一种示例性实施例中，所述驱动信号线包括复位信号线，所述第一子信号线包括第一子复位信号线，所述第二子信号线包括第二子复位信号线，所述第一子复位信号线设于所述栅极材料层且由所述周边区延伸至显示区，所述第二子复位信号线设于所述第一源漏极材料子层或第二源漏极材料子层且至少位于所述显示区，所述第一子复位信号线和第二子复位信号线通过过孔电连接。
在本公开的一种示例性实施例中，所述第一子信号线和第二子信号线沿相同方向延伸，或沿不同方向延伸。
在本公开的一种示例性实施例中，所述阵列基板还包括电源线，所述电源线包括第一子电源线和第二子电源线，所述第一子电源线设于所述第一源漏极材料子层，所述第二子电源线设于所述第二源漏极材料子层，所述第一子电源线和第二子电源线通过过孔电连接。
在本公开的一种示例性实施例中，所述第二子信号线和第二子电源线均位于所述第二源漏极材料子层，所述第二子信号线和第二子电源线 沿同一方向延伸，且沿另一方向排列。
在本公开的一种示例性实施例中，所述第一子信号线沿第一方向延伸，所述第一子电源线沿第二方向延伸，所述第二子信号线和第二子电源线均沿所述第一方向延伸，且沿所述第二方向排列，所述第一方向和第二方向相交。
在本公开的一种示例性实施例中，所述第一子信号线和第二子信号线在所述衬底基板上的投影重叠。
在本公开的一种示例性实施例中，所述第二子信号线还位于所述周边区，所述第一子信号线和所述第二子信号线在所述周边区通过过孔电连接。
在本公开的一种示例性实施例中，所述第二子信号线的线宽大于所述第一子信号线的线宽。
在本公开的一种示例性实施例中，所述第二子信号线的线宽大于或等于5μm。
在本公开的一种示例性实施例中，所述阵列基板包括GOA驱动电路，所述第一子信号线连接所述GOA驱动电路的输出端。
在本公开的一种示例性实施例中，所述栅极材料层包括层叠设置的第一栅极材料层和第二栅极材料层以及位于所述第一栅极材料层和第二栅极材料层之间的栅极绝缘层，所述第一子信号线位于所述第一栅极材料层或第二栅极材料层。
根据本公开的另一个方面，提供一种显示装置，包括以上所述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他 的附图。
图1为一种7T1C的像素电路结构示意图；
图2为图1像素驱动电路一种驱动方法中各节点的时序图；
图3为本实施方式中的阵列基板的一种结构版图；
图4为图3中有源层的结构示意图；
图5为图3中第一栅极材料层的结构示意图；
图6为图4和图5的层叠结构示意图；
图7为图3中第二栅极材料层的结构示意图；
图8为图6和图7的层叠结构示意图；
图9为图3中第一源漏极材料子层的结构示意图；
图10为图8和图9的层叠结构示意图；
图11为图3中第二源漏极材料子层的结构示意图；
图12为图10和图11的层叠结构示意图；
图13为图3和图12中A-A向的截面示意图；
图14为一种GOA驱动电路的电路图；
图15为图14所示的GOA驱动电路的一种结构版图；
图16为图15中B-B向的截面示意图。
附图标记说明：
100、衬底基板；200、有源层；201、栅极绝缘层；300、栅极材料层；310、第一栅极材料层；320、第二栅极材料层；301、层间介质层；400、源漏极材料层；410、第一源漏极材料子层；401、绝缘层；402、平坦层；420、第二源漏极材料子层；51、第一子栅极驱动线；52、第二子栅极驱动线；61、第一子使能信号线；62、第二子使能信号线；71、第一子复位信号线；72、第二子复位信号线；80、连接部；81、第一子电源线；82、第二子电源线；
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思 全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开实施方式提供了一种阵列基板，具有显示区和围绕显示区的周边区，阵列基板还包括衬底基板100和依次层叠设置在衬底基板100上的栅极材料层300和源漏极材料层400。阵列基板还包括驱动信号线，驱动信号线包括第一子信号线和第二子信号线，第一子信号线设于栅极材料层300且由周边区延伸至显示区，第二子信号线设于源漏极材料层400且至少位于显示区，第一子信号线和第二子信号线通过过孔电连接。
本公开将驱动信号线走线分为两层，一层位于栅极材料层300，另一侧位于源漏极材料层400，将两层进行并联，可以降低驱动信号线上的负载电阻，从而降低驱动电路的输出功耗，同时减小驱动电路的尺寸。另一方面，栅极材料层300的电阻率较高，约为0.52Ω/m，源漏极材料层400电阻率较低，约0.045Ω/m，在电阻率较高信号线上并联一电阻率较低的信号线，进一步降低了信号线的整体负载电阻。
其中，栅极材料层指驱动电路栅极金属的材料层，其可以包括栅极图案、扫描线图案等；同样的，源漏级材料层指驱动电路中晶体管源漏电极材料的膜层，可以包括源漏电极或者电源信号线图形，或者其他转 接图案等。
参考图1，为一种7T1C的像素电路结构示意图，该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接节点N，第二极连接初始化信号线Vinit，栅极连接复位信号线Re；第二晶体管T2第一极连接驱动晶体管T3的第一极，第二极连接节点N；栅极连接栅极驱动信号线Gate；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号线Data，第二极连接驱动晶体管T3的第二极，栅极连接栅极驱动信号线Gate；第五晶体管T5的第一极连接第一电源信号线VDD，第二极连接驱动晶体管T3的第二极，栅极连接使能信号线EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号线EM；第七晶体管T7的第一极连接初始化信号线Vinit，第二极连接第六晶体管T6的第二极。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源线VSS之间。其中，晶体管T1-T7可以均为P型晶体管。
如图2所示，为图1像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re表示复位信号端Re的时序，EM表示使能信号端EM的时序，Data表示数据信号端Data的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re输出低电平信号，第一晶体管T1、第七晶体管T7导通，初始化信号端Vinit向节点N，第六晶体管T6的第二极输入初始化信号。在补偿阶段t2：栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Data输出驱动信号以向节点N写入电压。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压作用下发光。
如图3所示，图3为本实施方式中的阵列基板的一种示例性的结构版图，图3所示的阵列基板可以形成图1所示的像素驱动电路，图4～图12依次示出了该阵列基板的各膜层示意图和叠层示意图。参考上述附图， 阵列基板包括衬底基板100，位于衬底基板100一侧的有源层200，位于有源层200背离衬底基板100一侧的第一栅极材料层310、位于第一栅极材料层310背离衬底基板100一侧的第二栅极材料层320、位于第二栅极材料层320背离衬底基板100一侧的第一源漏极材料子层410、位于第一源漏极材料子层410背离衬底基板100一侧的第二源漏极材料子层420。有源层200和第一栅极材料层310之间、第一栅极材料层310和第二栅极材料层320之间设置有栅极绝缘层201，第二栅极材料层320和第一源漏极材料子层410之间设置有第一层间介质层301，第一源漏极材料子层410和第二源漏极材料子层420之间设置有绝缘层401。
衬底基板100可以通过绝缘材料形成，例如，衬底基板100可以包括依次设置的第一聚酰亚胺(PI)层、第一氧化硅(SiO)层、非晶硅层、第二聚酰亚胺(PI)层、第二氧化硅层。形成有源层的原始材料可以为半导体，该阵列基板在制作过程中，可以通过第一导电层为掩膜版对有源层进行导体化处理，从而将晶体管沟道区以外的半导体结构转化为导通结构。
第一源漏极材料子层410和第二源漏极材料子层420均可以通过至少一层金属层形成。例如，第一源漏极材料子层410和第二源漏极材料子层420均可以是镁、银、铜、铝、钼等任意一种或者多种金属材料，也可以是上述任意两种或多种的合金材料，其可以是单层结构，也可以是叠层结构，例如，第一源漏极材料子层410和第二源漏极材料子层420均可以通过第一钛层、铝层、第二钛层依次层叠形成。第一栅极材料层310和有源层200之间、第一栅极材料层310和第二栅极材料层320之间设置的栅极绝缘层可以为氧化硅层，第二栅极材料层320与第一源漏极材料子层410之间的层间介质层、第一源漏极材料子层410和第二源漏极材料子层420之间的绝缘层可以为氮化硅层。同理，栅极材料层也可以为单金属材料或合金材料，可以为单层或叠层结构，此处不再赘述。
在一种实施例中，阵列基板还包括栅极驱动信号线，该栅极驱动信号线可以用于提供图1中的栅极驱动信号Gate，以向驱动晶体管提供栅极驱动信号。参考图5、图6、图11和图12，栅极驱动信号线包括第一子栅极驱动线51和第二子栅极驱动线52，第一子栅极驱动线51设于第 一栅极材料层310且由周边区延伸至显示区，位于周边区的一端与驱动芯片或GOA驱动电路连接，以接收驱动信号。第二子栅极驱动线52设于第一源漏极材料子层410或第二源漏极材料子层420且至少位于显示区。由于第一子栅极驱动线51和第二子栅极驱动线52位于不同层，因此二者通过过孔电连接。将两层栅极驱动线进行并联，可以降低栅极驱动信号线上的负载电阻，从而降低驱动电路的输出功耗。第一子栅极驱动线51和第二子栅极驱动线52可以沿相同方向延伸，也可以沿不同方向延伸。
本实施方式中，阵列基板还包括电源线，该电源线可以用于提供图1中的电源端信号VDD，以向电容C的第一电极提供电源信号。在一种实施例中，参考图9-图12，电源线包括第一子电源线81和第二子电源线82，第一子电源线81设于第一源漏极材料子层410，第二子电源线82设于第二源漏极材料子层420，由于第一子电源线81和第二子电源线82位于不同层，因此二者通过过孔电连接。将电源线设置在两个源漏极材料层内且并联，可以降低电源线的IR Drop。如图3和图12所示，本实施例中，第一子电源线81沿纵向延伸，第二子电源线82沿横向延伸，二者横纵相交呈网格状，能够增加电源信号的传输路径，最大程度上降低电源线的IR Drop。图3和图12中第一子电源线81和第二子电源线82电连接的A-A截面可参考图13，第一子电源线81和第二子电源线82可通过贯穿绝缘层401的过孔电连接，当第一源漏极材料子层410和第二源漏极材料子层420之间还包含其他膜层，例如平坦层402，该过孔也需贯穿其他膜层。另外，本实施例中，横向延伸的第二子电源线82在衬底基板上投影与位于第二栅极材料层320上的初始化信号线在衬底基板上的投影重叠，这样能够减少布线所占据的空间，进一步提升面板透过率。由于电源信号和初始化信号均是恒定信号，投影重叠对信号稳定性相互影响不大。
当第二子栅极驱动线52和第二子电源线82均位于第二源漏极材料子层420时，应当保证二者不会相交，即需要二者沿同一方向延伸，且沿另一方向排列。如图所示，第二子栅极驱动线52也沿横向延伸，且与第二子电源线82在纵向上间隔排列。在其他实施方式中，当第二子电源 线82沿其他方向延伸时，第二子栅极驱动线52也需要与第二子电源线82保持相同的延伸方向。
在另外一些实施方式中，当第二源漏极材料子层420不设置第二子电源线82时，第二子栅极驱动线52的延伸方向则不受第二子电源线82的限制，例如，第一子栅极驱动线51沿第一方向延伸，第二子栅极驱动线52沿第二方向延伸。或者，第一子栅极驱动线51沿第一方向延伸，第二子栅极驱动线52横纵交叉呈网格状。再或者，在其他实施方式中，当第二子栅极驱动线52位于第一源漏极材料子层410时，第二子栅极驱动线52和第一子电源线81不相交。
进一步地，如图5、图6、图11和图12，所示，第一子栅极驱动线51和第二子栅极驱动线52均沿横向延伸，且二者在衬底基板100上的投影基本重叠，由此可以避免第二子栅极驱动线52与其他信号线重叠而增加寄生电容。另外，第一子栅极驱动线51和第二子栅极驱动线52在衬底基板100上的投影并不完全重叠，如图中M区所示，为第一子栅极驱动线51的投影未被第二子栅极驱动线52投影覆盖的位置，该位置露出可以减小对驱动晶体管栅极电位的影响。
在一种实施例中，阵列基板还包括使能信号线，该使能信号线可以用于提供图1中的使能信号EM。参考图5、图6、图11和图12，使能信号线包括第一子使能信号线61和第二子使能信号线62，第一子使能信号线61设于第一栅极材料层310且由周边区延伸至显示区，位于周边区的一端与驱动芯片或GOA驱动电路连接，以接收驱动信号。第二子使能信号线62设于第一源漏极材料子层410或第二源漏极材料子层420且至少位于显示区。由于第一子使能信号线61和第二子使能信号线62位于不同层，因此二者通过过孔电连接。将两层使能信号线进行并联，可以降低使能信号线上的负载电阻，从而降低驱动电路的输出功耗。第一子使能信号线61和第二子使能信号线62可以沿相同方向延伸，也可以沿不同方向延伸。
当第二子使能信号线62和第二子电源线82均位于第二源漏极材料子层420时，应当保证二者不会相交，即需要二者沿同一方向延伸，且沿另一方向排列。如图所示，第二子使能信号线62也沿横向延伸，且与 第二子电源线82在纵向上间隔排列。在其他实施方式中，当第二子电源线82沿其他方向延伸时，第二子使能信号线62也需要与第二子电源线82保持相同的延伸方向。
在另外一些实施方式中，当第二源漏极材料子层420不设置第二子电源线82时，第二子使能信号线62的延伸方向则不受第二子电源线82的限制，例如，第一子使能信号线61沿第一方向延伸，第二子使能信号线62沿第二方向延伸。或者，第一子使能信号线61沿第一方向延伸，第二子使能信号线62横纵交叉呈网格状。再或者，在其他实施方式中，当第二子使能信号线62位于第一源漏极材料子层410时，应当保证第二子使能信号线62和第一子电源线81不会相交。
进一步地，在一些实施例中，第一子使能信号线61和第二子使能信号线62均沿横向延伸，且二者在衬底基板100上的投影重叠，由此可以避免第二子使能信号线62与其他信号线重叠而增加寄生电容。而在如图所示的实施例中，第一子使能信号线61和第二子使能信号线62在衬底基板100上的投影并未完全重叠，这是为了避免第二子使能信号线62与该层其他导电结构距离过近。可以理解的是，在保证足够的布局空间的基础上，二者投影重叠为较优化的设计。
同时，本实施例的阵列基板中同时包含使能信号线和栅极驱动信号线，因此，位于同一层的第一子使能信号线61和第一子栅极驱动线51应当不相交，即沿同一方向延伸。例如图所示，第一子使能信号线61和第一子栅极驱动线51均位于第一栅极材料层310，都沿横向延伸且二者沿纵向间隔排列。相应的，当第二子使能信号线62和第二子栅极驱动线52也位于同一层时，二者也应当不相交，即沿同一方向延伸。例如图所示，第二子使能信号线62和第二子栅极驱动线52均位于第二源漏极材料子层420，都沿横向延伸且二者沿纵向间隔排列。
在一种实施例中，阵列基板还包括复位信号线，该复位信号线可以用于提供图1中的复位信号Reset。参考图5、图6、图11和图12，复位信号线包括第一子复位信号线71和第二子复位信号线72，第一子复位信号线71设于第一栅极材料层310且由周边区延伸至显示区，位于周边区的一端与驱动芯片或GOA驱动电路连接，以接收驱动信号。第二 子复位信号线72设于第一源漏极材料子层410或第二源漏极材料子层420且至少位于显示区。由于第一子复位信号线71和第二子复位信号线72位于不同层，因此二者通过过孔电连接。将两层复位信号线进行并联，可以降低复位信号线上的负载电阻，从而降低驱动电路的输出功耗。第一子复位信号线71和第二子复位信号线72可以沿相同方向延伸，也可以沿不同方向延伸。
当第二子复位信号线72和第二子电源线82均位于第二源漏极材料子层420时，应当保证二者不会相交，即需要二者沿同一方向延伸，且沿另一方向排列。如图所示，第二子复位信号线72也沿横向延伸，且与第二子电源线82在纵向上间隔排列。在其他实施方式中，当第二子电源线82沿其他方向延伸时，第二子复位信号线72也需要与第二子电源线82保持相同的延伸方向。
在另外一些实施方式中，当第二源漏极材料子层420不设置第二子电源线82时，第二子复位信号线72的延伸方向则不受第二子电源线82的限制，例如，第一子复位信号线71沿第一方向延伸，第二子复位信号线72沿第二方向延伸。或者，第一子复位信号线71沿第一方向延伸，第二子复位信号线72横纵交叉呈网格状。再或者，在其他实施方式中，当第二子复位信号线72位于第一源漏极材料子层410时，应当保证第二子复位信号线72和第一子电源线81不会相交。
进一步地，第一子复位信号线71和第二子复位信号线72均沿横向延伸，且二者在衬底基板100上的投影重叠，由此可以避免第二子复位信号线72与其他信号线重叠而增加寄生电容。
同时，本实施例的阵列基板中同时包含使能信号线、栅极驱动信号线和复位信号线，因此，位于同一层的第一子使能信号线61、第一子栅极驱动线51、第一子复位信号线71应当不相交，即沿同一方向延伸。如图所示，第一子使能信号线61、第一子栅极驱动线51、第一子复位信号线71均位于第一栅极材料层310，都沿横向延伸且三者沿纵向间隔排列。相应的，当第二子使能信号线62、第二子栅极驱动线52、第二子复位信号线72也位于同一层时，三者也应当不相交，即沿同一方向延伸。如图所示，第二子使能信号线62、第二子栅极驱动线52、第二子复位信 号线72均位于第二源漏极材料子层420，都沿横向延伸且二者沿纵向间隔排列。
参考图15，该阵列基板还可以包括平坦层402，平坦层402设于第一源漏极材料子层410和第二源漏极材料子层420之间，位于绝缘层401背离第一源漏极材料子层410的一侧，增大了第一源漏极材料子层410和第二源漏极材料子层420之间的间距，有助于降低纵横交错的数据线和电源线之间的信号串扰。由于平坦层通常采用有机材料制成，其厚度大于层间介质层301、绝缘层401等无机层，能够进一步缓解信号串扰的影响。
本公开中，由于将驱动信号线分两层布置，布线空间变大，可以通过增加信号线的线宽进一步降低负载电阻。具体而言，第一子信号线设于第一栅极材料层310，第二子驱动信号线位于第一源漏极材料子层410或第二源漏极材料子层420，由于第一源漏极材料子层410或第二源漏极材料子层420的电阻率相对第一栅极材料层310较低，可以增大第二子信号线的线宽，例如可以使第二子信号线的线宽大于第一子信号线的线宽，以进一步降低驱动信号线整体的负载电阻。在一种具体实施例中，第一子信号线的线宽设置为3μm左右，第二子信号线的线宽设置为大于或等于5μm，由此可以大大降低GOA电路的负载电阻。
需要说明的是，本实施方式中栅极材料层包括了第一栅极材料层310和第二栅极材料层320，第一子使能信号线61、第一子栅极驱动信号线51和第一子复位信号线71均位于第一栅极材料层310，第一栅极材料层310还设置有电容的一个电极板91(参考图6)，第二栅极材料层320用于设置电容的另一个电极板92以及其他导电连接部(参考图7)。在其他实施方式中，第一子使能信号线61、第一子栅极驱动信号线51和第一子复位信号线71也可以均设置在第二栅极材料层320。或者，这三种信号线可以分布在两个栅极材料层内。当然，栅极材料层可以只设置一层，这三种信号线均位于该栅极材料层内。
在其他实施例中，本公开的第二子信号线也可以位于其他负载电阻较低的膜层。例如在LTPO背板(Low Temperature Polycrystalline Oxide，低温多晶氧化物，即同一个像素中集成了LTPS和Oxide两种TFT器件， Oxide是底栅结构，LTPS是顶栅结构)中，该背板还包括设置于第二栅极材料层320与第一源漏极材料子层410之间的第三栅极材料层，以及设置于poly半导体有源层与衬底基板之间的遮挡层等其他导电膜层，当第二子信号线位于这些导电膜层时，同样能够降低驱动信号线整体的负载电阻。
再者，在一些实施例中，也可以也其他导电层(例如第三栅极材料层、遮挡层等)上设置第三子信号线，并使分别位于三个导电层的第一子信号线、第二子信号线和第三子信号线通过转接孔并联，同样能够降低驱动信号线整体的负载电阻。
本公开中，像素驱动电路中所需的使能信号、栅极驱动信号和复位信号可以由位于周边区的GOA驱动电路提供，GOA驱动电路能够实现行扫描，且能够降低阵列基板的制作成本。
参考图14，为本实施方式中一种GOA驱动电路的电路图，移位寄存电路可以包括：第一开关单元T1、第二开关单元T2、第三开关单元T3、第四开关单元T4、第五开关单元T5、第六开关单元T6、第七开关单元T7、第八开关单元T8、第一电容C1、第二电容C2。第一开关单元T1的控制端连接时钟信号端CK，第一端连接输入信号端，第二端连接第一节点N1；第三开关单元T3的控制端连接时钟信号端CK，第一端连接电源端VL，第二端连接第二节点N2；第二开关单元T2的控制端连接第一节点N1，端时钟信号端CK，第二端连接第二节点N2；第六开关单元T6的控制端连接第二节点N2，第一端连接电源信号端VH；第七开关单元T7的控制端连接时钟信号端CB，第一端连接第六开关单元T6的第二端，第二端连接第一节点N1；第八开关单元T8的控制端连接电源端VL，第一端连接第一节点N1；第五开关单元T5的控制端连接第八开关单元T8的第二端，第一端连接时钟信号端CB，第二端连接输出端OUT；第四开关单元T4的控制端连接第二节点N2，第一端连接电源端VH，第二端连接输出端OUT；第一电容C1连接于第八开关单元T8第二端和输出端OUT之间；第二电容C2连接于电源信号端VH和第二节点N2之间。
参考图15，为图14所示的GOA驱动电路的一种版图，其中，电源 信号线VH、时钟信号线CK、时钟信号线CB均设置于第二源漏极材料子层420，第一电容C1的一个极板设置于第一栅极材料层310，另一极板设置于第二栅极材料层320；第二电容C2的一个极板设置于第一栅极材料层310，另一极板设置于第二栅极材料层320。本实施例的版图中，位于第一栅极材料层310的输出端OUT连接第一子栅极驱动线51，用以向第一子栅极驱动线51输出栅极驱动信号。GOA驱动电路位于周边区，因此第一子栅极驱动线51也由周边区延伸至显示区。如图所示，第二子栅极驱动线52也可以由周边区延伸至显示区，且其位于周边区部分在衬底基板100上的投影与第一子栅极驱动线51周边区部分的投影重叠，二者通过设置在周边区的过孔电连接。参考图15示出了图14中B-B向的截面图，由于第一栅极材料层310和第二源漏极材料子层420中间间隔有第一源漏极材料子层410，因此需要通过设置在第一源漏极材料子层410上的导电连接部80使得第一子栅极驱动线51和第二子栅极驱动线连接，即导电连接部80和第一子栅极驱动线51通过一过孔连接，导电连接部80和第二子栅极驱动线52通过另一过孔连接。
在其他实施方式中，过孔还可以设置在其他位置，例如显示区。过孔的数量可以设置一个或多个，本申请不对此进行特殊限定。当过孔数量为多个时，可以在周边区相对的两侧分别设置，以用于使第一子栅极驱动线51和第二子栅极驱动线52电连接，而在显示区不设置过孔，以减小显示区过孔制作，提高分辨率。
图15和图16中以栅极驱动线为例说明了GOA驱动电路与像素电路之间的一种版图结构，该GOA为Gate GOA，本领域技术人员可以理解的是，下一级子像素的复位信号线可以与上一级子像素的栅极驱动线相连，以使上一级子像素的栅极驱动信号能够作为下一级子像素的复位信号，从而避免为复位信号单独引入专门的信号线，有效减少布线空间。因此，可以连接为，Gate GOA驱动电路的输出端还与第一子复位信号线71连接，进而通过过孔与第二子复位信号线72连接，用以向各像素单元传输复位信号。另外，GOA驱动电路还可以包括能够输出使能信号的输出端，该输出端与像素电路的第一子使能信号线61连接，进而通过过孔与第二子使能信号线62连接，用以向各像素单元传输使能信号，即该 GOA为EM GOA。需要说明的是，Gate GOA和EM GOA可以是一个整体的GOA，也可以是两个独立的GOA，本申请不对此进行特殊限定。
应该理解的是，图13提供的移位寄存器单元可以与图1中像素驱动电路配合应用于显示面板中，本示例性实施例提供的移位寄存器单元还可以与其他像素驱动电路配合使用应用于显示面板中，或者，本示例性实施例提供的像素驱动电路还可以和其他的移位寄存器单元使用应用于显示面板中。本公开不对移位寄存器单元和像素驱动电路进行限定。
本发明实施方式还提供一种显示装置，该显示装置包括上述实施方式的阵列基板。由于该显示装置包括上述阵列基板，因此具有相同的有益效果，本发明在此不再赘述。
本发明对于显示装置的适用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有柔性显示功能的产品或部件。
经验证，本公开驱动信号线的双层结构设置可以使的GOA电路负载电阻降低至0.65kΩ，与单层结构相比，本公开的GOA电路负载降低为单层结构的49％，大大降低了GOA的输出功耗，同时可以减小GOA电路输出管尺寸。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种阵列基板，具有显示区和围绕所述显示区的周边区，其中，所述阵列基板还包括：
    衬底基板；
    栅极材料层，设于所述衬底基板的一侧；
    源漏极材料层，设于所述栅极材料层背离所述衬底基板的一侧；
    所述阵列基板还包括驱动信号线，所述驱动信号线包括第一子信号线和第二子信号线，所述第一子信号线设于所述栅极材料层且由所述周边区延伸至显示区，所述第二子信号线设于所述源漏极材料层且至少位于所述显示区，所述第一子信号线和第二子信号线通过过孔电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述源漏极材料层包括：
    第一源漏极材料子层，设于所述栅极材料层背离所述衬底基板的一侧；
    第二源漏极材料子层，设于所述第一源漏极材料子层背离所述衬底基板的一侧；
    其中，所述第二子信号线设于所述第一源漏极材料子层或第二源漏极材料子层。
  3. 根据权利要求2所述的阵列基板，其中，所述驱动信号线包括栅极驱动信号线，所述第一子信号线包括第一子栅极驱动线，所述第二子信号线包括第二子栅极驱动线，所述第一子栅极驱动线设于所述栅极材料层且由所述周边区延伸至显示区，所述第二子栅极驱动线设于所述第一源漏极材料子层或第二源漏极材料子层且至少位于所述显示区，所述第一子栅极驱动线和第二子栅极驱动线通过过孔电连接。
  4. 根据权利要求2所述的阵列基板，其中，所述驱动信号线包括使能信号线，所述第一子信号线包括第一子使能信号线，所述第二子信号线包括第二子使能信号线，所述第一子使能信号线设于所述栅极材料层且由所述周边区延伸至显示区，所述第二子使能信号线设于所述第一源漏极材料子层或第二源漏极材料子层且至少位于所述显示区，所述第一子使能信号线和第二子使能信号线通过过孔电连接。
  5. 根据权利要求2所述的阵列基板，其中，所述驱动信号线包括复 位信号线，所述第一子信号线包括第一子复位信号线，所述第二子信号线包括第二子复位信号线，所述第一子复位信号线设于所述栅极材料层且由所述周边区延伸至显示区，所述第二子复位信号线设于所述第一源漏极材料子层或第二源漏极材料子层且至少位于所述显示区，所述第一子复位信号线和第二子复位信号线通过过孔电连接。
  6. 根据权利要求2-5中任一项所述的阵列基板，其中，所述第一子信号线和第二子信号线沿相同方向延伸，或沿不同方向延伸。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括电源线，所述电源线包括第一子电源线和第二子电源线，所述第一子电源线设于所述第一源漏极材料子层，所述第二子电源线设于所述第二源漏极材料子层，所述第一子电源线和第二子电源线通过过孔电连接。
  8. 根据权利要求7所述的阵列基板，其中，所述第二子信号线和第二子电源线均位于所述第二源漏极材料子层，所述第二子信号线和第二子电源线沿同一方向延伸，且沿另一方向排列。
  9. 根据权利要求8所述的阵列基板，其中，所述第一子信号线沿第一方向延伸，所述第一子电源线沿第二方向延伸，所述第二子信号线和第二子电源线均沿所述第一方向延伸，且沿所述第二方向排列，所述第一方向和第二方向相交。
  10. 根据权利要求7-9中任一项所述的阵列基板，其中，所述第二子信号线还位于所述周边区，所述第一子信号线和所述第二子信号线在所述周边区通过过孔电连接。
  11. 根据权利要求1所述的阵列基板，其中，所述第二子信号线的线宽大于所述第一子信号线的线宽。
  12. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    层间介质层，设于所述第二栅极材料层和第一源漏极材料子层之间；
    绝缘层，设于所述第一源漏极材料子层和第二源漏极材料子层之间；’
    平坦层，设于所述第一源漏极材料子层和第二源漏极材料子层之间，且位于所述绝缘层背离所述第一源漏极材料子层的一侧。
  13. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括GOA驱动电路，所述第一子信号线连接所述GOA驱动电路的输出端。
  14. 根据权利要求1所述的阵列基板，其中，所述栅极材料层包括层叠设置的第一栅极材料层和第二栅极材料层以及位于所述第一栅极材料层和第二栅极材料层之间的栅极绝缘层，所述第一子信号线位于所述第一栅极材料层或第二栅极材料层。
  15. 一种显示装置，其中，包括权利要求1-14中任一项所述的阵列基板。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474435A (zh) * 2013-09-17 2013-12-25 京东方科技集团股份有限公司 阵列基板及其制作方法
US20150123136A1 (en) * 2013-11-07 2015-05-07 Lg Display Co., Ltd. Array Substrate For Display Panel And Method For Manufacturing Thereof
CN109491543A (zh) * 2018-11-06 2019-03-19 京东方科技集团股份有限公司 一种触控显示面板、制作方法及驱动方法
CN110416270A (zh) * 2019-07-30 2019-11-05 京东方科技集团股份有限公司 Oled显示面板及其检测方法、显示装置
CN209729911U (zh) * 2019-06-19 2019-12-03 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN111682054A (zh) * 2020-06-24 2020-09-18 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474435A (zh) * 2013-09-17 2013-12-25 京东方科技集团股份有限公司 阵列基板及其制作方法
US20150123136A1 (en) * 2013-11-07 2015-05-07 Lg Display Co., Ltd. Array Substrate For Display Panel And Method For Manufacturing Thereof
CN109491543A (zh) * 2018-11-06 2019-03-19 京东方科技集团股份有限公司 一种触控显示面板、制作方法及驱动方法
CN209729911U (zh) * 2019-06-19 2019-12-03 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN110416270A (zh) * 2019-07-30 2019-11-05 京东方科技集团股份有限公司 Oled显示面板及其检测方法、显示装置
CN111682054A (zh) * 2020-06-24 2020-09-18 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置

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