WO2022160801A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

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Publication number
WO2022160801A1
WO2022160801A1 PCT/CN2021/125734 CN2021125734W WO2022160801A1 WO 2022160801 A1 WO2022160801 A1 WO 2022160801A1 CN 2021125734 W CN2021125734 W CN 2021125734W WO 2022160801 A1 WO2022160801 A1 WO 2022160801A1
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Prior art keywords
group
signal lines
pixel driving
driving circuits
emitting devices
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PCT/CN2021/125734
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English (en)
French (fr)
Inventor
杨明
张振宇
徐传祥
李付强
王亚薇
张晨阳
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/907,027 priority Critical patent/US20230132313A1/en
Publication of WO2022160801A1 publication Critical patent/WO2022160801A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • a display panel including: a base substrate including a display area, the display area including a first display area and a second display area other than the first display area; a first display area a group of light-emitting devices, located in the first display area, and including a plurality of first light-emitting devices; a first group of pixel driving circuits, located in the second display area, configured to drive the plurality of first light-emitting devices at least one of them, and includes at least one first pixel driving circuit; a second group of light-emitting devices, located in the second display area, and including a plurality of second light-emitting devices; and a second group of pixel driving circuits, located in the second a display area, and includes a plurality of second pixel driving circuits configured to drive the plurality of second light emitting devices, wherein, in a direction perpendicular to the base substrate, the first group of pixel driving circuits and the plurality of pixel
  • the plurality of first light emitting devices includes a first group of first light emitting devices and a second group of first light emitting devices;
  • the at least one first pixel driver circuit includes: a first group of first pixel driver circuits , configured to drive the first group of first light-emitting devices, and a second group of first pixel driving circuits configured to drive the second group of first light-emitting devices;
  • the display panel further includes: a first group of A first signal line is electrically connected to the first group of first pixel driving circuits; a first group of second signal lines is electrically connected to the first group of first light-emitting devices, and is electrically connected to the first group of via holes the first group of first signal lines; the second group of first signal lines, electrically connected to the second group of first pixel driving circuits; and the second group of second signal lines, electrically connected to the second group of a light emitting device electrically connected to the second group of first signal lines via a second group of vias.
  • the first set of second signal lines and at least one set of the second set of second signal lines include: a first subset of second signal lines; and a second subset The second signal lines are located on a different layer from the first subset of the second signal lines.
  • the first group of first signal lines is located on a side of the first group of first pixel driving circuits away from the second group of first pixel driving circuits; the first group of second signal lines located on the side of the first group of first light-emitting devices away from the second group of light-emitting devices; the second group of first signal lines are located in the second group of first pixel drive circuits away from the first group of first one side of the pixel driving circuit; and the second group of second signal lines is located on the side of the second group of first light-emitting devices away from the first group of light-emitting devices.
  • each first signal line in the first set of first signal lines includes: a first portion extending along a first direction and electrically connected to the first set of first pixel driving circuits a first pixel driving circuit of the is electrically connected to one second signal line in the first group of second signal lines.
  • each first signal line in the second set of first signal lines includes a third portion extending along the first direction and electrically connected to the second set of first pixels a first pixel drive circuit of the drive circuits; and a fourth portion electrically connected to the third portion, extending along the second direction, and electrically connected via one of the second set of vias to one second signal line in the second group of second signal lines.
  • the first set of second signal lines and the second set of second signal lines extend along the second direction.
  • the display panel further includes: a plurality of third signal lines electrically connected to the first group of pixel driving circuits; and a plurality of fourth signal lines electrically connected to the second group of pixel driving circuits
  • a first group of fourth signal lines in the plurality of fourth signal lines is electrically connected to the plurality of third signal lines and is located at a different layer from the plurality of third signal lines.
  • the orthographic projections of the plurality of third signal lines on the base substrate do not overlap with the first display area; and the plurality of fourth signal lines are on the base substrate The orthographic projection on does not overlap with the first display area.
  • the plurality of third signal lines include a plurality of first-type third signal lines and a plurality of second-type third signal lines; and the first group of fourth signal lines includes a plurality of first-type third signal lines and a plurality of fourth signal lines of the second type, the plurality of the fourth signal lines of the first type are electrically connected to the plurality of the third signal lines of the first kind, the plurality of the fourth signal lines of the second kind Four signal lines are electrically connected to the plurality of second type third signal lines.
  • a distance between adjacent first type third signal lines in the plurality of first type third signal lines is greater than a distance between adjacent first type and fourth signal lines in the plurality of first type fourth signal lines The distance between the fourth signal lines of the second type; and the distance between the adjacent third signal lines of the second type in the plurality of the third signal lines of the second type is greater than the distance between the plurality of the fourth signal lines of the second type The distance between adjacent second type fourth signal lines.
  • the display panel further includes: a plurality of fifth signal lines electrically connected to the first group of pixel driving circuits and extending along a first direction, where the plurality of fifth signal lines are located the orthographic projection on the base substrate overlaps the orthographic projection of the first group of pixel driving circuits on the base substrate; a plurality of sixth signal lines are electrically connected to the second group of pixel driving circuits, and extending along the first direction shown, the orthographic projection of the plurality of sixth signal lines on the base substrate does not overlap with the first display area; and a plurality of seventh signal lines, electrically connected to the between the plurality of fifth signal lines and the first group of sixth signal lines among the plurality of sixth signal lines, and extending along a second direction different from the first direction.
  • the plurality of seventh signal lines and the plurality of fifth signal lines are located at different layers, and are located at different layers from the plurality of sixth signal lines.
  • an orthographic projection of each seventh signal line in the plurality of seventh signal lines on the base substrate is at least one of the fifth signal lines in the plurality of fifth signal lines.
  • the orthographic projections on the base substrate overlap and overlap with the orthographic projections of at least one sixth signal line of the plurality of sixth signal lines on the base substrate.
  • the plurality of fifth signal lines, the sixth signal lines and the plurality of seventh signal lines include at least one of gate lines, light emission control lines, reset lines, and initialization lines.
  • the orthographic projections of the second set of pixel driving circuits on the base substrate do not overlap with the orthographic projections of the first set of pixel driving circuits on the base substrate.
  • the number of the plurality of second light emitting devices is greater than the number of the plurality of first light emitting devices; the number of the plurality of second pixel driving circuits is greater than the number of the at least one first pixel driving circuit and in a direction perpendicular to the base substrate, the first group of pixel driving circuits is located between the second group of pixel driving circuits and the base substrate.
  • a display device comprising: the display panel according to any one of the above embodiments.
  • the display device further includes: a camera located on a side of the base substrate away from the first group of light-emitting devices and located in the first display area.
  • a method for manufacturing a display panel including: providing a base substrate, the base substrate including a display area, the display area including a first display area and a first display area other than the first display area a second display area outside the display area; and forming a first group of light-emitting devices located in the first display area, a first group of pixel driving circuits located in the second display area, and a second group located in the second display area A group of light-emitting devices and a second group of pixel driving circuits located in the second display area.
  • the first group of light emitting devices includes a plurality of first light emitting devices, and the first group of pixel driver circuits are configured to drive at least one of the plurality of first light emitting devices and include at least one pixel driver circuit.
  • the second group of light emitting devices includes a plurality of second light emitting devices, and the second group of pixel driving circuits includes a plurality of second pixel driving circuits configured to drive the plurality of second light emitting devices.
  • a group of pixel driving circuits in the first group of pixel driving circuits and the second group of pixel driving circuits are located in the first group of pixel driving circuits and the second group of pixel driving circuits between another group of pixel driving circuits in the group of pixel driving circuits and the base substrate.
  • FIG. 1A is a schematic structural diagram illustrating a display panel according to an embodiment of the present disclosure
  • FIG. 1B is a schematic structural diagram illustrating a base substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram illustrating wiring between a first group of light-emitting devices and a first group of pixel driving circuits according to an embodiment of the present disclosure
  • FIGS. 3A-3C are schematic cross-sectional views illustrating V1, V2, and V3 shown in FIG. 2 according to some embodiments of the present disclosure
  • 4A is a schematic cross-sectional view illustrating a first group of second signal lines according to an embodiment of the present disclosure
  • 4B is a schematic cross-sectional view illustrating a second group of second signal lines according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram illustrating a layout of a third signal line and a fourth signal line according to an embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional view at V4 shown in FIG. 5 according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram illustrating a layout of a fifth signal line, a sixth signal line, and a seventh signal line according to an embodiment of the present disclosure
  • FIG. 8A and 8B are schematic cross-sectional views at V5 and V6 shown in FIG. 7 illustrating some implementations of the present disclosure
  • FIG. 9 is a schematic structural diagram illustrating a display device according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic flowchart illustrating a method of manufacturing a display panel according to an embodiment of the present disclosure.
  • first,” “second,” and similar words do not denote any order, quantity, or importance, but are merely used to distinguish the different parts.
  • “Comprising” or “comprising” and similar words mean that the element preceding the word covers the elements listed after the word, and does not exclude the possibility that other elements are also covered.
  • “Up”, “down”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • a specific component when a specific component is described as being between a first component and a second component, there may or may not be an intervening component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without intervening components, or may not be directly connected to the other components but have intervening components.
  • FIG. 1A is a schematic structural diagram illustrating a display panel according to an embodiment of the present disclosure.
  • FIG. 1B is a schematic structural diagram illustrating a base substrate according to an embodiment of the present disclosure.
  • the display panel may include a base substrate 11 , a first group of light emitting devices 12 , a first group of pixel driving circuits 13 , a second group of light emitting devices 14 and a second group of pixel driving circuits 15 .
  • the base substrate 11 includes a display area 110 .
  • the display area 110 includes a first display area 1101 and a second display area 1102 other than the first display area 1101 .
  • other areas of the display area 110 except the first display area 1101 are referred to as the second display area 1102 .
  • the number of the first display areas 1101 may be one or more.
  • the shape of the first display area 1101 may be, for example, a square, a circle, or the like.
  • the second display area 1102 may completely surround the first display area 1101 ; for another example, the second display area 1102 may partially surround the first display area 1101 , that is, a part of the edge of the first display area 1101 and the edge of the display area 111 Some edges overlap.
  • the first display area 1101 is an area for setting the camera.
  • the base substrate 11 may further include a peripheral area (not shown in FIG. 1B ) surrounding the display area 110 .
  • the base substrate 11 may include a flexible substrate.
  • the material of the base substrate 11 may include an organic material such as polyimide (PI).
  • the first group of light emitting devices 12 are located in the first display area 1101 .
  • the first group of light emitting devices 12 includes a plurality of first light emitting devices 120 .
  • the first light emitting device 121 may include, for example, an organic light emitting diode (OLED).
  • the first group of pixel driving circuits 13 are located in the second display area 1102 and are configured to drive at least one first light emitting device 121 of the plurality of first light emitting devices 120 .
  • the first group of pixel driving circuits 13 includes at least one first pixel driving circuit 130 .
  • the number of the first pixel driving circuits 130 in the first group of pixel driving circuits 13 is less than or equal to the number of the first light emitting devices 120 in the first group of light emitting devices 12 .
  • the first group of light-emitting devices 12 may include M (rows) ⁇ N (columns) of first light-emitting devices 120
  • the first group of pixel driving circuits 13 may include P (rows) ⁇ Q (columns) of first pixel driving circuits 130.
  • N may be an even number or an odd number
  • (M ⁇ N)/(P ⁇ Q) is an integer, such as 1, 2, and the like.
  • one first pixel driving circuit 130 may drive one first light emitting device 120 to emit light; for another example, one first pixel driving circuit 130 may drive two or more first light emitting devices 120 to emit light.
  • the second group of light emitting devices 14 are located in the second display area 1102 .
  • the second group of light emitting devices 14 includes a plurality of second light emitting devices 140 .
  • the second light emitting device 140 may include, for example, an OLED.
  • the second group of pixel driving circuits 15 is located in the second display area 1102 and includes a plurality of second pixel driving circuits 150 configured to drive the plurality of second light emitting devices 140 .
  • the number of the second pixel driving circuits 150 in the second group of pixel driving circuits 15 is greater than or equal to the number of the second light-emitting devices 140 in the second group of light-emitting devices 14 .
  • one second pixel driving circuit 150 may drive one second light emitting device 141 to emit light; for another example, one second pixel driving circuit 150 may drive two or more second light emitting devices 140 to emit light.
  • a group of pixel driving circuits in the first group of pixel driving circuits 13 and the second group of pixel driving circuits 15 are located in the first group of pixel driving circuits 13 and the second group of pixel driving circuits 15 between another group of pixel driving circuits and the base substrate 11 .
  • the first group of pixel driving circuits 13 and the second group of pixel driving circuits 15 are located in different spaces.
  • the first group of light emitting devices 12 and the second group of light emitting devices 14 are located on a side of the first group of pixel driving circuits 13 and the second group of pixel driving circuits 15 away from the base substrate 111 .
  • the first planarization layer PLN1 covers the first group of pixel driving circuits 13
  • the second group of pixel driving circuits 15 is located on the side of the first planarization layer PLN1 away from the base substrate 11
  • the second group of pixel driving circuits 15 The planarization layer PLN2 covers the second group of pixel driving circuits 15
  • the first group of light-emitting devices 12 and the second group of light-emitting devices 14 are located on the side of the second planarization layer PLN2 away from the base substrate 11 .
  • the first group of pixel driving circuits 13 for driving one or more first light-emitting devices 120 are located in the second display area 1102, so that the area of the display panel corresponding to the first display area 1101 can be increased. of light transmittance.
  • the first group of pixel driving circuits 13 and the second group of pixel driving circuits 15 are located in different spaces, so that a greater number of first pixel driving circuits 1101 can be arranged in the first display area 1101 .
  • the light emitting device 120 is beneficial to improve the display resolution of the area of the display panel corresponding to the first display area 1101 .
  • the first pixel driving circuit 131 in the first group of pixel driving circuits 13 and the second pixel driving circuit 151 in the second group of pixel driving circuits 15 may include a plurality of thin film transistors and capacitors.
  • the first pixel driving circuit 131 and the second pixel driving circuit 151 may include 2 thin film transistors and one capacitor (2T1C), 6 thin film transistors and one capacitor (6T1C), or 7 thin film transistors and one capacitor (7T1C) .
  • the active layer of each thin film transistor may include low temperature polysilicon (LTPS) or an oxide semiconductor.
  • the orthographic projection of the second group of pixel driving circuits 15 on the base substrate 11 does not overlap with the orthographic projection of the first group of pixel driving circuits 13 on the base substrate, so that the number of pixels in the second group can be reduced.
  • the mutual influence between the driving circuit 15 and the first group of pixel driving circuits 13 is beneficial to improve the display effect of the display panel.
  • the number of the plurality of second light-emitting devices 150 is greater than the number of the plurality of first light-emitting devices 120
  • the number of the plurality of second pixel driving circuits 130 is greater than that of the first group of pixel driving circuits 13 .
  • the number of pixel driving circuits 131 is one, and in the direction perpendicular to the base substrate 11 , the first group of pixel driving circuits 13 is located between the second group of pixel driving circuits 15 and the base substrate 11 . That is, the pixel driving circuits 13 of the first group are closer to the base substrate 11 than the pixel driving circuits 15 of the second group.
  • Such a structure is more conducive to the wiring between the second group of pixel driving circuits 15 and the second group of light emitting devices 14 .
  • FIG. 2 is a schematic diagram illustrating wiring between a first group of light emitting devices and a first group of pixel driving circuits according to an embodiment of the present disclosure.
  • the plurality of first light emitting devices 120 in the first group of light emitting devices 12 include a first group of first light emitting devices 121 and a second group of first light emitting devices 122 .
  • At least one first pixel driving circuit 130 in the first group of pixel driving circuits 13 includes a first group of first pixel driving circuits 131 and a second group of first pixel driving circuits 132 .
  • the first group of first pixel driving circuits 131 are configured to drive the first group of first light emitting devices 121
  • the second group of first pixel driving circuits 132 are configured to drive the second group of first light emitting devices 122 .
  • the display panel further includes a first group of first signal lines 16 , a first group of second signal lines 17 , a second group of first signal lines 18 and a second group of second signal lines 19 .
  • the first group of first signal lines 16 are electrically connected to the first group of first pixel driving circuits 131 ;
  • the first group of second signal lines 17 are electrically connected to the first group of first light-emitting devices 121 , and are electrically connected to the first group of via holes V1 .
  • the second group of first signal lines 18 are electrically connected to the second group of first pixel driving circuits 132; the second group of second signal lines 19 are electrically connected to the second group of first light-emitting devices 122, and is electrically connected to the second group of first signal lines 18 via the second group of vias V2.
  • the material of the first set of second signal lines 17 and the second set of second signal lines 19 includes a transparent material, such as indium tin oxide (ITO) or the like. In this way, it is beneficial to further increase the light transmittance of the area of the display panel corresponding to the first display area 1101 .
  • ITO indium tin oxide
  • the material of the first set of first signal lines 16 and the second set of first signal lines 18 includes a metal.
  • FIGS 3A-3C are schematic cross-sectional views showing V1, V2, and V3 shown in Figure 2 in accordance with some embodiments of the present disclosure.
  • each of the second signal lines 17 in the first group of second signal lines 17 is electrically connected to a corresponding one of the first signal lines in the first group of first signal lines 16 via a via hole V1 penetrating the insulating layer ILD1 Line 16.
  • the insulating layer ILD1 may include one or more insulating layers.
  • each second signal line 19 in the second group of second signal lines 19 is electrically connected to a corresponding one of the first signal lines in the second group of first signal lines 18 via a via V2 penetrating the insulating layer ILD2 Line 18.
  • the insulating layer ILD2 may include one or more insulating layers.
  • each of the second signal lines 17 in the first group of second signal lines 17 is electrically connected to one of the first light-emitting devices in the first group of first light-emitting devices 121 via vias V3 penetrating the insulating layer ILD3 120 anode AND.
  • the insulating layer ILD3 may be, for example, the second planarization layer 120 shown in FIG. 1B .
  • the first group of first signal lines 16 is located on the side of the first group of first pixel driving circuits 131 away from the second group of first pixel driving circuits 132
  • the first group of second signal lines 17 Located on the side of the first group of first light-emitting devices 121 away from the second group of light-emitting devices 122
  • the second group of first signal lines 18 are located at a side of the second group of first pixel driving circuits 132 away from the first group of first pixel driving circuits 131
  • the second group of the second signal lines 19 is located on the side of the second group of the first light emitting devices 122 away from the first group of the light emitting devices 121 .
  • first group of first signal lines 16 and the second group of first signal lines 18 are located on both sides of the first group of pixel driving circuits 13, respectively, and the first group of second signal lines 17 and the second group of second signal lines Lines 19 are located on both sides of the first group of light-emitting devices 12 respectively, which is beneficial to reduce the size of the first group of first signal lines 16, the second group of first signal lines 18, the first group of second signal lines 17 and the second group of second signal lines 17.
  • the signal lines 19 interfere with each other.
  • each first signal line 16 in the first set of first signal lines 16 includes a first portion 161 and a second portion 162 electrically connected to the first portion 161 .
  • the first part 161 and the second part 162 may be located on the same layer, or may be located on different layers.
  • the two parts are located in the same layer means that the two parts are formed by patterning the same material layer, and the two parts are located in different layers means that the two parts are formed by patterning different layers.
  • the material layer is formed by patterning.
  • the first portion 161 extends along the first direction and is electrically connected to one of the first pixel driving circuits 130 of the first group of first pixel driving circuits 131 .
  • the second portion 162 extends in a second direction different from the first direction, and is electrically connected to one first signal line 17 of the second group of first signal lines 17 via one via V1 of the first group of vias V1 .
  • the second direction is perpendicular to the first direction.
  • each first signal line 18 in the second set of first signal lines 18 includes a third portion 181 and a fourth portion 182 electrically connected to the third portion 181 .
  • the third part 181 and the fourth part 182 may be located on the same layer, or may be located on different layers.
  • the third portion 181 extends along the first direction and is electrically connected to one of the first pixel driving circuits 130 of the second group of first pixel driving circuits 132 .
  • the fourth portion 182 extends along the second direction and is electrically connected to one second signal line 19 of the second group of second signal lines 19 via one via V2 of the second group of vias V2.
  • the first set of second signal lines 17 and the second set of second signal lines 19 extend along the second direction.
  • 4A is a schematic cross-sectional view illustrating a first group of second signal lines according to one embodiment of the present disclosure.
  • 4B is a schematic cross-sectional view illustrating a second group of second signal lines according to one embodiment of the present disclosure.
  • At least one of the first set of second signal lines 17 and the second set of second signal lines 19 includes two subsets of second signal lines located on the same layer.
  • the first group of second signal lines 17 includes a first subgroup of second signal lines 171 and a second subgroup of second signal lines 172 located at different layers from the first subgroup of second signal lines 171 .
  • the first group of second signal lines 19 includes a first subgroup of second signal lines 191 and a second subgroup of second signal lines 192 located at different layers from the first subgroup of second signal lines 191 .
  • an insulating layer ILD4 may be disposed between two subsets of second signal lines located at different layers.
  • FIG. 5 is a schematic layout diagram illustrating a third signal line and a fourth signal line according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view at V4 shown in FIG. 5 according to one embodiment of the present disclosure.
  • the display panel further includes a plurality of third signal lines 20 and a plurality of fourth signal lines 21 .
  • the plurality of third signal lines 20 are electrically connected to the first group of pixel driving circuits 13
  • the plurality of fourth signal lines 21 are electrically connected to the second group of pixel driving circuits 15 shown in FIG. 1B .
  • the plurality of third signal lines 20 and the plurality of fourth signal lines 21 may extend along the second direction, for example.
  • the first group of fourth signal lines 211 of the plurality of fourth signal lines 21 are electrically connected to the plurality of third signal lines 20 .
  • a part of the fourth signal lines 211 of the plurality of fourth signal lines 21 are electrically connected to the plurality of third signal lines 20 .
  • the first group of fourth signal lines 211 are electrically connected to the plurality of third signal lines 20 via the fourth group of vias V4.
  • the first group of fourth signal lines 211 and the plurality of third signal lines 20 are located at different layers.
  • an insulating layer ILD5 is provided between the first group of fourth signal lines 211 and the plurality of third signal lines 20 .
  • the insulating layer ILD5 may include one or more insulating layers.
  • the plurality of third signal lines 20 and the plurality of fourth signal lines 21 may include at least one of data lines and power lines.
  • a data signal or a power supply signal may be provided to some of the second pixel driving circuits in the first group of pixel driving circuits 13 and the second group of pixel driving circuits 15 via the plurality of third signal lines 20 and the first group of fourth signal lines 211 150.
  • the material of the plurality of third signal lines 20 and the plurality of fourth signal lines 21 includes metal.
  • the first group of fourth signal lines 211 and the plurality of third signal lines 20 are located at different layers.
  • the plurality of third signal lines 20 do not need to occupy the space of the plurality of fourth signal lines 21 , therefore, a larger number of third signal lines 20 can be provided, which is more conducive to improving the display panel and the first display area.
  • the orthographic projection of at least one of the second portion 162 and the fourth portion 182 on the base substrate 11 does not overlap with the orthographic projection of the plurality of fourth signal lines 21 on the base substrate 11 . In this way, the mutual influence between at least one of the second part 162 and the fourth part 182 and the fourth signal line 21 can be reduced, thereby reducing crosstalk and improving the display effect of the display panel.
  • the orthographic projection of at least one group of second signal lines in the first group of second signal lines 17 and the second group of second signal lines 19 on the base substrate 11 is at the same level as the plurality of fourth signal lines 21 .
  • the orthographic projections on the base substrate 11 do not overlap. In this way, the mutual influence between at least one group of second signal lines in the first group of second signal lines 17 and the second group of second signal lines 19 and the fourth signal line 21 can be reduced, thereby reducing crosstalk, Improve the display effect of the display panel.
  • the plurality of third signal lines 20 include a plurality of first-type third signal lines (eg, data lines) and a plurality of second-type third signal lines (eg, power supply lines), and the first group of fourth signal lines
  • the lines 211 include a plurality of first-type fourth signal lines (eg, data lines) and a plurality of second-type fourth signal lines (eg, power supply lines).
  • the plurality of first type fourth signal lines are electrically connected to the plurality of first type third signal lines
  • the plurality of second type fourth signal lines are electrically connected to the plurality of second type third signal lines.
  • the distance between adjacent third signal lines 20 may be greater than the distance between adjacent fourth signal lines in the first group of fourth signal lines 211 distance between 21.
  • the distance between adjacent first type third signal lines in the plurality of first type third signal lines is greater than the distance between adjacent first type fourth signal lines in the plurality of first type fourth signal lines distance.
  • the distance between adjacent second type third signal lines among the plurality of second type third signal lines is greater than the distance between adjacent second type fourth signal lines among the plurality of second type fourth signal lines the distance.
  • the design space of the third signal lines 20 can be larger, so that the space between adjacent third signal lines 20 can be reduced. mutual influence.
  • the distance between adjacent third signal lines 20 is substantially equal to the distance between adjacent first pixel driving circuits 131
  • the distance between adjacent fourth signal lines 21 is substantially equal to the adjacent first light emitting circuits
  • the distance between the devices 121 , and the distance between the adjacent first pixel driving circuits 131 is greater than the distance between the adjacent first light emitting devices 121 .
  • the ratio of the distance between the adjacent third signal lines 20 and the distance between the adjacent first pixel driving circuits 131 is 0.8 to 1.2, for example, 1, 1.1, etc.; for another example, the adjacent fourth The ratio of the distance between the signal lines 21 to the distance between the adjacent first light emitting devices 121 is 0.8 to 1.2, eg, 1, 1.1, and the like.
  • the orthographic projections of the plurality of third signal lines 20 on the base substrate do not overlap with the first display area 1101
  • the orthographic projections of the plurality of fourth signal lines 21 on the base substrate do not overlap with the first display area 1101 .
  • a display area 1101 does not overlap. In this way, the light transmittance of the area of the display panel corresponding to the first display area 1101 can be further increased.
  • FIG. 7 is a schematic layout diagram illustrating a fifth signal line, a sixth signal line, and a seventh signal line according to an embodiment of the present disclosure.
  • the display panel further includes a plurality of fifth signal lines 22 , a plurality of sixth signal lines 23 and a plurality of seventh signal lines 24 .
  • the plurality of fifth signal lines 22 , the sixth signal lines 23 and the plurality of seventh signal lines 24 include at least one of gate lines, light emission control lines, reset lines, and initialization lines.
  • a gate signal, a light emission control signal, a reset signal, or an initialization signal is supplied to the first group of pixel driving circuits 13 and the first group of pixel driving circuits 13 and the first group via the plurality of fifth signal lines 22 , the plurality of sixth signal lines 23 and the plurality of seventh signal lines 24 .
  • Two groups of pixel driving circuits 15 Two groups of pixel driving circuits 15 .
  • the plurality of fifth signal lines 22 are electrically connected to the first group of pixel driving circuits 13 and extend along the first direction.
  • the orthographic projections of the plurality of fifth signal lines 22 on the base substrate 11 overlap with the orthographic projections of the first group of pixel driving circuits 13 on the base substrate 11 .
  • the plurality of sixth signal lines 23 are electrically connected to the second group of pixel driving circuits 15 and extend along the first direction.
  • the orthographic projections of the plurality of sixth signal lines 23 on the base substrate 11 do not overlap with the first display area 1101 .
  • a plurality of sixth signal lines 23 are respectively disposed on both sides of the first display area 1101 .
  • the plurality of seventh signal lines 24 are electrically connected between the plurality of fifth signal lines 22 and the first group of sixth signal lines 231 among the plurality of sixth signal lines 23, and along a second direction different from the first direction extend.
  • the plurality of seventh signal lines 24 are electrically connected to the plurality of fifth signal lines 22 via the fifth group of via holes V5, and are electrically connected to the first group of sixth signal lines 231 via the sixth group of via holes V5.
  • the material of the plurality of fifth signal lines 22 , the plurality of sixth signal lines 23 and the plurality of seventh signal lines 24 includes metal.
  • the orthographic projections of the plurality of sixth signal lines 23 on the base substrate 11 do not overlap with the first display area 1101, which can further increase the light transmission in the area of the display panel corresponding to the first display area 1101 Rate.
  • the orthographic projection of at least one of the first portion 161 and the third portion 181 on the base substrate 11 does not overlap with the orthographic projection of the plurality of fifth signal lines 22 on the base substrate 11 . In this way, the mutual influence between at least one of the first part 161 and the third part 181 and the plurality of fifth signal lines 22 can be reduced, thereby reducing crosstalk and improving the display effect of the display panel.
  • the orthographic projection of at least one of the second portion 162 and the fourth portion 182 on the base substrate 11 does not overlap with the orthographic projection of the plurality of seventh signal lines 24 on the base substrate 11 . In this way, the interaction between at least one of the second portion 162 and the fourth portion 182 and the seventh signal line 24 can be reduced, thereby reducing crosstalk and improving the display effect of the display panel.
  • FIG. 8A and 8B are schematic cross-sectional views at V5 and V6 shown in FIG. 7 illustrating some implementations of the present disclosure.
  • the plurality of seventh signal lines 24 are located between the plurality of fifth signal lines 22 and the plurality of sixth signal lines 23 .
  • the plurality of seventh signal lines 24 are electrically connected to the plurality of fifth signal lines 22 via the fifth group of via holes V5 penetrating the insulating layer ILD6, and are electrically connected to the plurality of sixth signal lines via the sixth group of via holes V6 penetrating the insulating layer ILD7 twenty three.
  • the plurality of sixth signal lines 23 are located between the plurality of fifth signal lines 22 and the plurality of seventh signal lines 24 .
  • the plurality of seventh signal lines 24 are electrically connected to the plurality of fifth signal lines 22 via a fifth set of vias V5 penetrating the insulating layer ILD6 and the insulating layer ILD7, and are electrically connected to the plurality of fifth signal lines 22 via a sixth set of vias V6 penetrating the insulating layer ILD7
  • the sixth signal line 23 is another implementation manner, as shown in FIG. 8B , in the direction perpendicular to the base substrate 11 .
  • the plurality of seventh signal lines 24 and the plurality of fifth signal lines 22 are located at different layers, and the plurality of sixth signal lines 23 are located at different layers. Such an approach is beneficial to reduce the space occupied by the plurality of seventh signal lines 24 .
  • the orthographic projection of each seventh signal line 24 in the plurality of seventh signal lines 24 on the base substrate 11 is lined with at least one fifth signal line 22 in the plurality of fifth signal lines 22
  • the orthographic projection on the base substrate 11 overlaps and overlaps with the orthographic projection of at least one sixth signal line 23 of the plurality of sixth signal lines 23 on the base substrate 11 .
  • the seventh signal line 24 can be arranged to overlap with the fifth signal line 22 and the sixth signal line 23, which is beneficial to reduce the space occupied by the seventh signal line 24.
  • FIG. 9 is a schematic structural diagram illustrating a display device according to an embodiment of the present disclosure.
  • the display device may include the display panel 10 of any one of the above embodiments.
  • the display device further includes a camera 20 located in the first display area 1101 and located on a side of the base substrate 11 away from the first group of light emitting devices 120 .
  • the display device may be, for example, a mobile terminal (eg, a smart phone, a tablet computer), a television, a monitor, a notebook computer, a digital photo frame, a navigator, an electronic paper, or any other product or component with a display function.
  • a mobile terminal eg, a smart phone, a tablet computer
  • a television e.g., a monitor, a notebook computer, a digital photo frame, a navigator, an electronic paper, or any other product or component with a display function.
  • FIG. 10 is a schematic flowchart illustrating a method of manufacturing a display panel according to an embodiment of the present disclosure.
  • a base substrate is provided.
  • the base substrate includes a display area
  • the display area includes a first display area and a second display area other than the first display area.
  • a first group of light-emitting devices located in the first display area, a first group of pixel driving circuits located in the second display area, a second group of light-emitting devices located in the second display area, and a second group of light-emitting devices located in the second display area are formed Group pixel drive circuit.
  • the first group of light emitting devices includes a plurality of first light emitting devices
  • the second group of light emitting devices includes a plurality of second light emitting devices.
  • the first group of pixel drive circuits is configured to drive at least one of the plurality of first light emitting devices and includes at least one pixel drive circuit.
  • the second set of pixel driving circuits includes a plurality of second pixel driving circuits configured to drive a plurality of second light emitting devices.
  • one group of pixel driving circuits in the first group of pixel driving circuits and the second group of pixel driving circuits is located in another group of pixels in the first group of pixel driving circuits and the second group of pixel driving circuits between the drive circuit and the base substrate.
  • the first group of pixel driving circuits for driving one or more first light-emitting devices is located in the second display area, so that the light transmittance of the area corresponding to the first display area of the display panel can be increased. Rate.
  • the first group of pixel driving circuits and the second group of pixel driving circuits are located in different spaces, so that a larger number of first light-emitting devices can be arranged in the first display area. It is beneficial to improve the display resolution of the area corresponding to the first display area of the display panel.

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Abstract

本公开提供了一种显示面板及其制造方法、显示装置，所述显示面板包括：衬底基板，包括显示区，显示区包括第一显示区和第二显示区；第一组发光器件，位于第一显示区，并且包括多个第一发光器件；第一组像素驱动电路，位于第二显示区，被配置为驱动多个第一发光器件中的至少一个，包括至少一个第一像素驱动电路；第二组发光器件，位于第二显示区，包括多个第二发光器件；和第二组像素驱动电路，位于第二显示区，包括被配置为驱动多个第二发光器件的多个第二像素驱动电路。在垂直于衬底基板的方向上，第一组像素驱动电路和第二组像素驱动电路中的一组像素驱动电路位于第一组像素驱动电路和第二组像素驱动电路中的另一组像素驱动电路与衬底基板之间。

Description

显示面板及其制造方法、显示装置
相关申请的交叉引用
本公开以中国申请号为202110105622.0，申请日为2021年1月26日的申请为基础，并主张其优先权，该中国申请的公开内容在此作为整体引入本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制造方法、显示装置。
背景技术
随着显示技术的发展，全面屏成为显示屏的发展趋势。显示屏的某些区域需要设置额外的器件，例如摄像头。这样的器件对全面屏的进一步发展提出了挑战。
发明内容
根据本公开实施例的一方面，提供一种显示面板，包括：衬底基板，包括显示区，所述显示区包括第一显示区和除所述第一显示区外的第二显示区；第一组发光器件，位于所述第一显示区，并且包括多个第一发光器件；第一组像素驱动电路，位于所述第二显示区，被配置为驱动所述多个第一发光器件中的至少一个，并且包括至少一个第一像素驱动电路；第二组发光器件，位于所述第二显示区，并且包括多个第二发光器件；和第二组像素驱动电路，位于所述第二显示区，并且包括被配置为驱动所述多个第二发光器件的多个第二像素驱动电路，其中，在垂直于所述衬底基板的方向上，所述第一组像素驱动电路和所述第二组像素驱动电路中的一组像素驱动电路位于所述第一组像素驱动电路和所述第二组像素驱动电路中的另一组像素驱动电路与所述衬底基板之间。
在一些实施例中，所述多个第一发光器件包括第一组第一发光器件和第二组第一发光器件；所述至少一个第一像素驱动电路包括：第一组第一像素驱动电路，被配置为驱动所述第一组第一发光器件，和第二组第一像素驱动电路，被配置为驱动所述第二组第一发光器件；并且所述显示面板还包括：第一组第一信号线，电连接至所述第一组第一像素驱动电路；第一组第二信号线，电连接至所述第一组第一发光器件，并且经由第一组过孔电连接至所述第一组第一信号线；第二组第一信号线，电连接至所 述第二组第一像素驱动电路；和第二组第二信号线，电连接至所述第二组第一发光器件，并且经由第二组过孔电连接至所述第二组第一信号线。
在一些实施例中，所述第一组第二信号线和所述第二组第二信号线中的至少一组第二信号线包括：第一子组第二信号线；和第二子组第二信号线，与所述第一子组第二信号线位于不同层。
在一些实施例中，所述第一组第一信号线位于所述第一组第一像素驱动电路远离所述第二组第一像素驱动电路的一侧；所述第一组第二信号线位于所述第一组第一发光器件远离所述第二组发光器件的一侧；所述第二组第一信号线位于所述第二组第一像素驱动电路远离所述第一组第一像素驱动电路的一侧；并且所述第二组第二信号线位于所述第二组第一发光器件远离所述第一组发光器件的一侧。
在一些实施例中，所述第一组第一信号线中的每个第一信号线包括：第一部分，沿着第一方向延伸，并且电连接至所述第一组第一像素驱动电路中的一个第一像素驱动电路；和与所述第一部分电连接的第二部分，沿着与所述第一方向不同的第二方向延伸，并且经由所述第一组过孔中的一个过孔电连接至所述第一组第二信号线中的一条第二信号线。
在一些实施例中，所述第二组第一信号线中的每个第一信号线包括：第三部分，沿着所述第一方向延伸，并且电连接至所述第二组第一像素驱动电路中的一个第一像素驱动电路；和与所述第三部分电连接的第四部分，沿着所述第二方向延伸，并且经由所述第二组过孔中的一个过孔电连接至所述第二组第二信号线中的一条第二信号线。
在一些实施例中，所述第一组第二信号线和所述第二组第二信号线沿着所述第二方向延伸。
在一些实施例中，所述显示面板还包括：多条第三信号线，电连接至所述第一组像素驱动电路；和多条第四信号线，电连接至所述第二组像素驱动电路，所述多条第四信号线中的第一组第四信号线电连接至所述多条第三信号线，并且与所述多条第三信号线位于不同层。
在一些实施例中，所述多条第三信号线在所述衬底基板上的正投影与所述第一显示区不交叠；并且所述多条第四信号线在所述衬底基板上的正投影与所述第一显示区不交叠。
在一些实施例中，所述多条第三信号线包括多条第一种第三信号线和多条第二种第三信号线；并且所述第一组第四信号线包括多条第一种第四信号线和多条第二种第四信号线，所述多条第一种第四信号线电连接至所述多条第一种第三信号线，所述多条第二种第四信号线电连接至所述多条第二种第三信号线。
在一些实施例中，所述多条第一种第三信号线中相邻的第一种第三信号线之间的距离大于所述多条第一种第四信号线中相邻的第一种第四信号线之间的距离；并且所述多条第二种第三信号线中相邻的第二种第三信号线之间的距离大于所述多条第二种第四信号线中相邻的第二种第四信号线之间的距离。
在一些实施例中，所述显示面板还包括：多条第五信号线，电连接至所述第一组像素驱动电路，并且沿着第一方向延伸，所述多条第五信号线在所述衬底基板上的正投影与所述第一组像素驱动电路在所述衬底基板上的正投影交叠；多条第六信号线，电连接至所述第二组像素驱动电路，并且沿着所示第一方向延伸，所述多条第六信号线在所述衬底基板上的正投影与所述第一显示区不交叠；和多条第七信号线，电连接在所述多条第五信号线和所述多条第六信号线中的第一组第六信号线之间，并且沿着与所述第一方向不同的第二方向延伸。
在一些实施例中，所述多条第七信号线与所述多条第五信号线位于不同层，并且与所述多条第六信号线位于不同层。
在一些实施例中，所述多条第七信号线中的每条第七信号线在所述衬底基板上的正投影与所述多条第五信号线中的至少一条第五信号线在所述衬底基板上的正投影交叠，并且与所述多条第六信号线中的至少一条第六信号线在所述衬底基板上的正投影交叠。
在一些实施例中，所述多条第五信号线、所述第六信号线和所述多条第七信号线包括栅极线、发光控制线、复位线、初始化线中的至少一种。
在一些实施例中，所述第二组像素驱动电路在所述衬底基板上的正投影与所述第一组像素驱动电路在所述衬底基板上的正投影不交叠。
在一些实施例中，所述多个第二发光器件的数量大于所述多个第一发光器件的数量；所述多个第二像素驱动电路的数量大于所述至少一个第一像素驱动电路的数量；并且在垂直于所述衬底基板的方向上，所述第一组像素驱动电路位于所述第二组像素驱动电路与所述衬底基板之间。
根据本公开实施例的另一方面，提供一种显示装置，包括：上述任意一个实施例所述的显示面板。
在一些实施例中，所述显示装置还包括：摄像头，位于所述衬底基板远离所述第一组发光器件的一侧，并且位于所述第一显示区。
根据本公开实施例的又一方面，提供一种显示面板的制造方法，包括：提供衬底基板，所述衬底基板包括显示区，所述显示区包括第一显示区和除所述第一显示区外的第二显示区；和形成位于所述第一显示区的第一组发光器件、位于所述第二显示区的第一组像素驱动电路、位于所述第二显示区的第二组发光器件和位于所述第二显示区的第二组像素驱动电路。所述第一组发光器件包括多个第一发光器件，所述第一组像素驱动电路被配置为驱动所述多个第一发光器件中的至少一个，并且包括至少一个像素驱动电路。所述第二组发光器件包括多个第二发光器件，所述第二组像素驱动电路包括被配置为驱动所述多个第二发光器件的多个第二像素驱动电路。在垂直于所述衬底基板的方向上，所述第一组像素驱动电路和所述第二组像素驱动电路中的一组像素驱动电路位于所述第一组像素驱动电路和所述第二组像素驱动电路中的另一组像素驱动电路与所述衬底基板之间。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本公开的示例性实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，在附图中：
图1A是示出根据本公开一个实施例的显示面板的结构示意图；
图1B是示出根据本公开一个实施例的衬底基板的结构示意图；
图2是示出根据本公开一个实施例的第一组发光器件和第一组像素驱动电路之间的布线示意图；
图3A-图3C是示出根据本公开一些实施例的图2所示V1、V2和V3处的截面示意图；
图4A是示出根据本公开一个实施例的第一组第二信号线的截面示意图；
图4B是示出根据本公开一个实施例的第二组第二信号线的截面示意图；
图5是示出根据本公开一个实施例的第三信号线和第四信号线的布局示意图；
图6是示出根据本公开一个实施例的图5所示V4处的截面示意图；
图7是示出根据本公开一个实施例的第五信号线、第六信号线和第七信号线的布局示意图；
图8A和图8B是示出根据本公开一些实现方式的图7所示V5和V6处的截面示意图；
图9是示出根据本公开一个实施例显示装置的结构示意图；
图10是示出根据本公开一个实施例的显示面板的制造方法的流程示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普 通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
发明人注意到，对于显示面板设置有诸如摄像头的器件的区域来说，这些区域在器件不工作时需要正常显示，而在器件工作时需要具有较高的光透过率。
有鉴于此，本公开实施例提出了如下技术方案。
图1A是示出根据本公开一个实施例的显示面板的结构示意图。图1B是示出根据本公开一个实施例的衬底基板的结构示意图。
下面结合图1A和图1B对根据本公开一些实施例的显示面板进行介绍。
如图1A所示，显示面板可以包括衬底基板11、第一组发光器件12、第一组像素驱动电路13、第二组发光器件14和第二组像素驱动电路15。
参见图1B，衬底基板11包括显示区110。这里，显示区110包括第一显示区1101和除第一显示区1101外的第二显示区1102。换言之，显示区110除第一显示区1101外的其他区域被称为第二显示区1102。第一显示区1101的数量可以是一个或多个。第一显示区1101的形状例如可以是方形、圆形等。例如，第二显示区1102可以完全地包围第一显示区1101；又例如，第二显示区1102可以部分地包围第一显示区1101，即，第一显示区1101的部分边缘与显示区111的部分边缘重叠。例如，第一显示区1101是用于设置摄像头的区域。
可以理解的是，衬底基板11还可以包括围绕显示区110的周边区(图1B未示出)。在一些实施例中，衬底基板11可以包括柔性基板。例如，衬底基板11的材料可以包括聚酰亚胺(PI)等有机材料。
第一组发光器件12位于第一显示区1101。第一组发光器件12包括多个第一发光器件120。第一发光器件121例如可以包括有机发光二极管(OLED)。
第一组像素驱动电路13位于第二显示区1102，并且被配置为驱动多个第一发光器件120中的至少一个第一发光器件121。这里，第一组像素驱动电路13包括至少一个第一像素驱动电路130。第一组像素驱动电路13中第一像素驱动电路130的数量小于或等于第一组发光器件12中第一发光器件120的数量。例如，第一组发光器件12可以包括M (行)×N(列)个第一发光器件120，第一组像素驱动电路13可以包括P(行)×Q(列)个第一像素驱动电路130。N可以是偶数，也可以是奇数，(M×N)/(P×Q)为整数，例如可以是1、2等。例如，一个第一像素驱动电路130可以驱动一个第一发光器件120发光；又例如，一个第一像素驱动电路130可以驱动两个或更多个第一发光器件120发光。
第二组发光器件14位于第二显示区1102。第二组发光器件14包括多个第二发光器件140。第二发光器件140例如可以包括OLED。
第二组像素驱动电路15位于第二显示区1102，并且包括被配置为驱动多个第二发光器件140的多个第二像素驱动电路150。第二组像素驱动电路15中第二像素驱动电路150的数量大于或等于第二组发光器件14中第二发光器件140的数量。例如，一个第二像素驱动电路150可以驱动一个第二发光器件141发光；又例如，一个第二像素驱动电路150可以驱动两个或更多个第二发光器件140发光。
在垂直于衬底基板11的方向上，第一组像素驱动电路13和第二组像素驱动电路15中的一组像素驱动电路位于第一组像素驱动电路13和第二组像素驱动电路15中的另一组像素驱动电路与衬底基板11之间。换言之，在垂直于衬底基板11的方向上，第一组像素驱动电路13和第二组像素驱动电路15位于不同的空间。在一些实施例中，参见图1B，第一组发光器件12和第二组发光器件14位于第一组像素驱动电路13和第二组像素驱动电路15远离衬底基板111的一侧。
在一些实施例中，参见图1B，第一平坦化层PLN1覆盖第一组像素驱动电路13，第二组像素驱动电路15位于第一平坦化层PLN1远离衬底基板11的一侧，第二平坦化层PLN2覆盖第二组像素驱动电路15，第一组发光器件12和第二组发光器件14位于第二平坦化层PLN2远离衬底基板11的一侧。
上述实施例中，一方面，用于驱动一个或多个第一发光器件120的第一组像素驱动电路13位于第二显示区1102，如此可以增大显示面板与第一显示区1101对应的区域的光透光率。另一方面，在垂直于衬底基板11的方向上，第一组像素驱动电路13和第二组像素驱动电路15位于不同的空间，如此可以在第一显示区1101设置更多数量的第一发光器件120，有利于提高显示面板与第一显示区1101对应的区域的显示分辨率。
可以理解的是，第一组像素驱动电路13中的第一像素驱动电路131和第二组像素驱动电路15中的第二像素驱动电路151可以包括多个薄膜晶体管和电容器。例如，第一像素驱动电路131和第二像素驱动电路151可以包括2个薄膜晶体管和一个电容器(2T1C)、 6个薄膜晶体管和一个电容器(6T1C)、或者7个薄膜晶体管和一个电容器(7T1C)。例如，每个薄膜晶体管的有源层可以包括低温多晶硅(LTPS)或氧化物半导体。
在一些实施例中，第二组像素驱动电路15在衬底基板11上的正投影与第一组像素驱动电路13在衬底基板上的正投影不交叠，如此可以减小第二组像素驱动电路15和第一组像素驱动电路13彼此之间的相互影响，有利于提高显示面板的显示效果。
在一些实施例中，参见图1B，多个第二发光器件150的数量大于多个第一发光器件120的数量，多个第二像素驱动电路130的数量大于第一组像素驱动电路13中第一像素驱动电路131的数量，并且在垂直于衬底基板11的方向上，第一组像素驱动电路13位于第二组像素驱动电路15与衬底基板11之间。即，第一组像素驱动电路13比第二组像素驱动电路15更靠近衬底基板11。这样的结构更有利于第二组像素驱动电路15与第二组发光器件14之间的布线。
图2是示出根据本公开一个实施例的第一组发光器件和第一组像素驱动电路之间的布线示意图。
如图2所示，第一组发光器件12中的多个第一发光器件120包括第一组第一发光器件121和第二组第一发光器件122。第一组像素驱动电路13中的至少一个第一像素驱动电路130包括第一组第一像素驱动电路131和第二组第一像素驱动电路132。第一组第一像素驱动电路131被配置为驱动第一组第一发光器件121，第二组第一像素驱动电路132被配置为驱动第二组第一发光器件122。
如图2所示，显示面板还包括第一组第一信号线16、第一组第二信号线17、第二组第一信号线18和第二组第二信号线19。第一组第一信号线16电连接至第一组第一像素驱动电路131；第一组第二信号线17电连接至第一组第一发光器件121，并且经由第一组过孔V1电连接至第一组第一信号线16；第二组第一信号线18电连接至第二组第一像素驱动电路132；第二组第二信号线19电连接至第二组第一发光器件122，并且经由第二组过孔V2电连接至第二组第一信号线18。
在一些实施例中，第一组第二信号线17和第二组第二信号线19的材料包括透明材料，例如氧化铟锡(ITO)等。这样的方式下，有利于进一步增大显示面板与第一显示区1101对应的区域的光透光率。
在一些实施例中，第一组第一信号线16和第二组第一信号线18的材料包括金属。
图3A-图3C是示出根据本公开一些实施例的图2所示V1、V2和V3处的截面示意 图。
如图3A所示，第一组第二信号线17中的每条第二信号线17经由贯穿绝缘层ILD1的过孔V1电连接至第一组第一信号线16中对应的一条第一信号线16。这里，绝缘层ILD1可以包括一层或多层绝缘层。
如图3B所示，第二组第二信号线19中的每条第二信号线19经由贯穿绝缘层ILD2的过孔V2电连接至第二组第一信号线18中对应的一条第一信号线18。这里，绝缘层ILD2可以包括一层或多层绝缘层。
如图3C所示，第一组第二信号线17中的每条第二信号线17经由贯穿绝缘层ILD3的过孔V3电连接至第一组第一发光器件121中的一个第一发光器件120的阳极AND。绝缘层ILD3例如可以是图1B所示的第二平坦化层120。
在一些实施例中，参见图2，第一组第一信号线16位于第一组第一像素驱动电路131远离第二组第一像素驱动电路132的一侧，第一组第二信号线17位于第一组第一发光器件121远离第二组发光器件122的一侧，第二组第一信号线18位于第二组第一像素驱动电路132远离第一组第一像素驱动电路131的一侧，并且，第二组第二信号线19位于第二组第一发光器件122远离第一组发光器件121的一侧。这样的方式下，第一组第一信号线16和第二组第一信号线18分别位于第一组像素驱动电路13的两侧，第一组第二信号线17和第二组第二信号线19分别位于第一组发光器件12的两侧，有利于减小第一组第一信号线16、第二组第一信号线18、第一组第二信号线17和第二组第二信号线19之间的彼此干扰。
在一些实施例中，参见图2，第一组第一信号线16中的每个第一信号线16包括第一部分161和与第一部分161电连接的第二部分162。第一部分161和第二部分162可以位于同一层，也可以位于不同层。
需要说明的是，在本文中，两个部件位于同一层是指这两个部件是通过对同一材料层进行图案化而形成的，两个部件位于不同层是指这两个部件是通过对不同材料层进行图案化而形成的。
第一部分161沿着第一方向延伸，并且电连接至第一组第一像素驱动电路131中的一个第一像素驱动电路130。第二部分162沿着与第一方向不同的第二方向延伸，并且经由第一组过孔V1中的一个过孔V1电连接至第二组第一信号线17中的一条第一信号线17。例如，第二方向与第一方向垂直。
在一些实施例中，参见图2，第二组第一信号线18中的每个第一信号线18包括第三部分181和与第三部分181电连接的第四部分182。第三部分181和第四部分182可以位于同一层，也可以位于不同层。
第三部分181沿着第一方向延伸，并且电连接至第二组第一像素驱动电路132中的一个第一像素驱动电路130。第四部分182沿着第二方向延伸，并且经由第二组过孔V2中的一个过孔V2电连接至第二组第二信号线19中的一条第二信号线19。
在一些实施例中，参见图2，第一组第二信号线17和第二组第二信号线19沿着第二方向延伸。
图4A是示出根据本公开一个实施例的第一组第二信号线的截面示意图。图4B是示出根据本公开一个实施例的第二组第二信号线的截面示意图。
在一些实施例中，第一组第二信号线17和第二组第二信号线19中的至少一组第二信号线包括位于同层的两个子组第二信号线。
如图4A所示，第一组第二信号线17包括第一子组第二信号线171和与第一子组第二信号线171位于不同层的第二子组第二信号线172。
如图4B所示，第一组第二信号线19包括第一子组第二信号线191和与第一子组第二信号线191位于不同层的第二子组第二信号线192。
例如，参见图4A和图4B，位于不同层的两个子组第二信号线之间可以设置有绝缘层ILD4。
这样的方式下，有利于减小第一组第二信号线17和第二组第二信号线19中的至少一组第二信号线占用的空间，如此，可以在第一显示区1101设置更多数量的第一发光器件120，从而更有利于提高显示面板与第一显示区1101对应的区域的显示分辨率。
图5是示出根据本公开一个实施例的第三信号线和第四信号线的布局示意图。图6是示出根据本公开一个实施例的图5所示V4处的截面示意图。
如图5所示，显示面板还包括多条第三信号线20和多条第四信号线21。多条第三信号线20电连接至第一组像素驱动电路13，多条第四信号线21电连接至图1B所示的第二组像素驱动电路15。多条第三信号线20和多条第四信号线21例如可以沿着第二方向延伸。
多条第四信号线21中的第一组第四信号线211电连接至多条第三信号线20。换言之，多条第四信号线21中的一部分第四信号线211与多条第三信号线20电连接。例如，参 见图6，第一组第四信号线211经由第四组过孔V4电连接至多条第三信号线20。
另外，参见图6，第一组第四信号线211与多条第三信号线20位于不同层。例如，第一组第四信号线211与多条第三信号线20之间设置有绝缘层ILD5。这里，绝缘层ILD5可以包括一层或多层绝缘层。
在一些实施例中，多条第三信号线20和多条第四信号线21可以包括数据线和电源线中的至少一种。例如，数据信号或电源信号可以经由多条第三信号线20和第一组第四信号线211提供至第一组像素驱动电路13和第二组像素驱动电路15中的部分第二像素驱动电路150。
在一些实施例中，多条第三信号线20和多条第四信号线21的材料包括金属。
上述实施例中，第一组第四信号线211与多条第三信号线20位于不同层。这样的方式下，多条第三信号线20无需占用多条第四信号线21的空间，故，可以设置更多数量的第三信号线20，从而更有利于提高显示面板与第一显示区1101对应的区域的显示分辨率。
在一些实施例中，上述第二部分162和第四部分182中的至少一个在衬底基板11上的正投影与多条第四信号线21在衬底基板11上的正投影不交叠。这样的方式下，可以减小第二部分162和第四部分182中的至少一个与第四信号线21之间的相互影响，从而降低串扰，提高显示面板的显示效果。
在一些实施例中，第一组第二信号线17和第二组第二信号线19中的至少一组第二信号线在衬底基板11上的正投影与多条第四信号线21在衬底基板11上的正投影不交叠。这样的方式下，可以减小第一组第二信号线17和第二组第二信号线19中的至少一组第二信号线与第四信号线21之间的相互影响，从而降低串扰，提高显示面板的显示效果。
在一些实施例中，多条第三信号线20包括多条第一种第三信号线(例如数据线)和多条第二种第三信号线(例如电源线)，第一组第四信号线211包括多条第一种第四信号线(例如数据线)和多条第二种第四信号线(例如电源线)。多条第一种第四信号线电连接至多条第一种第三信号线，多条第二种第四信号线电连接至多条第二种第三信号线。
在一些实施例中，针对某一种信号线(例如数据线)来说，相邻的第三信号线20之间的距离可以大于第一组第四信号线211中相邻的第四信号线21之间的距离。例如，多条第一种第三信号线中相邻的第一种第三信号线之间的距离大于多条第一种第四信号线中相邻的第一种第四信号线之间的距离。又例如，多条第二种第三信号线中相邻的第二 种第三信号线之间的距离大于多条第二种第四信号线中相邻的第二种第四信号线之间的距离。
这样的方式下，由于第一组第四信号线211与多条第三信号线20位于不同层，第三信号线20的设计空间可以更大，如此可以减小相邻第三信号线20之间的相互影响。
例如，相邻的第三信号线20之间的距离基本等于相邻的第一像素驱动电路131之间的距离，相邻的第四信号线21之间的距离基本等于相邻的第一发光器件121之间的距离，并且，相邻的第一像素驱动电路131之间的距离大于相邻的第一发光器件121之间的距离。例如，相邻的第三信号线20之间的距离与相邻的第一像素驱动电路131之间的距离的比值为0.8至1.2，例如，1、1.1等；又例如，相邻的第四信号线21之间的距离与相邻的第一发光器件121之间的距离的比值为0.8至1.2，例如，1、1.1等。
在一些实施例中，多条第三信号线20在衬底基板上的正投影与第一显示区1101不交叠，并且，多条第四信号线21在衬底基板上的正投影与第一显示区1101不交叠。这样的方式下，可以进一步增大显示面板与第一显示区1101对应的区域的光透过率。
图7是示出根据本公开一个实施例的第五信号线、第六信号线和第七信号线的布局示意图。
如图7所示，显示面板还包括多条第五信号线22、多条第六信号线23和多条第七信号线24。在一些实施例中，多条第五信号线22、第六信号线23和多条第七信号线24包括栅极线、发光控制线、复位线、初始化线中的至少一种。例如，栅极信号、发光控制信号、复位信号或初始化信号经由多条第五信号线22、多条第六信号线23和多条第七信号线24提供至第一组像素驱动电路13和第二组像素驱动电路15。
多条第五信号线22电连接至第一组像素驱动电路13，并且沿着第一方向延伸。多条第五信号线22在衬底基板11上的正投影与第一组像素驱动电路13在衬底基板11上的正投影交叠。
多条第六信号线23电连接至第二组像素驱动电路15，并且沿着第一方向延伸。多条第六信号线23在衬底基板11上的正投影与第一显示区1101不交叠。例如，在第一方向上，第一显示区1101的两侧分别设置有多条第六信号线23。
多条第七信号线24电连接在多条第五信号线22和多条第六信号线23中的第一组第六信号线231之间，并且沿着与第一方向不同的第二方向延伸。例如，多条第七信号线24经由第五组过孔V5电连接至多条第五信号线22，经由第六组过孔V5电连接至第一 组第六信号线231。
在一些实施例中，多条第五信号线22、多条第六信号线23和多条第七信号线24的材料包括金属。
上述实施例中，多条第六信号线23在衬底基板11上的正投影与第一显示区1101不交叠，可以进一步增大显示面板与第一显示区1101对应的区域的光透过率。
在一些实施例中，上述第一部分161和第三部分181中的至少一个在衬底基板11上的正投影与多条第五信号线22在衬底基板11上的正投影不交叠。这样的方式下，可以减小第一部分161和第三部分181中的至少一个与多条第五信号线22之间的相互影响，从而降低串扰，提高显示面板的显示效果。
在一些实施例中，上述第二部分162和第四部分182中的至少一个在衬底基板11上的正投影与多条第七信号线24在衬底基板11上的正投影不交叠。这样的方式下，可以减小第二部分162和第四部分182中的至少一个与第七信号线24之间的相互影响，从而降低串扰，提高显示面板的显示效果。
图8A和图8B是示出根据本公开一些实现方式的图7所示V5和V6处的截面示意图。
作为一些实现方式，如图8A所示，在垂直于衬底基板11的方向上，多条第七信号线24位于多条第五信号线22与多条第六信号线23之间。多条第七信号线24经由贯穿绝缘层ILD6的第五组过孔V5电连接至多条第五信号线22，并且经由贯穿绝缘层ILD7的第六组过孔V6电连接至多条第六信号线23。
作为另一些实现方式，如图8B所示，在垂直于衬底基板11的方向上，多条第六信号线23位于多条第五信号线22与多条第七信号线24之间。多条第七信号线24经由贯穿绝缘层ILD6和绝缘层ILD7的第五组过孔V5电连接至多条第五信号线22，并且经由贯穿绝缘层ILD7的第六组过孔V6电连接至多条第六信号线23。
在一些实施例中，参见图8A和图8B，多条第七信号线24与多条第五信号线22位于不同层，并且与多条第六信号线23位于不同层。这样的方式有利于减小多条第七信号线24占用的空间。
在一些实施例中，多条第七信号线24中的每条第七信号线24在衬底基板11上的正投影与多条第五信号线22中的至少一条第五信号线22在衬底基板11上的正投影交叠，并且与多条第六信号线23中的至少一条第六信号线23在衬底基板11上的正投影交叠。这样的方式下，第七信号线24可以与第五信号线22和第六信号线23交叠设置，有利于 减小第七信号线24占用的空间。
图9是示出根据本公开一个实施例显示装置的结构示意图。
如图9所示，显示装置可以包括上述任意一个实施例的显示面板10。在一些实施例中，参见图9，显示装置还包括摄像头20，位于第一显示区1101，并且位于衬底基板11远离第一组发光器件120的一侧。
在一些实施例中，显示装置例如可以是移动终端(例如智能手机、平板电脑)、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
图10是示出根据本公开一个实施例的显示面板的制造方法的流程示意图。
在步骤1002，提供衬底基板。这里，衬底基板包括显示区，显示区包括第一显示区和除第一显示区外的第二显示区。
在步骤1004，形成位于第一显示区的第一组发光器件、位于第二显示区的第一组像素驱动电路、位于第二显示区的第二组发光器件和位于第二显示区的第二组像素驱动电路。
第一组发光器件包括多个第一发光器件，第二组发光器件包括多个第二发光器件。第一组像素驱动电路被配置为驱动多个第一发光器件中的至少一个，并且包括至少一个像素驱动电路。第二组像素驱动电路包括被配置为驱动多个第二发光器件的多个第二像素驱动电路。
在垂直于衬底基板的方向上，第一组像素驱动电路和第二组像素驱动电路中的一组像素驱动电路位于第一组像素驱动电路和第二组像素驱动电路中的另一组像素驱动电路与衬底基板之间。
上述实施例中，一方面，用于驱动一个或多个第一发光器件的第一组像素驱动电路位于第二显示区，如此可以增大显示面板与第一显示区对应的区域的光透光率。另一方面，在垂直于衬底基板的方向上，第一组像素驱动电路和第二组像素驱动电路位于不同的空间，如此可以在第一显示区设置更多数量的第一发光器件，有利于提高显示面板与第一显示区对应的区域的显示分辨率。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种显示面板，包括：
    衬底基板，包括显示区，所述显示区包括第一显示区和除所述第一显示区外的第二显示区；
    第一组发光器件，位于所述第一显示区，并且包括多个第一发光器件；
    第一组像素驱动电路，位于所述第二显示区，被配置为驱动所述多个第一发光器件中的至少一个，并且包括至少一个第一像素驱动电路；
    第二组发光器件，位于所述第二显示区，并且包括多个第二发光器件；和
    第二组像素驱动电路，位于所述第二显示区，并且包括被配置为驱动所述多个第二发光器件的多个第二像素驱动电路，
    其中，在垂直于所述衬底基板的方向上，所述第一组像素驱动电路和所述第二组像素驱动电路中的一组像素驱动电路位于所述第一组像素驱动电路和所述第二组像素驱动电路中的另一组像素驱动电路与所述衬底基板之间。
  2. 根据权利要求1所述的显示面板，其中：
    所述多个第一发光器件包括第一组第一发光器件和第二组第一发光器件；
    所述至少一个第一像素驱动电路包括：
    第一组第一像素驱动电路，被配置为驱动所述第一组第一发光器件，和
    第二组第一像素驱动电路，被配置为驱动所述第二组第一发光器件；并且
    所述显示面板还包括：
    第一组第一信号线，电连接至所述第一组第一像素驱动电路，
    第一组第二信号线，电连接至所述第一组第一发光器件，并且经由第一组过孔电连接至所述第一组第一信号线，
    第二组第一信号线，电连接至所述第二组第一像素驱动电路，和
    第二组第二信号线，电连接至所述第二组第一发光器件，并且经由第二组过孔电连接至所述第二组第一信号线。
  3. 根据权利要求2所述的显示面板，其中，所述第一组第二信号线和所述第二组第 二信号线中的至少一组第二信号线包括：
    第一子组第二信号线；和
    第二子组第二信号线，与所述第一子组第二信号线位于不同层。
  4. 根据权利要求2所述的显示面板，其中：
    所述第一组第一信号线位于所述第一组第一像素驱动电路远离所述第二组第一像素驱动电路的一侧；
    所述第一组第二信号线位于所述第一组第一发光器件远离所述第二组发光器件的一侧；
    所述第二组第一信号线位于所述第二组第一像素驱动电路远离所述第一组第一像素驱动电路的一侧；并且
    所述第二组第二信号线位于所述第二组第一发光器件远离所述第一组发光器件的一侧。
  5. 根据权利要求2所述的显示面板，其中，所述第一组第一信号线中的每个第一信号线包括：
    第一部分，沿着第一方向延伸，并且电连接至所述第一组第一像素驱动电路中的一个第一像素驱动电路；和
    与所述第一部分电连接的第二部分，沿着与所述第一方向不同的第二方向延伸，并且经由所述第一组过孔中的一个过孔电连接至所述第一组第二信号线中的一条第二信号线。
  6. 根据权利要求5所述的显示面板，其中，所述第二组第一信号线中的每个第一信号线包括：
    第三部分，沿着所述第一方向延伸，并且电连接至所述第二组第一像素驱动电路中的一个第一像素驱动电路；和
    与所述第三部分电连接的第四部分，沿着所述第二方向延伸，并且经由所述第二组过孔中的一个过孔电连接至所述第二组第二信号线中的一条第二信号线。
  7. 根据权利要求5所述的显示面板，其中，所述第一组第二信号线和所述第二组第二信号线沿着所述第二方向延伸。
  8. 根据权利要求1-7任意一项所述的显示面板，还包括：
    多条第三信号线，电连接至所述第一组像素驱动电路；和
    多条第四信号线，电连接至所述第二组像素驱动电路，所述多条第四信号线中的第一组第四信号线电连接至所述多条第三信号线，并且与所述多条第三信号线位于不同层。
  9. 根据权利要求8所述的显示面板，其中：
    所述多条第三信号线在所述衬底基板上的正投影与所述第一显示区不交叠；并且
    所述多条第四信号线在所述衬底基板上的正投影与所述第一显示区不交叠。
  10. 根据权利要求8所述的显示面板，其中：
    所述多条第三信号线包括多条第一种第三信号线和多条第二种第三信号线；并且
    所述第一组第四信号线包括多条第一种第四信号线和多条第二种第四信号线，所述多条第一种第四信号线电连接至所述多条第一种第三信号线，所述多条第二种第四信号线电连接至所述多条第二种第三信号线。
  11. 根据权利要求10所述的显示面板，其中：
    所述多条第一种第三信号线中相邻的第一种第三信号线之间的距离大于所述多条第一种第四信号线中相邻的第一种第四信号线之间的距离；并且
    所述多条第二种第三信号线中相邻的第二种第三信号线之间的距离大于所述多条第二种第四信号线中相邻的第二种第四信号线之间的距离。
  12. 根据权利要求1-11任意一项所述的显示面板，还包括：
    多条第五信号线，电连接至所述第一组像素驱动电路，并且沿着第一方向延伸，所述多条第五信号线在所述衬底基板上的正投影与所述第一组像素驱动电路在所述衬底基板上的正投影交叠；
    多条第六信号线，电连接至所述第二组像素驱动电路，并且沿着所示第一方向延伸， 所述多条第六信号线在所述衬底基板上的正投影与所述第一显示区不交叠；和
    多条第七信号线，电连接在所述多条第五信号线和所述多条第六信号线中的第一组第六信号线之间，并且沿着与所述第一方向不同的第二方向延伸。
  13. 根据权利要求12所述的显示面板，其中，所述多条第七信号线与所述多条第五信号线位于不同层，并且与所述多条第六信号线位于不同层。
  14. 根据权利要求13所述的显示面板，其中，所述多条第七信号线中的每条第七信号线在所述衬底基板上的正投影与所述多条第五信号线中的至少一条第五信号线在所述衬底基板上的正投影交叠，并且与所述多条第六信号线中的至少一条第六信号线在所述衬底基板上的正投影交叠。
  15. 根据权利要求12所述的显示面板，其中，所述多条第五信号线、所述第六信号线和所述多条第七信号线包括栅极线、发光控制线、复位线、初始化线中的至少一种。
  16. 根据权利要求1所述的显示面板，其中，所述第二组像素驱动电路在所述衬底基板上的正投影与所述第一组像素驱动电路在所述衬底基板上的正投影不交叠。
  17. 根据权利要求1所述的显示面板，其中，
    所述多个第二发光器件的数量大于所述多个第一发光器件的数量；
    所述多个第二像素驱动电路的数量大于所述至少一个第一像素驱动电路的数量；并且
    在垂直于所述衬底基板的方向上，所述第一组像素驱动电路位于所述第二组像素驱动电路与所述衬底基板之间。
  18. 一种显示装置，包括：如权利要求1-17任意一项所述的显示面板。
  19. 根据权利要求18的显示装置，还包括：
    摄像头，位于所述衬底基板远离所述第一组发光器件的一侧，并且位于所述第一显 示区。
  20. 一种显示面板的制造方法，包括：
    提供衬底基板，所述衬底基板包括显示区，所述显示区包括第一显示区和除所述第一显示区外的第二显示区；和
    形成位于所述第一显示区的第一组发光器件、位于所述第二显示区的第一组像素驱动电路、位于所述第二显示区的第二组发光器件和位于所述第二显示区的第二组像素驱动电路，其中：
    所述第一组发光器件包括多个第一发光器件，
    所述第一组像素驱动电路被配置为驱动所述多个第一发光器件中的至少一个，并且包括至少一个像素驱动电路，
    所述第二组发光器件包括多个第二发光器件，
    所述第二组像素驱动电路包括被配置为驱动所述多个第二发光器件的多个第二像素驱动电路，并且
    在垂直于所述衬底基板的方向上，所述第一组像素驱动电路和所述第二组像素驱动电路中的一组像素驱动电路位于所述第一组像素驱动电路和所述第二组像素驱动电路中的另一组像素驱动电路与所述衬底基板之间。
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